annotate src/hotspot/cpu/arm/vm_version_arm_32.cpp @ 47946:b7c7428eaab9

8189610: Reconcile jvm.h and all jvm_md.h between java.base and hotspot Summary: Removed hotspot version of jvm*h and jni*h files. Reviewed-by: ihse, mchung, dholmes
author coleenp
date Tue, 31 Oct 2017 11:55:09 -0400
parents 71c04702a3d5
children 3300874b963c
rev   line source
bobv@42664 1 /*
kbarrett@46560 2 * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
bobv@42664 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
bobv@42664 4 *
bobv@42664 5 * This code is free software; you can redistribute it and/or modify it
bobv@42664 6 * under the terms of the GNU General Public License version 2 only, as
bobv@42664 7 * published by the Free Software Foundation.
bobv@42664 8 *
bobv@42664 9 * This code is distributed in the hope that it will be useful, but WITHOUT
bobv@42664 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
bobv@42664 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
bobv@42664 12 * version 2 for more details (a copy is included in the LICENSE file that
bobv@42664 13 * accompanied this code).
bobv@42664 14 *
bobv@42664 15 * You should have received a copy of the GNU General Public License version
bobv@42664 16 * 2 along with this work; if not, write to the Free Software Foundation,
bobv@42664 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
bobv@42664 18 *
bobv@42664 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
bobv@42664 20 * or visit www.oracle.com if you need additional information or have any
bobv@42664 21 * questions.
bobv@42664 22 *
bobv@42664 23 */
bobv@42664 24
bobv@42664 25 #include "precompiled.hpp"
coleenp@47946 26 #include "jvm.h"
bobv@42664 27 #include "asm/macroAssembler.inline.hpp"
bobv@42664 28 #include "memory/resourceArea.hpp"
bobv@42664 29 #include "runtime/java.hpp"
bobv@42664 30 #include "runtime/os.inline.hpp"
bobv@42664 31 #include "runtime/stubCodeGenerator.hpp"
bobv@42664 32 #include "vm_version_arm.hpp"
bobv@42664 33
bobv@42664 34 int VM_Version::_stored_pc_adjustment = 4;
bobv@42664 35 int VM_Version::_arm_arch = 5;
bobv@42664 36 bool VM_Version::_is_initialized = false;
bobv@42664 37 int VM_Version::_kuser_helper_version = 0;
bobv@42664 38
bobv@42664 39 extern "C" {
bobv@42664 40 typedef int (*get_cpu_info_t)();
bobv@42664 41 typedef bool (*check_vfp_t)(double *d);
bobv@42664 42 typedef bool (*check_simd_t)();
bobv@42664 43 }
bobv@42664 44
bobv@42664 45 #define __ _masm->
bobv@42664 46
bobv@42664 47 class VM_Version_StubGenerator: public StubCodeGenerator {
bobv@42664 48 public:
bobv@42664 49
bobv@42664 50 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
bobv@42664 51
bobv@42664 52 address generate_get_cpu_info() {
bobv@42664 53 StubCodeMark mark(this, "VM_Version", "get_cpu_info");
bobv@42664 54 address start = __ pc();
bobv@42664 55
bobv@42664 56 __ mov(R0, PC);
bobv@42664 57 __ push(PC);
bobv@42664 58 __ pop(R1);
bobv@42664 59 __ sub(R0, R1, R0);
bobv@42664 60 // return the result in R0
bobv@42664 61 __ bx(LR);
bobv@42664 62
bobv@42664 63 return start;
bobv@42664 64 };
bobv@42664 65
bobv@42664 66 address generate_check_vfp() {
bobv@42664 67 StubCodeMark mark(this, "VM_Version", "check_vfp");
bobv@42664 68 address start = __ pc();
bobv@42664 69
bobv@42664 70 __ fstd(D0, Address(R0));
bobv@42664 71 __ mov(R0, 1);
bobv@42664 72 __ bx(LR);
bobv@42664 73
bobv@42664 74 return start;
bobv@42664 75 };
bobv@42664 76
bobv@42664 77 address generate_check_vfp3_32() {
bobv@42664 78 StubCodeMark mark(this, "VM_Version", "check_vfp3_32");
bobv@42664 79 address start = __ pc();
bobv@42664 80
bobv@42664 81 __ fstd(D16, Address(R0));
bobv@42664 82 __ mov(R0, 1);
bobv@42664 83 __ bx(LR);
bobv@42664 84
bobv@42664 85 return start;
bobv@42664 86 };
bobv@42664 87
bobv@42664 88 address generate_check_simd() {
bobv@42664 89 StubCodeMark mark(this, "VM_Version", "check_simd");
bobv@42664 90 address start = __ pc();
bobv@42664 91
bobv@42664 92 __ vcnt(Stemp, Stemp);
bobv@42664 93 __ mov(R0, 1);
bobv@42664 94 __ bx(LR);
bobv@42664 95
bobv@42664 96 return start;
bobv@42664 97 };
bobv@42664 98 };
bobv@42664 99
bobv@42664 100 #undef __
bobv@42664 101
bobv@42664 102
bobv@42664 103 extern "C" address check_vfp3_32_fault_instr;
bobv@42664 104 extern "C" address check_vfp_fault_instr;
bobv@42664 105 extern "C" address check_simd_fault_instr;
bobv@42664 106
bobv@42664 107 void VM_Version::initialize() {
bobv@42664 108 ResourceMark rm;
bobv@42664 109
bobv@42664 110 // Making this stub must be FIRST use of assembler
bobv@42664 111 const int stub_size = 128;
bobv@42664 112 BufferBlob* stub_blob = BufferBlob::create("get_cpu_info", stub_size);
bobv@42664 113 if (stub_blob == NULL) {
bobv@42664 114 vm_exit_during_initialization("Unable to allocate get_cpu_info stub");
bobv@42664 115 }
bobv@42664 116
bobv@42664 117 CodeBuffer c(stub_blob);
bobv@42664 118 VM_Version_StubGenerator g(&c);
bobv@42664 119 address get_cpu_info_pc = g.generate_get_cpu_info();
bobv@42664 120 get_cpu_info_t get_cpu_info = CAST_TO_FN_PTR(get_cpu_info_t, get_cpu_info_pc);
bobv@42664 121
bobv@42664 122 int pc_adjustment = get_cpu_info();
bobv@42664 123
bobv@42664 124 VM_Version::_stored_pc_adjustment = pc_adjustment;
bobv@42664 125
bobv@42664 126 #ifndef __SOFTFP__
bobv@42664 127 address check_vfp_pc = g.generate_check_vfp();
bobv@42664 128 check_vfp_t check_vfp = CAST_TO_FN_PTR(check_vfp_t, check_vfp_pc);
bobv@42664 129
bobv@42664 130 check_vfp_fault_instr = (address)check_vfp;
bobv@42664 131 double dummy;
bobv@42664 132 if (check_vfp(&dummy)) {
bobv@42664 133 _features |= vfp_m;
bobv@42664 134 }
bobv@42664 135
bobv@42664 136 #ifdef COMPILER2
bobv@42664 137 if (has_vfp()) {
bobv@42664 138 address check_vfp3_32_pc = g.generate_check_vfp3_32();
bobv@42664 139 check_vfp_t check_vfp3_32 = CAST_TO_FN_PTR(check_vfp_t, check_vfp3_32_pc);
bobv@42664 140 check_vfp3_32_fault_instr = (address)check_vfp3_32;
bobv@42664 141 double dummy;
bobv@42664 142 if (check_vfp3_32(&dummy)) {
bobv@42664 143 _features |= vfp3_32_m;
bobv@42664 144 }
bobv@42664 145
bobv@42664 146 address check_simd_pc =g.generate_check_simd();
bobv@42664 147 check_simd_t check_simd = CAST_TO_FN_PTR(check_simd_t, check_simd_pc);
bobv@42664 148 check_simd_fault_instr = (address)check_simd;
bobv@42664 149 if (check_simd()) {
bobv@42664 150 _features |= simd_m;
bobv@42664 151 }
bobv@42664 152 }
bobv@42664 153 #endif
bobv@42664 154 #endif
bobv@42664 155
bobv@42664 156
bobv@42664 157 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
bobv@42664 158 warning("AES intrinsics are not available on this CPU");
bobv@42664 159 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
bobv@42664 160 }
bobv@42664 161
bobv@42664 162 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
bobv@42664 163 warning("AES instructions are not available on this CPU");
bobv@42664 164 FLAG_SET_DEFAULT(UseAES, false);
bobv@42664 165 }
bobv@42664 166
bobv@42664 167 if (UseAESCTRIntrinsics) {
bobv@42664 168 warning("AES/CTR intrinsics are not available on this CPU");
bobv@42664 169 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
bobv@42664 170 }
bobv@42664 171
bobv@42664 172 if (UseFMA) {
bobv@42664 173 warning("FMA instructions are not available on this CPU");
bobv@42664 174 FLAG_SET_DEFAULT(UseFMA, false);
bobv@42664 175 }
bobv@42664 176
bobv@42664 177 if (UseSHA) {
bobv@42664 178 warning("SHA instructions are not available on this CPU");
bobv@42664 179 FLAG_SET_DEFAULT(UseSHA, false);
bobv@42664 180 }
bobv@42664 181
bobv@42664 182 if (UseSHA1Intrinsics) {
bobv@42664 183 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
bobv@42664 184 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
bobv@42664 185 }
bobv@42664 186
bobv@42664 187 if (UseSHA256Intrinsics) {
bobv@42664 188 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
bobv@42664 189 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
bobv@42664 190 }
bobv@42664 191
bobv@42664 192 if (UseSHA512Intrinsics) {
bobv@42664 193 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
bobv@42664 194 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
bobv@42664 195 }
bobv@42664 196
bobv@42664 197 if (UseCRC32Intrinsics) {
bobv@42664 198 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
bobv@42664 199 warning("CRC32 intrinsics are not available on this CPU");
bobv@42664 200 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
bobv@42664 201 }
bobv@42664 202
bobv@42664 203 if (UseCRC32CIntrinsics) {
bobv@42664 204 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
bobv@42664 205 warning("CRC32C intrinsics are not available on this CPU");
bobv@42664 206 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
bobv@42664 207 }
bobv@42664 208
bobv@42664 209 if (UseAdler32Intrinsics) {
bobv@42664 210 warning("Adler32 intrinsics are not available on this CPU");
bobv@42664 211 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
bobv@42664 212 }
bobv@42664 213
bobv@42664 214 if (UseVectorizedMismatchIntrinsic) {
bobv@42664 215 warning("vectorizedMismatch intrinsic is not available on this CPU.");
bobv@42664 216 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
bobv@42664 217 }
bobv@42664 218
bobv@42664 219 get_os_cpu_info();
bobv@42664 220
bobv@42664 221 _kuser_helper_version = *(int*)KUSER_HELPER_VERSION_ADDR;
bobv@42664 222
bobv@42664 223 #ifdef COMPILER2
bobv@42664 224 // C2 is only supported on v7+ VFP at this time
bobv@42664 225 if (_arm_arch < 7 || !has_vfp()) {
bobv@42664 226 vm_exit_during_initialization("Server VM is only supported on ARMv7+ VFP");
bobv@42664 227 }
bobv@42664 228 #endif
bobv@42664 229
bobv@42664 230 // armv7 has the ldrexd instruction that can be used to implement cx8
bobv@42664 231 // armv5 with linux >= 3.1 can use kernel helper routine
bobv@42664 232 _supports_cx8 = (supports_ldrexd() || supports_kuser_cmpxchg64());
bobv@42664 233 // ARM doesn't have special instructions for these but ldrex/ldrexd
bobv@42664 234 // enable shorter instruction sequences that the ones based on cas.
bobv@42664 235 _supports_atomic_getset4 = supports_ldrex();
bobv@42664 236 _supports_atomic_getadd4 = supports_ldrex();
bobv@42664 237 _supports_atomic_getset8 = supports_ldrexd();
bobv@42664 238 _supports_atomic_getadd8 = supports_ldrexd();
bobv@42664 239
bobv@42664 240 #ifdef COMPILER2
bobv@42664 241 assert(_supports_cx8 && _supports_atomic_getset4 && _supports_atomic_getadd4
bobv@42664 242 && _supports_atomic_getset8 && _supports_atomic_getadd8, "C2: atomic operations must be supported");
bobv@42664 243 #endif
bobv@42664 244 char buf[512];
bobv@42664 245 jio_snprintf(buf, sizeof(buf), "(ARMv%d)%s%s%s",
bobv@42664 246 _arm_arch,
bobv@42664 247 (has_vfp() ? ", vfp" : ""),
bobv@42664 248 (has_vfp3_32() ? ", vfp3-32" : ""),
bobv@42664 249 (has_simd() ? ", simd" : ""));
bobv@42664 250
bobv@42664 251 // buf is started with ", " or is empty
bobv@42664 252 _features_string = os::strdup(buf);
bobv@42664 253
bobv@42664 254 if (has_simd()) {
bobv@42664 255 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
bobv@42664 256 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
bobv@42664 257 }
bobv@42664 258 }
bobv@42664 259
rraghavan@46547 260 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
rraghavan@46547 261 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 128);
rraghavan@46547 262 }
bobv@42664 263
bobv@42664 264 #ifdef COMPILER2
bobv@42664 265 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
bobv@42664 266
bobv@42664 267 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
bobv@42664 268 // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
bobv@42664 269 // SIMD/NEON can use 16, but default is 8 because currently
bobv@42664 270 // larger than 8 will disable instruction scheduling
bobv@42664 271 FLAG_SET_DEFAULT(MaxVectorSize, 8);
bobv@42664 272 }
bobv@42664 273
bobv@42664 274 if (MaxVectorSize > 16) {
bobv@42664 275 FLAG_SET_DEFAULT(MaxVectorSize, 8);
bobv@42664 276 }
bobv@42664 277 #endif
bobv@42664 278
bobv@42664 279 if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
bobv@42664 280 Tier4CompileThreshold = 10000;
bobv@42664 281 }
bobv@42664 282 if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {
bobv@42664 283 Tier3InvocationThreshold = 1000;
bobv@42664 284 }
bobv@42664 285 if (FLAG_IS_DEFAULT(Tier3CompileThreshold)) {
bobv@42664 286 Tier3CompileThreshold = 5000;
bobv@42664 287 }
bobv@42664 288 if (FLAG_IS_DEFAULT(Tier3MinInvocationThreshold)) {
bobv@42664 289 Tier3MinInvocationThreshold = 500;
bobv@42664 290 }
bobv@42664 291
bobv@42664 292 FLAG_SET_DEFAULT(TypeProfileLevel, 0); // unsupported
bobv@42664 293
bobv@42664 294 // This machine does not allow unaligned memory accesses
bobv@42664 295 if (UseUnalignedAccesses) {
bobv@42664 296 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
bobv@42664 297 warning("Unaligned memory access is not available on this CPU");
bobv@42664 298 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
bobv@42664 299 }
bobv@42664 300
bobv@42664 301 _is_initialized = true;
bobv@42664 302 }
bobv@42664 303
bobv@42664 304 bool VM_Version::use_biased_locking() {
bobv@42664 305 get_os_cpu_info();
bobv@42664 306 // The cost of CAS on uniprocessor ARM v6 and later is low compared to the
bobv@42664 307 // overhead related to slightly longer Biased Locking execution path.
bobv@42664 308 // Testing shows no improvement when running with Biased Locking enabled
bobv@42664 309 // on an ARMv6 and higher uniprocessor systems. The situation is different on
bobv@42664 310 // ARMv5 and MP systems.
bobv@42664 311 //
bobv@42664 312 // Therefore the Biased Locking is enabled on ARMv5 and ARM MP only.
bobv@42664 313 //
bobv@42664 314 return (!os::is_MP() && (arm_arch() > 5)) ? false : true;
bobv@42664 315 }
bobv@42664 316
bobv@42664 317 #define EXP
bobv@42664 318
bobv@42664 319 // Temporary override for experimental features
bobv@42664 320 // Copied from Abstract_VM_Version
bobv@42664 321 const char* VM_Version::vm_info_string() {
bobv@42664 322 switch (Arguments::mode()) {
bobv@42664 323 case Arguments::_int:
bobv@42664 324 return UseSharedSpaces ? "interpreted mode, sharing" EXP : "interpreted mode" EXP;
bobv@42664 325 case Arguments::_mixed:
bobv@42664 326 return UseSharedSpaces ? "mixed mode, sharing" EXP : "mixed mode" EXP;
bobv@42664 327 case Arguments::_comp:
bobv@42664 328 return UseSharedSpaces ? "compiled mode, sharing" EXP : "compiled mode" EXP;
bobv@42664 329 };
bobv@42664 330 ShouldNotReachHere();
bobv@42664 331 return "";
bobv@42664 332 }