annotate hotspot/src/cpu/x86/vm/macroAssembler_x86.hpp @ 37293:c010188d360f

8151003: Remove nds->is_valid() checks from assembler_x86.cpp Reviewed-by: kvn
author mcberg
date Tue, 05 Apr 2016 11:37:41 -0700
parents b18243f4d955
children 1dc6c6f21231
rev   line source
twisti@14626 1 /*
mikael@36561 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
twisti@14626 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@14626 4 *
twisti@14626 5 * This code is free software; you can redistribute it and/or modify it
twisti@14626 6 * under the terms of the GNU General Public License version 2 only, as
twisti@14626 7 * published by the Free Software Foundation.
twisti@14626 8 *
twisti@14626 9 * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@14626 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@14626 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
twisti@14626 12 * version 2 for more details (a copy is included in the LICENSE file that
twisti@14626 13 * accompanied this code).
twisti@14626 14 *
twisti@14626 15 * You should have received a copy of the GNU General Public License version
twisti@14626 16 * 2 along with this work; if not, write to the Free Software Foundation,
twisti@14626 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@14626 18 *
twisti@14626 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
twisti@14626 20 * or visit www.oracle.com if you need additional information or have any
twisti@14626 21 * questions.
twisti@14626 22 *
twisti@14626 23 */
twisti@14626 24
twisti@14626 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 27
twisti@14626 28 #include "asm/assembler.hpp"
jprovino@15482 29 #include "utilities/macros.hpp"
kvn@23491 30 #include "runtime/rtmLocking.hpp"
twisti@14626 31
twisti@14626 32 // MacroAssembler extends Assembler by frequently used macros.
twisti@14626 33 //
twisti@14626 34 // Instructions for which a 'better' code sequence exists depending
twisti@14626 35 // on arguments should also go in here.
twisti@14626 36
twisti@14626 37 class MacroAssembler: public Assembler {
twisti@14626 38 friend class LIR_Assembler;
twisti@14626 39 friend class Runtime1; // as_Address()
twisti@14626 40
twisti@14626 41 protected:
twisti@14626 42
twisti@14626 43 Address as_Address(AddressLiteral adr);
twisti@14626 44 Address as_Address(ArrayAddress adr);
twisti@14626 45
twisti@14626 46 // Support for VM calls
twisti@14626 47 //
twisti@14626 48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
twisti@14626 49 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 50 // additional registers when doing a VM call).
iveresov@33465 51
coleenp@35214 52 virtual void call_VM_leaf_base(
twisti@14626 53 address entry_point, // the entry point
twisti@14626 54 int number_of_arguments // the number of arguments to pop after the call
twisti@14626 55 );
twisti@14626 56
twisti@14626 57 // This is the base routine called by the different versions of call_VM. The interpreter
twisti@14626 58 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 59 // additional registers when doing a VM call).
twisti@14626 60 //
twisti@14626 61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
twisti@14626 62 // returns the register which contains the thread upon return. If a thread register has been
twisti@14626 63 // specified, the return value will correspond to that register. If no last_java_sp is specified
twisti@14626 64 // (noreg) than rsp will be used instead.
coleenp@35214 65 virtual void call_VM_base( // returns the register containing the thread upon return
twisti@14626 66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
twisti@14626 67 Register java_thread, // the thread if computed before ; use noreg otherwise
twisti@14626 68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
twisti@14626 69 address entry_point, // the entry point
twisti@14626 70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
twisti@14626 71 bool check_exceptions // whether to check for pending exceptions after return
twisti@14626 72 );
twisti@14626 73
twisti@14626 74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
twisti@14626 75 // The implementation is only non-empty for the InterpreterMacroAssembler,
twisti@14626 76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
twisti@14626 77 virtual void check_and_handle_popframe(Register java_thread);
twisti@14626 78 virtual void check_and_handle_earlyret(Register java_thread);
twisti@14626 79
twisti@14626 80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
twisti@14626 81
twisti@14626 82 // helpers for FPU flag access
twisti@14626 83 // tmp is a temporary register, if none is available use noreg
twisti@14626 84 void save_rax (Register tmp);
twisti@14626 85 void restore_rax(Register tmp);
twisti@14626 86
twisti@14626 87 public:
twisti@14626 88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
twisti@14626 89
twisti@14626 90 // Support for NULL-checks
twisti@14626 91 //
twisti@14626 92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
twisti@14626 93 // If the accessed location is M[reg + offset] and the offset is known, provide the
twisti@14626 94 // offset. No explicit code generation is needed if the offset is within a certain
twisti@14626 95 // range (0 <= offset <= page_size).
twisti@14626 96
twisti@14626 97 void null_check(Register reg, int offset = -1);
twisti@14626 98 static bool needs_explicit_null_check(intptr_t offset);
twisti@14626 99
twisti@14626 100 // Required platform-specific helpers for Label::patch_instructions.
twisti@14626 101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
twisti@14626 102 void pd_patch_instruction(address branch, address target) {
twisti@14626 103 unsigned char op = branch[0];
twisti@14626 104 assert(op == 0xE8 /* call */ ||
twisti@14626 105 op == 0xE9 /* jmp */ ||
twisti@14626 106 op == 0xEB /* short jmp */ ||
twisti@14626 107 (op & 0xF0) == 0x70 /* short jcc */ ||
kvn@23491 108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
kvn@23491 109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
twisti@14626 110 "Invalid opcode at patch point");
twisti@14626 111
twisti@14626 112 if (op == 0xEB || (op & 0xF0) == 0x70) {
twisti@14626 113 // short offset operators (jmp and jcc)
twisti@14626 114 char* disp = (char*) &branch[1];
twisti@14626 115 int imm8 = target - (address) &disp[1];
twisti@14626 116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
twisti@14626 117 *disp = imm8;
twisti@14626 118 } else {
kvn@23491 119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
twisti@14626 120 int imm32 = target - (address) &disp[1];
twisti@14626 121 *disp = imm32;
twisti@14626 122 }
twisti@14626 123 }
twisti@14626 124
twisti@14626 125 // The following 4 methods return the offset of the appropriate move instruction
twisti@14626 126
twisti@14626 127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
twisti@14626 128 int load_unsigned_byte(Register dst, Address src);
twisti@14626 129 int load_unsigned_short(Register dst, Address src);
twisti@14626 130
twisti@14626 131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
twisti@14626 132 int load_signed_byte(Register dst, Address src);
twisti@14626 133 int load_signed_short(Register dst, Address src);
twisti@14626 134
twisti@14626 135 // Support for sign-extension (hi:lo = extend_sign(lo))
twisti@14626 136 void extend_sign(Register hi, Register lo);
twisti@14626 137
twisti@14626 138 // Load and store values by size and signed-ness
twisti@14626 139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
twisti@14626 140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
twisti@14626 141
twisti@14626 142 // Support for inc/dec with optimal instruction selection depending on value
twisti@14626 143
twisti@14626 144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
twisti@14626 145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
twisti@14626 146
twisti@14626 147 void decrementl(Address dst, int value = 1);
twisti@14626 148 void decrementl(Register reg, int value = 1);
twisti@14626 149
twisti@14626 150 void decrementq(Register reg, int value = 1);
twisti@14626 151 void decrementq(Address dst, int value = 1);
twisti@14626 152
twisti@14626 153 void incrementl(Address dst, int value = 1);
twisti@14626 154 void incrementl(Register reg, int value = 1);
twisti@14626 155
twisti@14626 156 void incrementq(Register reg, int value = 1);
twisti@14626 157 void incrementq(Address dst, int value = 1);
twisti@14626 158
twisti@14626 159 // Support optimal SSE move instructions.
twisti@14626 160 void movflt(XMMRegister dst, XMMRegister src) {
twisti@14626 161 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
twisti@14626 162 else { movss (dst, src); return; }
twisti@14626 163 }
twisti@14626 164 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
twisti@14626 165 void movflt(XMMRegister dst, AddressLiteral src);
twisti@14626 166 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
twisti@14626 167
twisti@14626 168 void movdbl(XMMRegister dst, XMMRegister src) {
twisti@14626 169 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
twisti@14626 170 else { movsd (dst, src); return; }
twisti@14626 171 }
twisti@14626 172
twisti@14626 173 void movdbl(XMMRegister dst, AddressLiteral src);
twisti@14626 174
twisti@14626 175 void movdbl(XMMRegister dst, Address src) {
twisti@14626 176 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
twisti@14626 177 else { movlpd(dst, src); return; }
twisti@14626 178 }
twisti@14626 179 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
twisti@14626 180
twisti@14626 181 void incrementl(AddressLiteral dst);
twisti@14626 182 void incrementl(ArrayAddress dst);
twisti@14626 183
kvn@23491 184 void incrementq(AddressLiteral dst);
kvn@23491 185
twisti@14626 186 // Alignment
twisti@14626 187 void align(int modulus);
shade@32203 188 void align(int modulus, int target);
twisti@14626 189
twisti@14626 190 // A 5 byte nop that is safe for patching (see patch_verified_entry)
twisti@14626 191 void fat_nop();
twisti@14626 192
twisti@14626 193 // Stack frame creation/removal
twisti@14626 194 void enter();
twisti@14626 195 void leave();
twisti@14626 196
twisti@14626 197 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
twisti@14626 198 // The pointer will be loaded into the thread register.
twisti@14626 199 void get_thread(Register thread);
twisti@14626 200
twisti@14626 201
twisti@14626 202 // Support for VM calls
twisti@14626 203 //
twisti@14626 204 // It is imperative that all calls into the VM are handled via the call_VM macros.
twisti@14626 205 // They make sure that the stack linkage is setup correctly. call_VM's correspond
twisti@14626 206 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
twisti@14626 207
twisti@14626 208
twisti@14626 209 void call_VM(Register oop_result,
twisti@14626 210 address entry_point,
twisti@14626 211 bool check_exceptions = true);
twisti@14626 212 void call_VM(Register oop_result,
twisti@14626 213 address entry_point,
twisti@14626 214 Register arg_1,
twisti@14626 215 bool check_exceptions = true);
twisti@14626 216 void call_VM(Register oop_result,
twisti@14626 217 address entry_point,
twisti@14626 218 Register arg_1, Register arg_2,
twisti@14626 219 bool check_exceptions = true);
twisti@14626 220 void call_VM(Register oop_result,
twisti@14626 221 address entry_point,
twisti@14626 222 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 223 bool check_exceptions = true);
twisti@14626 224
twisti@14626 225 // Overloadings with last_Java_sp
twisti@14626 226 void call_VM(Register oop_result,
twisti@14626 227 Register last_java_sp,
twisti@14626 228 address entry_point,
twisti@14626 229 int number_of_arguments = 0,
twisti@14626 230 bool check_exceptions = true);
twisti@14626 231 void call_VM(Register oop_result,
twisti@14626 232 Register last_java_sp,
twisti@14626 233 address entry_point,
twisti@14626 234 Register arg_1, bool
twisti@14626 235 check_exceptions = true);
twisti@14626 236 void call_VM(Register oop_result,
twisti@14626 237 Register last_java_sp,
twisti@14626 238 address entry_point,
twisti@14626 239 Register arg_1, Register arg_2,
twisti@14626 240 bool check_exceptions = true);
twisti@14626 241 void call_VM(Register oop_result,
twisti@14626 242 Register last_java_sp,
twisti@14626 243 address entry_point,
twisti@14626 244 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 245 bool check_exceptions = true);
twisti@14626 246
twisti@14626 247 void get_vm_result (Register oop_result, Register thread);
twisti@14626 248 void get_vm_result_2(Register metadata_result, Register thread);
twisti@14626 249
twisti@14626 250 // These always tightly bind to MacroAssembler::call_VM_base
twisti@14626 251 // bypassing the virtual implementation
twisti@14626 252 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
twisti@14626 253 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
twisti@14626 254 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
twisti@14626 255 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
twisti@14626 256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
twisti@14626 257
twisti@14626 258 void call_VM_leaf(address entry_point,
twisti@14626 259 int number_of_arguments = 0);
twisti@14626 260 void call_VM_leaf(address entry_point,
twisti@14626 261 Register arg_1);
twisti@14626 262 void call_VM_leaf(address entry_point,
twisti@14626 263 Register arg_1, Register arg_2);
twisti@14626 264 void call_VM_leaf(address entry_point,
twisti@14626 265 Register arg_1, Register arg_2, Register arg_3);
twisti@14626 266
twisti@14626 267 // These always tightly bind to MacroAssembler::call_VM_leaf_base
twisti@14626 268 // bypassing the virtual implementation
twisti@14626 269 void super_call_VM_leaf(address entry_point);
twisti@14626 270 void super_call_VM_leaf(address entry_point, Register arg_1);
twisti@14626 271 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
twisti@14626 272 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
twisti@14626 273 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
twisti@14626 274
twisti@14626 275 // last Java Frame (fills frame anchor)
twisti@14626 276 void set_last_Java_frame(Register thread,
twisti@14626 277 Register last_java_sp,
twisti@14626 278 Register last_java_fp,
twisti@14626 279 address last_java_pc);
twisti@14626 280
twisti@14626 281 // thread in the default location (r15_thread on 64bit)
twisti@14626 282 void set_last_Java_frame(Register last_java_sp,
twisti@14626 283 Register last_java_fp,
twisti@14626 284 address last_java_pc);
twisti@14626 285
twisti@14626 286 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
twisti@14626 287
twisti@14626 288 // thread in the default location (r15_thread on 64bit)
twisti@14626 289 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
twisti@14626 290
twisti@14626 291 // Stores
twisti@14626 292 void store_check(Register obj); // store check for obj - register is destroyed afterwards
twisti@14626 293 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
twisti@14626 294
jprovino@15482 295 #if INCLUDE_ALL_GCS
twisti@14626 296
twisti@14626 297 void g1_write_barrier_pre(Register obj,
twisti@14626 298 Register pre_val,
twisti@14626 299 Register thread,
twisti@14626 300 Register tmp,
twisti@14626 301 bool tosca_live,
twisti@14626 302 bool expand_call);
twisti@14626 303
twisti@14626 304 void g1_write_barrier_post(Register store_addr,
twisti@14626 305 Register new_val,
twisti@14626 306 Register thread,
twisti@14626 307 Register tmp,
twisti@14626 308 Register tmp2);
twisti@14626 309
jprovino@15482 310 #endif // INCLUDE_ALL_GCS
twisti@14626 311
twisti@14626 312 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
twisti@14626 313 void c2bool(Register x);
twisti@14626 314
twisti@14626 315 // C++ bool manipulation
twisti@14626 316
twisti@14626 317 void movbool(Register dst, Address src);
twisti@14626 318 void movbool(Address dst, bool boolconst);
twisti@14626 319 void movbool(Address dst, Register src);
twisti@14626 320 void testbool(Register dst);
twisti@14626 321
twisti@14626 322 // oop manipulations
twisti@14626 323 void load_klass(Register dst, Register src);
twisti@14626 324 void store_klass(Register dst, Register src);
twisti@14626 325
twisti@14626 326 void load_heap_oop(Register dst, Address src);
twisti@14626 327 void load_heap_oop_not_null(Register dst, Address src);
twisti@14626 328 void store_heap_oop(Address dst, Register src);
twisti@14626 329 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
twisti@14626 330
twisti@14626 331 // Used for storing NULL. All other oop constants should be
twisti@14626 332 // stored using routines that take a jobject.
twisti@14626 333 void store_heap_oop_null(Address dst);
twisti@14626 334
twisti@14626 335 void load_prototype_header(Register dst, Register src);
twisti@14626 336
twisti@14626 337 #ifdef _LP64
twisti@14626 338 void store_klass_gap(Register dst, Register src);
twisti@14626 339
twisti@14626 340 // This dummy is to prevent a call to store_heap_oop from
twisti@14626 341 // converting a zero (like NULL) into a Register by giving
twisti@14626 342 // the compiler two choices it can't resolve
twisti@14626 343
twisti@14626 344 void store_heap_oop(Address dst, void* dummy);
twisti@14626 345
twisti@14626 346 void encode_heap_oop(Register r);
twisti@14626 347 void decode_heap_oop(Register r);
twisti@14626 348 void encode_heap_oop_not_null(Register r);
twisti@14626 349 void decode_heap_oop_not_null(Register r);
twisti@14626 350 void encode_heap_oop_not_null(Register dst, Register src);
twisti@14626 351 void decode_heap_oop_not_null(Register dst, Register src);
twisti@14626 352
twisti@14626 353 void set_narrow_oop(Register dst, jobject obj);
twisti@14626 354 void set_narrow_oop(Address dst, jobject obj);
twisti@14626 355 void cmp_narrow_oop(Register dst, jobject obj);
twisti@14626 356 void cmp_narrow_oop(Address dst, jobject obj);
twisti@14626 357
twisti@14626 358 void encode_klass_not_null(Register r);
twisti@14626 359 void decode_klass_not_null(Register r);
twisti@14626 360 void encode_klass_not_null(Register dst, Register src);
twisti@14626 361 void decode_klass_not_null(Register dst, Register src);
twisti@14626 362 void set_narrow_klass(Register dst, Klass* k);
twisti@14626 363 void set_narrow_klass(Address dst, Klass* k);
twisti@14626 364 void cmp_narrow_klass(Register dst, Klass* k);
twisti@14626 365 void cmp_narrow_klass(Address dst, Klass* k);
twisti@14626 366
hseigel@19319 367 // Returns the byte size of the instructions generated by decode_klass_not_null()
hseigel@19319 368 // when compressed klass pointers are being used.
hseigel@19319 369 static int instr_size_for_decode_klass_not_null();
hseigel@19319 370
twisti@14626 371 // if heap base register is used - reinit it with the correct value
twisti@14626 372 void reinit_heapbase();
twisti@14626 373
twisti@14626 374 DEBUG_ONLY(void verify_heapbase(const char* msg);)
twisti@14626 375
twisti@14626 376 #endif // _LP64
twisti@14626 377
twisti@14626 378 // Int division/remainder for Java
twisti@14626 379 // (as idivl, but checks for special case as described in JVM spec.)
twisti@14626 380 // returns idivl instruction offset for implicit exception handling
twisti@14626 381 int corrected_idivl(Register reg);
twisti@14626 382
twisti@14626 383 // Long division/remainder for Java
twisti@14626 384 // (as idivq, but checks for special case as described in JVM spec.)
twisti@14626 385 // returns idivq instruction offset for implicit exception handling
twisti@14626 386 int corrected_idivq(Register reg);
twisti@14626 387
twisti@14626 388 void int3();
twisti@14626 389
twisti@14626 390 // Long operation macros for a 32bit cpu
twisti@14626 391 // Long negation for Java
twisti@14626 392 void lneg(Register hi, Register lo);
twisti@14626 393
twisti@14626 394 // Long multiplication for Java
twisti@14626 395 // (destroys contents of eax, ebx, ecx and edx)
twisti@14626 396 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
twisti@14626 397
twisti@14626 398 // Long shifts for Java
twisti@14626 399 // (semantics as described in JVM spec.)
twisti@14626 400 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
twisti@14626 401 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
twisti@14626 402
twisti@14626 403 // Long compare for Java
twisti@14626 404 // (semantics as described in JVM spec.)
twisti@14626 405 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
twisti@14626 406
twisti@14626 407
twisti@14626 408 // misc
twisti@14626 409
twisti@14626 410 // Sign extension
twisti@14626 411 void sign_extend_short(Register reg);
twisti@14626 412 void sign_extend_byte(Register reg);
twisti@14626 413
twisti@14626 414 // Division by power of 2, rounding towards 0
twisti@14626 415 void division_with_shift(Register reg, int shift_value);
twisti@14626 416
twisti@14626 417 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
twisti@14626 418 //
twisti@14626 419 // CF (corresponds to C0) if x < y
twisti@14626 420 // PF (corresponds to C2) if unordered
twisti@14626 421 // ZF (corresponds to C3) if x = y
twisti@14626 422 //
twisti@14626 423 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 424 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
twisti@14626 425 void fcmp(Register tmp);
twisti@14626 426 // Variant of the above which allows y to be further down the stack
twisti@14626 427 // and which only pops x and y if specified. If pop_right is
twisti@14626 428 // specified then pop_left must also be specified.
twisti@14626 429 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
twisti@14626 430
twisti@14626 431 // Floating-point comparison for Java
twisti@14626 432 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
twisti@14626 433 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 434 // (semantics as described in JVM spec.)
twisti@14626 435 void fcmp2int(Register dst, bool unordered_is_less);
twisti@14626 436 // Variant of the above which allows y to be further down the stack
twisti@14626 437 // and which only pops x and y if specified. If pop_right is
twisti@14626 438 // specified then pop_left must also be specified.
twisti@14626 439 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
twisti@14626 440
twisti@14626 441 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
twisti@14626 442 // tmp is a temporary register, if none is available use noreg
twisti@14626 443 void fremr(Register tmp);
twisti@14626 444
twisti@14626 445
twisti@14626 446 // same as fcmp2int, but using SSE2
twisti@14626 447 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 448 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 449
twisti@14626 450 // Inlined sin/cos generator for Java; must not use CPU instruction
twisti@14626 451 // directly on Intel as it does not have high enough precision
twisti@14626 452 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
twisti@14626 453 // number of FPU stack slots in use; all but the topmost will
twisti@14626 454 // require saving if a slow case is necessary. Assumes argument is
twisti@14626 455 // on FP TOS; result is on FP TOS. No cpu registers are changed by
twisti@14626 456 // this code.
twisti@14626 457 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
twisti@14626 458
twisti@14626 459 // branch to L if FPU flag C2 is set/not set
twisti@14626 460 // tmp is a temporary register, if none is available use noreg
twisti@14626 461 void jC2 (Register tmp, Label& L);
twisti@14626 462 void jnC2(Register tmp, Label& L);
twisti@14626 463
twisti@14626 464 // Pop ST (ffree & fincstp combined)
twisti@14626 465 void fpop();
twisti@14626 466
zmajo@32391 467 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
zmajo@32391 468 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
zmajo@32391 469 void load_float(Address src);
zmajo@32391 470
zmajo@32391 471 // Store float value to 'address'. If UseSSE >= 1, the value is stored
zmajo@32391 472 // from register xmm0. Otherwise, the value is stored from the FPU stack.
zmajo@32391 473 void store_float(Address dst);
zmajo@32391 474
zmajo@32391 475 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
zmajo@32391 476 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
zmajo@32391 477 void load_double(Address src);
zmajo@32391 478
zmajo@32391 479 // Store double value to 'address'. If UseSSE >= 2, the value is stored
zmajo@32391 480 // from register xmm0. Otherwise, the value is stored from the FPU stack.
zmajo@32391 481 void store_double(Address dst);
zmajo@32391 482
twisti@14626 483 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
twisti@14626 484 void push_fTOS();
twisti@14626 485
twisti@14626 486 // pops double TOS element from CPU stack and pushes on FPU stack
twisti@14626 487 void pop_fTOS();
twisti@14626 488
twisti@14626 489 void empty_FPU_stack();
twisti@14626 490
twisti@14626 491 void push_IU_state();
twisti@14626 492 void pop_IU_state();
twisti@14626 493
twisti@14626 494 void push_FPU_state();
twisti@14626 495 void pop_FPU_state();
twisti@14626 496
twisti@14626 497 void push_CPU_state();
twisti@14626 498 void pop_CPU_state();
twisti@14626 499
twisti@14626 500 // Round up to a power of two
twisti@14626 501 void round_to(Register reg, int modulus);
twisti@14626 502
twisti@14626 503 // Callee saved registers handling
twisti@14626 504 void push_callee_saved_registers();
twisti@14626 505 void pop_callee_saved_registers();
twisti@14626 506
twisti@14626 507 // allocation
twisti@14626 508 void eden_allocate(
twisti@14626 509 Register obj, // result: pointer to object after successful allocation
twisti@14626 510 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 511 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 512 Register t1, // temp register
twisti@14626 513 Label& slow_case // continuation point if fast allocation fails
twisti@14626 514 );
twisti@14626 515 void tlab_allocate(
twisti@14626 516 Register obj, // result: pointer to object after successful allocation
twisti@14626 517 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 518 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 519 Register t1, // temp register
twisti@14626 520 Register t2, // temp register
twisti@14626 521 Label& slow_case // continuation point if fast allocation fails
twisti@14626 522 );
twisti@14626 523 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
zmajo@35548 524 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
zmajo@35548 525
twisti@14626 526 void incr_allocated_bytes(Register thread,
twisti@14626 527 Register var_size_in_bytes, int con_size_in_bytes,
twisti@14626 528 Register t1 = noreg);
twisti@14626 529
twisti@14626 530 // interface method calling
twisti@14626 531 void lookup_interface_method(Register recv_klass,
twisti@14626 532 Register intf_klass,
twisti@14626 533 RegisterOrConstant itable_index,
twisti@14626 534 Register method_result,
twisti@14626 535 Register scan_temp,
twisti@14626 536 Label& no_such_interface);
twisti@14626 537
twisti@14626 538 // virtual method calling
twisti@14626 539 void lookup_virtual_method(Register recv_klass,
twisti@14626 540 RegisterOrConstant vtable_index,
twisti@14626 541 Register method_result);
twisti@14626 542
twisti@14626 543 // Test sub_klass against super_klass, with fast and slow paths.
twisti@14626 544
twisti@14626 545 // The fast path produces a tri-state answer: yes / no / maybe-slow.
twisti@14626 546 // One of the three labels can be NULL, meaning take the fall-through.
twisti@14626 547 // If super_check_offset is -1, the value is loaded up from super_klass.
twisti@14626 548 // No registers are killed, except temp_reg.
twisti@14626 549 void check_klass_subtype_fast_path(Register sub_klass,
twisti@14626 550 Register super_klass,
twisti@14626 551 Register temp_reg,
twisti@14626 552 Label* L_success,
twisti@14626 553 Label* L_failure,
twisti@14626 554 Label* L_slow_path,
twisti@14626 555 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
twisti@14626 556
twisti@14626 557 // The rest of the type check; must be wired to a corresponding fast path.
twisti@14626 558 // It does not repeat the fast path logic, so don't use it standalone.
twisti@14626 559 // The temp_reg and temp2_reg can be noreg, if no temps are available.
twisti@14626 560 // Updates the sub's secondary super cache as necessary.
twisti@14626 561 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
twisti@14626 562 void check_klass_subtype_slow_path(Register sub_klass,
twisti@14626 563 Register super_klass,
twisti@14626 564 Register temp_reg,
twisti@14626 565 Register temp2_reg,
twisti@14626 566 Label* L_success,
twisti@14626 567 Label* L_failure,
twisti@14626 568 bool set_cond_codes = false);
twisti@14626 569
twisti@14626 570 // Simplified, combined version, good for typical uses.
twisti@14626 571 // Falls through on failure.
twisti@14626 572 void check_klass_subtype(Register sub_klass,
twisti@14626 573 Register super_klass,
twisti@14626 574 Register temp_reg,
twisti@14626 575 Label& L_success);
twisti@14626 576
twisti@14626 577 // method handles (JSR 292)
twisti@14626 578 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
twisti@14626 579
twisti@14626 580 //----
twisti@14626 581 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
twisti@14626 582
twisti@14626 583 // Debugging
twisti@14626 584
twisti@14626 585 // only if +VerifyOops
twisti@14626 586 // TODO: Make these macros with file and line like sparc version!
twisti@14626 587 void verify_oop(Register reg, const char* s = "broken oop");
twisti@14626 588 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
twisti@14626 589
twisti@14626 590 // TODO: verify method and klass metadata (compare against vptr?)
twisti@14626 591 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
twisti@14626 592 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
twisti@14626 593
twisti@14626 594 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
twisti@14626 595 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
twisti@14626 596
twisti@14626 597 // only if +VerifyFPU
twisti@14626 598 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
twisti@14626 599
kvn@16624 600 // Verify or restore cpu control state after JNI call
kvn@16624 601 void restore_cpu_control_state_after_jni();
kvn@16624 602
twisti@14626 603 // prints msg, dumps registers and stops execution
twisti@14626 604 void stop(const char* msg);
twisti@14626 605
twisti@14626 606 // prints msg and continues
twisti@14626 607 void warn(const char* msg);
twisti@14626 608
twisti@14626 609 // dumps registers and other state
twisti@14626 610 void print_state();
twisti@14626 611
twisti@14626 612 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
twisti@14626 613 static void debug64(char* msg, int64_t pc, int64_t regs[]);
twisti@14626 614 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
twisti@14626 615 static void print_state64(int64_t pc, int64_t regs[]);
twisti@14626 616
twisti@14626 617 void os_breakpoint();
twisti@14626 618
twisti@14626 619 void untested() { stop("untested"); }
twisti@14626 620
twisti@14626 621 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
twisti@14626 622
twisti@14626 623 void should_not_reach_here() { stop("should not reach here"); }
twisti@14626 624
twisti@14626 625 void print_CPU_state();
twisti@14626 626
twisti@14626 627 // Stack overflow checking
twisti@14626 628 void bang_stack_with_offset(int offset) {
twisti@14626 629 // stack grows down, caller passes positive offset
twisti@14626 630 assert(offset > 0, "must bang with negative offset");
twisti@14626 631 movl(Address(rsp, (-offset)), rax);
twisti@14626 632 }
twisti@14626 633
twisti@14626 634 // Writes to stack successive pages until offset reached to check for
twisti@14626 635 // stack overflow + shadow pages. Also, clobbers tmp
twisti@14626 636 void bang_stack_size(Register size, Register tmp);
twisti@14626 637
fparain@35071 638 // Check for reserved stack access in method being exited (for JIT)
fparain@35071 639 void reserved_stack_check();
fparain@35071 640
twisti@14626 641 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
twisti@14626 642 Register tmp,
twisti@14626 643 int offset);
twisti@14626 644
twisti@14626 645 // Support for serializing memory accesses between threads
twisti@14626 646 void serialize_memory(Register thread, Register tmp);
twisti@14626 647
twisti@14626 648 void verify_tlab();
twisti@14626 649
twisti@14626 650 // Biased locking support
twisti@14626 651 // lock_reg and obj_reg must be loaded up with the appropriate values.
twisti@14626 652 // swap_reg must be rax, and is killed.
twisti@14626 653 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
twisti@14626 654 // be killed; if not supplied, push/pop will be used internally to
twisti@14626 655 // allocate a temporary (inefficient, avoid if possible).
twisti@14626 656 // Optional slow case is for implementations (interpreter and C1) which branch to
twisti@14626 657 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
twisti@14626 658 // Returns offset of first potentially-faulting instruction for null
twisti@14626 659 // check info (currently consumed only by C1). If
twisti@14626 660 // swap_reg_contains_mark is true then returns -1 as it is assumed
twisti@14626 661 // the calling code has already passed any potential faults.
twisti@14626 662 int biased_locking_enter(Register lock_reg, Register obj_reg,
twisti@14626 663 Register swap_reg, Register tmp_reg,
twisti@14626 664 bool swap_reg_contains_mark,
twisti@14626 665 Label& done, Label* slow_case = NULL,
twisti@14626 666 BiasedLockingCounters* counters = NULL);
twisti@14626 667 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
kvn@22910 668 #ifdef COMPILER2
kvn@22910 669 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
kvn@22910 670 // See full desription in macroAssembler_x86.cpp.
kvn@23491 671 void fast_lock(Register obj, Register box, Register tmp,
kvn@23491 672 Register scr, Register cx1, Register cx2,
kvn@23491 673 BiasedLockingCounters* counters,
kvn@23491 674 RTMLockingCounters* rtm_counters,
kvn@23491 675 RTMLockingCounters* stack_rtm_counters,
kvn@23491 676 Metadata* method_data,
kvn@23491 677 bool use_rtm, bool profile_rtm);
kvn@23491 678 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
kvn@23491 679 #if INCLUDE_RTM_OPT
kvn@23491 680 void rtm_counters_update(Register abort_status, Register rtm_counters);
kvn@23491 681 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
kvn@23491 682 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
kvn@23491 683 RTMLockingCounters* rtm_counters,
kvn@23491 684 Metadata* method_data);
kvn@23491 685 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
kvn@23491 686 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
kvn@23491 687 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
kvn@23491 688 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
kvn@23491 689 void rtm_stack_locking(Register obj, Register tmp, Register scr,
kvn@23491 690 Register retry_on_abort_count,
kvn@23491 691 RTMLockingCounters* stack_rtm_counters,
kvn@23491 692 Metadata* method_data, bool profile_rtm,
kvn@23491 693 Label& DONE_LABEL, Label& IsInflated);
kvn@23491 694 void rtm_inflated_locking(Register obj, Register box, Register tmp,
kvn@23491 695 Register scr, Register retry_on_busy_count,
kvn@23491 696 Register retry_on_abort_count,
kvn@23491 697 RTMLockingCounters* rtm_counters,
kvn@23491 698 Metadata* method_data, bool profile_rtm,
kvn@23491 699 Label& DONE_LABEL);
kvn@23491 700 #endif
kvn@22910 701 #endif
twisti@14626 702
twisti@14626 703 Condition negate_condition(Condition cond);
twisti@14626 704
twisti@14626 705 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
twisti@14626 706 // operands. In general the names are modified to avoid hiding the instruction in Assembler
twisti@14626 707 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
twisti@14626 708 // here in MacroAssembler. The major exception to this rule is call
twisti@14626 709
twisti@14626 710 // Arithmetics
twisti@14626 711
twisti@14626 712
twisti@14626 713 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
twisti@14626 714 void addptr(Address dst, Register src);
twisti@14626 715
twisti@14626 716 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
twisti@14626 717 void addptr(Register dst, int32_t src);
twisti@14626 718 void addptr(Register dst, Register src);
twisti@14626 719 void addptr(Register dst, RegisterOrConstant src) {
twisti@14626 720 if (src.is_constant()) addptr(dst, (int) src.as_constant());
twisti@14626 721 else addptr(dst, src.as_register());
twisti@14626 722 }
twisti@14626 723
twisti@14626 724 void andptr(Register dst, int32_t src);
twisti@14626 725 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
twisti@14626 726
twisti@14626 727 void cmp8(AddressLiteral src1, int imm);
twisti@14626 728
twisti@14626 729 // renamed to drag out the casting of address to int32_t/intptr_t
twisti@14626 730 void cmp32(Register src1, int32_t imm);
twisti@14626 731
twisti@14626 732 void cmp32(AddressLiteral src1, int32_t imm);
twisti@14626 733 // compare reg - mem, or reg - &mem
twisti@14626 734 void cmp32(Register src1, AddressLiteral src2);
twisti@14626 735
twisti@14626 736 void cmp32(Register src1, Address src2);
twisti@14626 737
twisti@14626 738 #ifndef _LP64
twisti@14626 739 void cmpklass(Address dst, Metadata* obj);
twisti@14626 740 void cmpklass(Register dst, Metadata* obj);
twisti@14626 741 void cmpoop(Address dst, jobject obj);
twisti@14626 742 void cmpoop(Register dst, jobject obj);
twisti@14626 743 #endif // _LP64
twisti@14626 744
twisti@14626 745 // NOTE src2 must be the lval. This is NOT an mem-mem compare
twisti@14626 746 void cmpptr(Address src1, AddressLiteral src2);
twisti@14626 747
twisti@14626 748 void cmpptr(Register src1, AddressLiteral src2);
twisti@14626 749
twisti@14626 750 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 751 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 752 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 753
twisti@14626 754 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 755 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 756
twisti@14626 757 // cmp64 to avoild hiding cmpq
twisti@14626 758 void cmp64(Register src1, AddressLiteral src);
twisti@14626 759
twisti@14626 760 void cmpxchgptr(Register reg, Address adr);
twisti@14626 761
twisti@14626 762 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
twisti@14626 763
twisti@14626 764
twisti@14626 765 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
kvn@23491 766 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
twisti@14626 767
twisti@14626 768
twisti@14626 769 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
twisti@14626 770
twisti@14626 771 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
twisti@14626 772
twisti@14626 773 void shlptr(Register dst, int32_t shift);
twisti@14626 774 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
twisti@14626 775
twisti@14626 776 void shrptr(Register dst, int32_t shift);
twisti@14626 777 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
twisti@14626 778
twisti@14626 779 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
twisti@14626 780 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
twisti@14626 781
twisti@14626 782 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 783
twisti@14626 784 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 785 void subptr(Register dst, int32_t src);
twisti@14626 786 // Force generation of a 4 byte immediate value even if it fits into 8bit
twisti@14626 787 void subptr_imm32(Register dst, int32_t src);
twisti@14626 788 void subptr(Register dst, Register src);
twisti@14626 789 void subptr(Register dst, RegisterOrConstant src) {
twisti@14626 790 if (src.is_constant()) subptr(dst, (int) src.as_constant());
twisti@14626 791 else subptr(dst, src.as_register());
twisti@14626 792 }
twisti@14626 793
twisti@14626 794 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 795 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 796
twisti@14626 797 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 798 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 799
twisti@14626 800 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
twisti@14626 801
twisti@14626 802
twisti@14626 803
twisti@14626 804 // Helper functions for statistics gathering.
twisti@14626 805 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
twisti@14626 806 void cond_inc32(Condition cond, AddressLiteral counter_addr);
twisti@14626 807 // Unconditional atomic increment.
kvn@23491 808 void atomic_incl(Address counter_addr);
kvn@23491 809 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 810 #ifdef _LP64
kvn@23491 811 void atomic_incq(Address counter_addr);
kvn@23491 812 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 813 #endif
kvn@23491 814 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
kvn@23491 815 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
twisti@14626 816
twisti@14626 817 void lea(Register dst, AddressLiteral adr);
twisti@14626 818 void lea(Address dst, AddressLiteral adr);
twisti@14626 819 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
twisti@14626 820
twisti@14626 821 void leal32(Register dst, Address src) { leal(dst, src); }
twisti@14626 822
twisti@14626 823 // Import other testl() methods from the parent class or else
twisti@14626 824 // they will be hidden by the following overriding declaration.
twisti@14626 825 using Assembler::testl;
twisti@14626 826 void testl(Register dst, AddressLiteral src);
twisti@14626 827
twisti@14626 828 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 829 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 830 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
roland@20702 831 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
twisti@14626 832
twisti@14626 833 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
twisti@14626 834 void testptr(Register src1, Register src2);
twisti@14626 835
twisti@14626 836 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 837 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 838
twisti@14626 839 // Calls
twisti@14626 840
twisti@14626 841 void call(Label& L, relocInfo::relocType rtype);
twisti@14626 842 void call(Register entry);
twisti@14626 843
twisti@14626 844 // NOTE: this call tranfers to the effective address of entry NOT
twisti@14626 845 // the address contained by entry. This is because this is more natural
twisti@14626 846 // for jumps/calls.
twisti@14626 847 void call(AddressLiteral entry);
twisti@14626 848
twisti@14626 849 // Emit the CompiledIC call idiom
vlivanov@35086 850 void ic_call(address entry, jint method_index = 0);
twisti@14626 851
twisti@14626 852 // Jumps
twisti@14626 853
twisti@14626 854 // NOTE: these jumps tranfer to the effective address of dst NOT
twisti@14626 855 // the address contained by dst. This is because this is more natural
twisti@14626 856 // for jumps/calls.
twisti@14626 857 void jump(AddressLiteral dst);
twisti@14626 858 void jump_cc(Condition cc, AddressLiteral dst);
twisti@14626 859
twisti@14626 860 // 32bit can do a case table jump in one instruction but we no longer allow the base
twisti@14626 861 // to be installed in the Address class. This jump will tranfers to the address
twisti@14626 862 // contained in the location described by entry (not the address of entry)
twisti@14626 863 void jump(ArrayAddress entry);
twisti@14626 864
twisti@14626 865 // Floating
twisti@14626 866
twisti@14626 867 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
twisti@14626 868 void andpd(XMMRegister dst, AddressLiteral src);
vdeshpande@35540 869 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
twisti@14626 870
twisti@14626 871 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
twisti@14626 872 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
twisti@14626 873 void andps(XMMRegister dst, AddressLiteral src);
twisti@14626 874
twisti@14626 875 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
twisti@14626 876 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
twisti@14626 877 void comiss(XMMRegister dst, AddressLiteral src);
twisti@14626 878
twisti@14626 879 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
twisti@14626 880 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
twisti@14626 881 void comisd(XMMRegister dst, AddressLiteral src);
twisti@14626 882
twisti@14626 883 void fadd_s(Address src) { Assembler::fadd_s(src); }
twisti@14626 884 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
twisti@14626 885
twisti@14626 886 void fldcw(Address src) { Assembler::fldcw(src); }
twisti@14626 887 void fldcw(AddressLiteral src);
twisti@14626 888
twisti@14626 889 void fld_s(int index) { Assembler::fld_s(index); }
twisti@14626 890 void fld_s(Address src) { Assembler::fld_s(src); }
twisti@14626 891 void fld_s(AddressLiteral src);
twisti@14626 892
twisti@14626 893 void fld_d(Address src) { Assembler::fld_d(src); }
twisti@14626 894 void fld_d(AddressLiteral src);
twisti@14626 895
twisti@14626 896 void fld_x(Address src) { Assembler::fld_x(src); }
twisti@14626 897 void fld_x(AddressLiteral src);
twisti@14626 898
twisti@14626 899 void fmul_s(Address src) { Assembler::fmul_s(src); }
twisti@14626 900 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
twisti@14626 901
twisti@14626 902 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
twisti@14626 903 void ldmxcsr(AddressLiteral src);
twisti@14626 904
vdeshpande@36555 905 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
vdeshpande@36555 906 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
vdeshpande@36555 907 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 908 bool multi_block);
vdeshpande@36555 909
vdeshpande@36555 910 #ifdef _LP64
vdeshpande@36555 911 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
vdeshpande@36555 912 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
vdeshpande@36555 913 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 914 bool multi_block, XMMRegister shuf_mask);
vdeshpande@36555 915 #else
vdeshpande@36555 916 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
vdeshpande@36555 917 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
vdeshpande@36555 918 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 919 bool multi_block);
vdeshpande@36555 920 #endif
vdeshpande@36555 921
iveresov@33089 922 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
iveresov@33089 923 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
iveresov@33089 924 Register rax, Register rcx, Register rdx, Register tmp);
iveresov@33465 925
vdeshpande@36555 926 #ifdef _LP64
iveresov@33465 927 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
iveresov@33465 928 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 929 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
vdeshpande@35540 930
kvn@35146 931 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
kvn@35146 932 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
vdeshpande@36555 933 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
iveresov@33465 934
vdeshpande@35540 935 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@35540 936 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 937 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
vdeshpande@36555 938 Register tmp3, Register tmp4);
vdeshpande@35540 939
vdeshpande@35540 940 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@35540 941 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 942 Register rax, Register rcx, Register rdx, Register tmp1,
vdeshpande@36555 943 Register tmp2, Register tmp3, Register tmp4);
vdeshpande@36555 944 #else
vdeshpande@36555 945 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 946 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 947 Register rax, Register rcx, Register rdx, Register tmp1);
vdeshpande@35540 948
vdeshpande@36555 949 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
vdeshpande@36555 950 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
vdeshpande@36555 951 Register rdx, Register tmp);
vdeshpande@36555 952
vdeshpande@36555 953 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 954 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 955 Register rax, Register rbx, Register rdx);
vdeshpande@36555 956
vdeshpande@36555 957 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 958 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 959 Register rax, Register rcx, Register rdx, Register tmp);
vdeshpande@36555 960
vdeshpande@35540 961 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
vdeshpande@35540 962 Register edx, Register ebx, Register esi, Register edi,
vdeshpande@35540 963 Register ebp, Register esp);
vdeshpande@36555 964
vdeshpande@35540 965 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
vdeshpande@35540 966 Register esi, Register edi, Register ebp, Register esp);
vdeshpande@35540 967 #endif
vdeshpande@35540 968
twisti@14626 969 void increase_precision();
twisti@14626 970 void restore_precision();
twisti@14626 971
twisti@14626 972 private:
twisti@14626 973
twisti@14626 974 // call runtime as a fallback for trig functions and pow/exp.
twisti@14626 975 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
twisti@14626 976
twisti@14626 977 // these are private because users should be doing movflt/movdbl
twisti@14626 978
twisti@14626 979 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 980 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 981 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
twisti@14626 982 void movss(XMMRegister dst, AddressLiteral src);
twisti@14626 983
twisti@14626 984 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
twisti@14626 985 void movlpd(XMMRegister dst, AddressLiteral src);
twisti@14626 986
twisti@14626 987 public:
twisti@14626 988
twisti@14626 989 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
twisti@14626 990 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
twisti@14626 991 void addsd(XMMRegister dst, AddressLiteral src);
twisti@14626 992
twisti@14626 993 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
twisti@14626 994 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
twisti@14626 995 void addss(XMMRegister dst, AddressLiteral src);
twisti@14626 996
vdeshpande@35540 997 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
vdeshpande@35540 998 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
vdeshpande@35540 999 void addpd(XMMRegister dst, AddressLiteral src);
vdeshpande@35540 1000
twisti@14626 1001 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
twisti@14626 1002 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
twisti@14626 1003 void divsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1004
twisti@14626 1005 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
twisti@14626 1006 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
twisti@14626 1007 void divss(XMMRegister dst, AddressLiteral src);
twisti@14626 1008
twisti@14626 1009 // Move Unaligned Double Quadword
iveresov@34162 1010 void movdqu(Address dst, XMMRegister src);
iveresov@34162 1011 void movdqu(XMMRegister dst, Address src);
iveresov@34162 1012 void movdqu(XMMRegister dst, XMMRegister src);
twisti@14626 1013 void movdqu(XMMRegister dst, AddressLiteral src);
iveresov@34162 1014 // AVX Unaligned forms
iveresov@34162 1015 void vmovdqu(Address dst, XMMRegister src);
iveresov@34162 1016 void vmovdqu(XMMRegister dst, Address src);
iveresov@34162 1017 void vmovdqu(XMMRegister dst, XMMRegister src);
iveresov@34162 1018 void vmovdqu(XMMRegister dst, AddressLiteral src);
twisti@14626 1019
drchase@18507 1020 // Move Aligned Double Quadword
drchase@18507 1021 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
drchase@18507 1022 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
drchase@18507 1023 void movdqa(XMMRegister dst, AddressLiteral src);
drchase@18507 1024
twisti@14626 1025 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 1026 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 1027 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
twisti@14626 1028 void movsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1029
iveresov@33089 1030 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
iveresov@33089 1031 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
iveresov@33089 1032 void mulpd(XMMRegister dst, AddressLiteral src);
iveresov@33089 1033
twisti@14626 1034 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
twisti@14626 1035 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
twisti@14626 1036 void mulsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1037
twisti@14626 1038 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
twisti@14626 1039 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
twisti@14626 1040 void mulss(XMMRegister dst, AddressLiteral src);
twisti@14626 1041
kvn@25932 1042 // Carry-Less Multiplication Quadword
kvn@25932 1043 void pclmulldq(XMMRegister dst, XMMRegister src) {
kvn@25932 1044 // 0x00 - multiply lower 64 bits [0:63]
kvn@25932 1045 Assembler::pclmulqdq(dst, src, 0x00);
kvn@25932 1046 }
kvn@25932 1047 void pclmulhdq(XMMRegister dst, XMMRegister src) {
kvn@25932 1048 // 0x11 - multiply upper 64 bits [64:127]
kvn@25932 1049 Assembler::pclmulqdq(dst, src, 0x11);
kvn@25932 1050 }
kvn@25932 1051
mcberg@34203 1052 void pcmpeqb(XMMRegister dst, XMMRegister src);
mcberg@34203 1053 void pcmpeqw(XMMRegister dst, XMMRegister src);
mcberg@34203 1054
mcberg@34203 1055 void pcmpestri(XMMRegister dst, Address src, int imm8);
mcberg@34203 1056 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
mcberg@34203 1057
mcberg@34203 1058 void pmovzxbw(XMMRegister dst, XMMRegister src);
mcberg@34203 1059 void pmovzxbw(XMMRegister dst, Address src);
mcberg@34203 1060
mcberg@34203 1061 void pmovmskb(Register dst, XMMRegister src);
mcberg@34203 1062
mcberg@34203 1063 void ptest(XMMRegister dst, XMMRegister src);
mcberg@34203 1064
twisti@14626 1065 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
twisti@14626 1066 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
twisti@14626 1067 void sqrtsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1068
twisti@14626 1069 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
twisti@14626 1070 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
twisti@14626 1071 void sqrtss(XMMRegister dst, AddressLiteral src);
twisti@14626 1072
twisti@14626 1073 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
twisti@14626 1074 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
twisti@14626 1075 void subsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1076
twisti@14626 1077 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
twisti@14626 1078 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
twisti@14626 1079 void subss(XMMRegister dst, AddressLiteral src);
twisti@14626 1080
twisti@14626 1081 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
twisti@14626 1082 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
twisti@14626 1083 void ucomiss(XMMRegister dst, AddressLiteral src);
twisti@14626 1084
twisti@14626 1085 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
twisti@14626 1086 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
twisti@14626 1087 void ucomisd(XMMRegister dst, AddressLiteral src);
twisti@14626 1088
twisti@14626 1089 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
iveresov@34162 1090 void xorpd(XMMRegister dst, XMMRegister src);
twisti@14626 1091 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
twisti@14626 1092 void xorpd(XMMRegister dst, AddressLiteral src);
twisti@14626 1093
twisti@14626 1094 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
iveresov@34162 1095 void xorps(XMMRegister dst, XMMRegister src);
twisti@14626 1096 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
twisti@14626 1097 void xorps(XMMRegister dst, AddressLiteral src);
twisti@14626 1098
twisti@14626 1099 // Shuffle Bytes
twisti@14626 1100 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
twisti@14626 1101 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
twisti@14626 1102 void pshufb(XMMRegister dst, AddressLiteral src);
twisti@14626 1103 // AVX 3-operands instructions
twisti@14626 1104
twisti@14626 1105 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1106 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1107 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1108
twisti@14626 1109 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1110 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1111 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1112
iveresov@34162 1113 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
iveresov@34162 1114 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
iveresov@34162 1115
iveresov@34162 1116 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1117 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1118
iveresov@34162 1119 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1120 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1121
mcberg@34203 1122 void vpbroadcastw(XMMRegister dst, XMMRegister src);
mcberg@34203 1123
mcberg@34203 1124 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1125 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1126
mcberg@34203 1127 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
mcberg@34203 1128 void vpmovmskb(Register dst, XMMRegister src);
mcberg@34203 1129
mcberg@34203 1130 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1131 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
mcberg@34203 1132
iveresov@34162 1133 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1134 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1135
iveresov@34162 1136 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1137 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1138
iveresov@34162 1139 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1140 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1141
iveresov@34162 1142 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1143 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1144
iveresov@34162 1145 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1146 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1147
mcberg@34203 1148 void vptest(XMMRegister dst, XMMRegister src);
mcberg@34203 1149
iveresov@34162 1150 void punpcklbw(XMMRegister dst, XMMRegister src);
iveresov@34162 1151 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
iveresov@34162 1152
iveresov@34162 1153 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
iveresov@34162 1154 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
iveresov@34162 1155
kvn@30624 1156 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
kvn@30624 1157 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
kvn@30624 1158 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1159
kvn@30624 1160 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
kvn@30624 1161 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
kvn@30624 1162 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1163
twisti@14626 1164 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1165 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1166 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1167
twisti@14626 1168 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1169 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1170 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1171
twisti@14626 1172 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1173 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1174 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1175
twisti@14626 1176 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1177 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1178 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1179
twisti@14626 1180 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1181 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1182 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1183
twisti@14626 1184 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1185 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1186 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1187
mcberg@32727 1188 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
mcberg@32727 1189 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
mcberg@32727 1190
twisti@14626 1191 // AVX Vector instructions
twisti@14626 1192
kvn@30624 1193 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
kvn@30624 1194 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
kvn@30624 1195 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1196
kvn@30624 1197 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
kvn@30624 1198 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
kvn@30624 1199 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1200
kvn@30624 1201 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
kvn@30624 1202 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
kvn@30624 1203 Assembler::vpxor(dst, nds, src, vector_len);
twisti@14626 1204 else
kvn@30624 1205 Assembler::vxorpd(dst, nds, src, vector_len);
twisti@14626 1206 }
kvn@30624 1207 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
kvn@30624 1208 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
kvn@30624 1209 Assembler::vpxor(dst, nds, src, vector_len);
twisti@14626 1210 else
kvn@30624 1211 Assembler::vxorpd(dst, nds, src, vector_len);
twisti@14626 1212 }
twisti@14626 1213
kvn@15117 1214 // Simple version for AVX2 256bit vectors
kvn@15117 1215 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1216 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1217
mikael@36561 1218 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
mcberg@37293 1219 if (UseAVX > 2) {
mcberg@37293 1220 Assembler::vinserti32x4(dst, dst, src, imm8);
mcberg@37293 1221 } else if (UseAVX > 1) {
mcberg@37293 1222 // vinserti128 is available only in AVX2
mikael@36561 1223 Assembler::vinserti128(dst, nds, src, imm8);
mikael@36561 1224 } else {
mikael@36561 1225 Assembler::vinsertf128(dst, nds, src, imm8);
mikael@36561 1226 }
twisti@14626 1227 }
twisti@14626 1228
mikael@36561 1229 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
mcberg@37293 1230 if (UseAVX > 2) {
mcberg@37293 1231 Assembler::vinserti32x4(dst, dst, src, imm8);
mcberg@37293 1232 } else if (UseAVX > 1) {
mcberg@37293 1233 // vinserti128 is available only in AVX2
mikael@36561 1234 Assembler::vinserti128(dst, nds, src, imm8);
mikael@36561 1235 } else {
mikael@36561 1236 Assembler::vinsertf128(dst, nds, src, imm8);
mikael@36561 1237 }
mikael@36561 1238 }
mikael@36561 1239
mikael@36561 1240 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
mcberg@37293 1241 if (UseAVX > 2) {
mcberg@37293 1242 Assembler::vextracti32x4(dst, src, imm8);
mcberg@37293 1243 } else if (UseAVX > 1) {
mcberg@37293 1244 // vextracti128 is available only in AVX2
mikael@36561 1245 Assembler::vextracti128(dst, src, imm8);
mikael@36561 1246 } else {
mikael@36561 1247 Assembler::vextractf128(dst, src, imm8);
mikael@36561 1248 }
mikael@36561 1249 }
mikael@36561 1250
mikael@36561 1251 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
mcberg@37293 1252 if (UseAVX > 2) {
mcberg@37293 1253 Assembler::vextracti32x4(dst, src, imm8);
mcberg@37293 1254 } else if (UseAVX > 1) {
mcberg@37293 1255 // vextracti128 is available only in AVX2
mikael@36561 1256 Assembler::vextracti128(dst, src, imm8);
mikael@36561 1257 } else {
mikael@36561 1258 Assembler::vextractf128(dst, src, imm8);
mikael@36561 1259 }
mikael@36561 1260 }
mikael@36561 1261
mikael@36561 1262 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
mikael@36561 1263 void vinserti128_high(XMMRegister dst, XMMRegister src) {
mikael@36561 1264 vinserti128(dst, dst, src, 1);
mikael@36561 1265 }
mikael@36561 1266 void vinserti128_high(XMMRegister dst, Address src) {
mikael@36561 1267 vinserti128(dst, dst, src, 1);
mikael@36561 1268 }
mikael@36561 1269 void vextracti128_high(XMMRegister dst, XMMRegister src) {
mikael@36561 1270 vextracti128(dst, src, 1);
mikael@36561 1271 }
mikael@36561 1272 void vextracti128_high(Address dst, XMMRegister src) {
mikael@36561 1273 vextracti128(dst, src, 1);
mikael@36561 1274 }
mcberg@37293 1275
mikael@36561 1276 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1277 if (UseAVX > 2) {
mcberg@37293 1278 Assembler::vinsertf32x4(dst, dst, src, 1);
mcberg@37293 1279 } else {
mcberg@37293 1280 Assembler::vinsertf128(dst, dst, src, 1);
mcberg@37293 1281 }
mikael@36561 1282 }
mcberg@37293 1283
mikael@36561 1284 void vinsertf128_high(XMMRegister dst, Address src) {
mcberg@37293 1285 if (UseAVX > 2) {
mcberg@37293 1286 Assembler::vinsertf32x4(dst, dst, src, 1);
mcberg@37293 1287 } else {
mcberg@37293 1288 Assembler::vinsertf128(dst, dst, src, 1);
mcberg@37293 1289 }
mikael@36561 1290 }
mcberg@37293 1291
mikael@36561 1292 void vextractf128_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1293 if (UseAVX > 2) {
mcberg@37293 1294 Assembler::vextractf32x4(dst, src, 1);
mcberg@37293 1295 } else {
mcberg@37293 1296 Assembler::vextractf128(dst, src, 1);
mcberg@37293 1297 }
mikael@36561 1298 }
mcberg@37293 1299
mikael@36561 1300 void vextractf128_high(Address dst, XMMRegister src) {
mcberg@37293 1301 if (UseAVX > 2) {
mcberg@37293 1302 Assembler::vextractf32x4(dst, src, 1);
mcberg@37293 1303 } else {
mcberg@37293 1304 Assembler::vextractf128(dst, src, 1);
mcberg@37293 1305 }
mikael@36561 1306 }
mikael@36561 1307
mikael@36561 1308 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
mikael@36561 1309 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1310 Assembler::vinserti64x4(dst, dst, src, 1);
mikael@36561 1311 }
mikael@36561 1312 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1313 Assembler::vinsertf64x4(dst, dst, src, 1);
mikael@36561 1314 }
mikael@36561 1315 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1316 Assembler::vextracti64x4(dst, src, 1);
mikael@36561 1317 }
mikael@36561 1318 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1319 Assembler::vextractf64x4(dst, src, 1);
mikael@36561 1320 }
mikael@36561 1321 void vextractf64x4_high(Address dst, XMMRegister src) {
mcberg@37293 1322 Assembler::vextractf64x4(dst, src, 1);
mikael@36561 1323 }
mikael@36561 1324 void vinsertf64x4_high(XMMRegister dst, Address src) {
mcberg@37293 1325 Assembler::vinsertf64x4(dst, dst, src, 1);
mikael@36561 1326 }
mikael@36561 1327
mikael@36561 1328 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
mikael@36561 1329 void vinserti128_low(XMMRegister dst, XMMRegister src) {
mikael@36561 1330 vinserti128(dst, dst, src, 0);
mikael@36561 1331 }
mikael@36561 1332 void vinserti128_low(XMMRegister dst, Address src) {
mikael@36561 1333 vinserti128(dst, dst, src, 0);
mikael@36561 1334 }
mikael@36561 1335 void vextracti128_low(XMMRegister dst, XMMRegister src) {
mikael@36561 1336 vextracti128(dst, src, 0);
mikael@36561 1337 }
mikael@36561 1338 void vextracti128_low(Address dst, XMMRegister src) {
mikael@36561 1339 vextracti128(dst, src, 0);
mikael@36561 1340 }
mcberg@37293 1341
mikael@36561 1342 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1343 if (UseAVX > 2) {
mcberg@37293 1344 Assembler::vinsertf32x4(dst, dst, src, 0);
mcberg@37293 1345 } else {
mcberg@37293 1346 Assembler::vinsertf128(dst, dst, src, 0);
mcberg@37293 1347 }
mikael@36561 1348 }
mcberg@37293 1349
mikael@36561 1350 void vinsertf128_low(XMMRegister dst, Address src) {
mcberg@37293 1351 if (UseAVX > 2) {
mcberg@37293 1352 Assembler::vinsertf32x4(dst, dst, src, 0);
mcberg@37293 1353 } else {
mcberg@37293 1354 Assembler::vinsertf128(dst, dst, src, 0);
mcberg@37293 1355 }
mikael@36561 1356 }
mcberg@37293 1357
mikael@36561 1358 void vextractf128_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1359 if (UseAVX > 2) {
mcberg@37293 1360 Assembler::vextractf32x4(dst, src, 0);
mcberg@37293 1361 } else {
mcberg@37293 1362 Assembler::vextractf128(dst, src, 0);
mcberg@37293 1363 }
mikael@36561 1364 }
mcberg@37293 1365
mikael@36561 1366 void vextractf128_low(Address dst, XMMRegister src) {
mcberg@37293 1367 if (UseAVX > 2) {
mcberg@37293 1368 Assembler::vextractf32x4(dst, src, 0);
mcberg@37293 1369 } else {
mcberg@37293 1370 Assembler::vextractf128(dst, src, 0);
mcberg@37293 1371 }
mikael@36561 1372 }
mikael@36561 1373
mikael@36561 1374 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
mikael@36561 1375 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1376 Assembler::vinserti64x4(dst, dst, src, 0);
mikael@36561 1377 }
mikael@36561 1378 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1379 Assembler::vinsertf64x4(dst, dst, src, 0);
mikael@36561 1380 }
mikael@36561 1381 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1382 Assembler::vextracti64x4(dst, src, 0);
mikael@36561 1383 }
mikael@36561 1384 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1385 Assembler::vextractf64x4(dst, src, 0);
mikael@36561 1386 }
mikael@36561 1387 void vextractf64x4_low(Address dst, XMMRegister src) {
mcberg@37293 1388 Assembler::vextractf64x4(dst, src, 0);
mikael@36561 1389 }
mikael@36561 1390 void vinsertf64x4_low(XMMRegister dst, Address src) {
mcberg@37293 1391 Assembler::vinsertf64x4(dst, dst, src, 0);
mikael@36561 1392 }
mikael@36561 1393
drchase@18507 1394 // Carry-Less Multiplication Quadword
drchase@18507 1395 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1396 // 0x00 - multiply lower 64 bits [0:63]
drchase@18507 1397 Assembler::vpclmulqdq(dst, nds, src, 0x00);
drchase@18507 1398 }
drchase@18507 1399 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1400 // 0x11 - multiply upper 64 bits [64:127]
drchase@18507 1401 Assembler::vpclmulqdq(dst, nds, src, 0x11);
drchase@18507 1402 }
drchase@18507 1403
twisti@14626 1404 // Data
twisti@14626 1405
twisti@14626 1406 void cmov32( Condition cc, Register dst, Address src);
twisti@14626 1407 void cmov32( Condition cc, Register dst, Register src);
twisti@14626 1408
twisti@14626 1409 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
twisti@14626 1410
twisti@14626 1411 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1412 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1413
twisti@14626 1414 void movoop(Register dst, jobject obj);
twisti@14626 1415 void movoop(Address dst, jobject obj);
twisti@14626 1416
twisti@14626 1417 void mov_metadata(Register dst, Metadata* obj);
twisti@14626 1418 void mov_metadata(Address dst, Metadata* obj);
twisti@14626 1419
twisti@14626 1420 void movptr(ArrayAddress dst, Register src);
twisti@14626 1421 // can this do an lea?
twisti@14626 1422 void movptr(Register dst, ArrayAddress src);
twisti@14626 1423
twisti@14626 1424 void movptr(Register dst, Address src);
twisti@14626 1425
kvn@23491 1426 #ifdef _LP64
kvn@23491 1427 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
kvn@23491 1428 #else
kvn@23491 1429 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
kvn@23491 1430 #endif
twisti@14626 1431
twisti@14626 1432 void movptr(Register dst, intptr_t src);
twisti@14626 1433 void movptr(Register dst, Register src);
twisti@14626 1434 void movptr(Address dst, intptr_t src);
twisti@14626 1435
twisti@14626 1436 void movptr(Address dst, Register src);
twisti@14626 1437
twisti@14626 1438 void movptr(Register dst, RegisterOrConstant src) {
twisti@14626 1439 if (src.is_constant()) movptr(dst, src.as_constant());
twisti@14626 1440 else movptr(dst, src.as_register());
twisti@14626 1441 }
twisti@14626 1442
twisti@14626 1443 #ifdef _LP64
twisti@14626 1444 // Generally the next two are only used for moving NULL
twisti@14626 1445 // Although there are situations in initializing the mark word where
twisti@14626 1446 // they could be used. They are dangerous.
twisti@14626 1447
twisti@14626 1448 // They only exist on LP64 so that int32_t and intptr_t are not the same
twisti@14626 1449 // and we have ambiguous declarations.
twisti@14626 1450
twisti@14626 1451 void movptr(Address dst, int32_t imm32);
twisti@14626 1452 void movptr(Register dst, int32_t imm32);
twisti@14626 1453 #endif // _LP64
twisti@14626 1454
twisti@14626 1455 // to avoid hiding movl
twisti@14626 1456 void mov32(AddressLiteral dst, Register src);
twisti@14626 1457 void mov32(Register dst, AddressLiteral src);
twisti@14626 1458
twisti@14626 1459 // to avoid hiding movb
twisti@14626 1460 void movbyte(ArrayAddress dst, int src);
twisti@14626 1461
twisti@14626 1462 // Import other mov() methods from the parent class or else
twisti@14626 1463 // they will be hidden by the following overriding declaration.
twisti@14626 1464 using Assembler::movdl;
twisti@14626 1465 using Assembler::movq;
twisti@14626 1466 void movdl(XMMRegister dst, AddressLiteral src);
twisti@14626 1467 void movq(XMMRegister dst, AddressLiteral src);
twisti@14626 1468
twisti@14626 1469 // Can push value or effective address
twisti@14626 1470 void pushptr(AddressLiteral src);
twisti@14626 1471
twisti@14626 1472 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
twisti@14626 1473 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
twisti@14626 1474
twisti@14626 1475 void pushoop(jobject obj);
twisti@14626 1476 void pushklass(Metadata* obj);
twisti@14626 1477
twisti@14626 1478 // sign extend as need a l to ptr sized element
twisti@14626 1479 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
twisti@14626 1480 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
twisti@14626 1481
twisti@14626 1482 // C2 compiled method's prolog code.
roland@24018 1483 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
twisti@14626 1484
shade@36554 1485 // clear memory of size 'cnt' qwords, starting at 'base';
shade@36554 1486 // if 'is_large' is set, do not try to produce short loop
shade@36554 1487 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
kvn@15114 1488
thartmann@33628 1489 #ifdef COMPILER2
thartmann@33628 1490 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
thartmann@33628 1491 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
thartmann@33628 1492
twisti@14626 1493 // IndexOf strings.
twisti@14626 1494 // Small strings are loaded through stack if they cross page boundary.
twisti@14626 1495 void string_indexof(Register str1, Register str2,
twisti@14626 1496 Register cnt1, Register cnt2,
twisti@14626 1497 int int_cnt2, Register result,
thartmann@33628 1498 XMMRegister vec, Register tmp,
thartmann@33628 1499 int ae);
twisti@14626 1500
twisti@14626 1501 // IndexOf for constant substrings with size >= 8 elements
twisti@14626 1502 // which don't need to be loaded through stack.
twisti@14626 1503 void string_indexofC8(Register str1, Register str2,
twisti@14626 1504 Register cnt1, Register cnt2,
twisti@14626 1505 int int_cnt2, Register result,
thartmann@33628 1506 XMMRegister vec, Register tmp,
thartmann@33628 1507 int ae);
twisti@14626 1508
twisti@14626 1509 // Smallest code: we don't need to load through stack,
twisti@14626 1510 // check string tail.
twisti@14626 1511
thartmann@33628 1512 // helper function for string_compare
thartmann@33628 1513 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
thartmann@33628 1514 Address::ScaleFactor scale, Address::ScaleFactor scale1,
thartmann@33628 1515 Address::ScaleFactor scale2, Register index, int ae);
twisti@14626 1516 // Compare strings.
twisti@14626 1517 void string_compare(Register str1, Register str2,
twisti@14626 1518 Register cnt1, Register cnt2, Register result,
thartmann@33628 1519 XMMRegister vec1, int ae);
twisti@14626 1520
thartmann@33628 1521 // Search for Non-ASCII character (Negative byte value) in a byte array,
thartmann@33628 1522 // return true if it has any and false otherwise.
thartmann@33628 1523 void has_negatives(Register ary1, Register len,
thartmann@33628 1524 Register result, Register tmp1,
thartmann@33628 1525 XMMRegister vec1, XMMRegister vec2);
thartmann@33628 1526
thartmann@33628 1527 // Compare char[] or byte[] arrays.
thartmann@33628 1528 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
thartmann@33628 1529 Register limit, Register result, Register chr,
thartmann@33628 1530 XMMRegister vec1, XMMRegister vec2, bool is_char);
thartmann@33628 1531
thartmann@33628 1532 #endif
twisti@14626 1533
twisti@14626 1534 // Fill primitive arrays
twisti@14626 1535 void generate_fill(BasicType t, bool aligned,
twisti@14626 1536 Register to, Register value, Register count,
twisti@14626 1537 Register rtmp, XMMRegister xtmp);
twisti@14626 1538
kvn@15242 1539 void encode_iso_array(Register src, Register dst, Register len,
kvn@15242 1540 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
kvn@15242 1541 XMMRegister tmp4, Register tmp5, Register result);
kvn@15242 1542
kvn@26434 1543 #ifdef _LP64
kvn@26434 1544 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
kvn@26434 1545 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
kvn@26434 1546 Register y, Register y_idx, Register z,
kvn@26434 1547 Register carry, Register product,
kvn@26434 1548 Register idx, Register kdx);
kvn@26434 1549 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
kvn@26434 1550 Register yz_idx, Register idx,
kvn@26434 1551 Register carry, Register product, int offset);
kvn@26434 1552 void multiply_128_x_128_bmi2_loop(Register y, Register z,
kvn@26434 1553 Register carry, Register carry2,
kvn@26434 1554 Register idx, Register jdx,
kvn@26434 1555 Register yz_idx1, Register yz_idx2,
kvn@26434 1556 Register tmp, Register tmp3, Register tmp4);
kvn@26434 1557 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
kvn@26434 1558 Register yz_idx, Register idx, Register jdx,
kvn@26434 1559 Register carry, Register product,
kvn@26434 1560 Register carry2);
kvn@26434 1561 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
kvn@26434 1562 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
kvn@31129 1563 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
kvn@31129 1564 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
kvn@31129 1565 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
kvn@31129 1566 Register tmp2);
kvn@31129 1567 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
kvn@31129 1568 Register rdxReg, Register raxReg);
kvn@31129 1569 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
kvn@31129 1570 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
kvn@31129 1571 Register tmp3, Register tmp4);
kvn@31129 1572 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
kvn@31129 1573 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
kvn@31129 1574
kvn@31129 1575 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
kvn@31129 1576 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
kvn@31129 1577 Register raxReg);
kvn@31129 1578 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
kvn@31129 1579 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
kvn@31129 1580 Register raxReg);
kvn@35110 1581 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
kvn@35110 1582 Register result, Register tmp1, Register tmp2,
kvn@35110 1583 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
kvn@26434 1584 #endif
kvn@26434 1585
kvn@33066 1586 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
drchase@18507 1587 void update_byte_crc32(Register crc, Register val, Register table);
drchase@18507 1588 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
kvn@33066 1589 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
kvn@33066 1590 // Note on a naming convention:
kvn@33066 1591 // Prefix w = register only used on a Westmere+ architecture
kvn@33066 1592 // Prefix n = register only used on a Nehalem architecture
kvn@33066 1593 #ifdef _LP64
kvn@33066 1594 void crc32c_ipl_alg4(Register in_out, uint32_t n,
kvn@33066 1595 Register tmp1, Register tmp2, Register tmp3);
kvn@33066 1596 #else
kvn@33066 1597 void crc32c_ipl_alg4(Register in_out, uint32_t n,
kvn@33066 1598 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1599 XMMRegister xtmp1, XMMRegister xtmp2);
kvn@33066 1600 #endif
kvn@33066 1601 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
kvn@33066 1602 Register in_out,
kvn@33066 1603 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
kvn@33066 1604 XMMRegister w_xtmp2,
kvn@33066 1605 Register tmp1,
kvn@33066 1606 Register n_tmp2, Register n_tmp3);
kvn@33066 1607 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
kvn@33066 1608 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1609 Register tmp1, Register tmp2,
kvn@33066 1610 Register n_tmp3);
kvn@33066 1611 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
kvn@33066 1612 Register in_out1, Register in_out2, Register in_out3,
kvn@33066 1613 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1614 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1615 Register tmp4, Register tmp5,
kvn@33066 1616 Register n_tmp6);
kvn@33066 1617 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
kvn@33066 1618 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1619 Register tmp4, Register tmp5, Register tmp6,
kvn@33066 1620 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1621 bool is_pclmulqdq_supported);
drchase@18507 1622 // Fold 128-bit data chunk
drchase@18507 1623 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
drchase@18507 1624 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
drchase@18507 1625 // Fold 8-bit data
drchase@18507 1626 void fold_8bit_crc32(Register crc, Register table, Register tmp);
drchase@18507 1627 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
drchase@18507 1628
thartmann@33628 1629 // Compress char[] array to byte[].
thartmann@33628 1630 void char_array_compress(Register src, Register dst, Register len,
thartmann@33628 1631 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
thartmann@33628 1632 XMMRegister tmp4, Register tmp5, Register result);
thartmann@33628 1633
thartmann@33628 1634 // Inflate byte[] array to char[].
thartmann@33628 1635 void byte_array_inflate(Register src, Register dst, Register len,
thartmann@33628 1636 XMMRegister tmp1, Register tmp2);
thartmann@33628 1637
twisti@14626 1638 };
twisti@14626 1639
twisti@14626 1640 /**
twisti@14626 1641 * class SkipIfEqual:
twisti@14626 1642 *
twisti@14626 1643 * Instantiating this class will result in assembly code being output that will
twisti@14626 1644 * jump around any code emitted between the creation of the instance and it's
twisti@14626 1645 * automatic destruction at the end of a scope block, depending on the value of
twisti@14626 1646 * the flag passed to the constructor, which will be checked at run-time.
twisti@14626 1647 */
twisti@14626 1648 class SkipIfEqual {
twisti@14626 1649 private:
twisti@14626 1650 MacroAssembler* _masm;
twisti@14626 1651 Label _label;
twisti@14626 1652
twisti@14626 1653 public:
twisti@14626 1654 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
twisti@14626 1655 ~SkipIfEqual();
twisti@14626 1656 };
twisti@14626 1657
twisti@14626 1658 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP