annotate hotspot/src/cpu/x86/vm/macroAssembler_x86.hpp @ 41323:ddd5600d4762

8154122: Intrinsify fused mac operations Summary: added FMA intrinsics on x86 Reviewed-by: kvn, aph, darcy
author vdeshpande
date Fri, 26 Aug 2016 12:17:50 -0700
parents 39e631ed7145
children db627462f2c9
rev   line source
twisti@14626 1 /*
mikael@36561 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
twisti@14626 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@14626 4 *
twisti@14626 5 * This code is free software; you can redistribute it and/or modify it
twisti@14626 6 * under the terms of the GNU General Public License version 2 only, as
twisti@14626 7 * published by the Free Software Foundation.
twisti@14626 8 *
twisti@14626 9 * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@14626 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@14626 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
twisti@14626 12 * version 2 for more details (a copy is included in the LICENSE file that
twisti@14626 13 * accompanied this code).
twisti@14626 14 *
twisti@14626 15 * You should have received a copy of the GNU General Public License version
twisti@14626 16 * 2 along with this work; if not, write to the Free Software Foundation,
twisti@14626 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@14626 18 *
twisti@14626 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
twisti@14626 20 * or visit www.oracle.com if you need additional information or have any
twisti@14626 21 * questions.
twisti@14626 22 *
twisti@14626 23 */
twisti@14626 24
twisti@14626 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 27
twisti@14626 28 #include "asm/assembler.hpp"
jprovino@15482 29 #include "utilities/macros.hpp"
kvn@23491 30 #include "runtime/rtmLocking.hpp"
twisti@14626 31
twisti@14626 32 // MacroAssembler extends Assembler by frequently used macros.
twisti@14626 33 //
twisti@14626 34 // Instructions for which a 'better' code sequence exists depending
twisti@14626 35 // on arguments should also go in here.
twisti@14626 36
twisti@14626 37 class MacroAssembler: public Assembler {
twisti@14626 38 friend class LIR_Assembler;
twisti@14626 39 friend class Runtime1; // as_Address()
twisti@14626 40
twisti@14626 41 protected:
twisti@14626 42
twisti@14626 43 Address as_Address(AddressLiteral adr);
twisti@14626 44 Address as_Address(ArrayAddress adr);
twisti@14626 45
twisti@14626 46 // Support for VM calls
twisti@14626 47 //
twisti@14626 48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
twisti@14626 49 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 50 // additional registers when doing a VM call).
iveresov@33465 51
coleenp@35214 52 virtual void call_VM_leaf_base(
twisti@14626 53 address entry_point, // the entry point
twisti@14626 54 int number_of_arguments // the number of arguments to pop after the call
twisti@14626 55 );
twisti@14626 56
twisti@14626 57 // This is the base routine called by the different versions of call_VM. The interpreter
twisti@14626 58 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 59 // additional registers when doing a VM call).
twisti@14626 60 //
twisti@14626 61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
twisti@14626 62 // returns the register which contains the thread upon return. If a thread register has been
twisti@14626 63 // specified, the return value will correspond to that register. If no last_java_sp is specified
twisti@14626 64 // (noreg) than rsp will be used instead.
coleenp@35214 65 virtual void call_VM_base( // returns the register containing the thread upon return
twisti@14626 66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
twisti@14626 67 Register java_thread, // the thread if computed before ; use noreg otherwise
twisti@14626 68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
twisti@14626 69 address entry_point, // the entry point
twisti@14626 70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
twisti@14626 71 bool check_exceptions // whether to check for pending exceptions after return
twisti@14626 72 );
twisti@14626 73
twisti@14626 74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
twisti@14626 75 // The implementation is only non-empty for the InterpreterMacroAssembler,
twisti@14626 76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
twisti@14626 77 virtual void check_and_handle_popframe(Register java_thread);
twisti@14626 78 virtual void check_and_handle_earlyret(Register java_thread);
twisti@14626 79
twisti@14626 80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
twisti@14626 81
twisti@14626 82 // helpers for FPU flag access
twisti@14626 83 // tmp is a temporary register, if none is available use noreg
twisti@14626 84 void save_rax (Register tmp);
twisti@14626 85 void restore_rax(Register tmp);
twisti@14626 86
twisti@14626 87 public:
twisti@14626 88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
twisti@14626 89
twisti@14626 90 // Support for NULL-checks
twisti@14626 91 //
twisti@14626 92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
twisti@14626 93 // If the accessed location is M[reg + offset] and the offset is known, provide the
twisti@14626 94 // offset. No explicit code generation is needed if the offset is within a certain
twisti@14626 95 // range (0 <= offset <= page_size).
twisti@14626 96
twisti@14626 97 void null_check(Register reg, int offset = -1);
twisti@14626 98 static bool needs_explicit_null_check(intptr_t offset);
twisti@14626 99
twisti@14626 100 // Required platform-specific helpers for Label::patch_instructions.
twisti@14626 101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
twisti@14626 102 void pd_patch_instruction(address branch, address target) {
twisti@14626 103 unsigned char op = branch[0];
twisti@14626 104 assert(op == 0xE8 /* call */ ||
twisti@14626 105 op == 0xE9 /* jmp */ ||
twisti@14626 106 op == 0xEB /* short jmp */ ||
twisti@14626 107 (op & 0xF0) == 0x70 /* short jcc */ ||
kvn@23491 108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
kvn@23491 109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
twisti@14626 110 "Invalid opcode at patch point");
twisti@14626 111
twisti@14626 112 if (op == 0xEB || (op & 0xF0) == 0x70) {
twisti@14626 113 // short offset operators (jmp and jcc)
twisti@14626 114 char* disp = (char*) &branch[1];
twisti@14626 115 int imm8 = target - (address) &disp[1];
twisti@14626 116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
twisti@14626 117 *disp = imm8;
twisti@14626 118 } else {
kvn@23491 119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
twisti@14626 120 int imm32 = target - (address) &disp[1];
twisti@14626 121 *disp = imm32;
twisti@14626 122 }
twisti@14626 123 }
twisti@14626 124
twisti@14626 125 // The following 4 methods return the offset of the appropriate move instruction
twisti@14626 126
twisti@14626 127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
twisti@14626 128 int load_unsigned_byte(Register dst, Address src);
twisti@14626 129 int load_unsigned_short(Register dst, Address src);
twisti@14626 130
twisti@14626 131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
twisti@14626 132 int load_signed_byte(Register dst, Address src);
twisti@14626 133 int load_signed_short(Register dst, Address src);
twisti@14626 134
twisti@14626 135 // Support for sign-extension (hi:lo = extend_sign(lo))
twisti@14626 136 void extend_sign(Register hi, Register lo);
twisti@14626 137
twisti@14626 138 // Load and store values by size and signed-ness
twisti@14626 139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
twisti@14626 140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
twisti@14626 141
twisti@14626 142 // Support for inc/dec with optimal instruction selection depending on value
twisti@14626 143
twisti@14626 144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
twisti@14626 145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
twisti@14626 146
twisti@14626 147 void decrementl(Address dst, int value = 1);
twisti@14626 148 void decrementl(Register reg, int value = 1);
twisti@14626 149
twisti@14626 150 void decrementq(Register reg, int value = 1);
twisti@14626 151 void decrementq(Address dst, int value = 1);
twisti@14626 152
twisti@14626 153 void incrementl(Address dst, int value = 1);
twisti@14626 154 void incrementl(Register reg, int value = 1);
twisti@14626 155
twisti@14626 156 void incrementq(Register reg, int value = 1);
twisti@14626 157 void incrementq(Address dst, int value = 1);
twisti@14626 158
mcberg@38049 159 // special instructions for EVEX
mcberg@38049 160 void setvectmask(Register dst, Register src);
mcberg@38049 161 void restorevectmask();
mcberg@38049 162
twisti@14626 163 // Support optimal SSE move instructions.
twisti@14626 164 void movflt(XMMRegister dst, XMMRegister src) {
twisti@14626 165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
twisti@14626 166 else { movss (dst, src); return; }
twisti@14626 167 }
twisti@14626 168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
twisti@14626 169 void movflt(XMMRegister dst, AddressLiteral src);
twisti@14626 170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
twisti@14626 171
twisti@14626 172 void movdbl(XMMRegister dst, XMMRegister src) {
twisti@14626 173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
twisti@14626 174 else { movsd (dst, src); return; }
twisti@14626 175 }
twisti@14626 176
twisti@14626 177 void movdbl(XMMRegister dst, AddressLiteral src);
twisti@14626 178
twisti@14626 179 void movdbl(XMMRegister dst, Address src) {
twisti@14626 180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
twisti@14626 181 else { movlpd(dst, src); return; }
twisti@14626 182 }
twisti@14626 183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
twisti@14626 184
twisti@14626 185 void incrementl(AddressLiteral dst);
twisti@14626 186 void incrementl(ArrayAddress dst);
twisti@14626 187
kvn@23491 188 void incrementq(AddressLiteral dst);
kvn@23491 189
twisti@14626 190 // Alignment
twisti@14626 191 void align(int modulus);
shade@32203 192 void align(int modulus, int target);
twisti@14626 193
twisti@14626 194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
twisti@14626 195 void fat_nop();
twisti@14626 196
twisti@14626 197 // Stack frame creation/removal
twisti@14626 198 void enter();
twisti@14626 199 void leave();
twisti@14626 200
twisti@14626 201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
twisti@14626 202 // The pointer will be loaded into the thread register.
twisti@14626 203 void get_thread(Register thread);
twisti@14626 204
twisti@14626 205
twisti@14626 206 // Support for VM calls
twisti@14626 207 //
twisti@14626 208 // It is imperative that all calls into the VM are handled via the call_VM macros.
twisti@14626 209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
twisti@14626 210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
twisti@14626 211
twisti@14626 212
twisti@14626 213 void call_VM(Register oop_result,
twisti@14626 214 address entry_point,
twisti@14626 215 bool check_exceptions = true);
twisti@14626 216 void call_VM(Register oop_result,
twisti@14626 217 address entry_point,
twisti@14626 218 Register arg_1,
twisti@14626 219 bool check_exceptions = true);
twisti@14626 220 void call_VM(Register oop_result,
twisti@14626 221 address entry_point,
twisti@14626 222 Register arg_1, Register arg_2,
twisti@14626 223 bool check_exceptions = true);
twisti@14626 224 void call_VM(Register oop_result,
twisti@14626 225 address entry_point,
twisti@14626 226 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 227 bool check_exceptions = true);
twisti@14626 228
twisti@14626 229 // Overloadings with last_Java_sp
twisti@14626 230 void call_VM(Register oop_result,
twisti@14626 231 Register last_java_sp,
twisti@14626 232 address entry_point,
twisti@14626 233 int number_of_arguments = 0,
twisti@14626 234 bool check_exceptions = true);
twisti@14626 235 void call_VM(Register oop_result,
twisti@14626 236 Register last_java_sp,
twisti@14626 237 address entry_point,
twisti@14626 238 Register arg_1, bool
twisti@14626 239 check_exceptions = true);
twisti@14626 240 void call_VM(Register oop_result,
twisti@14626 241 Register last_java_sp,
twisti@14626 242 address entry_point,
twisti@14626 243 Register arg_1, Register arg_2,
twisti@14626 244 bool check_exceptions = true);
twisti@14626 245 void call_VM(Register oop_result,
twisti@14626 246 Register last_java_sp,
twisti@14626 247 address entry_point,
twisti@14626 248 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 249 bool check_exceptions = true);
twisti@14626 250
twisti@14626 251 void get_vm_result (Register oop_result, Register thread);
twisti@14626 252 void get_vm_result_2(Register metadata_result, Register thread);
twisti@14626 253
twisti@14626 254 // These always tightly bind to MacroAssembler::call_VM_base
twisti@14626 255 // bypassing the virtual implementation
twisti@14626 256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
twisti@14626 257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
twisti@14626 258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
twisti@14626 259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
twisti@14626 260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
twisti@14626 261
vdeshpande@38699 262 void call_VM_leaf0(address entry_point);
twisti@14626 263 void call_VM_leaf(address entry_point,
twisti@14626 264 int number_of_arguments = 0);
twisti@14626 265 void call_VM_leaf(address entry_point,
twisti@14626 266 Register arg_1);
twisti@14626 267 void call_VM_leaf(address entry_point,
twisti@14626 268 Register arg_1, Register arg_2);
twisti@14626 269 void call_VM_leaf(address entry_point,
twisti@14626 270 Register arg_1, Register arg_2, Register arg_3);
twisti@14626 271
twisti@14626 272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
twisti@14626 273 // bypassing the virtual implementation
twisti@14626 274 void super_call_VM_leaf(address entry_point);
twisti@14626 275 void super_call_VM_leaf(address entry_point, Register arg_1);
twisti@14626 276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
twisti@14626 277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
twisti@14626 278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
twisti@14626 279
twisti@14626 280 // last Java Frame (fills frame anchor)
twisti@14626 281 void set_last_Java_frame(Register thread,
twisti@14626 282 Register last_java_sp,
twisti@14626 283 Register last_java_fp,
twisti@14626 284 address last_java_pc);
twisti@14626 285
twisti@14626 286 // thread in the default location (r15_thread on 64bit)
twisti@14626 287 void set_last_Java_frame(Register last_java_sp,
twisti@14626 288 Register last_java_fp,
twisti@14626 289 address last_java_pc);
twisti@14626 290
dlong@40644 291 void reset_last_Java_frame(Register thread, bool clear_fp);
twisti@14626 292
twisti@14626 293 // thread in the default location (r15_thread on 64bit)
dlong@40644 294 void reset_last_Java_frame(bool clear_fp);
twisti@14626 295
twisti@14626 296 // Stores
twisti@14626 297 void store_check(Register obj); // store check for obj - register is destroyed afterwards
twisti@14626 298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
twisti@14626 299
jprovino@15482 300 #if INCLUDE_ALL_GCS
twisti@14626 301
twisti@14626 302 void g1_write_barrier_pre(Register obj,
twisti@14626 303 Register pre_val,
twisti@14626 304 Register thread,
twisti@14626 305 Register tmp,
twisti@14626 306 bool tosca_live,
twisti@14626 307 bool expand_call);
twisti@14626 308
twisti@14626 309 void g1_write_barrier_post(Register store_addr,
twisti@14626 310 Register new_val,
twisti@14626 311 Register thread,
twisti@14626 312 Register tmp,
twisti@14626 313 Register tmp2);
twisti@14626 314
jprovino@15482 315 #endif // INCLUDE_ALL_GCS
twisti@14626 316
twisti@14626 317 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
twisti@14626 318 void c2bool(Register x);
twisti@14626 319
twisti@14626 320 // C++ bool manipulation
twisti@14626 321
twisti@14626 322 void movbool(Register dst, Address src);
twisti@14626 323 void movbool(Address dst, bool boolconst);
twisti@14626 324 void movbool(Address dst, Register src);
twisti@14626 325 void testbool(Register dst);
twisti@14626 326
coleenp@38074 327 void load_mirror(Register mirror, Register method);
coleenp@38074 328
twisti@14626 329 // oop manipulations
twisti@14626 330 void load_klass(Register dst, Register src);
twisti@14626 331 void store_klass(Register dst, Register src);
twisti@14626 332
twisti@14626 333 void load_heap_oop(Register dst, Address src);
twisti@14626 334 void load_heap_oop_not_null(Register dst, Address src);
twisti@14626 335 void store_heap_oop(Address dst, Register src);
twisti@14626 336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
twisti@14626 337
twisti@14626 338 // Used for storing NULL. All other oop constants should be
twisti@14626 339 // stored using routines that take a jobject.
twisti@14626 340 void store_heap_oop_null(Address dst);
twisti@14626 341
twisti@14626 342 void load_prototype_header(Register dst, Register src);
twisti@14626 343
twisti@14626 344 #ifdef _LP64
twisti@14626 345 void store_klass_gap(Register dst, Register src);
twisti@14626 346
twisti@14626 347 // This dummy is to prevent a call to store_heap_oop from
twisti@14626 348 // converting a zero (like NULL) into a Register by giving
twisti@14626 349 // the compiler two choices it can't resolve
twisti@14626 350
twisti@14626 351 void store_heap_oop(Address dst, void* dummy);
twisti@14626 352
twisti@14626 353 void encode_heap_oop(Register r);
twisti@14626 354 void decode_heap_oop(Register r);
twisti@14626 355 void encode_heap_oop_not_null(Register r);
twisti@14626 356 void decode_heap_oop_not_null(Register r);
twisti@14626 357 void encode_heap_oop_not_null(Register dst, Register src);
twisti@14626 358 void decode_heap_oop_not_null(Register dst, Register src);
twisti@14626 359
twisti@14626 360 void set_narrow_oop(Register dst, jobject obj);
twisti@14626 361 void set_narrow_oop(Address dst, jobject obj);
twisti@14626 362 void cmp_narrow_oop(Register dst, jobject obj);
twisti@14626 363 void cmp_narrow_oop(Address dst, jobject obj);
twisti@14626 364
twisti@14626 365 void encode_klass_not_null(Register r);
twisti@14626 366 void decode_klass_not_null(Register r);
twisti@14626 367 void encode_klass_not_null(Register dst, Register src);
twisti@14626 368 void decode_klass_not_null(Register dst, Register src);
twisti@14626 369 void set_narrow_klass(Register dst, Klass* k);
twisti@14626 370 void set_narrow_klass(Address dst, Klass* k);
twisti@14626 371 void cmp_narrow_klass(Register dst, Klass* k);
twisti@14626 372 void cmp_narrow_klass(Address dst, Klass* k);
twisti@14626 373
hseigel@19319 374 // Returns the byte size of the instructions generated by decode_klass_not_null()
hseigel@19319 375 // when compressed klass pointers are being used.
hseigel@19319 376 static int instr_size_for_decode_klass_not_null();
hseigel@19319 377
twisti@14626 378 // if heap base register is used - reinit it with the correct value
twisti@14626 379 void reinit_heapbase();
twisti@14626 380
twisti@14626 381 DEBUG_ONLY(void verify_heapbase(const char* msg);)
twisti@14626 382
twisti@14626 383 #endif // _LP64
twisti@14626 384
twisti@14626 385 // Int division/remainder for Java
twisti@14626 386 // (as idivl, but checks for special case as described in JVM spec.)
twisti@14626 387 // returns idivl instruction offset for implicit exception handling
twisti@14626 388 int corrected_idivl(Register reg);
twisti@14626 389
twisti@14626 390 // Long division/remainder for Java
twisti@14626 391 // (as idivq, but checks for special case as described in JVM spec.)
twisti@14626 392 // returns idivq instruction offset for implicit exception handling
twisti@14626 393 int corrected_idivq(Register reg);
twisti@14626 394
twisti@14626 395 void int3();
twisti@14626 396
twisti@14626 397 // Long operation macros for a 32bit cpu
twisti@14626 398 // Long negation for Java
twisti@14626 399 void lneg(Register hi, Register lo);
twisti@14626 400
twisti@14626 401 // Long multiplication for Java
twisti@14626 402 // (destroys contents of eax, ebx, ecx and edx)
twisti@14626 403 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
twisti@14626 404
twisti@14626 405 // Long shifts for Java
twisti@14626 406 // (semantics as described in JVM spec.)
twisti@14626 407 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
twisti@14626 408 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
twisti@14626 409
twisti@14626 410 // Long compare for Java
twisti@14626 411 // (semantics as described in JVM spec.)
twisti@14626 412 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
twisti@14626 413
twisti@14626 414
twisti@14626 415 // misc
twisti@14626 416
twisti@14626 417 // Sign extension
twisti@14626 418 void sign_extend_short(Register reg);
twisti@14626 419 void sign_extend_byte(Register reg);
twisti@14626 420
twisti@14626 421 // Division by power of 2, rounding towards 0
twisti@14626 422 void division_with_shift(Register reg, int shift_value);
twisti@14626 423
twisti@14626 424 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
twisti@14626 425 //
twisti@14626 426 // CF (corresponds to C0) if x < y
twisti@14626 427 // PF (corresponds to C2) if unordered
twisti@14626 428 // ZF (corresponds to C3) if x = y
twisti@14626 429 //
twisti@14626 430 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 431 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
twisti@14626 432 void fcmp(Register tmp);
twisti@14626 433 // Variant of the above which allows y to be further down the stack
twisti@14626 434 // and which only pops x and y if specified. If pop_right is
twisti@14626 435 // specified then pop_left must also be specified.
twisti@14626 436 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
twisti@14626 437
twisti@14626 438 // Floating-point comparison for Java
twisti@14626 439 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
twisti@14626 440 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 441 // (semantics as described in JVM spec.)
twisti@14626 442 void fcmp2int(Register dst, bool unordered_is_less);
twisti@14626 443 // Variant of the above which allows y to be further down the stack
twisti@14626 444 // and which only pops x and y if specified. If pop_right is
twisti@14626 445 // specified then pop_left must also be specified.
twisti@14626 446 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
twisti@14626 447
twisti@14626 448 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
twisti@14626 449 // tmp is a temporary register, if none is available use noreg
twisti@14626 450 void fremr(Register tmp);
twisti@14626 451
vdeshpande@41323 452 // dst = c = a * b + c
vdeshpande@41323 453 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
vdeshpande@41323 454 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
vdeshpande@41323 455
twisti@14626 456
twisti@14626 457 // same as fcmp2int, but using SSE2
twisti@14626 458 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 459 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 460
twisti@14626 461 // branch to L if FPU flag C2 is set/not set
twisti@14626 462 // tmp is a temporary register, if none is available use noreg
twisti@14626 463 void jC2 (Register tmp, Label& L);
twisti@14626 464 void jnC2(Register tmp, Label& L);
twisti@14626 465
twisti@14626 466 // Pop ST (ffree & fincstp combined)
twisti@14626 467 void fpop();
twisti@14626 468
zmajo@32391 469 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
zmajo@32391 470 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
zmajo@32391 471 void load_float(Address src);
zmajo@32391 472
zmajo@32391 473 // Store float value to 'address'. If UseSSE >= 1, the value is stored
zmajo@32391 474 // from register xmm0. Otherwise, the value is stored from the FPU stack.
zmajo@32391 475 void store_float(Address dst);
zmajo@32391 476
zmajo@32391 477 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
zmajo@32391 478 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
zmajo@32391 479 void load_double(Address src);
zmajo@32391 480
zmajo@32391 481 // Store double value to 'address'. If UseSSE >= 2, the value is stored
zmajo@32391 482 // from register xmm0. Otherwise, the value is stored from the FPU stack.
zmajo@32391 483 void store_double(Address dst);
zmajo@32391 484
twisti@14626 485 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
twisti@14626 486 void push_fTOS();
twisti@14626 487
twisti@14626 488 // pops double TOS element from CPU stack and pushes on FPU stack
twisti@14626 489 void pop_fTOS();
twisti@14626 490
twisti@14626 491 void empty_FPU_stack();
twisti@14626 492
twisti@14626 493 void push_IU_state();
twisti@14626 494 void pop_IU_state();
twisti@14626 495
twisti@14626 496 void push_FPU_state();
twisti@14626 497 void pop_FPU_state();
twisti@14626 498
twisti@14626 499 void push_CPU_state();
twisti@14626 500 void pop_CPU_state();
twisti@14626 501
twisti@14626 502 // Round up to a power of two
twisti@14626 503 void round_to(Register reg, int modulus);
twisti@14626 504
twisti@14626 505 // Callee saved registers handling
twisti@14626 506 void push_callee_saved_registers();
twisti@14626 507 void pop_callee_saved_registers();
twisti@14626 508
twisti@14626 509 // allocation
twisti@14626 510 void eden_allocate(
twisti@14626 511 Register obj, // result: pointer to object after successful allocation
twisti@14626 512 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 513 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 514 Register t1, // temp register
twisti@14626 515 Label& slow_case // continuation point if fast allocation fails
twisti@14626 516 );
twisti@14626 517 void tlab_allocate(
twisti@14626 518 Register obj, // result: pointer to object after successful allocation
twisti@14626 519 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 520 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 521 Register t1, // temp register
twisti@14626 522 Register t2, // temp register
twisti@14626 523 Label& slow_case // continuation point if fast allocation fails
twisti@14626 524 );
twisti@14626 525 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
zmajo@35548 526 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
zmajo@35548 527
twisti@14626 528 void incr_allocated_bytes(Register thread,
twisti@14626 529 Register var_size_in_bytes, int con_size_in_bytes,
twisti@14626 530 Register t1 = noreg);
twisti@14626 531
twisti@14626 532 // interface method calling
twisti@14626 533 void lookup_interface_method(Register recv_klass,
twisti@14626 534 Register intf_klass,
twisti@14626 535 RegisterOrConstant itable_index,
twisti@14626 536 Register method_result,
twisti@14626 537 Register scan_temp,
twisti@14626 538 Label& no_such_interface);
twisti@14626 539
twisti@14626 540 // virtual method calling
twisti@14626 541 void lookup_virtual_method(Register recv_klass,
twisti@14626 542 RegisterOrConstant vtable_index,
twisti@14626 543 Register method_result);
twisti@14626 544
twisti@14626 545 // Test sub_klass against super_klass, with fast and slow paths.
twisti@14626 546
twisti@14626 547 // The fast path produces a tri-state answer: yes / no / maybe-slow.
twisti@14626 548 // One of the three labels can be NULL, meaning take the fall-through.
twisti@14626 549 // If super_check_offset is -1, the value is loaded up from super_klass.
twisti@14626 550 // No registers are killed, except temp_reg.
twisti@14626 551 void check_klass_subtype_fast_path(Register sub_klass,
twisti@14626 552 Register super_klass,
twisti@14626 553 Register temp_reg,
twisti@14626 554 Label* L_success,
twisti@14626 555 Label* L_failure,
twisti@14626 556 Label* L_slow_path,
twisti@14626 557 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
twisti@14626 558
twisti@14626 559 // The rest of the type check; must be wired to a corresponding fast path.
twisti@14626 560 // It does not repeat the fast path logic, so don't use it standalone.
twisti@14626 561 // The temp_reg and temp2_reg can be noreg, if no temps are available.
twisti@14626 562 // Updates the sub's secondary super cache as necessary.
twisti@14626 563 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
twisti@14626 564 void check_klass_subtype_slow_path(Register sub_klass,
twisti@14626 565 Register super_klass,
twisti@14626 566 Register temp_reg,
twisti@14626 567 Register temp2_reg,
twisti@14626 568 Label* L_success,
twisti@14626 569 Label* L_failure,
twisti@14626 570 bool set_cond_codes = false);
twisti@14626 571
twisti@14626 572 // Simplified, combined version, good for typical uses.
twisti@14626 573 // Falls through on failure.
twisti@14626 574 void check_klass_subtype(Register sub_klass,
twisti@14626 575 Register super_klass,
twisti@14626 576 Register temp_reg,
twisti@14626 577 Label& L_success);
twisti@14626 578
twisti@14626 579 // method handles (JSR 292)
twisti@14626 580 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
twisti@14626 581
twisti@14626 582 //----
twisti@14626 583 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
twisti@14626 584
twisti@14626 585 // Debugging
twisti@14626 586
twisti@14626 587 // only if +VerifyOops
twisti@14626 588 // TODO: Make these macros with file and line like sparc version!
twisti@14626 589 void verify_oop(Register reg, const char* s = "broken oop");
twisti@14626 590 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
twisti@14626 591
twisti@14626 592 // TODO: verify method and klass metadata (compare against vptr?)
twisti@14626 593 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
twisti@14626 594 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
twisti@14626 595
twisti@14626 596 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
twisti@14626 597 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
twisti@14626 598
twisti@14626 599 // only if +VerifyFPU
twisti@14626 600 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
twisti@14626 601
kvn@16624 602 // Verify or restore cpu control state after JNI call
kvn@16624 603 void restore_cpu_control_state_after_jni();
kvn@16624 604
twisti@14626 605 // prints msg, dumps registers and stops execution
twisti@14626 606 void stop(const char* msg);
twisti@14626 607
twisti@14626 608 // prints msg and continues
twisti@14626 609 void warn(const char* msg);
twisti@14626 610
twisti@14626 611 // dumps registers and other state
twisti@14626 612 void print_state();
twisti@14626 613
twisti@14626 614 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
twisti@14626 615 static void debug64(char* msg, int64_t pc, int64_t regs[]);
twisti@14626 616 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
twisti@14626 617 static void print_state64(int64_t pc, int64_t regs[]);
twisti@14626 618
twisti@14626 619 void os_breakpoint();
twisti@14626 620
twisti@14626 621 void untested() { stop("untested"); }
twisti@14626 622
twisti@14626 623 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
twisti@14626 624
twisti@14626 625 void should_not_reach_here() { stop("should not reach here"); }
twisti@14626 626
twisti@14626 627 void print_CPU_state();
twisti@14626 628
twisti@14626 629 // Stack overflow checking
twisti@14626 630 void bang_stack_with_offset(int offset) {
twisti@14626 631 // stack grows down, caller passes positive offset
twisti@14626 632 assert(offset > 0, "must bang with negative offset");
twisti@14626 633 movl(Address(rsp, (-offset)), rax);
twisti@14626 634 }
twisti@14626 635
twisti@14626 636 // Writes to stack successive pages until offset reached to check for
twisti@14626 637 // stack overflow + shadow pages. Also, clobbers tmp
twisti@14626 638 void bang_stack_size(Register size, Register tmp);
twisti@14626 639
fparain@35071 640 // Check for reserved stack access in method being exited (for JIT)
fparain@35071 641 void reserved_stack_check();
fparain@35071 642
twisti@14626 643 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
twisti@14626 644 Register tmp,
twisti@14626 645 int offset);
twisti@14626 646
twisti@14626 647 // Support for serializing memory accesses between threads
twisti@14626 648 void serialize_memory(Register thread, Register tmp);
twisti@14626 649
twisti@14626 650 void verify_tlab();
twisti@14626 651
twisti@14626 652 // Biased locking support
twisti@14626 653 // lock_reg and obj_reg must be loaded up with the appropriate values.
twisti@14626 654 // swap_reg must be rax, and is killed.
twisti@14626 655 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
twisti@14626 656 // be killed; if not supplied, push/pop will be used internally to
twisti@14626 657 // allocate a temporary (inefficient, avoid if possible).
twisti@14626 658 // Optional slow case is for implementations (interpreter and C1) which branch to
twisti@14626 659 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
twisti@14626 660 // Returns offset of first potentially-faulting instruction for null
twisti@14626 661 // check info (currently consumed only by C1). If
twisti@14626 662 // swap_reg_contains_mark is true then returns -1 as it is assumed
twisti@14626 663 // the calling code has already passed any potential faults.
twisti@14626 664 int biased_locking_enter(Register lock_reg, Register obj_reg,
twisti@14626 665 Register swap_reg, Register tmp_reg,
twisti@14626 666 bool swap_reg_contains_mark,
twisti@14626 667 Label& done, Label* slow_case = NULL,
twisti@14626 668 BiasedLockingCounters* counters = NULL);
twisti@14626 669 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
kvn@22910 670 #ifdef COMPILER2
kvn@22910 671 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
kvn@22910 672 // See full desription in macroAssembler_x86.cpp.
kvn@23491 673 void fast_lock(Register obj, Register box, Register tmp,
kvn@23491 674 Register scr, Register cx1, Register cx2,
kvn@23491 675 BiasedLockingCounters* counters,
kvn@23491 676 RTMLockingCounters* rtm_counters,
kvn@23491 677 RTMLockingCounters* stack_rtm_counters,
kvn@23491 678 Metadata* method_data,
kvn@23491 679 bool use_rtm, bool profile_rtm);
kvn@23491 680 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
kvn@23491 681 #if INCLUDE_RTM_OPT
kvn@23491 682 void rtm_counters_update(Register abort_status, Register rtm_counters);
kvn@23491 683 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
kvn@23491 684 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
kvn@23491 685 RTMLockingCounters* rtm_counters,
kvn@23491 686 Metadata* method_data);
kvn@23491 687 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
kvn@23491 688 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
kvn@23491 689 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
kvn@23491 690 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
kvn@23491 691 void rtm_stack_locking(Register obj, Register tmp, Register scr,
kvn@23491 692 Register retry_on_abort_count,
kvn@23491 693 RTMLockingCounters* stack_rtm_counters,
kvn@23491 694 Metadata* method_data, bool profile_rtm,
kvn@23491 695 Label& DONE_LABEL, Label& IsInflated);
kvn@23491 696 void rtm_inflated_locking(Register obj, Register box, Register tmp,
kvn@23491 697 Register scr, Register retry_on_busy_count,
kvn@23491 698 Register retry_on_abort_count,
kvn@23491 699 RTMLockingCounters* rtm_counters,
kvn@23491 700 Metadata* method_data, bool profile_rtm,
kvn@23491 701 Label& DONE_LABEL);
kvn@23491 702 #endif
kvn@22910 703 #endif
twisti@14626 704
twisti@14626 705 Condition negate_condition(Condition cond);
twisti@14626 706
twisti@14626 707 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
twisti@14626 708 // operands. In general the names are modified to avoid hiding the instruction in Assembler
twisti@14626 709 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
twisti@14626 710 // here in MacroAssembler. The major exception to this rule is call
twisti@14626 711
twisti@14626 712 // Arithmetics
twisti@14626 713
twisti@14626 714
twisti@14626 715 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
twisti@14626 716 void addptr(Address dst, Register src);
twisti@14626 717
twisti@14626 718 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
twisti@14626 719 void addptr(Register dst, int32_t src);
twisti@14626 720 void addptr(Register dst, Register src);
twisti@14626 721 void addptr(Register dst, RegisterOrConstant src) {
twisti@14626 722 if (src.is_constant()) addptr(dst, (int) src.as_constant());
twisti@14626 723 else addptr(dst, src.as_register());
twisti@14626 724 }
twisti@14626 725
twisti@14626 726 void andptr(Register dst, int32_t src);
twisti@14626 727 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
twisti@14626 728
twisti@14626 729 void cmp8(AddressLiteral src1, int imm);
twisti@14626 730
twisti@14626 731 // renamed to drag out the casting of address to int32_t/intptr_t
twisti@14626 732 void cmp32(Register src1, int32_t imm);
twisti@14626 733
twisti@14626 734 void cmp32(AddressLiteral src1, int32_t imm);
twisti@14626 735 // compare reg - mem, or reg - &mem
twisti@14626 736 void cmp32(Register src1, AddressLiteral src2);
twisti@14626 737
twisti@14626 738 void cmp32(Register src1, Address src2);
twisti@14626 739
twisti@14626 740 #ifndef _LP64
twisti@14626 741 void cmpklass(Address dst, Metadata* obj);
twisti@14626 742 void cmpklass(Register dst, Metadata* obj);
twisti@14626 743 void cmpoop(Address dst, jobject obj);
twisti@14626 744 void cmpoop(Register dst, jobject obj);
twisti@14626 745 #endif // _LP64
twisti@14626 746
twisti@14626 747 // NOTE src2 must be the lval. This is NOT an mem-mem compare
twisti@14626 748 void cmpptr(Address src1, AddressLiteral src2);
twisti@14626 749
twisti@14626 750 void cmpptr(Register src1, AddressLiteral src2);
twisti@14626 751
twisti@14626 752 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 753 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 754 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 755
twisti@14626 756 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 757 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 758
twisti@14626 759 // cmp64 to avoild hiding cmpq
twisti@14626 760 void cmp64(Register src1, AddressLiteral src);
twisti@14626 761
twisti@14626 762 void cmpxchgptr(Register reg, Address adr);
twisti@14626 763
twisti@14626 764 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
twisti@14626 765
twisti@14626 766
twisti@14626 767 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
kvn@23491 768 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
twisti@14626 769
twisti@14626 770
twisti@14626 771 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
twisti@14626 772
twisti@14626 773 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
twisti@14626 774
twisti@14626 775 void shlptr(Register dst, int32_t shift);
twisti@14626 776 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
twisti@14626 777
twisti@14626 778 void shrptr(Register dst, int32_t shift);
twisti@14626 779 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
twisti@14626 780
twisti@14626 781 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
twisti@14626 782 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
twisti@14626 783
twisti@14626 784 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 785
twisti@14626 786 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 787 void subptr(Register dst, int32_t src);
twisti@14626 788 // Force generation of a 4 byte immediate value even if it fits into 8bit
twisti@14626 789 void subptr_imm32(Register dst, int32_t src);
twisti@14626 790 void subptr(Register dst, Register src);
twisti@14626 791 void subptr(Register dst, RegisterOrConstant src) {
twisti@14626 792 if (src.is_constant()) subptr(dst, (int) src.as_constant());
twisti@14626 793 else subptr(dst, src.as_register());
twisti@14626 794 }
twisti@14626 795
twisti@14626 796 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 797 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 798
twisti@14626 799 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 800 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 801
twisti@14626 802 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
twisti@14626 803
twisti@14626 804
twisti@14626 805
twisti@14626 806 // Helper functions for statistics gathering.
twisti@14626 807 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
twisti@14626 808 void cond_inc32(Condition cond, AddressLiteral counter_addr);
twisti@14626 809 // Unconditional atomic increment.
kvn@23491 810 void atomic_incl(Address counter_addr);
kvn@23491 811 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 812 #ifdef _LP64
kvn@23491 813 void atomic_incq(Address counter_addr);
kvn@23491 814 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 815 #endif
kvn@23491 816 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
kvn@23491 817 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
twisti@14626 818
twisti@14626 819 void lea(Register dst, AddressLiteral adr);
twisti@14626 820 void lea(Address dst, AddressLiteral adr);
twisti@14626 821 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
twisti@14626 822
twisti@14626 823 void leal32(Register dst, Address src) { leal(dst, src); }
twisti@14626 824
twisti@14626 825 // Import other testl() methods from the parent class or else
twisti@14626 826 // they will be hidden by the following overriding declaration.
twisti@14626 827 using Assembler::testl;
twisti@14626 828 void testl(Register dst, AddressLiteral src);
twisti@14626 829
twisti@14626 830 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 831 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 832 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
roland@20702 833 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
twisti@14626 834
twisti@14626 835 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
twisti@14626 836 void testptr(Register src1, Register src2);
twisti@14626 837
twisti@14626 838 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 839 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 840
twisti@14626 841 // Calls
twisti@14626 842
twisti@14626 843 void call(Label& L, relocInfo::relocType rtype);
twisti@14626 844 void call(Register entry);
twisti@14626 845
psandoz@38238 846 // NOTE: this call transfers to the effective address of entry NOT
twisti@14626 847 // the address contained by entry. This is because this is more natural
twisti@14626 848 // for jumps/calls.
twisti@14626 849 void call(AddressLiteral entry);
twisti@14626 850
twisti@14626 851 // Emit the CompiledIC call idiom
vlivanov@35086 852 void ic_call(address entry, jint method_index = 0);
twisti@14626 853
twisti@14626 854 // Jumps
twisti@14626 855
twisti@14626 856 // NOTE: these jumps tranfer to the effective address of dst NOT
twisti@14626 857 // the address contained by dst. This is because this is more natural
twisti@14626 858 // for jumps/calls.
twisti@14626 859 void jump(AddressLiteral dst);
twisti@14626 860 void jump_cc(Condition cc, AddressLiteral dst);
twisti@14626 861
twisti@14626 862 // 32bit can do a case table jump in one instruction but we no longer allow the base
twisti@14626 863 // to be installed in the Address class. This jump will tranfers to the address
twisti@14626 864 // contained in the location described by entry (not the address of entry)
twisti@14626 865 void jump(ArrayAddress entry);
twisti@14626 866
twisti@14626 867 // Floating
twisti@14626 868
twisti@14626 869 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
twisti@14626 870 void andpd(XMMRegister dst, AddressLiteral src);
vdeshpande@35540 871 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
twisti@14626 872
twisti@14626 873 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
twisti@14626 874 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
twisti@14626 875 void andps(XMMRegister dst, AddressLiteral src);
twisti@14626 876
twisti@14626 877 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
twisti@14626 878 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
twisti@14626 879 void comiss(XMMRegister dst, AddressLiteral src);
twisti@14626 880
twisti@14626 881 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
twisti@14626 882 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
twisti@14626 883 void comisd(XMMRegister dst, AddressLiteral src);
twisti@14626 884
twisti@14626 885 void fadd_s(Address src) { Assembler::fadd_s(src); }
twisti@14626 886 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
twisti@14626 887
twisti@14626 888 void fldcw(Address src) { Assembler::fldcw(src); }
twisti@14626 889 void fldcw(AddressLiteral src);
twisti@14626 890
twisti@14626 891 void fld_s(int index) { Assembler::fld_s(index); }
twisti@14626 892 void fld_s(Address src) { Assembler::fld_s(src); }
twisti@14626 893 void fld_s(AddressLiteral src);
twisti@14626 894
twisti@14626 895 void fld_d(Address src) { Assembler::fld_d(src); }
twisti@14626 896 void fld_d(AddressLiteral src);
twisti@14626 897
twisti@14626 898 void fld_x(Address src) { Assembler::fld_x(src); }
twisti@14626 899 void fld_x(AddressLiteral src);
twisti@14626 900
twisti@14626 901 void fmul_s(Address src) { Assembler::fmul_s(src); }
twisti@14626 902 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
twisti@14626 903
twisti@14626 904 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
twisti@14626 905 void ldmxcsr(AddressLiteral src);
twisti@14626 906
jcivlin@38135 907 #ifdef _LP64
jcivlin@38135 908 private:
jcivlin@38135 909 void sha256_AVX2_one_round_compute(
jcivlin@38135 910 Register reg_old_h,
jcivlin@38135 911 Register reg_a,
jcivlin@38135 912 Register reg_b,
jcivlin@38135 913 Register reg_c,
jcivlin@38135 914 Register reg_d,
jcivlin@38135 915 Register reg_e,
jcivlin@38135 916 Register reg_f,
jcivlin@38135 917 Register reg_g,
jcivlin@38135 918 Register reg_h,
jcivlin@38135 919 int iter);
jcivlin@38135 920 void sha256_AVX2_four_rounds_compute_first(int start);
jcivlin@38135 921 void sha256_AVX2_four_rounds_compute_last(int start);
jcivlin@38135 922 void sha256_AVX2_one_round_and_sched(
jcivlin@38135 923 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
jcivlin@38135 924 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
jcivlin@38135 925 XMMRegister xmm_2, /* ymm6 */
jcivlin@38135 926 XMMRegister xmm_3, /* ymm7 */
jcivlin@38135 927 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
jcivlin@38135 928 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
jcivlin@38135 929 Register reg_c, /* edi */
jcivlin@38135 930 Register reg_d, /* esi */
jcivlin@38135 931 Register reg_e, /* r8d */
jcivlin@38135 932 Register reg_f, /* r9d */
jcivlin@38135 933 Register reg_g, /* r10d */
jcivlin@38135 934 Register reg_h, /* r11d */
jcivlin@38135 935 int iter);
jcivlin@38135 936
jcivlin@38135 937 void addm(int disp, Register r1, Register r2);
jcivlin@38135 938
jcivlin@38135 939 public:
jcivlin@38135 940 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
jcivlin@38135 941 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
jcivlin@38135 942 Register buf, Register state, Register ofs, Register limit, Register rsp,
jcivlin@38135 943 bool multi_block, XMMRegister shuf_mask);
jcivlin@38135 944 #endif
jcivlin@38135 945
vdeshpande@36555 946 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
vdeshpande@36555 947 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
vdeshpande@36555 948 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 949 bool multi_block);
vdeshpande@36555 950
vdeshpande@36555 951 #ifdef _LP64
vdeshpande@36555 952 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
vdeshpande@36555 953 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
vdeshpande@36555 954 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 955 bool multi_block, XMMRegister shuf_mask);
vdeshpande@36555 956 #else
vdeshpande@36555 957 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
vdeshpande@36555 958 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
vdeshpande@36555 959 Register buf, Register state, Register ofs, Register limit, Register rsp,
vdeshpande@36555 960 bool multi_block);
vdeshpande@36555 961 #endif
vdeshpande@36555 962
iveresov@33089 963 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
iveresov@33089 964 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
iveresov@33089 965 Register rax, Register rcx, Register rdx, Register tmp);
iveresov@33465 966
vdeshpande@36555 967 #ifdef _LP64
iveresov@33465 968 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
iveresov@33465 969 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 970 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
vdeshpande@35540 971
vdeshpande@38018 972 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@38018 973 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@38018 974 Register rax, Register rcx, Register rdx, Register r11);
vdeshpande@38018 975
kvn@35146 976 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
kvn@35146 977 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
vdeshpande@36555 978 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
iveresov@33465 979
vdeshpande@35540 980 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@35540 981 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 982 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
vdeshpande@36555 983 Register tmp3, Register tmp4);
vdeshpande@35540 984
vdeshpande@35540 985 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@35540 986 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 987 Register rax, Register rcx, Register rdx, Register tmp1,
vdeshpande@36555 988 Register tmp2, Register tmp3, Register tmp4);
vdeshpande@38018 989 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@38018 990 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@38018 991 Register rax, Register rcx, Register rdx, Register tmp1,
vdeshpande@38018 992 Register tmp2, Register tmp3, Register tmp4);
vdeshpande@36555 993 #else
vdeshpande@36555 994 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 995 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 996 Register rax, Register rcx, Register rdx, Register tmp1);
vdeshpande@35540 997
vdeshpande@38018 998 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@38018 999 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@38018 1000 Register rax, Register rcx, Register rdx, Register tmp);
vdeshpande@38018 1001
vdeshpande@36555 1002 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
vdeshpande@36555 1003 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
vdeshpande@36555 1004 Register rdx, Register tmp);
vdeshpande@36555 1005
vdeshpande@36555 1006 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 1007 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 1008 Register rax, Register rbx, Register rdx);
vdeshpande@36555 1009
vdeshpande@36555 1010 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@36555 1011 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@36555 1012 Register rax, Register rcx, Register rdx, Register tmp);
vdeshpande@36555 1013
vdeshpande@35540 1014 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
vdeshpande@35540 1015 Register edx, Register ebx, Register esi, Register edi,
vdeshpande@35540 1016 Register ebp, Register esp);
vdeshpande@36555 1017
vdeshpande@35540 1018 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
vdeshpande@35540 1019 Register esi, Register edi, Register ebp, Register esp);
vdeshpande@38018 1020
vdeshpande@38018 1021 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
vdeshpande@38018 1022 Register edx, Register ebx, Register esi, Register edi,
vdeshpande@38018 1023 Register ebp, Register esp);
vdeshpande@38018 1024
vdeshpande@38018 1025 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
vdeshpande@38018 1026 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
vdeshpande@38018 1027 Register rax, Register rcx, Register rdx, Register tmp);
vdeshpande@35540 1028 #endif
vdeshpande@35540 1029
twisti@14626 1030 void increase_precision();
twisti@14626 1031 void restore_precision();
twisti@14626 1032
twisti@14626 1033 private:
twisti@14626 1034
twisti@14626 1035 // these are private because users should be doing movflt/movdbl
twisti@14626 1036
twisti@14626 1037 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 1038 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 1039 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
twisti@14626 1040 void movss(XMMRegister dst, AddressLiteral src);
twisti@14626 1041
twisti@14626 1042 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
twisti@14626 1043 void movlpd(XMMRegister dst, AddressLiteral src);
twisti@14626 1044
twisti@14626 1045 public:
twisti@14626 1046
twisti@14626 1047 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
twisti@14626 1048 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
twisti@14626 1049 void addsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1050
twisti@14626 1051 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
twisti@14626 1052 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
twisti@14626 1053 void addss(XMMRegister dst, AddressLiteral src);
twisti@14626 1054
vdeshpande@35540 1055 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
vdeshpande@35540 1056 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
vdeshpande@35540 1057 void addpd(XMMRegister dst, AddressLiteral src);
vdeshpande@35540 1058
twisti@14626 1059 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
twisti@14626 1060 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
twisti@14626 1061 void divsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1062
twisti@14626 1063 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
twisti@14626 1064 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
twisti@14626 1065 void divss(XMMRegister dst, AddressLiteral src);
twisti@14626 1066
twisti@14626 1067 // Move Unaligned Double Quadword
iveresov@34162 1068 void movdqu(Address dst, XMMRegister src);
iveresov@34162 1069 void movdqu(XMMRegister dst, Address src);
iveresov@34162 1070 void movdqu(XMMRegister dst, XMMRegister src);
twisti@14626 1071 void movdqu(XMMRegister dst, AddressLiteral src);
iveresov@34162 1072 // AVX Unaligned forms
iveresov@34162 1073 void vmovdqu(Address dst, XMMRegister src);
iveresov@34162 1074 void vmovdqu(XMMRegister dst, Address src);
iveresov@34162 1075 void vmovdqu(XMMRegister dst, XMMRegister src);
iveresov@34162 1076 void vmovdqu(XMMRegister dst, AddressLiteral src);
twisti@14626 1077
drchase@18507 1078 // Move Aligned Double Quadword
drchase@18507 1079 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
drchase@18507 1080 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
drchase@18507 1081 void movdqa(XMMRegister dst, AddressLiteral src);
drchase@18507 1082
twisti@14626 1083 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 1084 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 1085 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
twisti@14626 1086 void movsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1087
iveresov@33089 1088 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
iveresov@33089 1089 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
iveresov@33089 1090 void mulpd(XMMRegister dst, AddressLiteral src);
iveresov@33089 1091
twisti@14626 1092 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
twisti@14626 1093 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
twisti@14626 1094 void mulsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1095
twisti@14626 1096 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
twisti@14626 1097 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
twisti@14626 1098 void mulss(XMMRegister dst, AddressLiteral src);
twisti@14626 1099
kvn@25932 1100 // Carry-Less Multiplication Quadword
kvn@25932 1101 void pclmulldq(XMMRegister dst, XMMRegister src) {
kvn@25932 1102 // 0x00 - multiply lower 64 bits [0:63]
kvn@25932 1103 Assembler::pclmulqdq(dst, src, 0x00);
kvn@25932 1104 }
kvn@25932 1105 void pclmulhdq(XMMRegister dst, XMMRegister src) {
kvn@25932 1106 // 0x11 - multiply upper 64 bits [64:127]
kvn@25932 1107 Assembler::pclmulqdq(dst, src, 0x11);
kvn@25932 1108 }
kvn@25932 1109
mcberg@34203 1110 void pcmpeqb(XMMRegister dst, XMMRegister src);
mcberg@34203 1111 void pcmpeqw(XMMRegister dst, XMMRegister src);
mcberg@34203 1112
mcberg@34203 1113 void pcmpestri(XMMRegister dst, Address src, int imm8);
mcberg@34203 1114 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
mcberg@34203 1115
mcberg@34203 1116 void pmovzxbw(XMMRegister dst, XMMRegister src);
mcberg@34203 1117 void pmovzxbw(XMMRegister dst, Address src);
mcberg@34203 1118
mcberg@34203 1119 void pmovmskb(Register dst, XMMRegister src);
mcberg@34203 1120
mcberg@34203 1121 void ptest(XMMRegister dst, XMMRegister src);
mcberg@34203 1122
twisti@14626 1123 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
twisti@14626 1124 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
twisti@14626 1125 void sqrtsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1126
twisti@14626 1127 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
twisti@14626 1128 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
twisti@14626 1129 void sqrtss(XMMRegister dst, AddressLiteral src);
twisti@14626 1130
twisti@14626 1131 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
twisti@14626 1132 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
twisti@14626 1133 void subsd(XMMRegister dst, AddressLiteral src);
twisti@14626 1134
twisti@14626 1135 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
twisti@14626 1136 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
twisti@14626 1137 void subss(XMMRegister dst, AddressLiteral src);
twisti@14626 1138
twisti@14626 1139 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
twisti@14626 1140 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
twisti@14626 1141 void ucomiss(XMMRegister dst, AddressLiteral src);
twisti@14626 1142
twisti@14626 1143 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
twisti@14626 1144 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
twisti@14626 1145 void ucomisd(XMMRegister dst, AddressLiteral src);
twisti@14626 1146
twisti@14626 1147 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
iveresov@34162 1148 void xorpd(XMMRegister dst, XMMRegister src);
twisti@14626 1149 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
twisti@14626 1150 void xorpd(XMMRegister dst, AddressLiteral src);
twisti@14626 1151
twisti@14626 1152 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
iveresov@34162 1153 void xorps(XMMRegister dst, XMMRegister src);
twisti@14626 1154 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
twisti@14626 1155 void xorps(XMMRegister dst, AddressLiteral src);
twisti@14626 1156
twisti@14626 1157 // Shuffle Bytes
twisti@14626 1158 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
twisti@14626 1159 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
twisti@14626 1160 void pshufb(XMMRegister dst, AddressLiteral src);
twisti@14626 1161 // AVX 3-operands instructions
twisti@14626 1162
twisti@14626 1163 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1164 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1165 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1166
twisti@14626 1167 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1168 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1169 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1170
iveresov@34162 1171 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
iveresov@34162 1172 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
iveresov@34162 1173
iveresov@34162 1174 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1175 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1176
iveresov@34162 1177 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1178 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1179
mcberg@34203 1180 void vpbroadcastw(XMMRegister dst, XMMRegister src);
mcberg@34203 1181
mcberg@34203 1182 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1183 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1184
mcberg@34203 1185 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
mcberg@34203 1186 void vpmovmskb(Register dst, XMMRegister src);
mcberg@34203 1187
mcberg@34203 1188 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
mcberg@34203 1189 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
mcberg@34203 1190
iveresov@34162 1191 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1192 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1193
iveresov@34162 1194 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
iveresov@34162 1195 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
iveresov@34162 1196
iveresov@34162 1197 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1198 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1199
iveresov@34162 1200 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1201 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1202
iveresov@34162 1203 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
iveresov@34162 1204 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
iveresov@34162 1205
mcberg@34203 1206 void vptest(XMMRegister dst, XMMRegister src);
mcberg@34203 1207
iveresov@34162 1208 void punpcklbw(XMMRegister dst, XMMRegister src);
iveresov@34162 1209 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
iveresov@34162 1210
iveresov@34162 1211 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
iveresov@34162 1212 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
iveresov@34162 1213
kvn@30624 1214 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
kvn@30624 1215 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
kvn@30624 1216 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1217
kvn@30624 1218 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
kvn@30624 1219 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
kvn@30624 1220 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1221
twisti@14626 1222 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1223 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1224 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1225
twisti@14626 1226 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1227 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1228 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1229
twisti@14626 1230 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1231 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1232 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1233
twisti@14626 1234 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1235 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1236 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1237
twisti@14626 1238 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1239 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1240 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1241
twisti@14626 1242 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1243 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1244 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1245
mcberg@32727 1246 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
mcberg@32727 1247 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
mcberg@32727 1248
twisti@14626 1249 // AVX Vector instructions
twisti@14626 1250
kvn@30624 1251 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
kvn@30624 1252 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
kvn@30624 1253 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1254
kvn@30624 1255 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
kvn@30624 1256 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
kvn@30624 1257 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
twisti@14626 1258
kvn@30624 1259 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
kvn@30624 1260 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
kvn@30624 1261 Assembler::vpxor(dst, nds, src, vector_len);
twisti@14626 1262 else
kvn@30624 1263 Assembler::vxorpd(dst, nds, src, vector_len);
twisti@14626 1264 }
kvn@30624 1265 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
kvn@30624 1266 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
kvn@30624 1267 Assembler::vpxor(dst, nds, src, vector_len);
twisti@14626 1268 else
kvn@30624 1269 Assembler::vxorpd(dst, nds, src, vector_len);
twisti@14626 1270 }
twisti@14626 1271
kvn@15117 1272 // Simple version for AVX2 256bit vectors
kvn@15117 1273 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1274 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1275
mikael@36561 1276 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
mcberg@37293 1277 if (UseAVX > 2) {
mcberg@37293 1278 Assembler::vinserti32x4(dst, dst, src, imm8);
mcberg@37293 1279 } else if (UseAVX > 1) {
mcberg@37293 1280 // vinserti128 is available only in AVX2
mikael@36561 1281 Assembler::vinserti128(dst, nds, src, imm8);
mikael@36561 1282 } else {
mikael@36561 1283 Assembler::vinsertf128(dst, nds, src, imm8);
mikael@36561 1284 }
twisti@14626 1285 }
twisti@14626 1286
mikael@36561 1287 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
mcberg@37293 1288 if (UseAVX > 2) {
mcberg@37293 1289 Assembler::vinserti32x4(dst, dst, src, imm8);
mcberg@37293 1290 } else if (UseAVX > 1) {
mcberg@37293 1291 // vinserti128 is available only in AVX2
mikael@36561 1292 Assembler::vinserti128(dst, nds, src, imm8);
mikael@36561 1293 } else {
mikael@36561 1294 Assembler::vinsertf128(dst, nds, src, imm8);
mikael@36561 1295 }
mikael@36561 1296 }
mikael@36561 1297
mikael@36561 1298 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
mcberg@37293 1299 if (UseAVX > 2) {
mcberg@37293 1300 Assembler::vextracti32x4(dst, src, imm8);
mcberg@37293 1301 } else if (UseAVX > 1) {
mcberg@37293 1302 // vextracti128 is available only in AVX2
mikael@36561 1303 Assembler::vextracti128(dst, src, imm8);
mikael@36561 1304 } else {
mikael@36561 1305 Assembler::vextractf128(dst, src, imm8);
mikael@36561 1306 }
mikael@36561 1307 }
mikael@36561 1308
mikael@36561 1309 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
mcberg@37293 1310 if (UseAVX > 2) {
mcberg@37293 1311 Assembler::vextracti32x4(dst, src, imm8);
mcberg@37293 1312 } else if (UseAVX > 1) {
mcberg@37293 1313 // vextracti128 is available only in AVX2
mikael@36561 1314 Assembler::vextracti128(dst, src, imm8);
mikael@36561 1315 } else {
mikael@36561 1316 Assembler::vextractf128(dst, src, imm8);
mikael@36561 1317 }
mikael@36561 1318 }
mikael@36561 1319
mikael@36561 1320 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
mikael@36561 1321 void vinserti128_high(XMMRegister dst, XMMRegister src) {
mikael@36561 1322 vinserti128(dst, dst, src, 1);
mikael@36561 1323 }
mikael@36561 1324 void vinserti128_high(XMMRegister dst, Address src) {
mikael@36561 1325 vinserti128(dst, dst, src, 1);
mikael@36561 1326 }
mikael@36561 1327 void vextracti128_high(XMMRegister dst, XMMRegister src) {
mikael@36561 1328 vextracti128(dst, src, 1);
mikael@36561 1329 }
mikael@36561 1330 void vextracti128_high(Address dst, XMMRegister src) {
mikael@36561 1331 vextracti128(dst, src, 1);
mikael@36561 1332 }
mcberg@37293 1333
mikael@36561 1334 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1335 if (UseAVX > 2) {
mcberg@37293 1336 Assembler::vinsertf32x4(dst, dst, src, 1);
mcberg@37293 1337 } else {
mcberg@37293 1338 Assembler::vinsertf128(dst, dst, src, 1);
mcberg@37293 1339 }
mikael@36561 1340 }
mcberg@37293 1341
mikael@36561 1342 void vinsertf128_high(XMMRegister dst, Address src) {
mcberg@37293 1343 if (UseAVX > 2) {
mcberg@37293 1344 Assembler::vinsertf32x4(dst, dst, src, 1);
mcberg@37293 1345 } else {
mcberg@37293 1346 Assembler::vinsertf128(dst, dst, src, 1);
mcberg@37293 1347 }
mikael@36561 1348 }
mcberg@37293 1349
mikael@36561 1350 void vextractf128_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1351 if (UseAVX > 2) {
mcberg@37293 1352 Assembler::vextractf32x4(dst, src, 1);
mcberg@37293 1353 } else {
mcberg@37293 1354 Assembler::vextractf128(dst, src, 1);
mcberg@37293 1355 }
mikael@36561 1356 }
mcberg@37293 1357
mikael@36561 1358 void vextractf128_high(Address dst, XMMRegister src) {
mcberg@37293 1359 if (UseAVX > 2) {
mcberg@37293 1360 Assembler::vextractf32x4(dst, src, 1);
mcberg@37293 1361 } else {
mcberg@37293 1362 Assembler::vextractf128(dst, src, 1);
mcberg@37293 1363 }
mikael@36561 1364 }
mikael@36561 1365
mikael@36561 1366 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
mikael@36561 1367 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1368 Assembler::vinserti64x4(dst, dst, src, 1);
mikael@36561 1369 }
mikael@36561 1370 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1371 Assembler::vinsertf64x4(dst, dst, src, 1);
mikael@36561 1372 }
mikael@36561 1373 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1374 Assembler::vextracti64x4(dst, src, 1);
mikael@36561 1375 }
mikael@36561 1376 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
mcberg@37293 1377 Assembler::vextractf64x4(dst, src, 1);
mikael@36561 1378 }
mikael@36561 1379 void vextractf64x4_high(Address dst, XMMRegister src) {
mcberg@37293 1380 Assembler::vextractf64x4(dst, src, 1);
mikael@36561 1381 }
mikael@36561 1382 void vinsertf64x4_high(XMMRegister dst, Address src) {
mcberg@37293 1383 Assembler::vinsertf64x4(dst, dst, src, 1);
mikael@36561 1384 }
mikael@36561 1385
mikael@36561 1386 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
mikael@36561 1387 void vinserti128_low(XMMRegister dst, XMMRegister src) {
mikael@36561 1388 vinserti128(dst, dst, src, 0);
mikael@36561 1389 }
mikael@36561 1390 void vinserti128_low(XMMRegister dst, Address src) {
mikael@36561 1391 vinserti128(dst, dst, src, 0);
mikael@36561 1392 }
mikael@36561 1393 void vextracti128_low(XMMRegister dst, XMMRegister src) {
mikael@36561 1394 vextracti128(dst, src, 0);
mikael@36561 1395 }
mikael@36561 1396 void vextracti128_low(Address dst, XMMRegister src) {
mikael@36561 1397 vextracti128(dst, src, 0);
mikael@36561 1398 }
mcberg@37293 1399
mikael@36561 1400 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1401 if (UseAVX > 2) {
mcberg@37293 1402 Assembler::vinsertf32x4(dst, dst, src, 0);
mcberg@37293 1403 } else {
mcberg@37293 1404 Assembler::vinsertf128(dst, dst, src, 0);
mcberg@37293 1405 }
mikael@36561 1406 }
mcberg@37293 1407
mikael@36561 1408 void vinsertf128_low(XMMRegister dst, Address src) {
mcberg@37293 1409 if (UseAVX > 2) {
mcberg@37293 1410 Assembler::vinsertf32x4(dst, dst, src, 0);
mcberg@37293 1411 } else {
mcberg@37293 1412 Assembler::vinsertf128(dst, dst, src, 0);
mcberg@37293 1413 }
mikael@36561 1414 }
mcberg@37293 1415
mikael@36561 1416 void vextractf128_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1417 if (UseAVX > 2) {
mcberg@37293 1418 Assembler::vextractf32x4(dst, src, 0);
mcberg@37293 1419 } else {
mcberg@37293 1420 Assembler::vextractf128(dst, src, 0);
mcberg@37293 1421 }
mikael@36561 1422 }
mcberg@37293 1423
mikael@36561 1424 void vextractf128_low(Address dst, XMMRegister src) {
mcberg@37293 1425 if (UseAVX > 2) {
mcberg@37293 1426 Assembler::vextractf32x4(dst, src, 0);
mcberg@37293 1427 } else {
mcberg@37293 1428 Assembler::vextractf128(dst, src, 0);
mcberg@37293 1429 }
mikael@36561 1430 }
mikael@36561 1431
mikael@36561 1432 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
mikael@36561 1433 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1434 Assembler::vinserti64x4(dst, dst, src, 0);
mikael@36561 1435 }
mikael@36561 1436 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1437 Assembler::vinsertf64x4(dst, dst, src, 0);
mikael@36561 1438 }
mikael@36561 1439 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1440 Assembler::vextracti64x4(dst, src, 0);
mikael@36561 1441 }
mikael@36561 1442 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
mcberg@37293 1443 Assembler::vextractf64x4(dst, src, 0);
mikael@36561 1444 }
mikael@36561 1445 void vextractf64x4_low(Address dst, XMMRegister src) {
mcberg@37293 1446 Assembler::vextractf64x4(dst, src, 0);
mikael@36561 1447 }
mikael@36561 1448 void vinsertf64x4_low(XMMRegister dst, Address src) {
mcberg@37293 1449 Assembler::vinsertf64x4(dst, dst, src, 0);
mikael@36561 1450 }
mikael@36561 1451
drchase@18507 1452 // Carry-Less Multiplication Quadword
drchase@18507 1453 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1454 // 0x00 - multiply lower 64 bits [0:63]
drchase@18507 1455 Assembler::vpclmulqdq(dst, nds, src, 0x00);
drchase@18507 1456 }
drchase@18507 1457 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1458 // 0x11 - multiply upper 64 bits [64:127]
drchase@18507 1459 Assembler::vpclmulqdq(dst, nds, src, 0x11);
drchase@18507 1460 }
drchase@18507 1461
twisti@14626 1462 // Data
twisti@14626 1463
twisti@14626 1464 void cmov32( Condition cc, Register dst, Address src);
twisti@14626 1465 void cmov32( Condition cc, Register dst, Register src);
twisti@14626 1466
twisti@14626 1467 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
twisti@14626 1468
twisti@14626 1469 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1470 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1471
twisti@14626 1472 void movoop(Register dst, jobject obj);
twisti@14626 1473 void movoop(Address dst, jobject obj);
twisti@14626 1474
twisti@14626 1475 void mov_metadata(Register dst, Metadata* obj);
twisti@14626 1476 void mov_metadata(Address dst, Metadata* obj);
twisti@14626 1477
twisti@14626 1478 void movptr(ArrayAddress dst, Register src);
twisti@14626 1479 // can this do an lea?
twisti@14626 1480 void movptr(Register dst, ArrayAddress src);
twisti@14626 1481
twisti@14626 1482 void movptr(Register dst, Address src);
twisti@14626 1483
kvn@23491 1484 #ifdef _LP64
kvn@23491 1485 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
kvn@23491 1486 #else
kvn@23491 1487 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
kvn@23491 1488 #endif
twisti@14626 1489
twisti@14626 1490 void movptr(Register dst, intptr_t src);
twisti@14626 1491 void movptr(Register dst, Register src);
twisti@14626 1492 void movptr(Address dst, intptr_t src);
twisti@14626 1493
twisti@14626 1494 void movptr(Address dst, Register src);
twisti@14626 1495
twisti@14626 1496 void movptr(Register dst, RegisterOrConstant src) {
twisti@14626 1497 if (src.is_constant()) movptr(dst, src.as_constant());
twisti@14626 1498 else movptr(dst, src.as_register());
twisti@14626 1499 }
twisti@14626 1500
twisti@14626 1501 #ifdef _LP64
twisti@14626 1502 // Generally the next two are only used for moving NULL
twisti@14626 1503 // Although there are situations in initializing the mark word where
twisti@14626 1504 // they could be used. They are dangerous.
twisti@14626 1505
twisti@14626 1506 // They only exist on LP64 so that int32_t and intptr_t are not the same
twisti@14626 1507 // and we have ambiguous declarations.
twisti@14626 1508
twisti@14626 1509 void movptr(Address dst, int32_t imm32);
twisti@14626 1510 void movptr(Register dst, int32_t imm32);
twisti@14626 1511 #endif // _LP64
twisti@14626 1512
twisti@14626 1513 // to avoid hiding movl
twisti@14626 1514 void mov32(AddressLiteral dst, Register src);
twisti@14626 1515 void mov32(Register dst, AddressLiteral src);
twisti@14626 1516
twisti@14626 1517 // to avoid hiding movb
twisti@14626 1518 void movbyte(ArrayAddress dst, int src);
twisti@14626 1519
twisti@14626 1520 // Import other mov() methods from the parent class or else
twisti@14626 1521 // they will be hidden by the following overriding declaration.
twisti@14626 1522 using Assembler::movdl;
twisti@14626 1523 using Assembler::movq;
twisti@14626 1524 void movdl(XMMRegister dst, AddressLiteral src);
twisti@14626 1525 void movq(XMMRegister dst, AddressLiteral src);
twisti@14626 1526
twisti@14626 1527 // Can push value or effective address
twisti@14626 1528 void pushptr(AddressLiteral src);
twisti@14626 1529
twisti@14626 1530 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
twisti@14626 1531 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
twisti@14626 1532
twisti@14626 1533 void pushoop(jobject obj);
twisti@14626 1534 void pushklass(Metadata* obj);
twisti@14626 1535
twisti@14626 1536 // sign extend as need a l to ptr sized element
twisti@14626 1537 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
twisti@14626 1538 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
twisti@14626 1539
twisti@14626 1540 // C2 compiled method's prolog code.
roland@24018 1541 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
twisti@14626 1542
shade@36554 1543 // clear memory of size 'cnt' qwords, starting at 'base';
shade@36554 1544 // if 'is_large' is set, do not try to produce short loop
shade@36554 1545 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
kvn@15114 1546
thartmann@33628 1547 #ifdef COMPILER2
thartmann@33628 1548 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
thartmann@33628 1549 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
thartmann@33628 1550
twisti@14626 1551 // IndexOf strings.
twisti@14626 1552 // Small strings are loaded through stack if they cross page boundary.
twisti@14626 1553 void string_indexof(Register str1, Register str2,
twisti@14626 1554 Register cnt1, Register cnt2,
twisti@14626 1555 int int_cnt2, Register result,
thartmann@33628 1556 XMMRegister vec, Register tmp,
thartmann@33628 1557 int ae);
twisti@14626 1558
twisti@14626 1559 // IndexOf for constant substrings with size >= 8 elements
twisti@14626 1560 // which don't need to be loaded through stack.
twisti@14626 1561 void string_indexofC8(Register str1, Register str2,
twisti@14626 1562 Register cnt1, Register cnt2,
twisti@14626 1563 int int_cnt2, Register result,
thartmann@33628 1564 XMMRegister vec, Register tmp,
thartmann@33628 1565 int ae);
twisti@14626 1566
twisti@14626 1567 // Smallest code: we don't need to load through stack,
twisti@14626 1568 // check string tail.
twisti@14626 1569
thartmann@33628 1570 // helper function for string_compare
thartmann@33628 1571 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
thartmann@33628 1572 Address::ScaleFactor scale, Address::ScaleFactor scale1,
thartmann@33628 1573 Address::ScaleFactor scale2, Register index, int ae);
twisti@14626 1574 // Compare strings.
twisti@14626 1575 void string_compare(Register str1, Register str2,
twisti@14626 1576 Register cnt1, Register cnt2, Register result,
thartmann@33628 1577 XMMRegister vec1, int ae);
twisti@14626 1578
thartmann@33628 1579 // Search for Non-ASCII character (Negative byte value) in a byte array,
thartmann@33628 1580 // return true if it has any and false otherwise.
thartmann@33628 1581 void has_negatives(Register ary1, Register len,
thartmann@33628 1582 Register result, Register tmp1,
thartmann@33628 1583 XMMRegister vec1, XMMRegister vec2);
thartmann@33628 1584
thartmann@33628 1585 // Compare char[] or byte[] arrays.
thartmann@33628 1586 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
thartmann@33628 1587 Register limit, Register result, Register chr,
thartmann@33628 1588 XMMRegister vec1, XMMRegister vec2, bool is_char);
thartmann@33628 1589
thartmann@33628 1590 #endif
twisti@14626 1591
twisti@14626 1592 // Fill primitive arrays
twisti@14626 1593 void generate_fill(BasicType t, bool aligned,
twisti@14626 1594 Register to, Register value, Register count,
twisti@14626 1595 Register rtmp, XMMRegister xtmp);
twisti@14626 1596
kvn@15242 1597 void encode_iso_array(Register src, Register dst, Register len,
kvn@15242 1598 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
kvn@15242 1599 XMMRegister tmp4, Register tmp5, Register result);
kvn@15242 1600
kvn@26434 1601 #ifdef _LP64
kvn@26434 1602 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
kvn@26434 1603 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
kvn@26434 1604 Register y, Register y_idx, Register z,
kvn@26434 1605 Register carry, Register product,
kvn@26434 1606 Register idx, Register kdx);
kvn@26434 1607 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
kvn@26434 1608 Register yz_idx, Register idx,
kvn@26434 1609 Register carry, Register product, int offset);
kvn@26434 1610 void multiply_128_x_128_bmi2_loop(Register y, Register z,
kvn@26434 1611 Register carry, Register carry2,
kvn@26434 1612 Register idx, Register jdx,
kvn@26434 1613 Register yz_idx1, Register yz_idx2,
kvn@26434 1614 Register tmp, Register tmp3, Register tmp4);
kvn@26434 1615 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
kvn@26434 1616 Register yz_idx, Register idx, Register jdx,
kvn@26434 1617 Register carry, Register product,
kvn@26434 1618 Register carry2);
kvn@26434 1619 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
kvn@26434 1620 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
kvn@31129 1621 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
kvn@31129 1622 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
kvn@31129 1623 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
kvn@31129 1624 Register tmp2);
kvn@31129 1625 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
kvn@31129 1626 Register rdxReg, Register raxReg);
kvn@31129 1627 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
kvn@31129 1628 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
kvn@31129 1629 Register tmp3, Register tmp4);
kvn@31129 1630 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
kvn@31129 1631 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
kvn@31129 1632
kvn@31129 1633 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
kvn@31129 1634 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
kvn@31129 1635 Register raxReg);
kvn@31129 1636 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
kvn@31129 1637 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
kvn@31129 1638 Register raxReg);
kvn@35110 1639 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
kvn@35110 1640 Register result, Register tmp1, Register tmp2,
kvn@35110 1641 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
kvn@26434 1642 #endif
kvn@26434 1643
kvn@33066 1644 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
drchase@18507 1645 void update_byte_crc32(Register crc, Register val, Register table);
drchase@18507 1646 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
kvn@33066 1647 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
kvn@33066 1648 // Note on a naming convention:
kvn@33066 1649 // Prefix w = register only used on a Westmere+ architecture
kvn@33066 1650 // Prefix n = register only used on a Nehalem architecture
kvn@33066 1651 #ifdef _LP64
kvn@33066 1652 void crc32c_ipl_alg4(Register in_out, uint32_t n,
kvn@33066 1653 Register tmp1, Register tmp2, Register tmp3);
kvn@33066 1654 #else
kvn@33066 1655 void crc32c_ipl_alg4(Register in_out, uint32_t n,
kvn@33066 1656 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1657 XMMRegister xtmp1, XMMRegister xtmp2);
kvn@33066 1658 #endif
kvn@33066 1659 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
kvn@33066 1660 Register in_out,
kvn@33066 1661 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
kvn@33066 1662 XMMRegister w_xtmp2,
kvn@33066 1663 Register tmp1,
kvn@33066 1664 Register n_tmp2, Register n_tmp3);
kvn@33066 1665 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
kvn@33066 1666 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1667 Register tmp1, Register tmp2,
kvn@33066 1668 Register n_tmp3);
kvn@33066 1669 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
kvn@33066 1670 Register in_out1, Register in_out2, Register in_out3,
kvn@33066 1671 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1672 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1673 Register tmp4, Register tmp5,
kvn@33066 1674 Register n_tmp6);
kvn@33066 1675 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
kvn@33066 1676 Register tmp1, Register tmp2, Register tmp3,
kvn@33066 1677 Register tmp4, Register tmp5, Register tmp6,
kvn@33066 1678 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
kvn@33066 1679 bool is_pclmulqdq_supported);
drchase@18507 1680 // Fold 128-bit data chunk
drchase@18507 1681 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
drchase@18507 1682 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
drchase@18507 1683 // Fold 8-bit data
drchase@18507 1684 void fold_8bit_crc32(Register crc, Register table, Register tmp);
drchase@18507 1685 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
drchase@18507 1686
thartmann@33628 1687 // Compress char[] array to byte[].
thartmann@33628 1688 void char_array_compress(Register src, Register dst, Register len,
thartmann@33628 1689 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
thartmann@33628 1690 XMMRegister tmp4, Register tmp5, Register result);
thartmann@33628 1691
thartmann@33628 1692 // Inflate byte[] array to char[].
thartmann@33628 1693 void byte_array_inflate(Register src, Register dst, Register len,
thartmann@33628 1694 XMMRegister tmp1, Register tmp2);
thartmann@33628 1695
twisti@14626 1696 };
twisti@14626 1697
twisti@14626 1698 /**
twisti@14626 1699 * class SkipIfEqual:
twisti@14626 1700 *
twisti@14626 1701 * Instantiating this class will result in assembly code being output that will
twisti@14626 1702 * jump around any code emitted between the creation of the instance and it's
twisti@14626 1703 * automatic destruction at the end of a scope block, depending on the value of
twisti@14626 1704 * the flag passed to the constructor, which will be checked at run-time.
twisti@14626 1705 */
twisti@14626 1706 class SkipIfEqual {
twisti@14626 1707 private:
twisti@14626 1708 MacroAssembler* _masm;
twisti@14626 1709 Label _label;
twisti@14626 1710
twisti@14626 1711 public:
twisti@14626 1712 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
twisti@14626 1713 ~SkipIfEqual();
twisti@14626 1714 };
twisti@14626 1715
twisti@14626 1716 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP