annotate hotspot/src/cpu/x86/vm/macroAssembler_x86.hpp @ 23491:f690330b10b9

8031320: Use Intel RTM instructions for locks Summary: Use RTM for inflated locks and stack locks. Reviewed-by: iveresov, twisti, roland, dcubed
author kvn
date Thu, 20 Mar 2014 17:49:27 -0700
parents 88c3369b5967
children 77b156916bab
rev   line source
twisti@14626 1 /*
drchase@18507 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
twisti@14626 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@14626 4 *
twisti@14626 5 * This code is free software; you can redistribute it and/or modify it
twisti@14626 6 * under the terms of the GNU General Public License version 2 only, as
twisti@14626 7 * published by the Free Software Foundation.
twisti@14626 8 *
twisti@14626 9 * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@14626 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@14626 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
twisti@14626 12 * version 2 for more details (a copy is included in the LICENSE file that
twisti@14626 13 * accompanied this code).
twisti@14626 14 *
twisti@14626 15 * You should have received a copy of the GNU General Public License version
twisti@14626 16 * 2 along with this work; if not, write to the Free Software Foundation,
twisti@14626 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@14626 18 *
twisti@14626 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
twisti@14626 20 * or visit www.oracle.com if you need additional information or have any
twisti@14626 21 * questions.
twisti@14626 22 *
twisti@14626 23 */
twisti@14626 24
twisti@14626 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
twisti@14626 27
twisti@14626 28 #include "asm/assembler.hpp"
jprovino@15482 29 #include "utilities/macros.hpp"
kvn@23491 30 #include "runtime/rtmLocking.hpp"
twisti@14626 31
twisti@14626 32
twisti@14626 33 // MacroAssembler extends Assembler by frequently used macros.
twisti@14626 34 //
twisti@14626 35 // Instructions for which a 'better' code sequence exists depending
twisti@14626 36 // on arguments should also go in here.
twisti@14626 37
twisti@14626 38 class MacroAssembler: public Assembler {
twisti@14626 39 friend class LIR_Assembler;
twisti@14626 40 friend class Runtime1; // as_Address()
twisti@14626 41
twisti@14626 42 protected:
twisti@14626 43
twisti@14626 44 Address as_Address(AddressLiteral adr);
twisti@14626 45 Address as_Address(ArrayAddress adr);
twisti@14626 46
twisti@14626 47 // Support for VM calls
twisti@14626 48 //
twisti@14626 49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
twisti@14626 50 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 51 // additional registers when doing a VM call).
twisti@14626 52 #ifdef CC_INTERP
twisti@14626 53 // c++ interpreter never wants to use interp_masm version of call_VM
twisti@14626 54 #define VIRTUAL
twisti@14626 55 #else
twisti@14626 56 #define VIRTUAL virtual
twisti@14626 57 #endif
twisti@14626 58
twisti@14626 59 VIRTUAL void call_VM_leaf_base(
twisti@14626 60 address entry_point, // the entry point
twisti@14626 61 int number_of_arguments // the number of arguments to pop after the call
twisti@14626 62 );
twisti@14626 63
twisti@14626 64 // This is the base routine called by the different versions of call_VM. The interpreter
twisti@14626 65 // may customize this version by overriding it for its purposes (e.g., to save/restore
twisti@14626 66 // additional registers when doing a VM call).
twisti@14626 67 //
twisti@14626 68 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
twisti@14626 69 // returns the register which contains the thread upon return. If a thread register has been
twisti@14626 70 // specified, the return value will correspond to that register. If no last_java_sp is specified
twisti@14626 71 // (noreg) than rsp will be used instead.
twisti@14626 72 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
twisti@14626 73 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
twisti@14626 74 Register java_thread, // the thread if computed before ; use noreg otherwise
twisti@14626 75 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
twisti@14626 76 address entry_point, // the entry point
twisti@14626 77 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
twisti@14626 78 bool check_exceptions // whether to check for pending exceptions after return
twisti@14626 79 );
twisti@14626 80
twisti@14626 81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
twisti@14626 82 // The implementation is only non-empty for the InterpreterMacroAssembler,
twisti@14626 83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
twisti@14626 84 virtual void check_and_handle_popframe(Register java_thread);
twisti@14626 85 virtual void check_and_handle_earlyret(Register java_thread);
twisti@14626 86
twisti@14626 87 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
twisti@14626 88
twisti@14626 89 // helpers for FPU flag access
twisti@14626 90 // tmp is a temporary register, if none is available use noreg
twisti@14626 91 void save_rax (Register tmp);
twisti@14626 92 void restore_rax(Register tmp);
twisti@14626 93
twisti@14626 94 public:
twisti@14626 95 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
twisti@14626 96
twisti@14626 97 // Support for NULL-checks
twisti@14626 98 //
twisti@14626 99 // Generates code that causes a NULL OS exception if the content of reg is NULL.
twisti@14626 100 // If the accessed location is M[reg + offset] and the offset is known, provide the
twisti@14626 101 // offset. No explicit code generation is needed if the offset is within a certain
twisti@14626 102 // range (0 <= offset <= page_size).
twisti@14626 103
twisti@14626 104 void null_check(Register reg, int offset = -1);
twisti@14626 105 static bool needs_explicit_null_check(intptr_t offset);
twisti@14626 106
twisti@14626 107 // Required platform-specific helpers for Label::patch_instructions.
twisti@14626 108 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
twisti@14626 109 void pd_patch_instruction(address branch, address target) {
twisti@14626 110 unsigned char op = branch[0];
twisti@14626 111 assert(op == 0xE8 /* call */ ||
twisti@14626 112 op == 0xE9 /* jmp */ ||
twisti@14626 113 op == 0xEB /* short jmp */ ||
twisti@14626 114 (op & 0xF0) == 0x70 /* short jcc */ ||
kvn@23491 115 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
kvn@23491 116 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
twisti@14626 117 "Invalid opcode at patch point");
twisti@14626 118
twisti@14626 119 if (op == 0xEB || (op & 0xF0) == 0x70) {
twisti@14626 120 // short offset operators (jmp and jcc)
twisti@14626 121 char* disp = (char*) &branch[1];
twisti@14626 122 int imm8 = target - (address) &disp[1];
twisti@14626 123 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
twisti@14626 124 *disp = imm8;
twisti@14626 125 } else {
kvn@23491 126 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
twisti@14626 127 int imm32 = target - (address) &disp[1];
twisti@14626 128 *disp = imm32;
twisti@14626 129 }
twisti@14626 130 }
twisti@14626 131
twisti@14626 132 // The following 4 methods return the offset of the appropriate move instruction
twisti@14626 133
twisti@14626 134 // Support for fast byte/short loading with zero extension (depending on particular CPU)
twisti@14626 135 int load_unsigned_byte(Register dst, Address src);
twisti@14626 136 int load_unsigned_short(Register dst, Address src);
twisti@14626 137
twisti@14626 138 // Support for fast byte/short loading with sign extension (depending on particular CPU)
twisti@14626 139 int load_signed_byte(Register dst, Address src);
twisti@14626 140 int load_signed_short(Register dst, Address src);
twisti@14626 141
twisti@14626 142 // Support for sign-extension (hi:lo = extend_sign(lo))
twisti@14626 143 void extend_sign(Register hi, Register lo);
twisti@14626 144
twisti@14626 145 // Load and store values by size and signed-ness
twisti@14626 146 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
twisti@14626 147 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
twisti@14626 148
twisti@14626 149 // Support for inc/dec with optimal instruction selection depending on value
twisti@14626 150
twisti@14626 151 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
twisti@14626 152 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
twisti@14626 153
twisti@14626 154 void decrementl(Address dst, int value = 1);
twisti@14626 155 void decrementl(Register reg, int value = 1);
twisti@14626 156
twisti@14626 157 void decrementq(Register reg, int value = 1);
twisti@14626 158 void decrementq(Address dst, int value = 1);
twisti@14626 159
twisti@14626 160 void incrementl(Address dst, int value = 1);
twisti@14626 161 void incrementl(Register reg, int value = 1);
twisti@14626 162
twisti@14626 163 void incrementq(Register reg, int value = 1);
twisti@14626 164 void incrementq(Address dst, int value = 1);
twisti@14626 165
twisti@14626 166 // Support optimal SSE move instructions.
twisti@14626 167 void movflt(XMMRegister dst, XMMRegister src) {
twisti@14626 168 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
twisti@14626 169 else { movss (dst, src); return; }
twisti@14626 170 }
twisti@14626 171 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
twisti@14626 172 void movflt(XMMRegister dst, AddressLiteral src);
twisti@14626 173 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
twisti@14626 174
twisti@14626 175 void movdbl(XMMRegister dst, XMMRegister src) {
twisti@14626 176 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
twisti@14626 177 else { movsd (dst, src); return; }
twisti@14626 178 }
twisti@14626 179
twisti@14626 180 void movdbl(XMMRegister dst, AddressLiteral src);
twisti@14626 181
twisti@14626 182 void movdbl(XMMRegister dst, Address src) {
twisti@14626 183 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
twisti@14626 184 else { movlpd(dst, src); return; }
twisti@14626 185 }
twisti@14626 186 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
twisti@14626 187
twisti@14626 188 void incrementl(AddressLiteral dst);
twisti@14626 189 void incrementl(ArrayAddress dst);
twisti@14626 190
kvn@23491 191 void incrementq(AddressLiteral dst);
kvn@23491 192
twisti@14626 193 // Alignment
twisti@14626 194 void align(int modulus);
twisti@14626 195
twisti@14626 196 // A 5 byte nop that is safe for patching (see patch_verified_entry)
twisti@14626 197 void fat_nop();
twisti@14626 198
twisti@14626 199 // Stack frame creation/removal
twisti@14626 200 void enter();
twisti@14626 201 void leave();
twisti@14626 202
twisti@14626 203 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
twisti@14626 204 // The pointer will be loaded into the thread register.
twisti@14626 205 void get_thread(Register thread);
twisti@14626 206
twisti@14626 207
twisti@14626 208 // Support for VM calls
twisti@14626 209 //
twisti@14626 210 // It is imperative that all calls into the VM are handled via the call_VM macros.
twisti@14626 211 // They make sure that the stack linkage is setup correctly. call_VM's correspond
twisti@14626 212 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
twisti@14626 213
twisti@14626 214
twisti@14626 215 void call_VM(Register oop_result,
twisti@14626 216 address entry_point,
twisti@14626 217 bool check_exceptions = true);
twisti@14626 218 void call_VM(Register oop_result,
twisti@14626 219 address entry_point,
twisti@14626 220 Register arg_1,
twisti@14626 221 bool check_exceptions = true);
twisti@14626 222 void call_VM(Register oop_result,
twisti@14626 223 address entry_point,
twisti@14626 224 Register arg_1, Register arg_2,
twisti@14626 225 bool check_exceptions = true);
twisti@14626 226 void call_VM(Register oop_result,
twisti@14626 227 address entry_point,
twisti@14626 228 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 229 bool check_exceptions = true);
twisti@14626 230
twisti@14626 231 // Overloadings with last_Java_sp
twisti@14626 232 void call_VM(Register oop_result,
twisti@14626 233 Register last_java_sp,
twisti@14626 234 address entry_point,
twisti@14626 235 int number_of_arguments = 0,
twisti@14626 236 bool check_exceptions = true);
twisti@14626 237 void call_VM(Register oop_result,
twisti@14626 238 Register last_java_sp,
twisti@14626 239 address entry_point,
twisti@14626 240 Register arg_1, bool
twisti@14626 241 check_exceptions = true);
twisti@14626 242 void call_VM(Register oop_result,
twisti@14626 243 Register last_java_sp,
twisti@14626 244 address entry_point,
twisti@14626 245 Register arg_1, Register arg_2,
twisti@14626 246 bool check_exceptions = true);
twisti@14626 247 void call_VM(Register oop_result,
twisti@14626 248 Register last_java_sp,
twisti@14626 249 address entry_point,
twisti@14626 250 Register arg_1, Register arg_2, Register arg_3,
twisti@14626 251 bool check_exceptions = true);
twisti@14626 252
twisti@14626 253 void get_vm_result (Register oop_result, Register thread);
twisti@14626 254 void get_vm_result_2(Register metadata_result, Register thread);
twisti@14626 255
twisti@14626 256 // These always tightly bind to MacroAssembler::call_VM_base
twisti@14626 257 // bypassing the virtual implementation
twisti@14626 258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
twisti@14626 259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
twisti@14626 260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
twisti@14626 261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
twisti@14626 262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
twisti@14626 263
twisti@14626 264 void call_VM_leaf(address entry_point,
twisti@14626 265 int number_of_arguments = 0);
twisti@14626 266 void call_VM_leaf(address entry_point,
twisti@14626 267 Register arg_1);
twisti@14626 268 void call_VM_leaf(address entry_point,
twisti@14626 269 Register arg_1, Register arg_2);
twisti@14626 270 void call_VM_leaf(address entry_point,
twisti@14626 271 Register arg_1, Register arg_2, Register arg_3);
twisti@14626 272
twisti@14626 273 // These always tightly bind to MacroAssembler::call_VM_leaf_base
twisti@14626 274 // bypassing the virtual implementation
twisti@14626 275 void super_call_VM_leaf(address entry_point);
twisti@14626 276 void super_call_VM_leaf(address entry_point, Register arg_1);
twisti@14626 277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
twisti@14626 278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
twisti@14626 279 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
twisti@14626 280
twisti@14626 281 // last Java Frame (fills frame anchor)
twisti@14626 282 void set_last_Java_frame(Register thread,
twisti@14626 283 Register last_java_sp,
twisti@14626 284 Register last_java_fp,
twisti@14626 285 address last_java_pc);
twisti@14626 286
twisti@14626 287 // thread in the default location (r15_thread on 64bit)
twisti@14626 288 void set_last_Java_frame(Register last_java_sp,
twisti@14626 289 Register last_java_fp,
twisti@14626 290 address last_java_pc);
twisti@14626 291
twisti@14626 292 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
twisti@14626 293
twisti@14626 294 // thread in the default location (r15_thread on 64bit)
twisti@14626 295 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
twisti@14626 296
twisti@14626 297 // Stores
twisti@14626 298 void store_check(Register obj); // store check for obj - register is destroyed afterwards
twisti@14626 299 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
twisti@14626 300
jprovino@15482 301 #if INCLUDE_ALL_GCS
twisti@14626 302
twisti@14626 303 void g1_write_barrier_pre(Register obj,
twisti@14626 304 Register pre_val,
twisti@14626 305 Register thread,
twisti@14626 306 Register tmp,
twisti@14626 307 bool tosca_live,
twisti@14626 308 bool expand_call);
twisti@14626 309
twisti@14626 310 void g1_write_barrier_post(Register store_addr,
twisti@14626 311 Register new_val,
twisti@14626 312 Register thread,
twisti@14626 313 Register tmp,
twisti@14626 314 Register tmp2);
twisti@14626 315
jprovino@15482 316 #endif // INCLUDE_ALL_GCS
twisti@14626 317
twisti@14626 318 // split store_check(Register obj) to enhance instruction interleaving
twisti@14626 319 void store_check_part_1(Register obj);
twisti@14626 320 void store_check_part_2(Register obj);
twisti@14626 321
twisti@14626 322 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
twisti@14626 323 void c2bool(Register x);
twisti@14626 324
twisti@14626 325 // C++ bool manipulation
twisti@14626 326
twisti@14626 327 void movbool(Register dst, Address src);
twisti@14626 328 void movbool(Address dst, bool boolconst);
twisti@14626 329 void movbool(Address dst, Register src);
twisti@14626 330 void testbool(Register dst);
twisti@14626 331
twisti@14626 332 // oop manipulations
twisti@14626 333 void load_klass(Register dst, Register src);
twisti@14626 334 void store_klass(Register dst, Register src);
twisti@14626 335
twisti@14626 336 void load_heap_oop(Register dst, Address src);
twisti@14626 337 void load_heap_oop_not_null(Register dst, Address src);
twisti@14626 338 void store_heap_oop(Address dst, Register src);
twisti@14626 339 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
twisti@14626 340
twisti@14626 341 // Used for storing NULL. All other oop constants should be
twisti@14626 342 // stored using routines that take a jobject.
twisti@14626 343 void store_heap_oop_null(Address dst);
twisti@14626 344
twisti@14626 345 void load_prototype_header(Register dst, Register src);
twisti@14626 346
twisti@14626 347 #ifdef _LP64
twisti@14626 348 void store_klass_gap(Register dst, Register src);
twisti@14626 349
twisti@14626 350 // This dummy is to prevent a call to store_heap_oop from
twisti@14626 351 // converting a zero (like NULL) into a Register by giving
twisti@14626 352 // the compiler two choices it can't resolve
twisti@14626 353
twisti@14626 354 void store_heap_oop(Address dst, void* dummy);
twisti@14626 355
twisti@14626 356 void encode_heap_oop(Register r);
twisti@14626 357 void decode_heap_oop(Register r);
twisti@14626 358 void encode_heap_oop_not_null(Register r);
twisti@14626 359 void decode_heap_oop_not_null(Register r);
twisti@14626 360 void encode_heap_oop_not_null(Register dst, Register src);
twisti@14626 361 void decode_heap_oop_not_null(Register dst, Register src);
twisti@14626 362
twisti@14626 363 void set_narrow_oop(Register dst, jobject obj);
twisti@14626 364 void set_narrow_oop(Address dst, jobject obj);
twisti@14626 365 void cmp_narrow_oop(Register dst, jobject obj);
twisti@14626 366 void cmp_narrow_oop(Address dst, jobject obj);
twisti@14626 367
twisti@14626 368 void encode_klass_not_null(Register r);
twisti@14626 369 void decode_klass_not_null(Register r);
twisti@14626 370 void encode_klass_not_null(Register dst, Register src);
twisti@14626 371 void decode_klass_not_null(Register dst, Register src);
twisti@14626 372 void set_narrow_klass(Register dst, Klass* k);
twisti@14626 373 void set_narrow_klass(Address dst, Klass* k);
twisti@14626 374 void cmp_narrow_klass(Register dst, Klass* k);
twisti@14626 375 void cmp_narrow_klass(Address dst, Klass* k);
twisti@14626 376
hseigel@19319 377 // Returns the byte size of the instructions generated by decode_klass_not_null()
hseigel@19319 378 // when compressed klass pointers are being used.
hseigel@19319 379 static int instr_size_for_decode_klass_not_null();
hseigel@19319 380
twisti@14626 381 // if heap base register is used - reinit it with the correct value
twisti@14626 382 void reinit_heapbase();
twisti@14626 383
twisti@14626 384 DEBUG_ONLY(void verify_heapbase(const char* msg);)
twisti@14626 385
twisti@14626 386 #endif // _LP64
twisti@14626 387
twisti@14626 388 // Int division/remainder for Java
twisti@14626 389 // (as idivl, but checks for special case as described in JVM spec.)
twisti@14626 390 // returns idivl instruction offset for implicit exception handling
twisti@14626 391 int corrected_idivl(Register reg);
twisti@14626 392
twisti@14626 393 // Long division/remainder for Java
twisti@14626 394 // (as idivq, but checks for special case as described in JVM spec.)
twisti@14626 395 // returns idivq instruction offset for implicit exception handling
twisti@14626 396 int corrected_idivq(Register reg);
twisti@14626 397
twisti@14626 398 void int3();
twisti@14626 399
twisti@14626 400 // Long operation macros for a 32bit cpu
twisti@14626 401 // Long negation for Java
twisti@14626 402 void lneg(Register hi, Register lo);
twisti@14626 403
twisti@14626 404 // Long multiplication for Java
twisti@14626 405 // (destroys contents of eax, ebx, ecx and edx)
twisti@14626 406 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
twisti@14626 407
twisti@14626 408 // Long shifts for Java
twisti@14626 409 // (semantics as described in JVM spec.)
twisti@14626 410 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
twisti@14626 411 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
twisti@14626 412
twisti@14626 413 // Long compare for Java
twisti@14626 414 // (semantics as described in JVM spec.)
twisti@14626 415 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
twisti@14626 416
twisti@14626 417
twisti@14626 418 // misc
twisti@14626 419
twisti@14626 420 // Sign extension
twisti@14626 421 void sign_extend_short(Register reg);
twisti@14626 422 void sign_extend_byte(Register reg);
twisti@14626 423
twisti@14626 424 // Division by power of 2, rounding towards 0
twisti@14626 425 void division_with_shift(Register reg, int shift_value);
twisti@14626 426
twisti@14626 427 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
twisti@14626 428 //
twisti@14626 429 // CF (corresponds to C0) if x < y
twisti@14626 430 // PF (corresponds to C2) if unordered
twisti@14626 431 // ZF (corresponds to C3) if x = y
twisti@14626 432 //
twisti@14626 433 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 434 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
twisti@14626 435 void fcmp(Register tmp);
twisti@14626 436 // Variant of the above which allows y to be further down the stack
twisti@14626 437 // and which only pops x and y if specified. If pop_right is
twisti@14626 438 // specified then pop_left must also be specified.
twisti@14626 439 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
twisti@14626 440
twisti@14626 441 // Floating-point comparison for Java
twisti@14626 442 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
twisti@14626 443 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
twisti@14626 444 // (semantics as described in JVM spec.)
twisti@14626 445 void fcmp2int(Register dst, bool unordered_is_less);
twisti@14626 446 // Variant of the above which allows y to be further down the stack
twisti@14626 447 // and which only pops x and y if specified. If pop_right is
twisti@14626 448 // specified then pop_left must also be specified.
twisti@14626 449 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
twisti@14626 450
twisti@14626 451 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
twisti@14626 452 // tmp is a temporary register, if none is available use noreg
twisti@14626 453 void fremr(Register tmp);
twisti@14626 454
twisti@14626 455
twisti@14626 456 // same as fcmp2int, but using SSE2
twisti@14626 457 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 458 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
twisti@14626 459
twisti@14626 460 // Inlined sin/cos generator for Java; must not use CPU instruction
twisti@14626 461 // directly on Intel as it does not have high enough precision
twisti@14626 462 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
twisti@14626 463 // number of FPU stack slots in use; all but the topmost will
twisti@14626 464 // require saving if a slow case is necessary. Assumes argument is
twisti@14626 465 // on FP TOS; result is on FP TOS. No cpu registers are changed by
twisti@14626 466 // this code.
twisti@14626 467 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
twisti@14626 468
twisti@14626 469 // branch to L if FPU flag C2 is set/not set
twisti@14626 470 // tmp is a temporary register, if none is available use noreg
twisti@14626 471 void jC2 (Register tmp, Label& L);
twisti@14626 472 void jnC2(Register tmp, Label& L);
twisti@14626 473
twisti@14626 474 // Pop ST (ffree & fincstp combined)
twisti@14626 475 void fpop();
twisti@14626 476
twisti@14626 477 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
twisti@14626 478 void push_fTOS();
twisti@14626 479
twisti@14626 480 // pops double TOS element from CPU stack and pushes on FPU stack
twisti@14626 481 void pop_fTOS();
twisti@14626 482
twisti@14626 483 void empty_FPU_stack();
twisti@14626 484
twisti@14626 485 void push_IU_state();
twisti@14626 486 void pop_IU_state();
twisti@14626 487
twisti@14626 488 void push_FPU_state();
twisti@14626 489 void pop_FPU_state();
twisti@14626 490
twisti@14626 491 void push_CPU_state();
twisti@14626 492 void pop_CPU_state();
twisti@14626 493
twisti@14626 494 // Round up to a power of two
twisti@14626 495 void round_to(Register reg, int modulus);
twisti@14626 496
twisti@14626 497 // Callee saved registers handling
twisti@14626 498 void push_callee_saved_registers();
twisti@14626 499 void pop_callee_saved_registers();
twisti@14626 500
twisti@14626 501 // allocation
twisti@14626 502 void eden_allocate(
twisti@14626 503 Register obj, // result: pointer to object after successful allocation
twisti@14626 504 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 505 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 506 Register t1, // temp register
twisti@14626 507 Label& slow_case // continuation point if fast allocation fails
twisti@14626 508 );
twisti@14626 509 void tlab_allocate(
twisti@14626 510 Register obj, // result: pointer to object after successful allocation
twisti@14626 511 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
twisti@14626 512 int con_size_in_bytes, // object size in bytes if known at compile time
twisti@14626 513 Register t1, // temp register
twisti@14626 514 Register t2, // temp register
twisti@14626 515 Label& slow_case // continuation point if fast allocation fails
twisti@14626 516 );
twisti@14626 517 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
twisti@14626 518 void incr_allocated_bytes(Register thread,
twisti@14626 519 Register var_size_in_bytes, int con_size_in_bytes,
twisti@14626 520 Register t1 = noreg);
twisti@14626 521
twisti@14626 522 // interface method calling
twisti@14626 523 void lookup_interface_method(Register recv_klass,
twisti@14626 524 Register intf_klass,
twisti@14626 525 RegisterOrConstant itable_index,
twisti@14626 526 Register method_result,
twisti@14626 527 Register scan_temp,
twisti@14626 528 Label& no_such_interface);
twisti@14626 529
twisti@14626 530 // virtual method calling
twisti@14626 531 void lookup_virtual_method(Register recv_klass,
twisti@14626 532 RegisterOrConstant vtable_index,
twisti@14626 533 Register method_result);
twisti@14626 534
twisti@14626 535 // Test sub_klass against super_klass, with fast and slow paths.
twisti@14626 536
twisti@14626 537 // The fast path produces a tri-state answer: yes / no / maybe-slow.
twisti@14626 538 // One of the three labels can be NULL, meaning take the fall-through.
twisti@14626 539 // If super_check_offset is -1, the value is loaded up from super_klass.
twisti@14626 540 // No registers are killed, except temp_reg.
twisti@14626 541 void check_klass_subtype_fast_path(Register sub_klass,
twisti@14626 542 Register super_klass,
twisti@14626 543 Register temp_reg,
twisti@14626 544 Label* L_success,
twisti@14626 545 Label* L_failure,
twisti@14626 546 Label* L_slow_path,
twisti@14626 547 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
twisti@14626 548
twisti@14626 549 // The rest of the type check; must be wired to a corresponding fast path.
twisti@14626 550 // It does not repeat the fast path logic, so don't use it standalone.
twisti@14626 551 // The temp_reg and temp2_reg can be noreg, if no temps are available.
twisti@14626 552 // Updates the sub's secondary super cache as necessary.
twisti@14626 553 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
twisti@14626 554 void check_klass_subtype_slow_path(Register sub_klass,
twisti@14626 555 Register super_klass,
twisti@14626 556 Register temp_reg,
twisti@14626 557 Register temp2_reg,
twisti@14626 558 Label* L_success,
twisti@14626 559 Label* L_failure,
twisti@14626 560 bool set_cond_codes = false);
twisti@14626 561
twisti@14626 562 // Simplified, combined version, good for typical uses.
twisti@14626 563 // Falls through on failure.
twisti@14626 564 void check_klass_subtype(Register sub_klass,
twisti@14626 565 Register super_klass,
twisti@14626 566 Register temp_reg,
twisti@14626 567 Label& L_success);
twisti@14626 568
twisti@14626 569 // method handles (JSR 292)
twisti@14626 570 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
twisti@14626 571
twisti@14626 572 //----
twisti@14626 573 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
twisti@14626 574
twisti@14626 575 // Debugging
twisti@14626 576
twisti@14626 577 // only if +VerifyOops
twisti@14626 578 // TODO: Make these macros with file and line like sparc version!
twisti@14626 579 void verify_oop(Register reg, const char* s = "broken oop");
twisti@14626 580 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
twisti@14626 581
twisti@14626 582 // TODO: verify method and klass metadata (compare against vptr?)
twisti@14626 583 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
twisti@14626 584 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
twisti@14626 585
twisti@14626 586 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
twisti@14626 587 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
twisti@14626 588
twisti@14626 589 // only if +VerifyFPU
twisti@14626 590 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
twisti@14626 591
kvn@16624 592 // Verify or restore cpu control state after JNI call
kvn@16624 593 void restore_cpu_control_state_after_jni();
kvn@16624 594
twisti@14626 595 // prints msg, dumps registers and stops execution
twisti@14626 596 void stop(const char* msg);
twisti@14626 597
twisti@14626 598 // prints msg and continues
twisti@14626 599 void warn(const char* msg);
twisti@14626 600
twisti@14626 601 // dumps registers and other state
twisti@14626 602 void print_state();
twisti@14626 603
twisti@14626 604 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
twisti@14626 605 static void debug64(char* msg, int64_t pc, int64_t regs[]);
twisti@14626 606 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
twisti@14626 607 static void print_state64(int64_t pc, int64_t regs[]);
twisti@14626 608
twisti@14626 609 void os_breakpoint();
twisti@14626 610
twisti@14626 611 void untested() { stop("untested"); }
twisti@14626 612
twisti@14626 613 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
twisti@14626 614
twisti@14626 615 void should_not_reach_here() { stop("should not reach here"); }
twisti@14626 616
twisti@14626 617 void print_CPU_state();
twisti@14626 618
twisti@14626 619 // Stack overflow checking
twisti@14626 620 void bang_stack_with_offset(int offset) {
twisti@14626 621 // stack grows down, caller passes positive offset
twisti@14626 622 assert(offset > 0, "must bang with negative offset");
twisti@14626 623 movl(Address(rsp, (-offset)), rax);
twisti@14626 624 }
twisti@14626 625
twisti@14626 626 // Writes to stack successive pages until offset reached to check for
twisti@14626 627 // stack overflow + shadow pages. Also, clobbers tmp
twisti@14626 628 void bang_stack_size(Register size, Register tmp);
twisti@14626 629
twisti@14626 630 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
twisti@14626 631 Register tmp,
twisti@14626 632 int offset);
twisti@14626 633
twisti@14626 634 // Support for serializing memory accesses between threads
twisti@14626 635 void serialize_memory(Register thread, Register tmp);
twisti@14626 636
twisti@14626 637 void verify_tlab();
twisti@14626 638
twisti@14626 639 // Biased locking support
twisti@14626 640 // lock_reg and obj_reg must be loaded up with the appropriate values.
twisti@14626 641 // swap_reg must be rax, and is killed.
twisti@14626 642 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
twisti@14626 643 // be killed; if not supplied, push/pop will be used internally to
twisti@14626 644 // allocate a temporary (inefficient, avoid if possible).
twisti@14626 645 // Optional slow case is for implementations (interpreter and C1) which branch to
twisti@14626 646 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
twisti@14626 647 // Returns offset of first potentially-faulting instruction for null
twisti@14626 648 // check info (currently consumed only by C1). If
twisti@14626 649 // swap_reg_contains_mark is true then returns -1 as it is assumed
twisti@14626 650 // the calling code has already passed any potential faults.
twisti@14626 651 int biased_locking_enter(Register lock_reg, Register obj_reg,
twisti@14626 652 Register swap_reg, Register tmp_reg,
twisti@14626 653 bool swap_reg_contains_mark,
twisti@14626 654 Label& done, Label* slow_case = NULL,
twisti@14626 655 BiasedLockingCounters* counters = NULL);
twisti@14626 656 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
kvn@22910 657 #ifdef COMPILER2
kvn@22910 658 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
kvn@22910 659 // See full desription in macroAssembler_x86.cpp.
kvn@23491 660 void fast_lock(Register obj, Register box, Register tmp,
kvn@23491 661 Register scr, Register cx1, Register cx2,
kvn@23491 662 BiasedLockingCounters* counters,
kvn@23491 663 RTMLockingCounters* rtm_counters,
kvn@23491 664 RTMLockingCounters* stack_rtm_counters,
kvn@23491 665 Metadata* method_data,
kvn@23491 666 bool use_rtm, bool profile_rtm);
kvn@23491 667 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
kvn@23491 668 #if INCLUDE_RTM_OPT
kvn@23491 669 void rtm_counters_update(Register abort_status, Register rtm_counters);
kvn@23491 670 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
kvn@23491 671 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
kvn@23491 672 RTMLockingCounters* rtm_counters,
kvn@23491 673 Metadata* method_data);
kvn@23491 674 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
kvn@23491 675 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
kvn@23491 676 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
kvn@23491 677 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
kvn@23491 678 void rtm_stack_locking(Register obj, Register tmp, Register scr,
kvn@23491 679 Register retry_on_abort_count,
kvn@23491 680 RTMLockingCounters* stack_rtm_counters,
kvn@23491 681 Metadata* method_data, bool profile_rtm,
kvn@23491 682 Label& DONE_LABEL, Label& IsInflated);
kvn@23491 683 void rtm_inflated_locking(Register obj, Register box, Register tmp,
kvn@23491 684 Register scr, Register retry_on_busy_count,
kvn@23491 685 Register retry_on_abort_count,
kvn@23491 686 RTMLockingCounters* rtm_counters,
kvn@23491 687 Metadata* method_data, bool profile_rtm,
kvn@23491 688 Label& DONE_LABEL);
kvn@23491 689 #endif
kvn@22910 690 #endif
twisti@14626 691
twisti@14626 692 Condition negate_condition(Condition cond);
twisti@14626 693
twisti@14626 694 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
twisti@14626 695 // operands. In general the names are modified to avoid hiding the instruction in Assembler
twisti@14626 696 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
twisti@14626 697 // here in MacroAssembler. The major exception to this rule is call
twisti@14626 698
twisti@14626 699 // Arithmetics
twisti@14626 700
twisti@14626 701
twisti@14626 702 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
twisti@14626 703 void addptr(Address dst, Register src);
twisti@14626 704
twisti@14626 705 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
twisti@14626 706 void addptr(Register dst, int32_t src);
twisti@14626 707 void addptr(Register dst, Register src);
twisti@14626 708 void addptr(Register dst, RegisterOrConstant src) {
twisti@14626 709 if (src.is_constant()) addptr(dst, (int) src.as_constant());
twisti@14626 710 else addptr(dst, src.as_register());
twisti@14626 711 }
twisti@14626 712
twisti@14626 713 void andptr(Register dst, int32_t src);
twisti@14626 714 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
twisti@14626 715
twisti@14626 716 void cmp8(AddressLiteral src1, int imm);
twisti@14626 717
twisti@14626 718 // renamed to drag out the casting of address to int32_t/intptr_t
twisti@14626 719 void cmp32(Register src1, int32_t imm);
twisti@14626 720
twisti@14626 721 void cmp32(AddressLiteral src1, int32_t imm);
twisti@14626 722 // compare reg - mem, or reg - &mem
twisti@14626 723 void cmp32(Register src1, AddressLiteral src2);
twisti@14626 724
twisti@14626 725 void cmp32(Register src1, Address src2);
twisti@14626 726
twisti@14626 727 #ifndef _LP64
twisti@14626 728 void cmpklass(Address dst, Metadata* obj);
twisti@14626 729 void cmpklass(Register dst, Metadata* obj);
twisti@14626 730 void cmpoop(Address dst, jobject obj);
twisti@14626 731 void cmpoop(Register dst, jobject obj);
twisti@14626 732 #endif // _LP64
twisti@14626 733
twisti@14626 734 // NOTE src2 must be the lval. This is NOT an mem-mem compare
twisti@14626 735 void cmpptr(Address src1, AddressLiteral src2);
twisti@14626 736
twisti@14626 737 void cmpptr(Register src1, AddressLiteral src2);
twisti@14626 738
twisti@14626 739 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 740 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 741 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 742
twisti@14626 743 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 744 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
twisti@14626 745
twisti@14626 746 // cmp64 to avoild hiding cmpq
twisti@14626 747 void cmp64(Register src1, AddressLiteral src);
twisti@14626 748
twisti@14626 749 void cmpxchgptr(Register reg, Address adr);
twisti@14626 750
twisti@14626 751 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
twisti@14626 752
twisti@14626 753
twisti@14626 754 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
kvn@23491 755 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
twisti@14626 756
twisti@14626 757
twisti@14626 758 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
twisti@14626 759
twisti@14626 760 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
twisti@14626 761
twisti@14626 762 void shlptr(Register dst, int32_t shift);
twisti@14626 763 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
twisti@14626 764
twisti@14626 765 void shrptr(Register dst, int32_t shift);
twisti@14626 766 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
twisti@14626 767
twisti@14626 768 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
twisti@14626 769 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
twisti@14626 770
twisti@14626 771 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 772
twisti@14626 773 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
twisti@14626 774 void subptr(Register dst, int32_t src);
twisti@14626 775 // Force generation of a 4 byte immediate value even if it fits into 8bit
twisti@14626 776 void subptr_imm32(Register dst, int32_t src);
twisti@14626 777 void subptr(Register dst, Register src);
twisti@14626 778 void subptr(Register dst, RegisterOrConstant src) {
twisti@14626 779 if (src.is_constant()) subptr(dst, (int) src.as_constant());
twisti@14626 780 else subptr(dst, src.as_register());
twisti@14626 781 }
twisti@14626 782
twisti@14626 783 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 784 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
twisti@14626 785
twisti@14626 786 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 787 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
twisti@14626 788
twisti@14626 789 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
twisti@14626 790
twisti@14626 791
twisti@14626 792
twisti@14626 793 // Helper functions for statistics gathering.
twisti@14626 794 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
twisti@14626 795 void cond_inc32(Condition cond, AddressLiteral counter_addr);
twisti@14626 796 // Unconditional atomic increment.
kvn@23491 797 void atomic_incl(Address counter_addr);
kvn@23491 798 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 799 #ifdef _LP64
kvn@23491 800 void atomic_incq(Address counter_addr);
kvn@23491 801 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
kvn@23491 802 #endif
kvn@23491 803 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
kvn@23491 804 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
twisti@14626 805
twisti@14626 806 void lea(Register dst, AddressLiteral adr);
twisti@14626 807 void lea(Address dst, AddressLiteral adr);
twisti@14626 808 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
twisti@14626 809
twisti@14626 810 void leal32(Register dst, Address src) { leal(dst, src); }
twisti@14626 811
twisti@14626 812 // Import other testl() methods from the parent class or else
twisti@14626 813 // they will be hidden by the following overriding declaration.
twisti@14626 814 using Assembler::testl;
twisti@14626 815 void testl(Register dst, AddressLiteral src);
twisti@14626 816
twisti@14626 817 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 818 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
twisti@14626 819 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
roland@20702 820 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
twisti@14626 821
twisti@14626 822 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
twisti@14626 823 void testptr(Register src1, Register src2);
twisti@14626 824
twisti@14626 825 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 826 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
twisti@14626 827
twisti@14626 828 // Calls
twisti@14626 829
twisti@14626 830 void call(Label& L, relocInfo::relocType rtype);
twisti@14626 831 void call(Register entry);
twisti@14626 832
twisti@14626 833 // NOTE: this call tranfers to the effective address of entry NOT
twisti@14626 834 // the address contained by entry. This is because this is more natural
twisti@14626 835 // for jumps/calls.
twisti@14626 836 void call(AddressLiteral entry);
twisti@14626 837
twisti@14626 838 // Emit the CompiledIC call idiom
twisti@14626 839 void ic_call(address entry);
twisti@14626 840
twisti@14626 841 // Jumps
twisti@14626 842
twisti@14626 843 // NOTE: these jumps tranfer to the effective address of dst NOT
twisti@14626 844 // the address contained by dst. This is because this is more natural
twisti@14626 845 // for jumps/calls.
twisti@14626 846 void jump(AddressLiteral dst);
twisti@14626 847 void jump_cc(Condition cc, AddressLiteral dst);
twisti@14626 848
twisti@14626 849 // 32bit can do a case table jump in one instruction but we no longer allow the base
twisti@14626 850 // to be installed in the Address class. This jump will tranfers to the address
twisti@14626 851 // contained in the location described by entry (not the address of entry)
twisti@14626 852 void jump(ArrayAddress entry);
twisti@14626 853
twisti@14626 854 // Floating
twisti@14626 855
twisti@14626 856 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
twisti@14626 857 void andpd(XMMRegister dst, AddressLiteral src);
twisti@14626 858
twisti@14626 859 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
twisti@14626 860 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
twisti@14626 861 void andps(XMMRegister dst, AddressLiteral src);
twisti@14626 862
twisti@14626 863 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
twisti@14626 864 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
twisti@14626 865 void comiss(XMMRegister dst, AddressLiteral src);
twisti@14626 866
twisti@14626 867 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
twisti@14626 868 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
twisti@14626 869 void comisd(XMMRegister dst, AddressLiteral src);
twisti@14626 870
twisti@14626 871 void fadd_s(Address src) { Assembler::fadd_s(src); }
twisti@14626 872 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
twisti@14626 873
twisti@14626 874 void fldcw(Address src) { Assembler::fldcw(src); }
twisti@14626 875 void fldcw(AddressLiteral src);
twisti@14626 876
twisti@14626 877 void fld_s(int index) { Assembler::fld_s(index); }
twisti@14626 878 void fld_s(Address src) { Assembler::fld_s(src); }
twisti@14626 879 void fld_s(AddressLiteral src);
twisti@14626 880
twisti@14626 881 void fld_d(Address src) { Assembler::fld_d(src); }
twisti@14626 882 void fld_d(AddressLiteral src);
twisti@14626 883
twisti@14626 884 void fld_x(Address src) { Assembler::fld_x(src); }
twisti@14626 885 void fld_x(AddressLiteral src);
twisti@14626 886
twisti@14626 887 void fmul_s(Address src) { Assembler::fmul_s(src); }
twisti@14626 888 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
twisti@14626 889
twisti@14626 890 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
twisti@14626 891 void ldmxcsr(AddressLiteral src);
twisti@14626 892
twisti@14626 893 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
twisti@14626 894 // all corner cases and may result in NaN and require fallback to a
twisti@14626 895 // runtime call.
twisti@14626 896 void fast_pow();
twisti@14626 897 void fast_exp();
twisti@14626 898 void increase_precision();
twisti@14626 899 void restore_precision();
twisti@14626 900
twisti@14626 901 // computes exp(x). Fallback to runtime call included.
twisti@14626 902 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
twisti@14626 903 // computes pow(x,y). Fallback to runtime call included.
twisti@14626 904 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
twisti@14626 905
twisti@14626 906 private:
twisti@14626 907
twisti@14626 908 // call runtime as a fallback for trig functions and pow/exp.
twisti@14626 909 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
twisti@14626 910
twisti@14626 911 // computes 2^(Ylog2X); Ylog2X in ST(0)
twisti@14626 912 void pow_exp_core_encoding();
twisti@14626 913
twisti@14626 914 // computes pow(x,y) or exp(x). Fallback to runtime call included.
twisti@14626 915 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
twisti@14626 916
twisti@14626 917 // these are private because users should be doing movflt/movdbl
twisti@14626 918
twisti@14626 919 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 920 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
twisti@14626 921 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
twisti@14626 922 void movss(XMMRegister dst, AddressLiteral src);
twisti@14626 923
twisti@14626 924 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
twisti@14626 925 void movlpd(XMMRegister dst, AddressLiteral src);
twisti@14626 926
twisti@14626 927 public:
twisti@14626 928
twisti@14626 929 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
twisti@14626 930 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
twisti@14626 931 void addsd(XMMRegister dst, AddressLiteral src);
twisti@14626 932
twisti@14626 933 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
twisti@14626 934 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
twisti@14626 935 void addss(XMMRegister dst, AddressLiteral src);
twisti@14626 936
twisti@14626 937 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
twisti@14626 938 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
twisti@14626 939 void divsd(XMMRegister dst, AddressLiteral src);
twisti@14626 940
twisti@14626 941 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
twisti@14626 942 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
twisti@14626 943 void divss(XMMRegister dst, AddressLiteral src);
twisti@14626 944
twisti@14626 945 // Move Unaligned Double Quadword
twisti@14626 946 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
twisti@14626 947 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
twisti@14626 948 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
twisti@14626 949 void movdqu(XMMRegister dst, AddressLiteral src);
twisti@14626 950
drchase@18507 951 // Move Aligned Double Quadword
drchase@18507 952 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
drchase@18507 953 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
drchase@18507 954 void movdqa(XMMRegister dst, AddressLiteral src);
drchase@18507 955
twisti@14626 956 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 957 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
twisti@14626 958 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
twisti@14626 959 void movsd(XMMRegister dst, AddressLiteral src);
twisti@14626 960
twisti@14626 961 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
twisti@14626 962 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
twisti@14626 963 void mulsd(XMMRegister dst, AddressLiteral src);
twisti@14626 964
twisti@14626 965 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
twisti@14626 966 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
twisti@14626 967 void mulss(XMMRegister dst, AddressLiteral src);
twisti@14626 968
twisti@14626 969 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
twisti@14626 970 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
twisti@14626 971 void sqrtsd(XMMRegister dst, AddressLiteral src);
twisti@14626 972
twisti@14626 973 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
twisti@14626 974 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
twisti@14626 975 void sqrtss(XMMRegister dst, AddressLiteral src);
twisti@14626 976
twisti@14626 977 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
twisti@14626 978 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
twisti@14626 979 void subsd(XMMRegister dst, AddressLiteral src);
twisti@14626 980
twisti@14626 981 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
twisti@14626 982 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
twisti@14626 983 void subss(XMMRegister dst, AddressLiteral src);
twisti@14626 984
twisti@14626 985 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
twisti@14626 986 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
twisti@14626 987 void ucomiss(XMMRegister dst, AddressLiteral src);
twisti@14626 988
twisti@14626 989 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
twisti@14626 990 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
twisti@14626 991 void ucomisd(XMMRegister dst, AddressLiteral src);
twisti@14626 992
twisti@14626 993 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
twisti@14626 994 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
twisti@14626 995 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
twisti@14626 996 void xorpd(XMMRegister dst, AddressLiteral src);
twisti@14626 997
twisti@14626 998 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
twisti@14626 999 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
twisti@14626 1000 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
twisti@14626 1001 void xorps(XMMRegister dst, AddressLiteral src);
twisti@14626 1002
twisti@14626 1003 // Shuffle Bytes
twisti@14626 1004 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
twisti@14626 1005 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
twisti@14626 1006 void pshufb(XMMRegister dst, AddressLiteral src);
twisti@14626 1007 // AVX 3-operands instructions
twisti@14626 1008
twisti@14626 1009 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1010 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
twisti@14626 1011 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1012
twisti@14626 1013 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1014 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
twisti@14626 1015 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1016
twisti@14626 1017 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
twisti@14626 1018 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
twisti@14626 1019 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@14626 1020
twisti@14626 1021 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
twisti@14626 1022 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
twisti@14626 1023 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@14626 1024
twisti@14626 1025 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1026 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
twisti@14626 1027 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1028
twisti@14626 1029 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1030 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
twisti@14626 1031 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1032
twisti@14626 1033 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1034 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
twisti@14626 1035 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1036
twisti@14626 1037 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1038 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
twisti@14626 1039 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1040
twisti@14626 1041 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1042 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
twisti@14626 1043 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1044
twisti@14626 1045 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1046 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
twisti@14626 1047 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
twisti@14626 1048
twisti@14626 1049 // AVX Vector instructions
twisti@14626 1050
twisti@14626 1051 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
twisti@14626 1052 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
twisti@14626 1053 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@14626 1054
twisti@14626 1055 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
twisti@14626 1056 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
twisti@14626 1057 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
twisti@14626 1058
twisti@14626 1059 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
twisti@14626 1060 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
twisti@14626 1061 Assembler::vpxor(dst, nds, src, vector256);
twisti@14626 1062 else
twisti@14626 1063 Assembler::vxorpd(dst, nds, src, vector256);
twisti@14626 1064 }
twisti@14626 1065 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
twisti@14626 1066 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
twisti@14626 1067 Assembler::vpxor(dst, nds, src, vector256);
twisti@14626 1068 else
twisti@14626 1069 Assembler::vxorpd(dst, nds, src, vector256);
twisti@14626 1070 }
twisti@14626 1071
kvn@15117 1072 // Simple version for AVX2 256bit vectors
kvn@15117 1073 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1074 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
kvn@15117 1075
twisti@14626 1076 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
twisti@14626 1077 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
twisti@14626 1078 if (UseAVX > 1) // vinserti128h is available only in AVX2
twisti@14626 1079 Assembler::vinserti128h(dst, nds, src);
twisti@14626 1080 else
twisti@14626 1081 Assembler::vinsertf128h(dst, nds, src);
twisti@14626 1082 }
twisti@14626 1083
drchase@18507 1084 // Carry-Less Multiplication Quadword
drchase@18507 1085 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1086 // 0x00 - multiply lower 64 bits [0:63]
drchase@18507 1087 Assembler::vpclmulqdq(dst, nds, src, 0x00);
drchase@18507 1088 }
drchase@18507 1089 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
drchase@18507 1090 // 0x11 - multiply upper 64 bits [64:127]
drchase@18507 1091 Assembler::vpclmulqdq(dst, nds, src, 0x11);
drchase@18507 1092 }
drchase@18507 1093
twisti@14626 1094 // Data
twisti@14626 1095
twisti@14626 1096 void cmov32( Condition cc, Register dst, Address src);
twisti@14626 1097 void cmov32( Condition cc, Register dst, Register src);
twisti@14626 1098
twisti@14626 1099 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
twisti@14626 1100
twisti@14626 1101 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1102 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
twisti@14626 1103
twisti@14626 1104 void movoop(Register dst, jobject obj);
twisti@14626 1105 void movoop(Address dst, jobject obj);
twisti@14626 1106
twisti@14626 1107 void mov_metadata(Register dst, Metadata* obj);
twisti@14626 1108 void mov_metadata(Address dst, Metadata* obj);
twisti@14626 1109
twisti@14626 1110 void movptr(ArrayAddress dst, Register src);
twisti@14626 1111 // can this do an lea?
twisti@14626 1112 void movptr(Register dst, ArrayAddress src);
twisti@14626 1113
twisti@14626 1114 void movptr(Register dst, Address src);
twisti@14626 1115
kvn@23491 1116 #ifdef _LP64
kvn@23491 1117 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
kvn@23491 1118 #else
kvn@23491 1119 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
kvn@23491 1120 #endif
twisti@14626 1121
twisti@14626 1122 void movptr(Register dst, intptr_t src);
twisti@14626 1123 void movptr(Register dst, Register src);
twisti@14626 1124 void movptr(Address dst, intptr_t src);
twisti@14626 1125
twisti@14626 1126 void movptr(Address dst, Register src);
twisti@14626 1127
twisti@14626 1128 void movptr(Register dst, RegisterOrConstant src) {
twisti@14626 1129 if (src.is_constant()) movptr(dst, src.as_constant());
twisti@14626 1130 else movptr(dst, src.as_register());
twisti@14626 1131 }
twisti@14626 1132
twisti@14626 1133 #ifdef _LP64
twisti@14626 1134 // Generally the next two are only used for moving NULL
twisti@14626 1135 // Although there are situations in initializing the mark word where
twisti@14626 1136 // they could be used. They are dangerous.
twisti@14626 1137
twisti@14626 1138 // They only exist on LP64 so that int32_t and intptr_t are not the same
twisti@14626 1139 // and we have ambiguous declarations.
twisti@14626 1140
twisti@14626 1141 void movptr(Address dst, int32_t imm32);
twisti@14626 1142 void movptr(Register dst, int32_t imm32);
twisti@14626 1143 #endif // _LP64
twisti@14626 1144
twisti@14626 1145 // to avoid hiding movl
twisti@14626 1146 void mov32(AddressLiteral dst, Register src);
twisti@14626 1147 void mov32(Register dst, AddressLiteral src);
twisti@14626 1148
twisti@14626 1149 // to avoid hiding movb
twisti@14626 1150 void movbyte(ArrayAddress dst, int src);
twisti@14626 1151
twisti@14626 1152 // Import other mov() methods from the parent class or else
twisti@14626 1153 // they will be hidden by the following overriding declaration.
twisti@14626 1154 using Assembler::movdl;
twisti@14626 1155 using Assembler::movq;
twisti@14626 1156 void movdl(XMMRegister dst, AddressLiteral src);
twisti@14626 1157 void movq(XMMRegister dst, AddressLiteral src);
twisti@14626 1158
twisti@14626 1159 // Can push value or effective address
twisti@14626 1160 void pushptr(AddressLiteral src);
twisti@14626 1161
twisti@14626 1162 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
twisti@14626 1163 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
twisti@14626 1164
twisti@14626 1165 void pushoop(jobject obj);
twisti@14626 1166 void pushklass(Metadata* obj);
twisti@14626 1167
twisti@14626 1168 // sign extend as need a l to ptr sized element
twisti@14626 1169 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
twisti@14626 1170 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
twisti@14626 1171
twisti@14626 1172 // C2 compiled method's prolog code.
twisti@14626 1173 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
twisti@14626 1174
kvn@15114 1175 // clear memory of size 'cnt' qwords, starting at 'base'.
kvn@15114 1176 void clear_mem(Register base, Register cnt, Register rtmp);
kvn@15114 1177
twisti@14626 1178 // IndexOf strings.
twisti@14626 1179 // Small strings are loaded through stack if they cross page boundary.
twisti@14626 1180 void string_indexof(Register str1, Register str2,
twisti@14626 1181 Register cnt1, Register cnt2,
twisti@14626 1182 int int_cnt2, Register result,
twisti@14626 1183 XMMRegister vec, Register tmp);
twisti@14626 1184
twisti@14626 1185 // IndexOf for constant substrings with size >= 8 elements
twisti@14626 1186 // which don't need to be loaded through stack.
twisti@14626 1187 void string_indexofC8(Register str1, Register str2,
twisti@14626 1188 Register cnt1, Register cnt2,
twisti@14626 1189 int int_cnt2, Register result,
twisti@14626 1190 XMMRegister vec, Register tmp);
twisti@14626 1191
twisti@14626 1192 // Smallest code: we don't need to load through stack,
twisti@14626 1193 // check string tail.
twisti@14626 1194
twisti@14626 1195 // Compare strings.
twisti@14626 1196 void string_compare(Register str1, Register str2,
twisti@14626 1197 Register cnt1, Register cnt2, Register result,
twisti@14626 1198 XMMRegister vec1);
twisti@14626 1199
twisti@14626 1200 // Compare char[] arrays.
twisti@14626 1201 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
twisti@14626 1202 Register limit, Register result, Register chr,
twisti@14626 1203 XMMRegister vec1, XMMRegister vec2);
twisti@14626 1204
twisti@14626 1205 // Fill primitive arrays
twisti@14626 1206 void generate_fill(BasicType t, bool aligned,
twisti@14626 1207 Register to, Register value, Register count,
twisti@14626 1208 Register rtmp, XMMRegister xtmp);
twisti@14626 1209
kvn@15242 1210 void encode_iso_array(Register src, Register dst, Register len,
kvn@15242 1211 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
kvn@15242 1212 XMMRegister tmp4, Register tmp5, Register result);
kvn@15242 1213
drchase@18507 1214 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
drchase@18507 1215 void update_byte_crc32(Register crc, Register val, Register table);
drchase@18507 1216 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
drchase@18507 1217 // Fold 128-bit data chunk
drchase@18507 1218 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
drchase@18507 1219 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
drchase@18507 1220 // Fold 8-bit data
drchase@18507 1221 void fold_8bit_crc32(Register crc, Register table, Register tmp);
drchase@18507 1222 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
drchase@18507 1223
twisti@14626 1224 #undef VIRTUAL
twisti@14626 1225
twisti@14626 1226 };
twisti@14626 1227
twisti@14626 1228 /**
twisti@14626 1229 * class SkipIfEqual:
twisti@14626 1230 *
twisti@14626 1231 * Instantiating this class will result in assembly code being output that will
twisti@14626 1232 * jump around any code emitted between the creation of the instance and it's
twisti@14626 1233 * automatic destruction at the end of a scope block, depending on the value of
twisti@14626 1234 * the flag passed to the constructor, which will be checked at run-time.
twisti@14626 1235 */
twisti@14626 1236 class SkipIfEqual {
twisti@14626 1237 private:
twisti@14626 1238 MacroAssembler* _masm;
twisti@14626 1239 Label _label;
twisti@14626 1240
twisti@14626 1241 public:
twisti@14626 1242 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
twisti@14626 1243 ~SkipIfEqual();
twisti@14626 1244 };
twisti@14626 1245
twisti@14626 1246 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP