diff src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp @ 51278:409bfb0c071e

8205341: AARCH64: Clean up duplicate uzp1 & uzp2 instruction definition Reviewed-by: aph
author dchuyko
date Tue, 19 Jun 2018 19:21:30 +0300
parents 66aa15778c5a
children db0a17475826
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	Tue Jun 19 08:19:54 2018 -0700
+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	Tue Jun 19 19:21:30 2018 +0300
@@ -3352,12 +3352,12 @@
       pmull2(v19, T8H, v0, v4, T16B);
       pmull2(v17, T8H, v0, v6, T16B);
 
-      uzp1(v24, v20, v22, T8H);
-      uzp2(v25, v20, v22, T8H);
+      uzp1(v24, T8H, v20, v22);
+      uzp2(v25, T8H, v20, v22);
       eor(v20, T16B, v24, v25);
 
-      uzp1(v26, v16, v18, T8H);
-      uzp2(v27, v16, v18, T8H);
+      uzp1(v26, T8H, v16, v18);
+      uzp2(v27, T8H, v16, v18);
       eor(v16, T16B, v26, v27);
 
       ushll2(v22, T4S, v20, T8H, 8);
@@ -3371,8 +3371,8 @@
       eor(v20, T16B, v21, v20);
       eor(v16, T16B, v17, v16);
 
-      uzp1(v17, v16, v20, T2D);
-      uzp2(v21, v16, v20, T2D);
+      uzp1(v17, T2D, v16, v20);
+      uzp2(v21, T2D, v16, v20);
       eor(v17, T16B, v17, v21);
 
       ushll2(v20, T2D, v17, T4S, 16);
@@ -3381,8 +3381,8 @@
       eor(v20, T16B, v20, v22);
       eor(v16, T16B, v16, v18);
 
-      uzp1(v17, v20, v16, T2D);
-      uzp2(v21, v20, v16, T2D);
+      uzp1(v17, T2D, v20, v16);
+      uzp2(v21, T2D, v20, v16);
       eor(v28, T16B, v17, v21);
 
       pmull(v22, T8H, v1, v5, T8B);
@@ -3397,12 +3397,12 @@
 
       ld1(v0, v1, T2D, post(buf, 32));
 
-      uzp1(v24, v20, v22, T8H);
-      uzp2(v25, v20, v22, T8H);
+      uzp1(v24, T8H, v20, v22);
+      uzp2(v25, T8H, v20, v22);
       eor(v20, T16B, v24, v25);
 
-      uzp1(v26, v16, v18, T8H);
-      uzp2(v27, v16, v18, T8H);
+      uzp1(v26, T8H, v16, v18);
+      uzp2(v27, T8H, v16, v18);
       eor(v16, T16B, v26, v27);
 
       ushll2(v22, T4S, v20, T8H, 8);
@@ -3416,8 +3416,8 @@
       eor(v20, T16B, v21, v20);
       eor(v16, T16B, v17, v16);
 
-      uzp1(v17, v16, v20, T2D);
-      uzp2(v21, v16, v20, T2D);
+      uzp1(v17, T2D, v16, v20);
+      uzp2(v21, T2D, v16, v20);
       eor(v16, T16B, v17, v21);
 
       ushll2(v20, T2D, v16, T4S, 16);
@@ -3426,8 +3426,8 @@
       eor(v20, T16B, v22, v20);
       eor(v16, T16B, v16, v18);
 
-      uzp1(v17, v20, v16, T2D);
-      uzp2(v21, v20, v16, T2D);
+      uzp1(v17, T2D, v20, v16);
+      uzp2(v21, T2D, v20, v16);
       eor(v20, T16B, v17, v21);
 
       shl(v16, T2D, v28, 1);