changeset 46378:4ccca1fdf627

8160748: Inconsistent types for ideal_reg Summary: Made ideal_reg consistently uint. Reviewed-by: kvn, iveresov
author kbarrett
date Wed, 12 Apr 2017 01:31:36 -0400
parents e2660702788f
children 43ec76e10184
files hotspot/src/cpu/aarch64/vm/aarch64.ad hotspot/src/cpu/arm/vm/arm.ad hotspot/src/cpu/ppc/vm/ppc.ad hotspot/src/cpu/s390/vm/s390.ad hotspot/src/cpu/sparc/vm/sparc.ad hotspot/src/cpu/x86/vm/x86.ad hotspot/src/share/vm/adlc/output_c.cpp hotspot/src/share/vm/opto/chaitin.cpp hotspot/src/share/vm/opto/coalesce.cpp hotspot/src/share/vm/opto/matcher.cpp hotspot/src/share/vm/opto/matcher.hpp hotspot/src/share/vm/opto/reg_split.cpp hotspot/src/share/vm/opto/type.cpp hotspot/src/share/vm/opto/type.hpp
diffstat 14 files changed, 53 insertions(+), 53 deletions(-) [+]
line wrap: on
line diff
--- a/hotspot/src/cpu/aarch64/vm/aarch64.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
 // Copyright (c) 2014, Red Hat Inc. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
@@ -3564,7 +3564,7 @@
 }
 
 // Vector ideal reg.
-const int Matcher::vector_ideal_reg(int len) {
+const uint Matcher::vector_ideal_reg(int len) {
   switch(len) {
     case  8: return Op_VecD;
     case 16: return Op_VecX;
@@ -3573,7 +3573,7 @@
   return 0;
 }
 
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   return Op_VecX;
 }
 
--- a/hotspot/src/cpu/arm/vm/arm.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/arm/vm/arm.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -1122,7 +1122,7 @@
 }
 
 // Vector ideal reg corresponding to specified size in bytes
-const int Matcher::vector_ideal_reg(int size) {
+const uint Matcher::vector_ideal_reg(int size) {
   assert(MaxVectorSize >= size, "");
   switch(size) {
     case  8: return Op_VecD;
@@ -1132,7 +1132,7 @@
   return 0;
 }
 
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   return vector_ideal_reg(size);
 }
 
--- a/hotspot/src/cpu/ppc/vm/ppc.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/ppc/vm/ppc.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
 // Copyright (c) 2012, 2016 SAP SE. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
@@ -2053,12 +2053,12 @@
 }
 
 // Vector ideal reg.
-const int Matcher::vector_ideal_reg(int size) {
+const uint Matcher::vector_ideal_reg(int size) {
   assert(MaxVectorSize == 8 && size == 8, "");
   return Op_RegL;
 }
 
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   fatal("vector shift is not supported");
   return Node::NotAMachineReg;
 }
--- a/hotspot/src/cpu/s390/vm/s390.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/s390/vm/s390.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
 // Copyright (c) 2016 SAP SE. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
@@ -1562,7 +1562,7 @@
 }
 
 // Vector ideal reg.
-const int Matcher::vector_ideal_reg(int size) {
+const uint Matcher::vector_ideal_reg(int size) {
   assert(MaxVectorSize == 8 && size == 8, "");
   return Op_RegL;
 }
@@ -1577,7 +1577,7 @@
   return max_vector_size(bt); // Same as max.
 }
 
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   fatal("vector shift is not supported");
   return Node::NotAMachineReg;
 }
--- a/hotspot/src/cpu/sparc/vm/sparc.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/sparc/vm/sparc.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -1919,12 +1919,12 @@
 }
 
 // Vector ideal reg
-const int Matcher::vector_ideal_reg(int size) {
+const uint Matcher::vector_ideal_reg(int size) {
   assert(MaxVectorSize == 8, "");
   return Op_RegD;
 }
 
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   fatal("vector shift is not supported");
   return Node::NotAMachineReg;
 }
--- a/hotspot/src/cpu/x86/vm/x86.ad	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/x86.ad	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -1387,7 +1387,7 @@
 }
 
 // Vector ideal reg corresponding to specidied size in bytes
-const int Matcher::vector_ideal_reg(int size) {
+const uint Matcher::vector_ideal_reg(int size) {
   assert(MaxVectorSize >= size, "");
   switch(size) {
     case  4: return Op_VecS;
@@ -1401,7 +1401,7 @@
 }
 
 // Only lowest bits of xmm reg are used for vector shift count.
-const int Matcher::vector_shift_count_ideal_reg(int size) {
+const uint Matcher::vector_shift_count_ideal_reg(int size) {
   return Op_VecS;
 }
 
--- a/hotspot/src/share/vm/adlc/output_c.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/adlc/output_c.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -4172,11 +4172,11 @@
   fprintf(fp_cpp,"%s\n", _frame->_c_calling_convention);
   fprintf(fp_cpp,"}\n\n");
   // Java Return Value Location
-  fprintf(fp_cpp,"OptoRegPair Matcher::return_value(int ideal_reg, bool is_outgoing) {\n");
+  fprintf(fp_cpp,"OptoRegPair Matcher::return_value(uint ideal_reg, bool is_outgoing) {\n");
   fprintf(fp_cpp,"%s\n", _frame->_return_value);
   fprintf(fp_cpp,"}\n\n");
   // Native Return Value Location
-  fprintf(fp_cpp,"OptoRegPair Matcher::c_return_value(int ideal_reg, bool is_outgoing) {\n");
+  fprintf(fp_cpp,"OptoRegPair Matcher::c_return_value(uint ideal_reg, bool is_outgoing) {\n");
   fprintf(fp_cpp,"%s\n", _frame->_c_return_value);
   fprintf(fp_cpp,"}\n\n");
 
--- a/hotspot/src/share/vm/opto/chaitin.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/chaitin.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -793,7 +793,7 @@
         const RegMask &rm = n->out_RegMask();
         lrg.AND( rm );
 
-        int ireg = n->ideal_reg();
+        uint ireg = n->ideal_reg();
         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
                 "oops must be in Op_RegP's" );
 
@@ -1013,7 +1013,7 @@
 
         // Check for bound register masks
         const RegMask &lrgmask = lrg.mask();
-        int kreg = n->in(k)->ideal_reg();
+        uint kreg = n->in(k)->ideal_reg();
         bool is_vect = RegMask::is_vector(kreg);
         assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
                is_vect || kreg == Op_RegD || kreg == Op_RegL,
--- a/hotspot/src/share/vm/opto/coalesce.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/coalesce.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -292,9 +292,9 @@
               // Copy any flags as well
               _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
             } else {
-              int ireg = m->ideal_reg();
+              uint ireg = m->ideal_reg();
               if (ireg == 0 || ireg == Op_RegFlags) {
-                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
+                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
                        m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::PhiInput));
                 C->record_method_not_compilable("attempted to spill a non-spillable item");
                 return;
@@ -333,9 +333,9 @@
               b->insert_node(copy, l++);
               l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
             } else {
-              int ireg = m->ideal_reg();
+              uint ireg = m->ideal_reg();
               if (ireg == 0 || ireg == Op_RegFlags) {
-                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
+                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
                        m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::TwoAddress));
                 C->record_method_not_compilable("attempted to spill a non-spillable item");
                 return;
@@ -387,9 +387,9 @@
               if( k < b->_num_succs )
                 continue;     // Live out; do not pre-split
               // Split the lrg at this use
-              int ireg = inp->ideal_reg();
+              uint ireg = inp->ideal_reg();
               if (ireg == 0 || ireg == Op_RegFlags) {
-                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
+                assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %u, spill_type: %s",
                        inp->_idx, inp->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::DebugUse));
                 C->record_method_not_compilable("attempted to spill a non-spillable item");
                 return;
--- a/hotspot/src/share/vm/opto/matcher.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/matcher.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -188,7 +188,7 @@
   const TypeTuple *range = C->tf()->range();
   if( range->cnt() > TypeFunc::Parms ) { // If not a void function
     // Get ideal-register return type
-    int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
+    uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
     // Get machine return register
     uint sop = C->start()->Opcode();
     OptoRegPair regs = return_value(ireg, false);
--- a/hotspot/src/share/vm/opto/matcher.hpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/matcher.hpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -334,8 +334,8 @@
   }
 
   // Vector ideal reg
-  static const int vector_ideal_reg(int len);
-  static const int vector_shift_count_ideal_reg(int len);
+  static const uint vector_ideal_reg(int len);
+  static const uint vector_shift_count_ideal_reg(int len);
 
   // CPU supports misaligned vectors store/load.
   static const bool misaligned_vectors_ok();
@@ -377,8 +377,8 @@
   virtual OptoReg::Name return_addr() const;
   RegMask              _return_addr_mask;
   // Return value register.  On Intel it is EAX.  On Sparc i0/o0.
-  static OptoRegPair   return_value(int ideal_reg, bool is_outgoing);
-  static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
+  static OptoRegPair   return_value(uint ideal_reg, bool is_outgoing);
+  static OptoRegPair c_return_value(uint ideal_reg, bool is_outgoing);
   RegMask                     _return_value_mask;
   // Inline Cache Register
   static OptoReg::Name  inline_cache_reg();
--- a/hotspot/src/share/vm/opto/reg_split.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/reg_split.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -60,9 +60,9 @@
   // If ideal reg doesn't exist we've got a bad schedule happening
   // that is forcing us to spill something that isn't spillable.
   // Bail rather than abort
-  int ireg = def->ideal_reg();
+  uint ireg = def->ideal_reg();
   if (ireg == 0 || ireg == Op_RegFlags) {
-    assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %d, spill_type: %s",
+    assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %u, spill_type: %s",
            def->_idx, def->Name(), use->_idx, use->Name(), ireg,
            MachSpillCopyNode::spill_type(spill_type));
     C->record_method_not_compilable("attempted to spill a non-spillable item");
@@ -1184,7 +1184,7 @@
         // Grab UP info for DEF
         const RegMask &dmask = n->out_RegMask();
         bool defup = dmask.is_UP();
-        int ireg = n->ideal_reg();
+        uint ireg = n->ideal_reg();
         bool is_vect = RegMask::is_vector(ireg);
         // Only split at Def if this is a HRP block or bound (and spilled once)
         if( !n->rematerialize() &&
--- a/hotspot/src/share/vm/opto/type.cpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/type.cpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -49,7 +49,7 @@
 Dict* Type::_shared_type_dict = NULL;
 
 // Array which maps compiler types to Basic Types
-Type::TypeInfo Type::_type_info[Type::lastype] = {
+const Type::TypeInfo Type::_type_info[Type::lastype] = {
   { Bad,             T_ILLEGAL,    "bad",           false, Node::NotAMachineReg, relocInfo::none          },  // Bad
   { Control,         T_ILLEGAL,    "control",       false, 0,                    relocInfo::none          },  // Control
   { Bottom,          T_VOID,       "top",           false, 0,                    relocInfo::none          },  // Top
--- a/hotspot/src/share/vm/opto/type.hpp	Tue Apr 11 11:12:58 2017 +0200
+++ b/hotspot/src/share/vm/opto/type.hpp	Wed Apr 12 01:31:36 2017 -0400
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -131,17 +131,17 @@
 
 private:
   typedef struct {
-    const TYPES                dual_type;
-    const BasicType            basic_type;
-    const char*                msg;
-    const bool                 isa_oop;
-    const int                  ideal_reg;
-    const relocInfo::relocType reloc;
+    TYPES                dual_type;
+    BasicType            basic_type;
+    const char*          msg;
+    bool                 isa_oop;
+    uint                 ideal_reg;
+    relocInfo::relocType reloc;
   } TypeInfo;
 
   // Dictionary of types shared among compilations.
   static Dict* _shared_type_dict;
-  static TypeInfo _type_info[];
+  static const TypeInfo _type_info[];
 
   static int uhash( const Type *const t );
   // Structural equality check.  Assumes that cmp() has already compared
@@ -410,7 +410,7 @@
 
   // Mapping from compiler type to VM BasicType
   BasicType basic_type() const       { return _type_info[_base].basic_type; }
-  int ideal_reg() const              { return _type_info[_base].ideal_reg; }
+  uint ideal_reg() const             { return _type_info[_base].ideal_reg; }
   const char* msg() const            { return _type_info[_base].msg; }
   bool isa_oop_ptr() const           { return _type_info[_base].isa_oop; }
   relocInfo::relocType reloc() const { return _type_info[_base].reloc; }