changeset 50637:a2322c683d17

8202395: AARCH64: wrong encoding for SIMD instructions zip, trn, uzp Reviewed-by: aph
author dpochepk
date Fri, 11 May 2018 21:22:28 +0300
parents cd4bf3b1ee77
children b0ed185e8f94
files src/hotspot/cpu/aarch64/assembler_aarch64.hpp
diffstat 1 files changed, 2 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Fri May 11 21:19:47 2018 +0300
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Fri May 11 21:22:28 2018 +0300
@@ -2410,7 +2410,8 @@
 #define INSN(NAME, opcode)                                              \
   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
     starti;                                                             \
-    f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0b001110, 15, 10);       \
+    f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15);                  \
+    f(opcode, 14, 12), f(0b10, 11, 10);                                 \
     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);                                   \
     f(T & 1, 30), f(T >> 1, 23, 22);                                    \
   }