annotate src/cpu/x86/vm/assembler_x86.hpp @ 423:a1980da045cc

6462850: generate biased locking code in C2 ideal graph Summary: Inline biased locking code in C2 ideal graph during macro nodes expansion Reviewed-by: never
author kvn
date Fri, 07 Nov 2008 09:29:38 -0800
parents 2649e5276dd7
children 56aae7be60d4
rev   line source
duke@0 1 /*
xdono@196 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 class BiasedLockingCounters;
duke@0 26
duke@0 27 // Contains all the definitions needed for x86 assembly code generation.
duke@0 28
duke@0 29 // Calling convention
duke@0 30 class Argument VALUE_OBJ_CLASS_SPEC {
duke@0 31 public:
duke@0 32 enum {
duke@0 33 #ifdef _LP64
duke@0 34 #ifdef _WIN64
duke@0 35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
duke@0 36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
duke@0 37 #else
duke@0 38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
duke@0 39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
duke@0 40 #endif // _WIN64
duke@0 41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
duke@0 42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
duke@0 43 #else
duke@0 44 n_register_parameters = 0 // 0 registers used to pass arguments
duke@0 45 #endif // _LP64
duke@0 46 };
duke@0 47 };
duke@0 48
duke@0 49
duke@0 50 #ifdef _LP64
duke@0 51 // Symbolically name the register arguments used by the c calling convention.
duke@0 52 // Windows is different from linux/solaris. So much for standards...
duke@0 53
duke@0 54 #ifdef _WIN64
duke@0 55
duke@0 56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
duke@0 57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
duke@0 58 REGISTER_DECLARATION(Register, c_rarg2, r8);
duke@0 59 REGISTER_DECLARATION(Register, c_rarg3, r9);
duke@0 60
never@307 61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
never@307 62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
never@307 63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
never@307 64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
duke@0 65
duke@0 66 #else
duke@0 67
duke@0 68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
duke@0 69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
duke@0 70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
duke@0 71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
duke@0 72 REGISTER_DECLARATION(Register, c_rarg4, r8);
duke@0 73 REGISTER_DECLARATION(Register, c_rarg5, r9);
duke@0 74
never@307 75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
never@307 76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
never@307 77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
never@307 78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
never@307 79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
never@307 80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
never@307 81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
never@307 82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
duke@0 83
duke@0 84 #endif // _WIN64
duke@0 85
duke@0 86 // Symbolically name the register arguments used by the Java calling convention.
duke@0 87 // We have control over the convention for java so we can do what we please.
duke@0 88 // What pleases us is to offset the java calling convention so that when
duke@0 89 // we call a suitable jni method the arguments are lined up and we don't
duke@0 90 // have to do little shuffling. A suitable jni method is non-static and a
duke@0 91 // small number of arguments (two fewer args on windows)
duke@0 92 //
duke@0 93 // |-------------------------------------------------------|
duke@0 94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
duke@0 95 // |-------------------------------------------------------|
duke@0 96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
duke@0 97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
duke@0 98 // |-------------------------------------------------------|
duke@0 99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
duke@0 100 // |-------------------------------------------------------|
duke@0 101
duke@0 102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
duke@0 103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
duke@0 104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
duke@0 105 // Windows runs out of register args here
duke@0 106 #ifdef _WIN64
duke@0 107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
duke@0 108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
duke@0 109 #else
duke@0 110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
duke@0 111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
duke@0 112 #endif /* _WIN64 */
duke@0 113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
duke@0 114
never@307 115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
never@307 116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
never@307 117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
never@307 118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
never@307 119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
never@307 120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
never@307 121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
never@307 122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
duke@0 123
duke@0 124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
duke@0 125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
duke@0 126
never@307 127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
duke@0 128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
duke@0 129
never@307 130 #else
never@307 131 // rscratch1 will apear in 32bit code that is dead but of course must compile
never@307 132 // Using noreg ensures if the dead code is incorrectly live and executed it
never@307 133 // will cause an assertion failure
never@307 134 #define rscratch1 noreg
never@307 135
duke@0 136 #endif // _LP64
duke@0 137
duke@0 138 // Address is an abstraction used to represent a memory location
duke@0 139 // using any of the amd64 addressing modes with one object.
duke@0 140 //
duke@0 141 // Note: A register location is represented via a Register, not
duke@0 142 // via an address for efficiency & simplicity reasons.
duke@0 143
duke@0 144 class ArrayAddress;
duke@0 145
duke@0 146 class Address VALUE_OBJ_CLASS_SPEC {
duke@0 147 public:
duke@0 148 enum ScaleFactor {
duke@0 149 no_scale = -1,
duke@0 150 times_1 = 0,
duke@0 151 times_2 = 1,
duke@0 152 times_4 = 2,
never@307 153 times_8 = 3,
never@307 154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
duke@0 155 };
duke@0 156
duke@0 157 private:
duke@0 158 Register _base;
duke@0 159 Register _index;
duke@0 160 ScaleFactor _scale;
duke@0 161 int _disp;
duke@0 162 RelocationHolder _rspec;
duke@0 163
never@307 164 // Easily misused constructors make them private
never@307 165 // %%% can we make these go away?
never@307 166 NOT_LP64(Address(address loc, RelocationHolder spec);)
never@307 167 Address(int disp, address loc, relocInfo::relocType rtype);
never@307 168 Address(int disp, address loc, RelocationHolder spec);
duke@0 169
duke@0 170 public:
never@307 171
never@307 172 int disp() { return _disp; }
duke@0 173 // creation
duke@0 174 Address()
duke@0 175 : _base(noreg),
duke@0 176 _index(noreg),
duke@0 177 _scale(no_scale),
duke@0 178 _disp(0) {
duke@0 179 }
duke@0 180
duke@0 181 // No default displacement otherwise Register can be implicitly
duke@0 182 // converted to 0(Register) which is quite a different animal.
duke@0 183
duke@0 184 Address(Register base, int disp)
duke@0 185 : _base(base),
duke@0 186 _index(noreg),
duke@0 187 _scale(no_scale),
duke@0 188 _disp(disp) {
duke@0 189 }
duke@0 190
duke@0 191 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
duke@0 192 : _base (base),
duke@0 193 _index(index),
duke@0 194 _scale(scale),
duke@0 195 _disp (disp) {
duke@0 196 assert(!index->is_valid() == (scale == Address::no_scale),
duke@0 197 "inconsistent address");
duke@0 198 }
duke@0 199
duke@0 200 // The following two overloads are used in connection with the
duke@0 201 // ByteSize type (see sizes.hpp). They simplify the use of
duke@0 202 // ByteSize'd arguments in assembly code. Note that their equivalent
duke@0 203 // for the optimized build are the member functions with int disp
duke@0 204 // argument since ByteSize is mapped to an int type in that case.
duke@0 205 //
duke@0 206 // Note: DO NOT introduce similar overloaded functions for WordSize
duke@0 207 // arguments as in the optimized mode, both ByteSize and WordSize
duke@0 208 // are mapped to the same type and thus the compiler cannot make a
duke@0 209 // distinction anymore (=> compiler errors).
duke@0 210
duke@0 211 #ifdef ASSERT
duke@0 212 Address(Register base, ByteSize disp)
duke@0 213 : _base(base),
duke@0 214 _index(noreg),
duke@0 215 _scale(no_scale),
duke@0 216 _disp(in_bytes(disp)) {
duke@0 217 }
duke@0 218
duke@0 219 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
duke@0 220 : _base(base),
duke@0 221 _index(index),
duke@0 222 _scale(scale),
duke@0 223 _disp(in_bytes(disp)) {
duke@0 224 assert(!index->is_valid() == (scale == Address::no_scale),
duke@0 225 "inconsistent address");
duke@0 226 }
duke@0 227 #endif // ASSERT
duke@0 228
duke@0 229 // accessors
ysr@345 230 bool uses(Register reg) const { return _base == reg || _index == reg; }
ysr@345 231 Register base() const { return _base; }
ysr@345 232 Register index() const { return _index; }
ysr@345 233 ScaleFactor scale() const { return _scale; }
ysr@345 234 int disp() const { return _disp; }
duke@0 235
duke@0 236 // Convert the raw encoding form into the form expected by the constructor for
duke@0 237 // Address. An index of 4 (rsp) corresponds to having no index, so convert
duke@0 238 // that to noreg for the Address constructor.
duke@0 239 static Address make_raw(int base, int index, int scale, int disp);
duke@0 240
duke@0 241 static Address make_array(ArrayAddress);
duke@0 242
duke@0 243
duke@0 244 private:
duke@0 245 bool base_needs_rex() const {
duke@0 246 return _base != noreg && _base->encoding() >= 8;
duke@0 247 }
duke@0 248
duke@0 249 bool index_needs_rex() const {
duke@0 250 return _index != noreg &&_index->encoding() >= 8;
duke@0 251 }
duke@0 252
duke@0 253 relocInfo::relocType reloc() const { return _rspec.type(); }
duke@0 254
duke@0 255 friend class Assembler;
duke@0 256 friend class MacroAssembler;
duke@0 257 friend class LIR_Assembler; // base/index/scale/disp
duke@0 258 };
duke@0 259
duke@0 260 //
duke@0 261 // AddressLiteral has been split out from Address because operands of this type
duke@0 262 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
duke@0 263 // the few instructions that need to deal with address literals are unique and the
duke@0 264 // MacroAssembler does not have to implement every instruction in the Assembler
duke@0 265 // in order to search for address literals that may need special handling depending
duke@0 266 // on the instruction and the platform. As small step on the way to merging i486/amd64
duke@0 267 // directories.
duke@0 268 //
duke@0 269 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
duke@0 270 friend class ArrayAddress;
duke@0 271 RelocationHolder _rspec;
duke@0 272 // Typically we use AddressLiterals we want to use their rval
duke@0 273 // However in some situations we want the lval (effect address) of the item.
duke@0 274 // We provide a special factory for making those lvals.
duke@0 275 bool _is_lval;
duke@0 276
duke@0 277 // If the target is far we'll need to load the ea of this to
duke@0 278 // a register to reach it. Otherwise if near we can do rip
duke@0 279 // relative addressing.
duke@0 280
duke@0 281 address _target;
duke@0 282
duke@0 283 protected:
duke@0 284 // creation
duke@0 285 AddressLiteral()
duke@0 286 : _is_lval(false),
duke@0 287 _target(NULL)
duke@0 288 {}
duke@0 289
duke@0 290 public:
duke@0 291
duke@0 292
duke@0 293 AddressLiteral(address target, relocInfo::relocType rtype);
duke@0 294
duke@0 295 AddressLiteral(address target, RelocationHolder const& rspec)
duke@0 296 : _rspec(rspec),
duke@0 297 _is_lval(false),
duke@0 298 _target(target)
duke@0 299 {}
duke@0 300
duke@0 301 AddressLiteral addr() {
duke@0 302 AddressLiteral ret = *this;
duke@0 303 ret._is_lval = true;
duke@0 304 return ret;
duke@0 305 }
duke@0 306
duke@0 307
duke@0 308 private:
duke@0 309
duke@0 310 address target() { return _target; }
duke@0 311 bool is_lval() { return _is_lval; }
duke@0 312
duke@0 313 relocInfo::relocType reloc() const { return _rspec.type(); }
duke@0 314 const RelocationHolder& rspec() const { return _rspec; }
duke@0 315
duke@0 316 friend class Assembler;
duke@0 317 friend class MacroAssembler;
duke@0 318 friend class Address;
duke@0 319 friend class LIR_Assembler;
duke@0 320 };
duke@0 321
duke@0 322 // Convience classes
duke@0 323 class RuntimeAddress: public AddressLiteral {
duke@0 324
duke@0 325 public:
duke@0 326
duke@0 327 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
duke@0 328
duke@0 329 };
duke@0 330
duke@0 331 class OopAddress: public AddressLiteral {
duke@0 332
duke@0 333 public:
duke@0 334
duke@0 335 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
duke@0 336
duke@0 337 };
duke@0 338
duke@0 339 class ExternalAddress: public AddressLiteral {
duke@0 340
duke@0 341 public:
duke@0 342
duke@0 343 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
duke@0 344
duke@0 345 };
duke@0 346
duke@0 347 class InternalAddress: public AddressLiteral {
duke@0 348
duke@0 349 public:
duke@0 350
duke@0 351 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
duke@0 352
duke@0 353 };
duke@0 354
duke@0 355 // x86 can do array addressing as a single operation since disp can be an absolute
duke@0 356 // address amd64 can't. We create a class that expresses the concept but does extra
duke@0 357 // magic on amd64 to get the final result
duke@0 358
duke@0 359 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
duke@0 360 private:
duke@0 361
duke@0 362 AddressLiteral _base;
duke@0 363 Address _index;
duke@0 364
duke@0 365 public:
duke@0 366
duke@0 367 ArrayAddress() {};
duke@0 368 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
duke@0 369 AddressLiteral base() { return _base; }
duke@0 370 Address index() { return _index; }
duke@0 371
duke@0 372 };
duke@0 373
never@307 374 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
duke@0 375
duke@0 376 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
duke@0 377 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
duke@0 378 // is what you get. The Assembler is generating code into a CodeBuffer.
duke@0 379
duke@0 380 class Assembler : public AbstractAssembler {
duke@0 381 friend class AbstractAssembler; // for the non-virtual hack
duke@0 382 friend class LIR_Assembler; // as_Address()
never@307 383 friend class StubGenerator;
duke@0 384
duke@0 385 public:
duke@0 386 enum Condition { // The x86 condition codes used for conditional jumps/moves.
duke@0 387 zero = 0x4,
duke@0 388 notZero = 0x5,
duke@0 389 equal = 0x4,
duke@0 390 notEqual = 0x5,
duke@0 391 less = 0xc,
duke@0 392 lessEqual = 0xe,
duke@0 393 greater = 0xf,
duke@0 394 greaterEqual = 0xd,
duke@0 395 below = 0x2,
duke@0 396 belowEqual = 0x6,
duke@0 397 above = 0x7,
duke@0 398 aboveEqual = 0x3,
duke@0 399 overflow = 0x0,
duke@0 400 noOverflow = 0x1,
duke@0 401 carrySet = 0x2,
duke@0 402 carryClear = 0x3,
duke@0 403 negative = 0x8,
duke@0 404 positive = 0x9,
duke@0 405 parity = 0xa,
duke@0 406 noParity = 0xb
duke@0 407 };
duke@0 408
duke@0 409 enum Prefix {
duke@0 410 // segment overrides
duke@0 411 CS_segment = 0x2e,
duke@0 412 SS_segment = 0x36,
duke@0 413 DS_segment = 0x3e,
duke@0 414 ES_segment = 0x26,
duke@0 415 FS_segment = 0x64,
duke@0 416 GS_segment = 0x65,
duke@0 417
duke@0 418 REX = 0x40,
duke@0 419
duke@0 420 REX_B = 0x41,
duke@0 421 REX_X = 0x42,
duke@0 422 REX_XB = 0x43,
duke@0 423 REX_R = 0x44,
duke@0 424 REX_RB = 0x45,
duke@0 425 REX_RX = 0x46,
duke@0 426 REX_RXB = 0x47,
duke@0 427
duke@0 428 REX_W = 0x48,
duke@0 429
duke@0 430 REX_WB = 0x49,
duke@0 431 REX_WX = 0x4A,
duke@0 432 REX_WXB = 0x4B,
duke@0 433 REX_WR = 0x4C,
duke@0 434 REX_WRB = 0x4D,
duke@0 435 REX_WRX = 0x4E,
duke@0 436 REX_WRXB = 0x4F
duke@0 437 };
duke@0 438
duke@0 439 enum WhichOperand {
duke@0 440 // input to locate_operand, and format code for relocations
never@307 441 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
duke@0 442 disp32_operand = 1, // embedded 32-bit displacement or address
duke@0 443 call32_operand = 2, // embedded 32-bit self-relative displacement
never@307 444 #ifndef _LP64
duke@0 445 _WhichOperand_limit = 3
never@307 446 #else
never@307 447 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
never@307 448 _WhichOperand_limit = 4
never@307 449 #endif
duke@0 450 };
duke@0 451
never@307 452
never@307 453
never@307 454 // NOTE: The general philopsophy of the declarations here is that 64bit versions
never@307 455 // of instructions are freely declared without the need for wrapping them an ifdef.
never@307 456 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
never@307 457 // In the .cpp file the implementations are wrapped so that they are dropped out
never@307 458 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
never@307 459 // to the size it was prior to merging up the 32bit and 64bit assemblers.
never@307 460 //
never@307 461 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
never@307 462 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
never@307 463
never@307 464 private:
never@307 465
never@307 466
never@307 467 // 64bit prefixes
never@307 468 int prefix_and_encode(int reg_enc, bool byteinst = false);
never@307 469 int prefixq_and_encode(int reg_enc);
never@307 470
never@307 471 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
never@307 472 int prefixq_and_encode(int dst_enc, int src_enc);
never@307 473
never@307 474 void prefix(Register reg);
never@307 475 void prefix(Address adr);
never@307 476 void prefixq(Address adr);
never@307 477
never@307 478 void prefix(Address adr, Register reg, bool byteinst = false);
never@307 479 void prefixq(Address adr, Register reg);
never@307 480
never@307 481 void prefix(Address adr, XMMRegister reg);
never@307 482
never@307 483 void prefetch_prefix(Address src);
never@307 484
never@307 485 // Helper functions for groups of instructions
never@307 486 void emit_arith_b(int op1, int op2, Register dst, int imm8);
never@307 487
never@307 488 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
never@307 489 // only 32bit??
never@307 490 void emit_arith(int op1, int op2, Register dst, jobject obj);
never@307 491 void emit_arith(int op1, int op2, Register dst, Register src);
never@307 492
never@307 493 void emit_operand(Register reg,
never@307 494 Register base, Register index, Address::ScaleFactor scale,
never@307 495 int disp,
never@307 496 RelocationHolder const& rspec,
never@307 497 int rip_relative_correction = 0);
never@307 498
never@307 499 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
never@307 500
never@307 501 // operands that only take the original 32bit registers
never@307 502 void emit_operand32(Register reg, Address adr);
never@307 503
never@307 504 void emit_operand(XMMRegister reg,
never@307 505 Register base, Register index, Address::ScaleFactor scale,
never@307 506 int disp,
never@307 507 RelocationHolder const& rspec);
never@307 508
never@307 509 void emit_operand(XMMRegister reg, Address adr);
never@307 510
never@307 511 void emit_operand(MMXRegister reg, Address adr);
never@307 512
never@307 513 // workaround gcc (3.2.1-7) bug
never@307 514 void emit_operand(Address adr, MMXRegister reg);
never@307 515
never@307 516
never@307 517 // Immediate-to-memory forms
never@307 518 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
never@307 519
never@307 520 void emit_farith(int b1, int b2, int i);
never@307 521
duke@0 522
duke@0 523 protected:
never@307 524 #ifdef ASSERT
never@307 525 void check_relocation(RelocationHolder const& rspec, int format);
never@307 526 #endif
never@307 527
never@307 528 inline void emit_long64(jlong x);
never@307 529
never@307 530 void emit_data(jint data, relocInfo::relocType rtype, int format);
never@307 531 void emit_data(jint data, RelocationHolder const& rspec, int format);
never@307 532 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
never@307 533 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
never@307 534
never@307 535
never@307 536 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
never@307 537
never@307 538 // These are all easily abused and hence protected
never@307 539
never@307 540 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
never@307 541
never@307 542 // 32BIT ONLY SECTION
never@307 543 #ifndef _LP64
never@307 544 // Make these disappear in 64bit mode since they would never be correct
never@307 545 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@307 546 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@307 547
never@307 548 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@307 549
never@307 550 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@307 551 #else
never@307 552 // 64BIT ONLY SECTION
never@307 553 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
never@307 554 #endif // _LP64
never@307 555
never@307 556 // These are unique in that we are ensured by the caller that the 32bit
never@307 557 // relative in these instructions will always be able to reach the potentially
never@307 558 // 64bit address described by entry. Since they can take a 64bit address they
never@307 559 // don't have the 32 suffix like the other instructions in this class.
never@307 560
never@307 561 void call_literal(address entry, RelocationHolder const& rspec);
never@307 562 void jmp_literal(address entry, RelocationHolder const& rspec);
never@307 563
never@307 564 // Avoid using directly section
never@307 565 // Instructions in this section are actually usable by anyone without danger
never@307 566 // of failure but have performance issues that are addressed my enhanced
never@307 567 // instructions which will do the proper thing base on the particular cpu.
never@307 568 // We protect them because we don't trust you...
never@307 569
duke@0 570 // Don't use next inc() and dec() methods directly. INC & DEC instructions
duke@0 571 // could cause a partial flag stall since they don't set CF flag.
duke@0 572 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
duke@0 573 // which call inc() & dec() or add() & sub() in accordance with
duke@0 574 // the product flag UseIncDec value.
duke@0 575
duke@0 576 void decl(Register dst);
duke@0 577 void decl(Address dst);
never@307 578 void decq(Register dst);
never@307 579 void decq(Address dst);
duke@0 580
duke@0 581 void incl(Register dst);
duke@0 582 void incl(Address dst);
never@307 583 void incq(Register dst);
never@307 584 void incq(Address dst);
never@307 585
never@307 586 // New cpus require use of movsd and movss to avoid partial register stall
never@307 587 // when loading from memory. But for old Opteron use movlpd instead of movsd.
never@307 588 // The selection is done in MacroAssembler::movdbl() and movflt().
never@307 589
never@307 590 // Move Scalar Single-Precision Floating-Point Values
never@307 591 void movss(XMMRegister dst, Address src);
never@307 592 void movss(XMMRegister dst, XMMRegister src);
never@307 593 void movss(Address dst, XMMRegister src);
never@307 594
never@307 595 // Move Scalar Double-Precision Floating-Point Values
never@307 596 void movsd(XMMRegister dst, Address src);
never@307 597 void movsd(XMMRegister dst, XMMRegister src);
never@307 598 void movsd(Address dst, XMMRegister src);
never@307 599 void movlpd(XMMRegister dst, Address src);
never@307 600
never@307 601 // New cpus require use of movaps and movapd to avoid partial register stall
never@307 602 // when moving between registers.
never@307 603 void movaps(XMMRegister dst, XMMRegister src);
never@307 604 void movapd(XMMRegister dst, XMMRegister src);
never@307 605
never@307 606 // End avoid using directly
never@307 607
never@307 608
never@307 609 // Instruction prefixes
never@307 610 void prefix(Prefix p);
never@307 611
never@307 612 public:
never@307 613
never@307 614 // Creation
never@307 615 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
never@307 616
never@307 617 // Decoding
never@307 618 static address locate_operand(address inst, WhichOperand which);
never@307 619 static address locate_next_instruction(address inst);
never@307 620
never@307 621 // Utilities
never@307 622
never@307 623 #ifdef _LP64
never@307 624 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
never@307 625 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
never@307 626 #else
never@307 627 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
never@307 628 static bool is_simm32(int32_t x) { return true; }
never@307 629 #endif // LP64
never@307 630
never@307 631 // Generic instructions
never@307 632 // Does 32bit or 64bit as needed for the platform. In some sense these
never@307 633 // belong in macro assembler but there is no need for both varieties to exist
never@307 634
never@307 635 void lea(Register dst, Address src);
never@307 636
never@307 637 void mov(Register dst, Register src);
never@307 638
never@307 639 void pusha();
never@307 640 void popa();
never@307 641
never@307 642 void pushf();
never@307 643 void popf();
never@307 644
never@307 645 void push(int32_t imm32);
never@307 646
never@307 647 void push(Register src);
never@307 648
never@307 649 void pop(Register dst);
never@307 650
never@307 651 // These are dummies to prevent surprise implicit conversions to Register
never@307 652 void push(void* v);
never@307 653 void pop(void* v);
never@307 654
never@307 655
never@307 656 // These do register sized moves/scans
never@307 657 void rep_mov();
never@307 658 void rep_set();
never@307 659 void repne_scan();
never@307 660 #ifdef _LP64
never@307 661 void repne_scanl();
never@307 662 #endif
never@307 663
never@307 664 // Vanilla instructions in lexical order
never@307 665
never@307 666 void adcl(Register dst, int32_t imm32);
never@307 667 void adcl(Register dst, Address src);
never@307 668 void adcl(Register dst, Register src);
never@307 669
never@307 670 void adcq(Register dst, int32_t imm32);
never@307 671 void adcq(Register dst, Address src);
never@307 672 void adcq(Register dst, Register src);
never@307 673
never@307 674
never@307 675 void addl(Address dst, int32_t imm32);
never@307 676 void addl(Address dst, Register src);
never@307 677 void addl(Register dst, int32_t imm32);
never@307 678 void addl(Register dst, Address src);
never@307 679 void addl(Register dst, Register src);
never@307 680
never@307 681 void addq(Address dst, int32_t imm32);
never@307 682 void addq(Address dst, Register src);
never@307 683 void addq(Register dst, int32_t imm32);
never@307 684 void addq(Register dst, Address src);
never@307 685 void addq(Register dst, Register src);
never@307 686
never@307 687
duke@0 688 void addr_nop_4();
duke@0 689 void addr_nop_5();
duke@0 690 void addr_nop_7();
duke@0 691 void addr_nop_8();
duke@0 692
never@307 693 // Add Scalar Double-Precision Floating-Point Values
never@307 694 void addsd(XMMRegister dst, Address src);
never@307 695 void addsd(XMMRegister dst, XMMRegister src);
never@307 696
never@307 697 // Add Scalar Single-Precision Floating-Point Values
never@307 698 void addss(XMMRegister dst, Address src);
never@307 699 void addss(XMMRegister dst, XMMRegister src);
never@307 700
never@307 701 void andl(Register dst, int32_t imm32);
never@307 702 void andl(Register dst, Address src);
never@307 703 void andl(Register dst, Register src);
never@307 704
never@307 705 void andq(Register dst, int32_t imm32);
never@307 706 void andq(Register dst, Address src);
never@307 707 void andq(Register dst, Register src);
never@307 708
never@307 709
never@307 710 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
never@307 711 void andpd(XMMRegister dst, Address src);
never@307 712 void andpd(XMMRegister dst, XMMRegister src);
never@307 713
never@307 714 void bswapl(Register reg);
never@307 715
never@307 716 void bswapq(Register reg);
never@307 717
duke@0 718 void call(Label& L, relocInfo::relocType rtype);
duke@0 719 void call(Register reg); // push pc; pc <- reg
duke@0 720 void call(Address adr); // push pc; pc <- adr
duke@0 721
never@307 722 void cdql();
never@307 723
never@307 724 void cdqq();
never@307 725
never@307 726 void cld() { emit_byte(0xfc); }
never@307 727
never@307 728 void clflush(Address adr);
never@307 729
never@307 730 void cmovl(Condition cc, Register dst, Register src);
never@307 731 void cmovl(Condition cc, Register dst, Address src);
never@307 732
never@307 733 void cmovq(Condition cc, Register dst, Register src);
never@307 734 void cmovq(Condition cc, Register dst, Address src);
never@307 735
never@307 736
never@307 737 void cmpb(Address dst, int imm8);
never@307 738
never@307 739 void cmpl(Address dst, int32_t imm32);
never@307 740
never@307 741 void cmpl(Register dst, int32_t imm32);
never@307 742 void cmpl(Register dst, Register src);
never@307 743 void cmpl(Register dst, Address src);
never@307 744
never@307 745 void cmpq(Address dst, int32_t imm32);
never@307 746 void cmpq(Address dst, Register src);
never@307 747
never@307 748 void cmpq(Register dst, int32_t imm32);
never@307 749 void cmpq(Register dst, Register src);
never@307 750 void cmpq(Register dst, Address src);
never@307 751
never@307 752 // these are dummies used to catch attempting to convert NULL to Register
never@307 753 void cmpl(Register dst, void* junk); // dummy
never@307 754 void cmpq(Register dst, void* junk); // dummy
never@307 755
never@307 756 void cmpw(Address dst, int imm16);
never@307 757
never@307 758 void cmpxchg8 (Address adr);
never@307 759
never@307 760 void cmpxchgl(Register reg, Address adr);
never@307 761
never@307 762 void cmpxchgq(Register reg, Address adr);
never@307 763
never@307 764 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
never@307 765 void comisd(XMMRegister dst, Address src);
never@307 766
never@307 767 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
never@307 768 void comiss(XMMRegister dst, Address src);
never@307 769
never@307 770 // Identify processor type and features
never@307 771 void cpuid() {
never@307 772 emit_byte(0x0F);
never@307 773 emit_byte(0xA2);
never@307 774 }
never@307 775
never@307 776 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
never@307 777 void cvtsd2ss(XMMRegister dst, XMMRegister src);
never@307 778
never@307 779 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
never@307 780 void cvtsi2sdl(XMMRegister dst, Register src);
never@307 781 void cvtsi2sdq(XMMRegister dst, Register src);
never@307 782
never@307 783 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
never@307 784 void cvtsi2ssl(XMMRegister dst, Register src);
never@307 785 void cvtsi2ssq(XMMRegister dst, Register src);
never@307 786
never@307 787 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
never@307 788 void cvtdq2pd(XMMRegister dst, XMMRegister src);
never@307 789
never@307 790 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
never@307 791 void cvtdq2ps(XMMRegister dst, XMMRegister src);
never@307 792
never@307 793 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
never@307 794 void cvtss2sd(XMMRegister dst, XMMRegister src);
never@307 795
never@307 796 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
never@307 797 void cvttsd2sil(Register dst, Address src);
never@307 798 void cvttsd2sil(Register dst, XMMRegister src);
never@307 799 void cvttsd2siq(Register dst, XMMRegister src);
never@307 800
never@307 801 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
never@307 802 void cvttss2sil(Register dst, XMMRegister src);
never@307 803 void cvttss2siq(Register dst, XMMRegister src);
never@307 804
never@307 805 // Divide Scalar Double-Precision Floating-Point Values
never@307 806 void divsd(XMMRegister dst, Address src);
never@307 807 void divsd(XMMRegister dst, XMMRegister src);
never@307 808
never@307 809 // Divide Scalar Single-Precision Floating-Point Values
never@307 810 void divss(XMMRegister dst, Address src);
never@307 811 void divss(XMMRegister dst, XMMRegister src);
never@307 812
never@307 813 void emms();
never@307 814
never@307 815 void fabs();
never@307 816
never@307 817 void fadd(int i);
never@307 818
never@307 819 void fadd_d(Address src);
never@307 820 void fadd_s(Address src);
never@307 821
never@307 822 // "Alternate" versions of x87 instructions place result down in FPU
never@307 823 // stack instead of on TOS
never@307 824
never@307 825 void fadda(int i); // "alternate" fadd
never@307 826 void faddp(int i = 1);
never@307 827
never@307 828 void fchs();
never@307 829
never@307 830 void fcom(int i);
never@307 831
never@307 832 void fcomp(int i = 1);
never@307 833 void fcomp_d(Address src);
never@307 834 void fcomp_s(Address src);
never@307 835
never@307 836 void fcompp();
never@307 837
never@307 838 void fcos();
never@307 839
never@307 840 void fdecstp();
never@307 841
never@307 842 void fdiv(int i);
never@307 843 void fdiv_d(Address src);
never@307 844 void fdivr_s(Address src);
never@307 845 void fdiva(int i); // "alternate" fdiv
never@307 846 void fdivp(int i = 1);
never@307 847
never@307 848 void fdivr(int i);
never@307 849 void fdivr_d(Address src);
never@307 850 void fdiv_s(Address src);
never@307 851
never@307 852 void fdivra(int i); // "alternate" reversed fdiv
never@307 853
never@307 854 void fdivrp(int i = 1);
never@307 855
never@307 856 void ffree(int i = 0);
never@307 857
never@307 858 void fild_d(Address adr);
never@307 859 void fild_s(Address adr);
never@307 860
never@307 861 void fincstp();
never@307 862
never@307 863 void finit();
never@307 864
never@307 865 void fist_s (Address adr);
never@307 866 void fistp_d(Address adr);
never@307 867 void fistp_s(Address adr);
never@307 868
never@307 869 void fld1();
never@307 870
never@307 871 void fld_d(Address adr);
never@307 872 void fld_s(Address adr);
never@307 873 void fld_s(int index);
never@307 874 void fld_x(Address adr); // extended-precision (80-bit) format
never@307 875
never@307 876 void fldcw(Address src);
never@307 877
never@307 878 void fldenv(Address src);
never@307 879
never@307 880 void fldlg2();
never@307 881
never@307 882 void fldln2();
never@307 883
never@307 884 void fldz();
never@307 885
never@307 886 void flog();
never@307 887 void flog10();
never@307 888
never@307 889 void fmul(int i);
never@307 890
never@307 891 void fmul_d(Address src);
never@307 892 void fmul_s(Address src);
never@307 893
never@307 894 void fmula(int i); // "alternate" fmul
never@307 895
never@307 896 void fmulp(int i = 1);
never@307 897
never@307 898 void fnsave(Address dst);
never@307 899
never@307 900 void fnstcw(Address src);
never@307 901
never@307 902 void fnstsw_ax();
never@307 903
never@307 904 void fprem();
never@307 905 void fprem1();
never@307 906
never@307 907 void frstor(Address src);
never@307 908
never@307 909 void fsin();
never@307 910
never@307 911 void fsqrt();
never@307 912
never@307 913 void fst_d(Address adr);
never@307 914 void fst_s(Address adr);
never@307 915
never@307 916 void fstp_d(Address adr);
never@307 917 void fstp_d(int index);
never@307 918 void fstp_s(Address adr);
never@307 919 void fstp_x(Address adr); // extended-precision (80-bit) format
never@307 920
never@307 921 void fsub(int i);
never@307 922 void fsub_d(Address src);
never@307 923 void fsub_s(Address src);
never@307 924
never@307 925 void fsuba(int i); // "alternate" fsub
never@307 926
never@307 927 void fsubp(int i = 1);
never@307 928
never@307 929 void fsubr(int i);
never@307 930 void fsubr_d(Address src);
never@307 931 void fsubr_s(Address src);
never@307 932
never@307 933 void fsubra(int i); // "alternate" reversed fsub
never@307 934
never@307 935 void fsubrp(int i = 1);
never@307 936
never@307 937 void ftan();
never@307 938
never@307 939 void ftst();
never@307 940
never@307 941 void fucomi(int i = 1);
never@307 942 void fucomip(int i = 1);
never@307 943
never@307 944 void fwait();
never@307 945
never@307 946 void fxch(int i = 1);
never@307 947
never@307 948 void fxrstor(Address src);
never@307 949
never@307 950 void fxsave(Address dst);
never@307 951
never@307 952 void fyl2x();
never@307 953
never@307 954 void hlt();
never@307 955
never@307 956 void idivl(Register src);
never@307 957
never@307 958 void idivq(Register src);
never@307 959
never@307 960 void imull(Register dst, Register src);
never@307 961 void imull(Register dst, Register src, int value);
never@307 962
never@307 963 void imulq(Register dst, Register src);
never@307 964 void imulq(Register dst, Register src, int value);
never@307 965
duke@0 966
duke@0 967 // jcc is the generic conditional branch generator to run-
duke@0 968 // time routines, jcc is used for branches to labels. jcc
duke@0 969 // takes a branch opcode (cc) and a label (L) and generates
duke@0 970 // either a backward branch or a forward branch and links it
duke@0 971 // to the label fixup chain. Usage:
duke@0 972 //
duke@0 973 // Label L; // unbound label
duke@0 974 // jcc(cc, L); // forward branch to unbound label
duke@0 975 // bind(L); // bind label to the current pc
duke@0 976 // jcc(cc, L); // backward branch to bound label
duke@0 977 // bind(L); // illegal: a label may be bound only once
duke@0 978 //
duke@0 979 // Note: The same Label can be used for forward and backward branches
duke@0 980 // but it may be bound only once.
duke@0 981
duke@0 982 void jcc(Condition cc, Label& L,
duke@0 983 relocInfo::relocType rtype = relocInfo::none);
duke@0 984
duke@0 985 // Conditional jump to a 8-bit offset to L.
duke@0 986 // WARNING: be very careful using this for forward jumps. If the label is
duke@0 987 // not bound within an 8-bit offset of this instruction, a run-time error
duke@0 988 // will occur.
duke@0 989 void jccb(Condition cc, Label& L);
duke@0 990
never@307 991 void jmp(Address entry); // pc <- entry
never@307 992
never@307 993 // Label operations & relative jumps (PPUM Appendix D)
never@307 994 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
never@307 995
never@307 996 void jmp(Register entry); // pc <- entry
never@307 997
never@307 998 // Unconditional 8-bit offset jump to L.
never@307 999 // WARNING: be very careful using this for forward jumps. If the label is
never@307 1000 // not bound within an 8-bit offset of this instruction, a run-time error
never@307 1001 // will occur.
never@307 1002 void jmpb(Label& L);
never@307 1003
never@307 1004 void ldmxcsr( Address src );
never@307 1005
never@307 1006 void leal(Register dst, Address src);
never@307 1007
never@307 1008 void leaq(Register dst, Address src);
never@307 1009
never@307 1010 void lfence() {
never@307 1011 emit_byte(0x0F);
never@307 1012 emit_byte(0xAE);
never@307 1013 emit_byte(0xE8);
never@307 1014 }
never@307 1015
never@307 1016 void lock();
never@307 1017
never@307 1018 enum Membar_mask_bits {
never@307 1019 StoreStore = 1 << 3,
never@307 1020 LoadStore = 1 << 2,
never@307 1021 StoreLoad = 1 << 1,
never@307 1022 LoadLoad = 1 << 0
never@307 1023 };
never@307 1024
never@307 1025 // Serializes memory.
never@307 1026 void membar(Membar_mask_bits order_constraint) {
never@307 1027 // We only have to handle StoreLoad and LoadLoad
never@307 1028 if (order_constraint & StoreLoad) {
never@307 1029 // MFENCE subsumes LFENCE
never@307 1030 mfence();
never@307 1031 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
never@307 1032 lfence();
never@307 1033 } */
never@307 1034 }
never@307 1035
never@307 1036 void mfence();
never@307 1037
never@307 1038 // Moves
never@307 1039
never@307 1040 void mov64(Register dst, int64_t imm64);
never@307 1041
never@307 1042 void movb(Address dst, Register src);
never@307 1043 void movb(Address dst, int imm8);
never@307 1044 void movb(Register dst, Address src);
never@307 1045
never@307 1046 void movdl(XMMRegister dst, Register src);
never@307 1047 void movdl(Register dst, XMMRegister src);
never@307 1048
never@307 1049 // Move Double Quadword
never@307 1050 void movdq(XMMRegister dst, Register src);
never@307 1051 void movdq(Register dst, XMMRegister src);
never@307 1052
never@307 1053 // Move Aligned Double Quadword
never@307 1054 void movdqa(Address dst, XMMRegister src);
never@307 1055 void movdqa(XMMRegister dst, Address src);
never@307 1056 void movdqa(XMMRegister dst, XMMRegister src);
never@307 1057
kvn@408 1058 // Move Unaligned Double Quadword
kvn@408 1059 void movdqu(Address dst, XMMRegister src);
kvn@408 1060 void movdqu(XMMRegister dst, Address src);
kvn@408 1061 void movdqu(XMMRegister dst, XMMRegister src);
kvn@408 1062
never@307 1063 void movl(Register dst, int32_t imm32);
never@307 1064 void movl(Address dst, int32_t imm32);
never@307 1065 void movl(Register dst, Register src);
never@307 1066 void movl(Register dst, Address src);
never@307 1067 void movl(Address dst, Register src);
never@307 1068
never@307 1069 // These dummies prevent using movl from converting a zero (like NULL) into Register
never@307 1070 // by giving the compiler two choices it can't resolve
never@307 1071
never@307 1072 void movl(Address dst, void* junk);
never@307 1073 void movl(Register dst, void* junk);
never@307 1074
never@307 1075 #ifdef _LP64
never@307 1076 void movq(Register dst, Register src);
never@307 1077 void movq(Register dst, Address src);
never@307 1078 void movq(Address dst, Register src);
never@307 1079 #endif
never@307 1080
never@307 1081 void movq(Address dst, MMXRegister src );
never@307 1082 void movq(MMXRegister dst, Address src );
never@307 1083
never@307 1084 #ifdef _LP64
never@307 1085 // These dummies prevent using movq from converting a zero (like NULL) into Register
never@307 1086 // by giving the compiler two choices it can't resolve
never@307 1087
never@307 1088 void movq(Address dst, void* dummy);
never@307 1089 void movq(Register dst, void* dummy);
never@307 1090 #endif
never@307 1091
never@307 1092 // Move Quadword
never@307 1093 void movq(Address dst, XMMRegister src);
never@307 1094 void movq(XMMRegister dst, Address src);
never@307 1095
never@307 1096 void movsbl(Register dst, Address src);
never@307 1097 void movsbl(Register dst, Register src);
never@307 1098
never@307 1099 #ifdef _LP64
never@307 1100 // Move signed 32bit immediate to 64bit extending sign
never@307 1101 void movslq(Address dst, int32_t imm64);
never@307 1102 void movslq(Register dst, int32_t imm64);
never@307 1103
never@307 1104 void movslq(Register dst, Address src);
never@307 1105 void movslq(Register dst, Register src);
never@307 1106 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
never@307 1107 #endif
never@307 1108
never@307 1109 void movswl(Register dst, Address src);
never@307 1110 void movswl(Register dst, Register src);
never@307 1111
never@307 1112 void movw(Address dst, int imm16);
never@307 1113 void movw(Register dst, Address src);
never@307 1114 void movw(Address dst, Register src);
never@307 1115
never@307 1116 void movzbl(Register dst, Address src);
never@307 1117 void movzbl(Register dst, Register src);
never@307 1118
never@307 1119 void movzwl(Register dst, Address src);
never@307 1120 void movzwl(Register dst, Register src);
never@307 1121
never@307 1122 void mull(Address src);
never@307 1123 void mull(Register src);
never@307 1124
never@307 1125 // Multiply Scalar Double-Precision Floating-Point Values
never@307 1126 void mulsd(XMMRegister dst, Address src);
never@307 1127 void mulsd(XMMRegister dst, XMMRegister src);
never@307 1128
never@307 1129 // Multiply Scalar Single-Precision Floating-Point Values
never@307 1130 void mulss(XMMRegister dst, Address src);
never@307 1131 void mulss(XMMRegister dst, XMMRegister src);
never@307 1132
never@307 1133 void negl(Register dst);
never@307 1134
never@307 1135 #ifdef _LP64
never@307 1136 void negq(Register dst);
never@307 1137 #endif
never@307 1138
never@307 1139 void nop(int i = 1);
never@307 1140
never@307 1141 void notl(Register dst);
never@307 1142
never@307 1143 #ifdef _LP64
never@307 1144 void notq(Register dst);
never@307 1145 #endif
never@307 1146
never@307 1147 void orl(Address dst, int32_t imm32);
never@307 1148 void orl(Register dst, int32_t imm32);
never@307 1149 void orl(Register dst, Address src);
never@307 1150 void orl(Register dst, Register src);
never@307 1151
never@307 1152 void orq(Address dst, int32_t imm32);
never@307 1153 void orq(Register dst, int32_t imm32);
never@307 1154 void orq(Register dst, Address src);
never@307 1155 void orq(Register dst, Register src);
never@307 1156
never@307 1157 void popl(Address dst);
never@307 1158
never@307 1159 #ifdef _LP64
never@307 1160 void popq(Address dst);
never@307 1161 #endif
never@307 1162
never@307 1163 // Prefetches (SSE, SSE2, 3DNOW only)
never@307 1164
never@307 1165 void prefetchnta(Address src);
never@307 1166 void prefetchr(Address src);
never@307 1167 void prefetcht0(Address src);
never@307 1168 void prefetcht1(Address src);
never@307 1169 void prefetcht2(Address src);
never@307 1170 void prefetchw(Address src);
never@307 1171
never@307 1172 // Shuffle Packed Doublewords
never@307 1173 void pshufd(XMMRegister dst, XMMRegister src, int mode);
never@307 1174 void pshufd(XMMRegister dst, Address src, int mode);
never@307 1175
never@307 1176 // Shuffle Packed Low Words
never@307 1177 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
never@307 1178 void pshuflw(XMMRegister dst, Address src, int mode);
never@307 1179
never@307 1180 // Shift Right Logical Quadword Immediate
never@307 1181 void psrlq(XMMRegister dst, int shift);
never@307 1182
never@307 1183 // Interleave Low Bytes
never@307 1184 void punpcklbw(XMMRegister dst, XMMRegister src);
never@307 1185
never@307 1186 void pushl(Address src);
never@307 1187
never@307 1188 void pushq(Address src);
never@307 1189
never@307 1190 // Xor Packed Byte Integer Values
never@307 1191 void pxor(XMMRegister dst, Address src);
never@307 1192 void pxor(XMMRegister dst, XMMRegister src);
never@307 1193
never@307 1194 void rcll(Register dst, int imm8);
never@307 1195
never@307 1196 void rclq(Register dst, int imm8);
never@307 1197
never@307 1198 void ret(int imm16);
duke@0 1199
duke@0 1200 void sahf();
duke@0 1201
never@307 1202 void sarl(Register dst, int imm8);
never@307 1203 void sarl(Register dst);
never@307 1204
never@307 1205 void sarq(Register dst, int imm8);
never@307 1206 void sarq(Register dst);
never@307 1207
never@307 1208 void sbbl(Address dst, int32_t imm32);
never@307 1209 void sbbl(Register dst, int32_t imm32);
never@307 1210 void sbbl(Register dst, Address src);
never@307 1211 void sbbl(Register dst, Register src);
never@307 1212
never@307 1213 void sbbq(Address dst, int32_t imm32);
never@307 1214 void sbbq(Register dst, int32_t imm32);
never@307 1215 void sbbq(Register dst, Address src);
never@307 1216 void sbbq(Register dst, Register src);
never@307 1217
never@307 1218 void setb(Condition cc, Register dst);
never@307 1219
never@307 1220 void shldl(Register dst, Register src);
never@307 1221
never@307 1222 void shll(Register dst, int imm8);
never@307 1223 void shll(Register dst);
never@307 1224
never@307 1225 void shlq(Register dst, int imm8);
never@307 1226 void shlq(Register dst);
never@307 1227
never@307 1228 void shrdl(Register dst, Register src);
never@307 1229
never@307 1230 void shrl(Register dst, int imm8);
never@307 1231 void shrl(Register dst);
never@307 1232
never@307 1233 void shrq(Register dst, int imm8);
never@307 1234 void shrq(Register dst);
never@307 1235
never@307 1236 void smovl(); // QQQ generic?
never@307 1237
never@307 1238 // Compute Square Root of Scalar Double-Precision Floating-Point Value
never@307 1239 void sqrtsd(XMMRegister dst, Address src);
never@307 1240 void sqrtsd(XMMRegister dst, XMMRegister src);
never@307 1241
never@307 1242 void std() { emit_byte(0xfd); }
never@307 1243
never@307 1244 void stmxcsr( Address dst );
never@307 1245
never@307 1246 void subl(Address dst, int32_t imm32);
never@307 1247 void subl(Address dst, Register src);
never@307 1248 void subl(Register dst, int32_t imm32);
never@307 1249 void subl(Register dst, Address src);
never@307 1250 void subl(Register dst, Register src);
never@307 1251
never@307 1252 void subq(Address dst, int32_t imm32);
never@307 1253 void subq(Address dst, Register src);
never@307 1254 void subq(Register dst, int32_t imm32);
never@307 1255 void subq(Register dst, Address src);
never@307 1256 void subq(Register dst, Register src);
never@307 1257
never@307 1258
never@307 1259 // Subtract Scalar Double-Precision Floating-Point Values
never@307 1260 void subsd(XMMRegister dst, Address src);
never@307 1261 void subsd(XMMRegister dst, XMMRegister src);
never@307 1262
never@307 1263 // Subtract Scalar Single-Precision Floating-Point Values
never@307 1264 void subss(XMMRegister dst, Address src);
duke@0 1265 void subss(XMMRegister dst, XMMRegister src);
never@307 1266
never@307 1267 void testb(Register dst, int imm8);
never@307 1268
never@307 1269 void testl(Register dst, int32_t imm32);
never@307 1270 void testl(Register dst, Register src);
never@307 1271 void testl(Register dst, Address src);
never@307 1272
never@307 1273 void testq(Register dst, int32_t imm32);
never@307 1274 void testq(Register dst, Register src);
never@307 1275
never@307 1276
never@307 1277 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
never@307 1278 void ucomisd(XMMRegister dst, Address src);
never@307 1279 void ucomisd(XMMRegister dst, XMMRegister src);
never@307 1280
never@307 1281 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
never@307 1282 void ucomiss(XMMRegister dst, Address src);
duke@0 1283 void ucomiss(XMMRegister dst, XMMRegister src);
never@307 1284
never@307 1285 void xaddl(Address dst, Register src);
never@307 1286
never@307 1287 void xaddq(Address dst, Register src);
never@307 1288
never@307 1289 void xchgl(Register reg, Address adr);
never@307 1290 void xchgl(Register dst, Register src);
never@307 1291
never@307 1292 void xchgq(Register reg, Address adr);
never@307 1293 void xchgq(Register dst, Register src);
never@307 1294
never@307 1295 void xorl(Register dst, int32_t imm32);
never@307 1296 void xorl(Register dst, Address src);
never@307 1297 void xorl(Register dst, Register src);
never@307 1298
never@307 1299 void xorq(Register dst, Address src);
never@307 1300 void xorq(Register dst, Register src);
never@307 1301
never@307 1302 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
never@307 1303 void xorpd(XMMRegister dst, Address src);
never@307 1304 void xorpd(XMMRegister dst, XMMRegister src);
never@307 1305
never@307 1306 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
never@307 1307 void xorps(XMMRegister dst, Address src);
duke@0 1308 void xorps(XMMRegister dst, XMMRegister src);
never@307 1309
never@307 1310 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
duke@0 1311 };
duke@0 1312
duke@0 1313
duke@0 1314 // MacroAssembler extends Assembler by frequently used macros.
duke@0 1315 //
duke@0 1316 // Instructions for which a 'better' code sequence exists depending
duke@0 1317 // on arguments should also go in here.
duke@0 1318
duke@0 1319 class MacroAssembler: public Assembler {
ysr@345 1320 friend class LIR_Assembler;
ysr@345 1321 friend class Runtime1; // as_Address()
duke@0 1322 protected:
duke@0 1323
duke@0 1324 Address as_Address(AddressLiteral adr);
duke@0 1325 Address as_Address(ArrayAddress adr);
duke@0 1326
duke@0 1327 // Support for VM calls
duke@0 1328 //
duke@0 1329 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
duke@0 1330 // may customize this version by overriding it for its purposes (e.g., to save/restore
duke@0 1331 // additional registers when doing a VM call).
duke@0 1332 #ifdef CC_INTERP
duke@0 1333 // c++ interpreter never wants to use interp_masm version of call_VM
duke@0 1334 #define VIRTUAL
duke@0 1335 #else
duke@0 1336 #define VIRTUAL virtual
duke@0 1337 #endif
duke@0 1338
duke@0 1339 VIRTUAL void call_VM_leaf_base(
duke@0 1340 address entry_point, // the entry point
duke@0 1341 int number_of_arguments // the number of arguments to pop after the call
duke@0 1342 );
duke@0 1343
duke@0 1344 // This is the base routine called by the different versions of call_VM. The interpreter
duke@0 1345 // may customize this version by overriding it for its purposes (e.g., to save/restore
duke@0 1346 // additional registers when doing a VM call).
duke@0 1347 //
duke@0 1348 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
duke@0 1349 // returns the register which contains the thread upon return. If a thread register has been
duke@0 1350 // specified, the return value will correspond to that register. If no last_java_sp is specified
duke@0 1351 // (noreg) than rsp will be used instead.
duke@0 1352 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
duke@0 1353 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
duke@0 1354 Register java_thread, // the thread if computed before ; use noreg otherwise
duke@0 1355 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
duke@0 1356 address entry_point, // the entry point
duke@0 1357 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
duke@0 1358 bool check_exceptions // whether to check for pending exceptions after return
duke@0 1359 );
duke@0 1360
duke@0 1361 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
duke@0 1362 // The implementation is only non-empty for the InterpreterMacroAssembler,
duke@0 1363 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
duke@0 1364 virtual void check_and_handle_popframe(Register java_thread);
duke@0 1365 virtual void check_and_handle_earlyret(Register java_thread);
duke@0 1366
duke@0 1367 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
duke@0 1368
duke@0 1369 // helpers for FPU flag access
duke@0 1370 // tmp is a temporary register, if none is available use noreg
duke@0 1371 void save_rax (Register tmp);
duke@0 1372 void restore_rax(Register tmp);
duke@0 1373
duke@0 1374 public:
duke@0 1375 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
duke@0 1376
duke@0 1377 // Support for NULL-checks
duke@0 1378 //
duke@0 1379 // Generates code that causes a NULL OS exception if the content of reg is NULL.
duke@0 1380 // If the accessed location is M[reg + offset] and the offset is known, provide the
duke@0 1381 // offset. No explicit code generation is needed if the offset is within a certain
duke@0 1382 // range (0 <= offset <= page_size).
duke@0 1383
duke@0 1384 void null_check(Register reg, int offset = -1);
kvn@168 1385 static bool needs_explicit_null_check(intptr_t offset);
duke@0 1386
duke@0 1387 // Required platform-specific helpers for Label::patch_instructions.
duke@0 1388 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
duke@0 1389 void pd_patch_instruction(address branch, address target);
duke@0 1390 #ifndef PRODUCT
duke@0 1391 static void pd_print_patched_instruction(address branch);
duke@0 1392 #endif
duke@0 1393
duke@0 1394 // The following 4 methods return the offset of the appropriate move instruction
duke@0 1395
duke@0 1396 // Support for fast byte/word loading with zero extension (depending on particular CPU)
duke@0 1397 int load_unsigned_byte(Register dst, Address src);
duke@0 1398 int load_unsigned_word(Register dst, Address src);
duke@0 1399
duke@0 1400 // Support for fast byte/word loading with sign extension (depending on particular CPU)
duke@0 1401 int load_signed_byte(Register dst, Address src);
duke@0 1402 int load_signed_word(Register dst, Address src);
duke@0 1403
duke@0 1404 // Support for sign-extension (hi:lo = extend_sign(lo))
duke@0 1405 void extend_sign(Register hi, Register lo);
duke@0 1406
duke@0 1407 // Support for inc/dec with optimal instruction selection depending on value
never@307 1408
never@307 1409 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
never@307 1410 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
never@307 1411
never@307 1412 void decrementl(Address dst, int value = 1);
never@307 1413 void decrementl(Register reg, int value = 1);
never@307 1414
never@307 1415 void decrementq(Register reg, int value = 1);
never@307 1416 void decrementq(Address dst, int value = 1);
never@307 1417
never@307 1418 void incrementl(Address dst, int value = 1);
never@307 1419 void incrementl(Register reg, int value = 1);
never@307 1420
never@307 1421 void incrementq(Register reg, int value = 1);
never@307 1422 void incrementq(Address dst, int value = 1);
never@307 1423
duke@0 1424
duke@0 1425 // Support optimal SSE move instructions.
duke@0 1426 void movflt(XMMRegister dst, XMMRegister src) {
duke@0 1427 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
duke@0 1428 else { movss (dst, src); return; }
duke@0 1429 }
duke@0 1430 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
duke@0 1431 void movflt(XMMRegister dst, AddressLiteral src);
duke@0 1432 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
duke@0 1433
duke@0 1434 void movdbl(XMMRegister dst, XMMRegister src) {
duke@0 1435 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
duke@0 1436 else { movsd (dst, src); return; }
duke@0 1437 }
duke@0 1438
duke@0 1439 void movdbl(XMMRegister dst, AddressLiteral src);
duke@0 1440
duke@0 1441 void movdbl(XMMRegister dst, Address src) {
duke@0 1442 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
duke@0 1443 else { movlpd(dst, src); return; }
duke@0 1444 }
duke@0 1445 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
duke@0 1446
never@307 1447 void incrementl(AddressLiteral dst);
never@307 1448 void incrementl(ArrayAddress dst);
duke@0 1449
duke@0 1450 // Alignment
duke@0 1451 void align(int modulus);
duke@0 1452
duke@0 1453 // Misc
duke@0 1454 void fat_nop(); // 5 byte nop
duke@0 1455
duke@0 1456 // Stack frame creation/removal
duke@0 1457 void enter();
duke@0 1458 void leave();
duke@0 1459
duke@0 1460 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
duke@0 1461 // The pointer will be loaded into the thread register.
duke@0 1462 void get_thread(Register thread);
duke@0 1463
apetrusenko@365 1464
duke@0 1465 // Support for VM calls
duke@0 1466 //
duke@0 1467 // It is imperative that all calls into the VM are handled via the call_VM macros.
duke@0 1468 // They make sure that the stack linkage is setup correctly. call_VM's correspond
duke@0 1469 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
duke@0 1470
never@307 1471
never@307 1472 void call_VM(Register oop_result,
never@307 1473 address entry_point,
never@307 1474 bool check_exceptions = true);
never@307 1475 void call_VM(Register oop_result,
never@307 1476 address entry_point,
never@307 1477 Register arg_1,
never@307 1478 bool check_exceptions = true);
never@307 1479 void call_VM(Register oop_result,
never@307 1480 address entry_point,
never@307 1481 Register arg_1, Register arg_2,
never@307 1482 bool check_exceptions = true);
never@307 1483 void call_VM(Register oop_result,
never@307 1484 address entry_point,
never@307 1485 Register arg_1, Register arg_2, Register arg_3,
never@307 1486 bool check_exceptions = true);
never@307 1487
never@307 1488 // Overloadings with last_Java_sp
never@307 1489 void call_VM(Register oop_result,
never@307 1490 Register last_java_sp,
never@307 1491 address entry_point,
never@307 1492 int number_of_arguments = 0,
never@307 1493 bool check_exceptions = true);
never@307 1494 void call_VM(Register oop_result,
never@307 1495 Register last_java_sp,
never@307 1496 address entry_point,
never@307 1497 Register arg_1, bool
never@307 1498 check_exceptions = true);
never@307 1499 void call_VM(Register oop_result,
never@307 1500 Register last_java_sp,
never@307 1501 address entry_point,
never@307 1502 Register arg_1, Register arg_2,
never@307 1503 bool check_exceptions = true);
never@307 1504 void call_VM(Register oop_result,
never@307 1505 Register last_java_sp,
never@307 1506 address entry_point,
never@307 1507 Register arg_1, Register arg_2, Register arg_3,
never@307 1508 bool check_exceptions = true);
never@307 1509
never@307 1510 void call_VM_leaf(address entry_point,
never@307 1511 int number_of_arguments = 0);
never@307 1512 void call_VM_leaf(address entry_point,
never@307 1513 Register arg_1);
never@307 1514 void call_VM_leaf(address entry_point,
never@307 1515 Register arg_1, Register arg_2);
never@307 1516 void call_VM_leaf(address entry_point,
never@307 1517 Register arg_1, Register arg_2, Register arg_3);
duke@0 1518
duke@0 1519 // last Java Frame (fills frame anchor)
never@307 1520 void set_last_Java_frame(Register thread,
never@307 1521 Register last_java_sp,
never@307 1522 Register last_java_fp,
never@307 1523 address last_java_pc);
never@307 1524
never@307 1525 // thread in the default location (r15_thread on 64bit)
never@307 1526 void set_last_Java_frame(Register last_java_sp,
never@307 1527 Register last_java_fp,
never@307 1528 address last_java_pc);
never@307 1529
duke@0 1530 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
duke@0 1531
never@307 1532 // thread in the default location (r15_thread on 64bit)
never@307 1533 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
never@307 1534
duke@0 1535 // Stores
duke@0 1536 void store_check(Register obj); // store check for obj - register is destroyed afterwards
duke@0 1537 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
duke@0 1538
apetrusenko@365 1539 void g1_write_barrier_pre(Register obj,
apetrusenko@365 1540 #ifndef _LP64
apetrusenko@365 1541 Register thread,
apetrusenko@365 1542 #endif
apetrusenko@365 1543 Register tmp,
apetrusenko@365 1544 Register tmp2,
apetrusenko@365 1545 bool tosca_live);
apetrusenko@365 1546 void g1_write_barrier_post(Register store_addr,
apetrusenko@365 1547 Register new_val,
apetrusenko@365 1548 #ifndef _LP64
apetrusenko@365 1549 Register thread,
apetrusenko@365 1550 #endif
apetrusenko@365 1551 Register tmp,
apetrusenko@365 1552 Register tmp2);
ysr@345 1553
ysr@345 1554
duke@0 1555 // split store_check(Register obj) to enhance instruction interleaving
duke@0 1556 void store_check_part_1(Register obj);
duke@0 1557 void store_check_part_2(Register obj);
duke@0 1558
duke@0 1559 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
duke@0 1560 void c2bool(Register x);
duke@0 1561
duke@0 1562 // C++ bool manipulation
duke@0 1563
duke@0 1564 void movbool(Register dst, Address src);
duke@0 1565 void movbool(Address dst, bool boolconst);
duke@0 1566 void movbool(Address dst, Register src);
duke@0 1567 void testbool(Register dst);
duke@0 1568
never@307 1569 // oop manipulations
never@307 1570 void load_klass(Register dst, Register src);
never@307 1571 void store_klass(Register dst, Register src);
never@307 1572
never@307 1573 void load_prototype_header(Register dst, Register src);
never@307 1574
never@307 1575 #ifdef _LP64
never@307 1576 void store_klass_gap(Register dst, Register src);
never@307 1577
never@307 1578 void load_heap_oop(Register dst, Address src);
never@307 1579 void store_heap_oop(Address dst, Register src);
never@307 1580 void encode_heap_oop(Register r);
never@307 1581 void decode_heap_oop(Register r);
never@307 1582 void encode_heap_oop_not_null(Register r);
never@307 1583 void decode_heap_oop_not_null(Register r);
never@307 1584 void encode_heap_oop_not_null(Register dst, Register src);
never@307 1585 void decode_heap_oop_not_null(Register dst, Register src);
never@307 1586
never@307 1587 void set_narrow_oop(Register dst, jobject obj);
never@307 1588
never@307 1589 // if heap base register is used - reinit it with the correct value
never@307 1590 void reinit_heapbase();
never@307 1591 #endif // _LP64
never@307 1592
never@307 1593 // Int division/remainder for Java
duke@0 1594 // (as idivl, but checks for special case as described in JVM spec.)
duke@0 1595 // returns idivl instruction offset for implicit exception handling
duke@0 1596 int corrected_idivl(Register reg);
duke@0 1597
never@307 1598 // Long division/remainder for Java
never@307 1599 // (as idivq, but checks for special case as described in JVM spec.)
never@307 1600 // returns idivq instruction offset for implicit exception handling
never@307 1601 int corrected_idivq(Register reg);
never@307 1602
duke@0 1603 void int3();
duke@0 1604
never@307 1605 // Long operation macros for a 32bit cpu
duke@0 1606 // Long negation for Java
duke@0 1607 void lneg(Register hi, Register lo);
duke@0 1608
duke@0 1609 // Long multiplication for Java
never@307 1610 // (destroys contents of eax, ebx, ecx and edx)
duke@0 1611 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
duke@0 1612
duke@0 1613 // Long shifts for Java
duke@0 1614 // (semantics as described in JVM spec.)
duke@0 1615 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
duke@0 1616 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
duke@0 1617
duke@0 1618 // Long compare for Java
duke@0 1619 // (semantics as described in JVM spec.)
duke@0 1620 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
duke@0 1621
never@307 1622
never@307 1623 // misc
never@307 1624
never@307 1625 // Sign extension
never@307 1626 void sign_extend_short(Register reg);
never@307 1627 void sign_extend_byte(Register reg);
never@307 1628
never@307 1629 // Division by power of 2, rounding towards 0
never@307 1630 void division_with_shift(Register reg, int shift_value);
never@307 1631
duke@0 1632 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
duke@0 1633 //
duke@0 1634 // CF (corresponds to C0) if x < y
duke@0 1635 // PF (corresponds to C2) if unordered
duke@0 1636 // ZF (corresponds to C3) if x = y
duke@0 1637 //
duke@0 1638 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
duke@0 1639 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
duke@0 1640 void fcmp(Register tmp);
duke@0 1641 // Variant of the above which allows y to be further down the stack
duke@0 1642 // and which only pops x and y if specified. If pop_right is
duke@0 1643 // specified then pop_left must also be specified.
duke@0 1644 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
duke@0 1645
duke@0 1646 // Floating-point comparison for Java
duke@0 1647 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
duke@0 1648 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
duke@0 1649 // (semantics as described in JVM spec.)
duke@0 1650 void fcmp2int(Register dst, bool unordered_is_less);
duke@0 1651 // Variant of the above which allows y to be further down the stack
duke@0 1652 // and which only pops x and y if specified. If pop_right is
duke@0 1653 // specified then pop_left must also be specified.
duke@0 1654 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
duke@0 1655
duke@0 1656 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
duke@0 1657 // tmp is a temporary register, if none is available use noreg
duke@0 1658 void fremr(Register tmp);
duke@0 1659
duke@0 1660
duke@0 1661 // same as fcmp2int, but using SSE2
duke@0 1662 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
duke@0 1663 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
duke@0 1664
duke@0 1665 // Inlined sin/cos generator for Java; must not use CPU instruction
duke@0 1666 // directly on Intel as it does not have high enough precision
duke@0 1667 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
duke@0 1668 // number of FPU stack slots in use; all but the topmost will
duke@0 1669 // require saving if a slow case is necessary. Assumes argument is
duke@0 1670 // on FP TOS; result is on FP TOS. No cpu registers are changed by
duke@0 1671 // this code.
duke@0 1672 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
duke@0 1673
duke@0 1674 // branch to L if FPU flag C2 is set/not set
duke@0 1675 // tmp is a temporary register, if none is available use noreg
duke@0 1676 void jC2 (Register tmp, Label& L);
duke@0 1677 void jnC2(Register tmp, Label& L);
duke@0 1678
duke@0 1679 // Pop ST (ffree & fincstp combined)
duke@0 1680 void fpop();
duke@0 1681
duke@0 1682 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
duke@0 1683 void push_fTOS();
duke@0 1684
duke@0 1685 // pops double TOS element from CPU stack and pushes on FPU stack
duke@0 1686 void pop_fTOS();
duke@0 1687
duke@0 1688 void empty_FPU_stack();
duke@0 1689
duke@0 1690 void push_IU_state();
duke@0 1691 void pop_IU_state();
duke@0 1692
duke@0 1693 void push_FPU_state();
duke@0 1694 void pop_FPU_state();
duke@0 1695
duke@0 1696 void push_CPU_state();
duke@0 1697 void pop_CPU_state();
duke@0 1698
duke@0 1699 // Round up to a power of two
duke@0 1700 void round_to(Register reg, int modulus);
duke@0 1701
duke@0 1702 // Callee saved registers handling
duke@0 1703 void push_callee_saved_registers();
duke@0 1704 void pop_callee_saved_registers();
duke@0 1705
duke@0 1706 // allocation
duke@0 1707 void eden_allocate(
duke@0 1708 Register obj, // result: pointer to object after successful allocation
duke@0 1709 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@0 1710 int con_size_in_bytes, // object size in bytes if known at compile time
duke@0 1711 Register t1, // temp register
duke@0 1712 Label& slow_case // continuation point if fast allocation fails
duke@0 1713 );
duke@0 1714 void tlab_allocate(
duke@0 1715 Register obj, // result: pointer to object after successful allocation
duke@0 1716 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@0 1717 int con_size_in_bytes, // object size in bytes if known at compile time
duke@0 1718 Register t1, // temp register
duke@0 1719 Register t2, // temp register
duke@0 1720 Label& slow_case // continuation point if fast allocation fails
duke@0 1721 );
duke@0 1722 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
duke@0 1723
duke@0 1724 //----
duke@0 1725 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
duke@0 1726
duke@0 1727 // Debugging
never@307 1728
never@307 1729 // only if +VerifyOops
never@307 1730 void verify_oop(Register reg, const char* s = "broken oop");
duke@0 1731 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
duke@0 1732
never@307 1733 // only if +VerifyFPU
never@307 1734 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
never@307 1735
never@307 1736 // prints msg, dumps registers and stops execution
never@307 1737 void stop(const char* msg);
never@307 1738
never@307 1739 // prints msg and continues
never@307 1740 void warn(const char* msg);
never@307 1741
never@307 1742 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
never@307 1743 static void debug64(char* msg, int64_t pc, int64_t regs[]);
never@307 1744
duke@0 1745 void os_breakpoint();
never@307 1746
duke@0 1747 void untested() { stop("untested"); }
never@307 1748
duke@0 1749 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
never@307 1750
duke@0 1751 void should_not_reach_here() { stop("should not reach here"); }
never@307 1752
duke@0 1753 void print_CPU_state();
duke@0 1754
duke@0 1755 // Stack overflow checking
duke@0 1756 void bang_stack_with_offset(int offset) {
duke@0 1757 // stack grows down, caller passes positive offset
duke@0 1758 assert(offset > 0, "must bang with negative offset");
duke@0 1759 movl(Address(rsp, (-offset)), rax);
duke@0 1760 }
duke@0 1761
duke@0 1762 // Writes to stack successive pages until offset reached to check for
duke@0 1763 // stack overflow + shadow pages. Also, clobbers tmp
duke@0 1764 void bang_stack_size(Register size, Register tmp);
duke@0 1765
duke@0 1766 // Support for serializing memory accesses between threads
duke@0 1767 void serialize_memory(Register thread, Register tmp);
duke@0 1768
duke@0 1769 void verify_tlab();
duke@0 1770
duke@0 1771 // Biased locking support
duke@0 1772 // lock_reg and obj_reg must be loaded up with the appropriate values.
duke@0 1773 // swap_reg must be rax, and is killed.
duke@0 1774 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
duke@0 1775 // be killed; if not supplied, push/pop will be used internally to
duke@0 1776 // allocate a temporary (inefficient, avoid if possible).
duke@0 1777 // Optional slow case is for implementations (interpreter and C1) which branch to
duke@0 1778 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
duke@0 1779 // Returns offset of first potentially-faulting instruction for null
duke@0 1780 // check info (currently consumed only by C1). If
duke@0 1781 // swap_reg_contains_mark is true then returns -1 as it is assumed
duke@0 1782 // the calling code has already passed any potential faults.
kvn@423 1783 int biased_locking_enter(Register lock_reg, Register obj_reg,
kvn@423 1784 Register swap_reg, Register tmp_reg,
duke@0 1785 bool swap_reg_contains_mark,
duke@0 1786 Label& done, Label* slow_case = NULL,
duke@0 1787 BiasedLockingCounters* counters = NULL);
duke@0 1788 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
duke@0 1789
duke@0 1790
duke@0 1791 Condition negate_condition(Condition cond);
duke@0 1792
duke@0 1793 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
duke@0 1794 // operands. In general the names are modified to avoid hiding the instruction in Assembler
duke@0 1795 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
duke@0 1796 // here in MacroAssembler. The major exception to this rule is call
duke@0 1797
duke@0 1798 // Arithmetics
duke@0 1799
never@307 1800
never@307 1801 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
never@307 1802 void addptr(Address dst, Register src);
never@307 1803
never@307 1804 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
never@307 1805 void addptr(Register dst, int32_t src);
never@307 1806 void addptr(Register dst, Register src);
never@307 1807
never@307 1808 void andptr(Register dst, int32_t src);
never@307 1809 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
never@307 1810
never@307 1811 void cmp8(AddressLiteral src1, int imm);
never@307 1812
never@307 1813 // renamed to drag out the casting of address to int32_t/intptr_t
duke@0 1814 void cmp32(Register src1, int32_t imm);
duke@0 1815
duke@0 1816 void cmp32(AddressLiteral src1, int32_t imm);
duke@0 1817 // compare reg - mem, or reg - &mem
duke@0 1818 void cmp32(Register src1, AddressLiteral src2);
duke@0 1819
duke@0 1820 void cmp32(Register src1, Address src2);
duke@0 1821
never@307 1822 #ifndef _LP64
never@307 1823 void cmpoop(Address dst, jobject obj);
never@307 1824 void cmpoop(Register dst, jobject obj);
never@307 1825 #endif // _LP64
never@307 1826
duke@0 1827 // NOTE src2 must be the lval. This is NOT an mem-mem compare
duke@0 1828 void cmpptr(Address src1, AddressLiteral src2);
duke@0 1829
duke@0 1830 void cmpptr(Register src1, AddressLiteral src2);
duke@0 1831
never@307 1832 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@307 1833 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@307 1834 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@307 1835
never@307 1836 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@307 1837 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@307 1838
never@307 1839 // cmp64 to avoild hiding cmpq
never@307 1840 void cmp64(Register src1, AddressLiteral src);
never@307 1841
never@307 1842 void cmpxchgptr(Register reg, Address adr);
never@307 1843
never@307 1844 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
never@307 1845
never@307 1846
never@307 1847 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
never@307 1848
never@307 1849
never@307 1850 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
never@307 1851
never@307 1852 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
never@307 1853
never@307 1854 void shlptr(Register dst, int32_t shift);
never@307 1855 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
never@307 1856
never@307 1857 void shrptr(Register dst, int32_t shift);
never@307 1858 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
never@307 1859
never@307 1860 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
never@307 1861 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
never@307 1862
never@307 1863 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
never@307 1864
never@307 1865 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
never@307 1866 void subptr(Register dst, int32_t src);
never@307 1867 void subptr(Register dst, Register src);
never@307 1868
never@307 1869
never@307 1870 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
never@307 1871 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
never@307 1872
never@307 1873 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
never@307 1874 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
never@307 1875
never@307 1876 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
never@307 1877
never@307 1878
duke@0 1879
duke@0 1880 // Helper functions for statistics gathering.
duke@0 1881 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
duke@0 1882 void cond_inc32(Condition cond, AddressLiteral counter_addr);
duke@0 1883 // Unconditional atomic increment.
duke@0 1884 void atomic_incl(AddressLiteral counter_addr);
duke@0 1885
duke@0 1886 void lea(Register dst, AddressLiteral adr);
duke@0 1887 void lea(Address dst, AddressLiteral adr);
never@307 1888 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
never@307 1889
never@307 1890 void leal32(Register dst, Address src) { leal(dst, src); }
never@307 1891
never@307 1892 void test32(Register src1, AddressLiteral src2);
never@307 1893
never@307 1894 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@307 1895 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@307 1896 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@307 1897
never@307 1898 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
never@307 1899 void testptr(Register src1, Register src2);
never@307 1900
never@307 1901 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
never@307 1902 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
duke@0 1903
duke@0 1904 // Calls
duke@0 1905
duke@0 1906 void call(Label& L, relocInfo::relocType rtype);
duke@0 1907 void call(Register entry);
duke@0 1908
duke@0 1909 // NOTE: this call tranfers to the effective address of entry NOT
duke@0 1910 // the address contained by entry. This is because this is more natural
duke@0 1911 // for jumps/calls.
duke@0 1912 void call(AddressLiteral entry);
duke@0 1913
duke@0 1914 // Jumps
duke@0 1915
duke@0 1916 // NOTE: these jumps tranfer to the effective address of dst NOT
duke@0 1917 // the address contained by dst. This is because this is more natural
duke@0 1918 // for jumps/calls.
duke@0 1919 void jump(AddressLiteral dst);
duke@0 1920 void jump_cc(Condition cc, AddressLiteral dst);
duke@0 1921
duke@0 1922 // 32bit can do a case table jump in one instruction but we no longer allow the base
duke@0 1923 // to be installed in the Address class. This jump will tranfers to the address
duke@0 1924 // contained in the location described by entry (not the address of entry)
duke@0 1925 void jump(ArrayAddress entry);
duke@0 1926
duke@0 1927 // Floating
duke@0 1928
duke@0 1929 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
duke@0 1930 void andpd(XMMRegister dst, AddressLiteral src);
duke@0 1931
duke@0 1932 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
duke@0 1933 void comiss(XMMRegister dst, AddressLiteral src);
duke@0 1934
duke@0 1935 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
duke@0 1936 void comisd(XMMRegister dst, AddressLiteral src);
duke@0 1937
duke@0 1938 void fldcw(Address src) { Assembler::fldcw(src); }
duke@0 1939 void fldcw(AddressLiteral src);
duke@0 1940
duke@0 1941 void fld_s(int index) { Assembler::fld_s(index); }
duke@0 1942 void fld_s(Address src) { Assembler::fld_s(src); }
duke@0 1943 void fld_s(AddressLiteral src);
duke@0 1944
duke@0 1945 void fld_d(Address src) { Assembler::fld_d(src); }
duke@0 1946 void fld_d(AddressLiteral src);
duke@0 1947
duke@0 1948 void fld_x(Address src) { Assembler::fld_x(src); }
duke@0 1949 void fld_x(AddressLiteral src);
duke@0 1950
duke@0 1951 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
duke@0 1952 void ldmxcsr(AddressLiteral src);
duke@0 1953
never@307 1954 private:
never@307 1955 // these are private because users should be doing movflt/movdbl
never@307 1956
duke@0 1957 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
duke@0 1958 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
duke@0 1959 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
duke@0 1960 void movss(XMMRegister dst, AddressLiteral src);
duke@0 1961
never@307 1962 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
never@307 1963 void movlpd(XMMRegister dst, AddressLiteral src);
never@307 1964
never@307 1965 public:
never@307 1966
duke@0 1967 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
duke@0 1968 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
duke@0 1969 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
duke@0 1970 void movsd(XMMRegister dst, AddressLiteral src);
duke@0 1971
duke@0 1972 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
duke@0 1973 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
duke@0 1974 void ucomiss(XMMRegister dst, AddressLiteral src);
duke@0 1975
duke@0 1976 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
duke@0 1977 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
duke@0 1978 void ucomisd(XMMRegister dst, AddressLiteral src);
duke@0 1979
duke@0 1980 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
duke@0 1981 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
duke@0 1982 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
duke@0 1983 void xorpd(XMMRegister dst, AddressLiteral src);
duke@0 1984
duke@0 1985 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
duke@0 1986 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
duke@0 1987 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
duke@0 1988 void xorps(XMMRegister dst, AddressLiteral src);
duke@0 1989
duke@0 1990 // Data
duke@0 1991
never@307 1992 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@307 1993
never@307 1994 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@307 1995 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@307 1996
duke@0 1997 void movoop(Register dst, jobject obj);
duke@0 1998 void movoop(Address dst, jobject obj);
duke@0 1999
duke@0 2000 void movptr(ArrayAddress dst, Register src);
duke@0 2001 // can this do an lea?
duke@0 2002 void movptr(Register dst, ArrayAddress src);
duke@0 2003
never@307 2004 void movptr(Register dst, Address src);
never@307 2005
duke@0 2006 void movptr(Register dst, AddressLiteral src);
duke@0 2007
never@307 2008 void movptr(Register dst, intptr_t src);
never@307 2009 void movptr(Register dst, Register src);
never@307 2010 void movptr(Address dst, intptr_t src);
never@307 2011
never@307 2012 void movptr(Address dst, Register src);
never@307 2013
never@307 2014 #ifdef _LP64
never@307 2015 // Generally the next two are only used for moving NULL
never@307 2016 // Although there are situations in initializing the mark word where
never@307 2017 // they could be used. They are dangerous.
never@307 2018
never@307 2019 // They only exist on LP64 so that int32_t and intptr_t are not the same
never@307 2020 // and we have ambiguous declarations.
never@307 2021
never@307 2022 void movptr(Address dst, int32_t imm32);
never@307 2023 void movptr(Register dst, int32_t imm32);
never@307 2024 #endif // _LP64
never@307 2025
duke@0 2026 // to avoid hiding movl
duke@0 2027 void mov32(AddressLiteral dst, Register src);
duke@0 2028 void mov32(Register dst, AddressLiteral src);
never@307 2029
duke@0 2030 // to avoid hiding movb
duke@0 2031 void movbyte(ArrayAddress dst, int src);
duke@0 2032
duke@0 2033 // Can push value or effective address
duke@0 2034 void pushptr(AddressLiteral src);
duke@0 2035
never@307 2036 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
never@307 2037 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
never@307 2038
never@307 2039 void pushoop(jobject obj);
never@307 2040
never@307 2041 // sign extend as need a l to ptr sized element
never@307 2042 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
never@307 2043 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
never@307 2044
never@307 2045
duke@0 2046 #undef VIRTUAL
duke@0 2047
duke@0 2048 };
duke@0 2049
duke@0 2050 /**
duke@0 2051 * class SkipIfEqual:
duke@0 2052 *
duke@0 2053 * Instantiating this class will result in assembly code being output that will
duke@0 2054 * jump around any code emitted between the creation of the instance and it's
duke@0 2055 * automatic destruction at the end of a scope block, depending on the value of
duke@0 2056 * the flag passed to the constructor, which will be checked at run-time.
duke@0 2057 */
duke@0 2058 class SkipIfEqual {
duke@0 2059 private:
duke@0 2060 MacroAssembler* _masm;
duke@0 2061 Label _label;
duke@0 2062
duke@0 2063 public:
duke@0 2064 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
duke@0 2065 ~SkipIfEqual();
duke@0 2066 };
duke@0 2067
duke@0 2068 #ifdef ASSERT
duke@0 2069 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
duke@0 2070 #endif