annotate src/cpu/sparc/vm/register_sparc.hpp @ 1563:c18cbe5936b8

6941466: Oracle rebranding changes for Hotspot repositories Summary: Change all the Sun copyrights to Oracle copyright Reviewed-by: ohair
author trims
date Thu, 27 May 2010 19:08:38 -0700
parents a61af66fc99e
children f95d63e2154a
rev   line source
duke@0 1 /*
trims@1563 2 * Copyright (c) 2000, 2007, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1563 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1563 20 * or visit www.oracle.com if you need additional information or have any
trims@1563 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 // forward declaration
duke@0 26 class Address;
duke@0 27 class VMRegImpl;
duke@0 28 typedef VMRegImpl* VMReg;
duke@0 29
duke@0 30
duke@0 31 // Use Register as shortcut
duke@0 32 class RegisterImpl;
duke@0 33 typedef RegisterImpl* Register;
duke@0 34
duke@0 35
duke@0 36 inline Register as_Register(int encoding) {
duke@0 37 return (Register)(intptr_t) encoding;
duke@0 38 }
duke@0 39
duke@0 40 // The implementation of integer registers for the SPARC architecture
duke@0 41 class RegisterImpl: public AbstractRegisterImpl {
duke@0 42 public:
duke@0 43 enum {
duke@0 44 log_set_size = 3, // the number of bits to encode the set register number
duke@0 45 number_of_sets = 4, // the number of registers sets (in, local, out, global)
duke@0 46 number_of_registers = number_of_sets << log_set_size,
duke@0 47
duke@0 48 iset_no = 3, ibase = iset_no << log_set_size, // the in register set
duke@0 49 lset_no = 2, lbase = lset_no << log_set_size, // the local register set
duke@0 50 oset_no = 1, obase = oset_no << log_set_size, // the output register set
duke@0 51 gset_no = 0, gbase = gset_no << log_set_size // the global register set
duke@0 52 };
duke@0 53
duke@0 54
duke@0 55 friend Register as_Register(int encoding);
duke@0 56 // set specific construction
duke@0 57 friend Register as_iRegister(int number);
duke@0 58 friend Register as_lRegister(int number);
duke@0 59 friend Register as_oRegister(int number);
duke@0 60 friend Register as_gRegister(int number);
duke@0 61
duke@0 62 VMReg as_VMReg();
duke@0 63
duke@0 64 // accessors
duke@0 65 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
duke@0 66 const char* name() const;
duke@0 67
duke@0 68 // testers
duke@0 69 bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); }
duke@0 70 bool is_even() const { return (encoding() & 1) == 0; }
duke@0 71 bool is_in() const { return (encoding() >> log_set_size) == iset_no; }
duke@0 72 bool is_local() const { return (encoding() >> log_set_size) == lset_no; }
duke@0 73 bool is_out() const { return (encoding() >> log_set_size) == oset_no; }
duke@0 74 bool is_global() const { return (encoding() >> log_set_size) == gset_no; }
duke@0 75
duke@0 76 // derived registers, offsets, and addresses
duke@0 77 Register successor() const { return as_Register(encoding() + 1); }
duke@0 78
duke@0 79 int input_number() const {
duke@0 80 assert(is_in(), "must be input register");
duke@0 81 return encoding() - ibase;
duke@0 82 }
duke@0 83
duke@0 84 Register after_save() const {
duke@0 85 assert(is_out() || is_global(), "register not visible after save");
duke@0 86 return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this;
duke@0 87 }
duke@0 88
duke@0 89 Register after_restore() const {
duke@0 90 assert(is_in() || is_global(), "register not visible after restore");
duke@0 91 return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this;
duke@0 92 }
duke@0 93
duke@0 94 int sp_offset_in_saved_window() const {
duke@0 95 assert(is_in() || is_local(), "only i and l registers are saved in frame");
duke@0 96 return encoding() - lbase;
duke@0 97 }
duke@0 98
duke@0 99 inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp
duke@0 100 };
duke@0 101
duke@0 102
duke@0 103 // set specific construction
duke@0 104 inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); }
duke@0 105 inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); }
duke@0 106 inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); }
duke@0 107 inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); }
duke@0 108
duke@0 109 // The integer registers of the SPARC architecture
duke@0 110
duke@0 111 CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1));
duke@0 112
duke@0 113 CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0));
duke@0 114 CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1));
duke@0 115 CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2));
duke@0 116 CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3));
duke@0 117 CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4));
duke@0 118 CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5));
duke@0 119 CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6));
duke@0 120 CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7));
duke@0 121
duke@0 122 CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0));
duke@0 123 CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1));
duke@0 124 CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2));
duke@0 125 CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3));
duke@0 126 CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4));
duke@0 127 CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5));
duke@0 128 CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6));
duke@0 129 CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7));
duke@0 130
duke@0 131 CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0));
duke@0 132 CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1));
duke@0 133 CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2));
duke@0 134 CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3));
duke@0 135 CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4));
duke@0 136 CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5));
duke@0 137 CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6));
duke@0 138 CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7));
duke@0 139
duke@0 140 CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0));
duke@0 141 CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1));
duke@0 142 CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2));
duke@0 143 CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3));
duke@0 144 CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4));
duke@0 145 CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5));
duke@0 146 CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6));
duke@0 147 CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7));
duke@0 148
duke@0 149 CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6));
duke@0 150 CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6));
duke@0 151
duke@0 152 //
duke@0 153 // Because sparc has so many registers, #define'ing values for the is
duke@0 154 // beneficial in code size and the cost of some of the dangers of
duke@0 155 // defines. We don't use them on Intel because win32 uses asm
duke@0 156 // directives which use the same names for registers as Hotspot does,
duke@0 157 // so #defines would screw up the inline assembly. If a particular
duke@0 158 // file has a problem with these defines then it's possible to turn
duke@0 159 // them off in that file by defining DONT_USE_REGISTER_DEFINES.
duke@0 160 // register_definition_sparc.cpp does that so that it's able to
duke@0 161 // provide real definitions of these registers for use in debuggers
duke@0 162 // and such.
duke@0 163 //
duke@0 164
duke@0 165 #ifndef DONT_USE_REGISTER_DEFINES
duke@0 166 #define noreg ((Register)(noreg_RegisterEnumValue))
duke@0 167
duke@0 168 #define G0 ((Register)(G0_RegisterEnumValue))
duke@0 169 #define G1 ((Register)(G1_RegisterEnumValue))
duke@0 170 #define G2 ((Register)(G2_RegisterEnumValue))
duke@0 171 #define G3 ((Register)(G3_RegisterEnumValue))
duke@0 172 #define G4 ((Register)(G4_RegisterEnumValue))
duke@0 173 #define G5 ((Register)(G5_RegisterEnumValue))
duke@0 174 #define G6 ((Register)(G6_RegisterEnumValue))
duke@0 175 #define G7 ((Register)(G7_RegisterEnumValue))
duke@0 176
duke@0 177 #define O0 ((Register)(O0_RegisterEnumValue))
duke@0 178 #define O1 ((Register)(O1_RegisterEnumValue))
duke@0 179 #define O2 ((Register)(O2_RegisterEnumValue))
duke@0 180 #define O3 ((Register)(O3_RegisterEnumValue))
duke@0 181 #define O4 ((Register)(O4_RegisterEnumValue))
duke@0 182 #define O5 ((Register)(O5_RegisterEnumValue))
duke@0 183 #define O6 ((Register)(O6_RegisterEnumValue))
duke@0 184 #define O7 ((Register)(O7_RegisterEnumValue))
duke@0 185
duke@0 186 #define L0 ((Register)(L0_RegisterEnumValue))
duke@0 187 #define L1 ((Register)(L1_RegisterEnumValue))
duke@0 188 #define L2 ((Register)(L2_RegisterEnumValue))
duke@0 189 #define L3 ((Register)(L3_RegisterEnumValue))
duke@0 190 #define L4 ((Register)(L4_RegisterEnumValue))
duke@0 191 #define L5 ((Register)(L5_RegisterEnumValue))
duke@0 192 #define L6 ((Register)(L6_RegisterEnumValue))
duke@0 193 #define L7 ((Register)(L7_RegisterEnumValue))
duke@0 194
duke@0 195 #define I0 ((Register)(I0_RegisterEnumValue))
duke@0 196 #define I1 ((Register)(I1_RegisterEnumValue))
duke@0 197 #define I2 ((Register)(I2_RegisterEnumValue))
duke@0 198 #define I3 ((Register)(I3_RegisterEnumValue))
duke@0 199 #define I4 ((Register)(I4_RegisterEnumValue))
duke@0 200 #define I5 ((Register)(I5_RegisterEnumValue))
duke@0 201 #define I6 ((Register)(I6_RegisterEnumValue))
duke@0 202 #define I7 ((Register)(I7_RegisterEnumValue))
duke@0 203
duke@0 204 #define FP ((Register)(FP_RegisterEnumValue))
duke@0 205 #define SP ((Register)(SP_RegisterEnumValue))
duke@0 206 #endif // DONT_USE_REGISTER_DEFINES
duke@0 207
duke@0 208 // Use FloatRegister as shortcut
duke@0 209 class FloatRegisterImpl;
duke@0 210 typedef FloatRegisterImpl* FloatRegister;
duke@0 211
duke@0 212
duke@0 213 // construction
duke@0 214 inline FloatRegister as_FloatRegister(int encoding) {
duke@0 215 return (FloatRegister)(intptr_t)encoding;
duke@0 216 }
duke@0 217
duke@0 218 // The implementation of float registers for the SPARC architecture
duke@0 219
duke@0 220 class FloatRegisterImpl: public AbstractRegisterImpl {
duke@0 221 public:
duke@0 222 enum {
duke@0 223 number_of_registers = 64
duke@0 224 };
duke@0 225
duke@0 226 enum Width {
duke@0 227 S = 1, D = 2, Q = 3
duke@0 228 };
duke@0 229
duke@0 230 // construction
duke@0 231 VMReg as_VMReg( );
duke@0 232
duke@0 233 // accessors
duke@0 234 int encoding() const { assert(is_valid(), "invalid register"); return value(); }
duke@0 235
duke@0 236 public:
duke@0 237 int encoding(Width w) const {
duke@0 238 const int c = encoding();
duke@0 239 switch (w) {
duke@0 240 case S:
duke@0 241 assert(c < 32, "bad single float register");
duke@0 242 return c;
duke@0 243
duke@0 244 case D:
duke@0 245 assert(c < 64 && (c & 1) == 0, "bad double float register");
duke@0 246 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
duke@0 247 return (c & 0x1e) | ((c & 0x20) >> 5);
duke@0 248
duke@0 249 case Q:
duke@0 250 assert(c < 64 && (c & 3) == 0, "bad quad float register");
duke@0 251 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform");
duke@0 252 return (c & 0x1c) | ((c & 0x20) >> 5);
duke@0 253 }
duke@0 254 ShouldNotReachHere();
duke@0 255 return -1;
duke@0 256 }
duke@0 257
duke@0 258 bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
duke@0 259 const char* name() const;
duke@0 260
duke@0 261 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
duke@0 262 };
duke@0 263
duke@0 264
duke@0 265 // The float registers of the SPARC architecture
duke@0 266
duke@0 267 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
duke@0 268
duke@0 269 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0));
duke@0 270 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1));
duke@0 271 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2));
duke@0 272 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3));
duke@0 273 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4));
duke@0 274 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5));
duke@0 275 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6));
duke@0 276 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7));
duke@0 277 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8));
duke@0 278 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9));
duke@0 279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10));
duke@0 280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11));
duke@0 281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12));
duke@0 282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13));
duke@0 283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14));
duke@0 284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15));
duke@0 285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16));
duke@0 286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17));
duke@0 287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18));
duke@0 288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19));
duke@0 289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20));
duke@0 290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21));
duke@0 291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22));
duke@0 292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23));
duke@0 293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24));
duke@0 294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25));
duke@0 295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26));
duke@0 296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27));
duke@0 297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28));
duke@0 298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29));
duke@0 299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30));
duke@0 300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31));
duke@0 301
duke@0 302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32));
duke@0 303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34));
duke@0 304 CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36));
duke@0 305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38));
duke@0 306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40));
duke@0 307 CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42));
duke@0 308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44));
duke@0 309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46));
duke@0 310 CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48));
duke@0 311 CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50));
duke@0 312 CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52));
duke@0 313 CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54));
duke@0 314 CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56));
duke@0 315 CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58));
duke@0 316 CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60));
duke@0 317 CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62));
duke@0 318
duke@0 319
duke@0 320 #ifndef DONT_USE_REGISTER_DEFINES
duke@0 321 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue))
duke@0 322 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue))
duke@0 323 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue))
duke@0 324 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue))
duke@0 325 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue))
duke@0 326 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue))
duke@0 327 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue))
duke@0 328 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue))
duke@0 329 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue))
duke@0 330 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue))
duke@0 331 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue))
duke@0 332 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue))
duke@0 333 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue))
duke@0 334 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue))
duke@0 335 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue))
duke@0 336 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue))
duke@0 337 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue))
duke@0 338 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue))
duke@0 339 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue))
duke@0 340 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue))
duke@0 341 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue))
duke@0 342 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue))
duke@0 343 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue))
duke@0 344 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue))
duke@0 345 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue))
duke@0 346 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue))
duke@0 347 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue))
duke@0 348 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue))
duke@0 349 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue))
duke@0 350 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue))
duke@0 351 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue))
duke@0 352 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue))
duke@0 353 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue))
duke@0 354 #define F32 ((FloatRegister)( F32_FloatRegisterEnumValue))
duke@0 355 #define F34 ((FloatRegister)( F34_FloatRegisterEnumValue))
duke@0 356 #define F36 ((FloatRegister)( F36_FloatRegisterEnumValue))
duke@0 357 #define F38 ((FloatRegister)( F38_FloatRegisterEnumValue))
duke@0 358 #define F40 ((FloatRegister)( F40_FloatRegisterEnumValue))
duke@0 359 #define F42 ((FloatRegister)( F42_FloatRegisterEnumValue))
duke@0 360 #define F44 ((FloatRegister)( F44_FloatRegisterEnumValue))
duke@0 361 #define F46 ((FloatRegister)( F46_FloatRegisterEnumValue))
duke@0 362 #define F48 ((FloatRegister)( F48_FloatRegisterEnumValue))
duke@0 363 #define F50 ((FloatRegister)( F50_FloatRegisterEnumValue))
duke@0 364 #define F52 ((FloatRegister)( F52_FloatRegisterEnumValue))
duke@0 365 #define F54 ((FloatRegister)( F54_FloatRegisterEnumValue))
duke@0 366 #define F56 ((FloatRegister)( F56_FloatRegisterEnumValue))
duke@0 367 #define F58 ((FloatRegister)( F58_FloatRegisterEnumValue))
duke@0 368 #define F60 ((FloatRegister)( F60_FloatRegisterEnumValue))
duke@0 369 #define F62 ((FloatRegister)( F62_FloatRegisterEnumValue))
duke@0 370 #endif // DONT_USE_REGISTER_DEFINES
duke@0 371
duke@0 372 // Maximum number of incoming arguments that can be passed in i registers.
duke@0 373 const int SPARC_ARGS_IN_REGS_NUM = 6;
duke@0 374
duke@0 375 class ConcreteRegisterImpl : public AbstractRegisterImpl {
duke@0 376 public:
duke@0 377 enum {
duke@0 378 // This number must be large enough to cover REG_COUNT (defined by c2) registers.
duke@0 379 // There is no requirement that any ordering here matches any ordering c2 gives
duke@0 380 // it's optoregs.
duke@0 381 number_of_registers = 2*RegisterImpl::number_of_registers +
duke@0 382 FloatRegisterImpl::number_of_registers +
duke@0 383 1 + // ccr
duke@0 384 4 // fcc
duke@0 385 };
duke@0 386 static const int max_gpr;
duke@0 387 static const int max_fpr;
duke@0 388
duke@0 389 };
duke@0 390
duke@0 391 // Single, Double and Quad fp reg classes. These exist to map the ADLC
duke@0 392 // encoding for a floating point register, to the FloatRegister number
duke@0 393 // desired by the macroassembler. A FloatRegister is a number between
duke@0 394 // 0 and 63 passed around as a pointer. For ADLC, an fp register encoding
duke@0 395 // is the actual bit encoding used by the sparc hardware. When ADLC used
duke@0 396 // the macroassembler to generate an instruction that references, e.g., a
duke@0 397 // double fp reg, it passed the bit encoding to the macroassembler via
duke@0 398 // as_FloatRegister, which, for double regs > 30, returns an illegal
duke@0 399 // register number.
duke@0 400 //
duke@0 401 // Therefore we provide the following classes for use by ADLC. Their
duke@0 402 // sole purpose is to convert from sparc register encodings to FloatRegisters.
duke@0 403 // At some future time, we might replace FloatRegister with these classes,
duke@0 404 // hence the definitions of as_xxxFloatRegister as class methods rather
duke@0 405 // than as external inline routines.
duke@0 406
duke@0 407 class SingleFloatRegisterImpl;
duke@0 408 typedef SingleFloatRegisterImpl *SingleFloatRegister;
duke@0 409
duke@0 410 inline FloatRegister as_SingleFloatRegister(int encoding);
duke@0 411 class SingleFloatRegisterImpl {
duke@0 412 public:
duke@0 413 friend inline FloatRegister as_SingleFloatRegister(int encoding) {
duke@0 414 assert(encoding < 32, "bad single float register encoding");
duke@0 415 return as_FloatRegister(encoding);
duke@0 416 }
duke@0 417 };
duke@0 418
duke@0 419
duke@0 420 class DoubleFloatRegisterImpl;
duke@0 421 typedef DoubleFloatRegisterImpl *DoubleFloatRegister;
duke@0 422
duke@0 423 inline FloatRegister as_DoubleFloatRegister(int encoding);
duke@0 424 class DoubleFloatRegisterImpl {
duke@0 425 public:
duke@0 426 friend inline FloatRegister as_DoubleFloatRegister(int encoding) {
duke@0 427 assert(encoding < 32, "bad double float register encoding");
duke@0 428 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) );
duke@0 429 }
duke@0 430 };
duke@0 431
duke@0 432
duke@0 433 class QuadFloatRegisterImpl;
duke@0 434 typedef QuadFloatRegisterImpl *QuadFloatRegister;
duke@0 435
duke@0 436 class QuadFloatRegisterImpl {
duke@0 437 public:
duke@0 438 friend FloatRegister as_QuadFloatRegister(int encoding) {
duke@0 439 assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding");
duke@0 440 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) );
duke@0 441 }
duke@0 442 };