--- a/agent/make/build-pkglist Thu Sep 04 18:40:08 2008 -0700
+++ b/agent/make/build-pkglist Thu Sep 04 18:40:43 2008 -0700
@@ -8,4 +8,4 @@ SED=$MKS_HOME/sed
SED=$MKS_HOME/sed
SORT=$MKS_HOME/sort
-$CD ../src/share/classes; $FIND sun/jvm/hotspot \( -name SCCS -prune \) -o -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
+$CD ../src/share/classes; $FIND sun/jvm/hotspot com/sun/java/swing -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
--- a/make/linux/makefiles/sa.make Thu Sep 04 18:40:08 2008 -0700
+++ b/make/linux/makefiles/sa.make Thu Sep 04 18:40:43 2008 -0700
@@ -41,8 +41,9 @@ SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/too
SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
# gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
SA_CLASSDIR = $(GENERATED)/saclasses
@@ -58,7 +59,7 @@ all:
$(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
fi
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
$(QUIETLY) echo "Making $@"
$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -72,9 +73,18 @@ all:
$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
mkdir -p $(SA_CLASSDIR); \
fi
- $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+
+ $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+ $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+
$(QUIETLY) $(REMOTE) $(COMPILE.RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(QUIETLY) $(REMOTE) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
$(QUIETLY) $(REMOTE) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
$(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext
--- a/make/sa.files Thu Sep 04 18:40:08 2008 -0700
+++ b/make/sa.files Thu Sep 04 18:40:43 2008 -0700
@@ -33,40 +33,23 @@
AGENT_SRC_DIR = $(AGENT_DIR)/src/share/classes
-AGENT_ALLFILES = \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/DebugServer.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HelloWorld.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotAgent.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotSolarisVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotTypeDataBase.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/LinuxVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/ObjectHistogram.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/RMIHelper.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/StackTrace.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/TestDebugger.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/Win32VtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Immediate.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ImmediateOrRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Operand.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCArgument.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisterType.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86RegisterPart.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/BugSpotAgent.java \
+# Splitted the set of files into two sets because on linux plaform
+# listing or compiling all the files results in 'Argument list too long' error.
+
+AGENT_FILES1 = \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/tree/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/c1/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/code/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/compiler/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/x86/*.java \
@@ -75,7 +58,6 @@ AGENT_ALLFILES = \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/sparc/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/x86/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dummy/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/ia64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/amd64/*.java \
@@ -107,7 +89,10 @@ AGENT_ALLFILES = \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/jdi/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/livejvm/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/memory/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java
+
+
+AGENT_FILES2 = \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/ia64/*.java \
@@ -127,7 +112,17 @@ AGENT_ALLFILES = \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/x86/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/jcore/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/soql/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/types/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/types/basic/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/memo/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/action/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/classbrowser/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/table/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/tree/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/treetable/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/action/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/ui/*.java
--- a/make/solaris/makefiles/reorder_COMPILER1_i486 Thu Sep 04 18:40:08 2008 -0700
+++ b/make/solaris/makefiles/reorder_COMPILER1_i486 Thu Sep 04 18:40:43 2008 -0700
@@ -8,20 +8,20 @@ text: .text%__1cQAgentLibraryList2t6M_v_
text: .text%__1cQAgentLibraryList2t6M_v_: arguments.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable.o;
text: .text%__1cFRInfo2t6M_v_: c1_AllocTable.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_AllocTable_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_AllocTable_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals.o;
text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Canonicalizer.o;
text: .text%__1cFRInfo2t6M_v_: c1_Canonicalizer.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator.o;
text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator_i486.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeStubs_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_CodeStubs_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeStubs_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeStubs_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compilation.o;
text: .text%__1cFRInfo2t6M_v_: c1_Compilation.o;
text: .text%__1cMelapsedTimer2t6M_v_: c1_Compilation.o;
@@ -29,9 +29,9 @@ text: .text%__1cFRInfo2t6M_v_: c1_Compil
text: .text%__1cFRInfo2t6M_v_: c1_Compiler.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap.o;
text: .text%__1cFRInfo2t6M_v_: c1_FrameMap.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_FrameMap_i486.o;
-text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_GraphBuilder.o;
text: .text%__1cFRInfo2t6M_v_: c1_GraphBuilder.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_IR.o;
@@ -43,41 +43,41 @@ text: .text%__1cU__STATIC_CONSTRUCTOR6F_
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items.o;
text: .text%__1cFRInfo2t6M_v_: c1_Items.o;
text: .text%__1cIHintItem2t6MpnJValueType_i_v_: c1_Items.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_Items_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Items_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIR.o;
text: .text%__1cFRInfo2t6M_v_: c1_LIR.o;
text: .text%__1cLLIR_OprFactHillegal6F_pnLLIR_OprDesc__: c1_LIR.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler.o;
text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter.o;
text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIROptimizer.o;
text: .text%__1cFRInfo2t6M_v_: c1_LIROptimizer.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Loops.o;
text: .text%__1cFRInfo2t6M_v_: c1_Loops.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_MacroAssembler_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_MacroAssembler_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_MacroAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_MacroAssembler_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Optimizer.o;
text: .text%__1cFRInfo2t6M_v_: c1_Optimizer.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo.o;
text: .text%__1cFRInfo2t6M_v_: c1_RInfo.o;
text: .text%__1cKc1_RegMask2t6M_v_: c1_RInfo.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_RInfo_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RInfo_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc.o;
text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1.o;
text: .text%__1cFRInfo2t6M_v_: c1_Runtime1.o;
text: .text%__1cIiEntries2t6M_v_;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_Runtime1_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Runtime1_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ScanBlocks.o;
text: .text%__1cFRInfo2t6M_v_: c1_ScanBlocks.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueMap.o;
@@ -105,8 +105,8 @@ text: .text%__1cMelapsedTimer2t6M_v_: fp
text: .text%__1cMelapsedTimer2t6M_v_: fprofiler.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: frame.o;
text: .text%__1cFRInfo2t6M_v_: frame.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: frame_i486.o;
-text: .text%__1cFRInfo2t6M_v_: frame_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: frame_x86.o;
+text: .text%__1cFRInfo2t6M_v_: frame_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: genCollectedHeap.o;
text: .text%__1cTAssertIsPermClosure2t6M_v_: genCollectedHeap.o;
text: .text%__1cRAlwaysTrueClosure2t6M_v_: genCollectedHeap.o;
@@ -117,8 +117,8 @@ text: .text%__1cMelapsedTimer2t6M_v_: ge
text: .text%__1cMelapsedTimer2t6M_v_: generateOopMap.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: interpreter.o;
text: .text%__1cKEntryPoint2t6M_v_;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: interpreter_i486.o;
-text: .text%__1cFRInfo2t6M_v_: interpreter_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: interpreter_x86.o;
+text: .text%__1cFRInfo2t6M_v_: interpreter_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: java.o;
text: .text%__1cFRInfo2t6M_v_: java.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: jvmtiEnvBase.o;
@@ -151,16 +151,16 @@ text: .text%__1cNGrowableArray4CpnNMemor
text: .text%__1cNGrowableArray4CpnNMemoryManager__2t6Mii_v_: memoryService.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: methodOop.o;
text: .text%__1cFRInfo2t6M_v_: methodOop.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: nativeInst_i486.o;
-text: .text%__1cFRInfo2t6M_v_: nativeInst_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: nativeInst_x86.o;
+text: .text%__1cFRInfo2t6M_v_: nativeInst_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: nmethod.o;
text: .text%__1cFRInfo2t6M_v_: nmethod.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: oopMap.o;
text: .text%__1cQDoNothingClosure2t6M_v_: oopMap.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: os_solaris.o;
text: .text%__1cFRInfo2t6M_v_: os_solaris.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: os_solaris_i486.o;
-text: .text%__1cFRInfo2t6M_v_: os_solaris_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: os_solaris_x86.o;
+text: .text%__1cFRInfo2t6M_v_: os_solaris_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: parGCAllocBuffer.o;
text: .text%__1cMarrayOopDescLheader_size6FnJBasicType__i_: parGCAllocBuffer.o;
text: .text%__1cRalign_object_size6Fi_i_: parGCAllocBuffer.o;
@@ -181,8 +181,8 @@ text: .text%__1cJTimeStamp2t6M_v_: runti
text: .text%__1cJTimeStamp2t6M_v_: runtimeService.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: safepoint.o;
text: .text%__1cFRInfo2t6M_v_: safepoint.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: safepoint_solaris_i486.o;
-text: .text%__1cFRInfo2t6M_v_: safepoint_solaris_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: safepoint_solaris_x86.o;
+text: .text%__1cFRInfo2t6M_v_: safepoint_solaris_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: sharedHeap.o;
text: .text%__1cTAssertIsPermClosure2t6M_v_: sharedHeap.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: sharedRuntime.o;
@@ -197,10 +197,10 @@ text: .text%__1cU__STATIC_CONSTRUCTOR6F_
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: vm_version.o;
text: .text%__1cTAbstract_VM_VersionKvm_release6F_pkc_;
text: .text%__1cTAbstract_VM_VersionXinternal_vm_info_string6F_pkc_;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: vtableStubs_i486.o;
-text: .text%__1cFRInfo2t6M_v_: vtableStubs_i486.o;
-text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIROptimizer_i486.o;
-text: .text%__1cFRInfo2t6M_v_: c1_LIROptimizer_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: vtableStubs_x86.o;
+text: .text%__1cFRInfo2t6M_v_: vtableStubs_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIROptimizer_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIROptimizer_x86.o;
text: .text%JNI_CreateJavaVM;
text: .text%__1cCosVatomic_xchg_bootstrap6Fipoi_i_;
text: .text%__1cHThreadsJcreate_vm6FpnOJavaVMInitArgs_pi_i_;
@@ -279,7 +279,7 @@ text: .text%__1cSThreadLocalStorageHpd_i
text: .text%__1cSThreadLocalStorageHpd_init6F_v_;
text: .text%__1cCosbDallocate_thread_local_storage6F_i_;
text: .text%__1cSThreadLocalStoragebCgenerate_code_for_get_thread6F_v_;
-text: .text%__1cRAllocateTLSOffset6F_v_: threadLS_solaris_i486.o;
+text: .text%__1cRAllocateTLSOffset6F_v_: threadLS_solaris_x86.o;
text: .text%__1cPvm_init_globals6F_v_;
text: .text%__1cScheck_ThreadShadow6F_v_;
text: .text%__1cRcheck_basic_types6F_v_;
@@ -463,7 +463,7 @@ text: .text%__1cXresource_allocate_bytes
text: .text%__1cXresource_allocate_bytes6FI_pc_;
text: .text%__1cKCodeBuffer2t6MpCi_v_;
text: .text%__1cRAbstractAssembler2t6MpnKCodeBuffer__v_;
-text: .text%__1cYVM_Version_StubGeneratorTgenerate_getPsrInfo6M_pC_: vm_version_i486.o;
+text: .text%__1cYVM_Version_StubGeneratorTgenerate_getPsrInfo6M_pC_: vm_version_x86.o;
text: .text%__1cMStubCodeMark2t6MpnRStubCodeGenerator_pkc4_v_;
text: .text%__1cRStubCodeGeneratorLstub_prolog6MpnMStubCodeDesc__v_;
text: .text%__1cJAssemblerFpushl6MpnMRegisterImpl__v_;
@@ -497,14 +497,14 @@ text: .text%__1cFForteNregister_stub6Fpk
text: .text%__1cFForteNregister_stub6FpkcpC3_v_;
text: .text%__1cKVM_VersionWget_processor_features6F_v_;
text: .text%__1cCosMsupports_sse6F_i_;
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+text: .text%__1cVcheck_for_sse_support6F_v_: os_solaris_x86.o;
text: .text%jio_snprintf;
text: .text%jio_vsnprintf;
text: .text%__1cPlocal_vsnprintf6FpcIpkcpv_i_;
text: .text%__1cSstubRoutines_init16F_v_;
text: .text%__1cMStubRoutinesLinitialize16F_v_;
text: .text%__1cWStubGenerator_generate6FpnKCodeBuffer_i_v_;
-text: .text%__1cNStubGeneratorbAgenerate_forward_exception6M_pC_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorbAgenerate_forward_exception6M_pC_: stubGenerator_x86.o;
text: .text%__1cOMacroAssemblerMcall_VM_leaf6MpCpnMRegisterImpl__v_;
text: .text%__1cOMacroAssemblerMcall_VM_leaf6MpCi_v_;
text: .text%__1cOMacroAssemblerRcall_VM_leaf_base6MpCi_v_;
@@ -525,7 +525,7 @@ text: .text%__1cJAssemblerEmovl6MnHAddre
text: .text%__1cJAssemblerEmovl6MnHAddress_i_v_;
text: .text%__1cOMacroAssemblerKverify_oop6MpnMRegisterImpl_pkc_v_;
text: .text%__1cJAssemblerDjmp6MpnMRegisterImpl_nJrelocInfoJrelocType__v_;
-text: .text%__1cNStubGeneratorSgenerate_call_stub6MrpC_1_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorSgenerate_call_stub6MrpC_1_: stubGenerator_x86.o;
text: .text%__1cOMacroAssemblerFenter6M_v_;
text: .text%__1cJAssemblerEsubl6MpnMRegisterImpl_i_v_;
text: .text%__1cJAssemblerFtestl6MpnMRegisterImpl_2_v_;
@@ -534,14 +534,14 @@ text: .text%__1cJAssemblerEcmpl6MpnMRegi
text: .text%__1cJAssemblerEcmpl6MpnMRegisterImpl_i_v_;
text: .text%__1cJAssemblerGfstp_s6MnHAddress__v_;
text: .text%__1cJAssemblerGfstp_d6MnHAddress__v_;
-text: .text%__1cNStubGeneratorYgenerate_catch_exception6M_pC_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorYgenerate_catch_exception6M_pC_: stubGenerator_x86.o;
text: .text%__1cJAssemblerDjmp6MpCnJrelocInfoJrelocType__v_;
-text: .text%__1cNStubGeneratorUgenerate_atomic_xchg6M_pC_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorUgenerate_atomic_xchg6M_pC_: stubGenerator_x86.o;
text: .text%__1cJAssemblerExchg6MpnMRegisterImpl_nHAddress__v_;
text: .text%__1cJAssemblerGpushad6M_v_;
text: .text%__1cJAssemblerFpopad6M_v_;
-text: .text%__1cNStubGeneratorYgenerate_get_previous_fp6M_pC_: stubGenerator_i486.o;
-text: .text%__1cNStubGeneratorUgenerate_d2i_wrapper6MpC_1_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorYgenerate_get_previous_fp6M_pC_: stubGenerator_x86.o;
+text: .text%__1cNStubGeneratorUgenerate_d2i_wrapper6MpC_1_: stubGenerator_x86.o;
text: .text%__1cOMacroAssemblerOpush_FPU_state6M_v_;
text: .text%__1cJAssemblerGfnsave6MnHAddress__v_;
text: .text%__1cJAssemblerFfwait6M_v_;
@@ -552,7 +552,7 @@ text: .text%__1cJAssemblerLemit_farith6M
text: .text%__1cJAssemblerLemit_farith6Miii_v_;
text: .text%__1cOMacroAssemblerNpop_FPU_state6M_v_;
text: .text%__1cJAssemblerGfrstor6MnHAddress__v_;
-text: .text%__1cNStubGeneratorUcreate_control_words6M_v_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorUcreate_control_words6M_v_: stubGenerator_x86.o;
text: .text%__1cJTraceTime2T6M_v_;
text: .text%__1cNcarSpace_init6F_v_;
text: .text%__1cICarSpaceEinit6F_v_;
@@ -773,7 +773,7 @@ text: .text%__1cJAssemblerEaddl6MpnMRegi
text: .text%__1cJAssemblerEaddl6MpnMRegisterImpl_2_v_;
text: .text%__1cJAssemblerEcmpl6MpnMRegisterImpl_nHAddress__v_;
text: .text%__1cbCAbstractInterpreterGeneratorXbang_stack_shadow_pages6Mi_v_;
-text: .text%__1cOMacroAssemblerWbang_stack_with_offset6Mi_v_: interp_masm_i486.o;
+text: .text%__1cOMacroAssemblerWbang_stack_with_offset6Mi_v_: interp_masm_x86.o;
text: .text%__1cZInterpreterMacroAssemblerTnotify_method_entry6M_v_;
text: .text%__1cUInterpreterGeneratorZgenerate_counter_overflow6MpC_v_;
text: .text%__1cJAssemblerEnegl6MpnMRegisterImpl__v_;
@@ -785,7 +785,7 @@ text: .text%__1cUInterpreterGeneratorUge
text: .text%__1cUInterpreterGeneratorUgenerate_empty_entry6M_pC_;
text: .text%__1cUInterpreterGeneratorXgenerate_accessor_entry6M_pC_;
text: .text%__1cJAssemblerEshrl6MpnMRegisterImpl_i_v_;
-text: .text%__1cLlog2_intptr6Fi_i_: interpreter_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: interpreter_x86.o;
text: .text%__1cOMacroAssemblerQload_signed_byte6MpnMRegisterImpl_nHAddress__i_;
text: .text%__1cJAssemblerGmovsxb6MpnMRegisterImpl_nHAddress__v_;
text: .text%__1cOMacroAssemblerQload_signed_word6MpnMRegisterImpl_nHAddress__i_;
@@ -982,7 +982,7 @@ text: .text%__1cOMacroAssemblerIfcmp2int
text: .text%__1cOMacroAssemblerIfcmp2int6MpnMRegisterImpl_i_v_;
text: .text%__1cNTemplateTableKdouble_cmp6Fi_v_;
text: .text%__1cNTemplateTableHif_0cmp6Fn0AJCondition__v_;
-text: .text%__1cFj_not6FnNTemplateTableJCondition__nJAssemblerJCondition__: templateTable_i486.o;
+text: .text%__1cFj_not6FnNTemplateTableJCondition__nJAssemblerJCondition__: templateTable_x86.o;
text: .text%__1cNTemplateTableGbranch6Fii_v_;
text: .text%__1cZInterpreterMacroAssemblerUprofile_taken_branch6MpnMRegisterImpl_2_v_;
text: .text%__1cZInterpreterMacroAssemblerNdispatch_only6MnITosState__v_;
@@ -1488,7 +1488,7 @@ text: .text%__1cIRegAllocYinit_register_
text: .text%__1cIRegAllocYinit_register_allocation6F_v_;
text: .text%__1cIFrameMapEinit6F_v_;
text: .text%__1cKc1_RegMaskKinit_masks6Fi_v_;
-text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_FrameMap_i486.o;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_FrameMap_x86.o;
text: .text%__1cNc1_AllocTableLinit_tables6F_v_;
text: .text%__1cIFrameMapOfirst_register6F_pnMRegisterImpl__;
text: .text%__1cIFrameMapLcpu_reg2rnr6FpnMRegisterImpl__i_;
@@ -1502,7 +1502,7 @@ text: .text%__1cKCodeBufferQalloc_reloca
text: .text%__1cKCodeBufferQalloc_relocation6MI_v_;
text: .text%__1cJOopMapSet2t6M_v_;
text: .text%__1cJAssemblerEsubl6MnHAddress_i_v_;
-text: .text%__1cTsave_live_registers6FpnOMacroAssembler_i_pnGOopMap__: c1_Runtime1_i486.o;
+text: .text%__1cTsave_live_registers6FpnOMacroAssembler_i_pnGOopMap__: c1_Runtime1_x86.o;
text: .text%__1cJAssemblerGfldenv6MnHAddress__v_;
text: .text%__1cGOopMap2t6Mii_v_;
text: .text%__1cGOopMapQset_callee_saved6MnHOptoRegEName_ii2_v_;
@@ -1564,10 +1564,10 @@ text: .text%__1cJStubFrame2T6M_v_;
text: .text%__1cJStubFrame2T6M_v_;
text: .text%__1cIRuntime1Ygenerate_exception_throw6FpnNStubAssembler_pCpnMRegisterImpl__pnJOopMapSet__;
text: .text%__1cOMacroAssemblerLtlab_refill6MrnFLabel_22_v_;
-text: .text%__1cLlog2_intptr6Fi_i_: assembler_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: assembler_x86.o;
text: .text%__1cOMacroAssemblerNeden_allocate6MpnMRegisterImpl_2i2rnFLabel__v_;
text: .text%__1cOMacroAssemblerLverify_tlab6M_v_;
-text: .text%__1cLlog2_intptr6Fi_i_: c1_Runtime1_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: c1_Runtime1_x86.o;
text: .text%__1cOMacroAssemblerNtlab_allocate6MpnMRegisterImpl_2i22rnFLabel__v_;
text: .text%__1cRC1_MacroAssemblerRinitialize_object6MpnMRegisterImpl_22i22_v_;
text: .text%__1cRC1_MacroAssemblerRinitialize_header6MpnMRegisterImpl_22_v_;
@@ -1581,7 +1581,7 @@ text: .text%__1cRNativeGeneralJumpQjump_
text: .text%__1cRNativeGeneralJumpQjump_destination6kM_pC_;
text: .text%__1cJAssemblerOlocate_operand6FpCn0AMWhichOperand__1_;
text: .text%__1cIRuntime1Rgenerate_patching6FpnNStubAssembler_pC_pnJOopMapSet__;
-text: .text%__1cWrestore_live_registers6FpnOMacroAssembler__v_: c1_Runtime1_i486.o;
+text: .text%__1cWrestore_live_registers6FpnOMacroAssembler__v_: c1_Runtime1_x86.o;
text: .text%__1cNSafepointBlobGcreate6FpnKCodeBuffer_pnJOopMapSet_i_p0_;
text: .text%__1cNSafepointBlob2n6FII_pv_;
text: .text%__1cNSafepointBlob2t6MpnKCodeBuffer_ipnJOopMapSet_i_v_;
@@ -1778,8 +1778,8 @@ text: .text%__1cZsun_misc_AtomicLongCSIm
text: .text%__1cZsun_misc_AtomicLongCSImplPcompute_offsets6F_v_;
text: .text%__1cSstubRoutines_init26F_v_;
text: .text%__1cMStubRoutinesLinitialize26F_v_;
-text: .text%__1cNStubGeneratorYgenerate_throw_exception6MpkcpCi_3_: stubGenerator_i486.o;
-text: .text%__1cNStubGeneratorTgenerate_verify_oop6M_pC_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorYgenerate_throw_exception6MpkcpCi_3_: stubGenerator_x86.o;
+text: .text%__1cNStubGeneratorTgenerate_verify_oop6M_pC_: stubGenerator_x86.o;
text: .text%__1cJAssemblerEincl6MnHAddress__v_;
text: .text%__1cHThreadsDadd6FpnKJavaThread_i_v_;
text: .text%__1cNThreadServiceKadd_thread6FpnKJavaThread_i_v_;
@@ -3074,11 +3074,11 @@ text: .text%__1cLLIR_EmitterRarithmetic_
text: .text%__1cLLIR_EmitterRarithmetic_op_int6MnJBytecodesECode_pnLLIR_OprDesc_44nFRInfo__v_;
text: .text%__1cLLIR_EmitterNarithmetic_op6MnJBytecodesECode_pnLLIR_OprDesc_44inFRInfo_pnMCodeEmitInfo__v_;
text: .text%__1cLLIR_EmitterYstrength_reduce_multiply6MpnLLIR_OprDesc_i22_i_;
-text: .text%__1cILIR_ListHreg2reg6MnFRInfo_1nJBasicType__v_: c1_LIREmitter_i486.o;
-text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_LIREmitter_i486.o;
-text: .text%__1cLlog2_intptr6Fi_i_: c1_LIREmitter_i486.o;
+text: .text%__1cILIR_ListHreg2reg6MnFRInfo_1nJBasicType__v_: c1_LIREmitter_x86.o;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_LIREmitter_x86.o;
+text: .text%__1cLlog2_intptr6Fi_i_: c1_LIREmitter_x86.o;
text: .text%__1cILIR_ListKshift_left6MpnLLIR_OprDesc_222_v_;
-text: .text%__1cILIR_ListDsub6MpnLLIR_OprDesc_22pnMCodeEmitInfo__v_: c1_LIREmitter_i486.o;
+text: .text%__1cILIR_ListDsub6MpnLLIR_OprDesc_22pnMCodeEmitInfo__v_: c1_LIREmitter_x86.o;
text: .text%__1cIValueGenWcan_inline_as_constant6MpnEItem__i_;
text: .text%__1cIRegAllocPget_register_rc6kMnFRInfo__i_;
text: .text%__1cLGetRefCountGdo_cpu6Mi_v_: c1_RegAlloc.o;
@@ -3098,7 +3098,7 @@ text: .text%__1cLLIR_EmitterMindexed_loa
text: .text%__1cLLIR_EmitterMindexed_load6MnFRInfo_nJBasicType_pnLLIR_OprDesc_4pnMCodeEmitInfo__v_;
text: .text%__1cLLIR_EmitterNarray_address6MpnLLIR_OprDesc_2inJBasicType__pnLLIR_Address__;
text: .text%__1cLLIR_AddressFscale6FnJBasicType__n0AFScale__;
-text: .text%__1cILIR_ListEmove6MpnLLIR_Address_pnLLIR_OprDesc_pnMCodeEmitInfo__v_: c1_LIREmitter_i486.o;
+text: .text%__1cILIR_ListEmove6MpnLLIR_Address_pnLLIR_OprDesc_pnMCodeEmitInfo__v_: c1_LIREmitter_x86.o;
text: .text%__1cIRegAllocNoops_in_spill6kM_pnIintStack__;
text: .text%__1cIRegAllocRoops_in_registers6kM_pnPRInfoCollection__;
text: .text%__1cIValueGenbDsafepoint_poll_needs_register6F_i_;
@@ -3137,9 +3137,9 @@ text: .text%__1cPRegisterManagerElock6Mn
text: .text%__1cPRegisterManagerElock6MnFRInfo__v_;
text: .text%__1cHLIR_Op2Fvisit6MpnQLIR_OpVisitState__v_;
text: .text%__1cMLIR_OpBranchFvisit6MpnQLIR_OpVisitState__v_;
-text: .text%__1cORangeCheckStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_i486.o;
-text: .text%__1cQLIR_OpVisitStateGappend6MnFRInfo__v_: c1_CodeStubs_i486.o;
-text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeStubs_i486.o;
+text: .text%__1cORangeCheckStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cQLIR_OpVisitStateGappend6MnFRInfo__v_: c1_CodeStubs_x86.o;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeStubs_x86.o;
text: .text%__1cNc1_AllocTableFmerge6Mp0_v_;
text: .text%__1cGLIR_OpFvisit6MpnQLIR_OpVisitState__v_;
text: .text%__1cQLIR_LocalCachingXcache_locals_for_blocks6MpnJBlockList_pnPRegisterManager_i_pnMLocalMapping__;
@@ -3201,7 +3201,7 @@ text: .text%__1cRLIR_PeepholeStateYset_d
text: .text%__1cRLIR_PeepholeStateYset_disable_optimization6Mi_v_;
text: .text%__1cLLIR_OpLabelJemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerMemit_opLabel6MpnLLIR_OpLabel__v_;
-text: .text%__1cNLIR_OptimizerFvisit6M_v_: c1_LIROptimizer_i486.o;
+text: .text%__1cNLIR_OptimizerFvisit6M_v_: c1_LIROptimizer_x86.o;
text: .text%__1cHLIR_Op0Jemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerIemit_op06MpnHLIR_Op0__v_;
text: .text%__1cHLIR_Op2Jemit_code6MpnVLIR_AbstractAssembler__v_;
@@ -3225,7 +3225,7 @@ text: .text%__1cNLIR_OptimizerNoptimize_
text: .text%__1cNLIR_OptimizerNoptimize_move6MpnHLIR_Op1_rpnLLIR_OprDesc_5_i_;
text: .text%__1cRLIR_PeepholeStatebFequivalent_register_or_constant6MpnLLIR_OprDesc__2_;
text: .text%__1cRLIR_PeepholeStateOequivalent_opr6MpnLLIR_OprDesc__2_;
-text: .text%__1cNLIR_OptimizerKmaybe_opto6MpnLLIR_OprDesc_2_2_: c1_LIROptimizer_i486.o;
+text: .text%__1cNLIR_OptimizerKmaybe_opto6MpnLLIR_OprDesc_2_2_: c1_LIROptimizer_x86.o;
text: .text%__1cNLIR_OptimizerMis_cache_reg6MpnLLIR_OprDesc__i_;
text: .text%__1cMLocalMappingMis_cache_reg6kMpnLLIR_OprDesc__i_;
text: .text%__1cMLocalMappingMis_cache_reg6kMnFRInfo__i_;
@@ -3294,13 +3294,13 @@ text: .text%__1cIFrameMapYsignature_type
text: .text%__1cIFrameMapYsignature_type_array_for6FpknIciMethod__pnNBasicTypeList__;
text: .text%__1cIFrameMapScalling_convention6FpknIciMethod_pnIintArray__pnRCallingConvention__;
text: .text%__1cIFrameMapScalling_convention6FirknOBasicTypeArray_pnIintArray__pnRCallingConvention__;
-text: .text%__1cIintArray2t6Mki1_v_: c1_FrameMap_i486.o;
+text: .text%__1cIintArray2t6Mki1_v_: c1_FrameMap_x86.o;
text: .text%__1cIFrameMapRname_for_argument6Fi_i_;
text: .text%__1cIFrameMapSfp_offset_for_name6kMiii_i_;
text: .text%__1cIFrameMapPnum_local_names6kM_i_;
text: .text%__1cIFrameMapNlocal_to_slot6kMii_i_;
text: .text%__1cIFrameMapSfp_offset_for_slot6kMi_i_;
-text: .text%__1cQArgumentLocation2t6Mci_v_: c1_FrameMap_i486.o;
+text: .text%__1cQArgumentLocation2t6Mci_v_: c1_FrameMap_x86.o;
text: .text%__1cQArgumentLocationSset_stack_location6Mi_v_;
text: .text%__1cIFrameMapQaddress_for_name6kMiii_nHAddress__;
text: .text%__1cIFrameMapQmake_new_address6kMi_nHAddress__;
@@ -3321,12 +3321,12 @@ text: .text%__1cNLIR_AssemblerLcode_offs
text: .text%__1cNLIR_AssemblerLcode_offset6kM_i_;
text: .text%__1cNLIR_AssemblerbDadd_debug_info_for_null_check6MipnMCodeEmitInfo__v_;
text: .text%__1cNLIR_AssemblerOemit_code_stub6MpnICodeStub__v_;
-text: .text%__1cVImplicitNullCheckStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_i486.o;
+text: .text%__1cVImplicitNullCheckStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerCpc6kM_pC_;
-text: .text%__1cICodeStubLset_code_pc6MpC_v_: c1_CodeStubs_i486.o;
-text: .text%__1cICodeStubMis_call_stub6kM_i_: c1_CodeStubs_i486.o;
+text: .text%__1cICodeStubLset_code_pc6MpC_v_: c1_CodeStubs_x86.o;
+text: .text%__1cICodeStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler.o;
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+text: .text%__1cORangeCheckStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerOsafepoint_poll6MnFRInfo_pnMCodeEmitInfo__v_;
text: .text%__1cNLIR_AssemblerZadd_debug_info_for_branch6MpnMCodeEmitInfo__v_;
text: .text%__1cPpoll_RelocationEtype6M_nJrelocInfoJrelocType__: codeBlob.o;
@@ -3396,7 +3396,7 @@ text: .text%__1cRC1_MacroAssemblerRexcep
text: .text%__1cRC1_MacroAssemblerRexception_handler6Mii_v_;
text: .text%__1cNLIR_AssemblerPemit_call_stubs6M_v_;
text: .text%__1cNLIR_AssemblerbCmaybe_adjust_stack_alignment6MpnIciMethod__v_;
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+text: .text%__1cKreal_index6FpnIFrameMap_i_i_: c1_LIRAssembler_x86.o;
text: .text%__1cLCompilationbEgenerate_exception_range_table6M_v_;
text: .text%__1cOExceptionScopeGequals6kMp0_i_;
text: .text%__1cLCompilationbBadd_exception_range_entries6MiipnOExceptionScope_ip2pi_v_;
@@ -3582,10 +3582,10 @@ text: .text%__1cIValueGenQexceptionPcRIn
text: .text%__1cIValueGenQexceptionPcRInfo6F_nFRInfo__;
text: .text%__1cILIR_ListPthrow_exception6MnFRInfo_1pnMCodeEmitInfo__v_: c1_CodeGenerator.o;
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+text: .text%__1cPNewInstanceStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
text: .text%__1cOLIR_OpJavaCallFvisit6MpnQLIR_OpVisitState__v_;
text: .text%__1cQLIR_OpVisitStateGappend6MnFRInfo__v_: c1_LIR.o;
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+text: .text%__1cOStaticCallStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
text: .text%__1cIFrameMapWcaller_save_cpu_reg_at6Fi_pnLLIR_OprDesc__;
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text: .text%__1cIVoidTypeDtag6kM_nIValueTag__: c1_ValueType.o;
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text: .text%__1cNLIR_AssemblerPpatching_epilog6MpnMPatchingStub_nHLIR_Op1NLIR_PatchCode_pnMRegisterImpl_pnMCodeEmitInfo__v_;
text: .text%__1cMPatchingStubHinstall6MpnOMacroAssembler_nHLIR_Op1NLIR_PatchCode_pnMRegisterImpl_pnMCodeEmitInfo__v_: c1_LIRAssembler.o;
text: .text%__1cNLIR_AssemblerUappend_patching_stub6MpnMPatchingStub__v_;
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+text: .text%__1cPNewInstanceStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerJemit_call6MpnOLIR_OpJavaCall__v_;
text: .text%__1cNLIR_AssemblerKalign_call6MnILIR_Code__v_;
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+text: .text%__1cICodeStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cOStaticCallStubLset_code_pc6MpC_v_: c1_CodeStubs_x86.o;
+text: .text%__1cOStaticCallStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerEcall6MpCnJrelocInfoJrelocType_pnMCodeEmitInfo__v_;
text: .text%__1cbBopt_virtual_call_RelocationEtype6M_nJrelocInfoJrelocType__: relocInfo.o;
text: .text%__1cKRelocationJpack_data6M_i_: relocInfo.o;
@@ -4010,15 +4010,15 @@ text: .text%__1cQNullCheckVisitorNdo_Ins
text: .text%__1cQNullCheckVisitorNdo_InstanceOf6MpnKInstanceOf__v_;
text: .text%__1cQNullCheckVisitorMdo_CheckCast6MpnJCheckCast__v_;
text: .text%__1cIValueGenNdo_InstanceOf6MpnKInstanceOf__v_;
-text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeGenerator_i486.o;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeGenerator_x86.o;
text: .text%__1cLLIR_EmitterNinstanceof_op6MpnLLIR_OprDesc_2pnHciKlass_nFRInfo_5ipnMCodeEmitInfo__v_;
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text: .text%__1cIValueGenMdo_CheckCast6MpnJCheckCast__v_;
text: .text%__1cILIR_ListJcheckcast6MpnLLIR_OprDesc_2pnHciKlass_22ipnMCodeEmitInfo_6pnICodeStub__v_;
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text: .text%__1cPLIR_OpTypeCheckFvisit6MpnQLIR_OpVisitState__v_;
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text: .text%__1cPLIR_OpTypeCheckJemit_code6MpnVLIR_AbstractAssembler__v_;
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text: .text%__1cTSimpleExceptionStubJemit_code6MpnNLIR_Assembler__v_;
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text: .text%__1cJLoadFieldMas_LoadField6M_p0_: c1_Instruction.o;
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text: .text%__1cQNewTypeArrayStub2t6MnFRInfo_11pnMCodeEmitInfo__v_;
text: .text%__1cQciTypeArrayKlassEmake6FnJBasicType__p0_;
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+text: .text%__1cILIR_ListHoop2reg6MpnI_jobject_nFRInfo__v_: c1_LIREmitter_x86.o;
text: .text%__1cILIR_ListOallocate_array6MnFRInfo_11111nJBasicType_1pnICodeStub__v_;
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text: .text%__1cIValueGenMdo_ArrayCopy6MpnJIntrinsic__v_;
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text: .text%__1cLArrayLengthOas_ArrayLength6M_p0_: c1_GraphBuilder.o;
text: .text%__1cQis_constant_zero6FpnLInstruction__i_: c1_CodeGenerator.o;
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+text: .text%__1cILIR_ListJarraycopy6MpnLLIR_OprDesc_22222pnMciArrayKlass_ipnMCodeEmitInfo__v_: c1_CodeGenerator_x86.o;
text: .text%__1cLLIR_EmitterNwrite_barrier6MpnLLIR_OprDesc_2_v_;
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+text: .text%__1cILIR_ListUunsigned_shift_right6MnFRInfo_i1_v_: c1_LIREmitter_x86.o;
text: .text%__1cILIR_ListUunsigned_shift_right6MpnLLIR_OprDesc_222_v_;
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text: .text%__1cPLIR_OpArrayCopyFvisit6MpnQLIR_OpVisitState__v_;
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+text: .text%__1cQNewTypeArrayStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerOemit_arraycopy6MpnPLIR_OpArrayCopy__v_;
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+text: .text%__1cNArrayCopyStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerOpush_parameter6MpnMRegisterImpl_i_v_;
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text: .text%__1cNArrayCopyStubJemit_code6MpnNLIR_Assembler__v_;
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+text: .text%__1cSNewObjectArrayStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
text: .text%__1cOLIR_OpAllocObjJemit_code6MpnVLIR_AbstractAssembler__v_;
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+text: .text%__1cSNewObjectArrayStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
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+text: .text%__1cXArrayStoreExceptionStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cXArrayStoreExceptionStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
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+text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler_x86.o;
text: .text%__1cXArrayStoreExceptionStubJemit_code6MpnNLIR_Assembler__v_;
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+text: .text%__1cIintArrayIindex_of6kMki_i_: c1_FrameMap_x86.o;
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text: .text%__1cIFrameMapLFpuStackSimDpop6Mi_i_;
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+text: .text%__1cNDivByZeroStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNDivByZeroStubJemit_code6MpnNLIR_Assembler__v_;
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text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_GraphBuilder.o;
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text: .text%__1cRComputeEntryStackHdo_byte6M_v_: generateOopMap.o;
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+text: .text%__1cUSlowSignatureHandlerLpass_object6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorIdo_array6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorGdo_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerIpass_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorHdo_bool6M_v_: interpreterRT_x86.o;
text: .text%jni_GetFloatArrayRegion: jni.o;
text: .text%jni_GetCharArrayRegion: jni.o;
text: .text%jni_SetFloatField: jni.o;
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text: .text%__1cLLIR_EmitterMmonitor_exit6MnFRInfo_11i_v_;
text: .text%__1cILIR_ListNunlock_object6MnFRInfo_11pnICodeStub__v_;
text: .text%__1cKLIR_OpLockFvisit6MpnQLIR_OpVisitState__v_;
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-text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_i486.o;
+text: .text%__1cQMonitorEnterStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
text: .text%__1cKLIR_OpLockJemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerJemit_lock6MpnKLIR_OpLock__v_;
text: .text%__1cNLIR_AssemblerPmonitor_address6MinFRInfo__v_;
@@ -4915,7 +4915,7 @@ text: .text%__1cIFrameMapbAfp_offset_for
text: .text%__1cIFrameMapbAfp_offset_for_monitor_lock6kMi_i_;
text: .text%__1cNLIR_AssemblerJemit_lock6MpnKLIR_OpLock__v_;
text: .text%__1cRC1_MacroAssemblerLlock_object6MpnMRegisterImpl_22rnFLabel__v_;
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+text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cIFrameMapWmonitor_object_regname6kMi_nHOptoRegEName__;
text: .text%__1cIFrameMapbCfp_offset_for_monitor_object6kMi_i_;
text: .text%__1cMCodeEmitInfobHlocation_for_monitor_object_index6Mi_nILocation__;
@@ -4925,7 +4925,7 @@ text: .text%__1cMMonitorValue2t6MpnKScop
text: .text%__1cMMonitorValue2t6MpnKScopeValue_nILocation__v_;
text: .text%__1cMMonitorValueIwrite_on6MpnUDebugInfoWriteStream__v_;
text: .text%__1cRC1_MacroAssemblerNunlock_object6MpnMRegisterImpl_22rnFLabel__v_;
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+text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
text: .text%__1cQMonitorEnterStubJemit_code6MpnNLIR_Assembler__v_;
text: .text%__1cNLIR_AssemblerRload_receiver_reg6MpnMRegisterImpl__v_;
text: .text%__1cNLIR_AssemblerLmonitorexit6MnFRInfo_1pnMRegisterImpl_i3_v_;
@@ -5168,7 +5168,7 @@ text: .text%__1cCosHrealloc6FpvI_1_;
text: .text%__1cCosHrealloc6FpvI_1_;
text: .text%Unsafe_GetNativeFloat;
text: .text%__1cIValueGenQdo_currentThread6MpnJIntrinsic__v_;
-text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_i486.o;
+text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_x86.o;
text: .text%__1cNLIR_AssemblerKget_thread6MpnLLIR_OprDesc__v_;
text: .text%__1cIValueGenSload_item_patching6MpnHIRScope_ipnEItem_pnKValueStack_pnOExceptionScope__v_;
text: .text%__1cEItemUget_jobject_constant6kM_pnIciObject__;
@@ -5246,7 +5246,7 @@ text: .text%__1cFframeLnmethods_do6M_v_;
text: .text%__1cFframeLnmethods_do6M_v_;
text: .text%__1cFframeVnmethods_code_blob_do6M_v_;
text: .text%__1cILIR_ListEidiv6MnFRInfo_i11pnMCodeEmitInfo__v_;
-text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_x86.o;
text: .text%__1cONMethodSweeperPprocess_nmethod6FpnHnmethod__v_;
text: .text%__1cHnmethodPis_locked_by_vm6kM_i_: nmethod.o;
text: .text%__1cHnmethodLis_unloaded6kM_i_: nmethod.o;
@@ -5423,13 +5423,13 @@ text: .text%__1cLLIR_EmitterOget_raw_uns
text: .text%__1cLLIR_EmitterOget_raw_unsafe6MnFRInfo_pnLLIR_OprDesc_3inJBasicType__v_;
text: .text%__1cILIR_ListMload_mem_reg6MpnLLIR_Address_nFRInfo_nJBasicType_pnMCodeEmitInfo_nHLIR_Op1NLIR_PatchCode__v_;
text: .text%__1cIValueGenPdo_LookupSwitch6MpnMLookupSwitch__v_;
-text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_i486.o;
+text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_x86.o;
text: .text%__1cLLIR_EmitterVlookupswitch_range_op6MpnLLIR_OprDesc_iipnKBlockBegin__v_;
text: .text%__1cNSharedRuntimeEldiv6Fxx_x_;
text: .text%Unsafe_GetObjectVolatile;
text: .text%signalHandler;
text: .text%JVM_handle_solaris_signal;
-text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_i486.o;
+text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_x86.o;
text: .text%__1cICodeBlobRis_at_poll_return6MpC_i_;
text: .text%__1cUSafepointSynchronizebDhandle_polling_page_exception6FpnKJavaThread__pC_;
text: .text%__1cbCCompiledCodeSafepointHandlerbDhandle_polling_page_exception6M_pC_;
--- a/make/solaris/makefiles/sa.make Thu Sep 04 18:40:08 2008 -0700
+++ b/make/solaris/makefiles/sa.make Thu Sep 04 18:40:43 2008 -0700
@@ -37,8 +37,9 @@ SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/too
SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
# gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
SA_CLASSDIR = $(GENERATED)/saclasses
@@ -52,7 +53,7 @@ all:
$(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
fi
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
$(QUIETLY) echo "Making $@";
$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -66,9 +67,17 @@ all:
$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
mkdir -p $(SA_CLASSDIR); \
fi
- $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+ $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+ $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+
$(QUIETLY) $(COMPILE.RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(QUIETLY) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
$(QUIETLY) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
$(QUIETLY) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.proc.ProcDebuggerLocal
--- a/make/windows/makefiles/sa.make Thu Sep 04 18:40:08 2008 -0700
+++ b/make/windows/makefiles/sa.make Thu Sep 04 18:40:43 2008 -0700
@@ -49,15 +49,22 @@ SA_PROPERTIES = $(SA_CLASSDIR)\sa.proper
default:: $(GENERATED)\sa-jdi.jar
-$(GENERATED)\sa-jdi.jar: $(AGENT_ALLFILES:/=\)
+$(GENERATED)\sa-jdi.jar: $(AGENT_FILES1:/=\) $(AGENT_FILES2:/=\)
@if not exist $(SA_CLASSDIR) mkdir $(SA_CLASSDIR)
@echo ...Building sa-jdi.jar
@echo ...$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) ....
- @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES:/=\)
+ @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1:/=\)
+ @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2:/=\)
$(COMPILE_RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo $(SA_BUILD_VERSION_PROP) > $(SA_PROPERTIES)
$(RUN_JAR) cf $@ -C saclasses .
$(RUN_JAR) uf $@ -C $(AGENT_SRC_DIR:/=\) META-INF\services\com.sun.jdi.connect.Connector
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.windbg.WindbgDebuggerLocal
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.ia64.IA64ThreadContext
--- a/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -956,7 +956,8 @@ void LIRGenerator::do_NewMultiArray(NewM
size->load_item();
store_stack_parameter (size->result(),
in_ByteSize(STACK_BIAS +
- (i + frame::memory_parameter_word_sp_offset) * wordSize));
+ frame::memory_parameter_word_sp_offset * wordSize +
+ i * sizeof(jint)));
}
// This instruction can be deoptimized in the slow path : use
--- a/src/cpu/sparc/vm/relocInfo_sparc.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/sparc/vm/relocInfo_sparc.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -204,3 +204,9 @@ void Relocation::pd_swap_out_breakpoint(
NativeInstruction* ni = nativeInstruction_at(x);
ni->set_long_at(0, u.l);
}
+
+void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
+
+void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
--- a/src/cpu/sparc/vm/sharedRuntime_sparc.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/sparc/vm/sharedRuntime_sparc.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -465,9 +465,7 @@ int SharedRuntime::java_calling_conventi
case T_LONG:
assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
-#ifdef COMPILER2
#ifdef _LP64
- // Can't be tiered (yet)
if (int_reg < int_reg_max) {
Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
regs[i].set2(r->as_VMReg());
@@ -476,11 +474,12 @@ int SharedRuntime::java_calling_conventi
stk_reg_pairs += 2;
}
#else
+#ifdef COMPILER2
// For 32-bit build, can't pass longs in O-regs because they become
// I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
// spare and available. This convention isn't used by the Sparc ABI or
// anywhere else. If we're tiered then we don't use G-regs because c1
- // can't deal with them as a "pair".
+ // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
// G0: zero
// G1: 1st Long arg
// G2: global allocated to TLS
@@ -500,7 +499,6 @@ int SharedRuntime::java_calling_conventi
regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
stk_reg_pairs += 2;
}
-#endif // _LP64
#else // COMPILER2
if (int_reg_pairs + 1 < int_reg_max) {
if (is_outgoing) {
@@ -514,6 +512,7 @@ int SharedRuntime::java_calling_conventi
stk_reg_pairs += 2;
}
#endif // COMPILER2
+#endif // _LP64
break;
case T_FLOAT:
@@ -699,17 +698,16 @@ Register AdapterGenerator::next_arg_slot
// Stores long into offset pointed to by base
void AdapterGenerator::store_c2i_long(Register r, Register base,
const int st_off, bool is_stack) {
-#ifdef COMPILER2
#ifdef _LP64
// In V9, longs are given 2 64-bit slots in the interpreter, but the
// data is passed in only 1 slot.
__ stx(r, base, next_arg_slot(st_off));
#else
+#ifdef COMPILER2
// Misaligned store of 64-bit data
__ stw(r, base, arg_slot(st_off)); // lo bits
__ srlx(r, 32, r);
__ stw(r, base, next_arg_slot(st_off)); // hi bits
-#endif // _LP64
#else
if (is_stack) {
// Misaligned store of 64-bit data
@@ -721,6 +719,7 @@ void AdapterGenerator::store_c2i_long(Re
__ stw(r , base, next_arg_slot(st_off)); // hi bits
}
#endif // COMPILER2
+#endif // _LP64
tag_c2i_arg(frame::TagCategory2, base, st_off, r);
}
@@ -1637,7 +1636,7 @@ static void long_move(MacroAssembler* ma
}
} else if (dst.is_single_phys_reg()) {
if (src.is_adjacent_aligned_on_stack(2)) {
- __ ld_long(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
+ __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
} else {
// dst is a single reg.
// Remember lo is low address not msb for stack slots
@@ -1810,7 +1809,6 @@ nmethod *SharedRuntime::generate_native_
BasicType *in_sig_bt,
VMRegPair *in_regs,
BasicType ret_type) {
-
// Native nmethod wrappers never take possesion of the oop arguments.
// So the caller will gc the arguments. The only thing we need an
--- a/src/cpu/x86/vm/c1_CodeStubs_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_CodeStubs_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -43,11 +43,12 @@ void ConversionStub::emit_code(LIR_Assem
__ comisd(input()->as_xmm_double_reg(),
ExternalAddress((address)&double_zero));
} else {
- __ pushl(rax);
+ LP64_ONLY(ShouldNotReachHere());
+ __ push(rax);
__ ftst();
__ fnstsw_ax();
__ sahf();
- __ popl(rax);
+ __ pop(rax);
}
Label NaN, do_return;
@@ -61,7 +62,7 @@ void ConversionStub::emit_code(LIR_Assem
// input is NaN -> return 0
__ bind(NaN);
- __ xorl(result()->as_register(), result()->as_register());
+ __ xorptr(result()->as_register(), result()->as_register());
__ bind(do_return);
__ jmp(_continuation);
@@ -139,7 +140,7 @@ void NewInstanceStub::emit_code(LIR_Asse
void NewInstanceStub::emit_code(LIR_Assembler* ce) {
assert(__ rsp_offset() == 0, "frame size should be fixed");
__ bind(_entry);
- __ movl(rdx, _klass_reg->as_register());
+ __ movptr(rdx, _klass_reg->as_register());
__ call(RuntimeAddress(Runtime1::entry_for(_stub_id)));
ce->add_call_info_here(_info);
ce->verify_oop_map(_info);
@@ -306,10 +307,10 @@ void PatchingStub::emit_code(LIR_Assembl
assert(_obj != noreg, "must be a valid register");
Register tmp = rax;
if (_obj == tmp) tmp = rbx;
- __ pushl(tmp);
+ __ push(tmp);
__ get_thread(tmp);
- __ cmpl(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
- __ popl(tmp);
+ __ cmpptr(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
+ __ pop(tmp);
__ jcc(Assembler::notEqual, call_patch);
// access_field patches may execute the patched code before it's
@@ -434,7 +435,7 @@ void ArrayCopyStub::emit_code(LIR_Assemb
VMReg r_1 = args[i].first();
if (r_1->is_stack()) {
int st_off = r_1->reg2stack() * wordSize;
- __ movl (Address(rsp, st_off), r[i]);
+ __ movptr (Address(rsp, st_off), r[i]);
} else {
assert(r[i] == args[i].first()->as_Register(), "Wrong register for arg ");
}
@@ -449,7 +450,7 @@ void ArrayCopyStub::emit_code(LIR_Assemb
ce->add_call_info_here(info());
#ifndef PRODUCT
- __ increment(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
+ __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
#endif
__ jmp(_continuation);
--- a/src/cpu/x86/vm/c1_Defs_x86.hpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_Defs_x86.hpp Thu Sep 04 18:40:43 2008 -0700
@@ -36,27 +36,34 @@ enum {
// registers
enum {
- pd_nof_cpu_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_fpu_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_xmm_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_caller_save_cpu_regs_frame_map = 6, // number of registers killed by calls
- pd_nof_caller_save_fpu_regs_frame_map = 8, // number of registers killed by calls
- pd_nof_caller_save_xmm_regs_frame_map = 8, // number of registers killed by calls
+ pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
+ pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
+ pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission
- pd_nof_cpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
+#ifdef _LP64
+ #define UNALLOCATED 4 // rsp, rbp, r15, r10
+#else
+ #define UNALLOCATED 2 // rsp, rbp
+#endif // LP64
+
+ pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
+ pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
+ pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls
+
+ pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator
pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
- pd_nof_cpu_regs_linearscan = 8, // number of registers visible to linear scan
- pd_nof_fpu_regs_linearscan = 8, // number of registers visible to linear scan
- pd_nof_xmm_regs_linearscan = 8, // number of registers visible to linear scan
+ pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
+ pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
+ pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
pd_first_cpu_reg = 0,
- pd_last_cpu_reg = 5,
+ pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
pd_first_byte_reg = 2,
pd_last_byte_reg = 5,
pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
pd_last_fpu_reg = pd_first_fpu_reg + 7,
pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
- pd_last_xmm_reg = pd_first_xmm_reg + 7
+ pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
};
--- a/src/cpu/x86/vm/c1_FrameMap_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_FrameMap_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -39,10 +39,15 @@ LIR_Opr FrameMap::map_to_opr(BasicType t
opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
} else if (r_1->is_Register()) {
Register reg = r_1->as_Register();
- if (r_2->is_Register()) {
+ if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
Register reg2 = r_2->as_Register();
+#ifdef _LP64
+ assert(reg2 == reg, "must be same register");
+ opr = as_long_opr(reg);
+#else
opr = as_long_opr(reg2, reg);
- } else if (type == T_OBJECT) {
+#endif // _LP64
+ } else if (type == T_OBJECT || type == T_ARRAY) {
opr = as_oop_opr(reg);
} else {
opr = as_opr(reg);
@@ -88,18 +93,39 @@ LIR_Opr FrameMap::rdx_oop_opr;
LIR_Opr FrameMap::rdx_oop_opr;
LIR_Opr FrameMap::rcx_oop_opr;
-LIR_Opr FrameMap::rax_rdx_long_opr;
-LIR_Opr FrameMap::rbx_rcx_long_opr;
+LIR_Opr FrameMap::long0_opr;
+LIR_Opr FrameMap::long1_opr;
LIR_Opr FrameMap::fpu0_float_opr;
LIR_Opr FrameMap::fpu0_double_opr;
LIR_Opr FrameMap::xmm0_float_opr;
LIR_Opr FrameMap::xmm0_double_opr;
+#ifdef _LP64
+
+LIR_Opr FrameMap::r8_opr;
+LIR_Opr FrameMap::r9_opr;
+LIR_Opr FrameMap::r10_opr;
+LIR_Opr FrameMap::r11_opr;
+LIR_Opr FrameMap::r12_opr;
+LIR_Opr FrameMap::r13_opr;
+LIR_Opr FrameMap::r14_opr;
+LIR_Opr FrameMap::r15_opr;
+
+// r10 and r15 can never contain oops since they aren't available to
+// the allocator
+LIR_Opr FrameMap::r8_oop_opr;
+LIR_Opr FrameMap::r9_oop_opr;
+LIR_Opr FrameMap::r11_oop_opr;
+LIR_Opr FrameMap::r12_oop_opr;
+LIR_Opr FrameMap::r13_oop_opr;
+LIR_Opr FrameMap::r14_oop_opr;
+#endif // _LP64
+
LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
-XMMRegister FrameMap::_xmm_regs [8] = { 0, };
+XMMRegister FrameMap::_xmm_regs [] = { 0, };
XMMRegister FrameMap::nr2xmmreg(int rnr) {
assert(_init_done, "tables not initialized");
@@ -113,18 +139,39 @@ void FrameMap::init() {
void FrameMap::init() {
if (_init_done) return;
- assert(nof_cpu_regs == 8, "wrong number of CPU registers");
- map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); rsi_oop_opr = LIR_OprFact::single_cpu_oop(0);
- map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); rdi_oop_opr = LIR_OprFact::single_cpu_oop(1);
- map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); rbx_oop_opr = LIR_OprFact::single_cpu_oop(2);
- map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); rax_oop_opr = LIR_OprFact::single_cpu_oop(3);
- map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); rdx_oop_opr = LIR_OprFact::single_cpu_oop(4);
- map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); rcx_oop_opr = LIR_OprFact::single_cpu_oop(5);
- map_register(6, rsp); rsp_opr = LIR_OprFact::single_cpu(6);
- map_register(7, rbp); rbp_opr = LIR_OprFact::single_cpu(7);
-
- rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
- rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+ assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
+ map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
+ map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
+ map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
+ map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
+ map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
+ map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
+
+#ifndef _LP64
+ // The unallocatable registers are at the end
+ map_register(6, rsp);
+ map_register(7, rbp);
+#else
+ map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
+ map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
+ map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
+ map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
+ map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
+ map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
+ // The unallocatable registers are at the end
+ map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
+ map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
+ map_register(14, rsp);
+ map_register(15, rbp);
+#endif // _LP64
+
+#ifdef _LP64
+ long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
+ long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
+#else
+ long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
+ long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+#endif // _LP64
fpu0_float_opr = LIR_OprFact::single_fpu(0);
fpu0_double_opr = LIR_OprFact::double_fpu(0);
xmm0_float_opr = LIR_OprFact::single_xmm(0);
@@ -136,6 +183,15 @@ void FrameMap::init() {
_caller_save_cpu_regs[3] = rax_opr;
_caller_save_cpu_regs[4] = rdx_opr;
_caller_save_cpu_regs[5] = rcx_opr;
+
+#ifdef _LP64
+ _caller_save_cpu_regs[6] = r8_opr;
+ _caller_save_cpu_regs[7] = r9_opr;
+ _caller_save_cpu_regs[8] = r11_opr;
+ _caller_save_cpu_regs[9] = r12_opr;
+ _caller_save_cpu_regs[10] = r13_opr;
+ _caller_save_cpu_regs[11] = r14_opr;
+#endif // _LP64
_xmm_regs[0] = xmm0;
@@ -147,18 +203,51 @@ void FrameMap::init() {
_xmm_regs[6] = xmm6;
_xmm_regs[7] = xmm7;
+#ifdef _LP64
+ _xmm_regs[8] = xmm8;
+ _xmm_regs[9] = xmm9;
+ _xmm_regs[10] = xmm10;
+ _xmm_regs[11] = xmm11;
+ _xmm_regs[12] = xmm12;
+ _xmm_regs[13] = xmm13;
+ _xmm_regs[14] = xmm14;
+ _xmm_regs[15] = xmm15;
+#endif // _LP64
+
for (int i = 0; i < 8; i++) {
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
+ }
+
+ for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
_caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
}
_init_done = true;
+
+ rsi_oop_opr = as_oop_opr(rsi);
+ rdi_oop_opr = as_oop_opr(rdi);
+ rbx_oop_opr = as_oop_opr(rbx);
+ rax_oop_opr = as_oop_opr(rax);
+ rdx_oop_opr = as_oop_opr(rdx);
+ rcx_oop_opr = as_oop_opr(rcx);
+
+ rsp_opr = as_pointer_opr(rsp);
+ rbp_opr = as_pointer_opr(rbp);
+
+#ifdef _LP64
+ r8_oop_opr = as_oop_opr(r8);
+ r9_oop_opr = as_oop_opr(r9);
+ r11_oop_opr = as_oop_opr(r11);
+ r12_oop_opr = as_oop_opr(r12);
+ r13_oop_opr = as_oop_opr(r13);
+ r14_oop_opr = as_oop_opr(r14);
+#endif // _LP64
VMRegPair regs;
BasicType sig_bt = T_OBJECT;
SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
receiver_opr = as_oop_opr(regs.first()->as_Register());
- assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx");
+
}
--- a/src/cpu/x86/vm/c1_FrameMap_x86.hpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_FrameMap_x86.hpp Thu Sep 04 18:40:43 2008 -0700
@@ -38,8 +38,13 @@
nof_xmm_regs = pd_nof_xmm_regs_frame_map,
nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
first_available_sp_in_frame = 0,
+#ifndef _LP64
frame_pad_in_bytes = 8,
nof_reg_args = 2
+#else
+ frame_pad_in_bytes = 16,
+ nof_reg_args = 6
+#endif // _LP64
};
private:
@@ -65,17 +70,49 @@
static LIR_Opr rax_oop_opr;
static LIR_Opr rdx_oop_opr;
static LIR_Opr rcx_oop_opr;
+#ifdef _LP64
- static LIR_Opr rax_rdx_long_opr;
- static LIR_Opr rbx_rcx_long_opr;
+ static LIR_Opr r8_opr;
+ static LIR_Opr r9_opr;
+ static LIR_Opr r10_opr;
+ static LIR_Opr r11_opr;
+ static LIR_Opr r12_opr;
+ static LIR_Opr r13_opr;
+ static LIR_Opr r14_opr;
+ static LIR_Opr r15_opr;
+
+ static LIR_Opr r8_oop_opr;
+ static LIR_Opr r9_oop_opr;
+
+ static LIR_Opr r11_oop_opr;
+ static LIR_Opr r12_oop_opr;
+ static LIR_Opr r13_oop_opr;
+ static LIR_Opr r14_oop_opr;
+
+#endif // _LP64
+
+ static LIR_Opr long0_opr;
+ static LIR_Opr long1_opr;
static LIR_Opr fpu0_float_opr;
static LIR_Opr fpu0_double_opr;
static LIR_Opr xmm0_float_opr;
static LIR_Opr xmm0_double_opr;
+#ifdef _LP64
+ static LIR_Opr as_long_opr(Register r) {
+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+ }
+ static LIR_Opr as_pointer_opr(Register r) {
+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+ }
+#else
static LIR_Opr as_long_opr(Register r, Register r2) {
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
}
+ static LIR_Opr as_pointer_opr(Register r) {
+ return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
+ }
+#endif // _LP64
// VMReg name for spilled physical FPU stack slot n
static VMReg fpu_regname (int n);
--- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -113,7 +113,7 @@ bool LIR_Assembler::is_small_constant(LI
LIR_Opr LIR_Assembler::receiverOpr() {
- return FrameMap::rcx_oop_opr;
+ return FrameMap::receiver_opr;
}
LIR_Opr LIR_Assembler::incomingReceiverOpr() {
@@ -121,7 +121,7 @@ LIR_Opr LIR_Assembler::incomingReceiverO
}
LIR_Opr LIR_Assembler::osrBufferPointer() {
- return FrameMap::rcx_opr;
+ return FrameMap::as_pointer_opr(receiverOpr()->as_register());
}
//--------------fpu register translations-----------------------
@@ -181,7 +181,7 @@ void LIR_Assembler::push(LIR_Opr opr) {
if (opr->is_single_cpu()) {
__ push_reg(opr->as_register());
} else if (opr->is_double_cpu()) {
- __ push_reg(opr->as_register_hi());
+ NOT_LP64(__ push_reg(opr->as_register_hi()));
__ push_reg(opr->as_register_lo());
} else if (opr->is_stack()) {
__ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
@@ -202,31 +202,45 @@ void LIR_Assembler::push(LIR_Opr opr) {
void LIR_Assembler::pop(LIR_Opr opr) {
if (opr->is_single_cpu()) {
- __ pop(opr->as_register());
+ __ pop_reg(opr->as_register());
} else {
ShouldNotReachHere();
}
}
+bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
+ return addr->base()->is_illegal() && addr->index()->is_illegal();
+}
+
//-------------------------------------------
+
Address LIR_Assembler::as_Address(LIR_Address* addr) {
+ return as_Address(addr, rscratch1);
+}
+
+Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
if (addr->base()->is_illegal()) {
assert(addr->index()->is_illegal(), "must be illegal too");
- //return Address(addr->disp(), relocInfo::none);
- // hack for now since this should really return an AddressLiteral
- // which will have to await 64bit c1 changes.
- return Address(noreg, addr->disp());
- }
-
- Register base = addr->base()->as_register();
+ AddressLiteral laddr((address)addr->disp(), relocInfo::none);
+ if (! __ reachable(laddr)) {
+ __ movptr(tmp, laddr.addr());
+ Address res(tmp, 0);
+ return res;
+ } else {
+ return __ as_Address(laddr);
+ }
+ }
+
+ Register base = addr->base()->as_pointer_register();
if (addr->index()->is_illegal()) {
return Address( base, addr->disp());
- } else if (addr->index()->is_single_cpu()) {
- Register index = addr->index()->as_register();
+ } else if (addr->index()->is_cpu_register()) {
+ Register index = addr->index()->as_pointer_register();
return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
} else if (addr->index()->is_constant()) {
- int addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+ intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+ assert(Assembler::is_simm32(addr_offset), "must be");
return Address(base, addr_offset);
} else {
@@ -284,7 +298,7 @@ void LIR_Assembler::osr_entry() {
// All other registers are dead at this point and the locals will be
// copied into place by code emitted in the IR.
- Register OSR_buf = osrBufferPointer()->as_register();
+ Register OSR_buf = osrBufferPointer()->as_pointer_register();
{ assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
int monitor_offset = BytesPerWord * method()->max_locals() +
(BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
@@ -294,16 +308,16 @@ void LIR_Assembler::osr_entry() {
// verify the interpreter's monitor has a non-null object
{
Label L;
- __ cmpl(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);
+ __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);
__ jcc(Assembler::notZero, L);
__ stop("locked object is NULL");
__ bind(L);
}
#endif
- __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
- __ movl(frame_map()->address_for_monitor_lock(i), rbx);
- __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
- __ movl(frame_map()->address_for_monitor_object(i), rbx);
+ __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
+ __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
+ __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
+ __ movptr(frame_map()->address_for_monitor_object(i), rbx);
}
}
}
@@ -313,10 +327,11 @@ int LIR_Assembler::check_icache() {
int LIR_Assembler::check_icache() {
Register receiver = FrameMap::receiver_opr->as_register();
Register ic_klass = IC_Klass;
+ const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
if (!VerifyOops) {
// insert some nops so that the verified entry point is aligned on CodeEntryAlignment
- while ((__ offset() + 9) % CodeEntryAlignment != 0) {
+ while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
__ nop();
}
}
@@ -347,7 +362,7 @@ void LIR_Assembler::monitorexit(LIR_Opr
// and cannot block => no GC can happen
// The slow case (MonitorAccessStub) uses the first two stack slots
// ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
- __ movl (Address(rsp, 2*wordSize), exception);
+ __ movptr (Address(rsp, 2*wordSize), exception);
}
Register obj_reg = obj_opr->as_register();
@@ -360,7 +375,7 @@ void LIR_Assembler::monitorexit(LIR_Opr
lock_reg = new_hdr;
// compute pointer to BasicLock
Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
- __ leal(lock_reg, lock_addr);
+ __ lea(lock_reg, lock_addr);
// unlock object
MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
// _slow_case_stubs->append(slow_case);
@@ -385,14 +400,18 @@ void LIR_Assembler::monitorexit(LIR_Opr
if (exception->is_valid()) {
// restore exception
- __ movl (exception, Address(rsp, 2 * wordSize));
+ __ movptr (exception, Address(rsp, 2 * wordSize));
}
}
// This specifies the rsp decrement needed to build the frame
int LIR_Assembler::initial_frame_size_in_bytes() {
// if rounding, must let FrameMap know!
- return (frame_map()->framesize() - 2) * BytesPerWord; // subtract two words to account for return address and link
+
+ // The frame_map records size in slots (32bit word)
+
+ // subtract two words to account for return address and link
+ return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
}
@@ -495,43 +514,43 @@ void LIR_Assembler::emit_deopt_handler()
// This is the fast version of java.lang.String.compare; it has not
// OSR-entry and therefore, we generate a slow version for OSR's
void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
- __ movl (rbx, rcx); // receiver is in rcx
- __ movl (rax, arg1->as_register());
+ __ movptr (rbx, rcx); // receiver is in rcx
+ __ movptr (rax, arg1->as_register());
// Get addresses of first characters from both Strings
- __ movl (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
- __ movl (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
- __ leal (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+ __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
+ __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
+ __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
// rbx, may be NULL
add_debug_info_for_null_check_here(info);
- __ movl (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
- __ movl (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
- __ leal (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+ __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
+ __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
+ __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
// compute minimum length (in rax) and difference of lengths (on top of stack)
if (VM_Version::supports_cmov()) {
- __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
- __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
- __ movl (rcx, rbx);
- __ subl (rbx, rax); // subtract lengths
- __ pushl(rbx); // result
- __ cmovl(Assembler::lessEqual, rax, rcx);
+ __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+ __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
+ __ mov (rcx, rbx);
+ __ subptr (rbx, rax); // subtract lengths
+ __ push (rbx); // result
+ __ cmov (Assembler::lessEqual, rax, rcx);
} else {
Label L;
- __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
- __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
- __ movl (rax, rbx);
- __ subl (rbx, rcx);
- __ pushl(rbx);
- __ jcc (Assembler::lessEqual, L);
- __ movl (rax, rcx);
+ __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+ __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
+ __ mov (rax, rbx);
+ __ subptr (rbx, rcx);
+ __ push (rbx);
+ __ jcc (Assembler::lessEqual, L);
+ __ mov (rax, rcx);
__ bind (L);
}
// is minimum length 0?
Label noLoop, haveResult;
- __ testl (rax, rax);
+ __ testptr (rax, rax);
__ jcc (Assembler::zero, noLoop);
// compare first characters
@@ -546,9 +565,9 @@ void LIR_Assembler::emit_string_compare(
// set rsi.edi to the end of the arrays (arrays have same length)
// negate the index
- __ leal(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
- __ leal(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
- __ negl(rax);
+ __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+ __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+ __ negptr(rax);
// compare the strings in a loop
@@ -565,12 +584,12 @@ void LIR_Assembler::emit_string_compare(
// strings are equal up to min length
__ bind(noLoop);
- __ popl(rax);
+ __ pop(rax);
return_op(LIR_OprFact::illegalOpr);
__ bind(haveResult);
// leave instruction is going to discard the TOS value
- __ movl (rax, rcx); // result of call is in rax,
+ __ mov (rax, rcx); // result of call is in rax,
}
@@ -589,6 +608,11 @@ void LIR_Assembler::return_op(LIR_Opr re
// the poll sets the condition code, but no data registers
AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
relocInfo::poll_return_type);
+
+ // NOTE: the requires that the polling page be reachable else the reloc
+ // goes to the movq that loads the address and not the faulting instruction
+ // which breaks the signal handler code
+
__ test32(rax, polling_page);
__ ret(0);
@@ -606,17 +630,22 @@ int LIR_Assembler::safepoint_poll(LIR_Op
}
int offset = __ offset();
+
+ // NOTE: the requires that the polling page be reachable else the reloc
+ // goes to the movq that loads the address and not the faulting instruction
+ // which breaks the signal handler code
+
__ test32(rax, polling_page);
return offset;
}
void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
- if (from_reg != to_reg) __ movl(to_reg, from_reg);
+ if (from_reg != to_reg) __ mov(to_reg, from_reg);
}
void LIR_Assembler::swap_reg(Register a, Register b) {
- __ xchgl(a, b);
+ __ xchgptr(a, b);
}
@@ -634,8 +663,12 @@ void LIR_Assembler::const2reg(LIR_Opr sr
case T_LONG: {
assert(patch_code == lir_patch_none, "no patching handled here");
- __ movl(dest->as_register_lo(), c->as_jint_lo());
- __ movl(dest->as_register_hi(), c->as_jint_hi());
+#ifdef _LP64
+ __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
+#else
+ __ movptr(dest->as_register_lo(), c->as_jint_lo());
+ __ movptr(dest->as_register_hi(), c->as_jint_hi());
+#endif // _LP64
break;
}
@@ -714,10 +747,15 @@ void LIR_Assembler::const2stack(LIR_Opr
case T_LONG: // fall through
case T_DOUBLE:
- __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
- lo_word_offset_in_bytes), c->as_jint_lo_bits());
- __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
- hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#ifdef _LP64
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
+#else
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ lo_word_offset_in_bytes), c->as_jint_lo_bits());
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#endif // _LP64
break;
default:
@@ -731,7 +769,7 @@ void LIR_Assembler::const2mem(LIR_Opr sr
LIR_Const* c = src->as_constant_ptr();
LIR_Address* addr = dest->as_address_ptr();
- if (info != NULL) add_debug_info_for_null_check_here(info);
+ int null_check_here = code_offset();
switch (type) {
case T_INT: // fall through
case T_FLOAT:
@@ -741,16 +779,33 @@ void LIR_Assembler::const2mem(LIR_Opr sr
case T_OBJECT: // fall through
case T_ARRAY:
if (c->as_jobject() == NULL) {
- __ movl(as_Address(addr), NULL_WORD);
+ __ movptr(as_Address(addr), (int32_t)NULL_WORD);
} else {
- __ movoop(as_Address(addr), c->as_jobject());
+ if (is_literal_address(addr)) {
+ ShouldNotReachHere();
+ __ movoop(as_Address(addr, noreg), c->as_jobject());
+ } else {
+ __ movoop(as_Address(addr), c->as_jobject());
+ }
}
break;
case T_LONG: // fall through
case T_DOUBLE:
- __ movl(as_Address_hi(addr), c->as_jint_hi_bits());
- __ movl(as_Address_lo(addr), c->as_jint_lo_bits());
+#ifdef _LP64
+ if (is_literal_address(addr)) {
+ ShouldNotReachHere();
+ __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
+ } else {
+ __ movptr(r10, (intptr_t)c->as_jlong_bits());
+ null_check_here = code_offset();
+ __ movptr(as_Address_lo(addr), r10);
+ }
+#else
+ // Always reachable in 32bit so this doesn't produce useless move literal
+ __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
+ __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
+#endif // _LP64
break;
case T_BOOLEAN: // fall through
@@ -766,6 +821,10 @@ void LIR_Assembler::const2mem(LIR_Opr sr
default:
ShouldNotReachHere();
};
+
+ if (info != NULL) {
+ add_debug_info_for_null_check(null_check_here, info);
+ }
}
@@ -775,6 +834,13 @@ void LIR_Assembler::reg2reg(LIR_Opr src,
// move between cpu-registers
if (dest->is_single_cpu()) {
+#ifdef _LP64
+ if (src->type() == T_LONG) {
+ // Can do LONG -> OBJECT
+ move_regs(src->as_register_lo(), dest->as_register());
+ return;
+ }
+#endif
assert(src->is_single_cpu(), "must match");
if (src->type() == T_OBJECT) {
__ verify_oop(src->as_register());
@@ -782,12 +848,26 @@ void LIR_Assembler::reg2reg(LIR_Opr src,
move_regs(src->as_register(), dest->as_register());
} else if (dest->is_double_cpu()) {
+#ifdef _LP64
+ if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
+ // Surprising to me but we can see move of a long to t_object
+ __ verify_oop(src->as_register());
+ move_regs(src->as_register(), dest->as_register_lo());
+ return;
+ }
+#endif
assert(src->is_double_cpu(), "must match");
Register f_lo = src->as_register_lo();
Register f_hi = src->as_register_hi();
Register t_lo = dest->as_register_lo();
Register t_hi = dest->as_register_hi();
+#ifdef _LP64
+ assert(f_hi == f_lo, "must be same");
+ assert(t_hi == t_lo, "must be same");
+ move_regs(f_lo, t_lo);
+#else
assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
+
if (f_lo == t_hi && f_hi == t_lo) {
swap_reg(f_lo, f_hi);
@@ -800,6 +880,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src,
move_regs(f_lo, t_lo);
move_regs(f_hi, t_hi);
}
+#endif // LP64
// special moves from fpu-register to xmm-register
// necessary for method results
@@ -841,14 +922,16 @@ void LIR_Assembler::reg2stack(LIR_Opr sr
Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
if (type == T_OBJECT || type == T_ARRAY) {
__ verify_oop(src->as_register());
- }
- __ movl (dst, src->as_register());
+ __ movptr (dst, src->as_register());
+ } else {
+ __ movl (dst, src->as_register());
+ }
} else if (src->is_double_cpu()) {
Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
- __ movl (dstLO, src->as_register_lo());
- __ movl (dstHI, src->as_register_hi());
+ __ movptr (dstLO, src->as_register_lo());
+ NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
} else if (src->is_single_xmm()) {
Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
@@ -885,6 +968,8 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
}
if (patch_code != lir_patch_none) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ Address toa = as_Address(to_addr);
+ assert(toa.disp() != 0, "must have");
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
@@ -918,6 +1003,10 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
case T_ADDRESS: // fall through
case T_ARRAY: // fall through
case T_OBJECT: // fall through
+#ifdef _LP64
+ __ movptr(as_Address(to_addr), src->as_register());
+ break;
+#endif // _LP64
case T_INT:
__ movl(as_Address(to_addr), src->as_register());
break;
@@ -925,6 +1014,9 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
case T_LONG: {
Register from_lo = src->as_register_lo();
Register from_hi = src->as_register_hi();
+#ifdef _LP64
+ __ movptr(as_Address_lo(to_addr), from_lo);
+#else
Register base = to_addr->base()->as_register();
Register index = noreg;
if (to_addr->index()->is_register()) {
@@ -950,6 +1042,7 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
}
__ movl(as_Address_hi(to_addr), from_hi);
}
+#endif // _LP64
break;
}
@@ -982,16 +1075,18 @@ void LIR_Assembler::stack2reg(LIR_Opr sr
assert(dest->is_register(), "should not call otherwise");
if (dest->is_single_cpu()) {
- __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
if (type == T_ARRAY || type == T_OBJECT) {
+ __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
__ verify_oop(dest->as_register());
+ } else {
+ __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
}
} else if (dest->is_double_cpu()) {
Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
- __ movl(dest->as_register_hi(), src_addr_HI);
- __ movl(dest->as_register_lo(), src_addr_LO);
+ __ movptr(dest->as_register_lo(), src_addr_LO);
+ NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
} else if (dest->is_single_xmm()) {
Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
@@ -1019,15 +1114,25 @@ void LIR_Assembler::stack2reg(LIR_Opr sr
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (src->is_single_stack()) {
- __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
- __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+ if (type == T_OBJECT || type == T_ARRAY) {
+ __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
+ __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
+ } else {
+ __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
+ __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+ }
} else if (src->is_double_stack()) {
+#ifdef _LP64
+ __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
+ __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
+#else
__ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
- // push and pop the part at src + 4, adding 4 for the previous push
- __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 4 + 4));
- __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 4 + 4));
+ // push and pop the part at src + wordSize, adding wordSize for the previous push
+ __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), wordSize));
+ __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), wordSize));
__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
+#endif // _LP64
} else {
ShouldNotReachHere();
@@ -1052,7 +1157,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
// so blow away the value of to_rinfo before loading a
// partial word into it. Do it here so that it precedes
// the potential patch point below.
- __ xorl(dest->as_register(), dest->as_register());
+ __ xorptr(dest->as_register(), dest->as_register());
}
break;
}
@@ -1060,6 +1165,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
PatchingStub* patch = NULL;
if (patch_code != lir_patch_none) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ assert(from_addr.disp() != 0, "must have");
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
@@ -1091,13 +1197,21 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
case T_ADDRESS: // fall through
case T_OBJECT: // fall through
case T_ARRAY: // fall through
+#ifdef _LP64
+ __ movptr(dest->as_register(), from_addr);
+ break;
+#endif // _L64
case T_INT:
- __ movl(dest->as_register(), from_addr);
+ // %%% could this be a movl? this is safer but longer instruction
+ __ movl2ptr(dest->as_register(), from_addr);
break;
case T_LONG: {
Register to_lo = dest->as_register_lo();
Register to_hi = dest->as_register_hi();
+#ifdef _LP64
+ __ movptr(to_lo, as_Address_lo(addr));
+#else
Register base = addr->base()->as_register();
Register index = noreg;
if (addr->index()->is_register()) {
@@ -1109,7 +1223,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
// array access so this code will never have to deal with
// patches or null checks.
assert(info == NULL && patch == NULL, "must be");
- __ leal(to_hi, as_Address(addr));
+ __ lea(to_hi, as_Address(addr));
__ movl(to_lo, Address(to_hi, 0));
__ movl(to_hi, Address(to_hi, BytesPerWord));
} else if (base == to_lo || index == to_lo) {
@@ -1132,6 +1246,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
}
__ movl(to_hi, as_Address_hi(addr));
}
+#endif // _LP64
break;
}
@@ -1140,12 +1255,13 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
Register dest_reg = dest->as_register();
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movsxb(dest_reg, from_addr);
+ __ movsbl(dest_reg, from_addr);
} else {
__ movb(dest_reg, from_addr);
__ shll(dest_reg, 24);
__ sarl(dest_reg, 24);
}
+ // These are unsigned so the zero extension on 64bit is just what we need
break;
}
@@ -1153,22 +1269,26 @@ void LIR_Assembler::mem2reg(LIR_Opr src,
Register dest_reg = dest->as_register();
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movzxw(dest_reg, from_addr);
+ __ movzwl(dest_reg, from_addr);
} else {
__ movw(dest_reg, from_addr);
}
+ // This is unsigned so the zero extension on 64bit is just what we need
+ // __ movl2ptr(dest_reg, dest_reg);
break;
}
case T_SHORT: {
Register dest_reg = dest->as_register();
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movsxw(dest_reg, from_addr);
+ __ movswl(dest_reg, from_addr);
} else {
__ movw(dest_reg, from_addr);
__ shll(dest_reg, 16);
__ sarl(dest_reg, 16);
}
+ // Might not be needed in 64bit but certainly doesn't hurt (except for code size)
+ __ movl2ptr(dest_reg, dest_reg);
break;
}
@@ -1306,9 +1426,13 @@ void LIR_Assembler::emit_opConvert(LIR_O
switch (op->bytecode()) {
case Bytecodes::_i2l:
+#ifdef _LP64
+ __ movl2ptr(dest->as_register_lo(), src->as_register());
+#else
move_regs(src->as_register(), dest->as_register_lo());
move_regs(src->as_register(), dest->as_register_hi());
__ sarl(dest->as_register_hi(), 31);
+#endif // LP64
break;
case Bytecodes::_l2i:
@@ -1346,9 +1470,9 @@ void LIR_Assembler::emit_opConvert(LIR_O
case Bytecodes::_i2f:
case Bytecodes::_i2d:
if (dest->is_single_xmm()) {
- __ cvtsi2ss(dest->as_xmm_float_reg(), src->as_register());
+ __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
} else if (dest->is_double_xmm()) {
- __ cvtsi2sd(dest->as_xmm_double_reg(), src->as_register());
+ __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
} else {
assert(dest->fpu() == 0, "result must be on TOS");
__ movl(Address(rsp, 0), src->as_register());
@@ -1359,9 +1483,9 @@ void LIR_Assembler::emit_opConvert(LIR_O
case Bytecodes::_f2i:
case Bytecodes::_d2i:
if (src->is_single_xmm()) {
- __ cvttss2si(dest->as_register(), src->as_xmm_float_reg());
+ __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
} else if (src->is_double_xmm()) {
- __ cvttsd2si(dest->as_register(), src->as_xmm_double_reg());
+ __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
} else {
assert(src->fpu() == 0, "input must be on TOS");
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
@@ -1382,8 +1506,8 @@ void LIR_Assembler::emit_opConvert(LIR_O
assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
assert(dest->fpu() == 0, "result must be on TOS");
- __ movl(Address(rsp, 0), src->as_register_lo());
- __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
+ __ movptr(Address(rsp, 0), src->as_register_lo());
+ NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
__ fild_d(Address(rsp, 0));
// float result is rounded later through spilling
break;
@@ -1392,7 +1516,7 @@ void LIR_Assembler::emit_opConvert(LIR_O
case Bytecodes::_d2l:
assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
assert(src->fpu() == 0, "input must be on TOS");
- assert(dest == FrameMap::rax_rdx_long_opr, "runtime stub places result in these registers");
+ assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
// instruction sequence too long to inline it here
{
@@ -1439,7 +1563,7 @@ void LIR_Assembler::emit_alloc_array(LIR
} else if (len == tmp3) {
// everything is ok
} else {
- __ movl(tmp3, len);
+ __ mov(tmp3, len);
}
__ allocate_array(op->obj()->as_register(),
len,
@@ -1466,31 +1590,32 @@ void LIR_Assembler::emit_opTypeCheck(LIR
CodeStub* stub = op->stub();
Label done;
- __ cmpl(value, 0);
+ __ cmpptr(value, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, done);
add_debug_info_for_null_check_here(op->info_for_exception());
- __ movl(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
- __ movl(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
+ __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
// get instance klass
- __ movl(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
+ __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
// get super_check_offset
__ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
__ jcc(Assembler::equal, done);
// check for immediate negative hit
__ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, *stub->entry());
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(k_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(k_RInfo);
+ // result is a boolean
__ cmpl(k_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
__ bind(done);
@@ -1521,10 +1646,14 @@ void LIR_Assembler::emit_opTypeCheck(LIR
if (!k->is_loaded()) {
jobject2reg_with_patching(k_RInfo, op->info_for_patch());
} else {
+#ifdef _LP64
+ __ movoop(k_RInfo, k->encoding());
+#else
k_RInfo = noreg;
+#endif // _LP64
}
assert(obj != k_RInfo, "must be different");
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
if (op->profiled_method() != NULL) {
ciMethod* method = op->profiled_method();
int bci = op->profiled_bci();
@@ -1556,9 +1685,13 @@ void LIR_Assembler::emit_opTypeCheck(LIR
// get object classo
// not a safepoint as obj null check happens earlier
if (k->is_loaded()) {
+#ifdef _LP64
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+#else
__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+#endif // _LP64
} else {
- __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
}
__ jcc(Assembler::notEqual, *stub->entry());
@@ -1566,24 +1699,37 @@ void LIR_Assembler::emit_opTypeCheck(LIR
} else {
// get object class
// not a safepoint as obj null check happens earlier
- __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
if (k->is_loaded()) {
// See if we get an immediate positive hit
+#ifdef _LP64
+ __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
+#else
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
+#endif // _LP64
if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
__ jcc(Assembler::notEqual, *stub->entry());
} else {
// See if we get an immediate positive hit
__ jcc(Assembler::equal, done);
// check for self
+#ifdef _LP64
+ __ cmpptr(klass_RInfo, k_RInfo);
+#else
__ cmpoop(klass_RInfo, k->encoding());
+#endif // _LP64
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
+ __ push(klass_RInfo);
+#ifdef _LP64
+ __ push(k_RInfo);
+#else
__ pushoop(k->encoding());
+#endif // _LP64
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(klass_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(klass_RInfo);
+ // result is a boolean
__ cmpl(klass_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
}
@@ -1591,20 +1737,21 @@ void LIR_Assembler::emit_opTypeCheck(LIR
} else {
__ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
__ jcc(Assembler::equal, done);
// check for immediate negative hit
__ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, *stub->entry());
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(k_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(k_RInfo);
+ // result is a boolean
__ cmpl(k_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
__ bind(done);
@@ -1612,7 +1759,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR
}
if (dst != obj) {
- __ movl(dst, obj);
+ __ mov(dst, obj);
}
} else if (code == lir_instanceof) {
Register obj = op->object()->as_register();
@@ -1632,29 +1779,33 @@ void LIR_Assembler::emit_opTypeCheck(LIR
// so let's do it before loading the class
if (!k->is_loaded()) {
jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+ } else {
+ LP64_ONLY(__ movoop(k_RInfo, k->encoding()));
}
assert(obj != k_RInfo, "must be different");
__ verify_oop(obj);
if (op->fast_check()) {
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, zero);
// get object class
// not a safepoint as obj null check happens earlier
- if (k->is_loaded()) {
- __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+ if (LP64_ONLY(false &&) k->is_loaded()) {
+ NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding()));
k_RInfo = noreg;
} else {
- __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
}
__ jcc(Assembler::equal, one);
} else {
// get object class
// not a safepoint as obj null check happens earlier
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, zero);
- __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+
+#ifndef _LP64
if (k->is_loaded()) {
// See if we get an immediate positive hit
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
@@ -1663,40 +1814,43 @@ void LIR_Assembler::emit_opTypeCheck(LIR
// check for self
__ cmpoop(klass_RInfo, k->encoding());
__ jcc(Assembler::equal, one);
- __ pushl(klass_RInfo);
+ __ push(klass_RInfo);
__ pushoop(k->encoding());
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(dst);
+ __ pop(klass_RInfo);
+ __ pop(dst);
__ jmp(done);
}
} else {
+#else
+ { // YUCK
+#endif // LP64
assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
__ movl(dst, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
__ jcc(Assembler::equal, one);
// check for immediate negative hit
__ cmpl(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, zero);
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, one);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(dst);
+ __ pop(klass_RInfo);
+ __ pop(dst);
__ jmp(done);
}
}
__ bind(zero);
- __ xorl(dst, dst);
+ __ xorptr(dst, dst);
__ jmp(done);
__ bind(one);
- __ movl(dst, 1);
+ __ movptr(dst, 1);
__ bind(done);
} else {
ShouldNotReachHere();
@@ -1706,8 +1860,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR
void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
- if (op->code() == lir_cas_long) {
- assert(VM_Version::supports_cx8(), "wrong machine");
+ if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
assert(op->new_value()->as_register_lo() == rbx, "wrong register");
@@ -1716,10 +1869,11 @@ void LIR_Assembler::emit_compare_and_swa
if (os::is_MP()) {
__ lock();
}
- __ cmpxchg8(Address(addr, 0));
-
- } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
- Register addr = op->addr()->as_register();
+ NOT_LP64(__ cmpxchg8(Address(addr, 0)));
+
+ } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
+ NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
+ Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
Register newval = op->new_value()->as_register();
Register cmpval = op->cmp_value()->as_register();
assert(cmpval == rax, "wrong register");
@@ -1730,7 +1884,28 @@ void LIR_Assembler::emit_compare_and_swa
if (os::is_MP()) {
__ lock();
}
- __ cmpxchg(newval, Address(addr, 0));
+ if ( op->code() == lir_cas_obj) {
+ __ cmpxchgptr(newval, Address(addr, 0));
+ } else if (op->code() == lir_cas_int) {
+ __ cmpxchgl(newval, Address(addr, 0));
+ } else {
+ LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
+ }
+#ifdef _LP64
+ } else if (op->code() == lir_cas_long) {
+ Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
+ Register newval = op->new_value()->as_register_lo();
+ Register cmpval = op->cmp_value()->as_register_lo();
+ assert(cmpval == rax, "wrong register");
+ assert(newval != NULL, "new val must be register");
+ assert(cmpval != newval, "cmp and new values must be in different registers");
+ assert(cmpval != addr, "cmp and addr must be in different registers");
+ assert(newval != addr, "new value and addr must be in different registers");
+ if (os::is_MP()) {
+ __ lock();
+ }
+ __ cmpxchgq(newval, Address(addr, 0));
+#endif // _LP64
} else {
Unimplemented();
}
@@ -1765,17 +1940,17 @@ void LIR_Assembler::cmove(LIR_Condition
// optimized version that does not require a branch
if (opr2->is_single_cpu()) {
assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
- __ cmovl(ncond, result->as_register(), opr2->as_register());
+ __ cmov(ncond, result->as_register(), opr2->as_register());
} else if (opr2->is_double_cpu()) {
assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
- __ cmovl(ncond, result->as_register_lo(), opr2->as_register_lo());
- __ cmovl(ncond, result->as_register_hi(), opr2->as_register_hi());
+ __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
+ NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
} else if (opr2->is_single_stack()) {
__ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
} else if (opr2->is_double_stack()) {
- __ cmovl(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
- __ cmovl(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));
+ __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
+ NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
} else {
ShouldNotReachHere();
}
@@ -1851,23 +2026,28 @@ void LIR_Assembler::arith_op(LIR_Code co
// cpu register - cpu register
Register rreg_lo = right->as_register_lo();
Register rreg_hi = right->as_register_hi();
- assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi);
+ NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
+ LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
switch (code) {
case lir_add:
- __ addl(lreg_lo, rreg_lo);
- __ adcl(lreg_hi, rreg_hi);
+ __ addptr(lreg_lo, rreg_lo);
+ NOT_LP64(__ adcl(lreg_hi, rreg_hi));
break;
case lir_sub:
- __ subl(lreg_lo, rreg_lo);
- __ sbbl(lreg_hi, rreg_hi);
+ __ subptr(lreg_lo, rreg_lo);
+ NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
break;
case lir_mul:
+#ifdef _LP64
+ __ imulq(lreg_lo, rreg_lo);
+#else
assert(lreg_lo == rax && lreg_hi == rdx, "must be");
__ imull(lreg_hi, rreg_lo);
__ imull(rreg_hi, lreg_lo);
__ addl (rreg_hi, lreg_hi);
__ mull (rreg_lo);
__ addl (lreg_hi, rreg_hi);
+#endif // _LP64
break;
default:
ShouldNotReachHere();
@@ -1875,20 +2055,35 @@ void LIR_Assembler::arith_op(LIR_Code co
} else if (right->is_constant()) {
// cpu register - constant
+#ifdef _LP64
+ jlong c = right->as_constant_ptr()->as_jlong_bits();
+ __ movptr(r10, (intptr_t) c);
+ switch (code) {
+ case lir_add:
+ __ addptr(lreg_lo, r10);
+ break;
+ case lir_sub:
+ __ subptr(lreg_lo, r10);
+ break;
+ default:
+ ShouldNotReachHere();
+ }
+#else
jint c_lo = right->as_constant_ptr()->as_jint_lo();
jint c_hi = right->as_constant_ptr()->as_jint_hi();
switch (code) {
case lir_add:
- __ addl(lreg_lo, c_lo);
+ __ addptr(lreg_lo, c_lo);
__ adcl(lreg_hi, c_hi);
break;
case lir_sub:
- __ subl(lreg_lo, c_lo);
+ __ subptr(lreg_lo, c_lo);
__ sbbl(lreg_hi, c_hi);
break;
default:
ShouldNotReachHere();
}
+#endif // _LP64
} else {
ShouldNotReachHere();
@@ -2065,11 +2260,11 @@ void LIR_Assembler::arith_op(LIR_Code co
jint c = right->as_constant_ptr()->as_jint();
switch (code) {
case lir_add: {
- __ increment(laddr, c);
+ __ incrementl(laddr, c);
break;
}
case lir_sub: {
- __ decrement(laddr, c);
+ __ decrementl(laddr, c);
break;
}
default: ShouldNotReachHere();
@@ -2211,9 +2406,9 @@ void LIR_Assembler::logic_op(LIR_Code co
} else {
Register rright = right->as_register();
switch (code) {
- case lir_logic_and: __ andl (reg, rright); break;
- case lir_logic_or : __ orl (reg, rright); break;
- case lir_logic_xor: __ xorl (reg, rright); break;
+ case lir_logic_and: __ andptr (reg, rright); break;
+ case lir_logic_or : __ orptr (reg, rright); break;
+ case lir_logic_xor: __ xorptr (reg, rright); break;
default: ShouldNotReachHere();
}
}
@@ -2222,6 +2417,21 @@ void LIR_Assembler::logic_op(LIR_Code co
Register l_lo = left->as_register_lo();
Register l_hi = left->as_register_hi();
if (right->is_constant()) {
+#ifdef _LP64
+ __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
+ switch (code) {
+ case lir_logic_and:
+ __ andq(l_lo, rscratch1);
+ break;
+ case lir_logic_or:
+ __ orq(l_lo, rscratch1);
+ break;
+ case lir_logic_xor:
+ __ xorq(l_lo, rscratch1);
+ break;
+ default: ShouldNotReachHere();
+ }
+#else
int r_lo = right->as_constant_ptr()->as_jint_lo();
int r_hi = right->as_constant_ptr()->as_jint_hi();
switch (code) {
@@ -2239,22 +2449,23 @@ void LIR_Assembler::logic_op(LIR_Code co
break;
default: ShouldNotReachHere();
}
+#endif // _LP64
} else {
Register r_lo = right->as_register_lo();
Register r_hi = right->as_register_hi();
assert(l_lo != r_hi, "overwriting registers");
switch (code) {
case lir_logic_and:
- __ andl(l_lo, r_lo);
- __ andl(l_hi, r_hi);
+ __ andptr(l_lo, r_lo);
+ NOT_LP64(__ andptr(l_hi, r_hi);)
break;
case lir_logic_or:
- __ orl(l_lo, r_lo);
- __ orl(l_hi, r_hi);
+ __ orptr(l_lo, r_lo);
+ NOT_LP64(__ orptr(l_hi, r_hi);)
break;
case lir_logic_xor:
- __ xorl(l_lo, r_lo);
- __ xorl(l_hi, r_hi);
+ __ xorptr(l_lo, r_lo);
+ NOT_LP64(__ xorptr(l_hi, r_hi);)
break;
default: ShouldNotReachHere();
}
@@ -2263,6 +2474,9 @@ void LIR_Assembler::logic_op(LIR_Code co
Register dst_lo = dst->as_register_lo();
Register dst_hi = dst->as_register_hi();
+#ifdef _LP64
+ move_regs(l_lo, dst_lo);
+#else
if (dst_lo == l_hi) {
assert(dst_hi != l_lo, "overwriting registers");
move_regs(l_hi, dst_hi);
@@ -2272,6 +2486,7 @@ void LIR_Assembler::logic_op(LIR_Code co
move_regs(l_lo, dst_lo);
move_regs(l_hi, dst_hi);
}
+#endif // _LP64
}
}
@@ -2306,7 +2521,7 @@ void LIR_Assembler::arithmetic_idiv(LIR_
move_regs(lreg, dreg);
} else if (code == lir_irem) {
Label done;
- __ movl(dreg, lreg);
+ __ mov(dreg, lreg);
__ andl(dreg, 0x80000000 | (divisor - 1));
__ jcc(Assembler::positive, done);
__ decrement(dreg);
@@ -2340,21 +2555,36 @@ void LIR_Assembler::comp_op(LIR_Conditio
Register reg1 = opr1->as_register();
if (opr2->is_single_cpu()) {
// cpu register - cpu register
- __ cmpl(reg1, opr2->as_register());
+ if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+ __ cmpptr(reg1, opr2->as_register());
+ } else {
+ assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
+ __ cmpl(reg1, opr2->as_register());
+ }
} else if (opr2->is_stack()) {
// cpu register - stack
- __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+ __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ } else {
+ __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ }
} else if (opr2->is_constant()) {
// cpu register - constant
LIR_Const* c = opr2->as_constant_ptr();
if (c->type() == T_INT) {
__ cmpl(reg1, c->as_jint());
- } else if (c->type() == T_OBJECT) {
+ } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+ // In 64bit oops are single register
jobject o = c->as_jobject();
if (o == NULL) {
- __ cmpl(reg1, NULL_WORD);
+ __ cmpptr(reg1, (int32_t)NULL_WORD);
} else {
+#ifdef _LP64
+ __ movoop(rscratch1, o);
+ __ cmpptr(reg1, rscratch1);
+#else
__ cmpoop(reg1, c->as_jobject());
+#endif // _LP64
}
} else {
ShouldNotReachHere();
@@ -2373,6 +2603,9 @@ void LIR_Assembler::comp_op(LIR_Conditio
Register xlo = opr1->as_register_lo();
Register xhi = opr1->as_register_hi();
if (opr2->is_double_cpu()) {
+#ifdef _LP64
+ __ cmpptr(xlo, opr2->as_register_lo());
+#else
// cpu register - cpu register
Register ylo = opr2->as_register_lo();
Register yhi = opr2->as_register_hi();
@@ -2381,11 +2614,16 @@ void LIR_Assembler::comp_op(LIR_Conditio
if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
__ orl(xhi, xlo);
}
+#endif // _LP64
} else if (opr2->is_constant()) {
// cpu register - constant 0
assert(opr2->as_jlong() == (jlong)0, "only handles zero");
+#ifdef _LP64
+ __ cmpptr(xlo, (int32_t)opr2->as_jlong());
+#else
assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
__ orl(xhi, xlo);
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2438,16 +2676,28 @@ void LIR_Assembler::comp_op(LIR_Conditio
__ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
} else if (opr1->is_address() && opr2->is_constant()) {
+ LIR_Const* c = opr2->as_constant_ptr();
+#ifdef _LP64
+ if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+ assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
+ __ movoop(rscratch1, c->as_jobject());
+ }
+#endif // LP64
if (op->info() != NULL) {
add_debug_info_for_null_check_here(op->info());
}
// special case: address - constant
LIR_Address* addr = opr1->as_address_ptr();
- LIR_Const* c = opr2->as_constant_ptr();
if (c->type() == T_INT) {
__ cmpl(as_Address(addr), c->as_jint());
- } else if (c->type() == T_OBJECT) {
+ } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+#ifdef _LP64
+ // %%% Make this explode if addr isn't reachable until we figure out a
+ // better strategy by giving noreg as the temp for as_Address
+ __ cmpptr(rscratch1, as_Address(addr, noreg));
+#else
__ cmpoop(as_Address(addr), c->as_jobject());
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2476,11 +2726,27 @@ void LIR_Assembler::comp_fl2i(LIR_Code c
}
} else {
assert(code == lir_cmp_l2i, "check");
+#ifdef _LP64
+ Register dest = dst->as_register();
+ __ xorptr(dest, dest);
+ Label high, done;
+ __ cmpptr(left->as_register_lo(), right->as_register_lo());
+ __ jcc(Assembler::equal, done);
+ __ jcc(Assembler::greater, high);
+ __ decrement(dest);
+ __ jmp(done);
+ __ bind(high);
+ __ increment(dest);
+
+ __ bind(done);
+
+#else
__ lcmp2int(left->as_register_hi(),
left->as_register_lo(),
right->as_register_hi(),
right->as_register_lo());
move_regs(left->as_register_hi(), dst->as_register());
+#endif // _LP64
}
}
@@ -2551,7 +2817,8 @@ void LIR_Assembler::emit_static_call_stu
__ movoop(rbx, (jobject)NULL);
// must be set to -1 at code generation time
assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
- __ jump(RuntimeAddress((address)-1));
+ // On 64bit this will die since it will take a movq & jmp, must be only a jmp
+ __ jump(RuntimeAddress(__ pc()));
assert(__ offset() - start <= call_stub_size, "stub too big")
__ end_a_stub();
@@ -2616,6 +2883,14 @@ void LIR_Assembler::shift_op(LIR_Code co
Register lo = left->as_register_lo();
Register hi = left->as_register_hi();
assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
+#ifdef _LP64
+ switch (code) {
+ case lir_shl: __ shlptr(lo); break;
+ case lir_shr: __ sarptr(lo); break;
+ case lir_ushr: __ shrptr(lo); break;
+ default: ShouldNotReachHere();
+ }
+#else
switch (code) {
case lir_shl: __ lshl(hi, lo); break;
@@ -2623,6 +2898,7 @@ void LIR_Assembler::shift_op(LIR_Code co
case lir_ushr: __ lshr(hi, lo, false); break;
default: ShouldNotReachHere();
}
+#endif // LP64
} else {
ShouldNotReachHere();
}
@@ -2643,7 +2919,21 @@ void LIR_Assembler::shift_op(LIR_Code co
default: ShouldNotReachHere();
}
} else if (dest->is_double_cpu()) {
+#ifndef _LP64
Unimplemented();
+#else
+ // first move left into dest so that left is not destroyed by the shift
+ Register value = dest->as_register_lo();
+ count = count & 0x1F; // Java spec
+
+ move_regs(left->as_register_lo(), value);
+ switch (code) {
+ case lir_shl: __ shlptr(value, count); break;
+ case lir_shr: __ sarptr(value, count); break;
+ case lir_ushr: __ shrptr(value, count); break;
+ default: ShouldNotReachHere();
+ }
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2654,7 +2944,7 @@ void LIR_Assembler::store_parameter(Regi
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
- __ movl (Address(rsp, offset_from_rsp_in_bytes), r);
+ __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
}
@@ -2662,7 +2952,7 @@ void LIR_Assembler::store_parameter(jint
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
- __ movl (Address(rsp, offset_from_rsp_in_bytes), c);
+ __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
}
@@ -2710,27 +3000,52 @@ void LIR_Assembler::emit_arraycopy(LIR_O
// these are just temporary placements until we need to reload
store_parameter(src_pos, 3);
store_parameter(src, 4);
- assert(src == rcx && src_pos == rdx, "mismatch in calling convention");
+ NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
+
+ address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
// pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
- __ pushl(length);
- __ pushl(dst_pos);
- __ pushl(dst);
- __ pushl(src_pos);
- __ pushl(src);
- address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
+#ifdef _LP64
+ // The arguments are in java calling convention so we can trivially shift them to C
+ // convention
+ assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg0, j_rarg0);
+ assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg1, j_rarg1);
+ assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg2, j_rarg2);
+ assert_different_registers(c_rarg3, j_rarg4);
+ __ mov(c_rarg3, j_rarg3);
+#ifdef _WIN64
+ // Allocate abi space for args but be sure to keep stack aligned
+ __ subptr(rsp, 6*wordSize);
+ store_parameter(j_rarg4, 4);
+ __ call(RuntimeAddress(entry));
+ __ addptr(rsp, 6*wordSize);
+#else
+ __ mov(c_rarg4, j_rarg4);
+ __ call(RuntimeAddress(entry));
+#endif // _WIN64
+#else
+ __ push(length);
+ __ push(dst_pos);
+ __ push(dst);
+ __ push(src_pos);
+ __ push(src);
__ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
+
+#endif // _LP64
__ cmpl(rax, 0);
__ jcc(Assembler::equal, *stub->continuation());
// Reload values from the stack so they are where the stub
// expects them.
- __ movl (dst, Address(rsp, 0*BytesPerWord));
- __ movl (dst_pos, Address(rsp, 1*BytesPerWord));
- __ movl (length, Address(rsp, 2*BytesPerWord));
- __ movl (src_pos, Address(rsp, 3*BytesPerWord));
- __ movl (src, Address(rsp, 4*BytesPerWord));
+ __ movptr (dst, Address(rsp, 0*BytesPerWord));
+ __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
+ __ movptr (length, Address(rsp, 2*BytesPerWord));
+ __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
+ __ movptr (src, Address(rsp, 4*BytesPerWord));
__ jmp(*stub->entry());
__ bind(*stub->continuation());
@@ -2769,13 +3084,15 @@ void LIR_Assembler::emit_arraycopy(LIR_O
Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
+ // length and pos's are all sign extended at this point on 64bit
+
// test for NULL
if (flags & LIR_OpArrayCopy::src_null_check) {
- __ testl(src, src);
+ __ testptr(src, src);
__ jcc(Assembler::zero, *stub->entry());
}
if (flags & LIR_OpArrayCopy::dst_null_check) {
- __ testl(dst, dst);
+ __ testptr(dst, dst);
__ jcc(Assembler::zero, *stub->entry());
}
@@ -2794,19 +3111,19 @@ void LIR_Assembler::emit_arraycopy(LIR_O
}
if (flags & LIR_OpArrayCopy::src_range_check) {
- __ leal(tmp, Address(src_pos, length, Address::times_1, 0));
+ __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
__ cmpl(tmp, src_length_addr);
__ jcc(Assembler::above, *stub->entry());
}
if (flags & LIR_OpArrayCopy::dst_range_check) {
- __ leal(tmp, Address(dst_pos, length, Address::times_1, 0));
+ __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
__ cmpl(tmp, dst_length_addr);
__ jcc(Assembler::above, *stub->entry());
}
if (flags & LIR_OpArrayCopy::type_check) {
- __ movl(tmp, src_klass_addr);
- __ cmpl(tmp, dst_klass_addr);
+ __ movptr(tmp, src_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::notEqual, *stub->entry());
}
@@ -2822,14 +3139,14 @@ void LIR_Assembler::emit_arraycopy(LIR_O
Label known_ok, halt;
__ movoop(tmp, default_type->encoding());
if (basic_type != T_OBJECT) {
- __ cmpl(tmp, dst_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::notEqual, halt);
- __ cmpl(tmp, src_klass_addr);
+ __ cmpptr(tmp, src_klass_addr);
__ jcc(Assembler::equal, known_ok);
} else {
- __ cmpl(tmp, dst_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::equal, known_ok);
- __ cmpl(src, dst);
+ __ cmpptr(src, dst);
__ jcc(Assembler::equal, known_ok);
}
__ bind(halt);
@@ -2838,14 +3155,24 @@ void LIR_Assembler::emit_arraycopy(LIR_O
}
#endif
- __ leal(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ if (shift_amount > 0 && basic_type != T_OBJECT) {
+ __ shlptr(length, shift_amount);
+ }
+
+#ifdef _LP64
+ assert_different_registers(c_rarg0, dst, dst_pos, length);
+ __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ assert_different_registers(c_rarg1, length);
+ __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ __ mov(c_rarg2, length);
+
+#else
+ __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
store_parameter(tmp, 0);
- __ leal(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
store_parameter(tmp, 1);
- if (shift_amount > 0 && basic_type != T_OBJECT) {
- __ shll(length, shift_amount);
- }
store_parameter(length, 2);
+#endif // _LP64
if (basic_type == T_OBJECT) {
__ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
} else {
@@ -2945,13 +3272,13 @@ void LIR_Assembler::emit_profile_call(LI
}
}
} else {
- __ movl(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
+ __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
Label update_done;
uint i;
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
// See if the receiver is receiver[n].
- __ cmpl(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
+ __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
__ jcc(Assembler::notEqual, next_test);
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
__ addl(data_addr, DataLayout::counter_increment);
@@ -2963,9 +3290,9 @@ void LIR_Assembler::emit_profile_call(LI
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
- __ cmpl(recv_addr, NULL_WORD);
+ __ cmpptr(recv_addr, (int32_t)NULL_WORD);
__ jcc(Assembler::notEqual, next_test);
- __ movl(recv_addr, recv);
+ __ movptr(recv_addr, recv);
__ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
if (i < (VirtualCallData::row_limit() - 1)) {
__ jmp(update_done);
@@ -2985,7 +3312,7 @@ void LIR_Assembler::emit_delay(LIR_OpDel
void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
- __ leal(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
+ __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
}
@@ -3001,6 +3328,11 @@ void LIR_Assembler::negate(LIR_Opr left,
} else if (left->is_double_cpu()) {
Register lo = left->as_register_lo();
+#ifdef _LP64
+ Register dst = dest->as_register_lo();
+ __ movptr(dst, lo);
+ __ negptr(dst);
+#else
Register hi = left->as_register_hi();
__ lneg(hi, lo);
if (dest->as_register_lo() == hi) {
@@ -3011,6 +3343,7 @@ void LIR_Assembler::negate(LIR_Opr left,
move_regs(lo, dest->as_register_lo());
move_regs(hi, dest->as_register_hi());
}
+#endif // _LP64
} else if (dest->is_single_xmm()) {
if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
@@ -3039,8 +3372,9 @@ void LIR_Assembler::negate(LIR_Opr left,
void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
assert(addr->is_address() && dest->is_register(), "check");
- Register reg = dest->as_register();
- __ leal(dest->as_register(), as_Address(addr->as_address_ptr()));
+ Register reg;
+ reg = dest->as_pointer_register();
+ __ lea(reg, as_Address(addr->as_address_ptr()));
}
@@ -3063,9 +3397,13 @@ void LIR_Assembler::volatile_move_op(LIR
if (src->is_double_xmm()) {
if (dest->is_double_cpu()) {
- __ movd(dest->as_register_lo(), src->as_xmm_double_reg());
+#ifdef _LP64
+ __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
+#else
+ __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
__ psrlq(src->as_xmm_double_reg(), 32);
- __ movd(dest->as_register_hi(), src->as_xmm_double_reg());
+ __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
+#endif // _LP64
} else if (dest->is_double_stack()) {
__ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
} else if (dest->is_address()) {
@@ -3109,7 +3447,8 @@ void LIR_Assembler::volatile_move_op(LIR
void LIR_Assembler::membar() {
- __ membar();
+ // QQQ sparc TSO uses this,
+ __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
}
void LIR_Assembler::membar_acquire() {
@@ -3124,7 +3463,12 @@ void LIR_Assembler::membar_release() {
void LIR_Assembler::get_thread(LIR_Opr result_reg) {
assert(result_reg->is_register(), "check");
+#ifdef _LP64
+ // __ get_thread(result_reg->as_register_lo());
+ __ mov(result_reg->as_register(), r15_thread);
+#else
__ get_thread(result_reg->as_register());
+#endif // _LP64
}
--- a/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp Thu Sep 04 18:40:43 2008 -0700
@@ -36,13 +36,20 @@
address float_constant(float f);
address double_constant(double d);
+ bool is_literal_address(LIR_Address* addr);
+
+ // When we need to use something other than rscratch1 use this
+ // method.
+ Address as_Address(LIR_Address* addr, Register tmp);
+
+
public:
void store_parameter(Register r, int offset_from_esp_in_words);
void store_parameter(jint c, int offset_from_esp_in_words);
void store_parameter(jobject c, int offset_from_esp_in_words);
- enum { call_stub_size = 15,
+ enum { call_stub_size = NOT_LP64(15) LP64_ONLY(28),
exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175),
- deopt_handler_size = 10
+ deopt_handler_size = NOT_LP64(10) LP64_ONLY(17)
};
--- a/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -77,7 +77,7 @@ LIR_Opr LIRGenerator::result_register_fo
switch (type->tag()) {
case intTag: opr = FrameMap::rax_opr; break;
case objectTag: opr = FrameMap::rax_oop_opr; break;
- case longTag: opr = FrameMap::rax_rdx_long_opr; break;
+ case longTag: opr = FrameMap::long0_opr; break;
case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break;
case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break;
@@ -117,12 +117,14 @@ bool LIRGenerator::can_store_as_constant
bool LIRGenerator::can_inline_as_constant(Value v) const {
+ if (v->type()->tag() == longTag) return false;
return v->type()->tag() != objectTag ||
(v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
}
bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
+ if (c->type() == T_LONG) return false;
return c->type() != T_OBJECT || c->as_jobject() == NULL;
}
@@ -155,6 +157,13 @@ LIR_Address* LIRGenerator::emit_array_ad
addr = new LIR_Address(array_opr,
offset_in_bytes + index_opr->as_jint() * elem_size, type);
} else {
+#ifdef _LP64
+ if (index_opr->type() == T_INT) {
+ LIR_Opr tmp = new_register(T_LONG);
+ __ convert(Bytecodes::_i2l, index_opr, tmp);
+ index_opr = tmp;
+ }
+#endif // _LP64
addr = new LIR_Address(array_opr,
index_opr,
LIR_Address::scale(type),
@@ -164,7 +173,7 @@ LIR_Address* LIRGenerator::emit_array_ad
// This store will need a precise card mark, so go ahead and
// compute the full adddres instead of computing once for the
// store and again for the card mark.
- LIR_Opr tmp = new_register(T_INT);
+ LIR_Opr tmp = new_pointer_register();
__ leal(LIR_OprFact::address(addr), tmp);
return new LIR_Address(tmp, 0, type);
} else {
@@ -174,9 +183,8 @@ LIR_Address* LIRGenerator::emit_array_ad
void LIRGenerator::increment_counter(address counter, int step) {
- LIR_Opr temp = new_register(T_INT);
- LIR_Opr pointer = new_register(T_INT);
- __ move(LIR_OprFact::intConst((int)counter), pointer);
+ LIR_Opr pointer = new_pointer_register();
+ __ move(LIR_OprFact::intptrConst(counter), pointer);
LIR_Address* addr = new LIR_Address(pointer, 0, T_INT);
increment_counter(addr, step);
}
@@ -481,7 +489,7 @@ void LIRGenerator::do_ArithmeticOp_Long(
left.load_item();
right.load_item();
- LIR_Opr reg = FrameMap::rax_rdx_long_opr;
+ LIR_Opr reg = FrameMap::long0_opr;
arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
LIR_Opr result = rlock_result(x);
__ move(reg, result);
@@ -690,10 +698,10 @@ void LIRGenerator::do_AttemptUpdate(Intr
LIRItem new_value (x->argument_at(2), this); // replace field with new_value if it matches cmp_value
// compare value must be in rdx,eax (hi,lo); may be destroyed by cmpxchg8 instruction
- cmp_value.load_item_force(FrameMap::rax_rdx_long_opr);
+ cmp_value.load_item_force(FrameMap::long0_opr);
// new value must be in rcx,ebx (hi,lo)
- new_value.load_item_force(FrameMap::rbx_rcx_long_opr);
+ new_value.load_item_force(FrameMap::long1_opr);
// object pointer register is overwritten with field address
obj.load_item();
@@ -720,7 +728,10 @@ void LIRGenerator::do_CompareAndSwap(Int
LIRItem val (x->argument_at(3), this); // replace field with val if matches cmp
assert(obj.type()->tag() == objectTag, "invalid type");
- assert(offset.type()->tag() == intTag, "invalid type");
+
+ // In 64bit the type can be long, sparc doesn't have this assert
+ // assert(offset.type()->tag() == intTag, "invalid type");
+
assert(cmp.type()->tag() == type->tag(), "invalid type");
assert(val.type()->tag() == type->tag(), "invalid type");
@@ -735,8 +746,8 @@ void LIRGenerator::do_CompareAndSwap(Int
cmp.load_item_force(FrameMap::rax_opr);
val.load_item();
} else if (type == longType) {
- cmp.load_item_force(FrameMap::rax_rdx_long_opr);
- val.load_item_force(FrameMap::rbx_rcx_long_opr);
+ cmp.load_item_force(FrameMap::long0_opr);
+ val.load_item_force(FrameMap::long1_opr);
} else {
ShouldNotReachHere();
}
@@ -833,12 +844,33 @@ void LIRGenerator::do_ArrayCopy(Intrinsi
// operands for arraycopy must use fixed registers, otherwise
// LinearScan will fail allocation (because arraycopy always needs a
// call)
+
+#ifndef _LP64
src.load_item_force (FrameMap::rcx_oop_opr);
src_pos.load_item_force (FrameMap::rdx_opr);
dst.load_item_force (FrameMap::rax_oop_opr);
dst_pos.load_item_force (FrameMap::rbx_opr);
length.load_item_force (FrameMap::rdi_opr);
LIR_Opr tmp = (FrameMap::rsi_opr);
+#else
+
+ // The java calling convention will give us enough registers
+ // so that on the stub side the args will be perfect already.
+ // On the other slow/special case side we call C and the arg
+ // positions are not similar enough to pick one as the best.
+ // Also because the java calling convention is a "shifted" version
+ // of the C convention we can process the java args trivially into C
+ // args without worry of overwriting during the xfer
+
+ src.load_item_force (FrameMap::as_oop_opr(j_rarg0));
+ src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
+ dst.load_item_force (FrameMap::as_oop_opr(j_rarg2));
+ dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
+ length.load_item_force (FrameMap::as_opr(j_rarg4));
+
+ LIR_Opr tmp = FrameMap::as_opr(j_rarg5);
+#endif // LP64
+
set_no_result(x);
int flags;
@@ -857,7 +889,7 @@ LIR_Opr fixed_register_for(BasicType typ
case T_FLOAT: return FrameMap::fpu0_float_opr;
case T_DOUBLE: return FrameMap::fpu0_double_opr;
case T_INT: return FrameMap::rax_opr;
- case T_LONG: return FrameMap::rax_rdx_long_opr;
+ case T_LONG: return FrameMap::long0_opr;
default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
}
}
@@ -1161,9 +1193,13 @@ void LIRGenerator::do_If(If* x) {
LIR_Opr LIRGenerator::getThreadPointer() {
+#ifdef _LP64
+ return FrameMap::as_pointer_opr(r15_thread);
+#else
LIR_Opr result = new_register(T_INT);
__ get_thread(result);
return result;
+#endif //
}
void LIRGenerator::trace_block_entry(BlockBegin* block) {
--- a/src/cpu/x86/vm/c1_LinearScan_x86.hpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_LinearScan_x86.hpp Thu Sep 04 18:40:43 2008 -0700
@@ -23,18 +23,29 @@
*/
inline bool LinearScan::is_processed_reg_num(int reg_num) {
+#ifndef _LP64
// rsp and rbp (numbers 6 ancd 7) are ignored
assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
assert(reg_num >= 0, "invalid reg_num");
return reg_num < 6 || reg_num > 7;
+#else
+ // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
+ assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
+ assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
+ assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
+ assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
+ assert(reg_num >= 0, "invalid reg_num");
+
+ return reg_num < 12 || reg_num > 15;
+#endif // _LP64
}
inline int LinearScan::num_physical_regs(BasicType type) {
// Intel requires two cpu registers for long,
// but requires only one fpu register for double
- if (type == T_LONG) {
+ if (LP64_ONLY(false &&) type == T_LONG) {
return 2;
}
return 1;
--- a/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -26,18 +26,17 @@
#include "incls/_c1_MacroAssembler_x86.cpp.incl"
int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr, Register scratch, Label& slow_case) {
- const int aligned_mask = 3;
+ const int aligned_mask = BytesPerWord -1;
const int hdr_offset = oopDesc::mark_offset_in_bytes();
assert(hdr == rax, "hdr must be rax, for the cmpxchg instruction");
assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
- assert(BytesPerWord == 4, "adjust aligned_mask and code");
Label done;
int null_check_offset = -1;
verify_oop(obj);
// save object being locked into the BasicObjectLock
- movl(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
+ movptr(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
if (UseBiasedLocking) {
assert(scratch != noreg, "should have scratch register at this point");
@@ -47,16 +46,16 @@ int C1_MacroAssembler::lock_object(Regis
}
// Load object header
- movl(hdr, Address(obj, hdr_offset));
+ movptr(hdr, Address(obj, hdr_offset));
// and mark it as unlocked
- orl(hdr, markOopDesc::unlocked_value);
+ orptr(hdr, markOopDesc::unlocked_value);
// save unlocked object header into the displaced header location on the stack
- movl(Address(disp_hdr, 0), hdr);
+ movptr(Address(disp_hdr, 0), hdr);
// test if object header is still the same (i.e. unlocked), and if so, store the
// displaced header address in the object header - if it is not the same, get the
// object header instead
if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
- cmpxchg(disp_hdr, Address(obj, hdr_offset));
+ cmpxchgptr(disp_hdr, Address(obj, hdr_offset));
// if the object header was the same, we're done
if (PrintBiasedLockingStatistics) {
cond_inc32(Assembler::equal,
@@ -76,11 +75,11 @@ int C1_MacroAssembler::lock_object(Regis
//
// assuming both the stack pointer and page_size have their least
// significant 2 bits cleared and page_size is a power of 2
- subl(hdr, rsp);
- andl(hdr, aligned_mask - os::vm_page_size());
+ subptr(hdr, rsp);
+ andptr(hdr, aligned_mask - os::vm_page_size());
// for recursive locking, the result is zero => save it in the displaced header
// location (NULL in the displaced hdr location indicates recursive locking)
- movl(Address(disp_hdr, 0), hdr);
+ movptr(Address(disp_hdr, 0), hdr);
// otherwise we don't care about the result and handle locking via runtime call
jcc(Assembler::notZero, slow_case);
// done
@@ -90,35 +89,34 @@ int C1_MacroAssembler::lock_object(Regis
void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_hdr, Label& slow_case) {
- const int aligned_mask = 3;
+ const int aligned_mask = BytesPerWord -1;
const int hdr_offset = oopDesc::mark_offset_in_bytes();
assert(disp_hdr == rax, "disp_hdr must be rax, for the cmpxchg instruction");
assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
- assert(BytesPerWord == 4, "adjust aligned_mask and code");
Label done;
if (UseBiasedLocking) {
// load object
- movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+ movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
biased_locking_exit(obj, hdr, done);
}
// load displaced header
- movl(hdr, Address(disp_hdr, 0));
+ movptr(hdr, Address(disp_hdr, 0));
// if the loaded hdr is NULL we had recursive locking
- testl(hdr, hdr);
+ testptr(hdr, hdr);
// if we had recursive locking, we are done
jcc(Assembler::zero, done);
if (!UseBiasedLocking) {
// load object
- movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+ movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
}
verify_oop(obj);
// test if object header is pointing to the displaced header, and if so, restore
// the displaced header in the object - if the object header is not pointing to
// the displaced header, get the object header instead
if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
- cmpxchg(hdr, Address(obj, hdr_offset));
+ cmpxchgptr(hdr, Address(obj, hdr_offset));
// if the object header was not pointing to the displaced header,
// we do unlocking via runtime call
jcc(Assembler::notEqual, slow_case);
@@ -141,13 +139,14 @@ void C1_MacroAssembler::initialize_heade
assert_different_registers(obj, klass, len);
if (UseBiasedLocking && !len->is_valid()) {
assert_different_registers(obj, klass, len, t1, t2);
- movl(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- movl(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
- } else {
- movl(Address(obj, oopDesc::mark_offset_in_bytes ()), (int)markOopDesc::prototype());
- }
-
- movl(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
+ movptr(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ movptr(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
+ } else {
+ // This assumes that all prototype bits fit in an int32_t
+ movptr(Address(obj, oopDesc::mark_offset_in_bytes ()), (int32_t)(intptr_t)markOopDesc::prototype());
+ }
+
+ movptr(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
if (len->is_valid()) {
movl(Address(obj, arrayOopDesc::length_offset_in_bytes()), len);
}
@@ -160,25 +159,27 @@ void C1_MacroAssembler::initialize_body(
assert(obj != len_in_bytes && obj != t1 && t1 != len_in_bytes, "registers must be different");
assert((hdr_size_in_bytes & (BytesPerWord - 1)) == 0, "header size is not a multiple of BytesPerWord");
Register index = len_in_bytes;
- subl(index, hdr_size_in_bytes);
+ // index is positive and ptr sized
+ subptr(index, hdr_size_in_bytes);
jcc(Assembler::zero, done);
// initialize topmost word, divide index by 2, check if odd and test if zero
// note: for the remaining code to work, index must be a multiple of BytesPerWord
#ifdef ASSERT
{ Label L;
- testl(index, BytesPerWord - 1);
+ testptr(index, BytesPerWord - 1);
jcc(Assembler::zero, L);
stop("index is not a multiple of BytesPerWord");
bind(L);
}
#endif
- xorl(t1, t1); // use _zero reg to clear memory (shorter code)
+ xorptr(t1, t1); // use _zero reg to clear memory (shorter code)
if (UseIncDec) {
- shrl(index, 3); // divide by 8 and set carry flag if bit 2 was set
- } else {
- shrl(index, 2); // use 2 instructions to avoid partial flag stall
- shrl(index, 1);
- }
+ shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
+ } else {
+ shrptr(index, 2); // use 2 instructions to avoid partial flag stall
+ shrptr(index, 1);
+ }
+#ifndef _LP64
// index could have been not a multiple of 8 (i.e., bit 2 was set)
{ Label even;
// note: if index was a multiple of 8, than it cannot
@@ -186,16 +187,17 @@ void C1_MacroAssembler::initialize_body(
// => if it is even, we don't need to check for 0 again
jcc(Assembler::carryClear, even);
// clear topmost word (no jump needed if conditional assignment would work here)
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
// index could be 0 now, need to check again
jcc(Assembler::zero, done);
bind(even);
}
+#endif // !_LP64
// initialize remaining object fields: rdx is a multiple of 2 now
{ Label loop;
bind(loop);
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
+ NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);)
decrement(index);
jcc(Assembler::notZero, loop);
}
@@ -227,30 +229,30 @@ void C1_MacroAssembler::initialize_objec
const Register index = t2;
const int threshold = 6 * BytesPerWord; // approximate break even point for code size (see comments below)
if (var_size_in_bytes != noreg) {
- movl(index, var_size_in_bytes);
+ mov(index, var_size_in_bytes);
initialize_body(obj, index, hdr_size_in_bytes, t1_zero);
} else if (con_size_in_bytes <= threshold) {
// use explicit null stores
// code size = 2 + 3*n bytes (n = number of fields to clear)
- xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+ xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += BytesPerWord)
- movl(Address(obj, i), t1_zero);
+ movptr(Address(obj, i), t1_zero);
} else if (con_size_in_bytes > hdr_size_in_bytes) {
// use loop to null out the fields
// code size = 16 bytes for even n (n = number of fields to clear)
// initialize last object field first if odd number of fields
- xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
- movl(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
+ xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+ movptr(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
// initialize last object field if constant size is odd
if (((con_size_in_bytes - hdr_size_in_bytes) & 4) != 0)
- movl(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
+ movptr(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
// initialize remaining object fields: rdx is a multiple of 2
{ Label loop;
bind(loop);
- movl(Address(obj, index, Address::times_8,
- hdr_size_in_bytes - (1*BytesPerWord)), t1_zero);
- movl(Address(obj, index, Address::times_8,
- hdr_size_in_bytes - (2*BytesPerWord)), t1_zero);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (1*BytesPerWord)),
+ t1_zero);
+ NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)),
+ t1_zero);)
decrement(index);
jcc(Assembler::notZero, loop);
}
@@ -269,17 +271,17 @@ void C1_MacroAssembler::allocate_array(R
assert_different_registers(obj, len, t1, t2, klass);
// determine alignment mask
- assert(BytesPerWord == 4, "must be a multiple of 2 for masking code to work");
+ assert(!(BytesPerWord & 1), "must be a multiple of 2 for masking code to work");
// check for negative or excessive length
- cmpl(len, max_array_allocation_length);
+ cmpptr(len, (int32_t)max_array_allocation_length);
jcc(Assembler::above, slow_case);
const Register arr_size = t2; // okay to be the same
// align object end
- movl(arr_size, header_size * BytesPerWord + MinObjAlignmentInBytesMask);
- leal(arr_size, Address(arr_size, len, f));
- andl(arr_size, ~MinObjAlignmentInBytesMask);
+ movptr(arr_size, (int32_t)header_size * BytesPerWord + MinObjAlignmentInBytesMask);
+ lea(arr_size, Address(arr_size, len, f));
+ andptr(arr_size, ~MinObjAlignmentInBytesMask);
try_allocate(obj, arr_size, 0, t1, t2, slow_case);
@@ -305,12 +307,13 @@ void C1_MacroAssembler::inline_cache_che
// check against inline cache
assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), "must add explicit null check");
int start_offset = offset();
- cmpl(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
+ cmpptr(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
// if icache check fails, then jump to runtime routine
// Note: RECEIVER must still contain the receiver!
jump_cc(Assembler::notEqual,
RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
- assert(offset() - start_offset == 9, "check alignment in emit_method_entry");
+ const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
+ assert(offset() - start_offset == ic_cmp_size, "check alignment in emit_method_entry");
}
@@ -364,7 +367,7 @@ void C1_MacroAssembler::verify_not_null_
void C1_MacroAssembler::verify_not_null_oop(Register r) {
if (!VerifyOops) return;
Label not_null;
- testl(r, r);
+ testptr(r, r);
jcc(Assembler::notZero, not_null);
stop("non-null oop required");
bind(not_null);
@@ -373,12 +376,12 @@ void C1_MacroAssembler::verify_not_null_
void C1_MacroAssembler::invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) {
#ifdef ASSERT
- if (inv_rax) movl(rax, 0xDEAD);
- if (inv_rbx) movl(rbx, 0xDEAD);
- if (inv_rcx) movl(rcx, 0xDEAD);
- if (inv_rdx) movl(rdx, 0xDEAD);
- if (inv_rsi) movl(rsi, 0xDEAD);
- if (inv_rdi) movl(rdi, 0xDEAD);
+ if (inv_rax) movptr(rax, 0xDEAD);
+ if (inv_rbx) movptr(rbx, 0xDEAD);
+ if (inv_rcx) movptr(rcx, 0xDEAD);
+ if (inv_rdx) movptr(rdx, 0xDEAD);
+ if (inv_rsi) movptr(rsi, 0xDEAD);
+ if (inv_rdi) movptr(rdi, 0xDEAD);
#endif
}
--- a/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp Thu Sep 04 18:40:43 2008 -0700
@@ -94,16 +94,17 @@
// Note: NEVER push values directly, but only through following push_xxx functions;
// This helps us to track the rsp changes compared to the entry rsp (->_rsp_offset)
- void push_jint (jint i) { _rsp_offset++; pushl(i); }
+ void push_jint (jint i) { _rsp_offset++; push(i); }
void push_oop (jobject o) { _rsp_offset++; pushoop(o); }
- void push_addr (Address a) { _rsp_offset++; pushl(a); }
- void push_reg (Register r) { _rsp_offset++; pushl(r); }
- void pop (Register r) { _rsp_offset--; popl (r); assert(_rsp_offset >= 0, "stack offset underflow"); }
+ // Seems to always be in wordSize
+ void push_addr (Address a) { _rsp_offset++; pushptr(a); }
+ void push_reg (Register r) { _rsp_offset++; push(r); }
+ void pop_reg (Register r) { _rsp_offset--; pop(r); assert(_rsp_offset >= 0, "stack offset underflow"); }
void dec_stack (int nof_words) {
_rsp_offset -= nof_words;
assert(_rsp_offset >= 0, "stack offset underflow");
- addl(rsp, wordSize * nof_words);
+ addptr(rsp, wordSize * nof_words);
}
void dec_stack_after_call (int nof_words) {
--- a/src/cpu/x86/vm/c1_Runtime1_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/c1_Runtime1_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -30,52 +30,58 @@
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, int args_size) {
// setup registers
- const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
assert(!(oop_result1->is_valid() || oop_result2->is_valid()) || oop_result1 != oop_result2, "registers must be different");
assert(oop_result1 != thread && oop_result2 != thread, "registers must be different");
assert(args_size >= 0, "illegal args_size");
+#ifdef _LP64
+ mov(c_rarg0, thread);
+ set_num_rt_args(0); // Nothing on stack
+#else
set_num_rt_args(1 + args_size);
// push java thread (becomes first argument of C function)
get_thread(thread);
- pushl(thread);
+ push(thread);
+#endif // _LP64
set_last_Java_frame(thread, noreg, rbp, NULL);
+
// do the call
call(RuntimeAddress(entry));
int call_offset = offset();
// verify callee-saved register
#ifdef ASSERT
guarantee(thread != rax, "change this code");
- pushl(rax);
+ push(rax);
{ Label L;
get_thread(rax);
- cmpl(thread, rax);
+ cmpptr(thread, rax);
jcc(Assembler::equal, L);
int3();
stop("StubAssembler::call_RT: rdi not callee saved?");
bind(L);
}
- popl(rax);
+ pop(rax);
#endif
reset_last_Java_frame(thread, true, false);
// discard thread and arguments
- addl(rsp, (1 + args_size)*BytesPerWord);
+ NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
// check for pending exceptions
{ Label L;
- cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
jcc(Assembler::equal, L);
// exception pending => remove activation and forward to exception handler
- movl(rax, Address(thread, Thread::pending_exception_offset()));
+ movptr(rax, Address(thread, Thread::pending_exception_offset()));
// make sure that the vm_results are cleared
if (oop_result1->is_valid()) {
- movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
}
if (oop_result2->is_valid()) {
- movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
}
if (frame_size() == no_frame_size) {
leave();
@@ -89,13 +95,13 @@ int StubAssembler::call_RT(Register oop_
}
// get oop results if there are any and reset the values in the thread
if (oop_result1->is_valid()) {
- movl(oop_result1, Address(thread, JavaThread::vm_result_offset()));
- movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+ movptr(oop_result1, Address(thread, JavaThread::vm_result_offset()));
+ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
verify_oop(oop_result1);
}
if (oop_result2->is_valid()) {
- movl(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
- movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ movptr(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
+ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
verify_oop(oop_result2);
}
return call_offset;
@@ -103,22 +109,58 @@ int StubAssembler::call_RT(Register oop_
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {
- pushl(arg1);
+#ifdef _LP64
+ mov(c_rarg1, arg1);
+#else
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 1);
}
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {
- pushl(arg2);
- pushl(arg1);
+#ifdef _LP64
+ if (c_rarg1 == arg2) {
+ if (c_rarg2 == arg1) {
+ xchgq(arg1, arg2);
+ } else {
+ mov(c_rarg2, arg2);
+ mov(c_rarg1, arg1);
+ }
+ } else {
+ mov(c_rarg1, arg1);
+ mov(c_rarg2, arg2);
+ }
+#else
+ push(arg2);
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 2);
}
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {
- pushl(arg3);
- pushl(arg2);
- pushl(arg1);
+#ifdef _LP64
+ // if there is any conflict use the stack
+ if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
+ arg2 == c_rarg1 || arg1 == c_rarg3 ||
+ arg3 == c_rarg1 || arg1 == c_rarg2) {
+ push(arg3);
+ push(arg2);
+ push(arg1);
+ pop(c_rarg1);
+ pop(c_rarg2);
+ pop(c_rarg3);
+ } else {
+ mov(c_rarg1, arg1);
+ mov(c_rarg2, arg2);
+ mov(c_rarg3, arg3);
+ }
+#else
+ push(arg3);
+ push(arg2);
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 3);
}
@@ -154,7 +196,7 @@ void StubFrame::load_argument(int offset
// + 3: argument with offset 1
// + 4: ...
- __ movl(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
+ __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
}
@@ -170,8 +212,8 @@ StubFrame::~StubFrame() {
#define __ sasm->
-const int float_regs_as_doubles_size_in_words = 16;
-const int xmm_regs_as_doubles_size_in_words = 16;
+const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
+const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
// Stack layout for saving/restoring all the registers needed during a runtime
// call (this includes deoptimization)
@@ -180,29 +222,61 @@ const int xmm_regs_as_doubles_size_in_wo
// but the code in save_live_registers will take the argument count into
// account.
//
+#ifdef _LP64
+ #define SLOT2(x) x,
+ #define SLOT_PER_WORD 2
+#else
+ #define SLOT2(x)
+ #define SLOT_PER_WORD 1
+#endif // _LP64
+
enum reg_save_layout {
- dummy1,
- dummy2,
+ // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
+ // happen and will assert if the stack size we create is misaligned
+#ifdef _LP64
+ align_dummy_0, align_dummy_1,
+#endif // _LP64
+ dummy1, SLOT2(dummy1H) // 0, 4
+ dummy2, SLOT2(dummy2H) // 8, 12
// Two temps to be used as needed by users of save/restore callee registers
- temp_2_off,
- temp_1_off,
- xmm_regs_as_doubles_off,
- float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_words,
- fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_words,
- fpu_state_end_off = fpu_state_off + FPUStateSizeInWords,
- marker = fpu_state_end_off,
- extra_space_offset,
+ temp_2_off, SLOT2(temp_2H_off) // 16, 20
+ temp_1_off, SLOT2(temp_1H_off) // 24, 28
+ xmm_regs_as_doubles_off, // 32
+ float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
+ fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
+ // fpu_state_end_off is exclusive
+ fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
+ marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
+ extra_space_offset, // 360
+#ifdef _LP64
+ r15_off = extra_space_offset, r15H_off, // 360, 364
+ r14_off, r14H_off, // 368, 372
+ r13_off, r13H_off, // 376, 380
+ r12_off, r12H_off, // 384, 388
+ r11_off, r11H_off, // 392, 396
+ r10_off, r10H_off, // 400, 404
+ r9_off, r9H_off, // 408, 412
+ r8_off, r8H_off, // 416, 420
+ rdi_off, rdiH_off, // 424, 428
+#else
rdi_off = extra_space_offset,
- rsi_off,
- rbp_off,
- rsp_off,
- rbx_off,
- rdx_off,
- rcx_off,
- rax_off,
- saved_rbp_off,
- return_off,
- reg_save_frame_size, // As noted: neglects any parameters to runtime
+#endif // _LP64
+ rsi_off, SLOT2(rsiH_off) // 432, 436
+ rbp_off, SLOT2(rbpH_off) // 440, 444
+ rsp_off, SLOT2(rspH_off) // 448, 452
+ rbx_off, SLOT2(rbxH_off) // 456, 460
+ rdx_off, SLOT2(rdxH_off) // 464, 468
+ rcx_off, SLOT2(rcxH_off) // 472, 476
+ rax_off, SLOT2(raxH_off) // 480, 484
+ saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
+ return_off, SLOT2(returnH_off) // 496, 500
+ reg_save_frame_size, // As noted: neglects any parameters to runtime // 504
+
+#ifdef _WIN64
+ c_rarg0_off = rcx_off,
+#else
+ c_rarg0_off = rdi_off,
+#endif // WIN64
// equates
@@ -229,18 +303,49 @@ enum reg_save_layout {
static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
bool save_fpu_registers = true) {
- int frame_size = reg_save_frame_size + num_rt_args; // args + thread
- sasm->set_frame_size(frame_size);
+
+ // In 64bit all the args are in regs so there are no additional stack slots
+ LP64_ONLY(num_rt_args = 0);
+ LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
+ int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
+ sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
// record saved value locations in an OopMap
// locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
- OopMap* map = new OopMap(frame_size, 0);
+ OopMap* map = new OopMap(frame_size_in_slots, 0);
map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
+#ifdef _LP64
+ map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
+
+ // This is stupid but needed.
+ map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
+
+ map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
+#endif // _LP64
if (save_fpu_registers) {
if (UseSSE < 2) {
@@ -288,30 +393,31 @@ static OopMap* save_live_registers(StubA
bool save_fpu_registers = true) {
__ block_comment("save_live_registers");
- int frame_size = reg_save_frame_size + num_rt_args; // args + thread
+ // 64bit passes the args in regs to the c++ runtime
+ int frame_size_in_slots = reg_save_frame_size NOT_LP64(+ num_rt_args); // args + thread
// frame_size = round_to(frame_size, 4);
- sasm->set_frame_size(frame_size);
-
- __ pushad(); // integer registers
+ sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
+
+ __ pusha(); // integer registers
// assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
// assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
- __ subl(rsp, extra_space_offset * wordSize);
+ __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
#ifdef ASSERT
- __ movl(Address(rsp, marker * wordSize), 0xfeedbeef);
+ __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
#endif
if (save_fpu_registers) {
if (UseSSE < 2) {
// save FPU stack
- __ fnsave(Address(rsp, fpu_state_off * wordSize));
+ __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
__ fwait();
#ifdef ASSERT
Label ok;
- __ cmpw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
+ __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
__ jccb(Assembler::equal, ok);
__ stop("corrupted control word detected");
__ bind(ok);
@@ -321,18 +427,18 @@ static OopMap* save_live_registers(StubA
// since fstp_d can cause FPU stack underflow exceptions. Write it
// into the on stack copy and then reload that to make sure that the
// current and future values are correct.
- __ movw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
- __ frstor(Address(rsp, fpu_state_off * wordSize));
+ __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
+ __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
// Save the FPU registers in de-opt-able form
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 0));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 8));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 16));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 24));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 32));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 40));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 48));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 56));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
}
if (UseSSE >= 2) {
@@ -341,24 +447,34 @@ static OopMap* save_live_registers(StubA
// so always save them as doubles.
// note that float values are _not_ converted automatically, so for float values
// the second word contains only garbage data.
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 0), xmm0);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 8), xmm1);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
+#ifdef _LP64
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
+#endif // _LP64
} else if (UseSSE == 1) {
// save XMM registers as float because double not supported without SSE2
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 0), xmm0);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 8), xmm1);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
}
}
@@ -373,28 +489,38 @@ static void restore_fpu(StubAssembler* s
if (restore_fpu_registers) {
if (UseSSE >= 2) {
// restore XMM registers
- __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize + 0));
- __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize + 8));
- __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
- __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
- __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
- __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
- __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
- __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+ __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
+#ifdef _LP64
+ __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
+ __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
+ __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
+ __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
+ __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
+ __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
+ __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
+ __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
+#endif // _LP64
} else if (UseSSE == 1) {
// restore XMM registers
- __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize + 0));
- __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize + 8));
- __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
- __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
- __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
- __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
- __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
- __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+ __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
}
if (UseSSE < 2) {
- __ frstor(Address(rsp, fpu_state_off * wordSize));
+ __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
} else {
// check that FPU stack is really empty
__ verify_FPU(0, "restore_live_registers");
@@ -408,14 +534,14 @@ static void restore_fpu(StubAssembler* s
#ifdef ASSERT
{
Label ok;
- __ cmpl(Address(rsp, marker * wordSize), 0xfeedbeef);
+ __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
__ jcc(Assembler::equal, ok);
__ stop("bad offsets in frame");
__ bind(ok);
}
-#endif
-
- __ addl(rsp, extra_space_offset * wordSize);
+#endif // ASSERT
+
+ __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
}
@@ -423,7 +549,7 @@ static void restore_live_registers(StubA
__ block_comment("restore_live_registers");
restore_fpu(sasm, restore_fpu_registers);
- __ popad();
+ __ popa();
}
@@ -432,14 +558,35 @@ static void restore_live_registers_excep
restore_fpu(sasm, restore_fpu_registers);
- __ popl(rdi);
- __ popl(rsi);
- __ popl(rbp);
- __ popl(rbx); // skip this value
- __ popl(rbx);
- __ popl(rdx);
- __ popl(rcx);
- __ addl(rsp, 4);
+#ifdef _LP64
+ __ movptr(r15, Address(rsp, 0));
+ __ movptr(r14, Address(rsp, wordSize));
+ __ movptr(r13, Address(rsp, 2 * wordSize));
+ __ movptr(r12, Address(rsp, 3 * wordSize));
+ __ movptr(r11, Address(rsp, 4 * wordSize));
+ __ movptr(r10, Address(rsp, 5 * wordSize));
+ __ movptr(r9, Address(rsp, 6 * wordSize));
+ __ movptr(r8, Address(rsp, 7 * wordSize));
+ __ movptr(rdi, Address(rsp, 8 * wordSize));
+ __ movptr(rsi, Address(rsp, 9 * wordSize));
+ __ movptr(rbp, Address(rsp, 10 * wordSize));
+ // skip rsp
+ __ movptr(rbx, Address(rsp, 12 * wordSize));
+ __ movptr(rdx, Address(rsp, 13 * wordSize));
+ __ movptr(rcx, Address(rsp, 14 * wordSize));
+
+ __ addptr(rsp, 16 * wordSize);
+#else
+
+ __ pop(rdi);
+ __ pop(rsi);
+ __ pop(rbp);
+ __ pop(rbx); // skip this value
+ __ pop(rbx);
+ __ pop(rdx);
+ __ pop(rcx);
+ __ addptr(rsp, BytesPerWord);
+#endif // _LP64
}
@@ -465,10 +612,13 @@ OopMapSet* Runtime1::generate_exception_
// load argument for exception that is passed as an argument into the stub
if (has_argument) {
- __ movl(temp_reg, Address(rbp, 2*BytesPerWord));
- __ pushl(temp_reg);
+#ifdef _LP64
+ __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
+#else
+ __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
+ __ push(temp_reg);
+#endif // _LP64
}
-
int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
OopMapSet* oop_maps = new OopMapSet();
@@ -486,7 +636,7 @@ void Runtime1::generate_handle_exception
const Register exception_pc = rdx;
// other registers used in this stub
const Register real_return_addr = rbx;
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
__ block_comment("generate_handle_exception");
@@ -503,19 +653,19 @@ void Runtime1::generate_handle_exception
__ verify_not_null_oop(exception_oop);
// load address of JavaThread object for thread-local data
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are
// empty before writing to them
Label oop_empty;
- __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop already set");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc already set");
__ bind(pc_empty);
@@ -523,15 +673,15 @@ void Runtime1::generate_handle_exception
// save exception oop and issuing pc into JavaThread
// (exception handler will load it from here)
- __ movl(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
// save real return address (pc that called this stub)
- __ movl(real_return_addr, Address(rbp, 1*BytesPerWord));
- __ movl(Address(rsp, temp_1_off * BytesPerWord), real_return_addr);
+ __ movptr(real_return_addr, Address(rbp, 1*BytesPerWord));
+ __ movptr(Address(rsp, temp_1_off * VMRegImpl::stack_slot_size), real_return_addr);
// patch throwing pc into return address (has bci & oop map)
- __ movl(Address(rbp, 1*BytesPerWord), exception_pc);
+ __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
// compute the exception handler.
// the exception oop and the throwing pc are read from the fields in JavaThread
@@ -548,12 +698,12 @@ void Runtime1::generate_handle_exception
// Do we have an exception handler in the nmethod?
Label no_handler;
Label done;
- __ testl(rax, rax);
+ __ testptr(rax, rax);
__ jcc(Assembler::zero, no_handler);
// exception handler found
// patch the return address -> the stub will directly return to the exception handler
- __ movl(Address(rbp, 1*BytesPerWord), rax);
+ __ movptr(Address(rbp, 1*BytesPerWord), rax);
// restore registers
restore_live_registers(sasm, save_fpu_registers);
@@ -568,18 +718,18 @@ void Runtime1::generate_handle_exception
// there is no need to restore the registers
// restore the real return address that was saved before the RT-call
- __ movl(real_return_addr, Address(rsp, temp_1_off * BytesPerWord));
- __ movl(Address(rbp, 1*BytesPerWord), real_return_addr);
+ __ movptr(real_return_addr, Address(rsp, temp_1_off * VMRegImpl::stack_slot_size));
+ __ movptr(Address(rbp, 1*BytesPerWord), real_return_addr);
// load address of JavaThread object for thread-local data
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
// restore exception oop into rax, (convention for unwind code)
- __ movl(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
+ __ movptr(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
// clear exception fields in JavaThread because they are no longer needed
// (fields must be cleared because they are processed by GC otherwise)
- __ movl(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
// pop the stub frame off
__ leave();
@@ -595,22 +745,22 @@ void Runtime1::generate_unwind_exception
// other registers used in this stub
const Register exception_pc = rdx;
const Register handler_addr = rbx;
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
// verify that only rax, is valid at this time
__ invalidate_registers(false, true, true, true, true, true);
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are empty
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
Label oop_empty;
- __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop must be empty");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc must be empty");
__ bind(pc_empty);
@@ -622,12 +772,12 @@ void Runtime1::generate_unwind_exception
// leave activation of nmethod
__ leave();
// store return address (is on top of stack after leave)
- __ movl(exception_pc, Address(rsp, 0));
+ __ movptr(exception_pc, Address(rsp, 0));
__ verify_oop(exception_oop);
// save exception oop from rax, to stack before call
- __ pushl(exception_oop);
+ __ push(exception_oop);
// search the exception handler address of the caller (using the return address)
__ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), exception_pc);
@@ -637,17 +787,17 @@ void Runtime1::generate_unwind_exception
__ invalidate_registers(false, true, true, true, true, true);
// move result of call into correct register
- __ movl(handler_addr, rax);
+ __ movptr(handler_addr, rax);
// restore exception oop in rax, (required convention of exception handler)
- __ popl(exception_oop);
+ __ pop(exception_oop);
__ verify_oop(exception_oop);
// get throwing pc (= return address).
// rdx has been destroyed by the call, so it must be set again
// the pop is also necessary to simulate the effect of a ret(0)
- __ popl(exception_pc);
+ __ pop(exception_pc);
// verify that that there is really a valid exception in rax,
__ verify_not_null_oop(exception_oop);
@@ -677,12 +827,18 @@ OopMapSet* Runtime1::generate_patching(S
OopMap* oop_map = save_live_registers(sasm, num_rt_args);
- __ pushl(rax); // push dummy
+#ifdef _LP64
+ const Register thread = r15_thread;
+ // No need to worry about dummy
+ __ mov(c_rarg0, thread);
+#else
+ __ push(rax); // push dummy
const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
// push java thread (becomes first argument of C function)
__ get_thread(thread);
- __ pushl(thread);
+ __ push(thread);
+#endif // _LP64
__ set_last_Java_frame(thread, noreg, rbp, NULL);
// do the call
__ call(RuntimeAddress(target));
@@ -691,27 +847,29 @@ OopMapSet* Runtime1::generate_patching(S
// verify callee-saved register
#ifdef ASSERT
guarantee(thread != rax, "change this code");
- __ pushl(rax);
+ __ push(rax);
{ Label L;
__ get_thread(rax);
- __ cmpl(thread, rax);
+ __ cmpptr(thread, rax);
__ jcc(Assembler::equal, L);
- __ stop("StubAssembler::call_RT: rdi not callee saved?");
+ __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
__ bind(L);
}
- __ popl(rax);
+ __ pop(rax);
#endif
__ reset_last_Java_frame(thread, true, false);
- __ popl(rcx); // discard thread arg
- __ popl(rcx); // discard dummy
+#ifndef _LP64
+ __ pop(rcx); // discard thread arg
+ __ pop(rcx); // discard dummy
+#endif // _LP64
// check for pending exceptions
{ Label L;
- __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, L);
// exception pending => remove activation and forward to exception handler
- __ testl(rax, rax); // have we deoptimized?
+ __ testptr(rax, rax); // have we deoptimized?
__ jump_cc(Assembler::equal,
RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
@@ -719,38 +877,38 @@ OopMapSet* Runtime1::generate_patching(S
// JavaThread, so copy and clear pending exception.
// load and clear pending exception
- __ movl(rax, Address(thread, Thread::pending_exception_offset()));
- __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
+ __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
// check that there is really a valid exception
__ verify_not_null_oop(rax);
// load throwing pc: this is the return address of the stub
- __ movl(rdx, Address(rsp, return_off * BytesPerWord));
+ __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are empty
Label oop_empty;
- __ cmpoop(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop must be empty");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc must be empty");
__ bind(pc_empty);
#endif
// store exception oop and throwing pc to JavaThread
- __ movl(Address(thread, JavaThread::exception_oop_offset()), rax);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), rdx);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
restore_live_registers(sasm);
__ leave();
- __ addl(rsp, 4); // remove return address from stack
+ __ addptr(rsp, BytesPerWord); // remove return address from stack
// Forward the exception directly to deopt blob. We can blow no
// registers and must leave throwing pc on the stack. A patch may
@@ -767,7 +925,7 @@ OopMapSet* Runtime1::generate_patching(S
Label reexecuteEntry, cont;
- __ testl(rax, rax); // have we deoptimized?
+ __ testptr(rax, rax); // have we deoptimized?
__ jcc(Assembler::equal, cont); // no
// Will reexecute. Proper return address is already on the stack we just restore
@@ -806,21 +964,21 @@ OopMapSet* Runtime1::generate_code_for(S
// dispatch to the handler if found. Otherwise unwind and
// dispatch to the callers exception handler.
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
const Register exception_oop = rax;
const Register exception_pc = rdx;
// load pending exception oop into rax,
- __ movl(exception_oop, Address(thread, Thread::pending_exception_offset()));
+ __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
// clear pending exception
- __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
// load issuing PC (the return address for this stub) into rdx
- __ movl(exception_pc, Address(rbp, 1*BytesPerWord));
+ __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
// make sure that the vm_results are cleared (may be unnecessary)
- __ movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
- __ movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ __ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+ __ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
// verify that that there is really a valid exception in rax,
__ verify_not_null_oop(exception_oop);
@@ -857,8 +1015,8 @@ OopMapSet* Runtime1::generate_code_for(S
Register t2 = rsi;
assert_different_registers(klass, obj, obj_size, t1, t2);
- __ pushl(rdi);
- __ pushl(rbx);
+ __ push(rdi);
+ __ push(rbx);
if (id == fast_new_instance_init_check_id) {
// make sure the klass is initialized
@@ -889,28 +1047,28 @@ OopMapSet* Runtime1::generate_code_for(S
__ bind(retry_tlab);
- // get the instance size
+ // get the instance size (size is postive so movl is fine for 64bit)
__ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
__ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
__ initialize_object(obj, klass, obj_size, 0, t1, t2);
__ verify_oop(obj);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
__ ret(0);
__ bind(try_eden);
- // get the instance size
+ // get the instance size (size is postive so movl is fine for 64bit)
__ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
__ eden_allocate(obj, obj_size, 0, t1, slow_path);
__ initialize_object(obj, klass, obj_size, 0, t1, t2);
__ verify_oop(obj);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
__ ret(0);
__ bind(slow_path);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
}
__ enter();
@@ -996,15 +1154,17 @@ OopMapSet* Runtime1::generate_code_for(S
__ bind(retry_tlab);
// get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+ // since size is postive movl does right thing on 64bit
__ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
__ movl(arr_size, length);
assert(t1 == rcx, "fixed register usage");
- __ shll(arr_size /* by t1=rcx, mod 32 */);
- __ shrl(t1, Klass::_lh_header_size_shift);
- __ andl(t1, Klass::_lh_header_size_mask);
- __ addl(arr_size, t1);
- __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
- __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+ __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+ __ shrptr(t1, Klass::_lh_header_size_shift);
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ addptr(arr_size, t1);
+ __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+ __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
__ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
@@ -1012,24 +1172,26 @@ OopMapSet* Runtime1::generate_code_for(S
__ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
- __ andl(t1, Klass::_lh_header_size_mask);
- __ subl(arr_size, t1); // body length
- __ addl(t1, obj); // body start
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ subptr(arr_size, t1); // body length
+ __ addptr(t1, obj); // body start
__ initialize_body(t1, arr_size, 0, t2);
__ verify_oop(obj);
__ ret(0);
__ bind(try_eden);
// get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+ // since size is postive movl does right thing on 64bit
__ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
__ movl(arr_size, length);
assert(t1 == rcx, "fixed register usage");
- __ shll(arr_size /* by t1=rcx, mod 32 */);
- __ shrl(t1, Klass::_lh_header_size_shift);
- __ andl(t1, Klass::_lh_header_size_mask);
- __ addl(arr_size, t1);
- __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
- __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+ __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+ __ shrptr(t1, Klass::_lh_header_size_shift);
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ addptr(arr_size, t1);
+ __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+ __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
__ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
@@ -1037,9 +1199,9 @@ OopMapSet* Runtime1::generate_code_for(S
__ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
- __ andl(t1, Klass::_lh_header_size_mask);
- __ subl(arr_size, t1); // body length
- __ addl(t1, obj); // body start
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ subptr(arr_size, t1); // body length
+ __ addptr(t1, obj); // body start
__ initialize_body(t1, arr_size, 0, t2);
__ verify_oop(obj);
__ ret(0);
@@ -1089,15 +1251,23 @@ OopMapSet* Runtime1::generate_code_for(S
{
__ set_info("register_finalizer", dont_gc_arguments);
+ // This is called via call_runtime so the arguments
+ // will be place in C abi locations
+
+#ifdef _LP64
+ __ verify_oop(c_rarg0);
+ __ mov(rax, c_rarg0);
+#else
// The object is passed on the stack and we haven't pushed a
// frame yet so it's one work away from top of stack.
- __ movl(rax, Address(rsp, 1 * BytesPerWord));
+ __ movptr(rax, Address(rsp, 1 * BytesPerWord));
__ verify_oop(rax);
+#endif // _LP64
// load the klass and check the has finalizer flag
Label register_finalizer;
Register t = rsi;
- __ movl(t, Address(rax, oopDesc::klass_offset_in_bytes()));
+ __ movptr(t, Address(rax, oopDesc::klass_offset_in_bytes()));
__ movl(t, Address(t, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc)));
__ testl(t, JVM_ACC_HAS_FINALIZER);
__ jcc(Assembler::notZero, register_finalizer);
@@ -1185,46 +1355,49 @@ OopMapSet* Runtime1::generate_code_for(S
case slow_subtype_check_id:
{
enum layout {
- rax_off,
- rcx_off,
- rsi_off,
- rdi_off,
- saved_rbp_off,
- return_off,
- sub_off,
- super_off,
+ rax_off, SLOT2(raxH_off)
+ rcx_off, SLOT2(rcxH_off)
+ rsi_off, SLOT2(rsiH_off)
+ rdi_off, SLOT2(rdiH_off)
+ // saved_rbp_off, SLOT2(saved_rbpH_off)
+ return_off, SLOT2(returnH_off)
+ sub_off, SLOT2(subH_off)
+ super_off, SLOT2(superH_off)
framesize
};
__ set_info("slow_subtype_check", dont_gc_arguments);
- __ pushl(rdi);
- __ pushl(rsi);
- __ pushl(rcx);
- __ pushl(rax);
- __ movl(rsi, Address(rsp, (super_off - 1) * BytesPerWord)); // super
- __ movl(rax, Address(rsp, (sub_off - 1) * BytesPerWord)); // sub
-
- __ movl(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
- __ movl(rcx,Address(rdi,arrayOopDesc::length_offset_in_bytes()));
- __ addl(rdi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+ __ push(rdi);
+ __ push(rsi);
+ __ push(rcx);
+ __ push(rax);
+
+ // This is called by pushing args and not with C abi
+ __ movptr(rsi, Address(rsp, (super_off) * VMRegImpl::stack_slot_size)); // super
+ __ movptr(rax, Address(rsp, (sub_off ) * VMRegImpl::stack_slot_size)); // sub
+
+ __ movptr(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
+ __ movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
+ __ addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
Label miss;
__ repne_scan();
__ jcc(Assembler::notEqual, miss);
- __ movl(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
- __ movl(Address(rsp, (super_off - 1) * BytesPerWord), 1); // result
- __ popl(rax);
- __ popl(rcx);
- __ popl(rsi);
- __ popl(rdi);
+ __ movptr(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
+ __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 1); // result
+ __ pop(rax);
+ __ pop(rcx);
+ __ pop(rsi);
+ __ pop(rdi);
__ ret(0);
__ bind(miss);
- __ movl(Address(rsp, (super_off - 1) * BytesPerWord), 0); // result
- __ popl(rax);
- __ popl(rcx);
- __ popl(rsi);
- __ popl(rdi);
+ __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 0); // result
+ __ pop(rax);
+ __ pop(rcx);
+ __ pop(rsi);
+ __ pop(rdi);
__ ret(0);
}
break;
@@ -1237,6 +1410,8 @@ OopMapSet* Runtime1::generate_code_for(S
StubFrame f(sasm, "monitorenter", dont_gc_arguments);
OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
+ // Called with store_parameter and not C abi
+
f.load_argument(1, rax); // rax,: object
f.load_argument(0, rbx); // rbx,: lock address
@@ -1255,6 +1430,8 @@ OopMapSet* Runtime1::generate_code_for(S
{
StubFrame f(sasm, "monitorexit", dont_gc_arguments);
OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
+
+ // Called with store_parameter and not C abi
f.load_argument(0, rax); // rax,: lock address
@@ -1304,9 +1481,9 @@ OopMapSet* Runtime1::generate_code_for(S
// the live registers get saved.
save_live_registers(sasm, 1);
- __ pushl(rax);
+ __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
- __ popl(rax);
+ NOT_LP64(__ pop(rax));
restore_live_registers(sasm);
}
@@ -1316,18 +1493,19 @@ OopMapSet* Runtime1::generate_code_for(S
{
// rax, and rdx are destroyed, but should be free since the result is returned there
// preserve rsi,ecx
- __ pushl(rsi);
- __ pushl(rcx);
+ __ push(rsi);
+ __ push(rcx);
+ LP64_ONLY(__ push(rdx);)
// check for NaN
Label return0, do_return, return_min_jlong, do_convert;
- Address value_high_word(rsp, 8);
- Address value_low_word(rsp, 4);
- Address result_high_word(rsp, 16);
- Address result_low_word(rsp, 12);
-
- __ subl(rsp, 20);
+ Address value_high_word(rsp, wordSize + 4);
+ Address value_low_word(rsp, wordSize);
+ Address result_high_word(rsp, 3*wordSize + 4);
+ Address result_low_word(rsp, 3*wordSize);
+
+ __ subptr(rsp, 32); // more than enough on 32bit
__ fst_d(value_low_word);
__ movl(rax, value_high_word);
__ andl(rax, 0x7ff00000);
@@ -1340,7 +1518,7 @@ OopMapSet* Runtime1::generate_code_for(S
__ bind(do_convert);
__ fnstcw(Address(rsp, 0));
- __ movzxw(rax, Address(rsp, 0));
+ __ movzwl(rax, Address(rsp, 0));
__ orl(rax, 0xc00);
__ movw(Address(rsp, 2), rax);
__ fldcw(Address(rsp, 2));
@@ -1348,9 +1526,11 @@ OopMapSet* Runtime1::generate_code_for(S
__ fistp_d(result_low_word);
__ fldcw(Address(rsp, 0));
__ fwait();
- __ movl(rax, result_low_word);
+ // This gets the entire long in rax on 64bit
+ __ movptr(rax, result_low_word);
+ // testing of high bits
__ movl(rdx, result_high_word);
- __ movl(rcx, rax);
+ __ mov(rcx, rax);
// What the heck is the point of the next instruction???
__ xorl(rcx, 0x0);
__ movl(rsi, 0x80000000);
@@ -1360,34 +1540,52 @@ OopMapSet* Runtime1::generate_code_for(S
__ fldz();
__ fcomp_d(value_low_word);
__ fnstsw_ax();
+#ifdef _LP64
+ __ testl(rax, 0x4100); // ZF & CF == 0
+ __ jcc(Assembler::equal, return_min_jlong);
+#else
__ sahf();
__ jcc(Assembler::above, return_min_jlong);
+#endif // _LP64
// return max_jlong
+#ifndef _LP64
__ movl(rdx, 0x7fffffff);
__ movl(rax, 0xffffffff);
+#else
+ __ mov64(rax, CONST64(0x7fffffffffffffff));
+#endif // _LP64
__ jmp(do_return);
__ bind(return_min_jlong);
+#ifndef _LP64
__ movl(rdx, 0x80000000);
__ xorl(rax, rax);
+#else
+ __ mov64(rax, CONST64(0x8000000000000000));
+#endif // _LP64
__ jmp(do_return);
__ bind(return0);
__ fpop();
- __ xorl(rdx,rdx);
- __ xorl(rax,rax);
+#ifndef _LP64
+ __ xorptr(rdx,rdx);
+ __ xorptr(rax,rax);
+#else
+ __ xorptr(rax, rax);
+#endif // _LP64
__ bind(do_return);
- __ addl(rsp, 20);
- __ popl(rcx);
- __ popl(rsi);
+ __ addptr(rsp, 32);
+ LP64_ONLY(__ pop(rdx);)
+ __ pop(rcx);
+ __ pop(rsi);
__ ret(0);
}
break;
default:
{ StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
- __ movl(rax, (int)id);
+ __ movptr(rax, (int)id);
__ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
__ should_not_reach_here();
}
--- a/src/cpu/x86/vm/cppInterpreter_x86.cpp Thu Sep 04 18:40:08 2008 -0700
+++ b/src/cpu/x86/vm/cppInterpreter_x86.cpp Thu Sep 04 18:40:43 2008 -0700
@@ -44,6 +44,14 @@ Label fast_accessor_slow_entry_path; //
Label fast_accessor_slow_entry_path; // fast accessor methods need to be able to jmp to unsynchronized
// c++ interpreter entry point this holds that entry point label.
+// default registers for state and sender_sp
+// state and sender_sp are the same on 32bit because we have no choice.
+// state could be rsi on 64bit but it is an arg reg and not callee save
+// so r13 is better choice.
+
+const Register state = NOT_LP64(rsi) LP64_ONLY(r13);
+const Register sender_sp_on_entry = NOT_LP64(rsi) LP64_ONLY(r13);
+
// NEEDED for JVMTI?
// address AbstractInterpreter::_remove_activation_preserving_args_entry;
@@ -88,7 +96,6 @@ bool CppInterpreter::contains(address pc
address CppInterpreterGenerator::generate_result_handler_for(BasicType type) {
- const Register state = rsi; // current activation object, valid on entry
address entry = __ pc();
switch (type) {
case T_BOOLEAN: __ c2bool(rax); break;
@@ -98,19 +105,22 @@ address CppInterpreterGenerator::generat
case T_VOID : // fall thru
case T_LONG : // fall thru
case T_INT : /* nothing to do */ break;
+
case T_DOUBLE :
case T_FLOAT :
- { const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
- __ popl(t); // remove return address first
- __ pop_dtos_to_rsp();
+ {
+ const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
+ __ pop(t); // remove return address first
// Must return a result for interpreter or compiler. In SSE
// mode, results are returned in xmm0 and the FPU stack must
// be empty.
if (type == T_FLOAT && UseSSE >= 1) {
+#ifndef _LP64
// Load ST0
__ fld_d(Address(rsp, 0));
// Store as float and empty fpu stack
__ fstp_s(Address(rsp, 0));
+#endif // !_LP64
// and reload
__ movflt(xmm0, Address(rsp, 0));
} else if (type == T_DOUBLE && UseSSE >= 2 ) {
@@ -120,13 +130,13 @@ address CppInterpreterGenerator::generat
__ fld_d(Address(rsp, 0));
}
// and pop the temp
- __ addl(rsp, 2 * wordSize);
- __ pushl(t); // restore return address
+ __ addptr(rsp, 2 * wordSize);
+ __ push(t); // restore return address
}
break;
case T_OBJECT :
// retrieve result from frame
- __ movl(rax, STATE(_oop_temp));
+ __ movptr(rax, STATE(_oop_temp));
// and verify it
__ verify_oop(rax);
break;
@@ -146,7 +156,7 @@ address CppInterpreterGenerator::generat
address entry = __ pc();
const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
- __ popl(t); // remove return address first
+ __ pop(t); // remove return address first
switch (type) {
case T_VOID:
break;
@@ -154,53 +164,53 @@ address CppInterpreterGenerator::generat
#ifdef EXTEND
__ c2bool(rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_CHAR :
#ifdef EXTEND
__ andl(rax, 0xFFFF);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_BYTE :
#ifdef EXTEND
__ sign_extend_byte (rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_SHORT :
#ifdef EXTEND
__ sign_extend_short(rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_LONG :
- __ pushl(rdx);
- __ pushl(rax);
+ __ push(rdx); // pushes useless junk on 64bit
+ __ push(rax);
break;
case T_INT :
- __ pushl(rax);
+ __ push(rax);
break;
case T_FLOAT :
- // Result is in ST(0)
+ // Result is in ST(0)/xmm0
+ __ subptr(rsp, wordSize);
if ( UseSSE < 1) {
- __ push(ftos); // and save it
+ __ fstp_s(Address(rsp, 0));
} else {
- __ subl(rsp, wordSize);
__ movflt(Address(rsp, 0), xmm0);
}
break;
case T_DOUBLE :
+ __ subptr(rsp, 2*wordSize);
if ( UseSSE < 2 ) {
- __ push(dtos); // put ST0 on java stack
+ __ fstp_d(Address(rsp, 0));
} else {
- __ subl(rsp, 2*wordSize);
__ movdbl(Address(rsp, 0), xmm0);
}
break;
case T_OBJECT :
__ verify_oop(rax); // verify it
- __ pushl(rax);
+ __ push(rax);
break;
default : ShouldNotReachHere();
}
@@ -212,7 +222,7 @@ address CppInterpreterGenerator::generat
// A result is in the java expression stack of the interpreted method that has just
// returned. Place this result on the java expression stack of the caller.
//
- // The current interpreter activation in rsi is for the method just returning its
+ // The current interpreter activation in rsi/r13 is for the method just returning its
// result. So we know that the result of this method is on the top of the current
// execution stack (which is pre-pushed) and will be return to the top of the caller
// stack. The top of the callers stack is the bottom of the locals of the current
@@ -222,20 +232,19 @@ address CppInterpreterGenerator::generat
// of the calling activation. This enable this routine to leave the return address
// to the frame manager on the stack and do a vanilla return.
//
- // On entry: rsi - interpreter state of activation returning a (potential) result
- // On Return: rsi - unchanged
+ // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+ // On Return: rsi/r13 - unchanged
// rax - new stack top for caller activation (i.e. activation in _prev_link)
//
// Can destroy rdx, rcx.
//
address entry = __ pc();
- const Register state = rsi; // current activation object, valid on entry
const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
switch (type) {
case T_VOID:
- __ movl(rax, STATE(_locals)); // pop parameters get new stack value
- __ addl(rax, wordSize); // account for prepush before we return
+ __ movptr(rax, STATE(_locals)); // pop parameters get new stack value
+ __ addptr(rax, wordSize); // account for prepush before we return
break;
case T_FLOAT :
case T_BOOLEAN:
@@ -244,10 +253,10 @@ address CppInterpreterGenerator::generat
case T_SHORT :
case T_INT :
// 1 word result
- __ movl(rdx, STATE(_stack));
- __ movl(rax, STATE(_locals)); // address for result
+ __ movptr(rdx, STATE(_stack));
+ __ movptr(rax, STATE(_locals)); // address for result
__ movl(rdx, Address(rdx, wordSize)); // get result
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
case T_LONG :
case T_DOUBLE :
@@ -256,20 +265,20 @@ address CppInterpreterGenerator::generat
// except we allocated one extra word for this intepretState so we won't overwrite it
// when we return a two word result.
- __ movl(rax, STATE(_locals)); // address for result
- __ movl(rcx, STATE(_stack));
- __ subl(rax, wordSize); // need addition word besides locals[0]
- __ movl(rdx, Address(rcx, 2*wordSize)); // get result word
- __ movl(Address(rax, wordSize), rdx); // and store it
- __ movl(rdx, Address(rcx, wordSize)); // get result word
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(rax, STATE(_locals)); // address for result
+ __ movptr(rcx, STATE(_stack));
+ __ subptr(rax, wordSize); // need addition word besides locals[0]
+ __ movptr(rdx, Address(rcx, 2*wordSize)); // get result word (junk in 64bit)
+ __ movptr(Address(rax, wordSize), rdx); // and store it
+ __ movptr(rdx, Address(rcx, wordSize)); // get result word
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
case T_OBJECT :
- __ movl(rdx, STATE(_stack));
- __ movl(rax, STATE(_locals)); // address for result
- __ movl(rdx, Address(rdx, wordSize)); // get result
+ __ movptr(rdx, STATE(_stack));
+ __ movptr(rax, STATE(_locals)); // address for result
+ __ movptr(rdx, Address(rdx, wordSize)); // get result
__ verify_oop(rdx); // verify it
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
default : ShouldNotReachHere();
}
@@ -285,12 +294,11 @@ address CppInterpreterGenerator::generat
// frame manager execept in this situation the caller is native code (c1/c2/call_stub)
// and so rather than return result onto caller's java expression stack we return the
// result in the expected location based on the native abi.
- // On entry: rsi - interpreter state of activation returning a (potential) result
- // On Return: rsi - unchanged
+ // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+ // On Return: rsi/r13 - unchanged
// Other registers changed [rax/rdx/ST(0) as needed for the result returned]
address entry = __ pc();
- const Register state = rsi; // current activation object, valid on entry
switch (type) {
case T_VOID:
break;
@@ -299,17 +307,16 @@ address CppInterpreterGenerator::generat
case T_BYTE :
case T_SHORT :
case T_INT :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
__ movl(rax, Address(rdx, wordSize)); // get result word 1
break;
case T_LONG :
- __ movl(rdx, STATE(_stack)); // get top of stack
- __ movl(rax, Address(rdx, wordSize)); // get result low word
- __ movl(rdx, Address(rdx, 2*wordSize)); // get result high word
- break;
+ __ movptr(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rax, Address(rdx, wordSize)); // get result low word
+ NOT_LP64(__ movl(rdx, Address(rdx, 2*wordSize));) // get result high word
break;
case T_FLOAT :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
if ( UseSSE >= 1) {
__ movflt(xmm0, Address(rdx, wordSize));
} else {
@@ -317,7 +324,7 @@ address CppInterpreterGenerator::generat
}
break;
case T_DOUBLE :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
if ( UseSSE > 1) {
__ movdbl(xmm0, Address(rdx, wordSize));
} else {
@@ -325,8 +332,8 @@ address CppInterpreterGenerator::generat
}
break;
case T_OBJECT :
- __ movl(rdx, STATE(_stack)); // get top of stack
- __ movl(rax, Address(rdx, wordSize)); // get result word 1
+ __ movptr(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rax, Address(rdx, wordSize)); // get result word 1
__ verify_oop(rax); // verify it
break;
default : ShouldNotReachHere();
@@ -408,54 +415,58 @@ void CppInterpreterGenerator::generate_c
if (!native) {
#ifdef PRODUCT
- __ subl(rsp, 2*wordSize);
+ __ subptr(rsp, 2*wordSize);
#else /* PRODUCT */
- __ pushl((int)NULL);
- __ pushl(state); // make it look like a real argument
+ __ push((int32_t)NULL_WORD);
+ __ push(state); // make it look like a real argument
#endif /* PRODUCT */
}
// Now that we are assure of space for stack result, setup typical linkage
- __ pushl(rax);
+ __ push(rax);
__ enter();
- __ movl(rax, state); // save current state
-
- __ leal(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
- __ movl(state, rsp);
-
- // rsi == state/locals rax == prevstate
+ __ mov(rax, state); // save current state
+
+ __ lea(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
+ __ mov(state, rsp);
+
+ // rsi/r13 == state/locals rax == prevstate
// initialize the "shadow" frame so that use since C++ interpreter not directly
// recursive. Simpler to recurse but we can't trim expression stack as we call
// new methods.
- __ movl(STATE(_locals), locals); // state->_locals = locals()
- __ movl(STATE(_self_link), state); // point to self
- __ movl(STATE(_prev_link), rax); // state->_link = state on entry (NULL or previous state)
- __ movl(STATE(_sender_sp), sender_sp); // state->_sender_sp = sender_sp
+ __ movptr(STATE(_locals), locals); // state->_locals = locals()
+ __ movptr(STATE(_self_link), state); // point to self
+ __ movptr(STATE(_prev_link), rax); // state->_link = state on entry (NULL or previous state)
+ __ movptr(STATE(_sender_sp), sender_sp); // state->_sender_sp = sender_sp
+#ifdef _LP64
+ __ movptr(STATE(_thread), r15_thread); // state->_bcp = codes()
+#else
__ get_thread(rax); // get vm's javathread*
- __ movl(STATE(_thread), rax); // state->_bcp = codes()
- __ movl(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
- __ leal(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
+ __ movptr(STATE(_thread), rax); // state->_bcp = codes()
+#endif // _LP64
+ __ movptr(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
+ __ lea(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
if (native) {
- __ movl(STATE(_bcp), (intptr_t)NULL); // state->_bcp = NULL
+ __ movptr(STATE(_bcp), (int32_t)NULL_WORD); // state->_bcp = NULL
} else {
- __ movl(STATE(_bcp), rdx); // state->_bcp = codes()
- }
- __ xorl(rdx, rdx);
- __ movl(STATE(_oop_temp), rdx); // state->_oop_temp = NULL (only really needed for native)
- __ movl(STATE(_mdx), rdx); // state->_mdx = NULL
- __ movl(rdx, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
- __ movl(STATE(_constants), rdx); // state->_constants = constants()
-
- __ movl(STATE(_method), rbx); // state->_method = method()
- __ movl(STATE(_msg), (int) BytecodeInterpreter::method_entry); // state->_msg = initial method entry
- __ movl(STATE(_result._to_call._callee), (int) NULL); // state->_result._to_call._callee_callee = NULL
-
-
- __ movl(STATE(_monitor_base), rsp); // set monitor block bottom (grows down) this would point to entry [0]
+ __ movptr(STATE(_bcp), rdx); // state->_bcp = codes()
+ }
+ __ xorptr(rdx, rdx);
+ __ movptr(STATE(_oop_temp), rdx); // state->_oop_temp = NULL (only really needed for native)
+ __ movptr(STATE(_mdx), rdx); // state->_mdx = NULL
+ __ movptr(rdx, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
+ __ movptr(STATE(_constants), rdx); // state->_constants = constants()
+
+ __ movptr(STATE(_method), rbx); // state->_method = method()
+ __ movl(STATE(_msg), (int32_t) BytecodeInterpreter::method_entry); // state->_msg = initial method entry
+ __ movptr(STATE(_result._to_call._callee), (int32_t) NULL_WORD); // state->_result._to_call._callee_callee = NULL
+
+
+ __ movptr(STATE(_monitor_base), rsp); // set monitor block bottom (grows down) this would point to entry [0]
// entries run from -1..x where &monitor[x] ==
{
@@ -479,35 +490,43 @@ void CppInterpreterGenerator::generate_c
const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
__ movl(rax, access_flags);
__ testl(rax, JVM_ACC_STATIC);
- __ movl(rax, Address(locals, 0)); // get receiver (assume this is frequent case)
+ __ movptr(rax, Address(locals, 0)); // get receiver (assume this is frequent case)
__ jcc(Assembler::zero, done);
- __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
- __ movl(rax, Address(rax, mirror_offset));
+ __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+ __ movptr(rax, Address(rax, mirror_offset));
__ bind(done);
// add space for monitor & lock
- __ subl(rsp, entry_size); // add space for a monitor entry
- __ movl(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
+ __ subptr(rsp, entry_size); // add space for a monitor entry
+ __ movptr(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
__ bind(not_synced);
}
- __ movl(STATE(_stack_base), rsp); // set expression stack base ( == &monitors[-count])
+ __ movptr(STATE(_stack_base), rsp); // set expression stack base ( == &monitors[-count])
if (native) {
- __ movl(STATE(_stack), rsp); // set current expression stack tos
- __ movl(STATE(_stack_limit), rsp);
+ __ movptr(STATE(_stack), rsp); // set current expression stack tos
+ __ movptr(STATE(_stack_limit), rsp);
} else {
- __ subl(rsp, wordSize); // pre-push stack
- __ movl(STATE(_stack), rsp); // set current expression stack tos
+ __ subptr(rsp, wordSize); // pre-push stack
+ __ movptr(STATE(_stack), rsp); // set current expression stack tos
// compute full expression stack limit
const Address size_of_stack (rbx, methodOopDesc::max_stack_offset());
__ load_unsigned_word(rdx, size_of_stack); // get size of expression stack in words
- __ negl(rdx); // so we can subtract in next step
+ __ negptr(rdx); // so we can subtract in next step
// Allocate expression stack
- __ leal(rsp, Address(rsp, rdx, Address::times_4));
- __ movl(STATE(_stack_limit), rsp);
- }
+ __ lea(rsp, Address(rsp, rdx, Address::times_ptr));
+ __ movptr(STATE(_stack_limit), rsp);
+ }
+
+#ifdef _LP64
+ // Make sure stack is properly aligned and sized for the abi
+ __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+ __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+#endif // _LP64
+
+
}
@@ -528,7 +547,7 @@ void InterpreterGenerator::generate_coun
const Address backedge_counter (rbx, methodOopDesc::backedge_counter_offset() + InvocationCounter::counter_offset());
if (ProfileInterpreter) { // %%% Merge this into methodDataOop
- __ increment(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
+ __ incrementl(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
}
// Update standard invocation counters
__ movl(rax, backedge_counter); // load backedge counter
@@ -552,7 +571,7 @@ void InterpreterGenerator::generate_coun
void InterpreterGenerator::generate_counter_overflow(Label* do_continue) {
// C++ interpreter on entry
- // rsi - new interpreter state pointer
+ // rsi/r13 - new interpreter state pointer
// rbp - interpreter frame pointer
// rbx - method
@@ -563,7 +582,7 @@ void InterpreterGenerator::generate_coun
// rsp - sender_sp
// C++ interpreter only
- // rsi - previous interpreter state pointer
+ // rsi/r13 - previous interpreter state pointer
const Address size_of_parameters(rbx, methodOopDesc::size_of_parameters_offset());
@@ -571,16 +590,14 @@ void InterpreterGenerator::generate_coun
// indicating if the counter overflow occurs at a backwards branch (non-NULL bcp).
// The call returns the address of the verified entry point for the method or NULL
// if the compilation did not complete (either went background or bailed out).
- __ movl(rax, (int)false);
+ __ movptr(rax, (int32_t)false);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), rax);
// for c++ interpreter can rsi really be munged?
- __ leal(rsi, Address(rbp, -sizeof(BytecodeInterpreter))); // restore state
- __ movl(rbx, Address(rsi, byte_offset_of(BytecodeInterpreter, _method))); // restore method
- __ movl(rdi, Address(rsi, byte_offset_of(BytecodeInterpreter, _locals))); // get locals pointer
-
- // Preserve invariant that rsi/rdi contain bcp/locals of sender frame
- // and jump to the interpreted entry.
+ __ lea(state, Address(rbp, -sizeof(BytecodeInterpreter))); // restore state
+ __ movptr(rbx, Address(state, byte_offset_of(BytecodeInterpreter, _method))); // restore method
+ __ movptr(rdi, Address(state, byte_offset_of(BytecodeInterpreter, _locals))); // get locals pointer
+
__ jmp(*do_continue, relocInfo::none);
}
@@ -597,7 +614,7 @@ void InterpreterGenerator::generate_stac
// rbx,: methodOop
// C++ Interpreter
- // rsi: previous interpreter frame state object
+ // rsi/r13: previous interpreter frame state object
// rdi: &locals[0]
// rcx: # of locals
// rdx: number of additional locals this frame needs (what we must check)
@@ -628,11 +645,11 @@ void InterpreterGenerator::generate_stac
// save rsi == caller's bytecode ptr (c++ previous interp. state)
// QQQ problem here?? rsi overload????
- __ pushl(rsi);
-
- const Register thread = rsi;
-
- __ get_thread(thread);
+ __ push(state);
+
+ const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rsi);
+
+ NOT_LP64(__ get_thread(thread));
const Address stack_base(thread, Thread::stack_base_offset());
const Address stack_size(thread, Thread::stack_size_offset());
@@ -643,26 +660,26 @@ void InterpreterGenerator::generate_stac
// Any additional monitors need a check when moving the expression stack
const one_monitor = frame::interpreter_frame_monitor_size() * wordSize;
__ load_unsigned_word(rax, size_of_stack); // get size of expression stack in words
- __ leal(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
- __ leal(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
+ __ lea(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
+ __ lea(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
#ifdef ASSERT
Label stack_base_okay, stack_size_okay;
// verify that thread stack base is non-zero
- __ cmpl(stack_base, 0);
+ __ cmpptr(stack_base, (int32_t)0);
__ jcc(Assembler::notEqual, stack_base_okay);
__ stop("stack base is zero");
__ bind(stack_base_okay);
// verify that thread stack size is non-zero
- __ cmpl(stack_size, 0);
+ __ cmpptr(stack_size, (int32_t)0);
__ jcc(Assembler::notEqual, stack_size_okay);
__ stop("stack size is zero");
__ bind(stack_size_okay);
#endif
// Add stack base to locals and subtract stack size
- __ addl(rax, stack_base);
- __ subl(rax, stack_size);
+ __ addptr(rax, stack_base);
+ __ subptr(rax, stack_size);
// We should have a magic number here for the size of the c++ interpreter frame.
// We can't actually tell this ahead of time. The debug version size is around 3k
@@ -674,20 +691,20 @@ void InterpreterGenerator::generate_stac
(StackRedPages+StackYellowPages);
// Only need this if we are stack banging which is temporary while
// we're debugging.
- __ addl(rax, slop + 2*max_pages * page_size);
+ __ addptr(rax, slop + 2*max_pages * page_size);
// check against the current stack bottom
- __ cmpl(rsp, rax);
+ __ cmpptr(rsp, rax);
__ jcc(Assembler::above, after_frame_check_pop);
- __ popl(rsi); // get saved bcp / (c++ prev state ).
+ __ pop(state); // get c++ prev state.
// throw exception return address becomes throwing pc
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_StackOverflowError));
// all done with frame size check
__ bind(after_frame_check_pop);
- __ popl(rsi);
+ __ pop(state);
__ bind(after_frame_check);
}
@@ -696,17 +713,18 @@ void InterpreterGenerator::generate_stac
// rbx - methodOop
//
void InterpreterGenerator::lock_method(void) {
- // assumes state == rsi == pointer to current interpreterState
- // minimally destroys rax, rdx, rdi
+ // assumes state == rsi/r13 == pointer to current interpreterState
+ // minimally destroys rax, rdx|c_rarg1, rdi
//
// synchronize method
- const Register state = rsi;
const int entry_size = frame::interpreter_frame_monitor_size() * wordSize;
const Address access_flags (rbx, methodOopDesc::access_flags_offset());
+ const Register monitor = NOT_LP64(rdx) LP64_ONLY(c_rarg1);
+
// find initial monitor i.e. monitors[-1]
- __ movl(rdx, STATE(_monitor_base)); // get monitor bottom limit
- __ subl(rdx, entry_size); // point to initial monitor
+ __ movptr(monitor, STATE(_monitor_base)); // get monitor bottom limit
+ __ subptr(monitor, entry_size); // point to initial monitor
#ifdef ASSERT
{ Label L;
@@ -721,35 +739,34 @@ void InterpreterGenerator::lock_method(v
{ Label done;
const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
__ movl(rax, access_flags);
- __ movl(rdi, STATE(_locals)); // prepare to get receiver (assume common case)
+ __ movptr(rdi, STATE(_locals)); // prepare to get receiver (assume common case)
__ testl(rax, JVM_ACC_STATIC);
- __ movl(rax, Address(rdi, 0)); // get receiver (assume this is frequent case)
+ __ movptr(rax, Address(rdi, 0)); // get receiver (assume this is frequent case)
__ jcc(Assembler::zero, done);
- __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
- __ movl(rax, Address(rax, mirror_offset));
+ __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+ __ movptr(rax, Address(rax, mirror_offset));
__ bind(done);
}
#ifdef ASSERT
{ Label L;
- __ cmpl(rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes())); // correct object?
+ __ cmpptr(rax, Address(monitor, BasicObjectLock::obj_offset_in_bytes())); // correct object?
__ jcc(Assembler::equal, L);
__ stop("wrong synchronization lobject");
__ bind(L);
}
#endif // ASSERT
- // can destroy rax, rdx, rcx, and (via call_VM) rdi!
- __ lock_object(rdx);
+ // can destroy rax, rdx|c_rarg1, rcx, and (via call_VM) rdi!
+ __ lock_object(monitor);
}
// Call an accessor method (assuming it is resolved, otherwise drop into vanilla (slow path) entry
address InterpreterGenerator::generate_accessor_entry(void) {
- // rbx,: methodOop
- // rcx: receiver (preserve for slow entry into asm interpreter)
-
- // rsi: senderSP must preserved for slow path, set SP to it on fast path
+ // rbx: methodOop
+
+ // rsi/r13: senderSP must preserved for slow path, set SP to it on fast path
Label xreturn_path;
@@ -772,21 +789,21 @@ address InterpreterGenerator::generate_a
// these conditions first and use slow path if necessary.
// rbx,: method
// rcx: receiver
- __ movl(rax, Address(rsp, wordSize));
+ __ movptr(rax, Address(rsp, wordSize));
// check if local 0 != NULL and read field
- __ testl(rax, rax);
+ __ testptr(rax, rax);
__ jcc(Assembler::zero, slow_path);
- __ movl(rdi, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rdi, Address(rbx, methodOopDesc::constants_offset()));
// read first instruction word and extract bytecode @ 1 and index @ 2
- __ movl(rdx, Address(rbx, methodOopDesc::const_offset()));
+ __ movptr(rdx, Address(rbx, methodOopDesc::const_offset()));
__ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
// Shift codes right to get the index on the right.
// The bytecode fetched looks like <index><0xb4><0x2a>
__ shrl(rdx, 2*BitsPerByte);
__ shll(rdx, exact_log2(in_words(ConstantPoolCacheEntry::size())));
- __ movl(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
+ __ movptr(rdi, Address(rdi, constantPoolOopDesc::cache_offset_in_bytes()));
// rax,: local 0
// rbx,: method
@@ -794,7 +811,7 @@ address InterpreterGenerator::generate_a
// rcx: scratch
// rdx: constant pool cache index
// rdi: constant pool cache
- // rsi: sender sp
+ // rsi/r13: sender sp
// check if getfield has been resolved and read constant pool cache entry
// check the validity of the cache entry by testing whether _indices field
@@ -803,21 +820,21 @@ address InterpreterGenerator::generate_a
__ movl(rcx,
Address(rdi,
rdx,
- Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
+ Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset()));
__ shrl(rcx, 2*BitsPerByte);
__ andl(rcx, 0xFF);
__ cmpl(rcx, Bytecodes::_getfield);
__ jcc(Assembler::notEqual, slow_path);
// Note: constant pool entry is not valid before bytecode is resolved
- __ movl(rcx,
+ __ movptr(rcx,
Address(rdi,
rdx,
- Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
+ Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::f2_offset()));
__ movl(rdx,
Address(rdi,
rdx,
- Address::times_4, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
+ Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::flags_offset()));
Label notByte, notShort, notChar;
const Address field_address (rax, rcx, Address::times_1);
@@ -828,6 +845,16 @@ address InterpreterGenerator::generate_a
__ shrl(rdx, ConstantPoolCacheEntry::tosBits);
// Make sure we don't need to mask rdx for tosBits after the above shift
ConstantPoolCacheEntry::verify_tosBits();
+#ifdef _LP64
+ Label notObj;
+ __ cmpl(rdx, atos);
+ __ jcc(Assembler::notEqual, notObj);
+ // atos
+ __ movptr(rax, field_address);
+ __ jmp(xreturn_path);
+
+ __ bind(notObj);
+#endif // _LP64
__ cmpl(rdx, btos);
__ jcc(Assembler::notEqual, notByte);
__ load_signed_byte(rax, field_address);
@@ -848,8 +875,10 @@ address InterpreterGenerator::generate_a
__ bind(notChar);
#ifdef ASSERT
Label okay;
+#ifndef _LP64
__ cmpl(rdx, atos);
__ jcc(Assembler::equal, okay);
+#endif // _LP64
__ cmpl(rdx, itos);
__ jcc(Assembler::equal, okay);
__ stop("what type is this?");
@@ -861,8 +890,8 @@ address InterpreterGenerator::generate_a
__ bind(xreturn_path);
// _ireturn/_areturn
- __ popl(rdi); // get return address
- __ movl(rsp, rsi); // set sp to sender sp
+ __ pop(rdi); // get return address
+ __ mov(rsp, sender_sp_on_entry); // set sp to sender sp
__ jmp(rdi);
// generate a vanilla interpreter entry as the slow path
@@ -894,8 +923,8 @@ address InterpreterGenerator::generate_n
// rbx: methodOop
// rcx: receiver (unused)
- // rsi: previous interpreter state (if called from C++ interpreter) must preserve
- // in any case. If called via c1/c2/call_stub rsi is junk (to use) but harmless
+ // rsi/r13: previous interpreter state (if called from C++ interpreter) must preserve
+ // in any case. If called via c1/c2/call_stub rsi/r13 is junk (to use) but harmless
// to save/restore.
address entry_point = __ pc();
@@ -904,8 +933,7 @@ address InterpreterGenerator::generate_n
const Address invocation_counter(rbx, methodOopDesc::invocation_counter_offset() + InvocationCounter::counter_offset());
const Address access_flags (rbx, methodOopDesc::access_flags_offset());
- // rsi == state/locals rdi == prevstate
- const Register state = rsi;
+ // rsi/r13 == state/locals rdi == prevstate
const Register locals = rdi;
// get parameter size (always needed)
@@ -913,11 +941,11 @@ address InterpreterGenerator::generate_n
// rbx: methodOop
// rcx: size of parameters
- __ popl(rax); // get return address
+ __ pop(rax); // get return address
// for natives the size of locals is zero
// compute beginning of parameters /locals
- __ leal(locals, Address(rsp, rcx, Address::times_4, -wordSize));
+ __ lea(locals, Address(rsp, rcx, Address::times_ptr, -wordSize));
// initialize fixed part of activation frame
@@ -931,15 +959,20 @@ address InterpreterGenerator::generate_n
// OUT(rsp) -> bottom of methods expression stack
// save sender_sp
- __ movl(rcx, rsi);
+ __ mov(rcx, sender_sp_on_entry);
// start with NULL previous state
- __ movl(state, 0);
+ __ movptr(state, (int32_t)NULL_WORD);
generate_compute_interpreter_state(state, locals, rcx, true);
#ifdef ASSERT
{ Label L;
- __ movl(rax, STATE(_stack_base));
- __ cmpl(rax, rsp);
+ __ movptr(rax, STATE(_stack_base));
+#ifdef _LP64
+ // duplicate the alignment rsp got after setting stack_base
+ __ subptr(rax, frame::arg_reg_save_area_bytes); // windows
+ __ andptr(rax, -16); // must be 16 byte boundry (see amd64 ABI)
+#endif // _LP64
+ __ cmpptr(rax, rsp);
__ jcc(Assembler::equal, L);
__ stop("broken stack frame setup in interpreter");
__ bind(L);
@@ -948,14 +981,15 @@ address InterpreterGenerator::generate_n
if (inc_counter) __ movl(rcx, invocation_counter); // (pre-)fetch invocation count
- __ movl(rax, STATE(_thread)); // get thread
+ const Register unlock_thread = LP64_ONLY(r15_thread) NOT_LP64(rax);
+ NOT_LP64(__ movptr(unlock_thread, STATE(_thread));) // get thread
// Since at this point in the method invocation the exception handler
// would try to exit the monitor of synchronized methods which hasn't
// been entered yet, we set the thread local variable
// _do_not_unlock_if_synchronized to true. The remove_activation will
// check this flag.
- const Address do_not_unlock_if_synchronized(rax,
+ const Address do_not_unlock_if_synchronized(unlock_thread,
in_bytes(JavaThread::do_not_unlock_if_synchronized_offset()));
__ movbool(do_not_unlock_if_synchronized, true);
@@ -991,7 +1025,7 @@ address InterpreterGenerator::generate_n
bang_stack_shadow_pages(true);
// reset the _do_not_unlock_if_synchronized flag
- __ movl(rax, STATE(_thread)); // get thread
+ NOT_LP64(__ movl(rax, STATE(_thread));) // get thread
__ movbool(do_not_unlock_if_synchronized, false);
@@ -1022,62 +1056,81 @@ address InterpreterGenerator::generate_n
// work registers
const Register method = rbx;
- const Register thread = rdi;
- const Register t = rcx;
+ const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rdi);
+ const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp(); // rcx|rscratch1
// allocate space for parameters
- __ movl(method, STATE(_method));
+ __ movptr(method, STATE(_method));
__ verify_oop(method);
__ load_unsigned_word(t, Address(method, methodOopDesc::size_of_parameters_offset()));
__ shll(t, 2);
- __ addl(t, 2*wordSize); // allocate two more slots for JNIEnv and possible mirror
- __ subl(rsp, t);
- __ andl(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
+#ifdef _LP64
+ __ subptr(rsp, t);
+ __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+ __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+#else
+ __ addptr(t, 2*wordSize); // allocate two more slots for JNIEnv and possible mirror
+ __ subptr(rsp, t);
+ __ andptr(rsp, -(StackAlignmentInBytes)); // gcc needs 16 byte aligned stacks to do XMM intrinsics
+#endif // _LP64
// get signature handler
Label pending_exception_present;
{ Label L;
- __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
- __ testl(t, t);
+ __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
+ __ testptr(t, t);
__ jcc(Assembler::notZero, L);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method, false);
- __ movl(method, STATE(_method));
- __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ movptr(method, STATE(_method));
+ __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::notEqual, pending_exception_present);
__ verify_oop(method);
- __ movl(t, Address(method, methodOopDesc::signature_handler_offset()));
+ __ movptr(t, Address(method, methodOopDesc::signature_handler_offset()));
__ bind(L);
}
#ifdef ASSERT
{
Label L;
- __ pushl(t);
+ __ push(t);
__ get_thread(t); // get vm's javathread*
- __ cmpl(t, STATE(_thread));
+ __ cmpptr(t, STATE(_thread));
__ jcc(Assembler::equal, L);
__ int3();
__ bind(L);
- __ popl(t);
+ __ pop(t);
}
#endif //
+ const Register from_ptr = InterpreterRuntime::SignatureHandlerGenerator::from();
// call signature handler
- assert(InterpreterRuntime::SignatureHandlerGenerator::from() == rdi, "adjust this code");
assert(InterpreterRuntime::SignatureHandlerGenerator::to () == rsp, "adjust this code");
- assert(InterpreterRuntime::SignatureHandlerGenerator::temp() == t , "adjust this code");
+
// The generated handlers do not touch RBX (the method oop).
// However, large signatures cannot be cached and are generated
// each time here. The slow-path generator will blow RBX
// sometime, so we must reload it after the call.
- __ movl(rdi, STATE(_locals)); // get the from pointer
+ __ movptr(from_ptr, STATE(_locals)); // get the from pointer
__ call(t);
- __ movl(method, STATE(_method));
+ __ movptr(method, STATE(_method));
__ verify_oop(method);
// result handler is in rax
// set result handler
- __ movl(STATE(_result_handler), rax);
+ __ movptr(STATE(_result_handler), rax);
+
+
+ // get native function entry point
+ { Label L;
+ __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
+ __ testptr(rax, rax);
+ __ jcc(Assembler::notZero, L);
+ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
+ __ movptr(method, STATE(_method));
+ __ verify_oop(method);
+ __ movptr(rax, Address(method, methodOopDesc::native_function_offset()));
+ __ bind(L);
+ }
// pass mirror handle if static call
{ Label L;
@@ -1086,55 +1139,53 @@ address InterpreterGenerator::generate_n
__ testl(t, JVM_ACC_STATIC);
__ jcc(Assembler::zero, L);
// get mirror
- __ movl(t, Address(method, methodOopDesc:: constants_offset()));
- __ movl(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
- __ movl(t, Address(t, mirror_offset));
+ __ movptr(t, Address(method, methodOopDesc:: constants_offset()));
+ __ movptr(t, Address(t, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+ __ movptr(t, Address(t, mirror_offset));
// copy mirror into activation object
- __ movl(STATE(_oop_temp), t);
+ __ movptr(STATE(_oop_temp), t);
// pass handle to mirror
- __ leal(t, STATE(_oop_temp));
- __ movl(Address(rsp, wordSize), t);
+#ifdef _LP64
+ __ lea(c_rarg1, STATE(_oop_temp));
+#else
+ __ lea(t, STATE(_oop_temp));
+ __ movptr(Address(rsp, wordSize), t);
+#endif // _LP64
__ bind(L);
}
#ifdef ASSERT
{
Label L;
- __ pushl(t);
+ __ push(t);
__ get_thread(t); // get vm's javathread*
- __ cmpl(t, STATE(_thread));
+ __ cmpptr(t, STATE(_thread));
__ jcc(Assembler::equal, L);
__ int3();
__ bind(L);
- __ popl(t);
+ __ pop(t);
}
#endif //
- // get native function entry point
- { Label L;
- __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
- __ testl(rax, rax);
- __ jcc(Assembler::notZero, L);
- __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method);
- __ movl(method, STATE(_method));
- __ verify_oop(method);
- __ movl(rax, Address(method, methodOopDesc::native_function_offset()));
- __ bind(L);
- }
-
// pass JNIEnv
- __ movl(thread, STATE(_thread)); // get thread
- __ leal(t, Address(thread, JavaThread::jni_environment_offset()));
- __ movl(Address(rsp, 0), t);
+#ifdef _LP64
+ __ lea(c_rarg0, Address(thread, JavaThread::jni_environment_offset()));
+#else
+ __ movptr(thread, STATE(_thread)); // get thread
+ __ lea(t, Address(thread, JavaThread::jni_environment_offset()));
+
+ __ movptr(Address(rsp, 0), t);
+#endif // _LP64
+
#ifdef ASSERT
{
Label L;
- __ pushl(t);
+ __ push(t);
__ get_thread(t); // get vm's javathread*
- __ cmpl(t, STATE(_thread));
+ __ cmpptr(t, STATE(_thread));
__ jcc(Assembler::equal, L);
__ int3();
__ bind(L);
- __ popl(t);
+ __ pop(t);
}
#endif //
@@ -1159,8 +1210,8 @@ address InterpreterGenerator::generate_n
__ call(rax);
// result potentially in rdx:rax or ST0
- __ movl(method, STATE(_method));
- __ movl(thread, STATE(_thread)); // get thread
+ __ movptr(method, STATE(_method));
+ NOT_LP64(__ movptr(thread, STATE(_thread));) // get thread
// The potential result is in ST(0) & rdx:rax
// With C++ interpreter we leave any possible result in ST(0) until we are in result handler and then
@@ -1170,7 +1221,7 @@ address InterpreterGenerator::generate_n
// It is safe to do these pushes because state is _thread_in_native and return address will be found
// via _last_native_pc and not via _last_jave_sp
- // Must save the value of ST(0) since it could be destroyed before we get to result handler
+ // Must save the value of ST(0)/xmm0 since it could be destroyed before we get to result handler
{ Label Lpush, Lskip;
ExternalAddress float_handler(AbstractInterpreter::result_handler(T_FLOAT));
ExternalAddress double_handler(AbstractInterpreter::result_handler(T_DOUBLE));
@@ -1179,11 +1230,20 @@ address InterpreterGenerator::generate_n
__ cmpptr(STATE(_result_handler), double_handler.addr());
__ jcc(Assembler::notEqual, Lskip);
__ bind(Lpush);
- __ push(dtos);
+ __ subptr(rsp, 2*wordSize);
+ if ( UseSSE < 2 ) {
+ __ fstp_d(Address(rsp, 0));
+ } else {
+ __ movdbl(Address(rsp, 0), xmm0);
+ }
__ bind(Lskip);
}
- __ push(ltos); // save rax:rdx for potential use by result handler.
+ // save rax:rdx for potential use by result handler.
+ __ push(rax);
+#ifndef _LP64
+ __ push(rdx);
+#endif // _LP64
// Either restore the MXCSR register after returning from the JNI Call
// or verify that it wasn't changed.
@@ -1192,15 +1252,17 @@ address InterpreterGenerator::generate_n
__ ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
}
else if (CheckJNICalls ) {
- __ call(RuntimeAddress(StubRoutines::i486::verify_mxcsr_entry()));
+ __ call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
}
}
+#ifndef _LP64
// Either restore the x87 floating pointer control word after returning
// from the JNI call or verify that it wasn't changed.
if (CheckJNICalls) {
- __ call(RuntimeAddress(StubRoutines::i486::verify_fpu_cntrl_wrd_entry()));
- }
+ __ call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
+ }
+#endif // _LP64
// change thread state
@@ -1231,17 +1293,16 @@ address InterpreterGenerator::generate_n
// Don't use call_VM as it will see a possible pending exception and forward it
// and never return here preventing us from clearing _last_native_pc down below.
// Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
- // preserved and correspond to the bcp/locals pointers. So we do a runtime call
- // by hand.
+ // preserved and correspond to the bcp/locals pointers.
//
- __ pushl(thread);
- __ call(RuntimeAddress(CAST_FROM_FN_PTR(address,
- JavaThread::check_special_condition_for_native_trans)));
+
+ ((MacroAssembler*)_masm)->call_VM_leaf(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
+ thread);
__ increment(rsp, wordSize);
- __ movl(method, STATE(_method));
+ __ movptr(method, STATE(_method));
__ verify_oop(method);
- __ movl(thread, STATE(_thread)); // get thread
+ __ movptr(thread, STATE(_thread)); // get thread
__ bind(Continue);
}
@@ -1252,8 +1313,8 @@ address InterpreterGenerator::generate_n
__ reset_last_Java_frame(thread, true, true);
// reset handle block
- __ movl(t, Address(thread, JavaThread::active_handles_offset()));
- __ movl(Address(t, JNIHandleBlock::top_offset_in_bytes()), NULL_WORD);
+ __ movptr(t, Address(thread, JavaThread::active_handles_offset()));
+ __ movptr(Address(t, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
// If result was an oop then unbox and save it in the frame
{ Label L;
@@ -1261,15 +1322,21 @@ address InterpreterGenerator::generate_n
ExternalAddress oop_handler(AbstractInterpreter::result_handler(T_OBJECT));
__ cmpptr(STATE(_result_handler), oop_handler.addr());
__ jcc(Assembler::notEqual, no_oop);
- __ pop(ltos);
- __ testl(rax, rax);
+#ifndef _LP64
+ __ pop(rdx);
+#endif // _LP64
+ __ pop(rax);
+ __ testptr(rax, rax);
__ jcc(Assembler::zero, store_result);
// unbox
- __ movl(rax, Address(rax, 0));
+ __ movptr(rax, Address(rax, 0));
__ bind(store_result);
- __ movl(STATE(_oop_temp), rax);
+ __ movptr(STATE(_oop_temp), rax);
// keep stack depth as expected by pushing oop which will eventually be discarded
- __ push(ltos);
+ __ push(rax);
+#ifndef _LP64
+ __ push(rdx);
+#endif // _LP64
__ bind(no_oop);
}
@@ -1278,9 +1345,9 @@ address InterpreterGenerator::generate_n
__ cmpl(Address(thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
__ jcc(Assembler::notEqual, no_reguard);
- __ pushad();
+ __ pusha();
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
- __ popad();
+ __ popa();
__ bind(no_reguard);
}
@@ -1295,7 +1362,7 @@ address InterpreterGenerator::generate_n
// handle exceptions (exception handling will handle unlocking!)
{ Label L;
- __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::zero, L);
__ bind(pending_exception_present);
@@ -1307,12 +1374,12 @@ address InterpreterGenerator::generate_n
// remove activation
- __ movl(t, STATE(_sender_sp));
+ __ movptr(t, STATE(_sender_sp));
__ leave(); // remove frame anchor
- __ popl(rdi); // get return address
- __ movl(state, STATE(_prev_link)); // get previous state for return
- __ movl(rsp, t); // set sp to sender sp
- __ pushl(rdi); // [ush throwing pc
+ __ pop(rdi); // get return address
+ __ movptr(state, STATE(_prev_link)); // get previous state for return
+ __ mov(rsp, t); // set sp to sender sp
+ __ push(rdi); // push throwing pc
// The skips unlocking!! This seems to be what asm interpreter does but seems
// very wrong. Not clear if this violates the spec.
__ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
@@ -1326,13 +1393,14 @@ address InterpreterGenerator::generate_n
__ jcc(Assembler::zero, L);
// the code below should be shared with interpreter macro assembler implementation
{ Label unlock;
+ const Register monitor = NOT_LP64(rdx) LP64_ONLY(c_rarg1);
// BasicObjectLock will be first in list, since this is a synchronized method. However, need
// to check that the object has not been unlocked by an explicit monitorexit bytecode.
- __ movl(rdx, STATE(_monitor_base));
- __ subl(rdx, frame::interpreter_frame_monitor_size() * wordSize); // address of initial monitor
-
- __ movl(t, Address(rdx, BasicObjectLock::obj_offset_in_bytes()));
- __ testl(t, t);
+ __ movptr(monitor, STATE(_monitor_base));
+ __ subptr(monitor, frame::interpreter_frame_monitor_size() * wordSize); // address of initial monitor
+
+ __ movptr(t, Address(monitor, BasicObjectLock::obj_offset_in_bytes()));
+ __ testptr(t, t);
__ jcc(Assembler::notZero, unlock);
// Entry already unlocked, need to throw exception
@@ -1340,9 +1408,9 @@ address InterpreterGenerator::generate_n
__ should_not_reach_here();
__ bind(unlock);
- __ unlock_object(rdx);
+ __ unlock_object(monitor);
// unlock can blow rbx so restore it for path that needs it below
- __ movl(method, STATE(_method));
+ __ movptr(method, STATE(_method));
}
__ bind(L);
}
@@ -1355,18 +1423,21 @@ address InterpreterGenerator::generate_n
__ notify_method_exit(vtos, InterpreterMacroAssembler::NotifyJVMTI);
// restore potential result in rdx:rax, call result handler to restore potential result in ST0 & handle result
- __ pop(ltos); // restore rax/rdx floating result if present still on stack
- __ movl(t, STATE(_result_handler)); // get result handler
+#ifndef _LP64
+ __ pop(rdx);
+#endif // _LP64
+ __ pop(rax);
+ __ movptr(t, STATE(_result_handler)); // get result handler
__ call(t); // call result handler to convert to tosca form
// remove activation
- __ movl(t, STATE(_sender_sp));
+ __ movptr(t, STATE(_sender_sp));
__ leave(); // remove frame anchor
- __ popl(rdi); // get return address
- __ movl(state, STATE(_prev_link)); // get previous state for return (if c++ interpreter was caller)
- __ movl(rsp, t); // set sp to sender sp
+ __ pop(rdi); // get return address
+ __ movptr(state, STATE(_prev_link)); // get previous state for return (if c++ interpreter was caller)
+ __ mov(rsp, t); // set sp to sender sp
__ jmp(rdi);
// invocation counter overflow
@@ -1382,7 +1453,6 @@ address InterpreterGenerator::generate_n
// Generate entries that will put a result type index into rcx
void CppInterpreterGenerator::generate_deopt_handling() {
- const Register state = rsi;
Label return_from_deopt_common;
// Generate entries that will put a result type index into rcx
@@ -1449,51 +1519,50 @@ void CppInterpreterGenerator::generate_d
//
__ bind(return_from_deopt_common);
- __ leal(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
+ __ lea(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
// setup rsp so we can push the "result" as needed.
- __ movl(rsp, STATE(_stack)); // trim stack (is prepushed)
- __ addl(rsp, wordSize); // undo prepush
+ __ movptr(rsp, STATE(_stack)); // trim stack (is prepushed)
+ __ addptr(rsp, wordSize); // undo prepush
ExternalAddress tosca_to_stack((address)CppInterpreter::_tosca_to_stack);
- // Address index(noreg, rcx, Address::times_4);
- __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_4)));
- // __ movl(rcx, Address(noreg, rcx, Address::times_4, int(AbstractInterpreter::_tosca_to_stack)));
+ // Address index(noreg, rcx, Address::times_ptr);
+ __ movptr(rcx, ArrayAddress(tosca_to_stack, Address(noreg, rcx, Address::times_ptr)));
+ // __ movl(rcx, Address(noreg, rcx, Address::times_ptr, int(AbstractInterpreter::_tosca_to_stack)));
__ call(rcx); // call result converter
__ movl(STATE(_msg), (int)BytecodeInterpreter::deopt_resume);
- __ leal(rsp, Address(rsp, -wordSize)); // prepush stack (result if any already present)
- __ movl(STATE(_stack), rsp); // inform interpreter of new stack depth (parameters removed,
+ __ lea(rsp, Address(rsp, -wordSize)); // prepush stack (result if any already present)
+ __ movptr(STATE(_stack), rsp); // inform interpreter of new stack depth (parameters removed,
// result if any on stack already )
- __ movl(rsp, STATE(_stack_limit)); // restore expression stack to full depth
+ __ movptr(rsp, STATE(_stack_limit)); // restore expression stack to full depth
}
// Generate the code to handle a more_monitors message from the c++ interpreter
void CppInterpreterGenerator::generate_more_monitors() {
- const Register state = rsi;
Label entry, loop;
const int entry_size = frame::interpreter_frame_monitor_size() * wordSize;
- // 1. compute new pointers // rsp: old expression stack top
- __ movl(rdx, STATE(_stack_base)); // rdx: old expression stack bottom
- __ subl(rsp, entry_size); // move expression stack top limit
- __ subl(STATE(_stack), entry_size); // update interpreter stack top
- __ movl(STATE(_stack_limit), rsp); // inform interpreter
- __ subl(rdx, entry_size); // move expression stack bottom
- __ movl(STATE(_stack_base), rdx); // inform interpreter
- __ movl(rcx, STATE(_stack)); // set start value for copy loop
+ // 1. compute new pointers // rsp: old expression stack top
+ __ movptr(rdx, STATE(_stack_base)); // rdx: old expression stack bottom
+ __ subptr(rsp, entry_size); // move expression stack top limit
+ __ subptr(STATE(_stack), entry_size); // update interpreter stack top
+ __ subptr(STATE(_stack_limit), entry_size); // inform interpreter
+ __ subptr(rdx, entry_size); // move expression stack bottom
+ __ movptr(STATE(_stack_base), rdx); // inform interpreter
+ __ movptr(rcx, STATE(_stack)); // set start value for copy loop
__ jmp(entry);
// 2. move expression stack contents
__ bind(loop);
- __ movl(rbx, Address(rcx, entry_size)); // load expression stack word from old location
- __ movl(Address(rcx, 0), rbx); // and store it at new location
- __ addl(rcx, wordSize); // advance to next word
+ __ movptr(rbx, Address(rcx, entry_size)); // load expression stack word from old location
+ __ movptr(Address(rcx, 0), rbx); // and store it at new location
+ __ addptr(rcx, wordSize); // advance to next word
__ bind(entry);
- __ cmpl(rcx, rdx); // check if bottom reached
- __ jcc(Assembler::notEqual, loop); // if not at bottom then copy next word
+ __ cmpptr(rcx, rdx); // check if bottom reached
+ __ jcc(Assembler::notEqual, loop); // if not at bottom then copy next word
// now zero the slot so we can find it.
- __ movl(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), (int) NULL);
+ __ movptr(Address(rdx, BasicObjectLock::obj_offset_in_bytes()), (int32_t) NULL_WORD);
__ movl(STATE(_msg), (int)BytecodeInterpreter::got_monitors);
}
@@ -1517,7 +1586,7 @@ void CppInterpreterGenerator::generate_m
//
// rbx: methodOop
// rcx: receiver - unused (retrieved from stack as needed)
-// rsi: previous frame manager state (NULL from the call_stub/c1/c2)
+// rsi/r13: previous frame manager state (NULL from the call_stub/c1/c2)
//
//
// Stack layout at entry
@@ -1539,7 +1608,7 @@ address InterpreterGenerator::generate_n
address InterpreterGenerator::generate_normal_entry(bool synchronized) {
// rbx: methodOop
- // rsi: sender sp
+ // rsi/r13: sender sp
// Because we redispatch "recursive" interpreter entries thru this same entry point
// the "input" register usage is a little strange and not what you expect coming
@@ -1562,12 +1631,11 @@ address InterpreterGenerator::generate_n
if (UseFastAccessorMethods && !synchronized) __ bind(fast_accessor_slow_entry_path);
Label dispatch_entry_2;
- __ movl(rcx, rsi);
- __ movl(rsi, 0); // no current activation
+ __ movptr(rcx, sender_sp_on_entry);
+ __ movptr(state, (int32_t)NULL_WORD); // no current activation
__ jmp(dispatch_entry_2);
- const Register state = rsi; // current activation object, valid on entry
const Register locals = rdi;
Label re_dispatch;
@@ -1575,12 +1643,12 @@ address InterpreterGenerator::generate_n
__ bind(re_dispatch);
// save sender sp (doesn't include return address
- __ leal(rcx, Address(rsp, wordSize));
+ __ lea(rcx, Address(rsp, wordSize));
__ bind(dispatch_entry_2);
// save sender sp
- __ pushl(rcx);
+ __ push(rcx);
const Address size_of_parameters(rbx, methodOopDesc::size_of_parameters_offset());
const Address size_of_locals (rbx, methodOopDesc::size_of_locals_offset());
@@ -1597,7 +1665,7 @@ address InterpreterGenerator::generate_n
// rcx: size of parameters
__ load_unsigned_word(rdx, size_of_locals); // get size of locals in words
- __ subl(rdx, rcx); // rdx = no. of additional locals
+ __ subptr(rdx, rcx); // rdx = no. of additional locals
// see if we've got enough room on the stack for locals plus overhead.
generate_stack_overflow_check(); // C++
@@ -1609,26 +1677,26 @@ address InterpreterGenerator::generate_n
// compute beginning of parameters (rdi)
- __ leal(locals, Address(rsp, rcx, Address::times_4, wordSize));
+ __ lea(locals, Address(rsp, rcx, Address::times_ptr, wordSize));
// save sender's sp
// __ movl(rcx, rsp);
// get sender's sp
- __ popl(rcx);
+ __ pop(rcx);
// get return address
- __ popl(rax);
+ __ pop(rax);
// rdx - # of additional locals
// allocate space for locals
// explicitly initialize locals
{
Label exit, loop;
- __ testl(rdx, rdx);
+ __ testl(rdx, rdx); // (32bit ok)
__ jcc(Assembler::lessEqual, exit); // do nothing if rdx <= 0
__ bind(loop);
- __ pushl((int)NULL); // initialize local variables
+ __ push((int32_t)NULL_WORD); // initialize local variables
__ decrement(rdx); // until everything initialized
__ jcc(Assembler::greater, loop);
__ bind(exit);
@@ -1664,17 +1732,21 @@ address InterpreterGenerator::generate_n
__ bind(call_interpreter_2);
{
- const Register thread = rcx;
-
- __ pushl(state); // push arg to interpreter
- __ movl(thread, STATE(_thread));
+ const Register thread = NOT_LP64(rcx) LP64_ONLY(r15_thread);
+
+#ifdef _LP64
+ __ mov(c_rarg0, state);
+#else
+ __ push(state); // push arg to interpreter
+ __ movptr(thread, STATE(_thread));
+#endif // _LP64
// We can setup the frame anchor with everything we want at this point
// as we are thread_in_Java and no safepoints can occur until we go to
// vm mode. We do have to clear flags on return from vm but that is it
//
- __ movl(Address(thread, JavaThread::last_Java_fp_offset()), rbp);
- __ movl(Address(thread, JavaThread::last_Java_sp_offset()), rsp);
+ __ movptr(Address(thread, JavaThread::last_Java_fp_offset()), rbp);
+ __ movptr(Address(thread, JavaThread::last_Java_sp_offset()), rsp);
// Call the interpreter
@@ -1682,14 +1754,14 @@ address InterpreterGenerator::generate_n
RuntimeAddress checking(CAST_FROM_FN_PTR(address, BytecodeInterpreter::runWithChecks));
__ call(JvmtiExport::can_post_interpreter_events() ? checking : normal);
- __ popl(rax); // discard parameter to run
+ NOT_LP64(__ pop(rax);) // discard parameter to run
//
// state is preserved since it is callee saved
//
// reset_last_Java_frame
- __ movl(thread, STATE(_thread));
+ NOT_LP64(__ movl(thread, STATE(_thread));)
__ reset_last_Java_frame(thread, true, true);
}
@@ -1703,15 +1775,15 @@ address InterpreterGenerator::generate_n
Label bad_msg;
Label do_OSR;
- __ cmpl(rdx, (int)BytecodeInterpreter::call_method);
+ __ cmpl(rdx, (int32_t)BytecodeInterpreter::call_method);
__ jcc(Assembler::equal, call_method);
- __ cmpl(rdx, (int)BytecodeInterpreter::return_from_method);
+ __ cmpl(rdx, (int32_t)BytecodeInterpreter::return_from_method);
__ jcc(Assembler::equal, return_from_interpreted_method);
- __ cmpl(rdx, (int)BytecodeInterpreter::do_osr);
+ __ cmpl(rdx, (int32_t)BytecodeInterpreter::do_osr);
__ jcc(Assembler::equal, do_OSR);
- __ cmpl(rdx, (int)BytecodeInterpreter::throwing_exception);
+ __ cmpl(rdx, (int32_t)BytecodeInterpreter::throwing_exception);
__ jcc(Assembler::equal, throw_exception);
- __ cmpl(rdx, (int)BytecodeInterpreter::more_monitors);
+ __ cmpl(rdx, (int32_t)BytecodeInterpreter::more_monitors);
__ jcc(Assembler::notEqual, bad_msg);
// Allocate more monitor space, shuffle expression stack....
@@ -1724,8 +1796,8 @@ address InterpreterGenerator::generate_n
unctrap_frame_manager_entry = __ pc();
//
// Load the registers we need.
- __ leal(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
- __ movl(rsp, STATE(_stack_limit)); // restore expression stack to full depth
+ __ lea(state, Address(rbp, -(int)sizeof(BytecodeInterpreter)));
+ __ movptr(rsp, STATE(_stack_limit)); // restore expression stack to full depth
__ jmp(call_interpreter_2);
@@ -1757,13 +1829,17 @@ address InterpreterGenerator::generate_n
Label unwind_and_forward;
// restore state pointer.
- __ leal(state, Address(rbp, -sizeof(BytecodeInterpreter)));
-
- __ movl(rbx, STATE(_method)); // get method
+ __ lea(state, Address(rbp, -sizeof(BytecodeInterpreter)));
+
+ __ movptr(rbx, STATE(_method)); // get method
+#ifdef _LP64
+ __ movptr(Address(r15_thread, Thread::pending_exception_offset()), rax);
+#else
__ movl(rcx, STATE(_thread)); // get thread
// Store exception with interpreter will expect it
- __ movl(Address(rcx, Thread::pending_exception_offset()), rax);
+ __ movptr(Address(rcx, Thread::pending_exception_offset()), rax);
+#endif // _LP64
// is current frame vanilla or native?