changeset 27346:197538942788

Merge
author thartmann
date Thu, 28 Jan 2016 09:49:17 +0100
parents 119702fc4dea ec13f1d4a9d3
children 1edcfb47e131
files make/gensrc/Gensrc-jdk.vm.ci.gmk src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp src/cpu/ppc/vm/abstractInterpreter_ppc.cpp src/cpu/ppc/vm/sharedRuntime_ppc.cpp src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp src/cpu/sparc/vm/macroAssembler_sparc.cpp src/cpu/x86/vm/macroAssembler_x86_libm.cpp src/jdk.vm.ci/share/classes/jdk.vm.ci.code/src/jdk/vm/ci/code/CompilationResult.java src/jdk.vm.ci/share/classes/jdk.vm.ci.code/src/jdk/vm/ci/code/DataSection.java src/jdk.vm.ci/share/classes/jdk.vm.ci.code/src/jdk/vm/ci/code/InfopointReason.java src/jdk.vm.ci/share/classes/jdk.vm.ci.service.processor/src/META-INF/services/javax.annotation.processing.Processor src/jdk.vm.ci/share/classes/jdk.vm.ci.service.processor/src/jdk/vm/ci/service/processor/ServiceProviderProcessor.java src/jdk.vm.ci/share/classes/jdk.vm.ci.service/.checkstyle_checks.xml src/jdk.vm.ci/share/classes/jdk.vm.ci.service/src/jdk/vm/ci/service/ServiceProvider.java src/jdk.vm.ci/share/classes/jdk.vm.ci.service/src/jdk/vm/ci/service/Services.java src/os/aix/vm/decoder_aix.hpp src/os/aix/vm/misc_aix.hpp src/os/aix/vm/os_aix.cpp src/os/aix/vm/os_aix.inline.hpp src/os/aix/vm/porting_aix.cpp src/os/aix/vm/porting_aix.hpp src/os_cpu/aix_ppc/vm/os_aix_ppc.cpp src/os_cpu/aix_ppc/vm/os_aix_ppc.hpp src/share/vm/c1/c1_Runtime1.cpp src/share/vm/ci/ciEnv.cpp src/share/vm/classfile/javaClasses.cpp src/share/vm/classfile/javaClasses.hpp src/share/vm/classfile/systemDictionary.cpp src/share/vm/code/nmethod.cpp src/share/vm/compiler/compileBroker.cpp src/share/vm/interpreter/interpreterRuntime.cpp src/share/vm/interpreter/linkResolver.cpp src/share/vm/jvmci/jvmciCompilerToVM.cpp src/share/vm/jvmci/jvmciJavaClasses.hpp src/share/vm/oops/method.cpp src/share/vm/prims/methodHandles.cpp src/share/vm/runtime/globals.hpp src/share/vm/runtime/sharedRuntime.cpp src/share/vm/runtime/vmStructs.cpp test/TEST.groups
diffstat 440 files changed, 15150 insertions(+), 9624 deletions(-) [+]
line wrap: on
line diff
--- a/.mx.jvmci/mx_jvmci.py	Tue Jan 26 17:13:18 2016 +0100
+++ b/.mx.jvmci/mx_jvmci.py	Thu Jan 28 09:49:17 2016 +0100
@@ -40,6 +40,8 @@
 
 _suite = mx.suite('jvmci')
 
+JVMCI_VERSION = 9
+
 """
 Top level directory of the JDK source workspace.
 """
@@ -153,11 +155,17 @@
     def deploy(self, jdkDir):
         mx.nyi('deploy', self)
 
+    def post_parse_cmd_line(self):
+        self.set_archiveparticipant()
+
+    def set_archiveparticipant(self):
+        dist = self.dist()
+        dist.set_archiveparticipant(JVMCIArchiveParticipant(dist))
+
 class ExtJDKDeployedDist(JvmciJDKDeployedDist):
     def __init__(self, name):
         JvmciJDKDeployedDist.__init__(self, name)
 
-
 """
 The monolithic JVMCI distribution is deployed through use of -Xbootclasspath/p
 so that it's not necessary to run JDK make after editing JVMCI sources.
@@ -186,7 +194,7 @@
         # JDK9 must be bootstrapped with a JDK8
         compliance = mx.JavaCompliance('8')
         jdk8 = mx.get_jdk(compliance.exactMatch, versionDescription=compliance.value)
-        cmd = ['sh', 'configure', '--with-debug-level=' + _vm.debugLevel, '--disable-debug-symbols', '--disable-precompiled-headers',
+        cmd = ['sh', 'configure', '--with-debug-level=' + _vm.debugLevel, '--with-native-debug-symbols=none', '--disable-precompiled-headers',
                '--with-jvm-variants=' + _vm.jvmVariant, '--disable-warnings-as-errors', '--with-boot-jdk=' + jdk8.home]
         mx.run(cmd, cwd=_jdkSourceRoot)
     cmd = [mx.gmake_cmd(), 'CONF=' + _vm.debugLevel]
@@ -205,7 +213,15 @@
     mx.run(cmd, cwd=_jdkSourceRoot)
 
     if 'images' in cmd:
-        _create_jdk_bundle(jdkBuildDir)
+        jdkImageDir = join(jdkBuildDir, 'images', 'jdk')
+
+        # The OpenJDK build creates an empty cacerts file so copy one from
+        # the default JDK (which is assumed to be an OracleJDK)
+        srcCerts = join(mx.get_jdk(tag='default').home, 'jre', 'lib', 'security', 'cacerts')
+        dstCerts = join(jdkImageDir, 'lib', 'security', 'cacerts')
+        shutil.copyfile(srcCerts, dstCerts)
+
+        _create_jdk_bundle(jdkBuildDir, _vm.debugLevel, jdkImageDir)
 
 def _get_jdk_bundle_arches():
     """
@@ -220,15 +236,14 @@
         return ['sparcv9']
     mx.abort('Unsupported JDK bundle arch: ' + cpu)
 
-def _create_jdk_bundle(jdkBuildDir):
+def _create_jdk_bundle(jdkBuildDir, debugLevel, jdkImageDir):
     """
     Creates a tar.gz JDK archive, an accompanying tar.gz.sha1 file with its
     SHA1 signature plus symlinks to the archive for non-canonical architecture names.
     """
-    jdkImageDir = join(jdkBuildDir, 'images', 'jdk')
 
     arches = _get_jdk_bundle_arches()
-    jdkTgzPath = join(_suite.get_output_root(), 'jdk-bundles', 'jdk9-{}-{}.tar.gz'.format(_get_openjdk_os(), arches[0]))
+    jdkTgzPath = join(_suite.get_output_root(), 'jdk-bundles', 'jdk9-{}-{}-{}.tar.gz'.format(debugLevel, _get_openjdk_os(), arches[0]))
     with mx.Archiver(jdkTgzPath, kind='tgz') as arc:
         mx.log('Creating ' + jdkTgzPath)
         for root, _, filenames in os.walk(jdkImageDir):
@@ -236,10 +251,6 @@
                 f = join(root, name)
                 arcname = 'jdk1.9.0/' + os.path.relpath(f, jdkImageDir)
                 arc.zf.add(name=f, arcname=arcname, recursive=False)
-        # The OpenJDK build creates an empty cacerts file so grab one from
-        # the default JDK which is assumed to be an OracleJDK
-        cacerts = join(mx.get_jdk(tag='default').home, 'jre', 'lib', 'security', 'cacerts')
-        arc.zf.add(name=cacerts, arcname='jdk1.9.0/lib/security/cacerts')
 
     with open(jdkTgzPath + '.sha1', 'w') as fp:
         mx.log('Creating ' + jdkTgzPath + '.sha1')
@@ -252,7 +263,7 @@
         os.symlink(source, link_name)
 
     for arch in arches[1:]:
-        link_name = join(_suite.get_output_root(), 'jdk-bundles', 'jdk9-{}-{}.tar.gz'.format(_get_openjdk_os(), arch))
+        link_name = join(_suite.get_output_root(), 'jdk-bundles', 'jdk9-{}-{}-{}.tar.gz'.format(debugLevel, _get_openjdk_os(), arch))
         jdkTgzName = os.path.basename(jdkTgzPath)
         _create_link(jdkTgzName, link_name)
         _create_link(jdkTgzName + '.sha1', link_name + '.sha1')
@@ -668,15 +679,10 @@
 
     def __opened__(self, arc, srcArc, services):
         self.services = services
+        self.jvmciServices = services
         self.arc = arc
 
     def __add__(self, arcname, contents):
-        if arcname.startswith('META-INF/jvmci.providers/'):
-            provider = arcname[len('META-INF/jvmci.providers/'):]
-            for service in contents.strip().split(os.linesep):
-                assert service
-                self.services.setdefault(service, []).append(provider)
-            return True
         return False
 
     def __addsrc__(self, arcname, contents):
@@ -757,6 +763,14 @@
 
         args = ['-Xbootclasspath/p:' + dep.classpath_repr() for dep in _jvmci_bootclasspath_prepends] + args
 
+        # Remove JVMCI jars from class path. They are only necessary when
+        # compiling with a javac from JDK8 or earlier.
+        cpIndex, cp = mx.find_classpath_arg(args)
+        if cp:
+            excluded = frozenset([dist.path for dist in _suite.dists])
+            cp = os.pathsep.join([e for e in cp.split(os.pathsep) if e not in excluded])
+            args[cpIndex] = cp
+
         jvmciModeArgs = _jvmciModes[_vm.jvmciMode]
         if jvmciModeArgs:
             bcpDeps = [jdkDist.dist() for jdkDist in jdkDeployedDists]
@@ -812,7 +826,7 @@
         _jvmci_jdks[debugLevel] = jdk
     return jdk
 
-class JVMCIJDKFactory(mx.JDKFactory):
+class JVMCI9JDKFactory(mx.JDKFactory):
     def getJDKConfig(self):
         jdk = get_jvmci_jdk(_vm.debugLevel)
         return jdk
@@ -836,8 +850,9 @@
 mx.add_argument('--jdk-debug-level', '--vmbuild', action='store', choices=_jdkDebugLevels + sorted(_legacyVmbuilds.viewkeys()), help='the JDK debug level to build/run (default: ' + _vm.debugLevel + ')')
 mx.add_argument('-I', '--use-jdk-image', action='store_true', help='build/run JDK image instead of exploded JDK')
 
+mx.addJDKFactory(_JVMCI_JDK_TAG, mx.JavaCompliance('9'), JVMCI9JDKFactory())
+
 def mx_post_parse_cmd_line(opts):
-    mx.addJDKFactory(_JVMCI_JDK_TAG, mx.JavaCompliance('9'), JVMCIJDKFactory())
     mx.set_java_command_default_jdk_tag(_JVMCI_JDK_TAG)
 
     jdkTag = mx.get_jdk_option().tag
@@ -864,6 +879,39 @@
     _vm.update(jvmVariant, debugLevel, jvmciMode)
 
     for jdkDist in jdkDeployedDists:
-        dist = jdkDist.dist()
-        if isinstance(jdkDist, JvmciJDKDeployedDist):
-            dist.set_archiveparticipant(JVMCIArchiveParticipant(dist))
+        jdkDist.post_parse_cmd_line()
+
+def _update_JDK9_STUBS_library():
+    """
+    Sets the "path" and "sha1" attributes of the "JDK9_STUBS" library.
+    """
+    jdk9InternalLib = _suite.suiteDict['libraries']['JDK9_STUBS']
+    jarInputDir = join(_suite.get_output_root(), 'jdk9-stubs')
+    jarPath = join(_suite.get_output_root(), 'jdk9-stubs.jar')
+
+    stubs = [
+        ('jdk.internal.misc', 'VM', """package jdk.internal.misc;
+public class VM {
+    public static String getSavedProperty(String key) {
+        throw new InternalError("should not reach here");
+    }
+}
+""")
+    ]
+
+    if not exists(jarPath):
+        sourceFiles = []
+        for (package, className, source) in stubs:
+            sourceFile = join(jarInputDir, package.replace('.', os.sep), className + '.java')
+            mx.ensure_dir_exists(os.path.dirname(sourceFile))
+            with open(sourceFile, 'w') as fp:
+                fp.write(source)
+            sourceFiles.append(sourceFile)
+        jdk = mx.get_jdk(tag='default')
+        mx.run([jdk.javac, '-d', jarInputDir] + sourceFiles)
+        mx.run([jdk.jar, 'cf', jarPath, '.'], cwd=jarInputDir)
+
+    jdk9InternalLib['path'] = jarPath
+    jdk9InternalLib['sha1'] = mx.sha1OfFile(jarPath)
+
+_update_JDK9_STUBS_library()
--- a/.mx.jvmci/suite.py	Tue Jan 26 17:13:18 2016 +0100
+++ b/.mx.jvmci/suite.py	Thu Jan 28 09:49:17 2016 +0100
@@ -1,5 +1,5 @@
 suite = {
-  "mxversion" : "5.5.12",
+  "mxversion" : "5.6.11",
   "name" : "jvmci",
   "url" : "http://openjdk.java.net/projects/graal",
   "developer" : {
@@ -24,7 +24,7 @@
 
   "defaultLicense" : "GPLv2-CPE",
 
-  # This puts mx/ as a sibiling of the JDK build configuration directories
+  # This puts mx/ as a sibling of the JDK build configuration directories
   # (e.g., macosx-x86_64-normal-server-release).
   "outputRoot" : "../build/mx/hotspot",
 
@@ -32,8 +32,6 @@
 
   "libraries" : {
 
-    # ------------- Libraries -------------
-
     "HCFDIS" : {
       "urls" : ["https://lafo.ssw.uni-linz.ac.at/pub/hcfdis-3.jar"],
       "sha1" : "a71247c6ddb90aad4abf7c77e501acc60674ef57",
@@ -53,34 +51,32 @@
       "sha1" : "122b87ca88e41a415cf8b523fd3d03b4325134a3",
       "urls" : ["https://lafo.ssw.uni-linz.ac.at/pub/graal-external-deps/batik-all-1.7.jar"],
     },
+
+    # Stubs for classes introduced in JDK9 that allow compilation with a JDK8 javac and Eclipse.
+    # The "path" and "sha1" attributes are added when mx_jvmci is loaded
+    # (see mx_jvmci._update_JDK9_STUBS_library()).
+    "JDK9_STUBS" : {
+        "license" : "GPLv2-CPE",
+     },
   },
 
   "projects" : {
 
     # ------------- JVMCI:Service -------------
 
-    "jdk.vm.ci.service" : {
+    "jdk.vm.ci.services" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
 
-    "jdk.vm.ci.service.processor" : {
-      "subDir" : "src/jdk.vm.ci/share/classes",
-      "sourceDirs" : ["src"],
-      "dependencies" : ["jdk.vm.ci.service"],
-      "checkstyle" : "jdk.vm.ci.service",
-      "javaCompliance" : "1.8",
-      "workingSets" : "JVMCI,Codegen,HotSpot",
-    },
-
     # ------------- JVMCI:API -------------
 
     "jdk.vm.ci.common" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
@@ -88,7 +84,7 @@
     "jdk.vm.ci.meta" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
@@ -97,7 +93,7 @@
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
       "dependencies" : ["jdk.vm.ci.meta"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
@@ -108,7 +104,7 @@
       "dependencies" : [
         "jdk.vm.ci.code",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
@@ -121,7 +117,7 @@
         "jdk.vm.ci.common",
         "jdk.vm.ci.runtime",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "API,JVMCI",
     },
@@ -129,7 +125,7 @@
     "jdk.vm.ci.inittimer" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI",
     },
@@ -140,7 +136,7 @@
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
       "dependencies" : ["jdk.vm.ci.code"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,AArch64",
     },
@@ -149,7 +145,7 @@
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
       "dependencies" : ["jdk.vm.ci.code"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,AMD64",
     },
@@ -158,7 +154,7 @@
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
       "dependencies" : ["jdk.vm.ci.code"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,SPARC",
     },
@@ -171,9 +167,10 @@
         "jdk.vm.ci.common",
         "jdk.vm.ci.inittimer",
         "jdk.vm.ci.runtime",
-        "jdk.vm.ci.service",
+        "jdk.vm.ci.services",
+        "JDK9_STUBS",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI",
     },
@@ -181,7 +178,7 @@
     "jdk.vm.ci.hotspotvmconfig" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "sourceDirs" : ["src"],
-      "checkstyle" : "jdk.vm.ci.service",
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,HotSpot",
     },
@@ -193,10 +190,7 @@
         "jdk.vm.ci.aarch64",
         "jdk.vm.ci.hotspot",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
-      "annotationProcessors" : [
-        "JVMCI_SERVICE_PROCESSOR",
-      ],
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,HotSpot,AArch64",
     },
@@ -208,10 +202,7 @@
         "jdk.vm.ci.amd64",
         "jdk.vm.ci.hotspot",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
-      "annotationProcessors" : [
-        "JVMCI_SERVICE_PROCESSOR",
-      ],
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,HotSpot,AMD64",
     },
@@ -223,10 +214,7 @@
         "jdk.vm.ci.sparc",
         "jdk.vm.ci.hotspot",
       ],
-      "checkstyle" : "jdk.vm.ci.service",
-      "annotationProcessors" : [
-        "JVMCI_SERVICE_PROCESSOR",
-      ],
+      "checkstyle" : "jdk.vm.ci.services",
       "javaCompliance" : "1.8",
       "workingSets" : "JVMCI,HotSpot,SPARC",
     },
@@ -241,9 +229,9 @@
 
     # ------------- Distributions -------------
 
-    "JVMCI_SERVICE" : {
+    "JVMCI_SERVICES" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
-      "dependencies" : ["jdk.vm.ci.service"],
+      "dependencies" : ["jdk.vm.ci.services"],
     },
 
     "JVMCI_API" : {
@@ -257,7 +245,7 @@
         "jdk.vm.ci.sparc",
       ],
       "distDependencies" : [
-        "JVMCI_SERVICE",
+        "JVMCI_SERVICES",
       ],
     },
 
@@ -277,7 +265,7 @@
       ],
       "distDependencies" : [
         "JVMCI_HOTSPOTVMCONFIG",
-        "JVMCI_SERVICE",
+        "JVMCI_SERVICES",
         "JVMCI_API",
       ],
     },
@@ -293,28 +281,18 @@
       "exclude" : ["mx:JUNIT"],
     },
 
-
-    "JVMCI_SERVICE_PROCESSOR" : {
-      "subDir" : "src/jdk.vm.ci/share/classes",
-      "dependencies" : ["jdk.vm.ci.service.processor"],
-      "distDependencies" : [
-        "JVMCI_SERVICE",
-      ],
-    },
-
     # This exists to have a monolithic jvmci.jar file which simplifies
     # using the -Xoverride option in JDK9.
     "JVMCI" : {
       "subDir" : "src/jdk.vm.ci/share/classes",
       "overlaps" : [
         "JVMCI_API",
-        "JVMCI_SERVICE",
+        "JVMCI_SERVICES",
         "JVMCI_HOTSPOT",
         "JVMCI_HOTSPOTVMCONFIG",
-        "JVMCI_SERVICE_PROCESSOR",
       ],
       "dependencies" : [
-        "jdk.vm.ci.service",
+        "jdk.vm.ci.services",
         "jdk.vm.ci.inittimer",
         "jdk.vm.ci.runtime",
         "jdk.vm.ci.common",
@@ -325,8 +303,8 @@
         "jdk.vm.ci.hotspot.aarch64",
         "jdk.vm.ci.hotspot.amd64",
         "jdk.vm.ci.hotspot.sparc",
-        "jdk.vm.ci.service.processor"
       ],
+      "exclude" : ["JDK9_STUBS"]
     },
   },
 }
--- a/make/aix/Makefile	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/Makefile	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2015 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2015 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/buildtree.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/buildtree.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/compiler2.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/compiler2.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/debug.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/debug.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/defs.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/defs.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/fastdebug.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/fastdebug.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/jsig.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/jsig.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2005, 2014, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/jvmti.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/jvmti.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/ppc64.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/ppc64.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2004, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2015 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2015 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/product.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/product.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/tiered.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/tiered.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2006, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2015 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2015 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/vm.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/vm.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/aix/makefiles/xlc.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/aix/makefiles/xlc.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
-# Copyright (c) 2012, 2015 SAP. All rights reserved.
+# Copyright (c) 2012, 2015 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/gensrc/Gensrc-jdk.vm.ci.gmk	Tue Jan 26 17:13:18 2016 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-#
-# Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved.
-# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-#
-# This code is free software; you can redistribute it and/or modify it
-# under the terms of the GNU General Public License version 2 only, as
-# published by the Free Software Foundation.  Oracle designates this
-# particular file as subject to the "Classpath" exception as provided
-# by Oracle in the LICENSE file that accompanied this code.
-#
-# This code is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-# version 2 for more details (a copy is included in the LICENSE file that
-# accompanied this code).
-#
-# You should have received a copy of the GNU General Public License version
-# 2 along with this work; if not, write to the Free Software Foundation,
-# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-#
-# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-# or visit www.oracle.com if you need additional information or have any
-# questions.
-#
-
-default: all
-
-include $(SPEC)
-include MakeBase.gmk
-include JavaCompilation.gmk
-include SetupJavaCompilers.gmk
-
-GENSRC_DIR := $(SUPPORT_OUTPUTDIR)/gensrc/jdk.vm.ci
-SRC_DIR := $(HOTSPOT_TOPDIR)/src/jdk.vm.ci/share/classes
-
-################################################################################
-# Compile the annotation processor
-
-$(eval $(call SetupJavaCompilation, BUILD_JVMCI_SERVICE, \
-    SETUP := GENERATE_OLDBYTECODE, \
-    SRC := $(SRC_DIR)/jdk.vm.ci.service/src \
-        $(SRC_DIR)/jdk.vm.ci.service.processor/src, \
-    BIN := $(BUILDTOOLS_OUTPUTDIR)/jvmci_service, \
-    JAR := $(BUILDTOOLS_OUTPUTDIR)/jdk.vm.ci.service.jar, \
-))
-
-################################################################################
-
-PROC_SRC_SUBDIRS := \
-    jdk.vm.ci.hotspot \
-    jdk.vm.ci.hotspot.aarch64 \
-    jdk.vm.ci.hotspot.amd64 \
-    jdk.vm.ci.hotspot.sparc \
-    jdk.vm.ci.runtime \
-    #
-
-PROC_SRC_DIRS := $(patsubst %, $(SRC_DIR)/%/src, $(PROC_SRC_SUBDIRS))
-
-PROC_SRCS := $(filter %.java, $(call CacheFind, $(PROC_SRC_DIRS)))
-
-ALL_SRC_DIRS := $(wildcard $(SRC_DIR)/*/src)
-SOURCEPATH := $(call PathList, $(ALL_SRC_DIRS))
-PROCESSOR_PATH := $(call PathList, \
-    $(BUILDTOOLS_OUTPUTDIR)/jdk.vm.ci.service.jar)
-
-$(GENSRC_DIR)/_gensrc_proc_done: $(PROC_SRCS) \
-    $(BUILD_JVMCI_SERVICE)
-	$(MKDIR) -p $(@D)
-	$(eval $(call ListPathsSafely,PROC_SRCS,$(@D)/_gensrc_proc_files))
-	$(JAVA_SMALL) $(NEW_JAVAC) \
-	    -XDignore.symbol.file \
-            -bootclasspath $(JDK_OUTPUTDIR)/modules/java.base \
-	    -sourcepath $(SOURCEPATH) \
-	    -implicit:none \
-	    -proc:only \
-	    -processorpath $(PROCESSOR_PATH) \
-	    -d $(GENSRC_DIR) \
-	    -s $(GENSRC_DIR) \
-	    @$(@D)/_gensrc_proc_files
-	$(TOUCH) $@
-
-TARGETS += $(GENSRC_DIR)/_gensrc_proc_done
-
-################################################################################
-
-$(GENSRC_DIR)/_providers_converted: $(GENSRC_DIR)/_gensrc_proc_done
-	$(MKDIR) -p $(GENSRC_DIR)/META-INF/services
-	($(CD) $(GENSRC_DIR)/META-INF/jvmci.providers && \
-	    for i in $$($(LS)); do \
-	      c=$$($(CAT) $$i | $(TR) -d '\n\r'); \
-	      $(ECHO) $$i >> $(GENSRC_DIR)/META-INF/services/$$c.tmp; \
-	    done)
-	($(CD) $(GENSRC_DIR)/META-INF/services && \
-	    for i in $$($(LS) *.tmp); do \
-	      $(MV) $$i $${i%.tmp}; \
-	    done)
-	$(TOUCH) $@
-
-TARGETS += $(GENSRC_DIR)/_providers_converted
-
-################################################################################
-
-all: $(TARGETS)
-
-.PHONY: default all
--- a/make/linux/makefiles/ppc64.make	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/linux/makefiles/ppc64.make	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved.
-# Copyright 2012, 2013 SAP AG. All rights reserved.
+# Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
--- a/make/share/makefiles/mapfile-vers	Tue Jan 26 17:13:18 2016 +0100
+++ b/make/share/makefiles/mapfile-vers	Thu Jan 28 09:49:17 2016 +0100
@@ -13,6 +13,7 @@
                 JVM_Clone;
                 JVM_ConstantPoolGetClassAt;
                 JVM_ConstantPoolGetClassAtIfLoaded;
+                JVM_ConstantPoolGetClassRefIndexAt;
                 JVM_ConstantPoolGetDoubleAt;
                 JVM_ConstantPoolGetFieldAt;
                 JVM_ConstantPoolGetFieldAtIfLoaded;
@@ -22,8 +23,11 @@
                 JVM_ConstantPoolGetMethodAt;
                 JVM_ConstantPoolGetMethodAtIfLoaded;
                 JVM_ConstantPoolGetMemberRefInfoAt;
+                JVM_ConstantPoolGetNameAndTypeRefInfoAt;
+                JVM_ConstantPoolGetNameAndTypeRefIndexAt;
                 JVM_ConstantPoolGetSize;
                 JVM_ConstantPoolGetStringAt;
+                JVM_ConstantPoolGetTagAt;
                 JVM_ConstantPoolGetUTF8At;
                 JVM_CountStackFrames;
                 JVM_CurrentClassLoader;
--- a/src/cpu/aarch64/vm/aarch64.ad	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad	Thu Jan 28 09:49:17 2016 +0100
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
 // Copyright (c) 2014, Red Hat Inc. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
@@ -577,7 +577,7 @@
     R26
  /* R27, */                     // heapbase
  /* R28, */                     // thread
-    R29,                        // fp
+ /* R29, */                     // fp
  /* R30, */                     // lr
  /* R31 */                      // sp
 );
@@ -646,7 +646,7 @@
     R26, R26_H,
  /* R27, R27_H, */              // heapbase
  /* R28, R28_H, */              // thread
-    R29, R29_H,                 // fp
+ /* R29, R29_H, */              // fp
  /* R30, R30_H, */              // lr
  /* R31, R31_H */               // sp
 );
@@ -4442,11 +4442,7 @@
 
   enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
     MacroAssembler _masm(&cbuf);
-    address page = (address)$src$$constant;
-    Register dst_reg = as_Register($dst$$reg);
-    unsigned long off;
-    __ adrp(dst_reg, ExternalAddress(page), off);
-    assert(off == 0, "assumed offset == 0");
+    __ load_byte_map_base($dst$$Register);
   %}
 
   enc_class aarch64_enc_mov_n(iRegN dst, immN src) %{
@@ -6673,6 +6669,14 @@
 
 //----------PIPELINE-----------------------------------------------------------
 // Rules which define the behavior of the target architectures pipeline.
+
+// For specific pipelines, eg A53, define the stages of that pipeline
+//pipe_desc(ISS, EX1, EX2, WR);
+#define ISS S0
+#define EX1 S1
+#define EX2 S2
+#define WR  S3
+
 // Integer ALU reg operation
 pipeline %{
 
@@ -6707,12 +6711,499 @@
 //----------PIPELINE DESCRIPTION-----------------------------------------------
 // Pipeline Description specifies the stages in the machine's pipeline
 
-pipe_desc(ISS, EX1, EX2, WR);
+// Define the pipeline as a generic 6 stage pipeline
+pipe_desc(S0, S1, S2, S3, S4, S5);
 
 //----------PIPELINE CLASSES---------------------------------------------------
 // Pipeline Classes describe the stages in which input and output are
 // referenced by the hardware pipeline.
 
+pipe_class fp_dop_reg_reg_s(vRegF dst, vRegF src1, vRegF src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_dop_reg_reg_d(vRegD dst, vRegD src1, vRegD src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_uop_s(vRegF dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_uop_d(vRegD dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2f(vRegF dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2d(vRegD dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2i(iRegINoSp dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_f2l(iRegLNoSp dst, vRegF src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_i2f(vRegF dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_l2f(vRegF dst, iRegL src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2i(iRegINoSp dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_d2l(iRegLNoSp dst, vRegD src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_i2d(vRegD dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_l2d(vRegD dst, iRegIorL2I src)
+%{
+  single_instruction;
+  src    : S1(read);
+  dst    : S5(write);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_div_s(vRegF dst, vRegF src1, vRegF src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_div_d(vRegD dst, vRegD src1, vRegD src2)
+%{
+  single_instruction;
+  src1   : S1(read);
+  src2   : S2(read);
+  dst    : S5(write);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class fp_cond_reg_reg_s(vRegF dst, vRegF src1, vRegF src2, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : S1(read);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_cond_reg_reg_d(vRegD dst, vRegD src1, vRegD src2, rFlagsReg cr)
+%{
+  single_instruction;
+  cr     : S1(read);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_imm_s(vRegF dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_imm_d(vRegD dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class fp_load_constant_s(vRegF dst)
+%{
+  single_instruction;
+  dst    : S4(write);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class fp_load_constant_d(vRegD dst)
+%{
+  single_instruction;
+  dst    : S4(write);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vmul64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmul128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmla64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmla128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  dst    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdop64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S4(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS01  : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vdop128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S4(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS0   : ISS;
+  NEON_FP : S4;
+%}
+
+pipe_class vlogical64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vlogical128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src1   : S2(read);
+  src2   : S2(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift64(vecD dst, vecD src, vecX shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  shift  : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift128(vecX dst, vecX src, vecX shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  shift  : S1(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift64_imm(vecD dst, vecD src, immI shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vshift128_imm(vecX dst, vecX src, immI shift)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdop_fp64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdop_fp128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmuldiv_fp64(vecD dst, vecD src1, vecD src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vmuldiv_fp128(vecX dst, vecX src1, vecX src2)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src1   : S1(read);
+  src2   : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vsqrt_fp128(vecX dst, vecX src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vunop_fp64(vecD dst, vecD src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vunop_fp128(vecX dst, vecX src)
+%{
+  single_instruction;
+  dst    : S5(write);
+  src    : S1(read);
+  INS0   : ISS;
+  NEON_FP : S5;
+%}
+
+pipe_class vdup_reg_reg64(vecD dst, iRegI src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_reg128(vecX dst, iRegI src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_freg64(vecD dst, vRegF src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_freg128(vecX dst, vRegF src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vdup_reg_dreg128(vecX dst, vRegD src)
+%{
+  single_instruction;
+  dst    : S3(write);
+  src    : S1(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vmovi_reg_imm64(vecD dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vmovi_reg_imm128(vecX dst)
+%{
+  single_instruction;
+  dst    : S3(write);
+  INS0   : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vload_reg_mem64(vecD dst, vmem mem)
+%{
+  single_instruction;
+  dst    : S5(write);
+  mem    : ISS(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vload_reg_mem128(vecX dst, vmem mem)
+%{
+  single_instruction;
+  dst    : S5(write);
+  mem    : ISS(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vstore_reg_mem64(vecD src, vmem mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  src    : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
+pipe_class vstore_reg_mem128(vecD src, vmem mem)
+%{
+  single_instruction;
+  mem    : ISS(read);
+  src    : S2(read);
+  INS01  : ISS;
+  NEON_FP : S3;
+%}
+
 //------- Integer ALU operations --------------------------
 
 // Integer ALU reg-reg operation
@@ -7559,7 +8050,7 @@
     __ fmovs(as_FloatRegister($dst$$reg), (double)$con$$constant);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_imm_s);
 %}
 
 // Load Float Constant
@@ -7577,7 +8068,7 @@
     __ ldrs(as_FloatRegister($dst$$reg), $constantaddress($con));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_load_constant_s);
 %}
 
 // Load Packed Double Constant
@@ -7590,7 +8081,7 @@
     __ fmovd(as_FloatRegister($dst$$reg), $con$$constant);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_imm_d);
 %}
 
 // Load Double Constant
@@ -7607,7 +8098,7 @@
     __ ldrd(as_FloatRegister($dst$$reg), $constantaddress($con));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_load_constant_d);
 %}
 
 // Store Instructions
@@ -9615,7 +10106,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_s);
 %}
 
 instruct cmovUF_reg(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1,  vRegF src2)
@@ -9633,7 +10124,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_s);
 %}
 
 instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1,  vRegD src2)
@@ -9651,7 +10142,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_d);
 %}
 
 instruct cmovUD_reg(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1,  vRegD src2)
@@ -9669,7 +10160,7 @@
               cond);
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_cond_reg_reg_d);
 %}
 
 // ============================================================================
@@ -12033,7 +12524,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct addD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12048,7 +12539,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 instruct subF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
@@ -12063,7 +12554,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct subD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12078,7 +12569,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 instruct mulF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
@@ -12093,7 +12584,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_s);
 %}
 
 instruct mulD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12108,7 +12599,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_dop_reg_reg_d);
 %}
 
 // We cannot use these fused mul w add/sub ops because they don't
@@ -12256,7 +12747,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_s);
 %}
 
 instruct divD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
@@ -12271,7 +12762,7 @@
              as_FloatRegister($src2$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_d);
 %}
 
 instruct negF_reg_reg(vRegF dst, vRegF src) %{
@@ -12285,7 +12776,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_s);
 %}
 
 instruct negD_reg_reg(vRegD dst, vRegD src) %{
@@ -12299,7 +12790,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_d);
 %}
 
 instruct absF_reg(vRegF dst, vRegF src) %{
@@ -12312,7 +12803,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_s);
 %}
 
 instruct absD_reg(vRegD dst, vRegD src) %{
@@ -12325,7 +12816,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_uop_d);
 %}
 
 instruct sqrtD_reg(vRegD dst, vRegD src) %{
@@ -12338,7 +12829,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_s);
 %}
 
 instruct sqrtF_reg(vRegF dst, vRegF src) %{
@@ -12351,7 +12842,7 @@
              as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_div_d);
 %}
 
 // ============================================================================
@@ -12638,7 +13129,7 @@
     __ fcvtd(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2f);
 %}
 
 instruct convF2D_reg(vRegD dst, vRegF src) %{
@@ -12651,7 +13142,7 @@
     __ fcvts(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2d);
 %}
 
 instruct convF2I_reg_reg(iRegINoSp dst, vRegF src) %{
@@ -12664,7 +13155,7 @@
     __ fcvtzsw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2i);
 %}
 
 instruct convF2L_reg_reg(iRegLNoSp dst, vRegF src) %{
@@ -12677,7 +13168,7 @@
     __ fcvtzs(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_f2l);
 %}
 
 instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
@@ -12690,7 +13181,7 @@
     __ scvtfws(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_i2f);
 %}
 
 instruct convL2F_reg_reg(vRegF dst, iRegL src) %{
@@ -12703,7 +13194,7 @@
     __ scvtfs(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_l2f);
 %}
 
 instruct convD2I_reg_reg(iRegINoSp dst, vRegD src) %{
@@ -12716,7 +13207,7 @@
     __ fcvtzdw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2i);
 %}
 
 instruct convD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
@@ -12729,7 +13220,7 @@
     __ fcvtzd(as_Register($dst$$reg), as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_d2l);
 %}
 
 instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
@@ -12742,7 +13233,7 @@
     __ scvtfwd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_i2d);
 %}
 
 instruct convL2D_reg_reg(vRegD dst, iRegL src) %{
@@ -12755,7 +13246,7 @@
     __ scvtfd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
   %}
 
-  ins_pipe(pipe_class_default);
+  ins_pipe(fp_l2d);
 %}
 
 // stack <-> reg and reg <-> reg shuffles with no conversion
@@ -14500,7 +14991,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrs   $dst,$mem\t# vector (32 bits)" %}
   ins_encode( aarch64_enc_ldrvS(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem64);
 %}
 
 // Load vector (64 bits)
@@ -14511,7 +15002,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrd   $dst,$mem\t# vector (64 bits)" %}
   ins_encode( aarch64_enc_ldrvD(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem64);
 %}
 
 // Load Vector (128 bits)
@@ -14522,7 +15013,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "ldrq   $dst,$mem\t# vector (128 bits)" %}
   ins_encode( aarch64_enc_ldrvQ(dst, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vload_reg_mem128);
 %}
 
 // Store Vector (32 bits)
@@ -14533,7 +15024,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strs   $mem,$src\t# vector (32 bits)" %}
   ins_encode( aarch64_enc_strvS(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem64);
 %}
 
 // Store Vector (64 bits)
@@ -14544,7 +15035,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strd   $mem,$src\t# vector (64 bits)" %}
   ins_encode( aarch64_enc_strvD(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem64);
 %}
 
 // Store Vector (128 bits)
@@ -14555,7 +15046,7 @@
   ins_cost(4 * INSN_COST);
   format %{ "strq   $mem,$src\t# vector (128 bits)" %}
   ins_encode( aarch64_enc_strvQ(src, mem) );
-  ins_pipe(pipe_class_memory);
+  ins_pipe(vstore_reg_mem128);
 %}
 
 instruct replicate8B(vecD dst, iRegIorL2I src)
@@ -14568,7 +15059,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate16B(vecX dst, iRegIorL2I src)
@@ -14580,7 +15071,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate8B_imm(vecD dst, immI con)
@@ -14593,7 +15084,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T8B, $con$$constant & 0xff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate16B_imm(vecX dst, immI con)
@@ -14605,7 +15096,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T16B, $con$$constant & 0xff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate4S(vecD dst, iRegIorL2I src)
@@ -14618,7 +15109,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T4H, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate8S(vecX dst, iRegIorL2I src)
@@ -14630,7 +15121,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T8H, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate4S_imm(vecD dst, immI con)
@@ -14643,7 +15134,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T4H, $con$$constant & 0xffff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate8S_imm(vecX dst, immI con)
@@ -14655,7 +15146,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T8H, $con$$constant & 0xffff);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2I(vecD dst, iRegIorL2I src)
@@ -14667,7 +15158,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T2S, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg64);
 %}
 
 instruct replicate4I(vecX dst, iRegIorL2I src)
@@ -14679,7 +15170,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T4S, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate2I_imm(vecD dst, immI con)
@@ -14691,7 +15182,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T2S, $con$$constant);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm64);
 %}
 
 instruct replicate4I_imm(vecX dst, immI con)
@@ -14703,7 +15194,7 @@
   ins_encode %{
     __ mov(as_FloatRegister($dst$$reg), __ T4S, $con$$constant);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2L(vecX dst, iRegL src)
@@ -14715,7 +15206,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T2D, as_Register($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct replicate2L_zero(vecX dst, immI0 zero)
@@ -14729,7 +15220,7 @@
            as_FloatRegister($dst$$reg),
            as_FloatRegister($dst$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmovi_reg_imm128);
 %}
 
 instruct replicate2F(vecD dst, vRegF src)
@@ -14742,7 +15233,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T2S,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_freg64);
 %}
 
 instruct replicate4F(vecX dst, vRegF src)
@@ -14755,7 +15246,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T4S,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_freg128);
 %}
 
 instruct replicate2D(vecX dst, vRegD src)
@@ -14768,7 +15259,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T2D,
            as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_dreg128);
 %}
 
 // ====================REDUCTION ARITHMETIC====================================
@@ -15014,7 +15505,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd16B(vecX dst, vecX src1, vecX src2)
@@ -15028,7 +15519,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd4S(vecD dst, vecD src1, vecD src2)
@@ -15043,7 +15534,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd8S(vecX dst, vecX src1, vecX src2)
@@ -15057,7 +15548,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2I(vecD dst, vecD src1, vecD src2)
@@ -15071,7 +15562,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vadd4I(vecX dst, vecX src1, vecX src2)
@@ -15085,7 +15576,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2L(vecX dst, vecX src1, vecX src2)
@@ -15099,7 +15590,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vadd2F(vecD dst, vecD src1, vecD src2)
@@ -15113,7 +15604,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp64);
 %}
 
 instruct vadd4F(vecX dst, vecX src1, vecX src2)
@@ -15127,7 +15618,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 instruct vadd2D(vecX dst, vecX src1, vecX src2)
@@ -15140,7 +15631,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 // --------------------------------- SUB --------------------------------------
@@ -15157,7 +15648,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub16B(vecX dst, vecX src1, vecX src2)
@@ -15171,7 +15662,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub4S(vecD dst, vecD src1, vecD src2)
@@ -15186,7 +15677,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub8S(vecX dst, vecX src1, vecX src2)
@@ -15200,7 +15691,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2I(vecD dst, vecD src1, vecD src2)
@@ -15214,7 +15705,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop64);
 %}
 
 instruct vsub4I(vecX dst, vecX src1, vecX src2)
@@ -15228,7 +15719,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2L(vecX dst, vecX src1, vecX src2)
@@ -15242,7 +15733,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop128);
 %}
 
 instruct vsub2F(vecD dst, vecD src1, vecD src2)
@@ -15256,7 +15747,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp64);
 %}
 
 instruct vsub4F(vecX dst, vecX src1, vecX src2)
@@ -15270,7 +15761,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 instruct vsub2D(vecX dst, vecX src1, vecX src2)
@@ -15284,7 +15775,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdop_fp128);
 %}
 
 // --------------------------------- MUL --------------------------------------
@@ -15301,7 +15792,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul64);
 %}
 
 instruct vmul8S(vecX dst, vecX src1, vecX src2)
@@ -15315,7 +15806,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul128);
 %}
 
 instruct vmul2I(vecD dst, vecD src1, vecD src2)
@@ -15329,7 +15820,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul64);
 %}
 
 instruct vmul4I(vecX dst, vecX src1, vecX src2)
@@ -15343,7 +15834,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmul128);
 %}
 
 instruct vmul2F(vecD dst, vecD src1, vecD src2)
@@ -15357,7 +15848,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp64);
 %}
 
 instruct vmul4F(vecX dst, vecX src1, vecX src2)
@@ -15371,7 +15862,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 instruct vmul2D(vecX dst, vecX src1, vecX src2)
@@ -15385,7 +15876,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 // --------------------------------- MLA --------------------------------------
@@ -15402,7 +15893,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmla8S(vecX dst, vecX src1, vecX src2)
@@ -15416,7 +15907,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 instruct vmla2I(vecD dst, vecD src1, vecD src2)
@@ -15430,7 +15921,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmla4I(vecX dst, vecX src1, vecX src2)
@@ -15444,7 +15935,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 // --------------------------------- MLS --------------------------------------
@@ -15461,7 +15952,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmls8S(vecX dst, vecX src1, vecX src2)
@@ -15475,7 +15966,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 instruct vmls2I(vecD dst, vecD src1, vecD src2)
@@ -15489,7 +15980,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla64);
 %}
 
 instruct vmls4I(vecX dst, vecX src1, vecX src2)
@@ -15503,7 +15994,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmla128);
 %}
 
 // --------------------------------- DIV --------------------------------------
@@ -15519,7 +16010,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp64);
 %}
 
 instruct vdiv4F(vecX dst, vecX src1, vecX src2)
@@ -15533,7 +16024,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 instruct vdiv2D(vecX dst, vecX src1, vecX src2)
@@ -15547,7 +16038,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vmuldiv_fp128);
 %}
 
 // --------------------------------- SQRT -------------------------------------
@@ -15561,7 +16052,7 @@
     __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
              as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vsqrt_fp128);
 %}
 
 // --------------------------------- ABS --------------------------------------
@@ -15576,7 +16067,7 @@
     __ fabs(as_FloatRegister($dst$$reg), __ T2S,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp64);
 %}
 
 instruct vabs4F(vecX dst, vecX src)
@@ -15589,7 +16080,7 @@
     __ fabs(as_FloatRegister($dst$$reg), __ T4S,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp128);
 %}
 
 instruct vabs2D(vecX dst, vecX src)
@@ -15602,7 +16093,7 @@
     __ fabs(as_FloatRegister($dst$$reg), __ T2D,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp128);
 %}
 
 // --------------------------------- NEG --------------------------------------
@@ -15617,7 +16108,7 @@
     __ fneg(as_FloatRegister($dst$$reg), __ T2S,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp64);
 %}
 
 instruct vneg4F(vecX dst, vecX src)
@@ -15630,7 +16121,7 @@
     __ fneg(as_FloatRegister($dst$$reg), __ T4S,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp128);
 %}
 
 instruct vneg2D(vecX dst, vecX src)
@@ -15643,7 +16134,7 @@
     __ fneg(as_FloatRegister($dst$$reg), __ T2D,
             as_FloatRegister($src$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vunop_fp128);
 %}
 
 // --------------------------------- AND --------------------------------------
@@ -15660,7 +16151,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vand16B(vecX dst, vecX src1, vecX src2)
@@ -15674,7 +16165,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // --------------------------------- OR ---------------------------------------
@@ -15691,7 +16182,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vor16B(vecX dst, vecX src1, vecX src2)
@@ -15705,7 +16196,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // --------------------------------- XOR --------------------------------------
@@ -15722,7 +16213,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical64);
 %}
 
 instruct vxor16B(vecX dst, vecX src1, vecX src2)
@@ -15736,7 +16227,7 @@
             as_FloatRegister($src1$$reg),
             as_FloatRegister($src2$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vlogical128);
 %}
 
 // ------------------------------ Shift ---------------------------------------
@@ -15747,7 +16238,7 @@
   ins_encode %{
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount
@@ -15758,7 +16249,7 @@
     __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
     __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vdup_reg_reg128);
 %}
 
 instruct vsll8B(vecD dst, vecD src, vecX shift) %{
@@ -15773,7 +16264,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsll16B(vecX dst, vecX src, vecX shift) %{
@@ -15787,7 +16278,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{
@@ -15801,7 +16292,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{
@@ -15814,7 +16305,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15834,7 +16325,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15853,7 +16344,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15869,7 +16360,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T8B,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15884,7 +16375,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T16B,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
@@ -15904,7 +16395,7 @@
              as_FloatRegister($src$$reg), -sh & 7);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
@@ -15923,7 +16414,7 @@
              as_FloatRegister($src$$reg), -sh & 7);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll4S(vecD dst, vecD src, vecX shift) %{
@@ -15938,7 +16429,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsll8S(vecX dst, vecX src, vecX shift) %{
@@ -15952,7 +16443,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{
@@ -15966,7 +16457,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64);
 %}
 
 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{
@@ -15979,7 +16470,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{
@@ -15999,7 +16490,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
@@ -16018,7 +16509,7 @@
              as_FloatRegister($src$$reg), sh);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
@@ -16034,7 +16525,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T4H,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
@@ -16049,7 +16540,7 @@
     __ sshr(as_FloatRegister($dst$$reg), __ T8H,
            as_FloatRegister($src$$reg), sh);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
@@ -16069,7 +16560,7 @@
              as_FloatRegister($src$$reg), -sh & 15);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
@@ -16088,7 +16579,7 @@
              as_FloatRegister($src$$reg), -sh & 15);
     }
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2I(vecD dst, vecD src, vecX shift) %{
@@ -16102,7 +16593,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
@@ -16116,7 +16607,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{
@@ -16129,7 +16620,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
@@ -16142,7 +16633,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
@@ -16155,7 +16646,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
@@ -16168,7 +16659,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
@@ -16181,7 +16672,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
@@ -16194,7 +16685,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
@@ -16207,7 +16698,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift64_imm);
 %}
 
 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
@@ -16220,7 +16711,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 31);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsll2L(vecX dst, vecX src, vecX shift) %{
@@ -16234,7 +16725,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{
@@ -16247,7 +16738,7 @@
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
@@ -16260,7 +16751,7 @@
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128);
 %}
 
 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
@@ -16273,7 +16764,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
@@ -16286,7 +16777,7 @@
             as_FloatRegister($src$$reg),
             -(int)$shift$$constant & 63);
   %}
-  ins_pipe(pipe_class_default);
+  ins_pipe(vshift128_imm);
 %}
 
 //----------PEEPHOLE RULES-----------------------------------------------------
--- a/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -256,6 +256,7 @@
 
 void DeoptimizeStub::emit_code(LIR_Assembler* ce) {
   __ bind(_entry);
+  ce->store_parameter(_trap_request, 0);
   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::deoptimize_id)));
   ce->add_call_info_here(_info);
   DEBUG_ONLY(__ should_not_reach_here());
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -3169,7 +3169,8 @@
       Register obj = as_reg(data);
       Register dst = as_reg(dest);
       if (is_oop && UseCompressedOops) {
-        __ encode_heap_oop(obj);
+        __ encode_heap_oop(rscratch1, obj);
+        obj = rscratch1;
       }
       assert_different_registers(obj, addr.base(), tmp, rscratch2, dst);
       Label again;
--- a/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1066,7 +1066,9 @@
       {
         StubFrame f(sasm, "deoptimize", dont_gc_arguments);
         OopMap* oop_map = save_live_registers(sasm);
-        int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
+        f.load_argument(0, c_rarg1);
+        int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), c_rarg1);
+
         oop_maps = new OopMapSet();
         oop_maps->add_gc_map(call_offset, oop_map);
         restore_live_registers(sasm);
@@ -1148,9 +1150,6 @@
 
 #if INCLUDE_ALL_GCS
 
-// Registers to be saved around calls to g1_wb_pre or g1_wb_post
-#define G1_SAVE_REGS (RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2))
-
     case g1_pre_barrier_slow_id:
       {
         StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments);
@@ -1192,10 +1191,10 @@
         __ b(done);
 
         __ bind(runtime);
-        __ push(G1_SAVE_REGS, sp);
+        __ push_call_clobbered_registers();
         f.load_argument(0, pre_val);
         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
-        __ pop(G1_SAVE_REGS, sp);
+        __ pop_call_clobbered_registers();
         __ bind(done);
       }
       break;
@@ -1223,45 +1222,49 @@
         Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
                                         DirtyCardQueue::byte_offset_of_buf()));
 
-        const Register card_addr = rscratch2;
-        ExternalAddress cardtable((address) ct->byte_map_base);
+        const Register card_offset = rscratch2;
+        // LR is free here, so we can use it to hold the byte_map_base.
+        const Register byte_map_base = lr;
 
-        f.load_argument(0, card_addr);
-        __ lsr(card_addr, card_addr, CardTableModRefBS::card_shift);
-        unsigned long offset;
-        __ adrp(rscratch1, cardtable, offset);
-        __ add(card_addr, card_addr, rscratch1);
-        __ ldrb(rscratch1, Address(card_addr, offset));
+        assert_different_registers(card_offset, byte_map_base, rscratch1);
+
+        f.load_argument(0, card_offset);
+        __ lsr(card_offset, card_offset, CardTableModRefBS::card_shift);
+        __ load_byte_map_base(byte_map_base);
+        __ ldrb(rscratch1, Address(byte_map_base, card_offset));
         __ cmpw(rscratch1, (int)G1SATBCardTableModRefBS::g1_young_card_val());
         __ br(Assembler::EQ, done);
 
         assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0");
 
         __ membar(Assembler::StoreLoad);
-        __ ldrb(rscratch1, Address(card_addr, offset));
+        __ ldrb(rscratch1, Address(byte_map_base, card_offset));
         __ cbzw(rscratch1, done);
 
         // storing region crossing non-NULL, card is clean.
         // dirty card and log.
-        __ strb(zr, Address(card_addr, offset));
+        __ strb(zr, Address(byte_map_base, card_offset));
+
+        // Convert card offset into an address in card_addr
+        Register card_addr = card_offset;
+        __ add(card_addr, byte_map_base, card_addr);
 
         __ ldr(rscratch1, queue_index);
         __ cbz(rscratch1, runtime);
         __ sub(rscratch1, rscratch1, wordSize);
         __ str(rscratch1, queue_index);
 
-        const Register buffer_addr = r0;
+        // Reuse LR to hold buffer_addr
+        const Register buffer_addr = lr;
 
-        __ push(RegSet::of(r0, r1), sp);
         __ ldr(buffer_addr, buffer);
         __ str(card_addr, Address(buffer_addr, rscratch1));
-        __ pop(RegSet::of(r0, r1), sp);
         __ b(done);
 
         __ bind(runtime);
-        __ push(G1_SAVE_REGS, sp);
+        __ push_call_clobbered_registers();
         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
-        __ pop(G1_SAVE_REGS, sp);
+        __ pop_call_clobbered_registers();
         __ bind(done);
 
       }
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -2301,6 +2301,30 @@
 }
 #endif
 
+void MacroAssembler::push_call_clobbered_registers() {
+  push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
+
+  // Push v0-v7, v16-v31.
+  for (int i = 30; i >= 0; i -= 2) {
+    if (i <= v7->encoding() || i >= v16->encoding()) {
+        stpd(as_FloatRegister(i), as_FloatRegister(i+1),
+             Address(pre(sp, -2 * wordSize)));
+    }
+  }
+}
+
+void MacroAssembler::pop_call_clobbered_registers() {
+
+  for (int i = 0; i < 32; i += 2) {
+    if (i <= v7->encoding() || i >= v16->encoding()) {
+      ldpd(as_FloatRegister(i), as_FloatRegister(i+1),
+           Address(post(sp, 2 * wordSize)));
+    }
+  }
+
+  pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
+}
+
 void MacroAssembler::push_CPU_state(bool save_vectors) {
   push(0x3fffffff, sp);         // integer registers except lr & sp
 
@@ -3099,12 +3123,7 @@
 
   assert(CardTableModRefBS::dirty_card_val() == 0, "must be");
 
-  {
-    ExternalAddress cardtable((address) ct->byte_map_base);
-    unsigned long offset;
-    adrp(rscratch1, cardtable, offset);
-    assert(offset == 0, "byte_map_base is misaligned");
-  }
+  load_byte_map_base(rscratch1);
 
   if (UseCondCardMark) {
     Label L_already_dirty;
@@ -3596,12 +3615,10 @@
 
   lsr(card_addr, store_addr, CardTableModRefBS::card_shift);
 
-  unsigned long offset;
-  adrp(tmp2, cardtable, offset);
-
   // get the address of the card
+  load_byte_map_base(tmp2);
   add(card_addr, card_addr, tmp2);
-  ldrb(tmp2, Address(card_addr, offset));
+  ldrb(tmp2, Address(card_addr));
   cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
   br(Assembler::EQ, done);
 
@@ -3609,13 +3626,13 @@
 
   membar(Assembler::StoreLoad);
 
-  ldrb(tmp2, Address(card_addr, offset));
+  ldrb(tmp2, Address(card_addr));
   cbzw(tmp2, done);
 
   // storing a region crossing, non-NULL oop, card is clean.
   // dirty card and log.
 
-  strb(zr, Address(card_addr, offset));
+  strb(zr, Address(card_addr));
 
   ldr(rscratch1, queue_index);
   cbz(rscratch1, runtime);
@@ -3938,7 +3955,7 @@
   // was post-decremented.)  Skip this address by starting at i=1, and
   // touch a few more pages below.  N.B.  It is important to touch all
   // the way down to and including i=StackShadowPages.
-  for (int i = 0; i < (JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
+  for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) {
     // this could be any sized move but this is can be a debugging crumb
     // so the bigger the better.
     lea(tmp, Address(tmp, -os::vm_page_size()));
@@ -3971,6 +3988,9 @@
   long offset_low = dest_page - low_page;
   long offset_high = dest_page - high_page;
 
+  assert(is_valid_AArch64_address(dest.target()), "bad address");
+  assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
+
   InstructionMark im(this);
   code_section()->relocate(inst_mark(), dest.rspec());
   // 8143067: Ensure that the adrp can reach the dest from anywhere within
@@ -3982,11 +4002,26 @@
     long offset = dest_page - pc_page;
     offset = (offset & ((1<<20)-1)) << 12;
     _adrp(reg1, pc()+offset);
-    movk(reg1, ((unsigned long)dest.target() >> 32) & 0xffff, 32);
+    movk(reg1, (unsigned long)dest.target() >> 32, 32);
   }
   byte_offset = (unsigned long)dest.target() & 0xfff;
 }
 
+void MacroAssembler::load_byte_map_base(Register reg) {
+  jbyte *byte_map_base =
+    ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base;
+
+  if (is_valid_AArch64_address((address)byte_map_base)) {
+    // Strictly speaking the byte_map_base isn't an address at all,
+    // and it might even be negative.
+    unsigned long offset;
+    adrp(reg, ExternalAddress((address)byte_map_base), offset);
+    assert(offset == 0, "misaligned card table base");
+  } else {
+    mov(reg, (uint64_t)byte_map_base);
+  }
+}
+
 void MacroAssembler::build_frame(int framesize) {
   assert(framesize > 0, "framesize must be > 0");
   if (framesize < ((1 << 9) + 2 * wordSize)) {
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -437,6 +437,13 @@
   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 
+  // Push and pop everything that might be clobbered by a native
+  // runtime call except rscratch1 and rscratch2.  (They are always
+  // scratch, so we don't have to protect them.)  Only save the lower
+  // 64 bits of each vector register.
+  void push_call_clobbered_registers();
+  void pop_call_clobbered_registers();
+
   // now mov instructions for loading absolute addresses and 32 or
   // 64 bit integers
 
@@ -1116,6 +1123,15 @@
   // of your data.
   Address form_address(Register Rd, Register base, long byte_offset, int shift);
 
+  // Return true iff an address is within the 48-bit AArch64 address
+  // space.
+  bool is_valid_AArch64_address(address a) {
+    return ((uint64_t)a >> 48) == 0;
+  }
+
+  // Load the base of the cardtable byte map into reg.
+  void load_byte_map_base(Register reg);
+
   // Prolog generator routines to support switch between x86 code and
   // generated ARM code
 
--- a/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/relocInfo_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -87,7 +87,6 @@
       return;
     }
   }
-  assert(addr() != x, "call instruction in an infinite loop");
   MacroAssembler::pd_patch_instruction(addr(), x);
   assert(pd_call_destination(addr()) == x, "fail in reloc");
 }
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -744,7 +744,7 @@
            __ sub(end, end, start); // number of bytes to copy
 
           const Register count = end; // 'end' register contains bytes count now
-          __ mov(scratch, (address)ct->byte_map_base);
+          __ load_byte_map_base(scratch);
           __ add(start, start, scratch);
           if (UseConcMarkSweepGC) {
             __ membar(__ StoreStore);
--- a/src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -930,7 +930,7 @@
 
   // If G1 is not enabled then attempt to go through the accessor entry point
   // Reference.get is an accessor
-  return generate_accessor_entry();
+  return NULL;
 }
 
 /**
@@ -1056,7 +1056,7 @@
   // an interpreter frame with greater than a page of locals, so each page
   // needs to be checked.  Only true for non-native.
   if (UseStackBanging) {
-    const int size_t n_shadow_pages = JavaThread::stack_shadow_zone_size() / os::vm_page_size();
+    const int n_shadow_pages = JavaThread::stack_shadow_zone_size() / os::vm_page_size();
     const int start_page = native_call ? n_shadow_pages : 1;
     const int page_size = os::vm_page_size();
     for (int pages = start_page; pages <= n_shadow_pages ; pages++) {
@@ -1398,8 +1398,8 @@
   {
     Label no_reguard;
     __ lea(rscratch1, Address(rthread, in_bytes(JavaThread::stack_guard_state_offset())));
-    __ ldrb(rscratch1, Address(rscratch1));
-    __ cmp(rscratch1, JavaThread::stack_guard_yellow_disabled);
+    __ ldrw(rscratch1, Address(rscratch1));
+    __ cmp(rscratch1, JavaThread::stack_guard_yellow_reserved_disabled);
     __ br(Assembler::NE, no_reguard);
 
     __ pusha(); // XXX only save smashed registers
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -121,7 +121,6 @@
   FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
   FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
   FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
-  FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
 
   unsigned long auxv = getauxval(AT_HWCAP);
 
--- a/src/cpu/ppc/vm/abstractInterpreter_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/abstractInterpreter_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/assembler_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/assembler_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/assembler_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/assembler_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/bytes_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/bytes_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_CodeStubs_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_CodeStubs_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_Defs_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_Defs_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_FpuStackSim_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_FpuStackSim_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_FrameMap_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_FrameMap_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_FrameMap_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_FrameMap_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_LIRAssembler_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_LIRAssembler_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_LIRAssembler_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_LIRAssembler_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_LIRGenerator_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_LIRGenerator_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_LinearScan_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_LinearScan_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_LinearScan_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_LinearScan_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_MacroAssembler_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_MacroAssembler_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_MacroAssembler_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_MacroAssembler_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_Runtime1_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_Runtime1_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c1_globals_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c1_globals_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c2_globals_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c2_globals_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/c2_init_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/c2_init_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/codeBuffer_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/codeBuffer_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/compiledIC_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/compiledIC_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/copy_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/copy_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/debug_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/debug_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/depChecker_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/depChecker_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/disassembler_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/disassembler_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/frame_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/frame_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/frame_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/frame_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/frame_ppc.inline.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/frame_ppc.inline.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/globalDefinitions_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/globalDefinitions_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/globals_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/globals_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/icBuffer_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/icBuffer_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/icache_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/icache_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/icache_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/icache_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/interp_masm_ppc_64.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/interp_masm_ppc_64.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/interpreterRT_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/interpreterRT_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/interpreterRT_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/interpreterRT_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2014, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2014 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/javaFrameAnchor_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/javaFrameAnchor_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2014 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/jniFastGetField_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/jniFastGetField_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/jniTypes_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/jniTypes_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/jni_ppc.h	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/jni_ppc.h	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -3172,11 +3172,12 @@
 //
 // Assumes that result differs from all other registers.
 //
-// Haystack, needle are the addresses of jchar-arrays.
-// NeedleChar is needle[0] if it is known at compile time.
-// Haycnt is the length of the haystack. We assume haycnt >=1.
+// 'haystack' is the addresses of a jchar-array.
+// 'needle' is either the character to search for or R0.
+// 'needleChar' is the character to search for if 'needle' == R0..
+// 'haycnt' is the length of the haystack. We assume 'haycnt' >=1.
 //
-// Preserves haystack, haycnt, kills all other registers.
+// Preserves haystack, haycnt, needle and kills all other registers.
 //
 // If needle == R0, we search for the constant needleChar.
 void MacroAssembler::string_indexof_1(Register result, Register haystack, Register haycnt,
@@ -3186,13 +3187,11 @@
   assert_different_registers(result, haystack, haycnt, needle, tmp1, tmp2);
 
   Label L_InnerLoop, L_FinalCheck, L_Found1, L_Found2, L_Found3, L_NotFound, L_End;
-  Register needle0 = needle, // Contains needle[0].
-           addr = tmp1,
+  Register addr = tmp1,
            ch1 = tmp2,
            ch2 = R0;
 
-//2 (variable) or 3 (const):
-   if (needle != R0) lhz(needle0, 0, needle); // Preload needle character, needle has len==1.
+//3:
    dcbtct(haystack, 0x00);                        // Indicate R/O access to haystack.
 
    srwi_(tmp2, haycnt, 1);   // Shift right by exact_log2(UNROLL_FACTOR).
@@ -3203,8 +3202,8 @@
   bind(L_InnerLoop);             // Main work horse (2x unrolled search loop).
    lhz(ch1, 0, addr);        // Load characters from haystack.
    lhz(ch2, 2, addr);
-   (needle != R0) ? cmpw(CCR0, ch1, needle0) : cmplwi(CCR0, ch1, needleChar);
-   (needle != R0) ? cmpw(CCR1, ch2, needle0) : cmplwi(CCR1, ch2, needleChar);
+   (needle != R0) ? cmpw(CCR0, ch1, needle) : cmplwi(CCR0, ch1, needleChar);
+   (needle != R0) ? cmpw(CCR1, ch2, needle) : cmplwi(CCR1, ch2, needleChar);
    beq(CCR0, L_Found1);   // Did we find the needle?
    beq(CCR1, L_Found2);
    addi(addr, addr, 4);
@@ -3214,7 +3213,7 @@
    andi_(R0, haycnt, 1);
    beq(CCR0, L_NotFound);
    lhz(ch1, 0, addr);        // One position left at which we have to compare.
-   (needle != R0) ? cmpw(CCR1, ch1, needle0) : cmplwi(CCR1, ch1, needleChar);
+   (needle != R0) ? cmpw(CCR1, ch1, needle) : cmplwi(CCR1, ch1, needleChar);
    beq(CCR1, L_Found3);
 //21:
   bind(L_NotFound);
@@ -3399,7 +3398,15 @@
             chr2_reg = cnt2_reg,
             addr_diff = str2_reg;
 
+   // 'cnt_reg' contains the number of characters in the string's character array for the
+   // pre-CompactStrings strings implementation and the number of bytes in the string's
+   // byte array for the CompactStrings strings implementation.
+   const int HAS_COMPACT_STRING = java_lang_String::has_coder_field() ? 1 : 0; // '1' = byte array, '0' = char array
+
    // Offset 0 should be 32 byte aligned.
+//-6:
+    srawi(cnt1_reg, cnt1_reg, HAS_COMPACT_STRING);
+    srawi(cnt2_reg, cnt2_reg, HAS_COMPACT_STRING);
 //-4:
     dcbtct(str1_reg, 0x00);  // Indicate R/O access to str1.
     dcbtct(str2_reg, 0x00);  // Indicate R/O access to str2.
@@ -3478,14 +3485,21 @@
   Register index_reg = tmp5_reg;
   Register cbc_iter  = tmp4_reg;
 
+  // 'cnt_reg' contains the number of characters in the string's character array for the
+  // pre-CompactStrings strings implementation and the number of bytes in the string's
+  // byte array for the CompactStrings strings implementation.
+  const int HAS_COMPACT_STRING = java_lang_String::has_coder_field() ? 1 : 0; // '1' = byte array, '0' = char array
+
 //-1:
   dcbtct(str1_reg, 0x00);  // Indicate R/O access to str1.
   dcbtct(str2_reg, 0x00);  // Indicate R/O access to str2.
 //1:
-  andi(cbc_iter, cnt_reg, 4-1);            // Remaining iterations after 4 java characters per iteration loop.
+  // cbc_iter: remaining characters after the '4 java characters per iteration' loop.
+  rlwinm(cbc_iter, cnt_reg, 32 - HAS_COMPACT_STRING, 30, 31); // (cnt_reg % (HAS_COMPACT_STRING ? 8 : 4)) >> HAS_COMPACT_STRING
   li(index_reg, 0); // init
   li(result_reg, 0); // assume false
-  srwi_(tmp2_reg, cnt_reg, exact_log2(4)); // Div: 4 java characters per iteration (main loop).
+  // tmp2_reg: units of 4 java characters (i.e. 8 bytes) per iteration (main loop).
+  srwi_(tmp2_reg, cnt_reg, exact_log2(4 << HAS_COMPACT_STRING)); // cnt_reg / (HAS_COMPACT_STRING ? 8 : 4)
 
   cmpwi(CCR1, cbc_iter, 0);             // CCR1 = (cbc_iter==0)
   beq(CCR0, Linit_cbc);                 // too short
@@ -3526,6 +3540,11 @@
   assert(sizeof(jchar) == 2, "must be");
   assert(cntval >= 0 && ((cntval & 0x7fff) == cntval), "wrong immediate");
 
+  // 'cntval' contains the number of characters in the string's character array for the
+  // pre-CompactStrings strings implementation and the number of bytes in the string's
+  // byte array for the CompactStrings strings implementation.
+  cntval >>= (java_lang_String::has_coder_field() ? 1 : 0); // '1' = byte array strings, '0' = char array strings
+
   Label Ldone_false;
 
   if (cntval < 16) { // short case
@@ -3652,9 +3671,9 @@
   assert_different_registers(table, tc0, tc1, tc2);
   assert(table == tc3, "must be!");
 
-  if (ix0 != 0) addi(tc0, table, ix0);
-  if (ix1 != 0) addi(tc1, table, ix1);
-  if (ix2 != 0) addi(tc2, table, ix2);
+  addi(tc0, table, ix0);
+  addi(tc1, table, ix1);
+  addi(tc2, table, ix2);
   if (ix3 != 0) addi(tc3, table, ix3);
 
   return ix3;
@@ -3720,14 +3739,14 @@
   const int mainLoop_alignment = loopAlignment ? 32 : 4; // (InputForNewCode > 4 ? InputForNewCode : 32) : 4;
 
   // Process all bytes in a single-byte loop.
-  cmpdi(CCR0, len, 0);                           // Anything to do?
-  mtctr(len);
+  clrldi_(len, len, 32);                         // Enforce 32 bit. Anything to do?
   beq(CCR0, L_done);
 
   if (invertCRC) {
     nand(crc, crc, crc);                         // ~c
   }
 
+  mtctr(len);
   align(mainLoop_alignment);
   BIND(L_mainLoop);
     lbz(data, 0, buf);                           // Byte from buffer, zero-extended.
@@ -3943,7 +3962,7 @@
 #else
   Register crc_rv = tmp;                         // Load_reverse needs separate registers to work on.
                                                  // Occupies tmp, but frees up crc.
-  load_reverse_32(crc_rv, crc);                  // evert byte order because we are dealing with big-endian data.
+  load_reverse_32(crc_rv, crc);                  // Revert byte order because we are dealing with big-endian data.
   tmp = crc;
 #endif
 
--- a/src/cpu/ppc/vm/macroAssembler_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/macroAssembler_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/macroAssembler_ppc.inline.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/macroAssembler_ppc.inline.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/metaspaceShared_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/metaspaceShared_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/methodHandles_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/methodHandles_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/methodHandles_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/methodHandles_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/nativeInst_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/nativeInst_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/nativeInst_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/nativeInst_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/ppc.ad	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/ppc.ad	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 //
-// Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
-// Copyright 2012, 2015 SAP AG. All rights reserved.
+// Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2012, 2015 SAP SE. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -956,36 +956,40 @@
 // the instruction. The padding must match the size of a NOP instruction.
 
 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
-  return (3*4-current_offset)&31;
+  return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
 }
 
 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
-  return (2*4-current_offset)&31;
+  return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
+}
+
+int string_indexOfCharNode::compute_padding(int current_offset) const {
+  return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
 }
 
 int string_indexOf_immNode::compute_padding(int current_offset) const {
-  return (3*4-current_offset)&31;
+  return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof(constant needlecount)
 }
 
 int string_indexOfNode::compute_padding(int current_offset) const {
-  return (1*4-current_offset)&31;
+  return (1*4-current_offset)&31;  // see MacroAssembler::string_indexof(variable needlecount)
 }
 
 int string_compareNode::compute_padding(int current_offset) const {
-  return (4*4-current_offset)&31;
+  return (2*4-current_offset)&31;  // see MacroAssembler::string_compare
 }
 
 int string_equals_immNode::compute_padding(int current_offset) const {
-  if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
-  return (2*4-current_offset)&31;
+  if (opnd_array(3)->constant() < 16) return 0; // For strlen < 16 no nops because loop completely unrolled
+  return (2*4-current_offset)&31;               // Genral case - see MacroAssembler::char_arrays_equalsImm
 }
 
 int string_equalsNode::compute_padding(int current_offset) const {
-  return (7*4-current_offset)&31;
+  return (7*4-current_offset)&31;  // see MacroAssembler::char_arrays_equals
 }
 
 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
-  return (2*4-current_offset)&31;
+  return (2*4-current_offset)&31;  // see MacroAssembler::clear_memory_doubleword
 }
 
 //=============================================================================
@@ -2025,6 +2029,8 @@
     return SpecialStringEquals && !CompactStrings;
   case Op_StrIndexOf:
     return SpecialStringIndexOf && !CompactStrings;
+  case Op_StrIndexOfChar:
+    return SpecialStringIndexOf && !CompactStrings;
   }
 
   return true;  // Per default match rules are supported.
@@ -11034,11 +11040,11 @@
 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
                                   immP needleImm, immL offsetImm, immI_1 needlecntImm,
                                   iRegIdst tmp1, iRegIdst tmp2,
-                                  flagsRegCR0 cr0, flagsRegCR1 cr1) %{
+                                  flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
   predicate(SpecialStringIndexOf && !CompactStrings);  // type check implicit by parameter type, See Matcher::match_rule_supported
   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
 
-  effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
+  effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
 
   ins_cost(150);
   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
@@ -11050,10 +11056,23 @@
     immPOper *needleOper = (immPOper *)$needleImm;
     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
-
+    jchar chr;
+    if (java_lang_String::has_coder_field()) {
+      // New compact strings byte array strings
+#ifdef VM_LITTLE_ENDIAN
+      chr = (((jchar)needle_values->element_value(1).as_byte()) << 8) |
+              (jchar)needle_values->element_value(0).as_byte();
+#else
+      chr = (((jchar)needle_values->element_value(0).as_byte()) << 8) |
+              (jchar)needle_values->element_value(1).as_byte();
+#endif
+    } else {
+      // Old char array strings
+      chr = needle_values->char_at(0);
+    }
     __ string_indexof_1($result$$Register,
                         $haystack$$Register, $haycnt$$Register,
-                        R0, needle_values->char_at(0),
+                        R0, chr,
                         $tmp1$$Register, $tmp2$$Register);
   %}
   ins_pipe(pipe_class_compare);
@@ -11073,12 +11092,13 @@
 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
                              rscratch2RegP needle, immI_1 needlecntImm,
                              iRegIdst tmp1, iRegIdst tmp2,
-                             flagsRegCR0 cr0, flagsRegCR1 cr1) %{
+                             flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
   effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
-         TEMP tmp1, TEMP tmp2);
+         TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
   // Required for EA: check if it is still a type_array.
-  predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
+  predicate(SpecialStringIndexOf && !CompactStrings &&
+            n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
   ins_cost(180);
 
@@ -11091,17 +11111,54 @@
     Node *ndl = in(operand_index($needle));  // The node that defines needle.
     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
     guarantee(needle_values, "sanity");
-    if (needle_values != NULL) {
-      __ string_indexof_1($result$$Register,
-                          $haystack$$Register, $haycnt$$Register,
-                          R0, needle_values->char_at(0),
-                          $tmp1$$Register, $tmp2$$Register);
+    jchar chr;
+    if (java_lang_String::has_coder_field()) {
+      // New compact strings byte array strings
+#ifdef VM_LITTLE_ENDIAN
+      chr = (((jchar)needle_values->element_value(1).as_byte()) << 8) |
+              (jchar)needle_values->element_value(0).as_byte();
+#else
+      chr = (((jchar)needle_values->element_value(0).as_byte()) << 8) |
+              (jchar)needle_values->element_value(1).as_byte();
+#endif
     } else {
-      __ string_indexof_1($result$$Register,
-                          $haystack$$Register, $haycnt$$Register,
-                          $needle$$Register, 0,
-                          $tmp1$$Register, $tmp2$$Register);
+      // Old char array strings
+      chr = needle_values->char_at(0);
     }
+    __ string_indexof_1($result$$Register,
+                        $haystack$$Register, $haycnt$$Register,
+                        R0, chr,
+                        $tmp1$$Register, $tmp2$$Register);
+  %}
+  ins_pipe(pipe_class_compare);
+%}
+
+// String_IndexOfChar
+//
+// Assumes register result differs from all input registers.
+//
+// Preserves registers haystack, haycnt
+// Kills     registers tmp1, tmp2
+// Defines   registers result
+//
+// Use dst register classes if register gets killed, as it is the case for tmp registers!
+instruct string_indexOfChar(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
+                            iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
+                            flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
+  match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
+  effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
+  predicate(SpecialStringIndexOf && !CompactStrings);
+  ins_cost(180);
+
+  ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
+
+  format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
+            " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
+  ins_encode %{
+    __ string_indexof_1($result$$Register,
+                        $haystack$$Register, $haycnt$$Register,
+                        $ch$$Register, 0 /* this is not used if the character is already in a register */,
+                        $tmp1$$Register, $tmp2$$Register);
   %}
   ins_pipe(pipe_class_compare);
 %}
@@ -11120,10 +11177,10 @@
 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
                             iRegPsrc needle, uimmI15 needlecntImm,
                             iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
-                            flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
+                            flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
-         TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
+         TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
   // Required for EA: check if it is still a type_array.
   predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
@@ -11153,11 +11210,11 @@
 // Use dst register classes if register gets killed, as it is the case for tmp registers!
 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
                         iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
-                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
+                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
          TEMP_DEF result,
-         TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
+         TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
   predicate(SpecialStringIndexOf && !CompactStrings);  // See Matcher::match_rule_supported.
   ins_cost(300);
 
--- a/src/cpu/ppc/vm/ppc_64.ad	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/ppc_64.ad	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 //
 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
-// Copyright 2012, 2013 SAP AG. All rights reserved.
+// Copyright (c) 2012, 2013 SAP SE. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/registerMap_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/registerMap_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/register_definitions_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/register_definitions_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/register_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/register_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/register_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/register_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2014 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -609,13 +609,11 @@
 REGISTER_DECLARATION(Register, R27_tmp7, R27);
 REGISTER_DECLARATION(Register, R28_tmp8, R28);
 REGISTER_DECLARATION(Register, R29_tmp9, R29);
-#ifndef CC_INTERP
 REGISTER_DECLARATION(Register, R24_dispatch_addr,     R24);
 REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
 REGISTER_DECLARATION(Register, R26_monitor,           R26);
 REGISTER_DECLARATION(Register, R27_constPoolCache,    R27);
 REGISTER_DECLARATION(Register, R28_mdx,               R28);
-#endif // CC_INTERP
 
 REGISTER_DECLARATION(Register, R19_inline_cache_reg, R19);
 REGISTER_DECLARATION(Register, R29_TOC, R29);
@@ -638,12 +636,9 @@
 #define R26_monitor           AS_REGISTER(Register, R26)
 #define R27_constPoolCache    AS_REGISTER(Register, R27)
 #define R28_mdx               AS_REGISTER(Register, R28)
-#endif
 
 #define R19_inline_cache_reg AS_REGISTER(Register, R19)
 #define R29_TOC AS_REGISTER(Register, R29)
-
-#define CCR4_is_synced AS_REGISTER(ConditionRegister, CCR4)
 #endif
 
 // Scratch registers are volatile.
--- a/src/cpu/ppc/vm/relocInfo_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/relocInfo_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/relocInfo_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/relocInfo_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/runtime_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/runtime_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/sharedRuntime_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/sharedRuntime_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
+ * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -3400,9 +3400,9 @@
 void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints,
                                         jint len, jlong inv,
                                         jint *m_ints) {
+  len = len & 0x7fffFFFF; // C2 does not respect int to long conversion for stub calls.
   assert(len % 2 == 0, "array length in montgomery_multiply must be even");
   int longwords = len/2;
-  assert(longwords > 0, "unsupported");
 
   // Make very sure we don't use so much space that the stack might
   // overflow. 512 jints corresponds to an 16384-bit integer and
@@ -3430,9 +3430,9 @@
 void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints,
                                       jint len, jlong inv,
                                       jint *m_ints) {
+  len = len & 0x7fffFFFF; // C2 does not respect int to long conversion for stub calls.
   assert(len % 2 == 0, "array length in montgomery_square must be even");
   int longwords = len/2;
-  assert(longwords > 0, "unsupported");
 
   // Make very sure we don't use so much space that the stack might
   // overflow. 512 jints corresponds to an 16384-bit integer and
--- a/src/cpu/ppc/vm/stubGenerator_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/stubGenerator_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -1070,6 +1070,12 @@
     return start;
   }
 
+  inline void assert_positive_int(Register count) {
+#ifdef ASSERT
+    __ srdi_(R0, count, 31);
+    __ asm_assert_eq("missing zero extend", 0xAFFE);
+#endif
+  }
 
   // Generate overlap test for array copy stubs.
   //
@@ -1082,10 +1088,7 @@
     Register tmp1 = R6_ARG4;
     Register tmp2 = R7_ARG5;
 
-#ifdef ASSERT
-    __ srdi_(tmp2, R5_ARG3, 31);
-    __ asm_assert_eq("missing zero extend", 0xAFFE);
-#endif
+    assert_positive_int(R5_ARG3);
 
     __ subf(tmp1, R3_ARG1, R4_ARG2); // distance in bytes
     __ sldi(tmp2, R5_ARG3, log2_elem_size); // size in bytes
@@ -1125,14 +1128,15 @@
   address generate_disjoint_byte_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
 
     Register tmp1 = R6_ARG4;
     Register tmp2 = R7_ARG5;
     Register tmp3 = R8_ARG6;
     Register tmp4 = R9_ARG7;
 
-
     Label l_1, l_2, l_3, l_4, l_5, l_6, l_7, l_8, l_9;
+
     // Don't try anything fancy if arrays don't have many elements.
     __ li(tmp3, 0);
     __ cmpwi(CCR0, R5_ARG3, 17);
@@ -1257,6 +1261,7 @@
   address generate_conjoint_byte_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
 
     Register tmp1 = R6_ARG4;
     Register tmp2 = R7_ARG5;
@@ -1349,8 +1354,10 @@
     Register tmp4 = R9_ARG7;
 
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
 
       Label l_1, l_2, l_3, l_4, l_5, l_6, l_7, l_8;
+
     // don't try anything fancy if arrays don't have many elements
     __ li(tmp3, 0);
     __ cmpwi(CCR0, R5_ARG3, 9);
@@ -1479,6 +1486,7 @@
   address generate_conjoint_short_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
 
     Register tmp1 = R6_ARG4;
     Register tmp2 = R7_ARG5;
@@ -1521,6 +1529,7 @@
     Register tmp4 = R0;
 
     Label l_1, l_2, l_3, l_4, l_5, l_6;
+
     // for short arrays, just do single element copy
     __ li(tmp3, 0);
     __ cmpwi(CCR0, R5_ARG3, 5);
@@ -1603,6 +1612,7 @@
   address generate_disjoint_int_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
     generate_disjoint_int_copy_core(aligned);
     __ li(R3_RET, 0); // return 0
     __ blr();
@@ -1688,7 +1698,7 @@
   address generate_conjoint_int_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
-
+    assert_positive_int(R5_ARG3);
     address nooverlap_target = aligned ?
       STUB_ENTRY(arrayof_jint_disjoint_arraycopy) :
       STUB_ENTRY(jint_disjoint_arraycopy);
@@ -1775,6 +1785,7 @@
   address generate_disjoint_long_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
+    assert_positive_int(R5_ARG3);
     generate_disjoint_long_copy_core(aligned);
     __ li(R3_RET, 0); // return 0
     __ blr();
@@ -1858,7 +1869,7 @@
   address generate_conjoint_long_copy(bool aligned, const char * name) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
-
+    assert_positive_int(R5_ARG3);
     address nooverlap_target = aligned ?
       STUB_ENTRY(arrayof_jlong_disjoint_arraycopy) :
       STUB_ENTRY(jlong_disjoint_arraycopy);
@@ -1885,7 +1896,7 @@
     StubCodeMark mark(this, "StubRoutines", name);
 
     address start = __ function_entry();
-
+    assert_positive_int(R5_ARG3);
     address nooverlap_target = aligned ?
       STUB_ENTRY(arrayof_oop_disjoint_arraycopy) :
       STUB_ENTRY(oop_disjoint_arraycopy);
@@ -1922,7 +1933,7 @@
   address generate_disjoint_oop_copy(bool aligned, const char * name, bool dest_uninitialized) {
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
-
+    assert_positive_int(R5_ARG3);
     gen_write_ref_array_pre_barrier(R3_ARG1, R4_ARG2, R5_ARG3, dest_uninitialized, R9_ARG7);
 
     // save some arguments, disjoint_long_copy_core destroys them.
@@ -1996,7 +2007,24 @@
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ function_entry();
 
-    // TODO: Assert that int is 64 bit sign extended and arrays are not conjoint.
+    // Assert that int is 64 bit sign extended and arrays are not conjoint.
+#ifdef ASSERT
+    {
+    assert_positive_int(R5_ARG3);
+    const Register tmp1 = R11_scratch1, tmp2 = R12_scratch2;
+    Label no_overlap;
+    __ subf(tmp1, R3_ARG1, R4_ARG2); // distance in bytes
+    __ sldi(tmp2, R5_ARG3, LogBytesPerHeapOop); // size in bytes
+    __ cmpld(CCR0, R3_ARG1, R4_ARG2); // Use unsigned comparison!
+    __ cmpld(CCR1, tmp1, tmp2);
+    __ crnand(CCR0, Assembler::less, CCR1, Assembler::less);
+    // Overlaps if Src before dst and distance smaller than size.
+    // Branch to forward copy routine otherwise.
+    __ blt(CCR0, no_overlap);
+    __ stop("overlap in checkcast_copy", 0x9543);
+    __ bind(no_overlap);
+    }
+#endif
 
     gen_write_ref_array_pre_barrier(R3_from, R4_to, R5_count, dest_uninitialized, R12_tmp, /* preserve: */ R6_ckoff, R7_ckval);
 
@@ -2445,12 +2473,14 @@
                                                              STUB_ENTRY(checkcast_arraycopy));
 
     // fill routines
-    StubRoutines::_jbyte_fill          = generate_fill(T_BYTE,  false, "jbyte_fill");
-    StubRoutines::_jshort_fill         = generate_fill(T_SHORT, false, "jshort_fill");
-    StubRoutines::_jint_fill           = generate_fill(T_INT,   false, "jint_fill");
-    StubRoutines::_arrayof_jbyte_fill  = generate_fill(T_BYTE,  true, "arrayof_jbyte_fill");
-    StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
-    StubRoutines::_arrayof_jint_fill   = generate_fill(T_INT,   true, "arrayof_jint_fill");
+    if (OptimizeFill) {
+      StubRoutines::_jbyte_fill          = generate_fill(T_BYTE,  false, "jbyte_fill");
+      StubRoutines::_jshort_fill         = generate_fill(T_SHORT, false, "jshort_fill");
+      StubRoutines::_jint_fill           = generate_fill(T_INT,   false, "jint_fill");
+      StubRoutines::_arrayof_jbyte_fill  = generate_fill(T_BYTE,  true, "arrayof_jbyte_fill");
+      StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
+      StubRoutines::_arrayof_jint_fill   = generate_fill(T_INT,   true, "arrayof_jint_fill");
+    }
   }
 
   // Safefetch stubs.
@@ -2535,6 +2565,11 @@
 
     BLOCK_COMMENT("Entry:");
 
+    // C2 does not respect int to long conversion for stub calls.
+    __ clrldi(xlen, xlen, 32);
+    __ clrldi(ylen, ylen, 32);
+    __ clrldi(zlen, zlen, 32);
+
     // Save non-volatile regs (frameless).
     int current_offs = 8;
     __ std(R24, -current_offs, R1_SP); current_offs += 8;
--- a/src/cpu/ppc/vm/stubRoutines_ppc_64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/stubRoutines_ppc_64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/stubRoutines_ppc_64.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/stubRoutines_ppc_64.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014, 2016, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/templateTable_ppc_64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/templateTable_ppc_64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2013, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2013, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/templateTable_ppc_64.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/templateTable_ppc_64.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2013, 2014 SAP AG. All rights reserved.
+ * Copyright (c) 2013, 2014 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vmStructs_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vmStructs_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vm_version_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vm_version_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vm_version_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vm_version_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vmreg_ppc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vmreg_ppc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vmreg_ppc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vmreg_ppc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vmreg_ppc.inline.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vmreg_ppc.inline.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2013 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/ppc/vm/vtableStubs_ppc_64.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/ppc/vm/vtableStubs_ppc_64.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2015 SAP AG. All rights reserved.
+ * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
--- a/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1805,9 +1805,7 @@
 
 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
   switch (code) {
-    case lir_sin:
-    case lir_tan:
-    case lir_cos: {
+    case lir_tan: {
       assert(thread->is_valid(), "preserve the thread object for performance reasons");
       assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
       break;
--- a/src/cpu/sparc/vm/c1_MacroAssembler_sparc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/c1_MacroAssembler_sparc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -205,12 +205,7 @@
 
 
 void C1_MacroAssembler::initialize_body(Register base, Register index) {
-  assert_different_registers(base, index);
-  Label loop;
-  bind(loop);
-  subcc(index, HeapWordSize, index);
-  brx(Assembler::greaterEqual, true, Assembler::pt, loop);
-  delayed()->st_ptr(G0, base, index);
+  zero_memory(base, index);
 }
 
 
@@ -237,7 +232,7 @@
   }
   try_allocate(obj, noreg, obj_size * wordSize, t2, t3, slow_case);
 
-  initialize_object(obj, klass, noreg, obj_size * HeapWordSize, t1, t2);
+  initialize_object(obj, klass, noreg, obj_size * HeapWordSize, t1, t2, /* is_tlab_allocated */ UseTLAB);
 }
 
 void C1_MacroAssembler::initialize_object(
@@ -246,7 +241,8 @@
   Register var_size_in_bytes,          // object size in bytes if unknown at compile time; invalid otherwise
   int      con_size_in_bytes,          // object size in bytes if   known at compile time
   Register t1,                         // temp register
-  Register t2                          // temp register
+  Register t2,                         // temp register
+  bool     is_tlab_allocated           // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB
   ) {
   const int hdr_size_in_bytes = instanceOopDesc::header_size() * HeapWordSize;
 
@@ -269,31 +265,33 @@
 
 #endif
 
-  // initialize body
-  const int threshold = 5 * HeapWordSize;              // approximate break even point for code size
-  if (var_size_in_bytes != noreg) {
-    // use a loop
-    add(obj, hdr_size_in_bytes, t1);               // compute address of first element
-    sub(var_size_in_bytes, hdr_size_in_bytes, t2); // compute size of body
-    initialize_body(t1, t2);
+  if (!(UseTLAB && ZeroTLAB && is_tlab_allocated)) {
+    // initialize body
+    const int threshold = 5 * HeapWordSize;              // approximate break even point for code size
+    if (var_size_in_bytes != noreg) {
+      // use a loop
+      add(obj, hdr_size_in_bytes, t1);               // compute address of first element
+      sub(var_size_in_bytes, hdr_size_in_bytes, t2); // compute size of body
+      initialize_body(t1, t2);
 #ifndef _LP64
-  } else if (con_size_in_bytes < threshold * 2) {
-    // on v9 we can do double word stores to fill twice as much space.
-    assert(hdr_size_in_bytes % 8 == 0, "double word aligned");
-    assert(con_size_in_bytes % 8 == 0, "double word aligned");
-    for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += 2 * HeapWordSize) stx(G0, obj, i);
+    } else if (con_size_in_bytes < threshold * 2) {
+      // on v9 we can do double word stores to fill twice as much space.
+      assert(hdr_size_in_bytes % 8 == 0, "double word aligned");
+      assert(con_size_in_bytes % 8 == 0, "double word aligned");
+      for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += 2 * HeapWordSize) stx(G0, obj, i);
 #endif
-  } else if (con_size_in_bytes <= threshold) {
-    // use explicit NULL stores
-    for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += HeapWordSize)     st_ptr(G0, obj, i);
-  } else if (con_size_in_bytes > hdr_size_in_bytes) {
-    // use a loop
-    const Register base  = t1;
-    const Register index = t2;
-    add(obj, hdr_size_in_bytes, base);               // compute address of first element
-    // compute index = number of words to clear
-    set(con_size_in_bytes - hdr_size_in_bytes, index);
-    initialize_body(base, index);
+    } else if (con_size_in_bytes <= threshold) {
+      // use explicit NULL stores
+      for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += HeapWordSize)     st_ptr(G0, obj, i);
+    } else if (con_size_in_bytes > hdr_size_in_bytes) {
+      // use a loop
+      const Register base  = t1;
+      const Register index = t2;
+      add(obj, hdr_size_in_bytes, base);               // compute address of first element
+      // compute index = number of words to clear
+      set(con_size_in_bytes - hdr_size_in_bytes, index);
+      initialize_body(base, index);
+    }
   }
 
   if (CURRENT_ENV->dtrace_alloc_probes()) {
--- a/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/c1_MacroAssembler_sparc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -50,7 +50,8 @@
     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
     int      con_size_in_bytes,        // object size in bytes if   known at compile time
     Register t1,                       // temp register
-    Register t2                        // temp register
+    Register t2,                       // temp register
+    bool is_tlab_allocated             // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB
   );
 
   // allocation of fixed-size objects
--- a/src/cpu/sparc/vm/c1_Runtime1_sparc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/c1_Runtime1_sparc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -435,7 +435,7 @@
 
           __ tlab_allocate(O0_obj, G1_obj_size, 0, G3_t1, slow_path);
 
-          __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
+          __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2, /* is_tlab_allocated */ true);
           __ verify_oop(O0_obj);
           __ mov(O0, I0);
           __ ret();
@@ -447,7 +447,7 @@
           __ eden_allocate(O0_obj, G1_obj_size, 0, G3_t1, G4_t2, slow_path);
           __ incr_allocated_bytes(G1_obj_size, G3_t1, G4_t2);
 
-          __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
+          __ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2, /* is_tlab_allocated */ false);
           __ verify_oop(O0_obj);
           __ mov(O0, I0);
           __ ret();
@@ -542,7 +542,9 @@
           __ ldub(klass_lh, G3_t1, klass_lh_header_size_offset);
           __ sub(G1_arr_size, G3_t1, O1_t2);  // body length
           __ add(O0_obj, G3_t1, G3_t1);       // body start
-          __ initialize_body(G3_t1, O1_t2);
+          if (!ZeroTLAB) {
+            __ initialize_body(G3_t1, O1_t2);
+          }
           __ verify_oop(O0_obj);
           __ retl();
           __ delayed()->nop();
--- a/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/macroAssembler_sparc.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -3469,11 +3469,27 @@
   add(top, t1, top); // t1 is tlab_size
   sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
   st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
+
+  if (ZeroTLAB) {
+    // This is a fast TLAB refill, therefore the GC is not notified of it.
+    // So compiled code must fill the new TLAB with zeroes.
+    ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
+    zero_memory(t2, t1);
+  }
   verify_tlab();
   ba(retry);
   delayed()->nop();
 }
 
+void MacroAssembler::zero_memory(Register base, Register index) {
+  assert_different_registers(base, index);
+  Label loop;
+  bind(loop);
+  subcc(index, HeapWordSize, index);
+  brx(Assembler::greaterEqual, true, Assembler::pt, loop);
+  delayed()->st_ptr(G0, base, index);
+}
+
 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
                                           Register t1, Register t2) {
   // Bump total bytes allocated by this thread
--- a/src/cpu/sparc/vm/macroAssembler_sparc.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/sparc/vm/macroAssembler_sparc.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1278,6 +1278,7 @@
     Label&   slow_case                 // continuation point if fast allocation fails
   );
   void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
+  void zero_memory(Register base, Register index);
   void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
                             Register t1, Register t2);
 
--- a/src/cpu/x86/vm/assembler_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/assembler_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1891,6 +1891,12 @@
   emit_int8((unsigned char)(0xF0 | encode));
 }
 
+void Assembler::imull(Register src) {
+  int encode = prefix_and_encode(src->encoding());
+  emit_int8((unsigned char)0xF7);
+  emit_int8((unsigned char)(0xE8 | encode));
+}
+
 void Assembler::imull(Register dst, Register src) {
   int encode = prefix_and_encode(dst->encoding(), src->encoding());
   emit_int8(0x0F);
@@ -4112,6 +4118,14 @@
   emit_arith_b(0xF6, 0xC0, dst, imm8);
 }
 
+void Assembler::testb(Address dst, int imm8) {
+  InstructionMark im(this);
+  prefix(dst);
+  emit_int8((unsigned char)0xF6);
+  emit_operand(rax, dst, 1);
+  emit_int8(imm8);
+}
+
 void Assembler::testl(Register dst, int32_t imm32) {
   // not using emit_arith because test
   // doesn't support sign-extension of
--- a/src/cpu/x86/vm/assembler_x86.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/assembler_x86.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1205,6 +1205,7 @@
   void idivq(Register src);
 #endif
 
+  void imull(Register src);
   void imull(Register dst, Register src);
   void imull(Register dst, Register src, int value);
   void imull(Register dst, Address src);
@@ -1727,6 +1728,7 @@
   void subss(XMMRegister dst, XMMRegister src);
 
   void testb(Register dst, int imm8);
+  void testb(Address dst, int imm8);
 
   void testl(Register dst, int32_t imm32);
   void testl(Register dst, Register src);
--- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -2368,15 +2368,6 @@
       case lir_log10 : __ flog10() ; break;
       case lir_abs   : __ fabs() ; break;
       case lir_sqrt  : __ fsqrt(); break;
-      case lir_sin   :
-        // Should consider not saving rbx, if not necessary
-        __ trigfunc('s', op->as_Op2()->fpu_stack_size());
-        break;
-      case lir_cos :
-        // Should consider not saving rbx, if not necessary
-        assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
-        __ trigfunc('c', op->as_Op2()->fpu_stack_size());
-        break;
       case lir_tan :
         // Should consider not saving rbx, if not necessary
         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
--- a/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -811,7 +811,8 @@
   assert(x->number_of_arguments() == 1 || (x->number_of_arguments() == 2 && x->id() == vmIntrinsics::_dpow), "wrong type");
 
   if (x->id() == vmIntrinsics::_dexp || x->id() == vmIntrinsics::_dlog ||
-      x->id() == vmIntrinsics::_dpow) {
+      x->id() == vmIntrinsics::_dpow || x->id() == vmIntrinsics::_dcos ||
+      x->id() == vmIntrinsics::_dsin) {
     do_LibmIntrinsic(x);
     return;
   }
@@ -821,11 +822,10 @@
   bool use_fpu = false;
   if (UseSSE >= 2) {
     switch(x->id()) {
-      case vmIntrinsics::_dsin:
-      case vmIntrinsics::_dcos:
       case vmIntrinsics::_dtan:
       case vmIntrinsics::_dlog10:
         use_fpu = true;
+        break;
     }
   } else {
     value.set_destroys_register();
@@ -870,8 +870,6 @@
   switch(x->id()) {
     case vmIntrinsics::_dabs:   __ abs  (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
     case vmIntrinsics::_dsqrt:  __ sqrt (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
-    case vmIntrinsics::_dsin:   __ sin  (calc_input, calc_result, tmp1, tmp2);              break;
-    case vmIntrinsics::_dcos:   __ cos  (calc_input, calc_result, tmp1, tmp2);              break;
     case vmIntrinsics::_dtan:   __ tan  (calc_input, calc_result, tmp1, tmp2);              break;
     case vmIntrinsics::_dlog10: __ log10(calc_input, calc_result, tmp1);                    break;
     default:                    ShouldNotReachHere();
@@ -923,17 +921,29 @@
     case vmIntrinsics::_dlog:
       if (VM_Version::supports_sse2()) {
         __ call_runtime_leaf(StubRoutines::dlog(), getThreadTemp(), result_reg, cc->args());
-      }
-      else {
+      } else {
         __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog), getThreadTemp(), result_reg, cc->args());
       }
       break;
     case vmIntrinsics::_dpow:
       if (VM_Version::supports_sse2()) {
         __ call_runtime_leaf(StubRoutines::dpow(), getThreadTemp(), result_reg, cc->args());
+      } else {
+        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), getThreadTemp(), result_reg, cc->args());
       }
-      else {
-        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), getThreadTemp(), result_reg, cc->args());
+      break;
+    case vmIntrinsics::_dsin:
+      if (VM_Version::supports_sse2() && StubRoutines::dsin() != NULL) {
+        __ call_runtime_leaf(StubRoutines::dsin(), getThreadTemp(), result_reg, cc->args());
+      } else {
+        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), getThreadTemp(), result_reg, cc->args());
+      }
+      break;
+    case vmIntrinsics::_dcos:
+      if (VM_Version::supports_sse2() && StubRoutines::dcos() != NULL) {
+        __ call_runtime_leaf(StubRoutines::dcos(), getThreadTemp(), result_reg, cc->args());
+      } else {
+        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), getThreadTemp(), result_reg, cc->args());
       }
       break;
     default:  ShouldNotReachHere();
@@ -949,8 +959,23 @@
     case vmIntrinsics::_dpow:
       __ call_runtime_leaf(StubRoutines::dpow(), getThreadTemp(), result_reg, cc->args());
       break;
+    case vmIntrinsics::_dsin:
+      if (StubRoutines::dsin() != NULL) {
+        __ call_runtime_leaf(StubRoutines::dsin(), getThreadTemp(), result_reg, cc->args());
+      } else {
+        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), getThreadTemp(), result_reg, cc->args());
+      }
+      break;
+    case vmIntrinsics::_dcos:
+      if (StubRoutines::dcos() != NULL) {
+        __ call_runtime_leaf(StubRoutines::dcos(), getThreadTemp(), result_reg, cc->args());
+      } else {
+        __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), getThreadTemp(), result_reg, cc->args());
+      }
+      break;
+    default:  ShouldNotReachHere();
   }
-#endif
+#endif // _LP64
   __ move(result_reg, calc_result);
 }
 
--- a/src/cpu/x86/vm/c1_LinearScan_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_LinearScan_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -811,9 +811,7 @@
     }
 
 
-    case lir_tan:
-    case lir_sin:
-    case lir_cos: {
+    case lir_tan: {
       // sin, cos and exp need two temporary fpu stack slots, so there are two temporary
       // registers (stored in right and temp of the operation).
       // the stack allocator must guarantee that the stack slots are really free,
--- a/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_LinearScan_x86.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -67,9 +67,7 @@
 
 inline void LinearScan::pd_add_temps(LIR_Op* op) {
   switch (op->code()) {
-    case lir_tan:
-    case lir_sin:
-    case lir_cos: {
+    case lir_tan: {
       // The slow path for these functions may need to save and
       // restore all live registers but we don't want to save and
       // restore everything all the time, so mark the xmms as being
--- a/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -182,54 +182,13 @@
 
 // preserves obj, destroys len_in_bytes
 void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1) {
+  assert(hdr_size_in_bytes >= 0, "header size must be positive or 0");
   Label done;
-  assert(obj != len_in_bytes && obj != t1 && t1 != len_in_bytes, "registers must be different");
-  assert((hdr_size_in_bytes & (BytesPerWord - 1)) == 0, "header size is not a multiple of BytesPerWord");
-  Register index = len_in_bytes;
-  // index is positive and ptr sized
-  subptr(index, hdr_size_in_bytes);
+
+  // len_in_bytes is positive and ptr sized
+  subptr(len_in_bytes, hdr_size_in_bytes);
   jcc(Assembler::zero, done);
-  // initialize topmost word, divide index by 2, check if odd and test if zero
-  // note: for the remaining code to work, index must be a multiple of BytesPerWord
-#ifdef ASSERT
-  { Label L;
-    testptr(index, BytesPerWord - 1);
-    jcc(Assembler::zero, L);
-    stop("index is not a multiple of BytesPerWord");
-    bind(L);
-  }
-#endif
-  xorptr(t1, t1);    // use _zero reg to clear memory (shorter code)
-  if (UseIncDec) {
-    shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
-  } else {
-    shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
-    shrptr(index, 1);
-  }
-#ifndef _LP64
-  // index could have been not a multiple of 8 (i.e., bit 2 was set)
-  { Label even;
-    // note: if index was a multiple of 8, than it cannot
-    //       be 0 now otherwise it must have been 0 before
-    //       => if it is even, we don't need to check for 0 again
-    jcc(Assembler::carryClear, even);
-    // clear topmost word (no jump needed if conditional assignment would work here)
-    movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
-    // index could be 0 now, need to check again
-    jcc(Assembler::zero, done);
-    bind(even);
-  }
-#endif // !_LP64
-  // initialize remaining object fields: rdx is a multiple of 2 now
-  { Label loop;
-    bind(loop);
-    movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
-    NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);)
-    decrement(index);
-    jcc(Assembler::notZero, loop);
-  }
-
-  // done
+  zero_memory(obj, len_in_bytes, hdr_size_in_bytes, t1);
   bind(done);
 }
 
@@ -241,47 +200,49 @@
 
   try_allocate(obj, noreg, object_size * BytesPerWord, t1, t2, slow_case);
 
-  initialize_object(obj, klass, noreg, object_size * HeapWordSize, t1, t2);
+  initialize_object(obj, klass, noreg, object_size * HeapWordSize, t1, t2, UseTLAB);
 }
 
-void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register var_size_in_bytes, int con_size_in_bytes, Register t1, Register t2) {
+void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register var_size_in_bytes, int con_size_in_bytes, Register t1, Register t2, bool is_tlab_allocated) {
   assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0,
          "con_size_in_bytes is not multiple of alignment");
   const int hdr_size_in_bytes = instanceOopDesc::header_size() * HeapWordSize;
 
   initialize_header(obj, klass, noreg, t1, t2);
 
-  // clear rest of allocated space
-  const Register t1_zero = t1;
-  const Register index = t2;
-  const int threshold = 6 * BytesPerWord;   // approximate break even point for code size (see comments below)
-  if (var_size_in_bytes != noreg) {
-    mov(index, var_size_in_bytes);
-    initialize_body(obj, index, hdr_size_in_bytes, t1_zero);
-  } else if (con_size_in_bytes <= threshold) {
-    // use explicit null stores
-    // code size = 2 + 3*n bytes (n = number of fields to clear)
-    xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
-    for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += BytesPerWord)
-      movptr(Address(obj, i), t1_zero);
-  } else if (con_size_in_bytes > hdr_size_in_bytes) {
-    // use loop to null out the fields
-    // code size = 16 bytes for even n (n = number of fields to clear)
-    // initialize last object field first if odd number of fields
-    xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
-    movptr(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
-    // initialize last object field if constant size is odd
-    if (((con_size_in_bytes - hdr_size_in_bytes) & 4) != 0)
-      movptr(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
-    // initialize remaining object fields: rdx is a multiple of 2
-    { Label loop;
-      bind(loop);
-      movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (1*BytesPerWord)),
-             t1_zero);
-      NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)),
-             t1_zero);)
-      decrement(index);
-      jcc(Assembler::notZero, loop);
+  if (!(UseTLAB && ZeroTLAB && is_tlab_allocated)) {
+    // clear rest of allocated space
+    const Register t1_zero = t1;
+    const Register index = t2;
+    const int threshold = 6 * BytesPerWord;   // approximate break even point for code size (see comments below)
+    if (var_size_in_bytes != noreg) {
+      mov(index, var_size_in_bytes);
+      initialize_body(obj, index, hdr_size_in_bytes, t1_zero);
+    } else if (con_size_in_bytes <= threshold) {
+      // use explicit null stores
+      // code size = 2 + 3*n bytes (n = number of fields to clear)
+      xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+      for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += BytesPerWord)
+        movptr(Address(obj, i), t1_zero);
+    } else if (con_size_in_bytes > hdr_size_in_bytes) {
+      // use loop to null out the fields
+      // code size = 16 bytes for even n (n = number of fields to clear)
+      // initialize last object field first if odd number of fields
+      xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+      movptr(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
+      // initialize last object field if constant size is odd
+      if (((con_size_in_bytes - hdr_size_in_bytes) & 4) != 0)
+        movptr(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
+      // initialize remaining object fields: rdx is a multiple of 2
+      { Label loop;
+        bind(loop);
+        movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (1*BytesPerWord)),
+               t1_zero);
+        NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)),
+               t1_zero);)
+        decrement(index);
+        jcc(Assembler::notZero, loop);
+      }
     }
   }
 
--- a/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -65,7 +65,8 @@
     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
     int      con_size_in_bytes,        // object size in bytes if   known at compile time
     Register t1,                       // temp register
-    Register t2                        // temp register
+    Register t2,                       // temp register
+    bool     is_tlab_allocated         // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB
   );
 
   // allocation of fixed-size objects
--- a/src/cpu/x86/vm/c1_Runtime1_x86.cpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/c1_Runtime1_x86.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1040,7 +1040,7 @@
 
           __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
 
-          __ initialize_object(obj, klass, obj_size, 0, t1, t2);
+          __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ true);
           __ verify_oop(obj);
           __ pop(rbx);
           __ pop(rdi);
@@ -1053,7 +1053,7 @@
           __ eden_allocate(obj, obj_size, 0, t1, slow_path);
           __ incr_allocated_bytes(thread, obj_size, 0);
 
-          __ initialize_object(obj, klass, obj_size, 0, t1, t2);
+          __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ false);
           __ verify_oop(obj);
           __ pop(rbx);
           __ pop(rdi);
@@ -1169,7 +1169,9 @@
           __ andptr(t1, Klass::_lh_header_size_mask);
           __ subptr(arr_size, t1);  // body length
           __ addptr(t1, obj);       // body start
-          __ initialize_body(t1, arr_size, 0, t2);
+          if (!ZeroTLAB) {
+            __ initialize_body(t1, arr_size, 0, t2);
+          }
           __ verify_oop(obj);
           __ ret(0);
 
--- a/src/cpu/x86/vm/globals_x86.hpp	Tue Jan 26 17:13:18 2016 +0100
+++ b/src/cpu/x86/vm/globals_x86.hpp	Thu Jan 28 09:49:17 2016 +0100
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -184,9 +184,18 @@
   product(bool, UseCountTrailingZerosInstruction, false,                    \
           "Use count trailing zeros instruction")                           \
                                                                             \
+  product(bool, UseSSE42Intrinsics, false,                                  \
+          "SSE4.2 versions of intrinsics")                                  \
+                                                                            \
   product(bool, UseBMI1Instructions, false,                                 \
           "Use BMI1 instructions")                                          \
                                                                             \
   product(bool, UseBMI2Instructions, false,                                 \
-          "Use BMI2 instructions")
+          "Use BMI2 instructions")                                          \
+                                                                            \
+  diagnostic(bool, UseLibmSinIntrinsic, true,                               \
+          "Use Libm Sin Intrinsic")                                         \
+                                                                            \
+  diagnostic(bool, UseLibmCosIntrinsic, true,                               \
+          "Use Libm Cos Intrinsic")
 #endif // CPU_X86_VM_GLOBALS_X86_HPP
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/x86/vm/macroAssembler_libm_x86_32.cpp	Thu Jan 28 09:49:17 2016 +0100
@@ -0,0 +1,4571 @@
+/*
+ * Copyright (c) 2015, Intel Corporation.
+ * Intel Math Library (LIBM) Source Code
+ *
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "asm/assembler.hpp"
+#include "asm/assembler.inline.hpp"
+#include "runtime/stubRoutines.hpp"
+#include "macroAssembler_x86.hpp"
+
+#ifdef _MSC_VER
+#define ALIGNED_(x) __declspec(align(x))
+#else
+#define ALIGNED_(x) __attribute__ ((aligned(x)))
+#endif
+
+// The 32 bit code is at most SSE2 compliant
+
+/******************************************************************************/
+//                     ALGORITHM DESCRIPTION - EXP()
+//                     ---------------------
+//
+// Description:
+//  Let K = 64 (table size).
+//        x    x/log(2)     n
+//       e  = 2          = 2 * T[j] * (1 + P(y))
+//  where
+//       x = m*log(2)/K + y,    y in [-log(2)/K..log(2)/K]
+//       m = n*K + j,           m,n,j - signed integer, j in [-K/2..K/2]
+//                  j/K
+//       values of 2   are tabulated as T[j] = T_hi[j] ( 1 + T_lo[j]).
+//
+//       P(y) is a minimax polynomial approximation of exp(x)-1
+//       on small interval [-log(2)/K..log(2)/K] (were calculated by Maple V).
+//
+//  To avoid problems with arithmetic overflow and underflow,
+//            n                        n1  n2
+//  value of 2  is safely computed as 2 * 2 where n1 in [-BIAS/2..BIAS/2]
+//  where BIAS is a value of exponent bias.
+//
+// Special cases:
+//  exp(NaN) = NaN
+//  exp(+INF) = +INF
+//  exp(-INF) = 0
+//  exp(x) = 1 for subnormals
+//  for finite argument, only exp(0)=1 is exact
+//  For IEEE double
+//    if x >  709.782712893383973096 then exp(x) overflow
+//    if x < -745.133219101941108420 then exp(x) underflow
+//
+/******************************************************************************/
+
+ALIGNED_(16) juint _static_const_table[] =
+{
+    0x00000000UL, 0xfff00000UL, 0x00000000UL, 0xfff00000UL, 0xffffffc0UL,
+    0x00000000UL, 0xffffffc0UL, 0x00000000UL, 0x0000ffc0UL, 0x00000000UL,
+    0x0000ffc0UL, 0x00000000UL, 0x00000000UL, 0x43380000UL, 0x00000000UL,
+    0x43380000UL, 0x652b82feUL, 0x40571547UL, 0x652b82feUL, 0x40571547UL,
+    0xfefa0000UL, 0x3f862e42UL, 0xfefa0000UL, 0x3f862e42UL, 0xbc9e3b3aUL,
+    0x3d1cf79aUL, 0xbc9e3b3aUL, 0x3d1cf79aUL, 0xfffffffeUL, 0x3fdfffffUL,
+    0xfffffffeUL, 0x3fdfffffUL, 0xe3289860UL, 0x3f56c15cUL, 0x555b9e25UL,
+    0x3fa55555UL, 0xc090cf0fUL, 0x3f811115UL, 0x55548ba1UL, 0x3fc55555UL,
+    0x00000000UL, 0x00000000UL, 0x00000000UL, 0x00000000UL, 0x0e03754dUL,
+    0x3cad7bbfUL, 0x3e778060UL, 0x00002c9aUL, 0x3567f613UL, 0x3c8cd252UL,
+    0xd3158574UL, 0x000059b0UL, 0x61e6c861UL, 0x3c60f74eUL, 0x18759bc8UL,
+    0x00008745UL, 0x5d837b6cUL, 0x3c979aa6UL, 0x6cf9890fUL, 0x0000b558UL,
+    0x702f9cd1UL, 0x3c3ebe3dUL, 0x32d3d1a2UL, 0x0000e3ecUL, 0x1e63bcd8UL,
+    0x3ca3516eUL, 0xd0125b50UL, 0x00011301UL, 0x26f0387bUL, 0x3ca4c554UL,
+    0xaea92ddfUL, 0x0001429aUL, 0x62523fb6UL, 0x3ca95153UL, 0x3c7d517aUL,
+    0x000172b8UL, 0x3f1353bfUL, 0x3c8b898cUL, 0xeb6fcb75UL, 0x0001a35bUL,
+    0x3e3a2f5fUL, 0x3c9aecf7UL, 0x3168b9aaUL, 0x0001d487UL, 0x44a6c38dUL,
+    0x3c8a6f41UL, 0x88628cd6UL, 0x0002063bUL, 0xe3a8a894UL, 0x3c968efdUL,
+    0x6e756238UL, 0x0002387aUL, 0x981fe7f2UL, 0x3c80472bUL, 0x65e27cddUL,
+    0x00026b45UL, 0x6d09ab31UL, 0x3c82f7e1UL, 0xf51fdee1UL, 0x00029e9dUL,
+    0x720c0ab3UL, 0x3c8b3782UL, 0xa6e4030bUL, 0x0002d285UL, 0x4db0abb6UL,
+    0x3c834d75UL, 0x0a31b715UL, 0x000306feUL, 0x5dd3f84aUL, 0x3c8fdd39UL,
+    0xb26416ffUL, 0x00033c08UL, 0xcc187d29UL, 0x3ca12f8cUL, 0x373aa9caUL,
+    0x000371a7UL, 0x738b5e8bUL, 0x3ca7d229UL, 0x34e59ff6UL, 0x0003a7dbUL,
+    0xa72a4c6dUL, 0x3c859f48UL, 0x4c123422UL, 0x0003dea6UL, 0x259d9205UL,
+    0x3ca8b846UL, 0x21f72e29UL, 0x0004160aUL, 0x60c2ac12UL, 0x3c4363edUL,
+    0x6061892dUL, 0x00044e08UL, 0xdaa10379UL, 0x3c6ecce1UL, 0xb5c13cd0UL,
+    0x000486a2UL, 0xbb7aafb0UL, 0x3c7690ceUL, 0xd5362a27UL, 0x0004bfdaUL,
+    0x9b282a09UL, 0x3ca083ccUL, 0x769d2ca6UL, 0x0004f9b2UL, 0xc1aae707UL,
+    0x3ca509b0UL, 0x569d4f81UL, 0x0005342bUL, 0x18fdd78eUL, 0x3c933505UL,
+    0x36b527daUL, 0x00056f47UL, 0xe21c5409UL, 0x3c9063e1UL, 0xdd485429UL,
+    0x0005ab07UL, 0x2b64c035UL, 0x3c9432e6UL, 0x15ad2148UL, 0x0005e76fUL,
+    0x99f08c0aUL, 0x3ca01284UL, 0xb03a5584UL, 0x0006247eUL, 0x0073dc06UL,
+    0x3c99f087UL, 0x82552224UL, 0x00066238UL, 0x0da05571UL, 0x3c998d4dUL,
+    0x667f3bccUL, 0x0006a09eUL, 0x86ce4786UL, 0x3ca52bb9UL, 0x3c651a2eUL,
+    0x0006dfb2UL, 0x206f0dabUL, 0x3ca32092UL, 0xe8ec5f73UL, 0x00071f75UL,
+    0x8e17a7a6UL, 0x3ca06122UL, 0x564267c8UL, 0x00075febUL, 0x461e9f86UL,
+    0x3ca244acUL, 0x73eb0186UL, 0x0007a114UL, 0xabd66c55UL, 0x3c65ebe1UL,
+    0x36cf4e62UL, 0x0007e2f3UL, 0xbbff67d0UL, 0x3c96fe9fUL, 0x994cce12UL,
+    0x00082589UL, 0x14c801dfUL, 0x3c951f14UL, 0x9b4492ecUL, 0x000868d9UL,
+    0xc1f0eab4UL, 0x3c8db72fUL, 0x422aa0dbUL, 0x0008ace5UL, 0x59f35f44UL,
+    0x3c7bf683UL, 0x99157736UL, 0x0008f1aeUL, 0x9c06283cUL, 0x3ca360baUL,
+    0xb0cdc5e4UL, 0x00093737UL, 0x20f962aaUL, 0x3c95e8d1UL, 0x9fde4e4fUL,
+    0x00097d82UL, 0x2b91ce27UL, 0x3c71affcUL, 0x82a3f090UL, 0x0009c491UL,
+    0x589a2ebdUL, 0x3c9b6d34UL, 0x7b5de564UL, 0x000a0c66UL, 0x9ab89880UL,
+    0x3c95277cUL, 0xb23e255cUL, 0x000a5503UL, 0x6e735ab3UL, 0x3c846984UL,
+    0x5579fdbfUL, 0x000a9e6bUL, 0x92cb3387UL, 0x3c8c1a77UL, 0x995ad3adUL,
+    0x000ae89fUL, 0xdc2d1d96UL, 0x3ca22466UL, 0xb84f15faUL, 0x000b33a2UL,
+    0xb19505aeUL, 0x3ca1112eUL, 0xf2fb5e46UL, 0x000b7f76UL, 0x0a5fddcdUL,
+    0x3c74ffd7UL, 0x904bc1d2UL, 0x000bcc1eUL, 0x30af0cb3UL, 0x3c736eaeUL,
+    0xdd85529cUL, 0x000c199bUL, 0xd10959acUL, 0x3c84e08fUL, 0x2e57d14bUL,
+    0x000c67f1UL, 0x6c921968UL, 0x3c676b2cUL, 0xdcef9069UL, 0x000cb720UL,
+    0x36df99b3UL, 0x3c937009UL, 0x4a07897bUL, 0x000d072dUL, 0xa63d07a7UL,
+    0x3c74a385UL, 0xdcfba487UL, 0x000d5818UL, 0xd5c192acUL, 0x3c8e5a50UL,
+    0x03db3285UL, 0x000da9e6UL, 0x1c4a9792UL, 0x3c98bb73UL, 0x337b9b5eUL,
+    0x000dfc97UL, 0x603a88d3UL, 0x3c74b604UL, 0xe78b3ff6UL, 0x000e502eUL,
+    0x92094926UL, 0x3c916f27UL, 0xa2a490d9UL, 0x000ea4afUL, 0x41aa2008UL,
+    0x3c8ec3bcUL, 0xee615a27UL, 0x000efa1bUL, 0x31d185eeUL, 0x3c8a64a9UL,
+    0x5b6e4540UL, 0x000f5076UL, 0x4d91cd9dUL, 0x3c77893bUL, 0x819e90d8UL,
+    0x000fa7c1UL, 0x00000000UL, 0x3ff00000UL, 0x00000000UL, 0x7ff00000UL,
+    0x00000000UL, 0x00000000UL, 0xffffffffUL, 0x7fefffffUL, 0x00000000UL,
+    0x00100000UL
+};
+
+//registers,
+// input: (rbp + 8)
+// scratch: xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
+//          rax, rdx, rcx, rbx (tmp)
+
+// Code generated by Intel C compiler for LIBM library
+
+void MacroAssembler::fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register eax, Register ecx, Register edx, Register tmp) {
+  Label L_2TAG_PACKET_0_0_2, L_2TAG_PACKET_1_0_2, L_2TAG_PACKET_2_0_2, L_2TAG_PACKET_3_0_2;
+  Label L_2TAG_PACKET_4_0_2, L_2TAG_PACKET_5_0_2, L_2TAG_PACKET_6_0_2, L_2TAG_PACKET_7_0_2;
+  Label L_2TAG_PACKET_8_0_2, L_2TAG_PACKET_9_0_2, L_2TAG_PACKET_10_0_2, L_2TAG_PACKET_11_0_2;
+  Label L_2TAG_PACKET_12_0_2, L_2TAG_PACKET_13_0_2, B1_3, B1_5, start;
+
+  assert_different_registers(tmp, eax, ecx, edx);
+  jmp(start);
+  address static_const_table = (address)_static_const_table;
+
+  bind(start);
+  subl(rsp, 120);
+  movl(Address(rsp, 64), tmp);
+  lea(tmp, ExternalAddress(static_const_table));
+  movdqu(xmm0, Address(rsp, 128));
+  unpcklpd(xmm0, xmm0);
+  movdqu(xmm1, Address(tmp, 64));          // 0x652b82feUL, 0x40571547UL, 0x652b82feUL, 0x40571547UL
+  movdqu(xmm6, Address(tmp, 48));          // 0x00000000UL, 0x43380000UL, 0x00000000UL, 0x43380000UL
+  movdqu(xmm2, Address(tmp, 80));          // 0xfefa0000UL, 0x3f862e42UL, 0xfefa0000UL, 0x3f862e42UL
+  movdqu(xmm3, Address(tmp, 96));          // 0xbc9e3b3aUL, 0x3d1cf79aUL, 0xbc9e3b3aUL, 0x3d1cf79aUL
+  pextrw(eax, xmm0, 3);
+  andl(eax, 32767);
+  movl(edx, 16527);
+  subl(edx, eax);
+  subl(eax, 15504);
+  orl(edx, eax);
+  cmpl(edx, INT_MIN);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_0_0_2);
+  mulpd(xmm1, xmm0);
+  addpd(xmm1, xmm6);
+  movapd(xmm7, xmm1);
+  subpd(xmm1, xmm6);
+  mulpd(xmm2, xmm1);
+  movdqu(xmm4, Address(tmp, 128));         // 0xe3289860UL, 0x3f56c15cUL, 0x555b9e25UL, 0x3fa55555UL
+  mulpd(xmm3, xmm1);
+  movdqu(xmm5, Address(tmp, 144));         // 0xc090cf0fUL, 0x3f811115UL, 0x55548ba1UL, 0x3fc55555UL
+  subpd(xmm0, xmm2);
+  movdl(eax, xmm7);
+  movl(ecx, eax);
+  andl(ecx, 63);
+  shll(ecx, 4);
+  sarl(eax, 6);
+  movl(edx, eax);
+  movdqu(xmm6, Address(tmp, 16));          // 0xffffffc0UL, 0x00000000UL, 0xffffffc0UL, 0x00000000UL
+  pand(xmm7, xmm6);
+  movdqu(xmm6, Address(tmp, 32));          // 0x0000ffc0UL, 0x00000000UL, 0x0000ffc0UL, 0x00000000UL
+  paddq(xmm7, xmm6);
+  psllq(xmm7, 46);
+  subpd(xmm0, xmm3);
+  movdqu(xmm2, Address(tmp, ecx, Address::times_1, 160));
+  mulpd(xmm4, xmm0);
+  movapd(xmm6, xmm0);
+  movapd(xmm1, xmm0);
+  mulpd(xmm6, xmm6);
+  mulpd(xmm0, xmm6);
+  addpd(xmm5, xmm4);
+  mulsd(xmm0, xmm6);
+  mulpd(xmm6, Address(tmp, 112));          // 0xfffffffeUL, 0x3fdfffffUL, 0xfffffffeUL, 0x3fdfffffUL
+  addsd(xmm1, xmm2);
+  unpckhpd(xmm2, xmm2);
+  mulpd(xmm0, xmm5);
+  addsd(xmm1, xmm0);
+  por(xmm2, xmm7);
+  unpckhpd(xmm0, xmm0);
+  addsd(xmm0, xmm1);
+  addsd(xmm0, xmm6);
+  addl(edx, 894);
+  cmpl(edx, 1916);
+  jcc (Assembler::above, L_2TAG_PACKET_1_0_2);
+  mulsd(xmm0, xmm2);
+  addsd(xmm0, xmm2);
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_1_0_2);
+  fnstcw(Address(rsp, 24));
+  movzwl(edx, Address(rsp, 24));
+  orl(edx, 768);
+  movw(Address(rsp, 28), edx);
+  fldcw(Address(rsp, 28));
+  movl(edx, eax);
+  sarl(eax, 1);
+  subl(edx, eax);
+  movdqu(xmm6, Address(tmp, 0));           // 0x00000000UL, 0xfff00000UL, 0x00000000UL, 0xfff00000UL
+  pandn(xmm6, xmm2);
+  addl(eax, 1023);
+  movdl(xmm3, eax);
+  psllq(xmm3, 52);
+  por(xmm6, xmm3);
+  addl(edx, 1023);
+  movdl(xmm4, edx);
+  psllq(xmm4, 52);
+  movsd(Address(rsp, 8), xmm0);
+  fld_d(Address(rsp, 8));
+  movsd(Address(rsp, 16), xmm6);
+  fld_d(Address(rsp, 16));
+  fmula(1);
+  faddp(1);
+  movsd(Address(rsp, 8), xmm4);
+  fld_d(Address(rsp, 8));
+  fmulp(1);
+  fstp_d(Address(rsp, 8));
+  movsd(xmm0,Address(rsp, 8));
+  fldcw(Address(rsp, 24));
+  pextrw(ecx, xmm0, 3);
+  andl(ecx, 32752);
+  cmpl(ecx, 32752);
+  jcc(Assembler::greaterEqual, L_2TAG_PACKET_3_0_2);
+  cmpl(ecx, 0);
+  jcc(Assembler::equal, L_2TAG_PACKET_4_0_2);
+  jmp(L_2TAG_PACKET_2_0_2);
+  cmpl(ecx, INT_MIN);
+  jcc(Assembler::less, L_2TAG_PACKET_3_0_2);
+  cmpl(ecx, -1064950997);
+  jcc(Assembler::less, L_2TAG_PACKET_2_0_2);
+  jcc(Assembler::greater, L_2TAG_PACKET_4_0_2);
+  movl(edx, Address(rsp, 128));
+  cmpl(edx ,-17155601);
+  jcc(Assembler::less, L_2TAG_PACKET_2_0_2);
+  jmp(L_2TAG_PACKET_4_0_2);
+
+  bind(L_2TAG_PACKET_3_0_2);
+  movl(edx, 14);
+  jmp(L_2TAG_PACKET_5_0_2);
+
+  bind(L_2TAG_PACKET_4_0_2);
+  movl(edx, 15);
+
+  bind(L_2TAG_PACKET_5_0_2);
+  movsd(Address(rsp, 0), xmm0);
+  movsd(xmm0, Address(rsp, 128));
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_7_0_2);
+  cmpl(eax, 2146435072);
+  jcc(Assembler::greaterEqual, L_2TAG_PACKET_8_0_2);
+  movl(eax, Address(rsp, 132));
+  cmpl(eax, INT_MIN);
+  jcc(Assembler::greaterEqual, L_2TAG_PACKET_9_0_2);
+  movsd(xmm0, Address(tmp, 1208));         // 0xffffffffUL, 0x7fefffffUL
+  mulsd(xmm0, xmm0);
+  movl(edx, 14);
+  jmp(L_2TAG_PACKET_5_0_2);
+
+  bind(L_2TAG_PACKET_9_0_2);
+  movsd(xmm0, Address(tmp, 1216));
+  mulsd(xmm0, xmm0);
+  movl(edx, 15);
+  jmp(L_2TAG_PACKET_5_0_2);
+
+  bind(L_2TAG_PACKET_8_0_2);
+  movl(edx, Address(rsp, 128));
+  cmpl(eax, 2146435072);
+  jcc(Assembler::above, L_2TAG_PACKET_10_0_2);
+  cmpl(edx, 0);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_10_0_2);
+  movl(eax, Address(rsp, 132));
+  cmpl(eax, 2146435072);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_11_0_2);
+  movsd(xmm0, Address(tmp, 1192));         // 0x00000000UL, 0x7ff00000UL
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_11_0_2);
+  movsd(xmm0, Address(tmp, 1200));         // 0x00000000UL, 0x00000000UL
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_10_0_2);
+  movsd(xmm0, Address(rsp, 128));
+  addsd(xmm0, xmm0);
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_0_0_2);
+  movl(eax, Address(rsp, 132));
+  andl(eax, 2147483647);
+  cmpl(eax, 1083179008);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_7_0_2);
+  movsd(xmm0, Address(rsp, 128));
+  addsd(xmm0, Address(tmp, 1184));         // 0x00000000UL, 0x3ff00000UL
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_2_0_2);
+  movsd(Address(rsp, 48), xmm0);
+  fld_d(Address(rsp, 48));
+
+  bind(L_2TAG_PACKET_6_0_2);
+  movl(tmp, Address(rsp, 64));
+}
+
+/******************************************************************************/
+//                     ALGORITHM DESCRIPTION - LOG()
+//                     ---------------------
+//
+//    x=2^k * mx, mx in [1,2)
+//
+//    Get B~1/mx based on the output of rcpss instruction (B0)
+//    B = int((B0*2^7+0.5))/2^7
+//
+//    Reduced argument: r=B*mx-1.0 (computed accurately in high and low parts)
+//
+//    Result:  k*log(2) - log(B) + p(r) if |x-1| >= small value (2^-6)  and
+//             p(r) is a degree 7 polynomial
+//             -log(B) read from data table (high, low parts)
+//             Result is formed from high and low parts
+//
+// Special cases:
+//  log(NaN) = quiet NaN, and raise invalid exception
+//  log(+INF) = that INF
+//  log(0) = -INF with divide-by-zero exception raised
+//  log(1) = +0
+//  log(x) = NaN with invalid exception raised if x < -0, including -INF
+//
+/******************************************************************************/
+
+ALIGNED_(16) juint _static_const_table_log[] =
+{
+  0xfefa3800UL, 0x3fe62e42UL, 0x93c76730UL, 0x3d2ef357UL, 0xaa241800UL,
+  0x3fe5ee82UL, 0x0cda46beUL, 0x3d220238UL, 0x5c364800UL, 0x3fe5af40UL,
+  0xac10c9fbUL, 0x3d2dfa63UL, 0x26bb8c00UL, 0x3fe5707aUL, 0xff3303ddUL,
+  0x3d09980bUL, 0x26867800UL, 0x3fe5322eUL, 0x5d257531UL, 0x3d05ccc4UL,
+  0x835a5000UL, 0x3fe4f45aUL, 0x6d93b8fbUL, 0xbd2e6c51UL, 0x6f970c00UL,
+  0x3fe4b6fdUL, 0xed4c541cUL, 0x3cef7115UL, 0x27e8a400UL, 0x3fe47a15UL,
+  0xf94d60aaUL, 0xbd22cb6aUL, 0xf2f92400UL, 0x3fe43d9fUL, 0x481051f7UL,
+  0xbcfd984fUL, 0x2125cc00UL, 0x3fe4019cUL, 0x30f0c74cUL, 0xbd26ce79UL,
+  0x0c36c000UL, 0x3fe3c608UL, 0x7cfe13c2UL, 0xbd02b736UL, 0x17197800UL,
+  0x3fe38ae2UL, 0xbb5569a4UL, 0xbd218b7aUL, 0xad9d8c00UL, 0x3fe35028UL,
+  0x9527e6acUL, 0x3d10b83fUL, 0x44340800UL, 0x3fe315daUL, 0xc5a0ed9cUL,
+  0xbd274e93UL, 0x57b0e000UL, 0x3fe2dbf5UL, 0x07b9dc11UL, 0xbd17a6e5UL,
+  0x6d0ec000UL, 0x3fe2a278UL, 0xe797882dUL, 0x3d206d2bUL, 0x1134dc00UL,
+  0x3fe26962UL, 0x05226250UL, 0xbd0b61f1UL, 0xd8bebc00UL, 0x3fe230b0UL,
+  0x6e48667bUL, 0x3d12fc06UL, 0x5fc61800UL, 0x3fe1f863UL, 0xc9fe81d3UL,
+  0xbd2a7242UL, 0x49ae6000UL, 0x3fe1c078UL, 0xed70e667UL, 0x3cccacdeUL,
+  0x40f23c00UL, 0x3fe188eeUL, 0xf8ab4650UL, 0x3d14cc4eUL, 0xf6f29800UL,
+  0x3fe151c3UL, 0xa293ae49UL, 0xbd2edd97UL, 0x23c75c00UL, 0x3fe11af8UL,
+  0xbb9ddcb2UL, 0xbd258647UL, 0x8611cc00UL, 0x3fe0e489UL, 0x07801742UL,
+  0x3d1c2998UL, 0xe2d05400UL, 0x3fe0ae76UL, 0x887e7e27UL, 0x3d1f486bUL,
+  0x0533c400UL, 0x3fe078bfUL, 0x41edf5fdUL, 0x3d268122UL, 0xbe760400UL,
+  0x3fe04360UL, 0xe79539e0UL, 0xbd04c45fUL, 0xe5b20800UL, 0x3fe00e5aUL,
+  0xb1727b1cUL, 0xbd053ba3UL, 0xaf7a4800UL, 0x3fdfb358UL, 0x3c164935UL,
+  0x3d0085faUL, 0xee031800UL, 0x3fdf4aa7UL, 0x6f014a8bUL, 0x3d12cde5UL,
+  0x56b41000UL, 0x3fdee2a1UL, 0x5a470251UL, 0x3d2f27f4UL, 0xc3ddb000UL,
+  0x3fde7b42UL, 0x5372bd08UL, 0xbd246550UL, 0x1a272800UL, 0x3fde148aUL,
+  0x07322938UL, 0xbd1326b2UL, 0x484c9800UL, 0x3fddae75UL, 0x60dc616aUL,
+  0xbd1ea42dUL, 0x46def800UL, 0x3fdd4902UL, 0xe9a767a8UL, 0x3d235bafUL,
+  0x18064800UL, 0x3fdce42fUL, 0x3ec7a6b0UL, 0xbd0797c3UL, 0xc7455800UL,
+  0x3fdc7ff9UL, 0xc15249aeUL, 0xbd29b6ddUL, 0x693fa000UL, 0x3fdc1c60UL,
+  0x7fe8e180UL, 0x3d2cec80UL, 0x1b80e000UL, 0x3fdbb961UL, 0xf40a666dUL,
+  0x3d27d85bUL, 0x04462800UL, 0x3fdb56faUL, 0x2d841995UL, 0x3d109525UL,
+  0x5248d000UL, 0x3fdaf529UL, 0x52774458UL, 0xbd217cc5UL, 0x3c8ad800UL,
+  0x3fda93edUL, 0xbea77a5dUL, 0x3d1e36f2UL, 0x0224f800UL, 0x3fda3344UL,
+  0x7f9d79f5UL, 0x3d23c645UL, 0xea15f000UL, 0x3fd9d32bUL, 0x10d0c0b0UL,
+  0xbd26279eUL, 0x43135800UL, 0x3fd973a3UL, 0xa502d9f0UL, 0xbd152313UL,
+  0x635bf800UL, 0x3fd914a8UL, 0x2ee6307dUL, 0xbd1766b5UL, 0xa88b3000UL,
+  0x3fd8b639UL, 0xe5e70470UL, 0xbd205ae1UL, 0x776dc800UL, 0x3fd85855UL,
+  0x3333778aUL, 0x3d2fd56fUL, 0x3bd81800UL, 0x3fd7fafaUL, 0xc812566aUL,
+  0xbd272090UL, 0x687cf800UL, 0x3fd79e26UL, 0x2efd1778UL, 0x3d29ec7dUL,
+  0x76c67800UL, 0x3fd741d8UL, 0x49dc60b3UL, 0x3d2d8b09UL, 0xe6af1800UL,
+  0x3fd6e60eUL, 0x7c222d87UL, 0x3d172165UL, 0x3e9c6800UL, 0x3fd68ac8UL,
+  0x2756eba0UL, 0x3d20a0d3UL, 0x0b3ab000UL, 0x3fd63003UL, 0xe731ae00UL,
+  0xbd2db623UL, 0xdf596000UL, 0x3fd5d5bdUL, 0x08a465dcUL, 0xbd0a0b2aUL,
+  0x53c8d000UL, 0x3fd57bf7UL, 0xee5d40efUL, 0x3d1fadedUL, 0x0738a000UL,
+  0x3fd522aeUL, 0x8164c759UL, 0x3d2ebe70UL, 0x9e173000UL, 0x3fd4c9e0UL,
+  0x1b0ad8a4UL, 0xbd2e2089UL, 0xc271c800UL, 0x3fd4718dUL, 0x0967d675UL,
+  0xbd2f27ceUL, 0x23d5e800UL, 0x3fd419b4UL, 0xec90e09dUL, 0x3d08e436UL,
+  0x77333000UL, 0x3fd3c252UL, 0xb606bd5cUL, 0x3d183b54UL, 0x76be1000UL,
+  0x3fd36b67UL, 0xb0f177c8UL, 0x3d116ecdUL, 0xe1d36000UL, 0x3fd314f1UL,
+  0xd3213cb8UL, 0xbd28e27aUL, 0x7cdc9000UL, 0x3fd2bef0UL, 0x4a5004f4UL,
+  0x3d2a9cfaUL, 0x1134d800UL, 0x3fd26962UL, 0xdf5bb3b6UL, 0x3d2c93c1UL,
+  0x6d0eb800UL, 0x3fd21445UL, 0xba46baeaUL, 0x3d0a87deUL, 0x635a6800UL,
+  0x3fd1bf99UL, 0x5147bdb7UL, 0x3d2ca6edUL, 0xcbacf800UL, 0x3fd16b5cUL,
+  0xf7a51681UL, 0x3d2b9acdUL, 0x8227e800UL, 0x3fd1178eUL, 0x63a5f01cUL,
+  0xbd2c210eUL, 0x67616000UL, 0x3fd0c42dUL, 0x163ceae9UL, 0x3d27188bUL,
+  0x604d5800UL, 0x3fd07138UL, 0x16ed4e91UL, 0x3cf89cdbUL, 0x5626c800UL,
+  0x3fd01eaeUL, 0x1485e94aUL, 0xbd16f08cUL, 0x6cb3b000UL, 0x3fcf991cUL,
+  0xca0cdf30UL, 0x3d1bcbecUL, 0xe4dd0000UL, 0x3fcef5adUL, 0x65bb8e11UL,
+  0xbcca2115UL, 0xffe71000UL, 0x3fce530eUL, 0x6041f430UL, 0x3cc21227UL,
+  0xb0d49000UL, 0x3fcdb13dUL, 0xf715b035UL, 0xbd2aff2aUL, 0xf2656000UL,
+  0x3fcd1037UL, 0x75b6f6e4UL, 0xbd084a7eUL, 0xc6f01000UL, 0x3fcc6ffbUL,
+  0xc5962bd2UL, 0xbcf1ec72UL, 0x383be000UL, 0x3fcbd087UL, 0x595412b6UL,
+  0xbd2d4bc4UL, 0x575bd000UL, 0x3fcb31d8UL, 0x4eace1aaUL, 0xbd0c358dUL,
+  0x3c8ae000UL, 0x3fca93edUL, 0x50562169UL, 0xbd287243UL, 0x07089000UL,
+  0x3fc9f6c4UL, 0x6865817aUL, 0x3d29904dUL, 0xdcf70000UL, 0x3fc95a5aUL,
+  0x58a0ff6fUL, 0x3d07f228UL, 0xeb390000UL, 0x3fc8beafUL, 0xaae92cd1UL,
+  0xbd073d54UL, 0x6551a000UL, 0x3fc823c1UL, 0x9a631e83UL, 0x3d1e0ddbUL,
+  0x85445000UL, 0x3fc7898dUL, 0x70914305UL, 0xbd1c6610UL, 0x8b757000UL,
+  0x3fc6f012UL, 0xe59c21e1UL, 0xbd25118dUL, 0xbe8c1000UL, 0x3fc6574eUL,
+  0x2c3c2e78UL, 0x3d19cf8bUL, 0x6b544000UL, 0x3fc5bf40UL, 0xeb68981cUL,
+  0xbd127023UL, 0xe4a1b000UL, 0x3fc527e5UL, 0xe5697dc7UL, 0x3d2633e8UL,
+  0x8333b000UL, 0x3fc4913dUL, 0x54fdb678UL, 0x3d258379UL, 0xa5993000UL,
+  0x3fc3fb45UL, 0x7e6a354dUL, 0xbd2cd1d8UL, 0xb0159000UL, 0x3fc365fcUL,
+  0x234b7289UL, 0x3cc62fa8UL, 0x0c868000UL, 0x3fc2d161UL, 0xcb81b4a1UL,
+  0x3d039d6cUL, 0x2a49c000UL, 0x3fc23d71UL, 0x8fd3df5cUL, 0x3d100d23UL,
+  0x7e23f000UL, 0x3fc1aa2bUL, 0x44389934UL, 0x3d2ca78eUL, 0x8227e000UL,
+  0x3fc1178eUL, 0xce2d07f2UL, 0x3d21ef78UL, 0xb59e4000UL, 0x3fc08598UL,
+  0x7009902cUL, 0xbd27e5ddUL, 0x39dbe000UL, 0x3fbfe891UL, 0x4fa10afdUL,
+  0xbd2534d6UL, 0x830a2000UL, 0x3fbec739UL, 0xafe645e0UL, 0xbd2dc068UL,
+  0x63844000UL, 0x3fbda727UL, 0x1fa71733UL, 0x3d1a8940UL, 0x01bc4000UL,
+  0x3fbc8858UL, 0xc65aacd3UL, 0x3d2646d1UL, 0x8dad6000UL, 0x3fbb6ac8UL,
+  0x2bf768e5UL, 0xbd139080UL, 0x40b1c000UL, 0x3fba4e76UL, 0xb94407c8UL,
+  0xbd0e42b6UL, 0x5d594000UL, 0x3fb9335eUL, 0x3abd47daUL, 0x3d23115cUL,
+  0x2f40e000UL, 0x3fb8197eUL, 0xf96ffdf7UL, 0x3d0f80dcUL, 0x0aeac000UL,
+  0x3fb700d3UL, 0xa99ded32UL, 0x3cec1e8dUL, 0x4d97a000UL, 0x3fb5e95aUL,
+  0x3c5d1d1eUL, 0xbd2c6906UL, 0x5d208000UL, 0x3fb4d311UL, 0x82f4e1efUL,
+  0xbcf53a25UL, 0xa7d1e000UL, 0x3fb3bdf5UL, 0xa5db4ed7UL, 0x3d2cc85eUL,
+  0xa4472000UL, 0x3fb2aa04UL, 0xae9c697dUL, 0xbd20b6e8UL, 0xd1466000UL,
+  0x3fb1973bUL, 0x560d9e9bUL, 0xbd25325dUL, 0xb59e4000UL, 0x3fb08598UL,
+  0x7009902cUL, 0xbd17e5ddUL, 0xc006c000UL, 0x3faeea31UL, 0x4fc93b7bUL,
+  0xbd0e113eUL, 0xcdddc000UL, 0x3faccb73UL, 0x47d82807UL, 0xbd1a68f2UL,
+  0xd0fb0000UL, 0x3faaaef2UL, 0x353bb42eUL, 0x3d20fc1aUL, 0x149fc000UL,
+  0x3fa894aaUL, 0xd05a267dUL, 0xbd197995UL, 0xf2d4c000UL, 0x3fa67c94UL,
+  0xec19afa2UL, 0xbd029efbUL, 0xd42e0000UL, 0x3fa466aeUL, 0x75bdfd28UL,
+  0xbd2c1673UL, 0x2f8d0000UL, 0x3fa252f3UL, 0xe021b67bUL, 0x3d283e9aUL,
+  0x89e74000UL, 0x3fa0415dUL, 0x5cf1d753UL, 0x3d0111c0UL, 0xec148000UL,
+  0x3f9c63d2UL, 0x3f9eb2f3UL, 0x3d2578c6UL, 0x28c90000UL, 0x3f984925UL,
+  0x325a0c34UL, 0xbd2aa0baUL, 0x25980000UL, 0x3f9432a9UL, 0x928637feUL,
+  0x3d098139UL, 0x58938000UL, 0x3f902056UL, 0x06e2f7d2UL, 0xbd23dc5bUL,
+  0xa3890000UL, 0x3f882448UL, 0xda74f640UL, 0xbd275577UL, 0x75890000UL,
+  0x3f801015UL, 0x999d2be8UL, 0xbd10c76bUL, 0x59580000UL, 0x3f700805UL,
+  0xcb31c67bUL, 0x3d2166afUL, 0x00000000UL, 0x00000000UL, 0x00000000UL,
+  0x80000000UL, 0xfefa3800UL, 0x3fa62e42UL, 0x93c76730UL, 0x3ceef357UL,
+  0x92492492UL, 0x3fc24924UL, 0x00000000UL, 0xbfd00000UL, 0x3d6fb175UL,
+  0xbfc5555eUL, 0x55555555UL, 0x3fd55555UL, 0x9999999aUL, 0x3fc99999UL,
+  0x00000000UL, 0xbfe00000UL, 0x00000000UL, 0xffffe000UL, 0x00000000UL,
+  0xffffe000UL
+};
+//registers,
+// input: xmm0
+// scratch: xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
+//          rax, rdx, rcx, rbx (tmp)
+
+void MacroAssembler::fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register eax, Register ecx, Register edx, Register tmp) {
+  Label L_2TAG_PACKET_0_0_2, L_2TAG_PACKET_1_0_2, L_2TAG_PACKET_2_0_2, L_2TAG_PACKET_3_0_2;
+  Label L_2TAG_PACKET_4_0_2, L_2TAG_PACKET_5_0_2, L_2TAG_PACKET_6_0_2, L_2TAG_PACKET_7_0_2;
+  Label L_2TAG_PACKET_8_0_2, L_2TAG_PACKET_9_0_2;
+  Label L_2TAG_PACKET_10_0_2, start;
+
+  assert_different_registers(tmp, eax, ecx, edx);
+  jmp(start);
+  address static_const_table = (address)_static_const_table_log;
+
+  bind(start);
+  subl(rsp, 104);
+  movl(Address(rsp, 40), tmp);
+  lea(tmp, ExternalAddress(static_const_table));
+  xorpd(xmm2, xmm2);
+  movl(eax, 16368);
+  pinsrw(xmm2, eax, 3);
+  xorpd(xmm3, xmm3);
+  movl(edx, 30704);
+  pinsrw(xmm3, edx, 3);
+  movsd(xmm0, Address(rsp, 112));
+  movapd(xmm1, xmm0);
+  movl(ecx, 32768);
+  movdl(xmm4, ecx);
+  movsd(xmm5, Address(tmp, 2128));         // 0x00000000UL, 0xffffe000UL
+  pextrw(eax, xmm0, 3);
+  por(xmm0, xmm2);
+  psllq(xmm0, 5);
+  movl(ecx, 16352);
+  psrlq(xmm0, 34);
+  rcpss(xmm0, xmm0);
+  psllq(xmm1, 12);
+  pshufd(xmm6, xmm5, 228);
+  psrlq(xmm1, 12);
+  subl(eax, 16);
+  cmpl(eax, 32736);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_0_0_2);
+
+  bind(L_2TAG_PACKET_1_0_2);
+  paddd(xmm0, xmm4);
+  por(xmm1, xmm3);
+  movdl(edx, xmm0);
+  psllq(xmm0, 29);
+  pand(xmm5, xmm1);
+  pand(xmm0, xmm6);
+  subsd(xmm1, xmm5);
+  mulpd(xmm5, xmm0);
+  andl(eax, 32752);
+  subl(eax, ecx);
+  cvtsi2sdl(xmm7, eax);
+  mulsd(xmm1, xmm0);
+  movsd(xmm6, Address(tmp, 2064));         // 0xfefa3800UL, 0x3fa62e42UL
+  movdqu(xmm3, Address(tmp, 2080));        // 0x92492492UL, 0x3fc24924UL, 0x00000000UL, 0xbfd00000UL
+  subsd(xmm5, xmm2);
+  andl(edx, 16711680);
+  shrl(edx, 12);
+  movdqu(xmm0, Address(tmp, edx));
+  movdqu(xmm4, Address(tmp, 2096));        // 0x3d6fb175UL, 0xbfc5555eUL, 0x55555555UL, 0x3fd55555UL
+  addsd(xmm1, xmm5);
+  movdqu(xmm2, Address(tmp, 2112));        // 0x9999999aUL, 0x3fc99999UL, 0x00000000UL, 0xbfe00000UL
+  mulsd(xmm6, xmm7);
+  pshufd(xmm5, xmm1, 68);
+  mulsd(xmm7, Address(tmp, 2072));         // 0x93c76730UL, 0x3ceef357UL, 0x92492492UL, 0x3fc24924UL
+  mulsd(xmm3, xmm1);
+  addsd(xmm0, xmm6);
+  mulpd(xmm4, xmm5);
+  mulpd(xmm5, xmm5);
+  pshufd(xmm6, xmm0, 228);
+  addsd(xmm0, xmm1);
+  addpd(xmm4, xmm2);
+  mulpd(xmm3, xmm5);
+  subsd(xmm6, xmm0);
+  mulsd(xmm4, xmm1);
+  pshufd(xmm2, xmm0, 238);
+  addsd(xmm1, xmm6);
+  mulsd(xmm5, xmm5);
+  addsd(xmm7, xmm2);
+  addpd(xmm4, xmm3);
+  addsd(xmm1, xmm7);
+  mulpd(xmm4, xmm5);
+  addsd(xmm1, xmm4);
+  pshufd(xmm5, xmm4, 238);
+  addsd(xmm1, xmm5);
+  addsd(xmm0, xmm1);
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_0_0_2);
+  movsd(xmm0, Address(rsp, 112));
+  movdqu(xmm1, xmm0);
+  addl(eax, 16);
+  cmpl(eax, 32768);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_3_0_2);
+  cmpl(eax, 16);
+  jcc(Assembler::below, L_2TAG_PACKET_4_0_2);
+
+  bind(L_2TAG_PACKET_5_0_2);
+  addsd(xmm0, xmm0);
+  jmp(L_2TAG_PACKET_2_0_2);
+
+  bind(L_2TAG_PACKET_6_0_2);
+  jcc(Assembler::above, L_2TAG_PACKET_5_0_2);
+  cmpl(edx, 0);
+  jcc(Assembler::above, L_2TAG_PACKET_5_0_2);
+  jmp(L_2TAG_PACKET_7_0_2);
+
+  bind(L_2TAG_PACKET_3_0_2);
+  movdl(edx, xmm1);
+  psrlq(xmm1, 32);
+  movdl(ecx, xmm1);
+  addl(ecx, ecx);
+  cmpl(ecx, -2097152);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_6_0_2);
+  orl(edx, ecx);
+  cmpl(edx, 0);
+  jcc(Assembler::equal, L_2TAG_PACKET_8_0_2);
+
+  bind(L_2TAG_PACKET_7_0_2);
+  xorpd(xmm1, xmm1);
+  xorpd(xmm0, xmm0);
+  movl(eax, 32752);
+  pinsrw(xmm1, eax, 3);
+  movl(edx, 3);
+  mulsd(xmm0, xmm1);
+
+  bind(L_2TAG_PACKET_9_0_2);
+  movsd(Address(rsp, 0), xmm0);
+  movsd(xmm0, Address(rsp, 112));
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_10_0_2);
+
+  bind(L_2TAG_PACKET_8_0_2);
+  xorpd(xmm1, xmm1);
+  xorpd(xmm0, xmm0);
+  movl(eax, 49136);
+  pinsrw(xmm0, eax, 3);
+  divsd(xmm0, xmm1);
+  movl(edx, 2);
+  jmp(L_2TAG_PACKET_9_0_2);
+
+  bind(L_2TAG_PACKET_4_0_2);
+  movdl(edx, xmm1);
+  psrlq(xmm1, 32);
+  movdl(ecx, xmm1);
+  orl(edx, ecx);
+  cmpl(edx, 0);
+  jcc(Assembler::equal, L_2TAG_PACKET_8_0_2);
+  xorpd(xmm1, xmm1);
+  movl(eax, 18416);
+  pinsrw(xmm1, eax, 3);
+  mulsd(xmm0, xmm1);
+  movapd(xmm1, xmm0);
+  pextrw(eax, xmm0, 3);
+  por(xmm0, xmm2);
+  psllq(xmm0, 5);
+  movl(ecx, 18416);
+  psrlq(xmm0, 34);
+  rcpss(xmm0, xmm0);
+  psllq(xmm1, 12);
+  pshufd(xmm6, xmm5, 228);
+  psrlq(xmm1, 12);
+  jmp(L_2TAG_PACKET_1_0_2);
+
+  bind(L_2TAG_PACKET_2_0_2);
+  movsd(Address(rsp, 24), xmm0);
+  fld_d(Address(rsp, 24));
+
+  bind(L_2TAG_PACKET_10_0_2);
+  movl(tmp, Address(rsp, 40));
+}
+
+/******************************************************************************/
+//                     ALGORITHM DESCRIPTION  - POW()
+//                     ---------------------
+//
+//    Let x=2^k * mx, mx in [1,2)
+//
+//    log2(x) calculation:
+//
+//    Get B~1/mx based on the output of rcpps instruction (B0)
+//    B = int((B0*LH*2^9+0.5))/2^9
+//    LH is a short approximation for log2(e)
+//
+//    Reduced argument, scaled by LH:
+//                r=B*mx-LH (computed accurately in high and low parts)
+//
+//    log2(x) result:  k - log2(B) + p(r)
+//             p(r) is a degree 8 polynomial
+//             -log2(B) read from data table (high, low parts)
+//             log2(x) is formed from high and low parts
+//    For |x| in [1-1/32, 1+1/16), a slower but more accurate computation
+//    based om the same table design is performed.
+//
+//   Main path is taken if | floor(log2(|log2(|x|)|) + floor(log2|y|) | < 8,
+//   to filter out all potential OF/UF cases.
+//   exp2(y*log2(x)) is computed using an 8-bit index table and a degree 5
+//   polynomial
+//
+// Special cases:
+//  pow(-0,y) = -INF and raises the divide-by-zero exception for y an odd
+//  integer < 0.
+//  pow(-0,y) = +INF and raises the divide-by-zero exception for y < 0 and
+//  not an odd integer.
+//  pow(-0,y) = -0 for y an odd integer > 0.
+//  pow(-0,y) = +0 for y > 0 and not an odd integer.
+//  pow(-1,-INF) = NaN.
+//  pow(+1,y) = NaN for any y, even a NaN.
+//  pow(x,-0) = 1 for any x, even a NaN.
+//  pow(x,y) = a NaN and raises the invalid exception for finite x < 0 and
+//  finite non-integer y.
+//  pow(x,-INF) = +INF for |x|<1.
+//  pow(x,-INF) = +0 for |x|>1.
+//  pow(x,+INF) = +0 for |x|<1.
+//  pow(x,+INF) = +INF for |x|>1.
+//  pow(-INF,y) = -0 for y an odd integer < 0.
+//  pow(-INF,y) = +0 for y < 0 and not an odd integer.
+//  pow(-INF,y) = -INF for y an odd integer > 0.
+//  pow(-INF,y) = +INF for y > 0 and not an odd integer.
+//  pow(+INF,y) = +0 for y <0.
+//  pow(+INF,y) = +INF for y >0.
+//
+/******************************************************************************/
+
+ALIGNED_(16) juint _static_const_table_pow[] =
+{
+  0x00000000UL, 0xbfd61a00UL, 0x00000000UL, 0xbf5dabe1UL, 0xf8000000UL,
+  0xffffffffUL, 0x00000000UL, 0xfffff800UL, 0x00000000UL, 0x3ff00000UL,
+  0x00000000UL, 0x00000000UL, 0x20000000UL, 0x3feff00aUL, 0x96621f95UL,
+  0x3e5b1856UL, 0xe0000000UL, 0x3fefe019UL, 0xe5916f9eUL, 0xbe325278UL,
+  0x00000000UL, 0x3fefd02fUL, 0x859a1062UL, 0x3e595fb7UL, 0xc0000000UL,
+  0x3fefc049UL, 0xb245f18fUL, 0xbe529c38UL, 0xe0000000UL, 0x3fefb069UL,
+  0xad2880a7UL, 0xbe501230UL, 0x60000000UL, 0x3fefa08fUL, 0xc8e72420UL,
+  0x3e597bd1UL, 0x80000000UL, 0x3fef90baUL, 0xc30c4500UL, 0xbe5d6c75UL,
+  0xe0000000UL, 0x3fef80eaUL, 0x02c63f43UL, 0x3e2e1318UL, 0xc0000000UL,
+  0x3fef7120UL, 0xb3d4ccccUL, 0xbe44c52aUL, 0x00000000UL, 0x3fef615cUL,
+  0xdbd91397UL, 0xbe4e7d6cUL, 0xa0000000UL, 0x3fef519cUL, 0x65c5cd68UL,
+  0xbe522dc8UL, 0xa0000000UL, 0x3fef41e2UL, 0x46d1306cUL, 0xbe5a840eUL,
+  0xe0000000UL, 0x3fef322dUL, 0xd2980e94UL, 0x3e5071afUL, 0xa0000000UL,
+  0x3fef227eUL, 0x773abadeUL, 0xbe5891e5UL, 0xa0000000UL, 0x3fef12d4UL,
+  0xdc6bf46bUL, 0xbe5cccbeUL, 0xe0000000UL, 0x3fef032fUL, 0xbc7247faUL,
+  0xbe2bab83UL, 0x80000000UL, 0x3feef390UL, 0xbcaa1e46UL, 0xbe53bb3bUL,
+  0x60000000UL, 0x3feee3f6UL, 0x5f6c682dUL, 0xbe54c619UL, 0x80000000UL,
+  0x3feed461UL, 0x5141e368UL, 0xbe4b6d86UL, 0xe0000000UL, 0x3feec4d1UL,
+  0xec678f76UL, 0xbe369af6UL, 0x80000000UL, 0x3feeb547UL, 0x41301f55UL,
+  0xbe2d4312UL, 0x60000000UL, 0x3feea5c2UL, 0x676da6bdUL, 0xbe4d8dd0UL,
+  0x60000000UL, 0x3fee9642UL, 0x57a891c4UL, 0x3e51f991UL, 0xa0000000UL,
+  0x3fee86c7UL, 0xe4eb491eUL, 0x3e579bf9UL, 0x20000000UL, 0x3fee7752UL,
+  0xfddc4a2cUL, 0xbe3356e6UL, 0xc0000000UL, 0x3fee67e1UL, 0xd75b5bf1UL,
+  0xbe449531UL, 0x80000000UL, 0x3fee5876UL, 0xbd423b8eUL, 0x3df54fe4UL,
+  0x60000000UL, 0x3fee4910UL, 0x330e51b9UL, 0x3e54289cUL, 0x80000000UL,
+  0x3fee39afUL, 0x8651a95fUL, 0xbe55aad6UL, 0xa0000000UL, 0x3fee2a53UL,
+  0x5e98c708UL, 0xbe2fc4a9UL, 0xe0000000UL, 0x3fee1afcUL, 0x0989328dUL,
+  0x3e23958cUL, 0x40000000UL, 0x3fee0babUL, 0xee642abdUL, 0xbe425dd8UL,
+  0xa0000000UL, 0x3fedfc5eUL, 0xc394d236UL, 0x3e526362UL, 0x20000000UL,
+  0x3feded17UL, 0xe104aa8eUL, 0x3e4ce247UL, 0xc0000000UL, 0x3fedddd4UL,
+  0x265a9be4UL, 0xbe5bb77aUL, 0x40000000UL, 0x3fedce97UL, 0x0ecac52fUL,
+  0x3e4a7cb1UL, 0xe0000000UL, 0x3fedbf5eUL, 0x124cb3b8UL, 0x3e257024UL,
+  0x80000000UL, 0x3fedb02bUL, 0xe6d4febeUL, 0xbe2033eeUL, 0x20000000UL,
+  0x3feda0fdUL, 0x39cca00eUL, 0xbe3ddabcUL, 0xc0000000UL, 0x3fed91d3UL,
+  0xef8a552aUL, 0xbe543390UL, 0x40000000UL, 0x3fed82afUL, 0xb8e85204UL,
+  0x3e513850UL, 0xe0000000UL, 0x3fed738fUL, 0x3d59fe08UL, 0xbe5db728UL,
+  0x40000000UL, 0x3fed6475UL, 0x3aa7ead1UL, 0x3e58804bUL, 0xc0000000UL,
+  0x3fed555fUL, 0xf8a35ba9UL, 0xbe5298b0UL, 0x00000000UL, 0x3fed464fUL,
+  0x9a88dd15UL, 0x3e5a8cdbUL, 0x40000000UL, 0x3fed3743UL, 0xb0b0a190UL,
+  0x3e598635UL, 0x80000000UL, 0x3fed283cUL, 0xe2113295UL, 0xbe5c1119UL,
+  0x80000000UL, 0x3fed193aUL, 0xafbf1728UL, 0xbe492e9cUL, 0x60000000UL,
+  0x3fed0a3dUL, 0xe4a4ccf3UL, 0x3e19b90eUL, 0x20000000UL, 0x3fecfb45UL,
+  0xba3cbeb8UL, 0x3e406b50UL, 0xc0000000UL, 0x3fecec51UL, 0x110f7dddUL,
+  0x3e0d6806UL, 0x40000000UL, 0x3fecdd63UL, 0x7dd7d508UL, 0xbe5a8943UL,
+  0x80000000UL, 0x3fecce79UL, 0x9b60f271UL, 0xbe50676aUL, 0x80000000UL,
+  0x3fecbf94UL, 0x0b9ad660UL, 0x3e59174fUL, 0x60000000UL, 0x3fecb0b4UL,
+  0x00823d9cUL, 0x3e5bbf72UL, 0x20000000UL, 0x3feca1d9UL, 0x38a6ec89UL,
+  0xbe4d38f9UL, 0x80000000UL, 0x3fec9302UL, 0x3a0b7d8eUL, 0x3e53dbfdUL,
+  0xc0000000UL, 0x3fec8430UL, 0xc6826b34UL, 0xbe27c5c9UL, 0xc0000000UL,
+  0x3fec7563UL, 0x0c706381UL, 0xbe593653UL, 0x60000000UL, 0x3fec669bUL,
+  0x7df34ec7UL, 0x3e461ab5UL, 0xe0000000UL, 0x3fec57d7UL, 0x40e5e7e8UL,
+  0xbe5c3daeUL, 0x00000000UL, 0x3fec4919UL, 0x5602770fUL, 0xbe55219dUL,
+  0xc0000000UL, 0x3fec3a5eUL, 0xec7911ebUL, 0x3e5a5d25UL, 0x60000000UL,
+  0x3fec2ba9UL, 0xb39ea225UL, 0xbe53c00bUL, 0x80000000UL, 0x3fec1cf8UL,
+  0x967a212eUL, 0x3e5a8ddfUL, 0x60000000UL, 0x3fec0e4cUL, 0x580798bdUL,
+  0x3e5f53abUL, 0x00000000UL, 0x3febffa5UL, 0xb8282df6UL, 0xbe46b874UL,
+  0x20000000UL, 0x3febf102UL, 0xe33a6729UL, 0x3e54963fUL, 0x00000000UL,
+  0x3febe264UL, 0x3b53e88aUL, 0xbe3adce1UL, 0x60000000UL, 0x3febd3caUL,
+  0xc2585084UL, 0x3e5cde9fUL, 0x80000000UL, 0x3febc535UL, 0xa335c5eeUL,
+  0xbe39fd9cUL, 0x20000000UL, 0x3febb6a5UL, 0x7325b04dUL, 0x3e42ba15UL,
+  0x60000000UL, 0x3feba819UL, 0x1564540fUL, 0x3e3a9f35UL, 0x40000000UL,
+  0x3feb9992UL, 0x83fff592UL, 0xbe5465ceUL, 0xa0000000UL, 0x3feb8b0fUL,
+  0xb9da63d3UL, 0xbe4b1a0aUL, 0x80000000UL, 0x3feb7c91UL, 0x6d6f1ea4UL,
+  0x3e557657UL, 0x00000000UL, 0x3feb6e18UL, 0x5e80a1bfUL, 0x3e4ddbb6UL,
+  0x00000000UL, 0x3feb5fa3UL, 0x1c9eacb5UL, 0x3e592877UL, 0xa0000000UL,
+  0x3feb5132UL, 0x6d40beb3UL, 0xbe51858cUL, 0xa0000000UL, 0x3feb42c6UL,
+  0xd740c67bUL, 0x3e427ad2UL, 0x40000000UL, 0x3feb345fUL, 0xa3e0cceeUL,
+  0xbe5c2fc4UL, 0x40000000UL, 0x3feb25fcUL, 0x8e752b50UL, 0xbe3da3c2UL,
+  0xc0000000UL, 0x3feb179dUL, 0xa892e7deUL, 0x3e1fb481UL, 0xc0000000UL,
+  0x3feb0943UL, 0x21ed71e9UL, 0xbe365206UL, 0x20000000UL, 0x3feafaeeUL,
+  0x0e1380a3UL, 0x3e5c5b7bUL, 0x20000000UL, 0x3feaec9dUL, 0x3c3d640eUL,
+  0xbe5dbbd0UL, 0x60000000UL, 0x3feade50UL, 0x8f97a715UL, 0x3e3a8ec5UL,
+  0x20000000UL, 0x3fead008UL, 0x23ab2839UL, 0x3e2fe98aUL, 0x40000000UL,
+  0x3feac1c4UL, 0xf4bbd50fUL, 0x3e54d8f6UL, 0xe0000000UL, 0x3feab384UL,
+  0x14757c4dUL, 0xbe48774cUL, 0xc0000000UL, 0x3feaa549UL, 0x7c7b0eeaUL,
+  0x3e5b51bbUL, 0x20000000UL, 0x3fea9713UL, 0xf56f7013UL, 0x3e386200UL,
+  0xe0000000UL, 0x3fea88e0UL, 0xbe428ebeUL, 0xbe514af5UL, 0xe0000000UL,
+  0x3fea7ab2UL, 0x8d0e4496UL, 0x3e4f9165UL, 0x60000000UL, 0x3fea6c89UL,
+  0xdbacc5d5UL, 0xbe5c063bUL, 0x20000000UL, 0x3fea5e64UL, 0x3f19d970UL,
+  0xbe5a0c8cUL, 0x20000000UL, 0x3fea5043UL, 0x09ea3e6bUL, 0x3e5065dcUL,
+  0x80000000UL, 0x3fea4226UL, 0x78df246cUL, 0x3e5e05f6UL, 0x40000000UL,
+  0x3fea340eUL, 0x4057d4a0UL, 0x3e431b2bUL, 0x40000000UL, 0x3fea25faUL,
+  0x82867bb5UL, 0x3e4b76beUL, 0xa0000000UL, 0x3fea17eaUL, 0x9436f40aUL,
+  0xbe5aad39UL, 0x20000000UL, 0x3fea09dfUL, 0x4b5253b3UL, 0x3e46380bUL,
+  0x00000000UL, 0x3fe9fbd8UL, 0x8fc52466UL, 0xbe386f9bUL, 0x20000000UL,
+  0x3fe9edd5UL, 0x22d3f344UL, 0xbe538347UL, 0x60000000UL, 0x3fe9dfd6UL,
+  0x1ac33522UL, 0x3e5dbc53UL, 0x00000000UL, 0x3fe9d1dcUL, 0xeabdff1dUL,
+  0x3e40fc0cUL, 0xe0000000UL, 0x3fe9c3e5UL, 0xafd30e73UL, 0xbe585e63UL,
+  0xe0000000UL, 0x3fe9b5f3UL, 0xa52f226aUL, 0xbe43e8f9UL, 0x20000000UL,
+  0x3fe9a806UL, 0xecb8698dUL, 0xbe515b36UL, 0x80000000UL, 0x3fe99a1cUL,
+  0xf2b4e89dUL, 0x3e48b62bUL, 0x20000000UL, 0x3fe98c37UL, 0x7c9a88fbUL,
+  0x3e44414cUL, 0x00000000UL, 0x3fe97e56UL, 0xda015741UL, 0xbe5d13baUL,
+  0xe0000000UL, 0x3fe97078UL, 0x5fdace06UL, 0x3e51b947UL, 0x00000000UL,
+  0x3fe962a0UL, 0x956ca094UL, 0x3e518785UL, 0x40000000UL, 0x3fe954cbUL,
+  0x01164c1dUL, 0x3e5d5b57UL, 0xc0000000UL, 0x3fe946faUL, 0xe63b3767UL,
+  0xbe4f84e7UL, 0x40000000UL, 0x3fe9392eUL, 0xe57cc2a9UL, 0x3e34eda3UL,
+  0xe0000000UL, 0x3fe92b65UL, 0x8c75b544UL, 0x3e5766a0UL, 0xc0000000UL,
+  0x3fe91da1UL, 0x37d1d087UL, 0xbe5e2ab1UL, 0x80000000UL, 0x3fe90fe1UL,
+  0xa953dc20UL, 0x3e5fa1f3UL, 0x80000000UL, 0x3fe90225UL, 0xdbd3f369UL,
+  0x3e47d6dbUL, 0xa0000000UL, 0x3fe8f46dUL, 0x1c9be989UL, 0xbe5e2b0aUL,
+  0xa0000000UL, 0x3fe8e6b9UL, 0x3c93d76aUL, 0x3e5c8618UL, 0xe0000000UL,
+  0x3fe8d909UL, 0x2182fc9aUL, 0xbe41aa9eUL, 0x20000000UL, 0x3fe8cb5eUL,
+  0xe6b3539dUL, 0xbe530d19UL, 0x60000000UL, 0x3fe8bdb6UL, 0x49e58cc3UL,
+  0xbe3bb374UL, 0xa0000000UL, 0x3fe8b012UL, 0xa7cfeb8fUL, 0x3e56c412UL,
+  0x00000000UL, 0x3fe8a273UL, 0x8d52bc19UL, 0x3e1429b8UL, 0x60000000UL,
+  0x3fe894d7UL, 0x4dc32c6cUL, 0xbe48604cUL, 0xc0000000UL, 0x3fe8873fUL,
+  0x0c868e56UL, 0xbe564ee5UL, 0x00000000UL, 0x3fe879acUL, 0x56aee828UL,
+  0x3e5e2fd8UL, 0x60000000UL, 0x3fe86c1cUL, 0x7ceab8ecUL, 0x3e493365UL,
+  0xc0000000UL, 0x3fe85e90UL, 0x78d4dadcUL, 0xbe4f7f25UL, 0x00000000UL,
+  0x3fe85109UL, 0x0ccd8280UL, 0x3e31e7a2UL, 0x40000000UL, 0x3fe84385UL,
+  0x34ba4e15UL, 0x3e328077UL, 0x80000000UL, 0x3fe83605UL, 0xa670975aUL,
+  0xbe53eee5UL, 0xa0000000UL, 0x3fe82889UL, 0xf61b77b2UL, 0xbe43a20aUL,
+  0xa0000000UL, 0x3fe81b11UL, 0x13e6643bUL, 0x3e5e5fe5UL, 0xc0000000UL,
+  0x3fe80d9dUL, 0x82cc94e8UL, 0xbe5ff1f9UL, 0xa0000000UL, 0x3fe8002dUL,
+  0x8a0c9c5dUL, 0xbe42b0e7UL, 0x60000000UL, 0x3fe7f2c1UL, 0x22a16f01UL,
+  0x3e5d9ea0UL, 0x20000000UL, 0x3fe7e559UL, 0xc38cd451UL, 0x3e506963UL,
+  0xc0000000UL, 0x3fe7d7f4UL, 0x9902bc71UL, 0x3e4503d7UL, 0x40000000UL,
+  0x3fe7ca94UL, 0xdef2a3c0UL, 0x3e3d98edUL, 0xa0000000UL, 0x3fe7bd37UL,
+  0xed49abb0UL, 0x3e24c1ffUL, 0xe0000000UL, 0x3fe7afdeUL, 0xe3b0be70UL,
+  0xbe40c467UL, 0x00000000UL, 0x3fe7a28aUL, 0xaf9f193cUL, 0xbe5dff6cUL,
+  0xe0000000UL, 0x3fe79538UL, 0xb74cf6b6UL, 0xbe258ed0UL, 0xa0000000UL,
+  0x3fe787ebUL, 0x1d9127c7UL, 0x3e345fb0UL, 0x40000000UL, 0x3fe77aa2UL,
+  0x1028c21dUL, 0xbe4619bdUL, 0xa0000000UL, 0x3fe76d5cUL, 0x7cb0b5e4UL,
+  0x3e40f1a2UL, 0xe0000000UL, 0x3fe7601aUL, 0x2b1bc4adUL, 0xbe32e8bbUL,
+  0xe0000000UL, 0x3fe752dcUL, 0x6839f64eUL, 0x3e41f57bUL, 0xc0000000UL,
+  0x3fe745a2UL, 0xc4121f7eUL, 0xbe52c40aUL, 0x60000000UL, 0x3fe7386cUL,
+  0xd6852d72UL, 0xbe5c4e6bUL, 0xc0000000UL, 0x3fe72b39UL, 0x91d690f7UL,
+  0xbe57f88fUL, 0xe0000000UL, 0x3fe71e0aUL, 0x627a2159UL, 0xbe4425d5UL,
+  0xc0000000UL, 0x3fe710dfUL, 0x50a54033UL, 0x3e422b7eUL, 0x60000000UL,
+  0x3fe703b8UL, 0x3b0b5f91UL, 0x3e5d3857UL, 0xe0000000UL, 0x3fe6f694UL,
+  0x84d628a2UL, 0xbe51f090UL, 0x00000000UL, 0x3fe6e975UL, 0x306d8894UL,
+  0xbe414d83UL, 0xe0000000UL, 0x3fe6dc58UL, 0x30bf24aaUL, 0xbe4650caUL,
+  0x80000000UL, 0x3fe6cf40UL, 0xd4628d69UL, 0xbe5db007UL, 0xc0000000UL,
+  0x3fe6c22bUL, 0xa2aae57bUL, 0xbe31d279UL, 0xc0000000UL, 0x3fe6b51aUL,
+  0x860edf7eUL, 0xbe2d4c4aUL, 0x80000000UL, 0x3fe6a80dUL, 0xf3559341UL,
+  0xbe5f7e98UL, 0xe0000000UL, 0x3fe69b03UL, 0xa885899eUL, 0xbe5c2011UL,
+  0xe0000000UL, 0x3fe68dfdUL, 0x2bdc6d37UL, 0x3e224a82UL, 0xa0000000UL,
+  0x3fe680fbUL, 0xc12ad1b9UL, 0xbe40cf56UL, 0x00000000UL, 0x3fe673fdUL,
+  0x1bcdf659UL, 0xbdf52f2dUL, 0x00000000UL, 0x3fe66702UL, 0x5df10408UL,
+  0x3e5663e0UL, 0xc0000000UL, 0x3fe65a0aUL, 0xa4070568UL, 0xbe40b12fUL,
+  0x00000000UL, 0x3fe64d17UL, 0x71c54c47UL, 0x3e5f5e8bUL, 0x00000000UL,
+  0x3fe64027UL, 0xbd4b7e83UL, 0x3e42ead6UL, 0xa0000000UL, 0x3fe6333aUL,
+  0x61598bd2UL, 0xbe4c48d4UL, 0xc0000000UL, 0x3fe62651UL, 0x6f538d61UL,
+  0x3e548401UL, 0xa0000000UL, 0x3fe6196cUL, 0x14344120UL, 0xbe529af6UL,
+  0x00000000UL, 0x3fe60c8bUL, 0x5982c587UL, 0xbe3e1e4fUL, 0x00000000UL,
+  0x3fe5ffadUL, 0xfe51d4eaUL, 0xbe4c897aUL, 0x80000000UL, 0x3fe5f2d2UL,
+  0xfd46ebe1UL, 0x3e552e00UL, 0xa0000000UL, 0x3fe5e5fbUL, 0xa4695699UL,
+  0x3e5ed471UL, 0x60000000UL, 0x3fe5d928UL, 0x80d118aeUL, 0x3e456b61UL,
+  0xa0000000UL, 0x3fe5cc58UL, 0x304c330bUL, 0x3e54dc29UL, 0x80000000UL,
+  0x3fe5bf8cUL, 0x0af2dedfUL, 0xbe3aa9bdUL, 0xe0000000UL, 0x3fe5b2c3UL,
+  0x15fc9258UL, 0xbe479a37UL, 0xc0000000UL, 0x3fe5a5feUL, 0x9292c7eaUL,
+  0x3e188650UL, 0x20000000UL, 0x3fe5993dUL, 0x33b4d380UL, 0x3e5d6d93UL,
+  0x20000000UL, 0x3fe58c7fUL, 0x02fd16c7UL, 0x3e2fe961UL, 0xa0000000UL,
+  0x3fe57fc4UL, 0x4a05edb6UL, 0xbe4d55b4UL, 0xa0000000UL, 0x3fe5730dUL,
+  0x3d443abbUL, 0xbe5e6954UL, 0x00000000UL, 0x3fe5665aUL, 0x024acfeaUL,
+  0x3e50e61bUL, 0x00000000UL, 0x3fe559aaUL, 0xcc9edd09UL, 0xbe325403UL,
+  0x60000000UL, 0x3fe54cfdUL, 0x1fe26950UL, 0x3e5d500eUL, 0x60000000UL,
+  0x3fe54054UL, 0x6c5ae164UL, 0xbe4a79b4UL, 0xc0000000UL, 0x3fe533aeUL,
+  0x154b0287UL, 0xbe401571UL, 0xa0000000UL, 0x3fe5270cUL, 0x0673f401UL,
+  0xbe56e56bUL, 0xe0000000UL, 0x3fe51a6dUL, 0x751b639cUL, 0x3e235269UL,
+  0xa0000000UL, 0x3fe50dd2UL, 0x7c7b2bedUL, 0x3ddec887UL, 0xc0000000UL,
+  0x3fe5013aUL, 0xafab4e17UL, 0x3e5e7575UL, 0x60000000UL, 0x3fe4f4a6UL,
+  0x2e308668UL, 0x3e59aed6UL, 0x80000000UL, 0x3fe4e815UL, 0xf33e2a76UL,
+  0xbe51f184UL, 0xe0000000UL, 0x3fe4db87UL, 0x839f3e3eUL, 0x3e57db01UL,
+  0xc0000000UL, 0x3fe4cefdUL, 0xa9eda7bbUL, 0x3e535e0fUL, 0x00000000UL,
+  0x3fe4c277UL, 0x2a8f66a5UL, 0x3e5ce451UL, 0xc0000000UL, 0x3fe4b5f3UL,
+  0x05192456UL, 0xbe4e8518UL, 0xc0000000UL, 0x3fe4a973UL, 0x4aa7cd1dUL,
+  0x3e46784aUL, 0x40000000UL, 0x3fe49cf7UL, 0x8e23025eUL, 0xbe5749f2UL,
+  0x00000000UL, 0x3fe4907eUL, 0x18d30215UL, 0x3e360f39UL, 0x20000000UL,
+  0x3fe48408UL, 0x63dcf2f3UL, 0x3e5e00feUL, 0xc0000000UL, 0x3fe47795UL,
+  0x46182d09UL, 0xbe5173d9UL, 0xa0000000UL, 0x3fe46b26UL, 0x8f0e62aaUL,
+  0xbe48f281UL, 0xe0000000UL, 0x3fe45ebaUL, 0x5775c40cUL, 0xbe56aad4UL,
+  0x60000000UL, 0x3fe45252UL, 0x0fe25f69UL, 0x3e48bd71UL, 0x40000000UL,
+  0x3fe445edUL, 0xe9989ec5UL, 0x3e590d97UL, 0x80000000UL, 0x3fe4398bUL,
+  0xb3d9ffe3UL, 0x3e479dbcUL, 0x20000000UL, 0x3fe42d2dUL, 0x388e4d2eUL,
+  0xbe5eed80UL, 0xe0000000UL, 0x3fe420d1UL, 0x6f797c18UL, 0x3e554b4cUL,
+  0x20000000UL, 0x3fe4147aUL, 0x31048bb4UL, 0xbe5b1112UL, 0x80000000UL,
+  0x3fe40825UL, 0x2efba4f9UL, 0x3e48ebc7UL, 0x40000000UL, 0x3fe3fbd4UL,
+  0x50201119UL, 0x3e40b701UL, 0x40000000UL, 0x3fe3ef86UL, 0x0a4db32cUL,
+  0x3e551de8UL, 0xa0000000UL, 0x3fe3e33bUL, 0x0c9c148bUL, 0xbe50c1f6UL,
+  0x20000000UL, 0x3fe3d6f4UL, 0xc9129447UL, 0x3e533fa0UL, 0x00000000UL,
+  0x3fe3cab0UL, 0xaae5b5a0UL, 0xbe22b68eUL, 0x20000000UL, 0x3fe3be6fUL,
+  0x02305e8aUL, 0xbe54fc08UL, 0x60000000UL, 0x3fe3b231UL, 0x7f908258UL,
+  0x3e57dc05UL, 0x00000000UL, 0x3fe3a5f7UL, 0x1a09af78UL, 0x3e08038bUL,
+  0xe0000000UL, 0x3fe399bfUL, 0x490643c1UL, 0xbe5dbe42UL, 0xe0000000UL,
+  0x3fe38d8bUL, 0x5e8ad724UL, 0xbe3c2b72UL, 0x20000000UL, 0x3fe3815bUL,
+  0xc67196b6UL, 0x3e1713cfUL, 0xa0000000UL, 0x3fe3752dUL, 0x6182e429UL,
+  0xbe3ec14cUL, 0x40000000UL, 0x3fe36903UL, 0xab6eb1aeUL, 0x3e5a2cc5UL,
+  0x40000000UL, 0x3fe35cdcUL, 0xfe5dc064UL, 0xbe5c5878UL, 0x40000000UL,
+  0x3fe350b8UL, 0x0ba6b9e4UL, 0x3e51619bUL, 0x80000000UL, 0x3fe34497UL,
+  0x857761aaUL, 0x3e5fff53UL, 0x00000000UL, 0x3fe3387aUL, 0xf872d68cUL,
+  0x3e484f4dUL, 0xa0000000UL, 0x3fe32c5fUL, 0x087e97c2UL, 0x3e52842eUL,
+  0x80000000UL, 0x3fe32048UL, 0x73d6d0c0UL, 0xbe503edfUL, 0x80000000UL,
+  0x3fe31434UL, 0x0c1456a1UL, 0xbe5f72adUL, 0xa0000000UL, 0x3fe30823UL,
+  0x83a1a4d5UL, 0xbe5e65ccUL, 0xe0000000UL, 0x3fe2fc15UL, 0x855a7390UL,
+  0xbe506438UL, 0x40000000UL, 0x3fe2f00bUL, 0xa2898287UL, 0x3e3d22a2UL,
+  0xe0000000UL, 0x3fe2e403UL, 0x8b56f66fUL, 0xbe5aa5fdUL, 0x80000000UL,
+  0x3fe2d7ffUL, 0x52db119aUL, 0x3e3a2e3dUL, 0x60000000UL, 0x3fe2cbfeUL,
+  0xe2ddd4c0UL, 0xbe586469UL, 0x40000000UL, 0x3fe2c000UL, 0x6b01bf10UL,
+  0x3e352b9dUL, 0x40000000UL, 0x3fe2b405UL, 0xb07a1cdfUL, 0x3e5c5cdaUL,
+  0x80000000UL, 0x3fe2a80dUL, 0xc7b5f868UL, 0xbe5668b3UL, 0xc0000000UL,
+  0x3fe29c18UL, 0x185edf62UL, 0xbe563d66UL, 0x00000000UL, 0x3fe29027UL,
+  0xf729e1ccUL, 0x3e59a9a0UL, 0x80000000UL, 0x3fe28438UL, 0x6433c727UL,
+  0xbe43cc89UL, 0x00000000UL, 0x3fe2784dUL, 0x41782631UL, 0xbe30750cUL,
+  0xa0000000UL, 0x3fe26c64UL, 0x914911b7UL, 0xbe58290eUL, 0x40000000UL,
+  0x3fe2607fUL, 0x3dcc73e1UL, 0xbe4269cdUL, 0x00000000UL, 0x3fe2549dUL,
+  0x2751bf70UL, 0xbe5a6998UL, 0xc0000000UL, 0x3fe248bdUL, 0x4248b9fbUL,
+  0xbe4ddb00UL, 0x80000000UL, 0x3fe23ce1UL, 0xf35cf82fUL, 0x3e561b71UL,
+  0x60000000UL, 0x3fe23108UL, 0x8e481a2dUL, 0x3e518fb9UL, 0x60000000UL,
+  0x3fe22532UL, 0x5ab96edcUL, 0xbe5fafc5UL, 0x40000000UL, 0x3fe2195fUL,
+  0x80943911UL, 0xbe07f819UL, 0x40000000UL, 0x3fe20d8fUL, 0x386f2d6cUL,
+  0xbe54ba8bUL, 0x40000000UL, 0x3fe201c2UL, 0xf29664acUL, 0xbe5eb815UL,
+  0x20000000UL, 0x3fe1f5f8UL, 0x64f03390UL, 0x3e5e320cUL, 0x20000000UL,
+  0x3fe1ea31UL, 0x747ff696UL, 0x3e5ef0a5UL, 0x40000000UL, 0x3fe1de6dUL,
+  0x3e9ceb51UL, 0xbe5f8d27UL, 0x20000000UL, 0x3fe1d2acUL, 0x4ae0b55eUL,
+  0x3e5faa21UL, 0x20000000UL, 0x3fe1c6eeUL, 0x28569a5eUL, 0x3e598a4fUL,
+  0x20000000UL, 0x3fe1bb33UL, 0x54b33e07UL, 0x3e46130aUL, 0x20000000UL,
+  0x3fe1af7bUL, 0x024f1078UL, 0xbe4dbf93UL, 0x00000000UL, 0x3fe1a3c6UL,
+  0xb0783bfaUL, 0x3e419248UL, 0xe0000000UL, 0x3fe19813UL, 0x2f02b836UL,
+  0x3e4e02b7UL, 0xc0000000UL, 0x3fe18c64UL, 0x28dec9d4UL, 0x3e09064fUL,
+  0x80000000UL, 0x3fe180b8UL, 0x45cbf406UL, 0x3e5b1f46UL, 0x40000000UL,
+  0x3fe1750fUL, 0x03d9964cUL, 0x3e5b0a79UL, 0x00000000UL, 0x3fe16969UL,
+  0x8b5b882bUL, 0xbe238086UL, 0xa0000000UL, 0x3fe15dc5UL, 0x73bad6f8UL,
+  0xbdf1fca4UL, 0x20000000UL, 0x3fe15225UL, 0x5385769cUL, 0x3e5e8d76UL,
+  0xa0000000UL, 0x3fe14687UL, 0x1676dc6bUL, 0x3e571d08UL, 0x20000000UL,
+  0x3fe13aedUL, 0xa8c41c7fUL, 0xbe598a25UL, 0x60000000UL, 0x3fe12f55UL,
+  0xc4e1aaf0UL, 0x3e435277UL, 0xa0000000UL, 0x3fe123c0UL, 0x403638e1UL,
+  0xbe21aa7cUL, 0xc0000000UL, 0x3fe1182eUL, 0x557a092bUL, 0xbdd0116bUL,
+  0xc0000000UL, 0x3fe10c9fUL, 0x7d779f66UL, 0x3e4a61baUL, 0xc0000000UL,
+  0x3fe10113UL, 0x2b09c645UL, 0xbe5d586eUL, 0x20000000UL, 0x3fe0ea04UL,
+  0xea2cad46UL, 0x3e5aa97cUL, 0x20000000UL, 0x3fe0d300UL, 0x23190e54UL,
+  0x3e50f1a7UL, 0xa0000000UL, 0x3fe0bc07UL, 0x1379a5a6UL, 0xbe51619dUL,
+  0x60000000UL, 0x3fe0a51aUL, 0x926a3d4aUL, 0x3e5cf019UL, 0xa0000000UL,
+  0x3fe08e38UL, 0xa8c24358UL, 0x3e35241eUL, 0x20000000UL, 0x3fe07762UL,
+  0x24317e7aUL, 0x3e512cfaUL, 0x00000000UL, 0x3fe06097UL, 0xfd9cf274UL,
+  0xbe55bef3UL, 0x00000000UL, 0x3fe049d7UL, 0x3689b49dUL, 0xbe36d26dUL,
+  0x40000000UL, 0x3fe03322UL, 0xf72ef6c4UL, 0xbe54cd08UL, 0xa0000000UL,
+  0x3fe01c78UL, 0x23702d2dUL, 0xbe5900bfUL, 0x00000000UL, 0x3fe005daUL,
+  0x3f59c14cUL, 0x3e57d80bUL, 0x40000000UL, 0x3fdfde8dUL, 0xad67766dUL,
+  0xbe57fad4UL, 0x40000000UL, 0x3fdfb17cUL, 0x644f4ae7UL, 0x3e1ee43bUL,
+  0x40000000UL, 0x3fdf8481UL, 0x903234d2UL, 0x3e501a86UL, 0x40000000UL,
+  0x3fdf579cUL, 0xafe9e509UL, 0xbe267c3eUL, 0x00000000UL, 0x3fdf2acdUL,
+  0xb7dfda0bUL, 0xbe48149bUL, 0x40000000UL, 0x3fdefe13UL, 0x3b94305eUL,
+  0x3e5f4ea7UL, 0x80000000UL, 0x3fded16fUL, 0x5d95da61UL, 0xbe55c198UL,
+  0x00000000UL, 0x3fdea4e1UL, 0x406960c9UL, 0xbdd99a19UL, 0x00000000UL,
+  0x3fde7868UL, 0xd22f3539UL, 0x3e470c78UL, 0x80000000UL, 0x3fde4c04UL,
+  0x83eec535UL, 0xbe3e1232UL, 0x40000000UL, 0x3fde1fb6UL, 0x3dfbffcbUL,
+  0xbe4b7d71UL, 0x40000000UL, 0x3fddf37dUL, 0x7e1be4e0UL, 0xbe5b8f8fUL,
+  0x40000000UL, 0x3fddc759UL, 0x46dae887UL, 0xbe350458UL, 0x80000000UL,
+  0x3fdd9b4aUL, 0xed6ecc49UL, 0xbe5f0045UL, 0x80000000UL, 0x3fdd6f50UL,
+  0x2e9e883cUL, 0x3e2915daUL, 0x80000000UL, 0x3fdd436bUL, 0xf0bccb32UL,
+  0x3e4a68c9UL, 0x80000000UL, 0x3fdd179bUL, 0x9bbfc779UL, 0xbe54a26aUL,
+  0x00000000UL, 0x3fdcebe0UL, 0x7cea33abUL, 0x3e43c6b7UL, 0x40000000UL,
+  0x3fdcc039UL, 0xe740fd06UL, 0x3e5526c2UL, 0x40000000UL, 0x3fdc94a7UL,
+  0x9eadeb1aUL, 0xbe396d8dUL, 0xc0000000UL, 0x3fdc6929UL, 0xf0a8f95aUL,
+  0xbe5c0ab2UL, 0x80000000UL, 0x3fdc3dc0UL, 0x6ee2693bUL, 0x3e0992e6UL,
+  0xc0000000UL, 0x3fdc126bUL, 0x5ac6b581UL, 0xbe2834b6UL, 0x40000000UL,
+  0x3fdbe72bUL, 0x8cc226ffUL, 0x3e3596a6UL, 0x00000000UL, 0x3fdbbbffUL,
+  0xf92a74bbUL, 0x3e3c5813UL, 0x00000000UL, 0x3fdb90e7UL, 0x479664c0UL,
+  0xbe50d644UL, 0x00000000UL, 0x3fdb65e3UL, 0x5004975bUL, 0xbe55258fUL,
+  0x00000000UL, 0x3fdb3af3UL, 0xe4b23194UL, 0xbe588407UL, 0xc0000000UL,
+  0x3fdb1016UL, 0xe65d4d0aUL, 0x3e527c26UL, 0x80000000UL, 0x3fdae54eUL,
+  0x814fddd6UL, 0x3e5962a2UL, 0x40000000UL, 0x3fdaba9aUL, 0xe19d0913UL,
+  0xbe562f4eUL, 0x80000000UL, 0x3fda8ff9UL, 0x43cfd006UL, 0xbe4cfdebUL,
+  0x40000000UL, 0x3fda656cUL, 0x686f0a4eUL, 0x3e5e47a8UL, 0xc0000000UL,
+  0x3fda3af2UL, 0x7200d410UL, 0x3e5e1199UL, 0xc0000000UL, 0x3fda108cUL,
+  0xabd2266eUL, 0x3e5ee4d1UL, 0x40000000UL, 0x3fd9e63aUL, 0x396f8f2cUL,
+  0x3e4dbffbUL, 0x00000000UL, 0x3fd9bbfbUL, 0xe32b25ddUL, 0x3e5c3a54UL,
+  0x40000000UL, 0x3fd991cfUL, 0x431e4035UL, 0xbe457925UL, 0x80000000UL,
+  0x3fd967b6UL, 0x7bed3dd3UL, 0x3e40c61dUL, 0x00000000UL, 0x3fd93db1UL,
+  0xd7449365UL, 0x3e306419UL, 0x80000000UL, 0x3fd913beUL, 0x1746e791UL,
+  0x3e56fcfcUL, 0x40000000UL, 0x3fd8e9dfUL, 0xf3a9028bUL, 0xbe5041b9UL,
+  0xc0000000UL, 0x3fd8c012UL, 0x56840c50UL, 0xbe26e20aUL, 0x40000000UL,
+  0x3fd89659UL, 0x19763102UL, 0xbe51f466UL, 0x80000000UL, 0x3fd86cb2UL,
+  0x7032de7cUL, 0xbe4d298aUL, 0x80000000UL, 0x3fd8431eUL, 0xdeb39fabUL,
+  0xbe4361ebUL, 0x40000000UL, 0x3fd8199dUL, 0x5d01cbe0UL, 0xbe5425b3UL,
+  0x80000000UL, 0x3fd7f02eUL, 0x3ce99aa9UL, 0x3e146fa8UL, 0x80000000UL,
+  0x3fd7c6d2UL, 0xd1a262b9UL, 0xbe5a1a69UL, 0xc0000000UL, 0x3fd79d88UL,
+  0x8606c236UL, 0x3e423a08UL, 0x80000000UL, 0x3fd77451UL, 0x8fd1e1b7UL,
+  0x3e5a6a63UL, 0xc0000000UL, 0x3fd74b2cUL, 0xe491456aUL, 0x3e42c1caUL,
+  0x40000000UL, 0x3fd7221aUL, 0x4499a6d7UL, 0x3e36a69aUL, 0x00000000UL,
+  0x3fd6f91aUL, 0x5237df94UL, 0xbe0f8f02UL, 0x00000000UL, 0x3fd6d02cUL,
+  0xb6482c6eUL, 0xbe5abcf7UL, 0x00000000UL, 0x3fd6a750UL, 0x1919fd61UL,
+  0xbe57ade2UL, 0x00000000UL, 0x3fd67e86UL, 0xaa7a994dUL, 0xbe3f3fbdUL,
+  0x00000000UL, 0x3fd655ceUL, 0x67db014cUL, 0x3e33c550UL, 0x00000000UL,
+  0x3fd62d28UL, 0xa82856b7UL, 0xbe1409d1UL, 0xc0000000UL, 0x3fd60493UL,
+  0x1e6a300dUL, 0x3e55d899UL, 0x80000000UL, 0x3fd5dc11UL, 0x1222bd5cUL,
+  0xbe35bfc0UL, 0xc0000000UL, 0x3fd5b3a0UL, 0x6e8dc2d3UL, 0x3e5d4d79UL,
+  0x00000000UL, 0x3fd58b42UL, 0xe0e4ace6UL, 0xbe517303UL, 0x80000000UL,
+  0x3fd562f4UL, 0xb306e0a8UL, 0x3e5edf0fUL, 0xc0000000UL, 0x3fd53ab8UL,
+  0x6574bc54UL, 0x3e5ee859UL, 0x80000000UL, 0x3fd5128eUL, 0xea902207UL,
+  0x3e5f6188UL, 0xc0000000UL, 0x3fd4ea75UL, 0x9f911d79UL, 0x3e511735UL,
+  0x80000000UL, 0x3fd4c26eUL, 0xf9c77397UL, 0xbe5b1643UL, 0x40000000UL,
+  0x3fd49a78UL, 0x15fc9258UL, 0x3e479a37UL, 0x80000000UL, 0x3fd47293UL,
+  0xd5a04dd9UL, 0xbe426e56UL, 0xc0000000UL, 0x3fd44abfUL, 0xe04042f5UL,
+  0x3e56f7c6UL, 0x40000000UL, 0x3fd422fdUL, 0x1d8bf2c8UL, 0x3e5d8810UL,
+  0x00000000UL, 0x3fd3fb4cUL, 0x88a8ddeeUL, 0xbe311454UL, 0xc0000000UL,
+  0x3fd3d3abUL, 0x3e3b5e47UL, 0xbe5d1b72UL, 0x40000000UL, 0x3fd3ac1cUL,
+  0xc2ab5d59UL, 0x3e31b02bUL, 0xc0000000UL, 0x3fd3849dUL, 0xd4e34b9eUL,
+  0x3e51cb2fUL, 0x40000000UL, 0x3fd35d30UL, 0x177204fbUL, 0xbe2b8cd7UL,
+  0x80000000UL, 0x3fd335d3UL, 0xfcd38c82UL, 0xbe4356e1UL, 0x80000000UL,
+  0x3fd30e87UL, 0x64f54accUL, 0xbe4e6224UL, 0x00000000UL, 0x3fd2e74cUL,
+  0xaa7975d9UL, 0x3e5dc0feUL, 0x80000000UL, 0x3fd2c021UL, 0x516dab3fUL,
+  0xbe50ffa3UL, 0x40000000UL, 0x3fd29907UL, 0x2bfb7313UL, 0x3e5674a2UL,
+  0xc0000000UL, 0x3fd271fdUL, 0x0549fc99UL, 0x3e385d29UL, 0xc0000000UL,
+  0x3fd24b04UL, 0x55b63073UL, 0xbe500c6dUL, 0x00000000UL, 0x3fd2241cUL,
+  0x3f91953aUL, 0x3e389977UL, 0xc0000000UL, 0x3fd1fd43UL, 0xa1543f71UL,
+  0xbe3487abUL, 0xc0000000UL, 0x3fd1d67bUL, 0x4ec8867cUL, 0x3df6a2dcUL,
+  0x00000000UL, 0x3fd1afc4UL, 0x4328e3bbUL, 0x3e41d9c0UL, 0x80000000UL,
+  0x3fd1891cUL, 0x2e1cda84UL, 0x3e3bdd87UL, 0x40000000UL, 0x3fd16285UL,
+  0x4b5331aeUL, 0xbe53128eUL, 0x00000000UL, 0x3fd13bfeUL, 0xb9aec164UL,
+  0xbe52ac98UL, 0xc0000000UL, 0x3fd11586UL, 0xd91e1316UL, 0xbe350630UL,
+  0x80000000UL, 0x3fd0ef1fUL, 0x7cacc12cUL, 0x3e3f5219UL, 0x40000000UL,
+  0x3fd0c8c8UL, 0xbce277b7UL, 0x3e3d30c0UL, 0x00000000UL, 0x3fd0a281UL,
+  0x2a63447dUL, 0xbe541377UL, 0x80000000UL, 0x3fd07c49UL, 0xfac483b5UL,
+  0xbe5772ecUL, 0xc0000000UL, 0x3fd05621UL, 0x36b8a570UL, 0xbe4fd4bdUL,
+  0xc0000000UL, 0x3fd03009UL, 0xbae505f7UL, 0xbe450388UL, 0x80000000UL,
+  0x3fd00a01UL, 0x3e35aeadUL, 0xbe5430fcUL, 0x80000000UL, 0x3fcfc811UL,
+  0x707475acUL, 0x3e38806eUL, 0x80000000UL, 0x3fcf7c3fUL, 0xc91817fcUL,
+  0xbe40cceaUL, 0x80000000UL, 0x3fcf308cUL, 0xae05d5e9UL, 0xbe4919b8UL,
+  0x80000000UL, 0x3fcee4f8UL, 0xae6cc9e6UL, 0xbe530b94UL, 0x00000000UL,
+  0x3fce9983UL, 0x1efe3e8eUL, 0x3e57747eUL, 0x00000000UL, 0x3fce4e2dUL,
+  0xda78d9bfUL, 0xbe59a608UL, 0x00000000UL, 0x3fce02f5UL, 0x8abe2c2eUL,
+  0x3e4a35adUL, 0x00000000UL, 0x3fcdb7dcUL, 0x1495450dUL, 0xbe0872ccUL,
+  0x80000000UL, 0x3fcd6ce1UL, 0x86ee0ba0UL, 0xbe4f59a0UL, 0x00000000UL,
+  0x3fcd2205UL, 0xe81ca888UL, 0x3e5402c3UL, 0x00000000UL, 0x3fccd747UL,
+  0x3b4424b9UL, 0x3e5dfdc3UL, 0x80000000UL, 0x3fcc8ca7UL, 0xd305b56cUL,
+  0x3e202da6UL, 0x00000000UL, 0x3fcc4226UL, 0x399a6910UL, 0xbe482a1cUL,
+  0x80000000UL, 0x3fcbf7c2UL, 0x747f7938UL, 0xbe587372UL, 0x80000000UL,
+  0x3fcbad7cUL, 0x6fc246a0UL, 0x3e50d83dUL, 0x00000000UL, 0x3fcb6355UL,
+  0xee9e9be5UL, 0xbe5c35bdUL, 0x80000000UL, 0x3fcb194aUL, 0x8416c0bcUL,
+  0x3e546d4fUL, 0x00000000UL, 0x3fcacf5eUL, 0x49f7f08fUL, 0x3e56da76UL,
+  0x00000000UL, 0x3fca858fUL, 0x5dc30de2UL, 0x3e5f390cUL, 0x00000000UL,
+  0x3fca3bdeUL, 0x950583b6UL, 0xbe5e4169UL, 0x80000000UL, 0x3fc9f249UL,
+  0x33631553UL, 0x3e52aeb1UL, 0x00000000UL, 0x3fc9a8d3UL, 0xde8795a6UL,
+  0xbe59a504UL, 0x00000000UL, 0x3fc95f79UL, 0x076bf41eUL, 0x3e5122feUL,
+  0x80000000UL, 0x3fc9163cUL, 0x2914c8e7UL, 0x3e3dd064UL, 0x00000000UL,
+  0x3fc8cd1dUL, 0x3a30eca3UL, 0xbe21b4aaUL, 0x80000000UL, 0x3fc8841aUL,
+  0xb2a96650UL, 0xbe575444UL, 0x80000000UL, 0x3fc83b34UL, 0x2376c0cbUL,
+  0xbe2a74c7UL, 0x80000000UL, 0x3fc7f26bUL, 0xd8a0b653UL, 0xbe5181b6UL,
+  0x00000000UL, 0x3fc7a9bfUL, 0x32257882UL, 0xbe4a78b4UL, 0x00000000UL,
+  0x3fc7612fUL, 0x1eee8bd9UL, 0xbe1bfe9dUL, 0x80000000UL, 0x3fc718bbUL,
+  0x0c603cc4UL, 0x3e36fdc9UL, 0x80000000UL, 0x3fc6d064UL, 0x3728b8cfUL,
+  0xbe1e542eUL, 0x80000000UL, 0x3fc68829UL, 0xc79a4067UL, 0x3e5c380fUL,
+  0x00000000UL, 0x3fc6400bUL, 0xf69eac69UL, 0x3e550a84UL, 0x80000000UL,
+  0x3fc5f808UL, 0xb7a780a4UL, 0x3e5d9224UL, 0x80000000UL, 0x3fc5b022UL,
+  0xad9dfb1eUL, 0xbe55242fUL, 0x00000000UL, 0x3fc56858UL, 0x659b18beUL,
+  0xbe4bfda3UL, 0x80000000UL, 0x3fc520a9UL, 0x66ee3631UL, 0xbe57d769UL,
+  0x80000000UL, 0x3fc4d916UL, 0x1ec62819UL, 0x3e2427f7UL, 0x80000000UL,
+  0x3fc4919fUL, 0xdec25369UL, 0xbe435431UL, 0x00000000UL, 0x3fc44a44UL,
+  0xa8acfc4bUL, 0xbe3c62e8UL, 0x00000000UL, 0x3fc40304UL, 0xcf1d3eabUL,
+  0xbdfba29fUL, 0x80000000UL, 0x3fc3bbdfUL, 0x79aba3eaUL, 0xbdf1b7c8UL,
+  0x80000000UL, 0x3fc374d6UL, 0xb8d186daUL, 0xbe5130cfUL, 0x80000000UL,
+  0x3fc32de8UL, 0x9d74f152UL, 0x3e2285b6UL, 0x00000000UL, 0x3fc2e716UL,
+  0x50ae7ca9UL, 0xbe503920UL, 0x80000000UL, 0x3fc2a05eUL, 0x6caed92eUL,
+  0xbe533924UL, 0x00000000UL, 0x3fc259c2UL, 0x9cb5034eUL, 0xbe510e31UL,
+  0x80000000UL, 0x3fc21340UL, 0x12c4d378UL, 0xbe540b43UL, 0x80000000UL,
+  0x3fc1ccd9UL, 0xcc418706UL, 0x3e59887aUL, 0x00000000UL, 0x3fc1868eUL,
+  0x921f4106UL, 0xbe528e67UL, 0x80000000UL, 0x3fc1405cUL, 0x3969441eUL,
+  0x3e5d8051UL, 0x00000000UL, 0x3fc0fa46UL, 0xd941ef5bUL, 0x3e5f9079UL,
+  0x80000000UL, 0x3fc0b44aUL, 0x5a3e81b2UL, 0xbe567691UL, 0x00000000UL,
+  0x3fc06e69UL, 0x9d66afe7UL, 0xbe4d43fbUL, 0x00000000UL, 0x3fc028a2UL,
+  0x0a92a162UL, 0xbe52f394UL, 0x00000000UL, 0x3fbfc5eaUL, 0x209897e5UL,
+  0x3e529e37UL, 0x00000000UL, 0x3fbf3ac5UL, 0x8458bd7bUL, 0x3e582831UL,
+  0x00000000UL, 0x3fbeafd5UL, 0xb8d8b4b8UL, 0xbe486b4aUL, 0x00000000UL,
+  0x3fbe2518UL, 0xe0a3b7b6UL, 0x3e5bafd2UL, 0x00000000UL, 0x3fbd9a90UL,
+  0x2bf2710eUL, 0x3e383b2bUL, 0x00000000UL, 0x3fbd103cUL, 0x73eb6ab7UL,
+  0xbe56d78dUL, 0x00000000UL, 0x3fbc861bUL, 0x32ceaff5UL, 0xbe32dc5aUL,
+  0x00000000UL, 0x3fbbfc2eUL, 0xbee04cb7UL, 0xbe4a71a4UL, 0x00000000UL,
+  0x3fbb7274UL, 0x35ae9577UL, 0x3e38142fUL, 0x00000000UL, 0x3fbae8eeUL,
+  0xcbaddab4UL, 0xbe5490f0UL, 0x00000000UL, 0x3fba5f9aUL, 0x95ce1114UL,
+  0x3e597c71UL, 0x00000000UL, 0x3fb9d67aUL, 0x6d7c0f78UL, 0x3e3abc2dUL,
+  0x00000000UL, 0x3fb94d8dUL, 0x2841a782UL, 0xbe566cbcUL, 0x00000000UL,
+  0x3fb8c4d2UL, 0x6ed429c6UL, 0xbe3cfff9UL, 0x00000000UL, 0x3fb83c4aUL,
+  0xe4a49fbbUL, 0xbe552964UL, 0x00000000UL, 0x3fb7b3f4UL, 0x2193d81eUL,
+  0xbe42fa72UL, 0x00000000UL, 0x3fb72bd0UL, 0xdd70c122UL, 0x3e527a8cUL,
+  0x00000000UL, 0x3fb6a3dfUL, 0x03108a54UL, 0xbe450393UL, 0x00000000UL,
+  0x3fb61c1fUL, 0x30ff7954UL, 0x3e565840UL, 0x00000000UL, 0x3fb59492UL,
+  0xdedd460cUL, 0xbe5422b5UL, 0x00000000UL, 0x3fb50d36UL, 0x950f9f45UL,
+  0xbe5313f6UL, 0x00000000UL, 0x3fb4860bUL, 0x582cdcb1UL, 0x3e506d39UL,
+  0x00000000UL, 0x3fb3ff12UL, 0x7216d3a6UL, 0x3e4aa719UL, 0x00000000UL,
+  0x3fb3784aUL, 0x57a423fdUL, 0x3e5a9b9fUL, 0x00000000UL, 0x3fb2f1b4UL,
+  0x7a138b41UL, 0xbe50b418UL, 0x00000000UL, 0x3fb26b4eUL, 0x2fbfd7eaUL,
+  0x3e23a53eUL, 0x00000000UL, 0x3fb1e519UL, 0x18913ccbUL, 0x3e465fc1UL,
+  0x00000000UL, 0x3fb15f15UL, 0x7ea24e21UL, 0x3e042843UL, 0x00000000UL,
+  0x3fb0d941UL, 0x7c6d9c77UL, 0x3e59f61eUL, 0x00000000UL, 0x3fb0539eUL,
+  0x114efd44UL, 0x3e4ccab7UL, 0x00000000UL, 0x3faf9c56UL, 0x1777f657UL,
+  0x3e552f65UL, 0x00000000UL, 0x3fae91d2UL, 0xc317b86aUL, 0xbe5a61e0UL,
+  0x00000000UL, 0x3fad87acUL, 0xb7664efbUL, 0xbe41f64eUL, 0x00000000UL,
+  0x3fac7de6UL, 0x5d3d03a9UL, 0x3e0807a0UL, 0x00000000UL, 0x3fab7480UL,
+  0x743c38ebUL, 0xbe3726e1UL, 0x00000000UL, 0x3faa6b78UL, 0x06a253f1UL,
+  0x3e5ad636UL, 0x00000000UL, 0x3fa962d0UL, 0xa35f541bUL, 0x3e5a187aUL,
+  0x00000000UL, 0x3fa85a88UL, 0x4b86e446UL, 0xbe508150UL, 0x00000000UL,
+  0x3fa7529cUL, 0x2589cacfUL, 0x3e52938aUL, 0x00000000UL, 0x3fa64b10UL,
+  0xaf6b11f2UL, 0xbe3454cdUL, 0x00000000UL, 0x3fa543e2UL, 0x97506fefUL,
+  0xbe5fdec5UL, 0x00000000UL, 0x3fa43d10UL, 0xe75f7dd9UL, 0xbe388dd3UL,
+  0x00000000UL, 0x3fa3369cUL, 0xa4139632UL, 0xbdea5177UL, 0x00000000UL,
+  0x3fa23086UL, 0x352d6f1eUL, 0xbe565ad6UL, 0x00000000UL, 0x3fa12accUL,
+  0x77449eb7UL, 0xbe50d5c7UL, 0x00000000UL, 0x3fa0256eUL, 0x7478da78UL,
+  0x3e404724UL, 0x00000000UL, 0x3f9e40dcUL, 0xf59cef7fUL, 0xbe539d0aUL,
+  0x00000000UL, 0x3f9c3790UL, 0x1511d43cUL, 0x3e53c2c8UL, 0x00000000UL,
+  0x3f9a2f00UL, 0x9b8bff3cUL, 0xbe43b3e1UL, 0x00000000UL, 0x3f982724UL,
+  0xad1e22a5UL, 0x3e46f0bdUL, 0x00000000UL, 0x3f962000UL, 0x130d9356UL,
+  0x3e475ba0UL, 0x00000000UL, 0x3f941994UL, 0x8f86f883UL, 0xbe513d0bUL,
+  0x00000000UL, 0x3f9213dcUL, 0x914d0dc8UL, 0xbe534335UL, 0x00000000UL,
+  0x3f900ed8UL, 0x2d73e5e7UL, 0xbe22ba75UL, 0x00000000UL, 0x3f8c1510UL,
+  0xc5b7d70eUL, 0x3e599c5dUL, 0x00000000UL, 0x3f880de0UL, 0x8a27857eUL,
+  0xbe3d28c8UL, 0x00000000UL, 0x3f840810UL, 0xda767328UL, 0x3e531b3dUL,
+  0x00000000UL, 0x3f8003b0UL, 0x77bacaf3UL, 0xbe5f04e3UL, 0x00000000UL,
+  0x3f780150UL, 0xdf4b0720UL, 0x3e5a8bffUL, 0x00000000UL, 0x3f6ffc40UL,
+  0x34c48e71UL, 0xbe3fcd99UL, 0x00000000UL, 0x3f5ff6c0UL, 0x1ad218afUL,
+  0xbe4c78a7UL, 0x00000000UL, 0x00000000UL, 0x00000000UL, 0x80000000UL,
+  0x00000000UL, 0xfffff800UL, 0x00000000UL, 0xfffff800UL, 0x00000000UL,
+  0x3ff72000UL, 0x161bb241UL, 0xbf5dabe1UL, 0x6dc96112UL, 0xbf836578UL,
+  0xee241472UL, 0xbf9b0301UL, 0x9f95985aUL, 0xbfb528dbUL, 0xb3841d2aUL,
+  0xbfd619b6UL, 0x518775e3UL, 0x3f9004f2UL, 0xac8349bbUL, 0x3fa76c9bUL,
+  0x486ececcUL, 0x3fc4635eUL, 0x161bb241UL, 0xbf5dabe1UL, 0x9f95985aUL,
+  0xbfb528dbUL, 0xf8b5787dUL, 0x3ef2531eUL, 0x486ececbUL, 0x3fc4635eUL,
+  0x412055ccUL, 0xbdd61bb2UL, 0x00000000UL, 0xfffffff8UL, 0x00000000UL,
+  0xffffffffUL, 0x00000000UL, 0x3ff00000UL, 0x00000000UL, 0x3b700000UL,
+  0xfa5abcbfUL, 0x3ff00b1aUL, 0xa7609f71UL, 0xbc84f6b2UL, 0xa9fb3335UL,
+  0x3ff0163dUL, 0x9ab8cdb7UL, 0x3c9b6129UL, 0x143b0281UL, 0x3ff02168UL,
+  0x0fc54eb6UL, 0xbc82bf31UL, 0x3e778061UL, 0x3ff02c9aUL, 0x535b085dUL,
+  0xbc719083UL, 0x2e11bbccUL, 0x3ff037d4UL, 0xeeade11aUL, 0x3c656811UL,
+  0xe86e7f85UL, 0x3ff04315UL, 0x1977c96eUL, 0xbc90a31cUL, 0x72f654b1UL,
+  0x3ff04e5fUL, 0x3aa0d08cUL, 0x3c84c379UL, 0xd3158574UL, 0x3ff059b0UL,
+  0xa475b465UL, 0x3c8d73e2UL, 0x0e3c1f89UL, 0x3ff0650aUL, 0x5799c397UL,
+  0xbc95cb7bUL, 0x29ddf6deUL, 0x3ff0706bUL, 0xe2b13c27UL, 0xbc8c91dfUL,
+  0x2b72a836UL, 0x3ff07bd4UL, 0x54458700UL, 0x3c832334UL, 0x18759bc8UL,
+  0x3ff08745UL, 0x4bb284ffUL, 0x3c6186beUL, 0xf66607e0UL, 0x3ff092bdUL,
+  0x800a3fd1UL, 0xbc968063UL, 0xcac6f383UL, 0x3ff09e3eUL, 0x18316136UL,
+  0x3c914878UL, 0x9b1f3919UL, 0x3ff0a9c7UL, 0x873d1d38UL, 0x3c85d16cUL,
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+  0xbc9a08e9UL, 0x4a07897cUL, 0x3ffd072dUL, 0x43797a9cUL, 0xbc9cbc37UL,
+  0x2b08c968UL, 0x3ffd1b53UL, 0x219a36eeUL, 0x3c955636UL, 0x080d89f2UL,
+  0x3ffd2f87UL, 0x719d8578UL, 0xbc9d487bUL, 0xeacaa1d6UL, 0x3ffd43c8UL,
+  0xbf5a1614UL, 0x3c93db53UL, 0xdcfba487UL, 0x3ffd5818UL, 0xd75b3707UL,
+  0x3c82ed02UL, 0xe862e6d3UL, 0x3ffd6c76UL, 0x4a8165a0UL, 0x3c5fe87aUL,
+  0x16c98398UL, 0x3ffd80e3UL, 0x8beddfe8UL, 0xbc911ec1UL, 0x71ff6075UL,
+  0x3ffd955dUL, 0xbb9af6beUL, 0x3c9a052dUL, 0x03db3285UL, 0x3ffda9e6UL,
+  0x696db532UL, 0x3c9c2300UL, 0xd63a8315UL, 0x3ffdbe7cUL, 0x926b8be4UL,
+  0xbc9b76f1UL, 0xf301b460UL, 0x3ffdd321UL, 0x78f018c3UL, 0x3c92da57UL,
+  0x641c0658UL, 0x3ffde7d5UL, 0x8e79ba8fUL, 0xbc9ca552UL, 0x337b9b5fUL,
+  0x3ffdfc97UL, 0x4f184b5cUL, 0xbc91a5cdUL, 0x6b197d17UL, 0x3ffe1167UL,
+  0xbd5c7f44UL, 0xbc72b529UL, 0x14f5a129UL, 0x3ffe2646UL, 0x817a1496UL,
+  0xbc97b627UL, 0x3b16ee12UL, 0x3ffe3b33UL, 0x31fdc68bUL, 0xbc99f4a4UL,
+  0xe78b3ff6UL, 0x3ffe502eUL, 0x80a9cc8fUL, 0x3c839e89UL, 0x24676d76UL,
+  0x3ffe6539UL, 0x7522b735UL, 0xbc863ff8UL, 0xfbc74c83UL, 0x3ffe7a51UL,
+  0xca0c8de2UL, 0x3c92d522UL, 0x77cdb740UL, 0x3ffe8f79UL, 0x80b054b1UL,
+  0xbc910894UL, 0xa2a490daUL, 0x3ffea4afUL, 0x179c2893UL, 0xbc9e9c23UL,
+  0x867cca6eUL, 0x3ffeb9f4UL, 0x2293e4f2UL, 0x3c94832fUL, 0x2d8e67f1UL,
+  0x3ffecf48UL, 0xb411ad8cUL, 0xbc9c93f3UL, 0xa2188510UL, 0x3ffee4aaUL,
+  0xa487568dUL, 0x3c91c68dUL, 0xee615a27UL, 0x3ffefa1bUL, 0x86a4b6b0UL,
+  0x3c9dc7f4UL, 0x1cb6412aUL, 0x3fff0f9cUL, 0x65181d45UL, 0xbc932200UL,
+  0x376bba97UL, 0x3fff252bUL, 0xbf0d8e43UL, 0x3c93a1a5UL, 0x48dd7274UL,
+  0x3fff3ac9UL, 0x3ed837deUL, 0xbc795a5aUL, 0x5b6e4540UL, 0x3fff5076UL,
+  0x2dd8a18bUL, 0x3c99d3e1UL, 0x798844f8UL, 0x3fff6632UL, 0x3539343eUL,
+  0x3c9fa37bUL, 0xad9cbe14UL, 0x3fff7bfdUL, 0xd006350aUL, 0xbc9dbb12UL,
+  0x02243c89UL, 0x3fff91d8UL, 0xa779f689UL, 0xbc612ea8UL, 0x819e90d8UL,
+  0x3fffa7c1UL, 0xf3a5931eUL, 0x3c874853UL, 0x3692d514UL, 0x3fffbdbaUL,
+  0x15098eb6UL, 0xbc796773UL, 0x2b8f71f1UL, 0x3fffd3c2UL, 0x966579e7UL,
+  0x3c62eb74UL, 0x6b2a23d9UL, 0x3fffe9d9UL, 0x7442fde3UL, 0x3c74a603UL,
+  0xe78a6731UL, 0x3f55d87fUL, 0xd704a0c0UL, 0x3fac6b08UL, 0x6fba4e77UL,
+  0x3f83b2abUL, 0xff82c58fUL, 0x3fcebfbdUL, 0xfefa39efUL, 0x3fe62e42UL,
+  0x00000000UL, 0x00000000UL, 0xfefa39efUL, 0x3fe62e42UL, 0xfefa39efUL,
+  0xbfe62e42UL, 0xf8000000UL, 0xffffffffUL, 0xf8000000UL, 0xffffffffUL,
+  0x00000000UL, 0x80000000UL, 0x00000000UL, 0x00000000UL
+
+};
+
+//registers,
+// input: xmm0, xmm1
+// scratch: xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
+//          eax, edx, ecx, ebx
+
+// Code generated by Intel C compiler for LIBM library
+
+void MacroAssembler::fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register eax, Register ecx, Register edx, Register tmp) {
+  Label L_2TAG_PACKET_0_0_2, L_2TAG_PACKET_1_0_2, L_2TAG_PACKET_2_0_2, L_2TAG_PACKET_3_0_2;
+  Label L_2TAG_PACKET_4_0_2, L_2TAG_PACKET_5_0_2, L_2TAG_PACKET_6_0_2, L_2TAG_PACKET_7_0_2;
+  Label L_2TAG_PACKET_8_0_2, L_2TAG_PACKET_9_0_2, L_2TAG_PACKET_10_0_2, L_2TAG_PACKET_11_0_2;
+  Label L_2TAG_PACKET_12_0_2, L_2TAG_PACKET_13_0_2, L_2TAG_PACKET_14_0_2, L_2TAG_PACKET_15_0_2;
+  Label L_2TAG_PACKET_16_0_2, L_2TAG_PACKET_17_0_2, L_2TAG_PACKET_18_0_2, L_2TAG_PACKET_19_0_2;
+  Label L_2TAG_PACKET_20_0_2, L_2TAG_PACKET_21_0_2, L_2TAG_PACKET_22_0_2, L_2TAG_PACKET_23_0_2;
+  Label L_2TAG_PACKET_24_0_2, L_2TAG_PACKET_25_0_2, L_2TAG_PACKET_26_0_2, L_2TAG_PACKET_27_0_2;
+  Label L_2TAG_PACKET_28_0_2, L_2TAG_PACKET_29_0_2, L_2TAG_PACKET_30_0_2, L_2TAG_PACKET_31_0_2;
+  Label L_2TAG_PACKET_32_0_2, L_2TAG_PACKET_33_0_2, L_2TAG_PACKET_34_0_2, L_2TAG_PACKET_35_0_2;
+  Label L_2TAG_PACKET_36_0_2, L_2TAG_PACKET_37_0_2, L_2TAG_PACKET_38_0_2, L_2TAG_PACKET_39_0_2;
+  Label L_2TAG_PACKET_40_0_2, L_2TAG_PACKET_41_0_2, L_2TAG_PACKET_42_0_2, L_2TAG_PACKET_43_0_2;
+  Label L_2TAG_PACKET_44_0_2, L_2TAG_PACKET_45_0_2, L_2TAG_PACKET_46_0_2, L_2TAG_PACKET_47_0_2;
+  Label L_2TAG_PACKET_48_0_2, L_2TAG_PACKET_49_0_2, L_2TAG_PACKET_50_0_2, L_2TAG_PACKET_51_0_2;
+  Label L_2TAG_PACKET_52_0_2, L_2TAG_PACKET_53_0_2, L_2TAG_PACKET_54_0_2, L_2TAG_PACKET_55_0_2;
+  Label L_2TAG_PACKET_56_0_2, L_2TAG_PACKET_57_0_2, L_2TAG_PACKET_58_0_2, start;
+
+  assert_different_registers(tmp, eax, ecx, edx);
+
+  address static_const_table_pow = (address)_static_const_table_pow;
+
+  bind(start);
+  subl(rsp, 120);
+  movl(Address(rsp, 64), tmp);
+  lea(tmp, ExternalAddress(static_const_table_pow));
+  movsd(xmm0, Address(rsp, 128));
+  movsd(xmm1, Address(rsp, 136));
+  xorpd(xmm2, xmm2);
+  movl(eax, 16368);
+  pinsrw(xmm2, eax, 3);
+  movl(ecx, 1069088768);
+  movdl(xmm7, ecx);
+  movsd(Address(rsp, 16), xmm1);
+  xorpd(xmm1, xmm1);
+  movl(edx, 30704);
+  pinsrw(xmm1, edx, 3);
+  movsd(Address(rsp, 8), xmm0);
+  movdqu(xmm3, xmm0);
+  movl(edx, 8192);
+  movdl(xmm4, edx);
+  movdqu(xmm6, Address(tmp, 8240));
+  pextrw(eax, xmm0, 3);
+  por(xmm0, xmm2);
+  psllq(xmm0, 5);
+  movsd(xmm2, Address(tmp, 8256));
+  psrlq(xmm0, 34);
+  movl(edx, eax);
+  andl(edx, 32752);
+  subl(edx, 16368);
+  movl(ecx, edx);
+  sarl(edx, 31);
+  addl(ecx, edx);
+  xorl(ecx, edx);
+  rcpss(xmm0, xmm0);
+  psllq(xmm3, 12);
+  addl(ecx, 16);
+  bsrl(ecx, ecx);
+  psrlq(xmm3, 12);
+  movl(Address(rsp, 24), rsi);
+  subl(eax, 16);
+  cmpl(eax, 32736);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_0_0_2);
+  movl(rsi, 0);
+
+  bind(L_2TAG_PACKET_1_0_2);
+  mulss(xmm0, xmm7);
+  movl(edx, -1);
+  subl(ecx, 4);
+  shll(edx);
+  movdl(xmm5, edx);
+  por(xmm3, xmm1);
+  subl(eax, 16351);
+  cmpl(eax, 1);
+  jcc(Assembler::belowEqual, L_2TAG_PACKET_2_0_2);
+  paddd(xmm0, xmm4);
+  psllq(xmm5, 32);
+  movdl(edx, xmm0);
+  psllq(xmm0, 29);
+  pand(xmm5, xmm3);
+
+  bind(L_2TAG_PACKET_3_0_2);
+  pand(xmm0, xmm6);
+  subsd(xmm3, xmm5);
+  subl(eax, 1);
+  sarl(eax, 4);
+  cvtsi2sdl(xmm7, eax);
+  mulpd(xmm5, xmm0);
+
+  bind(L_2TAG_PACKET_4_0_2);
+  mulsd(xmm3, xmm0);
+  movdqu(xmm1, Address(tmp, 8272));
+  subsd(xmm5, xmm2);
+  movdqu(xmm4, Address(tmp, 8288));
+  movl(ecx, eax);
+  sarl(eax, 31);
+  addl(ecx, eax);
+  xorl(eax, ecx);
+  addl(eax, 1);
+  bsrl(eax, eax);
+  unpcklpd(xmm5, xmm3);
+  movdqu(xmm6, Address(tmp, 8304));
+  addsd(xmm3, xmm5);
+  andl(edx, 16760832);
+  shrl(edx, 10);
+  addpd(xmm5, Address(tmp, edx, Address::times_1, -3616));
+  movdqu(xmm0, Address(tmp, 8320));
+  pshufd(xmm2, xmm3, 68);
+  mulsd(xmm3, xmm3);
+  mulpd(xmm1, xmm2);
+  mulpd(xmm4, xmm2);
+  addsd(xmm5, xmm7);
+  mulsd(xmm2, xmm3);
+  addpd(xmm6, xmm1);
+  mulsd(xmm3, xmm3);
+  addpd(xmm0, xmm4);
+  movsd(xmm1, Address(rsp, 16));
+  movzwl(ecx, Address(rsp, 22));
+  pshufd(xmm7, xmm5, 238);
+  movsd(xmm4, Address(tmp, 8368));
+  mulpd(xmm6, xmm2);
+  pshufd(xmm3, xmm3, 68);
+  mulpd(xmm0, xmm2);
+  shll(eax, 4);
+  subl(eax, 15872);
+  andl(ecx, 32752);
+  addl(eax, ecx);
+  mulpd(xmm3, xmm6);
+  cmpl(eax, 624);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_5_0_2);
+  xorpd(xmm6, xmm6);
+  movl(edx, 17080);
+  pinsrw(xmm6, edx, 3);
+  movdqu(xmm2, xmm1);
+  pand(xmm4, xmm1);
+  subsd(xmm1, xmm4);
+  mulsd(xmm4, xmm5);
+  addsd(xmm0, xmm7);
+  mulsd(xmm1, xmm5);
+  movdqu(xmm7, xmm6);
+  addsd(xmm6, xmm4);
+  addpd(xmm3, xmm0);
+  movdl(edx, xmm6);
+  subsd(xmm6, xmm7);
+  pshufd(xmm0, xmm3, 238);
+  subsd(xmm4, xmm6);
+  addsd(xmm0, xmm3);
+  movl(ecx, edx);
+  andl(edx, 255);
+  addl(edx, edx);
+  movdqu(xmm5, Address(tmp, edx, Address::times_8, 8384));
+  addsd(xmm4, xmm1);
+  mulsd(xmm2, xmm0);
+  movdqu(xmm7, Address(tmp, 12480));
+  movdqu(xmm3, Address(tmp, 12496));
+  shll(ecx, 12);
+  xorl(ecx, rsi);
+  andl(ecx, -1048576);
+  movdl(xmm6, ecx);
+  addsd(xmm2, xmm4);
+  movsd(xmm1, Address(tmp, 12512));
+  pshufd(xmm0, xmm2, 68);
+  pshufd(xmm4, xmm2, 68);
+  mulpd(xmm0, xmm0);
+  movl(rsi, Address(rsp, 24));
+  mulpd(xmm7, xmm4);
+  pshufd(xmm6, xmm6, 17);
+  mulsd(xmm1, xmm2);
+  mulsd(xmm0, xmm0);
+  paddd(xmm5, xmm6);
+  addpd(xmm3, xmm7);
+  mulsd(xmm1, xmm5);
+  pshufd(xmm6, xmm5, 238);
+  mulpd(xmm0, xmm3);
+  addsd(xmm1, xmm6);
+  pshufd(xmm3, xmm0, 238);
+  mulsd(xmm0, xmm5);
+  mulsd(xmm3, xmm5);
+  addsd(xmm0, xmm1);
+  addsd(xmm0, xmm3);
+  addsd(xmm0, xmm5);
+  movsd(Address(rsp, 0), xmm0);
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_7_0_2);
+  movsd(xmm0, Address(rsp, 128));
+  movsd(xmm1, Address(rsp, 136));
+  mulsd(xmm0, xmm1);
+  movsd(Address(rsp, 0), xmm0);
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_0_0_2);
+  addl(eax, 16);
+  movl(edx, 32752);
+  andl(edx, eax);
+  cmpl(edx, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_8_0_2);
+  testl(eax, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_9_0_2);
+
+  bind(L_2TAG_PACKET_10_0_2);
+  movl(ecx, Address(rsp, 16));
+  xorl(edx, edx);
+  testl(ecx, ecx);
+  movl(ecx, 1);
+  cmovl(Assembler::notEqual, edx, ecx);
+  orl(edx, Address(rsp, 20));
+  cmpl(edx, 1072693248);
+  jcc(Assembler::equal, L_2TAG_PACKET_7_0_2);
+  movsd(xmm0, Address(rsp, 8));
+  movsd(xmm3, Address(rsp, 8));
+  movdl(edx, xmm3);
+  psrlq(xmm3, 32);
+  movdl(ecx, xmm3);
+  orl(edx, ecx);
+  cmpl(edx, 0);
+  jcc(Assembler::equal, L_2TAG_PACKET_11_0_2);
+  xorpd(xmm3, xmm3);
+  movl(eax, 18416);
+  pinsrw(xmm3, eax, 3);
+  mulsd(xmm0, xmm3);
+  xorpd(xmm2, xmm2);
+  movl(eax, 16368);
+  pinsrw(xmm2, eax, 3);
+  movdqu(xmm3, xmm0);
+  pextrw(eax, xmm0, 3);
+  por(xmm0, xmm2);
+  movl(ecx, 18416);
+  psllq(xmm0, 5);
+  movsd(xmm2, Address(tmp, 8256));
+  psrlq(xmm0, 34);
+  rcpss(xmm0, xmm0);
+  psllq(xmm3, 12);
+  movdqu(xmm6, Address(tmp, 8240));
+  psrlq(xmm3, 12);
+  mulss(xmm0, xmm7);
+  movl(edx, -1024);
+  movdl(xmm5, edx);
+  por(xmm3, xmm1);
+  paddd(xmm0, xmm4);
+  psllq(xmm5, 32);
+  movdl(edx, xmm0);
+  psllq(xmm0, 29);
+  pand(xmm5, xmm3);
+  movl(rsi, 0);
+  pand(xmm0, xmm6);
+  subsd(xmm3, xmm5);
+  andl(eax, 32752);
+  subl(eax, 18416);
+  sarl(eax, 4);
+  cvtsi2sdl(xmm7, eax);
+  mulpd(xmm5, xmm0);
+  jmp(L_2TAG_PACKET_4_0_2);
+
+  bind(L_2TAG_PACKET_12_0_2);
+  movl(ecx, Address(rsp, 16));
+  xorl(edx, edx);
+  testl(ecx, ecx);
+  movl(ecx, 1);
+  cmovl(Assembler::notEqual, edx, ecx);
+  orl(edx, Address(rsp, 20));
+  cmpl(edx, 1072693248);
+  jcc(Assembler::equal, L_2TAG_PACKET_7_0_2);
+  movsd(xmm0, Address(rsp, 8));
+  movsd(xmm3, Address(rsp, 8));
+  movdl(edx, xmm3);
+  psrlq(xmm3, 32);
+  movdl(ecx, xmm3);
+  orl(edx, ecx);
+  cmpl(edx, 0);
+  jcc(Assembler::equal, L_2TAG_PACKET_11_0_2);
+  xorpd(xmm3, xmm3);
+  movl(eax, 18416);
+  pinsrw(xmm3, eax, 3);
+  mulsd(xmm0, xmm3);
+  xorpd(xmm2, xmm2);
+  movl(eax, 16368);
+  pinsrw(xmm2, eax, 3);
+  movdqu(xmm3, xmm0);
+  pextrw(eax, xmm0, 3);
+  por(xmm0, xmm2);
+  movl(ecx, 18416);
+  psllq(xmm0, 5);
+  movsd(xmm2, Address(tmp, 8256));
+  psrlq(xmm0, 34);
+  rcpss(xmm0, xmm0);
+  psllq(xmm3, 12);
+  movdqu(xmm6, Address(tmp, 8240));
+  psrlq(xmm3, 12);
+  mulss(xmm0, xmm7);
+  movl(edx, -1024);
+  movdl(xmm5, edx);
+  por(xmm3, xmm1);
+  paddd(xmm0, xmm4);
+  psllq(xmm5, 32);
+  movdl(edx, xmm0);
+  psllq(xmm0, 29);
+  pand(xmm5, xmm3);
+  movl(rsi, INT_MIN);
+  pand(xmm0, xmm6);
+  subsd(xmm3, xmm5);
+  andl(eax, 32752);
+  subl(eax, 18416);
+  sarl(eax, 4);
+  cvtsi2sdl(xmm7, eax);
+  mulpd(xmm5, xmm0);
+  jmp(L_2TAG_PACKET_4_0_2);
+
+  bind(L_2TAG_PACKET_5_0_2);
+  cmpl(eax, 0);
+  jcc(Assembler::less, L_2TAG_PACKET_13_0_2);
+  cmpl(eax, 752);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_14_0_2);
+
+  bind(L_2TAG_PACKET_15_0_2);
+  addsd(xmm0, xmm7);
+  movsd(xmm2, Address(tmp, 12544));
+  addpd(xmm3, xmm0);
+  xorpd(xmm6, xmm6);
+  movl(eax, 17080);
+  pinsrw(xmm6, eax, 3);
+  pshufd(xmm0, xmm3, 238);
+  addsd(xmm0, xmm3);
+  movdqu(xmm3, xmm5);
+  addsd(xmm5, xmm0);
+  movdqu(xmm4, xmm2);
+  subsd(xmm3, xmm5);
+  movdqu(xmm7, xmm5);
+  pand(xmm5, xmm2);
+  movdqu(xmm2, xmm1);
+  pand(xmm4, xmm1);
+  subsd(xmm7, xmm5);
+  addsd(xmm0, xmm3);
+  subsd(xmm1, xmm4);
+  mulsd(xmm4, xmm5);
+  addsd(xmm0, xmm7);
+  mulsd(xmm2, xmm0);
+  movdqu(xmm7, xmm6);
+  mulsd(xmm1, xmm5);
+  addsd(xmm6, xmm4);
+  movdl(eax, xmm6);
+  subsd(xmm6, xmm7);
+  addsd(xmm2, xmm1);
+  movdqu(xmm7, Address(tmp, 12480));
+  movdqu(xmm3, Address(tmp, 12496));
+  subsd(xmm4, xmm6);
+  pextrw(edx, xmm6, 3);
+  movl(ecx, eax);
+  andl(eax, 255);
+  addl(eax, eax);
+  movdqu(xmm5, Address(tmp, eax, Address::times_8, 8384));
+  addsd(xmm2, xmm4);
+  sarl(ecx, 8);
+  movl(eax, ecx);
+  sarl(ecx, 1);
+  subl(eax, ecx);
+  shll(ecx, 20);
+  xorl(ecx, rsi);
+  movdl(xmm6, ecx);
+  movsd(xmm1, Address(tmp, 12512));
+  andl(edx, 32767);
+  cmpl(edx, 16529);
+  jcc(Assembler::above, L_2TAG_PACKET_14_0_2);
+  pshufd(xmm0, xmm2, 68);
+  pshufd(xmm4, xmm2, 68);
+  mulpd(xmm0, xmm0);
+  mulpd(xmm7, xmm4);
+  pshufd(xmm6, xmm6, 17);
+  mulsd(xmm1, xmm2);
+  mulsd(xmm0, xmm0);
+  paddd(xmm5, xmm6);
+  addpd(xmm3, xmm7);
+  mulsd(xmm1, xmm5);
+  pshufd(xmm6, xmm5, 238);
+  mulpd(xmm0, xmm3);
+  addsd(xmm1, xmm6);
+  pshufd(xmm3, xmm0, 238);
+  mulsd(xmm0, xmm5);
+  mulsd(xmm3, xmm5);
+  shll(eax, 4);
+  xorpd(xmm4, xmm4);
+  addl(eax, 16368);
+  pinsrw(xmm4, eax, 3);
+  addsd(xmm0, xmm1);
+  movl(rsi, Address(rsp, 24));
+  addsd(xmm0, xmm3);
+  movdqu(xmm1, xmm0);
+  addsd(xmm0, xmm5);
+  mulsd(xmm0, xmm4);
+  pextrw(eax, xmm0, 3);
+  andl(eax, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_16_0_2);
+  cmpl(eax, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_17_0_2);
+
+  bind(L_2TAG_PACKET_18_0_2);
+  movsd(Address(rsp, 0), xmm0);
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_8_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movsd(xmm0, Address(rsp, 8));
+  movdqu(xmm2, xmm0);
+  movdl(eax, xmm2);
+  psrlq(xmm2, 20);
+  movdl(edx, xmm2);
+  orl(eax, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_19_0_2);
+  addsd(xmm0, xmm0);
+  movdl(eax, xmm1);
+  psrlq(xmm1, 32);
+  movdl(edx, xmm1);
+  movl(ecx, edx);
+  addl(edx, edx);
+  orl(eax, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_20_0_2);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_20_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  pinsrw(xmm0, eax, 3);
+  movl(edx, 29);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_22_0_2);
+  movsd(xmm0, Address(rsp, 16));
+  addpd(xmm0, xmm0);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_19_0_2);
+  movdl(eax, xmm1);
+  movdqu(xmm2, xmm1);
+  psrlq(xmm1, 32);
+  movdl(edx, xmm1);
+  movl(ecx, edx);
+  addl(edx, edx);
+  orl(eax, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_23_0_2);
+  pextrw(eax, xmm2, 3);
+  andl(eax, 32752);
+  cmpl(eax, 32752);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_24_0_2);
+  movdl(eax, xmm2);
+  psrlq(xmm2, 20);
+  movdl(edx, xmm2);
+  orl(eax, edx);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_22_0_2);
+
+  bind(L_2TAG_PACKET_24_0_2);
+  pextrw(eax, xmm0, 3);
+  testl(eax, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_25_0_2);
+  testl(ecx, INT_MIN);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_26_0_2);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_27_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movdl(eax, xmm1);
+  testl(eax, 1);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_28_0_2);
+  testl(eax, 2);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_29_0_2);
+  jmp(L_2TAG_PACKET_28_0_2);
+
+  bind(L_2TAG_PACKET_25_0_2);
+  shrl(ecx, 20);
+  andl(ecx, 2047);
+  cmpl(ecx, 1075);
+  jcc(Assembler::above, L_2TAG_PACKET_28_0_2);
+  jcc(Assembler::equal, L_2TAG_PACKET_30_0_2);
+  cmpl(ecx, 1074);
+  jcc(Assembler::above, L_2TAG_PACKET_27_0_2);
+  cmpl(ecx, 1023);
+  jcc(Assembler::below, L_2TAG_PACKET_28_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movl(eax, 17208);
+  xorpd(xmm3, xmm3);
+  pinsrw(xmm3, eax, 3);
+  movdqu(xmm4, xmm3);
+  addsd(xmm3, xmm1);
+  subsd(xmm4, xmm3);
+  addsd(xmm1, xmm4);
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32752);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_28_0_2);
+  movdl(eax, xmm3);
+  andl(eax, 1);
+  jcc(Assembler::equal, L_2TAG_PACKET_28_0_2);
+
+  bind(L_2TAG_PACKET_29_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32768);
+  jcc(Assembler::equal, L_2TAG_PACKET_18_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 32768);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_28_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_26_0_2);
+
+  bind(L_2TAG_PACKET_31_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 32752);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_30_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movdl(eax, xmm1);
+  andl(eax, 1);
+  jcc(Assembler::equal, L_2TAG_PACKET_28_0_2);
+  jmp(L_2TAG_PACKET_29_0_2);
+
+  bind(L_2TAG_PACKET_32_0_2);
+  movdl(eax, xmm1);
+  psrlq(xmm1, 20);
+  movdl(edx, xmm1);
+  orl(eax, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_33_0_2);
+  movsd(xmm0, Address(rsp, 16));
+  addsd(xmm0, xmm0);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_33_0_2);
+  movsd(xmm0, Address(rsp, 8));
+  pextrw(eax, xmm0, 3);
+  cmpl(eax, 49136);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_34_0_2);
+  movdl(ecx, xmm0);
+  psrlq(xmm0, 20);
+  movdl(edx, xmm0);
+  orl(ecx, edx);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_34_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 32760);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_34_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  andl(eax, 32752);
+  subl(eax, 16368);
+  pextrw(edx, xmm1, 3);
+  xorpd(xmm0, xmm0);
+  xorl(eax, edx);
+  andl(eax, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_18_0_2);
+  movl(ecx, 32752);
+  pinsrw(xmm0, ecx, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_35_0_2);
+  movdl(eax, xmm1);
+  cmpl(edx, 17184);
+  jcc(Assembler::above, L_2TAG_PACKET_36_0_2);
+  testl(eax, 1);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_37_0_2);
+  testl(eax, 2);
+  jcc(Assembler::equal, L_2TAG_PACKET_38_0_2);
+  jmp(L_2TAG_PACKET_39_0_2);
+
+  bind(L_2TAG_PACKET_36_0_2);
+  testl(eax, 1);
+  jcc(Assembler::equal, L_2TAG_PACKET_38_0_2);
+  jmp(L_2TAG_PACKET_39_0_2);
+
+  bind(L_2TAG_PACKET_9_0_2);
+  movsd(xmm2, Address(rsp, 8));
+  movdl(eax, xmm2);
+  psrlq(xmm2, 31);
+  movdl(ecx, xmm2);
+  orl(eax, ecx);
+  jcc(Assembler::equal, L_2TAG_PACKET_11_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  pextrw(edx, xmm1, 3);
+  movdl(eax, xmm1);
+  movdqu(xmm2, xmm1);
+  psrlq(xmm2, 32);
+  movdl(ecx, xmm2);
+  addl(ecx, ecx);
+  orl(ecx, eax);
+  jcc(Assembler::equal, L_2TAG_PACKET_40_0_2);
+  andl(edx, 32752);
+  cmpl(edx, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_32_0_2);
+  cmpl(edx, 17200);
+  jcc(Assembler::above, L_2TAG_PACKET_38_0_2);
+  cmpl(edx, 17184);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_35_0_2);
+  cmpl(edx, 16368);
+  jcc(Assembler::below, L_2TAG_PACKET_37_0_2);
+  movl(eax, 17208);
+  xorpd(xmm2, xmm2);
+  pinsrw(xmm2, eax, 3);
+  movdqu(xmm4, xmm2);
+  addsd(xmm2, xmm1);
+  subsd(xmm4, xmm2);
+  addsd(xmm1, xmm4);
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32767);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_37_0_2);
+  movdl(eax, xmm2);
+  andl(eax, 1);
+  jcc(Assembler::equal, L_2TAG_PACKET_38_0_2);
+
+  bind(L_2TAG_PACKET_39_0_2);
+  xorpd(xmm1, xmm1);
+  movl(edx, 30704);
+  pinsrw(xmm1, edx, 3);
+  movsd(xmm2, Address(tmp, 8256));
+  movsd(xmm4, Address(rsp, 8));
+  pextrw(eax, xmm4, 3);
+  movl(edx, 8192);
+  movdl(xmm4, edx);
+  andl(eax, 32767);
+  subl(eax, 16);
+  jcc(Assembler::less, L_2TAG_PACKET_12_0_2);
+  movl(edx, eax);
+  andl(edx, 32752);
+  subl(edx, 16368);
+  movl(ecx, edx);
+  sarl(edx, 31);
+  addl(ecx, edx);
+  xorl(ecx, edx);
+  addl(ecx, 16);
+  bsrl(ecx, ecx);
+  movl(rsi, INT_MIN);
+  jmp(L_2TAG_PACKET_1_0_2);
+
+  bind(L_2TAG_PACKET_37_0_2);
+  xorpd(xmm1, xmm1);
+  movl(eax, 32752);
+  pinsrw(xmm1, eax, 3);
+  xorpd(xmm0, xmm0);
+  mulsd(xmm0, xmm1);
+  movl(edx, 28);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_38_0_2);
+  xorpd(xmm1, xmm1);
+  movl(edx, 30704);
+  pinsrw(xmm1, edx, 3);
+  movsd(xmm2, Address(tmp, 8256));
+  movsd(xmm4, Address(rsp, 8));
+  pextrw(eax, xmm4, 3);
+  movl(edx, 8192);
+  movdl(xmm4, edx);
+  andl(eax, 32767);
+  subl(eax, 16);
+  jcc(Assembler::less, L_2TAG_PACKET_10_0_2);
+  movl(edx, eax);
+  andl(edx, 32752);
+  subl(edx, 16368);
+  movl(ecx, edx);
+  sarl(edx, 31);
+  addl(ecx, edx);
+  xorl(ecx, edx);
+  addl(ecx, 16);
+  bsrl(ecx, ecx);
+  movl(rsi, 0);
+  jmp(L_2TAG_PACKET_1_0_2);
+
+  bind(L_2TAG_PACKET_23_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_26_0_2);
+  xorpd(xmm0, xmm0);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_13_0_2);
+  addl(eax, 384);
+  cmpl(eax, 0);
+  jcc(Assembler::less, L_2TAG_PACKET_41_0_2);
+  mulsd(xmm5, xmm1);
+  addsd(xmm0, xmm7);
+  shrl(rsi, 31);
+  addpd(xmm3, xmm0);
+  pshufd(xmm0, xmm3, 238);
+  addsd(xmm3, xmm0);
+  movsd(xmm4, Address(tmp, rsi, Address::times_8, 12528));
+  mulsd(xmm1, xmm3);
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  shll(rsi, 15);
+  orl(eax, rsi);
+  pinsrw(xmm0, eax, 3);
+  addsd(xmm5, xmm1);
+  movl(rsi, Address(rsp, 24));
+  mulsd(xmm5, xmm4);
+  addsd(xmm0, xmm5);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_41_0_2);
+  movl(rsi, Address(rsp, 24));
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_40_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_42_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 16368);
+  pinsrw(xmm0, eax, 3);
+  movl(edx, 26);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_11_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movdqu(xmm2, xmm1);
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32752);
+  cmpl(eax, 32752);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_43_0_2);
+  movdl(eax, xmm2);
+  psrlq(xmm2, 20);
+  movdl(edx, xmm2);
+  orl(eax, edx);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_22_0_2);
+
+  bind(L_2TAG_PACKET_43_0_2);
+  movdl(eax, xmm1);
+  psrlq(xmm1, 32);
+  movdl(edx, xmm1);
+  movl(ecx, edx);
+  addl(edx, edx);
+  orl(eax, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_42_0_2);
+  shrl(edx, 21);
+  cmpl(edx, 1075);
+  jcc(Assembler::above, L_2TAG_PACKET_44_0_2);
+  jcc(Assembler::equal, L_2TAG_PACKET_45_0_2);
+  cmpl(edx, 1023);
+  jcc(Assembler::below, L_2TAG_PACKET_44_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movl(eax, 17208);
+  xorpd(xmm3, xmm3);
+  pinsrw(xmm3, eax, 3);
+  movdqu(xmm4, xmm3);
+  addsd(xmm3, xmm1);
+  subsd(xmm4, xmm3);
+  addsd(xmm1, xmm4);
+  pextrw(eax, xmm1, 3);
+  andl(eax, 32752);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_44_0_2);
+  movdl(eax, xmm3);
+  andl(eax, 1);
+  jcc(Assembler::equal, L_2TAG_PACKET_44_0_2);
+
+  bind(L_2TAG_PACKET_46_0_2);
+  movsd(xmm0, Address(rsp, 8));
+  testl(ecx, INT_MIN);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_47_0_2);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_45_0_2);
+  movsd(xmm1, Address(rsp, 16));
+  movdl(eax, xmm1);
+  testl(eax, 1);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_46_0_2);
+
+  bind(L_2TAG_PACKET_44_0_2);
+  testl(ecx, INT_MIN);
+  jcc(Assembler::equal, L_2TAG_PACKET_26_0_2);
+  xorpd(xmm0, xmm0);
+
+  bind(L_2TAG_PACKET_47_0_2);
+  movl(eax, 16368);
+  xorpd(xmm1, xmm1);
+  pinsrw(xmm1, eax, 3);
+  divsd(xmm1, xmm0);
+  movdqu(xmm0, xmm1);
+  movl(edx, 27);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_14_0_2);
+  movsd(xmm2, Address(rsp, 8));
+  movsd(xmm6, Address(rsp, 16));
+  pextrw(eax, xmm2, 3);
+  pextrw(edx, xmm6, 3);
+  movl(ecx, 32752);
+  andl(ecx, edx);
+  cmpl(ecx, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_48_0_2);
+  andl(eax, 32752);
+  subl(eax, 16368);
+  xorl(edx, eax);
+  testl(edx, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_49_0_2);
+
+  bind(L_2TAG_PACKET_50_0_2);
+  movl(eax, 32736);
+  pinsrw(xmm0, eax, 3);
+  shrl(rsi, 16);
+  orl(eax, rsi);
+  pinsrw(xmm1, eax, 3);
+  movl(rsi, Address(rsp, 24));
+  mulsd(xmm0, xmm1);
+
+  bind(L_2TAG_PACKET_17_0_2);
+  movl(edx, 24);
+
+  bind(L_2TAG_PACKET_21_0_2);
+  movsd(Address(rsp, 0), xmm0);
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_49_0_2);
+  movl(eax, 16);
+  pinsrw(xmm0, eax, 3);
+  mulsd(xmm0, xmm0);
+  testl(rsi, INT_MIN);
+  jcc(Assembler::equal, L_2TAG_PACKET_51_0_2);
+  movsd(xmm2, Address(tmp, 12560));
+  xorpd(xmm0, xmm2);
+
+  bind(L_2TAG_PACKET_51_0_2);
+  movl(rsi, Address(rsp, 24));
+  movl(edx, 25);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_16_0_2);
+  pextrw(ecx, xmm5, 3);
+  pextrw(edx, xmm4, 3);
+  movl(eax, -1);
+  andl(ecx, 32752);
+  subl(ecx, 16368);
+  andl(edx, 32752);
+  addl(edx, ecx);
+  movl(ecx, -31);
+  sarl(edx, 4);
+  subl(ecx, edx);
+  jcc(Assembler::lessEqual, L_2TAG_PACKET_52_0_2);
+  cmpl(ecx, 20);
+  jcc(Assembler::above, L_2TAG_PACKET_53_0_2);
+  shll(eax);
+
+  bind(L_2TAG_PACKET_52_0_2);
+  movdl(xmm0, eax);
+  psllq(xmm0, 32);
+  pand(xmm0, xmm5);
+  subsd(xmm5, xmm0);
+  addsd(xmm5, xmm1);
+  mulsd(xmm0, xmm4);
+  mulsd(xmm5, xmm4);
+  addsd(xmm0, xmm5);
+
+  bind(L_2TAG_PACKET_53_0_2);
+  movl(edx, 25);
+  jmp(L_2TAG_PACKET_21_0_2);
+
+  bind(L_2TAG_PACKET_2_0_2);
+  movzwl(ecx, Address(rsp, 22));
+  movl(edx, INT_MIN);
+  movdl(xmm1, edx);
+  xorpd(xmm7, xmm7);
+  paddd(xmm0, xmm4);
+  psllq(xmm5, 32);
+  movdl(edx, xmm0);
+  psllq(xmm0, 29);
+  paddq(xmm1, xmm3);
+  pand(xmm5, xmm1);
+  andl(ecx, 32752);
+  cmpl(ecx, 16560);
+  jcc(Assembler::below, L_2TAG_PACKET_3_0_2);
+  pand(xmm0, xmm6);
+  subsd(xmm3, xmm5);
+  addl(eax, 16351);
+  shrl(eax, 4);
+  subl(eax, 1022);
+  cvtsi2sdl(xmm7, eax);
+  mulpd(xmm5, xmm0);
+  movsd(xmm4, Address(tmp, 0));
+  mulsd(xmm3, xmm0);
+  movsd(xmm6, Address(tmp, 0));
+  subsd(xmm5, xmm2);
+  movsd(xmm1, Address(tmp, 8));
+  pshufd(xmm2, xmm3, 68);
+  unpcklpd(xmm5, xmm3);
+  addsd(xmm3, xmm5);
+  movsd(xmm0, Address(tmp, 8));
+  andl(edx, 16760832);
+  shrl(edx, 10);
+  addpd(xmm7, Address(tmp, edx, Address::times_1, -3616));
+  mulsd(xmm4, xmm5);
+  mulsd(xmm0, xmm5);
+  mulsd(xmm6, xmm2);
+  mulsd(xmm1, xmm2);
+  movdqu(xmm2, xmm5);
+  mulsd(xmm4, xmm5);
+  addsd(xmm5, xmm0);
+  movdqu(xmm0, xmm7);
+  addsd(xmm2, xmm3);
+  addsd(xmm7, xmm5);
+  mulsd(xmm6, xmm2);
+  subsd(xmm0, xmm7);
+  movdqu(xmm2, xmm7);
+  addsd(xmm7, xmm4);
+  addsd(xmm0, xmm5);
+  subsd(xmm2, xmm7);
+  addsd(xmm4, xmm2);
+  pshufd(xmm2, xmm5, 238);
+  movdqu(xmm5, xmm7);
+  addsd(xmm7, xmm2);
+  addsd(xmm4, xmm0);
+  movdqu(xmm0, Address(tmp, 8272));
+  subsd(xmm5, xmm7);
+  addsd(xmm6, xmm4);
+  movdqu(xmm4, xmm7);
+  addsd(xmm5, xmm2);
+  addsd(xmm7, xmm1);
+  movdqu(xmm2, Address(tmp, 8336));
+  subsd(xmm4, xmm7);
+  addsd(xmm6, xmm5);
+  addsd(xmm4, xmm1);
+  pshufd(xmm5, xmm7, 238);
+  movdqu(xmm1, xmm7);
+  addsd(xmm7, xmm5);
+  subsd(xmm1, xmm7);
+  addsd(xmm1, xmm5);
+  movdqu(xmm5, Address(tmp, 8352));
+  pshufd(xmm3, xmm3, 68);
+  addsd(xmm6, xmm4);
+  addsd(xmm6, xmm1);
+  movdqu(xmm1, Address(tmp, 8304));
+  mulpd(xmm0, xmm3);
+  mulpd(xmm2, xmm3);
+  pshufd(xmm4, xmm3, 68);
+  mulpd(xmm3, xmm3);
+  addpd(xmm0, xmm1);
+  addpd(xmm5, xmm2);
+  mulsd(xmm4, xmm3);
+  movsd(xmm2, Address(tmp, 16));
+  mulpd(xmm3, xmm3);
+  movsd(xmm1, Address(rsp, 16));
+  movzwl(ecx, Address(rsp, 22));
+  mulpd(xmm0, xmm4);
+  pextrw(eax, xmm7, 3);
+  mulpd(xmm5, xmm4);
+  mulpd(xmm0, xmm3);
+  movsd(xmm4, Address(tmp, 8376));
+  pand(xmm2, xmm7);
+  addsd(xmm5, xmm6);
+  subsd(xmm7, xmm2);
+  addpd(xmm5, xmm0);
+  andl(eax, 32752);
+  subl(eax, 16368);
+  andl(ecx, 32752);
+  cmpl(ecx, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_48_0_2);
+  addl(ecx, eax);
+  cmpl(ecx, 16576);
+  jcc(Assembler::aboveEqual, L_2TAG_PACKET_54_0_2);
+  pshufd(xmm0, xmm5, 238);
+  pand(xmm4, xmm1);
+  movdqu(xmm3, xmm1);
+  addsd(xmm5, xmm0);
+  subsd(xmm1, xmm4);
+  xorpd(xmm6, xmm6);
+  movl(edx, 17080);
+  pinsrw(xmm6, edx, 3);
+  addsd(xmm7, xmm5);
+  mulsd(xmm4, xmm2);
+  mulsd(xmm1, xmm2);
+  movdqu(xmm5, xmm6);
+  mulsd(xmm3, xmm7);
+  addsd(xmm6, xmm4);
+  addsd(xmm1, xmm3);
+  movdqu(xmm7, Address(tmp, 12480));
+  movdl(edx, xmm6);
+  subsd(xmm6, xmm5);
+  movdqu(xmm3, Address(tmp, 12496));
+  movsd(xmm2, Address(tmp, 12512));
+  subsd(xmm4, xmm6);
+  movl(ecx, edx);
+  andl(edx, 255);
+  addl(edx, edx);
+  movdqu(xmm5, Address(tmp, edx, Address::times_8, 8384));
+  addsd(xmm4, xmm1);
+  pextrw(edx, xmm6, 3);
+  shrl(ecx, 8);
+  movl(eax, ecx);
+  shrl(ecx, 1);
+  subl(eax, ecx);
+  shll(ecx, 20);
+  movdl(xmm6, ecx);
+  pshufd(xmm0, xmm4, 68);
+  pshufd(xmm1, xmm4, 68);
+  mulpd(xmm0, xmm0);
+  mulpd(xmm7, xmm1);
+  pshufd(xmm6, xmm6, 17);
+  mulsd(xmm2, xmm4);
+  andl(edx, 32767);
+  cmpl(edx, 16529);
+  jcc(Assembler::above, L_2TAG_PACKET_14_0_2);
+  mulsd(xmm0, xmm0);
+  paddd(xmm5, xmm6);
+  addpd(xmm3, xmm7);
+  mulsd(xmm2, xmm5);
+  pshufd(xmm6, xmm5, 238);
+  mulpd(xmm0, xmm3);
+  addsd(xmm2, xmm6);
+  pshufd(xmm3, xmm0, 238);
+  addl(eax, 1023);
+  shll(eax, 20);
+  orl(eax, rsi);
+  movdl(xmm4, eax);
+  mulsd(xmm0, xmm5);
+  mulsd(xmm3, xmm5);
+  addsd(xmm0, xmm2);
+  psllq(xmm4, 32);
+  addsd(xmm0, xmm3);
+  movdqu(xmm1, xmm0);
+  addsd(xmm0, xmm5);
+  movl(rsi, Address(rsp, 24));
+  mulsd(xmm0, xmm4);
+  pextrw(eax, xmm0, 3);
+  andl(eax, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_16_0_2);
+  cmpl(eax, 32752);
+  jcc(Assembler::equal, L_2TAG_PACKET_17_0_2);
+
+  bind(L_2TAG_PACKET_55_0_2);
+  movsd(Address(rsp, 0), xmm0);
+  fld_d(Address(rsp, 0));
+  jmp(L_2TAG_PACKET_6_0_2);
+
+  bind(L_2TAG_PACKET_48_0_2);
+  movl(rsi, Address(rsp, 24));
+
+  bind(L_2TAG_PACKET_56_0_2);
+  movsd(xmm0, Address(rsp, 8));
+  movsd(xmm1, Address(rsp, 16));
+  addsd(xmm1, xmm1);
+  xorpd(xmm2, xmm2);
+  movl(eax, 49136);
+  pinsrw(xmm2, eax, 3);
+  addsd(xmm2, xmm0);
+  pextrw(eax, xmm2, 3);
+  cmpl(eax, 0);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_57_0_2);
+  xorpd(xmm0, xmm0);
+  movl(eax, 32760);
+  pinsrw(xmm0, eax, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_57_0_2);
+  movdl(edx, xmm1);
+  movdqu(xmm3, xmm1);
+  psrlq(xmm3, 20);
+  movdl(ecx, xmm3);
+  orl(ecx, edx);
+  jcc(Assembler::equal, L_2TAG_PACKET_58_0_2);
+  addsd(xmm1, xmm1);
+  movdqu(xmm0, xmm1);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_58_0_2);
+  pextrw(eax, xmm0, 3);
+  andl(eax, 32752);
+  pextrw(edx, xmm1, 3);
+  xorpd(xmm0, xmm0);
+  subl(eax, 16368);
+  xorl(eax, edx);
+  testl(eax, 32768);
+  jcc(Assembler::notEqual, L_2TAG_PACKET_18_0_2);
+  movl(edx, 32752);
+  pinsrw(xmm0, edx, 3);
+  jmp(L_2TAG_PACKET_18_0_2);
+
+  bind(L_2TAG_PACKET_54_0_2);
+  pextrw(eax, xmm1, 3);
+  pextrw(ecx, xmm2, 3);
+  xorl(eax, ecx);
+  testl(eax, 32768);
+  jcc(Assembler::equal, L_2TAG_PACKET_50_0_2);
+  jmp(L_2TAG_PACKET_49_0_2);
+
+  bind(L_2TAG_PACKET_6_0_2);
+  movl(tmp, Address(rsp, 64));
+
+}
+
+/******************************************************************************/
+//                     ALGORITHM DESCRIPTION - SIN()
+//                     ---------------------
+//
+//     1. RANGE REDUCTION
+//
+//     We perform an initial range reduction from X to r with
+//
+//          X =~= N * pi/32 + r
+//
+//     so that |r| <= pi/64 + epsilon. We restrict inputs to those
+//     where |N| <= 932560. Beyond this, the range reduction is
+//     insufficiently accurate. For extremely small inputs,
+//     denormalization can occur internally, impacting performance.
+//     This means that the main path is actually only taken for
+//     2^-252 <= |X| < 90112.
+//
+//     To avoid branches, we perform the range reduction to full
+//     accuracy each time.
+//
+//          X - N * (P_1 + P_2 + P_3)
+//
+//     where P_1 and P_2 are 32-bit numbers (so multiplication by N
+//     is exact) and P_3 is a 53-bit number. Together, these
+//     approximate pi well enough for all cases in the restricted
+//     range.
+//
+//     The main reduction sequence is:
+//
+//             y = 32/pi * x
+//             N = integer(y)
+//     (computed by adding and subtracting off SHIFTER)
+//
+//             m_1 = N * P_1
+//             m_2 = N * P_2
+//             r_1 = x - m_1
+//             r = r_1 - m_2
+//     (this r can be used for most of the calculation)
+//
+//             c_1 = r_1 - r
+//             m_3 = N * P_3
+//             c_2 = c_1 - m_2
+//             c = c_2 - m_3
+//
+//     2. MAIN ALGORITHM
+//
+//     The algorithm uses a table lookup based on B = M * pi / 32
+//     where M = N mod 64. The stored values are:
+//       sigma             closest power of 2 to cos(B)
+//       C_hl              53-bit cos(B) - sigma
+//       S_hi + S_lo       2 * 53-bit sin(B)
+//
+//     The computation is organized as follows:
+//
+//          sin(B + r + c) = [sin(B) + sigma * r] +
+//                           r * (cos(B) - sigma) +
+//                           sin(B) * [cos(r + c) - 1] +
+//                           cos(B) * [sin(r + c) - r]
+//
+//     which is approximately:
+//
+//          [S_hi + sigma * r] +
+//          C_hl * r +
+//          S_lo + S_hi * [(cos(r) - 1) - r * c] +
+//          (C_hl + sigma) * [(sin(r) - r) + c]
+//
+//     and this is what is actually computed. We separate this sum
+//     into four parts:
+//
+//          hi + med + pols + corr
+//
+//     where
+//
+//          hi       = S_hi + sigma r
+//          med      = C_hl * r
+//          pols     = S_hi * (cos(r) - 1) + (C_hl + sigma) * (sin(r) - r)
+//          corr     = S_lo + c * ((C_hl + sigma) - S_hi * r)
+//
+//     3. POLYNOMIAL
+//
+//     The polynomial S_hi * (cos(r) - 1) + (C_hl + sigma) *
+//     (sin(r) - r) can be rearranged freely, since it is quite
+//     small, so we exploit parallelism to the fullest.
+//
+//          psc4       =   SC_4 * r_1
+//          msc4       =   psc4 * r
+//          r2         =   r * r
+//          msc2       =   SC_2 * r2
+//          r4         =   r2 * r2
+//          psc3       =   SC_3 + msc4
+//          psc1       =   SC_1 + msc2
+//          msc3       =   r4 * psc3
+//          sincospols =   psc1 + msc3
+//          pols       =   sincospols *
+//                         <S_hi * r^2 | (C_hl + sigma) * r^3>
+//
+//     4. CORRECTION TERM
+//
+//     This is where the "c" component of the range reduction is
+//     taken into account; recall that just "r" is used for most of
+//     the calculation.
+//
+//          -c   = m_3 - c_2
+//          -d   = S_hi * r - (C_hl + sigma)
+//          corr = -c * -d + S_lo
+//
+//     5. COMPENSATED SUMMATIONS
+//
+//     The two successive compensated summations add up the high
+//     and medium parts, leaving just the low parts to add up at
+//     the end.
+//
+//          rs        =  sigma * r
+//          res_int   =  S_hi + rs
+//          k_0       =  S_hi - res_int
+//          k_2       =  k_0 + rs
+//          med       =  C_hl * r
+//          res_hi    =  res_int + med
+//          k_1       =  res_int - res_hi
+//          k_3       =  k_1 + med
+//
+//     6. FINAL SUMMATION
+//
+//     We now add up all the small parts:
+//
+//          res_lo = pols(hi) + pols(lo) + corr + k_1 + k_3
+//
+//     Now the overall result is just:
+//
+//          res_hi + res_lo
+//
+//     7. SMALL ARGUMENTS
+//
+//     If |x| < SNN (SNN meaning the smallest normal number), we
+//     simply perform 0.1111111 cdots 1111 * x. For SNN <= |x|, we
+//     do 2^-55 * (2^55 * x - x).
+//
+// Special cases:
+//  sin(NaN) = quiet NaN, and raise invalid exception
+//  sin(INF) = NaN and raise invalid exception
+//  sin(+/-0) = +/-0
+//
+/******************************************************************************/
+
+ALIGNED_(8) juint _zero_none[] =
+{
+    0x00000000UL, 0x00000000UL, 0x00000000UL, 0xbff00000UL
+};
+
+ALIGNED_(4) juint __4onpi_d[] =
+{
+    0x6dc9c883UL, 0x3ff45f30UL
+};
+
+ALIGNED_(4) juint _TWO_32H[] =
+{
+    0x00000000UL, 0x41f80000UL
+};
+
+ALIGNED_(4) juint _pi04_3d[] =
+{
+    0x54442d00UL, 0x3fe921fbUL, 0x98cc5180UL, 0x3ce84698UL, 0xcbb5bf6cUL,
+    0xb9dfc8f8UL
+};
+
+ALIGNED_(4) juint _pi04_5d[] =
+{
+    0x54400000UL, 0x3fe921fbUL, 0x1a600000UL, 0x3dc0b461UL, 0x2e000000UL,
+    0x3b93198aUL, 0x25200000UL, 0x396b839aUL, 0x533e63a0UL, 0x37027044UL
+};
+
+ALIGNED_(4) juint _SCALE[] =
+{
+    0x00000000UL, 0x32600000UL
+};
+
+ALIGNED_(4) juint _zeros[] =
+{
+    0x00000000UL, 0x00000000UL, 0x00000000UL, 0x80000000UL
+};
+
+ALIGNED_(4) juint _pi04_2d[] =
+{
+    0x54400000UL, 0x3fe921fbUL, 0x1a626331UL, 0x3dc0b461UL
+};
+
+ALIGNED_(4) juint _TWO_12H[] =
+{
+    0x00000000UL, 0x40b80000UL
+};
+
+ALIGNED_(2) jushort __4onpi_31l[] =
+{
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x836e, 0xa2f9,
+    0x40d8, 0x0000, 0x0000, 0x0000, 0x2a50, 0x9c88, 0x40b7, 0x0000, 0x0000, 0x0000,
+    0xabe8, 0xfe13, 0x4099, 0x0000, 0x0000, 0x0000, 0x6ee0, 0xfa9a, 0x4079, 0x0000,
+    0x0000, 0x0000, 0x9580, 0xdb62, 0x4058, 0x0000, 0x0000, 0x0000, 0x1c82, 0xc9e2,
+    0x403d, 0x0000, 0x0000, 0x0000, 0xb1c0, 0xff28, 0x4019, 0x0000, 0x0000, 0x0000,
+    0xef14, 0xaf7a, 0x3ffe, 0x0000, 0x0000, 0x0000, 0x48dc, 0xc36e, 0x3fdf, 0x0000,
+    0x0000, 0x0000, 0x3740, 0xe909, 0x3fbe, 0x0000, 0x0000, 0x0000, 0x924a, 0xb801,
+    0x3fa2, 0x0000, 0x0000, 0x0000, 0x3a32, 0xdd41, 0x3f83, 0x0000, 0x0000, 0x0000,
+    0x8778, 0x873f, 0x3f62, 0x0000, 0x0000, 0x0000, 0x1298, 0xb1cb, 0x3f44, 0x0000,
+    0x0000, 0x0000, 0xa208, 0x9cfb, 0x3f26, 0x0000, 0x0000, 0x0000, 0xbaec, 0xd7d4,
+    0x3f06, 0x0000, 0x0000, 0x0000, 0xd338, 0x8909, 0x3ee7, 0x0000, 0x0000, 0x0000,
+    0x68b8, 0xe04d, 0x3ec7, 0x0000, 0x0000, 0x0000, 0x4e64, 0xdf90, 0x3eaa, 0x0000,
+    0x0000, 0x0000, 0xc1a8, 0xeb1c, 0x3e89, 0x0000, 0x0000, 0x0000, 0x2720, 0xce7d,
+    0x3e6a, 0x0000, 0x0000, 0x0000, 0x77b8, 0x8bf1, 0x3e4b, 0x0000, 0x0000, 0x0000,
+    0xec7e, 0xe4a0, 0x3e2e, 0x0000, 0x0000, 0x0000, 0xffbc, 0xf12f, 0x3e0f, 0x0000,
+    0x0000, 0x0000, 0xfdc0, 0xb301, 0x3deb, 0x0000, 0x0000, 0x0000, 0xc5ac, 0x9788,
+    0x3dd1, 0x0000, 0x0000, 0x0000, 0x47da, 0x829b, 0x3db2, 0x0000, 0x0000, 0x0000,
+    0xd9e4, 0xa6cf, 0x3d93, 0x0000, 0x0000, 0x0000, 0x36e8, 0xf961, 0x3d73, 0x0000,
+    0x0000, 0x0000, 0xf668, 0xf463, 0x3d54, 0x0000, 0x0000, 0x0000, 0x5168, 0xf2ff,
+    0x3d35, 0x0000, 0x0000, 0x0000, 0x758e, 0xea4f, 0x3d17, 0x0000, 0x0000, 0x0000,
+    0xf17a, 0xebe5, 0x3cf8, 0x0000, 0x0000, 0x0000, 0x9cfa, 0x9e83, 0x3cd9, 0x0000,
+    0x0000, 0x0000, 0xa4ba, 0xe294, 0x3cba, 0x0000, 0x0000, 0x0000, 0xd7ec, 0x9afe,
+    0x3c9a, 0x0000, 0x0000, 0x0000, 0xae80, 0x8fc6, 0x3c79, 0x0000, 0x0000, 0x0000,
+    0x3304, 0x8560, 0x3c5c, 0x0000, 0x0000, 0x0000, 0x6d70, 0xdf8f, 0x3c3b, 0x0000,
+    0x0000, 0x0000, 0x3ef0, 0xafc3, 0x3c1e, 0x0000, 0x0000, 0x0000, 0xd0d8, 0x826b,
+    0x3bfe, 0x0000, 0x0000, 0x0000, 0x1c80, 0xed4f, 0x3bdd, 0x0000, 0x0000, 0x0000,
+    0x730c, 0xb0af, 0x3bc1, 0x0000, 0x0000, 0x0000, 0x6660, 0xc219, 0x3ba2, 0x0000,
+    0x0000, 0x0000, 0x940c, 0xabe2, 0x3b83, 0x0000, 0x0000, 0x0000, 0xdffc, 0x8408,
+    0x3b64, 0x0000, 0x0000, 0x0000, 0x6b98, 0xc402, 0x3b45, 0x0000, 0x0000, 0x0000,
+    0x1818, 0x9cc4, 0x3b26, 0x0000, 0x0000, 0x0000, 0x5390, 0xaab6, 0x3b05, 0x0000,
+    0x0000, 0x0000, 0xb070, 0xd464, 0x3ae9, 0x0000, 0x0000, 0x0000, 0x231a, 0x9ef0,
+    0x3aca, 0x0000, 0x0000, 0x0000, 0x0670, 0xd1f1, 0x3aaa, 0x0000, 0x0000, 0x0000,
+    0x7738, 0xd9f3, 0x3a8a, 0x0000, 0x0000, 0x0000, 0xa834, 0x8092, 0x3a6c, 0x0000,
+    0x0000, 0x0000, 0xb45c, 0xce23, 0x3a4d, 0x0000, 0x0000, 0x0000, 0x36e8, 0xb0e5,
+    0x3a2d, 0x0000, 0x0000, 0x0000, 0xd156, 0xaf44, 0x3a10, 0x0000, 0x0000, 0x0000,
+    0x9f52, 0x8c82, 0x39f1, 0x0000, 0x0000, 0x0000, 0x829c, 0xff83, 0x39d1, 0x0000,
+    0x0000, 0x0000, 0x7d06, 0xefc6, 0x39b3, 0x0000, 0x0000, 0x0000, 0x93e0, 0xb0b7,
+    0x3992, 0x0000, 0x0000, 0x0000, 0xedde, 0xc193, 0x3975, 0x0000, 0x0000, 0x0000,
+    0xbbc0, 0xcf49, 0x3952, 0x0000, 0x0000, 0x0000, 0xbdf0, 0xd63c, 0x3937, 0x0000,
+    0x0000, 0x0000, 0x1f34, 0x9f3a, 0x3918, 0x0000, 0x0000, 0x0000, 0x3f8e, 0xe579,
+    0x38f9, 0x0000, 0x0000, 0x0000, 0x90c8, 0xc3f8, 0x38d9, 0x0000, 0x0000, 0x0000,
+    0x48c0, 0xf8f8, 0x38b7, 0x0000, 0x0000, 0x0000, 0xed56, 0xafa6, 0x389c, 0x0000,
+    0x0000, 0x0000, 0x8218, 0xb969, 0x387d, 0x0000, 0x0000, 0x0000, 0x1852, 0xec57,
+    0x385e, 0x0000, 0x0000, 0x0000, 0x670c, 0xd674, 0x383e, 0x0000, 0x0000, 0x0000,
+    0xad40, 0xc2c4, 0x3820, 0x0000, 0x0000, 0x0000, 0x2e80, 0xa696, 0x3801, 0x0000,
+    0x0000, 0x0000, 0xd800, 0xc467, 0x37dc, 0x0000, 0x0000, 0x0000, 0x3c72, 0xc5ae,
+    0x37c3, 0x0000, 0x0000, 0x0000, 0xb006, 0xac69, 0x37a4, 0x0000, 0x0000, 0x0000,
+    0x34a0, 0x8cdf, 0x3782, 0x0000, 0x0000, 0x0000, 0x9ed2, 0xd25e, 0x3766, 0x0000,
+    0x0000, 0x0000, 0x6fec, 0xaaaa, 0x3747, 0x0000, 0x0000, 0x0000, 0x6040, 0xfb5c,
+    0x3726, 0x0000, 0x0000, 0x0000, 0x764c, 0xa3fc, 0x3708, 0x0000, 0x0000, 0x0000,
+    0xb254, 0x954e, 0x36e9, 0x0000, 0x0000, 0x0000, 0x3e1c, 0xf5dc, 0x36ca, 0x0000,
+    0x0000, 0x0000, 0x7b06, 0xc635, 0x36ac, 0x0000, 0x0000, 0x0000, 0xa8ba, 0xd738,
+    0x368d, 0x0000, 0x0000, 0x0000, 0x06cc, 0xb24e, 0x366d, 0x0000, 0x0000, 0x0000,
+    0x7108, 0xac76, 0x364f, 0x0000, 0x0000, 0x0000, 0x2324, 0xa7cb, 0x3630, 0x0000,
+    0x0000, 0x0000, 0xac40, 0xef15, 0x360f, 0x0000, 0x0000, 0x0000, 0xae46, 0xd516,
+    0x35f2, 0x0000, 0x0000, 0x0000, 0x615e, 0xe003, 0x35d3, 0x0000, 0x0000, 0x0000,
+    0x0cf0, 0xefe7, 0x35b1, 0x0000, 0x0000, 0x0000, 0xfb50, 0xf98c, 0x3595, 0x0000,
+    0x0000, 0x0000, 0x0abc, 0xf333, 0x3575, 0x0000, 0x0000, 0x0000, 0xdd60, 0xca3f,
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+    0x15db, 0x0000, 0x0000, 0x0000, 0xad78, 0xd985, 0x15bc, 0x0000, 0x0000, 0x0000,
+    0xa46a, 0xae3f, 0x159d, 0x0000, 0x0000, 0x0000, 0x63a0, 0xd0da, 0x157c, 0x0000,
+    0x0000, 0x0000, 0x5e90, 0x817d, 0x155e, 0x0000, 0x0000, 0x0000, 0x1494, 0xb13f,
+    0x1540, 0x0000, 0x0000, 0x0000, 0x0090, 0x9c40, 0x1521, 0x0000, 0x0000, 0x0000,
+    0xdd70, 0xcc86, 0x1500, 0x0000, 0x0000, 0x0000, 0x64f8, 0xdb6f, 0x14e1, 0x0000,
+    0x0000, 0x0000, 0xe22c, 0xac17, 0x14c3, 0x0000, 0x0000, 0x0000, 0x60e0, 0xa9ad,
+    0x14a3, 0x0000, 0x0000, 0x0000, 0x4640, 0xd658, 0x1481, 0x0000, 0x0000, 0x0000,
+    0x6490, 0xa181, 0x1467, 0x0000, 0x0000, 0x0000, 0x1df4, 0xaaa2, 0x1447, 0x0000,
+    0x0000, 0x0000, 0xb94a, 0x8f61, 0x1429, 0x0000, 0x0000, 0x0000, 0x5198, 0x9d83,
+    0x1409, 0x0000, 0x0000, 0x0000, 0x0f7a, 0xa818, 0x13eb, 0x0000, 0x0000, 0x0000,
+    0xc45e, 0xc06c, 0x13cc, 0x0000, 0x0000, 0x0000, 0x4ec0, 0xfa29, 0x13a8, 0x0000,
+    0x0000, 0x0000, 0x6418, 0x8cad, 0x138c, 0x0000, 0x0000, 0x0000, 0xbcc8, 0xe7d1,
+    0x136f, 0x0000, 0x0000, 0x0000, 0xc934, 0xf9b0, 0x134f, 0x0000, 0x0000, 0x0000,
+    0x6ce0, 0x98df, 0x1331, 0x0000, 0x0000, 0x0000, 0x3516, 0xe5e9, 0x1312, 0x0000,
+    0x0000, 0x0000, 0xc6c0, 0xef8b, 0x12ef, 0x0000, 0x0000, 0x0000, 0xaf02, 0x913d,
+    0x12d4, 0x0000, 0x0000, 0x0000, 0xd230, 0xe1d5, 0x12b5, 0x0000, 0x0000, 0x0000,
+    0xfba8, 0xc232, 0x1295, 0x0000, 0x0000, 0x0000, 0x7ba4, 0xabeb, 0x1277, 0x0000,
+    0x0000, 0x0000, 0x6e5c, 0xc692, 0x1258, 0x0000, 0x0000, 0x0000, 0x76a2, 0x9756,
+    0x1239, 0x0000, 0x0000, 0x0000, 0xe180, 0xe423, 0x1214, 0x0000, 0x0000, 0x0000,
+    0x8c3c, 0x90f8, 0x11fb, 0x0000, 0x0000, 0x0000, 0x9f3c, 0x9fd2, 0x11dc, 0x0000,
+    0x0000, 0x0000, 0x53e0, 0xb73e, 0x11bd, 0x0000, 0x0000, 0x0000, 0x45be, 0x88d6,
+    0x119e, 0x0000, 0x0000, 0x0000, 0x111a, 0x8bc0, 0x117f, 0x0000, 0x0000, 0x0000,
+    0xe26a, 0xd7ff, 0x1160, 0x0000, 0x0000, 0x0000, 0xfb60, 0xdd8d, 0x113f, 0x0000,
+    0x0000, 0x0000, 0x9370, 0xc108, 0x1120, 0x0000, 0x0000, 0x0000, 0x9654, 0x8baf,
+    0x1103, 0x0000, 0x0000, 0x0000, 0xd6ec, 0xd6b9, 0x10e4, 0x0000, 0x0000, 0x0000,
+    0x23e4, 0xd7b7, 0x10c4, 0x0000, 0x0000, 0x0000, 0x1aa6, 0xa847, 0x10a6, 0x0000,
+    0x0000, 0x0000, 0xbee6, 0x9fef, 0x1087, 0x0000, 0x0000, 0x0000, 0x26d0, 0xa6eb,
+    0x1066, 0x0000, 0x0000, 0x0000, 0x5b86, 0xa880, 0x1049, 0x0000, 0x0000, 0x0000,
+    0x125c, 0xd971, 0x1029, 0x0000, 0x0000, 0x0000, 0x1f78, 0x9d18, 0x100a, 0x0000,
+    0x0000, 0x0000, 0x0e84, 0xb15b, 0x0feb, 0x0000, 0x0000, 0x0000, 0xd0c0, 0xc150,
+    0x0fcc, 0x0000, 0x0000, 0x0000, 0xa330, 0xc40c, 0x0fad, 0x0000, 0x0000, 0x0000,
+    0x5202, 0xfc2c, 0x0f8f, 0x0000, 0x0000, 0x0000, 0x3f7c, 0xecf5, 0x0f6f, 0x0000,
+    0x0000, 0x0000, 0xef44, 0xfdfd, 0x0f50, 0x0000, 0x0000, 0x0000, 0x3f6c, 0xab1b,
+    0x0f31, 0x0000, 0x0000, 0x0000, 0xf658, 0x89ec, 0x0f11, 0x0000, 0x0000, 0x0000,
+    0xbfc8, 0x9ba8, 0x0ef4, 0x0000, 0x0000, 0x0000, 0x3d40, 0xbe21, 0x0ed5, 0x0000,
+    0x0000, 0x0000, 0xbbc4, 0xc70d, 0x0eb6, 0x0000, 0x0000, 0x0000, 0x5158, 0xdb16,
+    0x0e96, 0x0000, 0x0000, 0x0000, 0xb5a8, 0xa8d8, 0x0e78, 0x0000, 0x0000, 0x0000,
+    0xcccc, 0xb40e, 0x0e58, 0x0000, 0x0000, 0x0000, 0x448c, 0xcb62, 0x0e3a, 0x0000,
+    0x0000, 0x0000, 0xf12a, 0x8aed, 0x0e1b, 0x0000, 0x0000, 0x0000, 0x79d0, 0xc59c,
+    0x0dfb, 0x0000, 0x0000, 0x0000, 0x06b4, 0xcdc9, 0x0ddd, 0x0000, 0x0000, 0x0000,
+    0xae70, 0xa979, 0x0dbe, 0x0000, 0x0000, 0x0000, 0x317c, 0xa8fb, 0x0d9e, 0x0000,
+    0x0000, 0x0000, 0x5fe0, 0x8a50, 0x0d7d, 0x0000, 0x0000, 0x0000, 0x70b6, 0xfdfa,
+    0x0d61, 0x0000, 0x0000, 0x0000, 0x1640, 0x9dc7, 0x0d41, 0x0000, 0x0000, 0x0000,
+    0x9a9c, 0xdc50, 0x0d23, 0x0000, 0x0000, 0x0000, 0x4fcc, 0x9a9b, 0x0d04, 0x0000,
+    0x0000, 0x0000, 0x7e48, 0x8f77, 0x0ce5, 0x0000, 0x0000, 0x0000, 0x84e4, 0xd4b9,
+    0x0cc6, 0x0000, 0x0000, 0x0000, 0x84e0, 0xbd10, 0x0ca6, 0x0000, 0x0000, 0x0000,
+    0x1b0a, 0xc8d9, 0x0c88, 0x0000, 0x0000, 0x0000, 0x6a48, 0xfc81, 0x0c68, 0x0000,
+    0x0000, 0x0000, 0x070a, 0xbef6, 0x0c4a, 0x0000, 0x0000, 0x0000, 0x8a70, 0xf096,
+    0x0c2b, 0x0000, 0x0000, 0x0000, 0xecc2, 0xc994, 0x0c0c, 0x0000, 0x0000, 0x0000,
+    0x1540, 0x9537, 0x0bea, 0x0000, 0x0000, 0x0000, 0x1b02, 0xab5b, 0x0bce, 0x0000,
+    0x0000, 0x0000, 0x5dc0, 0xb0c8, 0x0bad, 0x0000, 0x0000, 0x0000, 0xc928, 0xe034,
+    0x0b8f, 0x0000, 0x0000, 0x0000, 0x2d12, 0xb4b0, 0x0b71, 0x0000, 0x0000, 0x0000,
+    0x8fc2, 0xbb94, 0x0b52, 0x0000, 0x0000, 0x0000, 0xe236, 0xe22f, 0x0b33, 0x0000,
+    0x0000, 0x0000, 0xb97c, 0xbe9e, 0x0b13, 0x0000, 0x0000, 0x0000, 0xe1a6, 0xe16d,
+    0x0af5, 0x0000, 0x0000, 0x0000, 0xd330, 0xbaf0, 0x0ad6, 0x0000, 0x0000, 0x0000,
+    0xc0bc, 0xbbd0, 0x0ab7, 0x0000, 0x0000, 0x0000, 0x8e66, 0xdd9b, 0x0a98, 0x0000,
+    0x0000, 0x0000, 0xc95c, 0xf799, 0x0a79, 0x0000, 0x0000, 0x0000, 0xdac0, 0xbe4c,
+    0x0a55, 0x0000, 0x0000, 0x0000, 0xafc0, 0xc378, 0x0a37, 0x0000, 0x0000, 0x0000,
+    0xa880, 0xe341, 0x0a19, 0x0000, 0x0000, 0x0000, 0xc242, 0x81f6, 0x09fd, 0x0000,
+    0x0000, 0x0000, 0x7470, 0xc777, 0x09de, 0x0000, 0x0000, 0x0000, 0x62bc, 0xb684,
+    0x09be, 0x0000, 0x0000, 0x0000, 0x43ac, 0x8c58, 0x099f, 0x0000, 0x0000, 0x0000,
+    0xcc3c, 0xf9ac, 0x0981, 0x0000, 0x0000, 0x0000, 0x1526, 0xb670, 0x0962, 0x0000,
+    0x0000, 0x0000, 0xc9fe, 0xdf50, 0x0943, 0x0000, 0x0000, 0x0000, 0x6ae6, 0xc065,
+    0x0924, 0x0000, 0x0000, 0x0000, 0xb114, 0xcf29, 0x0905, 0x0000, 0x0000, 0x0000,
+    0xd388, 0x922a, 0x08e4, 0x0000, 0x0000, 0x0000, 0xcf54, 0xb926, 0x08c7, 0x0000,
+    0x0000, 0x0000, 0x3826, 0xe855, 0x08a8, 0x0000, 0x0000, 0x0000, 0xe7c8, 0x829b,
+    0x0888, 0x0000, 0x0000, 0x0000, 0x546c, 0xa903, 0x086a, 0x0000, 0x0000, 0x0000,
+    0x8768, 0x99cc, 0x0849, 0x0000, 0x0000, 0x0000, 0x00ac, 0xf529, 0x082b, 0x0000,
+    0x0000, 0x0000, 0x2658, 0x9f0b, 0x080c, 0x0000, 0x0000, 0x0000, 0xfe5c, 0x9e21,
+    0x07ee, 0x0000, 0x0000, 0x0000, 0x6da2, 0x9910, 0x07cf, 0x0000, 0x0000, 0x0000,
+    0x9220, 0xf9b3, 0x07b0, 0x0000, 0x0000, 0x0000, 0x3d90, 0xa541, 0x0791, 0x0000,
+    0x0000, 0x0000, 0x6e4c, 0xe7cc, 0x0771, 0x0000, 0x0000, 0x0000, 0xa8fa, 0xe80a,
+    0x0753, 0x0000, 0x0000, 0x0000, 0x4e14, 0xc3a7, 0x0734, 0x0000, 0x0000, 0x0000,
+    0xf7e0, 0xbad9, 0x0712, 0x0000, 0x0000, 0x0000, 0xfea0, 0xeff2, 0x06f5, 0x0000,
+    0x0000, 0x0000, 0xcef6, 0xbd48, 0x06d7, 0x0000, 0x0000, 0x0000, 0x7544, 0xf559,
+    0x06b7, 0x0000, 0x0000, 0x0000, 0x2388, 0xf655, 0x0698, 0x0000, 0x0000, 0x0000,
+    0xe900, 0xad56, 0x0676, 0x0000, 0x0000, 0x0000, 0x2cc0, 0x8437, 0x0659, 0x0000,
+    0x0000, 0x0000, 0x3068, 0xc544, 0x063b, 0x0000, 0x0000, 0x0000, 0xdc70, 0xe73c,
+    0x061b, 0x0000, 0x0000, 0x0000, 0xee50, 0x9d49, 0x05fc, 0x0000, 0x0000, 0x0000,
+    0x93d2, 0x81f6, 0x05df, 0x0000, 0x0000, 0x0000, 0x941c, 0xadff, 0x05bf, 0x0000,
+    0x0000, 0x0000, 0x2ce2, 0x8e45, 0x05a1, 0x0000, 0x0000, 0x0000, 0x4a60, 0x95fd,
+    0x0581, 0x0000, 0x0000, 0x0000, 0x79f8, 0xb83a, 0x0563, 0x0000, 0x0000, 0x0000,
+    0xcb58, 0xa1f5, 0x0543, 0x0000, 0x0000, 0x0000, 0x2a3a, 0xdc36, 0x0525, 0x0000,
+    0x0000, 0x0000, 0x14ee, 0x890e, 0x0506, 0x0000, 0x0000, 0x0000, 0x8f20, 0xc432,
+    0x04e3, 0x0000, 0x0000, 0x0000, 0x8440, 0xb21d, 0x04c6, 0x0000, 0x0000, 0x0000,
+    0x5430, 0xf698, 0x04a7, 0x0000, 0x0000, 0x0000, 0x04ae, 0x8b20, 0x048a, 0x0000,
+    0x0000, 0x0000, 0x04d0, 0xe872, 0x046b, 0x0000, 0x0000, 0x0000, 0xc78e, 0x8893,
+    0x044c, 0x0000, 0x0000, 0x0000, 0x0f78, 0x9895, 0x042b, 0x0000, 0x0000, 0x0000,
+    0x11d4, 0xdf2e, 0x040d, 0x0000, 0x0000, 0x0000, 0xe84c, 0x89d5, 0x03ef, 0x0000,
+    0x0000, 0x0000, 0xf7be, 0x8a67, 0x03d0, 0x0000, 0x0000, 0x0000, 0x95d0, 0xc906,
+    0x03b1, 0x0000, 0x0000, 0x0000, 0x64ce, 0xd96c, 0x0392, 0x0000, 0x0000, 0x0000,
+    0x97ba, 0xa16f, 0x0373, 0x0000, 0x0000, 0x0000, 0x463c, 0xc51a, 0x0354, 0x0000,
+    0x0000, 0x0000, 0xef0a, 0xe93e, 0x0335, 0x0000, 0x0000, 0x0000, 0x526a, 0xa466,
+    0x0316, 0x0000, 0x0000, 0x0000, 0x4140, 0xa94d, 0x02f5, 0x0000, 0x0000, 0x0000,
+    0xb4ec, 0xce68, 0x02d8, 0x0000, 0x0000, 0x0000, 0x4fa2, 0x8490, 0x02b9, 0x0000,
+    0x0000, 0x0000, 0x4e60, 0xca98, 0x0298, 0x0000, 0x0000, 0x0000, 0x08dc, 0xe09c,
+    0x027a, 0x0000, 0x0000, 0x0000, 0x2b90, 0xc7e3, 0x025c, 0x0000, 0x0000, 0x0000,
+    0x5a7c, 0xf8ef, 0x023c, 0x0000, 0x0000, 0x0000, 0x5022, 0x9d58, 0x021e, 0x0000,
+    0x0000, 0x0000, 0x553a, 0xe242, 0x01ff, 0x0000, 0x0000, 0x0000, 0x7e6e, 0xb54d,
+    0x01e0, 0x0000, 0x0000, 0x0000, 0xd2d4, 0xa88c, 0x01c1, 0x0000, 0x0000, 0x0000,
+    0x75b6, 0xfe6d, 0x01a2, 0x0000, 0x0000, 0x0000, 0x3bb2, 0xf04c, 0x0183, 0x0000,
+    0x0000, 0x0000, 0xc2d0, 0xc046, 0x0163, 0x0000, 0x0000, 0x0000, 0x250c, 0xf9d6,
+    0x0145, 0x0000, 0x0000, 0x0000, 0xb7b4, 0x8a0d, 0x0126, 0x0000, 0x0000, 0x0000,
+    0x1a72, 0xe4f5, 0x0107, 0x0000, 0x0000, 0x0000, 0x825c, 0xa9b8, 0x00e8, 0x0000,
+    0x0000, 0x0000, 0x6c90, 0xc9ad, 0x00c6, 0x0000, 0x0000, 0x0000, 0x4d00, 0xd1bb,
+    0x00aa, 0x0000, 0x0000, 0x0000, 0xa4a0, 0xee01, 0x0087, 0x0000, 0x0000, 0x0000,
+    0x89a8, 0xbe9f, 0x006b, 0x0000, 0x0000, 0x0000, 0x038e, 0xc80c, 0x004d, 0x0000,
+    0x0000, 0x0000, 0xfe26, 0x8384, 0x002e, 0x0000, 0x0000, 0x0000, 0xcd90, 0xca57,
+    0x000e, 0x0000
+};
+
+void MacroAssembler::libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx, Register esi, Register edi, Register ebp, Register esp) {
+  Label B1_1, B1_2, B1_3, B1_4, B1_5, B1_6, B1_7, B1_8, B1_9, B1_10, B1_11, B1_12;
+  Label B1_13, B1_14, B1_15;
+
+  assert_different_registers(ebx, eax, ecx, edx, esi, edi, ebp, esp);
+
+  address zero_none = (address)_zero_none;
+  address _4onpi_d = (address)__4onpi_d;
+  address TWO_32H = (address)_TWO_32H;
+  address pi04_3d = (address)_pi04_3d;
+  address pi04_5d = (address)_pi04_5d;
+  address SCALE = (address)_SCALE;
+  address zeros = (address)_zeros;
+  address pi04_2d = (address)_pi04_2d;
+  address TWO_12H = (address)_TWO_12H;
+  address _4onpi_31l = (address)__4onpi_31l;
+
+  bind(B1_1);
+  push(ebp);
+  movl(ebp, esp);
+  andl(esp, -16);
+  push(esi);
+  push(edi);
+  push(ebx);
+  subl(esp, 20);
+  movzwl(ebx, Address(ebp, 16));
+  andl(ebx, 32767);
+  movl(eax, Address(ebp, 20));
+  cmpl(ebx, 16413);
+  movl(esi, Address(ebp, 24));
+  movl(Address(esp, 4), eax);
+  jcc(Assembler::greaterEqual, B1_8);
+
+  bind(B1_2);
+  fld_x(Address(ebp, 8));
+  fld_d(ExternalAddress(_4onpi_d));    //0x6dc9c883UL, 0x3ff45f30UL
+  fmul(1);
+  fstp_x(Address(esp, 8));
+  movzwl(ecx, Address(esp, 16));
+  negl(ecx);
+  addl(ecx, 30);
+  movl(eax, Address(esp, 12));
+  shrl(eax);
+  cmpl(Address(esp, 4), 0);
+  jcc(Assembler::notEqual, B1_4);
+
+  bind(B1_3);
+  lea(ecx, Address(eax, 1));
+  andl(ecx, -2);
+  jmp(B1_5);
+
+  bind(B1_4);
+  movl(ecx, eax);
+  addl(eax, Address(esp, 4));
+  movl(edx, eax);
+  andl(edx, 1);
+  addl(ecx, edx);
+
+  bind(B1_5);
+  fld_d(ExternalAddress(TWO_32H));    //0x00000000UL, 0x41f80000UL
+  cmpl(ebx, 16400);
+  movl(Address(esp, 0), ecx);
+  fild_s(Address(esp, 0));
+  jcc(Assembler::greaterEqual, B1_7);
+
+  bind(B1_6);
+  fld_d(ExternalAddress(pi04_3d));    //0x54442d00UL, 0x3fe921fbUL
+  fmul(1);
+  fsubp(3);
+  fxch(1);
+  fmul(2);
+  fld_s(2);
+  fadd(1);
+  fsubrp(1);
+  fld_s(0);
+  fxch(1);
+  fsuba(3);
+  fld_d(ExternalAddress(8 + pi04_3d));    //0x98cc5180UL, 0x3ce84698UL
+  fmul(3);
+  fsuba(2);
+  fxch(1);
+  fsub(2);
+  fsubrp(1);
+  faddp(3);
+  fld_d(ExternalAddress(16 + pi04_3d));    //0xcbb5bf6cUL, 0xb9dfc8f8UL
+  fmulp(2);
+  fld_s(1);
+  fsubr(1);
+  fsuba(1);
+  fxch(2);
+  fsubp(1);
+  faddp(2);
+  fxch(1);
+  jmp(B1_15);
+
+  bind(B1_7);
+  fld_d(ExternalAddress(pi04_5d));    //0x54400000UL, 0x3fe921fbUL
+  fmul(1);
+  fsubp(3);
+  fxch(1);
+  fmul(2);
+  fld_s(2);
+  fadd(1);
+  fsubrp(1);
+  fld_s(0);
+  fxch(1);
+  fsuba(3);
+  fld_d(ExternalAddress(8 + pi04_5d));    //0x1a600000UL, 0x3dc0b461UL
+  fmul(3);
+  fsuba(2);
+  fxch(1);
+  fsub(2);
+  fsubrp(1);
+  faddp(3);
+  fld_d(ExternalAddress(16 + pi04_5d));    //0x2e000000UL, 0x3b93198aUL
+  fmul(2);
+  fld_s(0);
+  fsubr(2);
+  fsuba(2);
+  fxch(1);
+  fsubp(2);
+  fxch(1);
+  faddp(3);
+  fld_d(ExternalAddress(24 + pi04_5d));    //0x25200000UL, 0x396b839aUL
+  fmul(2);
+  fld_s(0);
+  fsubr(2);
+  fsuba(2);
+  fxch(1);
+  fsubp(2);
+  fxch(1);
+  faddp(3);
+  fld_d(ExternalAddress(32 + pi04_5d));    //0x533e63a0UL, 0x37027044UL
+  fmulp(2);
+  fld_s(1);
+  fsubr(1);
+  fsuba(1);
+  fxch(2);
+  fsubp(1);
+  faddp(2);
+  fxch(1);
+  jmp(B1_15);
+
+  bind(B1_8);
+  fld_x(Address(ebp, 8));
+  addl(ebx, -16417);
+  fmul_d(as_Address(ExternalAddress(SCALE)));    //0x00000000UL, 0x32600000UL
+  movl(eax, -2078209981);
+  imull(ebx);
+  addl(edx, ebx);
+  movl(ecx, ebx);
+  sarl(edx, 4);
+  sarl(ecx, 31);
+  subl(edx, ecx);
+  movl(eax, edx);
+  shll(eax, 5);
+  fstp_x(Address(ebp, 8));
+  fld_x(Address(ebp, 8));
+  subl(eax, edx);
+  movl(Address(ebp, 8), 0);
+  subl(ebx, eax);
+  fld_x(Address(ebp, 8));
+  cmpl(ebx, 17);
+  fsuba(1);
+  jcc(Assembler::less, B1_10);
+
+  bind(B1_9);
+  lea(eax, Address(noreg, edx, Address::times_8));
+  lea(ecx, Address(eax, edx, Address::times_4));
+  incl(edx);
+  fld_x(Address(_4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmul(2);
+  fld_x(Address(12 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmul(2);
+  fld_s(0);
+  fadd(2);
+  fsuba(2);
+  fxch(1);
+  faddp(2);
+  fld_s(1);
+  fadd(1);
+  fstp_x(Address(esp, 8));
+  andl(Address(esp, 8), -16777216);
+  fld_x(Address(esp, 8));
+  fsubp(1);
+  jmp(B1_11);
+
+  bind(B1_10);
+  fld_d(ExternalAddress(zeros));    //0x00000000UL, 0x00000000UL
+  fld_s(0);
+
+  bind(B1_11);
+  fld_s(0);
+  lea(eax, Address(noreg, edx, Address::times_8));
+  fld_s(3);
+  lea(edx, Address(eax, edx, Address::times_4));
+  fld_x(Address(_4onpi_31l, RelocationHolder::none).plus_disp(edx, Address::times_1));
+  fmul(6);
+  movl(Address(esp, 0), edx);
+  fadda(2);
+  fxch(2);
+  fsuba(3);
+  fxch(2);
+  faddp(3);
+  fxch(2);
+  faddp(3);
+  fld_x(Address(12 + _4onpi_31l, RelocationHolder::none).plus_disp(edx, Address::times_1));
+  fmula(2);
+  fld_s(2);
+  fadd(2);
+  fld_s(0);
+  fxch(1);
+  fsubra(3);
+  fxch(3);
+  fchs();
+  faddp(4);
+  fxch(3);
+  faddp(4);
+  fxch(2);
+  fadd(3);
+  fxch(2);
+  fmul(5);
+  fadda(2);
+  fld_s(4);
+  fld_x(Address(24 + _4onpi_31l, RelocationHolder::none).plus_disp(edx, Address::times_1));
+  fmula(1);
+  fxch(1);
+  fadda(4);
+  fxch(4);
+  fstp_x(Address(esp, 8));
+  movzwl(ebx, Address(esp, 16));
+  andl(ebx, 32767);
+  cmpl(ebx, 16415);
+  jcc(Assembler::greaterEqual, B1_13);
+
+  bind(B1_12);
+  negl(ebx);
+  addl(ebx, 30);
+  movl(ecx, ebx);
+  movl(eax, Address(esp, 12));
+  shrl(eax);
+  shll(eax);
+  movl(Address(esp, 12), eax);
+  movl(Address(esp, 8), 0);
+  shrl(eax);
+  jmp(B1_14);
+
+  bind(B1_13);
+  negl(ebx);
+  addl(ebx, 30);
+  movl(ecx, ebx);
+  movl(edx, Address(esp, 8));
+  shrl(edx);
+  shll(edx);
+  negl(ecx);
+  movl(eax, Address(esp, 12));
+  shll(eax);
+  movl(ecx, ebx);
+  movl(Address(esp, 8), edx);
+  shrl(edx);
+  orl(eax, edx);
+
+  bind(B1_14);
+  fld_x(Address(esp, 8));
+  addl(eax, Address(esp, 4));
+  fsubp(3);
+  fmul(6);
+  fld_s(4);
+  movl(edx, eax);
+  andl(edx, 1);
+  fadd(3);
+  movl(ecx, Address(esp, 0));
+  fsuba(3);
+  fxch(3);
+  faddp(5);
+  fld_s(1);
+  fxch(3);
+  fadd_d(Address(zero_none, RelocationHolder::none).plus_disp(edx, Address::times_8));
+  fadda(3);
+  fsub(3);
+  faddp(2);
+  fxch(1);
+  faddp(4);
+  fld_s(2);
+  fadd(2);
+  fsuba(2);
+  fxch(3);
+  faddp(2);
+  fxch(1);
+  faddp(3);
+  fld_s(0);
+  fadd(2);
+  fsuba(2);
+  fxch(1);
+  faddp(2);
+  fxch(1);
+  faddp(2);
+  fld_s(2);
+  fld_x(Address(36 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmula(1);
+  fld_s(1);
+  fadd(3);
+  fsuba(3);
+  fxch(2);
+  faddp(3);
+  fxch(2);
+  faddp(3);
+  fxch(1);
+  fmul(4);
+  fld_s(0);
+  fadd(2);
+  fsuba(2);
+  fxch(1);
+  faddp(2);
+  fxch(1);
+  faddp(2);
+  fld_s(2);
+  fld_x(Address(48 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmula(1);
+  fld_s(1);
+  fadd(3);
+  fsuba(3);
+  fxch(2);
+  faddp(3);
+  fxch(2);
+  faddp(3);
+  fld_s(3);
+  fxch(2);
+  fmul(5);
+  fld_x(Address(60 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmula(3);
+  fxch(3);
+  faddp(1);
+  fld_s(0);
+  fadd(2);
+  fsuba(2);
+  fxch(1);
+  faddp(2);
+  fxch(1);
+  faddp(3);
+  fld_s(3);
+  fxch(2);
+  fmul(5);
+  fld_x(Address(72 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmula(3);
+  fxch(3);
+  faddp(1);
+  fld_s(0);
+  fadd(2);
+  fsuba(2);
+  fxch(1);
+  faddp(2);
+  fxch(1);
+  faddp(3);
+  fxch(1);
+  fmulp(4);
+  fld_x(Address(84 + _4onpi_31l, RelocationHolder::none).plus_disp(ecx, Address::times_1));
+  fmulp(3);
+  fxch(2);
+  faddp(3);
+  fld_s(2);
+  fadd(2);
+  fld_d(ExternalAddress(TWO_32H));    //0x00000000UL, 0x41f80000UL
+  fmul(1);
+  fadda(1);
+  fsubp(1);
+  fsuba(2);
+  fxch(3);
+  faddp(2);
+  faddp(1);
+  fld_d(ExternalAddress(pi04_2d));    //0x54400000UL, 0x3fe921fbUL
+  fld_s(0);
+  fmul(2);
+  fxch(2);
+  fadd(3);
+  fxch(1);
+  fmulp(3);
+  fmul_d(as_Address(ExternalAddress(8 + pi04_2d)));    //0x1a626331UL, 0x3dc0b461UL
+  faddp(1);
+
+  bind(B1_15);
+  fld_d(ExternalAddress(TWO_12H));    //0x00000000UL, 0x40b80000UL
+  fld_s(2);
+  fadd(2);
+  fmula(1);
+  fstp_x(Address(esp, 8));
+  fld_x(Address(esp, 8));
+  fadd(1);
+  fsubrp(1);
+  fst_d(Address(esi, 0));
+  fsubp(2);
+  faddp(1);
+  fstp_d(Address(esi, 8));
+  addl(esp, 20);
+  pop(ebx);
+  pop(edi);
+  pop(esi);
+  movl(esp, ebp);
+  pop(ebp);
+  ret(0);
+}
+
+ALIGNED_(16) juint _L_2il0floatpacket_0[] =
+{
+    0xffffffffUL, 0x7fffffffUL, 0x00000000UL, 0x00000000UL
+};
+
+ALIGNED_(16) juint _Pi4Inv[] =
+{
+    0x6dc9c883UL, 0x3ff45f30UL
+};
+
+ALIGNED_(16) juint _Pi4x3[] =
+{
+    0x54443000UL, 0xbfe921fbUL, 0x3b39a000UL, 0x3d373dcbUL, 0xe0e68948UL,
+    0xba845c06UL
+};
+
+ALIGNED_(16) juint _Pi4x4[] =
+{
+    0x54400000UL, 0xbfe921fbUL, 0x1a600000UL, 0xbdc0b461UL, 0x2e000000UL,
+    0xbb93198aUL, 0x252049c1UL, 0xb96b839aUL
+};
+
+ALIGNED_(16) jushort _SP[] =
+{
+    0xaaab, 0xaaaa, 0xaaaa, 0xaaaa, 0xbffc, 0x0000, 0x8887, 0x8888, 0x8888, 0x8888,
+    0x3ff8, 0x0000, 0xc527, 0x0d00, 0x00d0, 0xd00d, 0xbff2, 0x0000, 0x45f6, 0xb616,
+    0x1d2a, 0xb8ef, 0x3fec, 0x0000, 0x825b, 0x3997, 0x2b3f, 0xd732, 0xbfe5, 0x0000,
+    0xbf33, 0x8bb4, 0x2fda, 0xb092, 0x3fde, 0x0000, 0x44a6, 0xed1a, 0x29ef, 0xd73e,
+    0xbfd6, 0x0000, 0x8610, 0x307f, 0x62a1, 0xc921, 0x3fce, 0x0000
+};
+
+ALIGNED_(16) jushort _CP[] =
+{
+    0x0000, 0x0000, 0x0000, 0x8000, 0xbffe, 0x0000, 0xaaa5, 0xaaaa, 0xaaaa, 0xaaaa,
+    0x3ffa, 0x0000, 0x9c2f, 0x0b60, 0x60b6, 0xb60b, 0xbff5, 0x0000, 0xf024, 0x0cac,
+    0x00d0, 0xd00d, 0x3fef, 0x0000, 0x03fe, 0x3f65, 0x7dbb, 0x93f2, 0xbfe9, 0x0000,
+    0xd84d, 0xadee, 0xc698, 0x8f76, 0x3fe2, 0x0000, 0xdaba, 0xfe79, 0xea36, 0xc9c9,
+    0xbfda, 0x0000, 0x3ac6, 0x0ba0, 0x07ce, 0xd585, 0x3fd2, 0x0000
+};
+
+ALIGNED_(16) juint _ones[] =
+{
+    0x00000000UL, 0x3ff00000UL, 0x00000000UL, 0xbff00000UL
+};
+
+void MacroAssembler::libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx, Register edx, Register ebx, Register esi, Register edi, Register ebp, Register esp) {
+  Label B1_1, B1_2, B1_3, B1_4, B1_5, B1_6, B1_7, B1_8, B1_9, B1_10, B1_11, B1_12;
+  Label B1_13, B1_14, B1_15, B1_16, B1_17, B1_18, B1_19, B1_20, B1_21, B1_22, B1_23;
+  Label B1_24, B1_25, B1_26, B1_27, B1_28, B1_29, B1_30, B1_31, B1_32, B1_33, B1_34;
+  Label B1_35, B1_36, B1_37, B1_38, B1_39, B1_40, B1_41, B1_42, B1_43, B1_44, B1_45, B1_46;
+
+  assert_different_registers(ebx, eax, ecx, edx, esi, edi, ebp, esp);
+
+  address L_2il0floatpacket_0 = (address)_L_2il0floatpacket_0;
+  address Pi4Inv = (address)_Pi4Inv;
+  address Pi4x3 = (address)_Pi4x3;
+  address Pi4x4 = (address)_Pi4x4;
+  address ones = (address)_ones;
+  address CP = (address)_CP;
+  address SP = (address)_SP;
+
+  bind(B1_1);
+  push(ebp);
+  movl(ebp, esp);
+  andl(esp, -64);
+  push(esi);
+  push(edi);
+  push(ebx);
+  subl(esp, 52);
+  movl(eax, Address(ebp, 16));
+  movl(edx, Address(ebp, 20));
+  movl(Address(esp, 32), eax);
+  movl(Address(esp, 36), edx);
+
+  bind(B1_2);
+  fnstcw(Address(esp, 30));
+
+  bind(B1_3);
+  movsd(xmm1, Address(ebp, 8));
+  movl(esi, Address(ebp, 12));
+  movl(eax, esi);
+  andl(eax, 2147483647);
+  andps(xmm1, ExternalAddress(L_2il0floatpacket_0));    //0xffffffffUL, 0x7fffffffUL, 0x00000000UL, 0x00000000UL
+  shrl(esi, 31);
+  movl(Address(esp, 40), eax);
+  cmpl(eax, 1104150528);
+  movsd(Address(ebp, 8), xmm1);
+  jcc(Assembler::aboveEqual, B1_11);
+
+  bind(B1_4);
+  movsd(xmm0, ExternalAddress(Pi4Inv));    //0x6dc9c883UL, 0x3ff45f30UL
+  mulsd(xmm0, xmm1);
+  movzwl(edx, Address(esp, 30));
+  movl(eax, edx);
+  andl(eax, 768);
+  movsd(Address(esp, 0), xmm0);
+  cmpl(eax, 768);
+  jcc(Assembler::equal, B1_42);
+
+  bind(B1_5);
+  orl(edx, -64768);
+  movw(Address(esp, 28), edx);
+
+  bind(B1_6);
+  fldcw(Address(esp, 28));
+
+  bind(B1_7);
+  movsd(xmm1, Address(ebp, 8));
+  movl(ebx, 1);
+
+  bind(B1_8);
+  movl(Address(esp, 12), ebx);
+  movl(ebx, Address(esp, 4));
+  movl(eax, ebx);
+  movl(Address(esp, 8), esi);
+  movl(esi, ebx);
+  shrl(esi, 20);
+  andl(eax, 1048575);
+  movl(ecx, esi);
+  orl(eax, 1048576);
+  negl(ecx);
+  movl(edx, eax);
+  addl(ecx, 19);
+  addl(esi, 13);
+  movl(Address(esp, 24), ecx);
+  shrl(edx);
+  movl(ecx, esi);
+  shll(eax);
+  movl(ecx, Address(esp, 24));
+  movl(esi, Address(esp, 0));
+  shrl(esi);
+  orl(eax, esi);
+  cmpl(ebx, 1094713344);
+  movsd(Address(esp, 16), xmm1);
+  fld_d(Address(esp, 16));
+  cmov32(Assembler::below, eax, edx);
+  movl(esi, Address(esp, 8));
+  lea(edx, Address(eax, 1));
+  movl(ebx, edx);
+  andl(ebx, -2);
+  movl(Address(esp, 16), ebx);
+  fild_s(Address(esp, 16));
+  movl(ebx, Address(esp, 12));
+  cmpl(Address(esp, 40), 1094713344);
+  jcc(Assembler::aboveEqual, B1_10);
+
+  bind(B1_9);
+  fld_d(ExternalAddress(Pi4x3));    //0x54443000UL, 0xbfe921fbUL
+  fmul(1);
+  faddp(2);
+  fld_d(ExternalAddress(8 + Pi4x3));    //0x3b39a000UL, 0x3d373dcbUL
+  fmul(1);
+  faddp(2);
+  fld_d(ExternalAddress(16 + Pi4x3));    //0xe0e68948UL, 0xba845c06UL
+  fmulp(1);
+  faddp(1);
+  jmp(B1_17);
+
+  bind(B1_10);
+  fld_d(ExternalAddress(Pi4x4));    //0x54400000UL, 0xbfe921fbUL
+  fmul(1);
+  faddp(2);
+  fld_d(ExternalAddress(8 + Pi4x4));    //0x1a600000UL, 0xbdc0b461UL
+  fmul(1);
+  faddp(2);
+  fld_d(ExternalAddress(16 + Pi4x4));    //0x2e000000UL, 0xbb93198aUL
+  fmul(1);
+  faddp(2);
+  fld_d(ExternalAddress(24 + Pi4x4));    //0x252049c1UL, 0xb96b839aUL
+  fmulp(1);
+  faddp(1);
+  jmp(B1_17);
+
+  bind(B1_11);
+  movzwl(edx, Address(esp, 30));
+  movl(eax, edx);
+  andl(eax, 768);
+  cmpl(eax, 768);
+  jcc(Assembler::equal, B1_43);
+  bind(B1_12);
+  orl(edx, -64768);
+  movw(Address(esp, 28), edx);
+
+  bind(B1_13);
+  fldcw(Address(esp, 28));
+
+  bind(B1_14);
+  movsd(xmm1, Address(ebp, 8));
+  movl(ebx, 1);
+
+  bind(B1_15);
+  movsd(Address(esp, 16), xmm1);
+  fld_d(Address(esp, 16));
+  addl(esp, -32);
+  lea(eax, Address(esp, 32));
+  fstp_x(Address(esp, 0));
+  movl(Address(esp, 12), 0);
+  movl(Address(esp, 16), eax);
+  call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::dlibm_reduce_pi04l())));
+
+  bind(B1_46);
+  addl(esp, 32);
+
+  bind(B1_16);
+  fld_d(Address(esp, 0));
+  lea(edx, Address(eax, 1));
+  fld_d(Address(esp, 8));
+  faddp(1);
+
+  bind(B1_17);
+  movl(ecx, edx);
+  addl(eax, 3);
+  shrl(ecx, 2);
+  andl(ecx, 1);
+  shrl(eax, 2);
+  xorl(esi, ecx);
+  movl(ecx, Address(esp, 36));
+  andl(eax, 1);
+  andl(ecx, 3);
+  cmpl(ecx, 3);
+  jcc(Assembler::notEqual, B1_25);
+
+  bind(B1_18);
+  fld_x(ExternalAddress(84 + SP));    //0x8610, 0x307f, 0x62
+  fld_s(1);
+  fmul((2));
+  testb(edx, 2);
+  fmula((1));
+  fld_x(ExternalAddress(72 + SP));    //0x44a6, 0xed1a, 0x29
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(60 + SP));    //0xbf33, 0x8bb4, 0x2f
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(48 + SP));    //0x825b, 0x3997, 0x2b
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(36 + SP));    //0x45f6, 0xb616, 0x1d
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(24 + SP));    //0xc527, 0x0d00, 0x00
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(12 + SP));    //0x8887, 0x8888, 0x88
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(SP));    //0xaaab, 0xaaaa, 0xaa
+  faddp(2);
+  fmula(1);
+  fld_x(ExternalAddress(84 + CP));    //0x3ac6, 0x0ba0, 0x07
+  fmul(1);
+  fld_x(ExternalAddress(72 + CP));    //0xdaba, 0xfe79, 0xea
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(62 + CP));    //0xd84d, 0xadee, 0xc6
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(48 + CP));    //0x03fe, 0x3f65, 0x7d
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(36 + CP));    //0xf024, 0x0cac, 0x00
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(24 + CP));    //0x9c2f, 0x0b60, 0x60
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(12 + CP));    //0xaaa5, 0xaaaa, 0xaa
+  faddp(1);
+  fmul(1);
+  fld_x(ExternalAddress(CP));    //0x0000, 0x0000, 0x00
+  faddp(1);
+  fmulp(1);
+  fld_d(Address(ones, RelocationHolder::none).plus_disp(esi, Address::times_8));
+  fld_d(Address(ones, RelocationHolder::none).plus_disp(eax, Address::times_8));
+  jcc(Assembler::equal, B1_22);
+
+  bind(B1_19);
+  fmulp(4);
+  testl(ebx, ebx);
+  fxch(2);
+  fmul(3);
+  movl(eax, Address(esp, 2));
+  faddp(3);
+  fxch(2);
+  fstp_d(Address(eax, 0));
+  fmula(1);
+  faddp(1);
+  fstp_d(Address(eax, 8));
+  jcc(Assembler::equal, B1_21);
+
+  bind(B1_20);
+  fldcw(Address(esp, 30));
+
+  bind(B1_21);
+  addl(esp, 52);
+  pop(ebx);
+  pop(edi);
+  pop(esi);
+  movl(esp, ebp);
+  pop(ebp);
+  ret(0);
+
+  bind(B1_22);
+  fxch(1);
+  fmulp(4);
+  testl(ebx, ebx);
+  fxch(2);
+  fmul(3);
+  movl(eax, Address(esp, 32));
+  faddp(3);
+  fxch(2);
+  fstp_d(Address(eax, 8));
+  fmula(1);
+  faddp(1);
+  fstp_d(Address(eax, 0));
+  jcc(Assembler::equal, B1_24);
+
+  bind(B1_23);
+  fldcw(Address(esp, 30));
+
+  bind(B1_24);
+  addl(esp, 52);
+  pop(ebx);
+  pop(edi);
+  pop(esi);
+  movl(esp, ebp);
+  pop(ebp);
+  ret(0);
+
+  bind(B1_25);
+  testb(Address(esp, 36), 2);
+  jcc(Assembler::equal, B1_33);
+
+  bind(B1_26);
+  fld_s(0);
+  testb(edx, 2);
+  fmul(1);
+  fld_s(0);
+  fmul(1);
+  jcc(Assembler::equal, B1_30);
+
+  bind(B1_27);
+  fstp_d(2);
+  fld_x(ExternalAddress(84 + CP));    //0x3ac6, 0x0ba0, 0x07
+  testl(ebx, ebx);
+  fmul(2);
+  fld_x(ExternalAddress(72 + CP));    //0xdaba, 0xfe79, 0xea
+  fmul(3);
+  fld_x(ExternalAddress(60 + CP));    //0xd84d, 0xadee, 0xc6
+  movl(eax, Address(rsp, 32));
+  faddp(2);
+  fxch(1);
+  fmul(3);
+  fld_x(ExternalAddress(48 + CP));    //0x03fe, 0x3f65, 0x7d
+  faddp(2);
+  fxch(1);
+  fmul(3);
+  fld_x(ExternalAddress(36 + CP));    //0xf024, 0x0cac, 0x00
+  faddp(2);
+  fxch(1);
+  fmul(3);
+  fld_x(ExternalAddress(24 + CP));    //0x9c2f, 0x0b60, 0x60
+  faddp(2);
+  fxch(1);
+  fmul(3);
+  fld_x(ExternalAddress(12 + CP));    //0xaaa5, 0xaaaa, 0xaa
+  faddp(2);