annotate src/os_cpu/windows_x86/vm/windows_x86_32.ad @ 0:a61af66fc99e

Initial load
author duke
date Sat, 01 Dec 2007 00:00:00 +0000
parents
children c18cbe5936b8
rev   line source
duke@0 1 //
duke@0 2 // Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
duke@0 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 // CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 // have any questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // X86 Win32 Architecture Description File
duke@0 26
duke@0 27 //----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
duke@0 28 // This block specifies the encoding classes used by the compiler to output
duke@0 29 // byte streams. Encoding classes generate functions which are called by
duke@0 30 // Machine Instruction Nodes in order to generate the bit encoding of the
duke@0 31 // instruction. Operands specify their base encoding interface with the
duke@0 32 // interface keyword. There are currently supported four interfaces,
duke@0 33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
duke@0 34 // operand to generate a function which returns its register number when
duke@0 35 // queried. CONST_INTER causes an operand to generate a function which
duke@0 36 // returns the value of the constant when queried. MEMORY_INTER causes an
duke@0 37 // operand to generate four functions which return the Base Register, the
duke@0 38 // Index Register, the Scale Value, and the Offset Value of the operand when
duke@0 39 // queried. COND_INTER causes an operand to generate six functions which
duke@0 40 // return the encoding code (ie - encoding bits for the instruction)
duke@0 41 // associated with each basic boolean condition for a conditional instruction.
duke@0 42 // Instructions specify two basic values for encoding. They use the
duke@0 43 // ins_encode keyword to specify their encoding class (which must be one of
duke@0 44 // the class names specified in the encoding block), and they use the
duke@0 45 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 46 // tertiary opcode. Only the opcode sections which a particular instruction
duke@0 47 // needs for encoding need to be specified.
duke@0 48 encode %{
duke@0 49 // Build emit functions for each basic byte or larger field in the intel
duke@0 50 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
duke@0 51 // code in the enc_class source block. Emit functions will live in the
duke@0 52 // main source block for now. In future, we can generalize this by
duke@0 53 // adding a syntax that specifies the sizes of fields in an order,
duke@0 54 // so that the adlc can build the emit functions automagically
duke@0 55
duke@0 56 enc_class tlsencode (eRegP dst, eRegP src) %{
duke@0 57 emit_rm(cbuf, 0x2, $dst$$reg, $src$$reg);
duke@0 58 emit_d32(cbuf, ThreadLocalStorage::get_thread_ptr_offset() );
duke@0 59 %}
duke@0 60
duke@0 61 enc_class call_epilog %{
duke@0 62 if( VerifyStackAtCalls ) {
duke@0 63 // Check that stack depth is unchanged: find majik cookie on stack
duke@0 64 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
duke@0 65 if(framesize >= 128) {
duke@0 66 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
duke@0 67 emit_d8(cbuf,0xBC);
duke@0 68 emit_d8(cbuf,0x24);
duke@0 69 emit_d32(cbuf,framesize); // Find majik cookie from ESP
duke@0 70 emit_d32(cbuf, 0xbadb100d);
duke@0 71 }
duke@0 72 else {
duke@0 73 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
duke@0 74 emit_d8(cbuf,0x7C);
duke@0 75 emit_d8(cbuf,0x24);
duke@0 76 emit_d8(cbuf,framesize); // Find majik cookie from ESP
duke@0 77 emit_d32(cbuf, 0xbadb100d);
duke@0 78 }
duke@0 79 // jmp EQ around INT3
duke@0 80 emit_opcode(cbuf,0x74);
duke@0 81 emit_d8(cbuf,1);
duke@0 82 // Die if stack mismatch
duke@0 83 emit_opcode(cbuf,0xCC);
duke@0 84 }
duke@0 85 %}
duke@0 86
duke@0 87 %}
duke@0 88
duke@0 89 // INSTRUCTIONS -- Platform dependent
duke@0 90
duke@0 91
duke@0 92 //----------OS and Locking Instructions----------------------------------------
duke@0 93
duke@0 94 // The prefix of this name is KNOWN by the ADLC and cannot be changed.
duke@0 95 instruct tlsLoadP_prefixLoadP(eRegP t1) %{
duke@0 96 effect(DEF t1);
duke@0 97
duke@0 98 format %{ "MOV $t1,FS:[0x00] "%}
duke@0 99 opcode(0x8B, 0x64);
duke@0 100 ins_encode(OpcS, OpcP, conmemref(t1));
duke@0 101 ins_pipe( ialu_reg_fat );
duke@0 102 %}
duke@0 103
duke@0 104 // This name is KNOWN by the ADLC and cannot be changed.
duke@0 105 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
duke@0 106 // for this guy.
duke@0 107 // %%% Should do this with a clause like: bottom_type(TypeRawPtr::BOTTOM);
duke@0 108 instruct tlsLoadP(eRegP dst, eRegP t1) %{
duke@0 109 effect(DEF dst, USE t1);
duke@0 110
duke@0 111 format %{ "MOV $dst,[$t1 + TLS::thread_ptr_offset()]" %}
duke@0 112 opcode(0x8B);
duke@0 113 ins_encode(OpcP, tlsencode(dst, t1));
duke@0 114 ins_pipe( ialu_reg_reg_fat );
duke@0 115 %}
duke@0 116
duke@0 117 instruct TLS(eRegP dst) %{
duke@0 118 match(Set dst (ThreadLocal));
duke@0 119 expand %{
duke@0 120 eRegP t1;
duke@0 121 tlsLoadP_prefixLoadP(t1);
duke@0 122 tlsLoadP(dst, t1);
duke@0 123 %}
duke@0 124 %}
duke@0 125
duke@0 126 // Die now
duke@0 127 instruct ShouldNotReachHere( )
duke@0 128 %{
duke@0 129 match(Halt);
duke@0 130 // Use the following format syntax
duke@0 131 format %{ "INT3 ; ShouldNotReachHere" %}
duke@0 132 opcode(0xCC);
duke@0 133 ins_encode(OpcP);
duke@0 134 ins_pipe( pipe_slow );
duke@0 135 %}
duke@0 136
duke@0 137 //
duke@0 138 // Platform dependent source
duke@0 139 //
duke@0 140 source %{
duke@0 141
duke@0 142 // emit an interrupt that is caught by the debugger
duke@0 143 void emit_break(CodeBuffer &cbuf) {
duke@0 144 *(cbuf.code_end()) = (unsigned char)(0xcc);
duke@0 145 cbuf.set_code_end(cbuf.code_end() + 1);
duke@0 146 }
duke@0 147
duke@0 148 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 149 emit_break(cbuf);
duke@0 150 }
duke@0 151
duke@0 152
duke@0 153 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
duke@0 154 return 1;
duke@0 155 }
duke@0 156
duke@0 157
duke@0 158 %}