annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 3064:0382d2b469b2

7013347: allow crypto functions to be called inline to enhance performance Reviewed-by: kvn
author never
date Wed, 01 Feb 2012 16:57:08 -0800
parents 6729bbc1fcd6
children 931e5f39e365
rev   line source
duke@0 1 /*
never@3064 2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1489 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1489 20 * or visit www.oracle.com if you need additional information or have any
trims@1489 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1869 25 #include "precompiled.hpp"
stefank@1869 26 #include "asm/assembler.hpp"
stefank@1869 27 #include "assembler_sparc.inline.hpp"
stefank@1869 28 #include "code/debugInfoRec.hpp"
stefank@1869 29 #include "code/icBuffer.hpp"
stefank@1869 30 #include "code/vtableStubs.hpp"
stefank@1869 31 #include "interpreter/interpreter.hpp"
stefank@1869 32 #include "oops/compiledICHolderOop.hpp"
stefank@1869 33 #include "prims/jvmtiRedefineClassesTrace.hpp"
stefank@1869 34 #include "runtime/sharedRuntime.hpp"
stefank@1869 35 #include "runtime/vframeArray.hpp"
stefank@1869 36 #include "vmreg_sparc.inline.hpp"
stefank@1869 37 #ifdef COMPILER1
stefank@1869 38 #include "c1/c1_Runtime1.hpp"
stefank@1869 39 #endif
stefank@1869 40 #ifdef COMPILER2
stefank@1869 41 #include "opto/runtime.hpp"
stefank@1869 42 #endif
stefank@1869 43 #ifdef SHARK
stefank@1869 44 #include "compiler/compileBroker.hpp"
stefank@1869 45 #include "shark/sharkCompiler.hpp"
stefank@1869 46 #endif
duke@0 47
duke@0 48 #define __ masm->
duke@0 49
duke@0 50
duke@0 51 class RegisterSaver {
duke@0 52
duke@0 53 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@0 54 // The Oregs are problematic. In the 32bit build the compiler can
duke@0 55 // have O registers live with 64 bit quantities. A window save will
duke@0 56 // cut the heads off of the registers. We have to do a very extensive
duke@0 57 // stack dance to save and restore these properly.
duke@0 58
duke@0 59 // Note that the Oregs problem only exists if we block at either a polling
duke@0 60 // page exception a compiled code safepoint that was not originally a call
duke@0 61 // or deoptimize following one of these kinds of safepoints.
duke@0 62
duke@0 63 // Lots of registers to save. For all builds, a window save will preserve
duke@0 64 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@0 65 // builds a window-save will preserve the %o registers. In the LION build
duke@0 66 // we need to save the 64-bit %o registers which requires we save them
duke@0 67 // before the window-save (as then they become %i registers and get their
duke@0 68 // heads chopped off on interrupt). We have to save some %g registers here
duke@0 69 // as well.
duke@0 70 enum {
duke@0 71 // This frame's save area. Includes extra space for the native call:
duke@0 72 // vararg's layout space and the like. Briefly holds the caller's
duke@0 73 // register save area.
duke@0 74 call_args_area = frame::register_save_words_sp_offset +
duke@0 75 frame::memory_parameter_word_sp_offset*wordSize,
duke@0 76 // Make sure save locations are always 8 byte aligned.
duke@0 77 // can't use round_to because it doesn't produce compile time constant
duke@0 78 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@0 79 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@0 80 g3_offset = g1_offset+8,
duke@0 81 g4_offset = g3_offset+8,
duke@0 82 g5_offset = g4_offset+8,
duke@0 83 o0_offset = g5_offset+8,
duke@0 84 o1_offset = o0_offset+8,
duke@0 85 o2_offset = o1_offset+8,
duke@0 86 o3_offset = o2_offset+8,
duke@0 87 o4_offset = o3_offset+8,
duke@0 88 o5_offset = o4_offset+8,
duke@0 89 start_of_flags_save_area = o5_offset+8,
duke@0 90 ccr_offset = start_of_flags_save_area,
duke@0 91 fsr_offset = ccr_offset + 8,
duke@0 92 d00_offset = fsr_offset+8, // Start of float save area
duke@0 93 register_save_size = d00_offset+8*32
duke@0 94 };
duke@0 95
duke@0 96
duke@0 97 public:
duke@0 98
duke@0 99 static int Oexception_offset() { return o0_offset; };
duke@0 100 static int G3_offset() { return g3_offset; };
duke@0 101 static int G5_offset() { return g5_offset; };
duke@0 102 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@0 103 static void restore_live_registers(MacroAssembler* masm);
duke@0 104
duke@0 105 // During deoptimization only the result register need to be restored
duke@0 106 // all the other values have already been extracted.
duke@0 107
duke@0 108 static void restore_result_registers(MacroAssembler* masm);
duke@0 109 };
duke@0 110
duke@0 111 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@0 112 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@0 113 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@0 114 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@0 115 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@0 116 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@0 117 int i;
kvn@992 118 // Always make the frame size 16 byte aligned.
duke@0 119 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@0 120 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@0 121 int frame_size_in_slots = frame_size / sizeof(jint);
duke@0 122 // CodeBlob frame size is in words.
duke@0 123 *total_frame_words = frame_size / wordSize;
duke@0 124 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@0 125 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@0 126
duke@0 127 #if !defined(_LP64)
duke@0 128
duke@0 129 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@0 130 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 131 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 132 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 133 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 134 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 135 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 136 #endif /* _LP64 */
duke@0 137
duke@0 138 __ save(SP, -frame_size, SP);
duke@0 139
duke@0 140 #ifndef _LP64
duke@0 141 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@0 142 // to Oregs here to avoid interrupts cutting off their heads
duke@0 143
duke@0 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 150
duke@0 151 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@0 152 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@0 153
duke@0 154 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@0 155
duke@0 156 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@0 157
duke@0 158 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@0 159 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@0 160
duke@0 161 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@0 162 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@0 163
duke@0 164 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@0 165 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@0 166
duke@0 167 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@0 168 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@0 169 #endif /* _LP64 */
duke@0 170
coleenp@108 171
coleenp@108 172 #ifdef _LP64
coleenp@108 173 int debug_offset = 0;
coleenp@108 174 #else
coleenp@108 175 int debug_offset = 4;
coleenp@108 176 #endif
duke@0 177 // Save the G's
duke@0 178 __ stx(G1, SP, g1_offset+STACK_BIAS);
coleenp@108 179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
duke@0 180
duke@0 181 __ stx(G3, SP, g3_offset+STACK_BIAS);
coleenp@108 182 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
duke@0 183
duke@0 184 __ stx(G4, SP, g4_offset+STACK_BIAS);
coleenp@108 185 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
duke@0 186
duke@0 187 __ stx(G5, SP, g5_offset+STACK_BIAS);
coleenp@108 188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
duke@0 189
duke@0 190 // This is really a waste but we'll keep things as they were for now
duke@0 191 if (true) {
duke@0 192 #ifndef _LP64
duke@0 193 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@0 194 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@0 195 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@0 196 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@0 197 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@0 198 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@0 199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@0 200 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@0 201 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@0 202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
coleenp@108 203 #endif /* _LP64 */
duke@0 204 }
duke@0 205
duke@0 206
duke@0 207 // Save the flags
duke@0 208 __ rdccr( G5 );
duke@0 209 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@0 210 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 211
kvn@992 212 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
duke@0 213 int offset = d00_offset;
kvn@992 214 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 215 FloatRegister f = as_FloatRegister(i);
duke@0 216 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
kvn@992 217 // Record as callee saved both halves of double registers (2 float registers).
duke@0 218 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
kvn@992 219 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@0 220 offset += sizeof(double);
duke@0 221 }
duke@0 222
duke@0 223 // And we're done.
duke@0 224
duke@0 225 return map;
duke@0 226 }
duke@0 227
duke@0 228
duke@0 229 // Pop the current frame and restore all the registers that we
duke@0 230 // saved.
duke@0 231 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@0 232
duke@0 233 // Restore all the FP registers
kvn@992 234 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 235 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@0 236 }
duke@0 237
duke@0 238 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@0 239 __ wrccr (G1) ;
duke@0 240
duke@0 241 // Restore the G's
duke@0 242 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@0 243 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@0 244
duke@0 245 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 246 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@0 247 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@0 248 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@0 249
duke@0 250
duke@0 251 #if !defined(_LP64)
duke@0 252 // Restore the 64-bit O's.
duke@0 253 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 254 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 255 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@0 256 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@0 257 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@0 258 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@0 259
duke@0 260 // And temporarily place them in TLS
duke@0 261
duke@0 262 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 263 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 264 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 265 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 266 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 267 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 268 #endif /* _LP64 */
duke@0 269
duke@0 270 // Restore flags
duke@0 271
duke@0 272 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 273
duke@0 274 __ restore();
duke@0 275
duke@0 276 #if !defined(_LP64)
duke@0 277 // Now reload the 64bit Oregs after we've restore the window.
duke@0 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 284 #endif /* _LP64 */
duke@0 285
duke@0 286 }
duke@0 287
duke@0 288 // Pop the current frame and restore the registers that might be holding
duke@0 289 // a result.
duke@0 290 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@0 291
duke@0 292 #if !defined(_LP64)
duke@0 293 // 32bit build returns longs in G1
duke@0 294 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 295
duke@0 296 // Retrieve the 64-bit O's.
duke@0 297 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 298 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 299 // and save to TLS
duke@0 300 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 301 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 302 #endif /* _LP64 */
duke@0 303
duke@0 304 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@0 305
duke@0 306 __ restore();
duke@0 307
duke@0 308 #if !defined(_LP64)
duke@0 309 // Now reload the 64bit Oregs after we've restore the window.
duke@0 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 311 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 312 #endif /* _LP64 */
duke@0 313
duke@0 314 }
duke@0 315
duke@0 316 // The java_calling_convention describes stack locations as ideal slots on
duke@0 317 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@0 318 // (like the placement of the register window) the slots must be biased by
duke@0 319 // the following value.
duke@0 320 static int reg2offset(VMReg r) {
duke@0 321 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@0 322 }
duke@0 323
never@3064 324 static VMRegPair reg64_to_VMRegPair(Register r) {
never@3064 325 VMRegPair ret;
never@3064 326 if (wordSize == 8) {
never@3064 327 ret.set2(r->as_VMReg());
never@3064 328 } else {
never@3064 329 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
never@3064 330 }
never@3064 331 return ret;
never@3064 332 }
never@3064 333
duke@0 334 // ---------------------------------------------------------------------------
duke@0 335 // Read the array of BasicTypes from a signature, and compute where the
duke@0 336 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@0 337 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@0 338 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@0 339 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@0 340 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@0 341 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@0 342 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@0 343 // Each 32-bit quantity is given its own number, so the integer registers
duke@0 344 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@0 345 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@0 346
duke@0 347 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@0 348 // convert to incoming arguments, convert all O's to I's. The regs array
duke@0 349 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@0 350 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@0 351 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@0 352 // passed (used as a placeholder for the other half of longs and doubles in
duke@0 353 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@0 354 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@0 355 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@0 356 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@0 357 // same VMRegPair.
duke@0 358
duke@0 359 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@0 360 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@0 361 // units regardless of build.
duke@0 362
duke@0 363
duke@0 364 // ---------------------------------------------------------------------------
duke@0 365 // The compiled Java calling convention. The Java convention always passes
duke@0 366 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@0 367 // floats in float registers and doubles in aligned float pairs. Values are
duke@0 368 // packed in the registers. There is no backing varargs store for values in
duke@0 369 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@0 370 // passed in I's, because longs in I's get their heads chopped off at
duke@0 371 // interrupt).
duke@0 372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@0 373 VMRegPair *regs,
duke@0 374 int total_args_passed,
duke@0 375 int is_outgoing) {
duke@0 376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@0 377
duke@0 378 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@0 379 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@0 380 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@0 381 // align. Then put longs and doubles into the same registers as they fit,
duke@0 382 // else spill to the stack.
duke@0 383 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@0 384 const int flt_reg_max = 8;
duke@0 385 //
duke@0 386 // Where 32-bit 1-reg longs start being passed
duke@0 387 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@0 388 // So make it look like we've filled all the G regs that c2 wants to use.
duke@0 389 Register g_reg = TieredCompilation ? noreg : G1;
duke@0 390
duke@0 391 // Count int/oop and float args. See how many stack slots we'll need and
duke@0 392 // where the longs & doubles will go.
duke@0 393 int int_reg_cnt = 0;
duke@0 394 int flt_reg_cnt = 0;
duke@0 395 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@0 396 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@0 397 int stk_reg_pairs = 0;
duke@0 398 for (int i = 0; i < total_args_passed; i++) {
duke@0 399 switch (sig_bt[i]) {
duke@0 400 case T_LONG: // LP64, longs compete with int args
duke@0 401 assert(sig_bt[i+1] == T_VOID, "");
duke@0 402 #ifdef _LP64
duke@0 403 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 404 #endif
duke@0 405 break;
duke@0 406 case T_OBJECT:
duke@0 407 case T_ARRAY:
duke@0 408 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 409 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 410 #ifndef _LP64
duke@0 411 else stk_reg_pairs++;
duke@0 412 #endif
duke@0 413 break;
duke@0 414 case T_INT:
duke@0 415 case T_SHORT:
duke@0 416 case T_CHAR:
duke@0 417 case T_BYTE:
duke@0 418 case T_BOOLEAN:
duke@0 419 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 420 else stk_reg_pairs++;
duke@0 421 break;
duke@0 422 case T_FLOAT:
duke@0 423 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@0 424 else stk_reg_pairs++;
duke@0 425 break;
duke@0 426 case T_DOUBLE:
duke@0 427 assert(sig_bt[i+1] == T_VOID, "");
duke@0 428 break;
duke@0 429 case T_VOID:
duke@0 430 break;
duke@0 431 default:
duke@0 432 ShouldNotReachHere();
duke@0 433 }
duke@0 434 }
duke@0 435
duke@0 436 // This is where the longs/doubles start on the stack.
duke@0 437 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@0 438
duke@0 439 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
duke@0 440 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@0 441
duke@0 442 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@0 443 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@0 444 int stk_reg = 0;
duke@0 445 int int_reg = 0;
duke@0 446 int flt_reg = 0;
duke@0 447
duke@0 448 // Now do the signature layout
duke@0 449 for (int i = 0; i < total_args_passed; i++) {
duke@0 450 switch (sig_bt[i]) {
duke@0 451 case T_INT:
duke@0 452 case T_SHORT:
duke@0 453 case T_CHAR:
duke@0 454 case T_BYTE:
duke@0 455 case T_BOOLEAN:
duke@0 456 #ifndef _LP64
duke@0 457 case T_OBJECT:
duke@0 458 case T_ARRAY:
duke@0 459 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 460 #endif // _LP64
duke@0 461 if (int_reg < int_reg_max) {
duke@0 462 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 463 regs[i].set1(r->as_VMReg());
duke@0 464 } else {
duke@0 465 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 466 }
duke@0 467 break;
duke@0 468
duke@0 469 #ifdef _LP64
duke@0 470 case T_OBJECT:
duke@0 471 case T_ARRAY:
duke@0 472 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 473 if (int_reg < int_reg_max) {
duke@0 474 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 475 regs[i].set2(r->as_VMReg());
duke@0 476 } else {
duke@0 477 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 478 stk_reg_pairs += 2;
duke@0 479 }
duke@0 480 break;
duke@0 481 #endif // _LP64
duke@0 482
duke@0 483 case T_LONG:
duke@0 484 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@0 485 #ifdef _LP64
duke@0 486 if (int_reg < int_reg_max) {
duke@0 487 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 488 regs[i].set2(r->as_VMReg());
duke@0 489 } else {
duke@0 490 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 491 stk_reg_pairs += 2;
duke@0 492 }
duke@0 493 #else
never@297 494 #ifdef COMPILER2
duke@0 495 // For 32-bit build, can't pass longs in O-regs because they become
duke@0 496 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@0 497 // spare and available. This convention isn't used by the Sparc ABI or
duke@0 498 // anywhere else. If we're tiered then we don't use G-regs because c1
never@297 499 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
duke@0 500 // G0: zero
duke@0 501 // G1: 1st Long arg
duke@0 502 // G2: global allocated to TLS
duke@0 503 // G3: used in inline cache check
duke@0 504 // G4: 2nd Long arg
duke@0 505 // G5: used in inline cache check
duke@0 506 // G6: used by OS
duke@0 507 // G7: used by OS
duke@0 508
duke@0 509 if (g_reg == G1) {
duke@0 510 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@0 511 g_reg = G4; // Where the next arg goes
duke@0 512 } else if (g_reg == G4) {
duke@0 513 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@0 514 g_reg = noreg; // No more longs in registers
duke@0 515 } else {
duke@0 516 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 517 stk_reg_pairs += 2;
duke@0 518 }
duke@0 519 #else // COMPILER2
duke@0 520 if (int_reg_pairs + 1 < int_reg_max) {
duke@0 521 if (is_outgoing) {
duke@0 522 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
duke@0 523 } else {
duke@0 524 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
duke@0 525 }
duke@0 526 int_reg_pairs += 2;
duke@0 527 } else {
duke@0 528 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 529 stk_reg_pairs += 2;
duke@0 530 }
duke@0 531 #endif // COMPILER2
never@297 532 #endif // _LP64
duke@0 533 break;
duke@0 534
duke@0 535 case T_FLOAT:
duke@0 536 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
duke@0 537 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
duke@0 538 break;
duke@0 539 case T_DOUBLE:
duke@0 540 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@0 541 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@0 542 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@0 543 flt_reg_pairs += 2;
duke@0 544 } else {
duke@0 545 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 546 stk_reg_pairs += 2;
duke@0 547 }
duke@0 548 break;
duke@0 549 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@0 550 default:
duke@0 551 ShouldNotReachHere();
duke@0 552 }
duke@0 553 }
duke@0 554
duke@0 555 // retun the amount of stack space these arguments will need.
duke@0 556 return stk_reg_pairs;
duke@0 557
duke@0 558 }
duke@0 559
twisti@991 560 // Helper class mostly to avoid passing masm everywhere, and handle
twisti@991 561 // store displacement overflow logic.
duke@0 562 class AdapterGenerator {
duke@0 563 MacroAssembler *masm;
duke@0 564 Register Rdisp;
duke@0 565 void set_Rdisp(Register r) { Rdisp = r; }
duke@0 566
duke@0 567 void patch_callers_callsite();
duke@0 568
duke@0 569 // base+st_off points to top of argument
twisti@1401 570 int arg_offset(const int st_off) { return st_off; }
duke@0 571 int next_arg_offset(const int st_off) {
twisti@1401 572 return st_off - Interpreter::stackElementSize;
twisti@991 573 }
twisti@991 574
twisti@991 575 // Argument slot values may be loaded first into a register because
twisti@991 576 // they might not fit into displacement.
twisti@991 577 RegisterOrConstant arg_slot(const int st_off);
twisti@991 578 RegisterOrConstant next_arg_slot(const int st_off);
twisti@991 579
duke@0 580 // Stores long into offset pointed to by base
duke@0 581 void store_c2i_long(Register r, Register base,
duke@0 582 const int st_off, bool is_stack);
duke@0 583 void store_c2i_object(Register r, Register base,
duke@0 584 const int st_off);
duke@0 585 void store_c2i_int(Register r, Register base,
duke@0 586 const int st_off);
duke@0 587 void store_c2i_double(VMReg r_2,
duke@0 588 VMReg r_1, Register base, const int st_off);
duke@0 589 void store_c2i_float(FloatRegister f, Register base,
duke@0 590 const int st_off);
duke@0 591
duke@0 592 public:
duke@0 593 void gen_c2i_adapter(int total_args_passed,
duke@0 594 // VMReg max_arg,
duke@0 595 int comp_args_on_stack, // VMRegStackSlots
duke@0 596 const BasicType *sig_bt,
duke@0 597 const VMRegPair *regs,
duke@0 598 Label& skip_fixup);
duke@0 599 void gen_i2c_adapter(int total_args_passed,
duke@0 600 // VMReg max_arg,
duke@0 601 int comp_args_on_stack, // VMRegStackSlots
duke@0 602 const BasicType *sig_bt,
duke@0 603 const VMRegPair *regs);
duke@0 604
duke@0 605 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@0 606 };
duke@0 607
duke@0 608
duke@0 609 // Patch the callers callsite with entry to compiled code if it exists.
duke@0 610 void AdapterGenerator::patch_callers_callsite() {
duke@0 611 Label L;
duke@0 612 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
kvn@2600 613 __ br_null(G3_scratch, false, Assembler::pt, L);
duke@0 614 // Schedule the branch target address early.
duke@0 615 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 616 // Call into the VM to patch the caller, then jump to compiled callee
duke@0 617 __ save_frame(4); // Args in compiled layout; do not blow them
duke@0 618
duke@0 619 // Must save all the live Gregs the list is:
duke@0 620 // G1: 1st Long arg (32bit build)
duke@0 621 // G2: global allocated to TLS
duke@0 622 // G3: used in inline cache check (scratch)
duke@0 623 // G4: 2nd Long arg (32bit build);
duke@0 624 // G5: used in inline cache check (methodOop)
duke@0 625
duke@0 626 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@0 627
duke@0 628 #ifdef _LP64
duke@0 629 // mov(s,d)
duke@0 630 __ mov(G1, L1);
duke@0 631 __ mov(G4, L4);
duke@0 632 __ mov(G5_method, L5);
duke@0 633 __ mov(G5_method, O0); // VM needs target method
duke@0 634 __ mov(I7, O1); // VM needs caller's callsite
duke@0 635 // Must be a leaf call...
duke@0 636 // can be very far once the blob has been relocated
twisti@720 637 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@0 638 __ relocate(relocInfo::runtime_call_type);
twisti@720 639 __ jumpl_to(dest, O7, O7);
duke@0 640 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 641 __ mov(L7_thread_cache, G2_thread);
duke@0 642 __ mov(L1, G1);
duke@0 643 __ mov(L4, G4);
duke@0 644 __ mov(L5, G5_method);
duke@0 645 #else
duke@0 646 __ stx(G1, FP, -8 + STACK_BIAS);
duke@0 647 __ stx(G4, FP, -16 + STACK_BIAS);
duke@0 648 __ mov(G5_method, L5);
duke@0 649 __ mov(G5_method, O0); // VM needs target method
duke@0 650 __ mov(I7, O1); // VM needs caller's callsite
duke@0 651 // Must be a leaf call...
duke@0 652 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@0 653 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 654 __ mov(L7_thread_cache, G2_thread);
duke@0 655 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@0 656 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@0 657 __ mov(L5, G5_method);
duke@0 658 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 659 #endif /* _LP64 */
duke@0 660
duke@0 661 __ restore(); // Restore args
duke@0 662 __ bind(L);
duke@0 663 }
duke@0 664
twisti@991 665
twisti@991 666 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
twisti@991 667 RegisterOrConstant roc(arg_offset(st_off));
twisti@991 668 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 669 }
duke@0 670
twisti@991 671 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
twisti@991 672 RegisterOrConstant roc(next_arg_offset(st_off));
twisti@991 673 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 674 }
twisti@991 675
twisti@991 676
duke@0 677 // Stores long into offset pointed to by base
duke@0 678 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@0 679 const int st_off, bool is_stack) {
duke@0 680 #ifdef _LP64
duke@0 681 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 682 // data is passed in only 1 slot.
duke@0 683 __ stx(r, base, next_arg_slot(st_off));
duke@0 684 #else
ysr@344 685 #ifdef COMPILER2
duke@0 686 // Misaligned store of 64-bit data
duke@0 687 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 688 __ srlx(r, 32, r);
duke@0 689 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 690 #else
duke@0 691 if (is_stack) {
duke@0 692 // Misaligned store of 64-bit data
duke@0 693 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 694 __ srlx(r, 32, r);
duke@0 695 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 696 } else {
duke@0 697 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@0 698 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@0 699 }
duke@0 700 #endif // COMPILER2
ysr@344 701 #endif // _LP64
duke@0 702 }
duke@0 703
duke@0 704 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@0 705 const int st_off) {
duke@0 706 __ st_ptr (r, base, arg_slot(st_off));
duke@0 707 }
duke@0 708
duke@0 709 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@0 710 const int st_off) {
duke@0 711 __ st (r, base, arg_slot(st_off));
duke@0 712 }
duke@0 713
duke@0 714 // Stores into offset pointed to by base
duke@0 715 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@0 716 VMReg r_1, Register base, const int st_off) {
duke@0 717 #ifdef _LP64
duke@0 718 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 719 // data is passed in only 1 slot.
duke@0 720 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 721 #else
duke@0 722 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 723 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 724 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@0 725 #endif
duke@0 726 }
duke@0 727
duke@0 728 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@0 729 const int st_off) {
duke@0 730 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@0 731 }
duke@0 732
duke@0 733 void AdapterGenerator::gen_c2i_adapter(
duke@0 734 int total_args_passed,
duke@0 735 // VMReg max_arg,
duke@0 736 int comp_args_on_stack, // VMRegStackSlots
duke@0 737 const BasicType *sig_bt,
duke@0 738 const VMRegPair *regs,
duke@0 739 Label& skip_fixup) {
duke@0 740
duke@0 741 // Before we get into the guts of the C2I adapter, see if we should be here
duke@0 742 // at all. We've come from compiled code and are attempting to jump to the
duke@0 743 // interpreter, which means the caller made a static call to get here
duke@0 744 // (vcalls always get a compiled target if there is one). Check for a
duke@0 745 // compiled target. If there is one, we need to patch the caller's call.
duke@0 746 // However we will run interpreted if we come thru here. The next pass
duke@0 747 // thru the call site will run compiled. If we ran compiled here then
duke@0 748 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@0 749 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@0 750 // we can have at most one and don't need to play any tricks to keep
duke@0 751 // from endlessly growing the stack.
duke@0 752 //
duke@0 753 // Actually if we detected that we had an i2c->c2i transition here we
duke@0 754 // ought to be able to reset the world back to the state of the interpreted
duke@0 755 // call and not bother building another interpreter arg area. We don't
duke@0 756 // do that at this point.
duke@0 757
duke@0 758 patch_callers_callsite();
duke@0 759
duke@0 760 __ bind(skip_fixup);
duke@0 761
duke@0 762 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@0 763 // space we need. Add in varargs area needed by the interpreter. Round up
duke@0 764 // to stack alignment.
twisti@1401 765 const int arg_size = total_args_passed * Interpreter::stackElementSize;
duke@0 766 const int varargs_area =
duke@0 767 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@0 768 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@0 769
duke@0 770 int bias = STACK_BIAS;
duke@0 771 const int interp_arg_offset = frame::varargs_offset*wordSize +
twisti@1401 772 (total_args_passed-1)*Interpreter::stackElementSize;
duke@0 773
duke@0 774 Register base = SP;
duke@0 775
duke@0 776 #ifdef _LP64
duke@0 777 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@0 778 // out of bits in the displacement to do loads and stores. Use g3 as
duke@0 779 // temporary displacement.
twisti@2872 780 if (!Assembler::is_simm13(extraspace)) {
duke@0 781 __ set(extraspace, G3_scratch);
duke@0 782 __ sub(SP, G3_scratch, SP);
duke@0 783 } else {
duke@0 784 __ sub(SP, extraspace, SP);
duke@0 785 }
duke@0 786 set_Rdisp(G3_scratch);
duke@0 787 #else
duke@0 788 __ sub(SP, extraspace, SP);
duke@0 789 #endif // _LP64
duke@0 790
duke@0 791 // First write G1 (if used) to where ever it must go
duke@0 792 for (int i=0; i<total_args_passed; i++) {
twisti@1401 793 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 794 VMReg r_1 = regs[i].first();
duke@0 795 VMReg r_2 = regs[i].second();
duke@0 796 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 797 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 798 store_c2i_object(G1_scratch, base, st_off);
duke@0 799 } else if (sig_bt[i] == T_LONG) {
duke@0 800 assert(!TieredCompilation, "should not use register args for longs");
duke@0 801 store_c2i_long(G1_scratch, base, st_off, false);
duke@0 802 } else {
duke@0 803 store_c2i_int(G1_scratch, base, st_off);
duke@0 804 }
duke@0 805 }
duke@0 806 }
duke@0 807
duke@0 808 // Now write the args into the outgoing interpreter space
duke@0 809 for (int i=0; i<total_args_passed; i++) {
twisti@1401 810 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 811 VMReg r_1 = regs[i].first();
duke@0 812 VMReg r_2 = regs[i].second();
duke@0 813 if (!r_1->is_valid()) {
duke@0 814 assert(!r_2->is_valid(), "");
duke@0 815 continue;
duke@0 816 }
duke@0 817 // Skip G1 if found as we did it first in order to free it up
duke@0 818 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 819 continue;
duke@0 820 }
duke@0 821 #ifdef ASSERT
duke@0 822 bool G1_forced = false;
duke@0 823 #endif // ASSERT
duke@0 824 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@0 825 #ifdef _LP64
duke@0 826 Register ld_off = Rdisp;
duke@0 827 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@0 828 #else
duke@0 829 int ld_off = reg2offset(r_1) + extraspace + bias;
kvn@1209 830 #endif // _LP64
duke@0 831 #ifdef ASSERT
duke@0 832 G1_forced = true;
duke@0 833 #endif // ASSERT
duke@0 834 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@0 835 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@0 836 else __ ldx(base, ld_off, G1_scratch);
duke@0 837 }
duke@0 838
duke@0 839 if (r_1->is_Register()) {
duke@0 840 Register r = r_1->as_Register()->after_restore();
duke@0 841 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 842 store_c2i_object(r, base, st_off);
duke@0 843 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
kvn@1209 844 #ifndef _LP64
duke@0 845 if (TieredCompilation) {
duke@0 846 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@0 847 }
kvn@1209 848 #endif // _LP64
duke@0 849 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@0 850 } else {
duke@0 851 store_c2i_int(r, base, st_off);
duke@0 852 }
duke@0 853 } else {
duke@0 854 assert(r_1->is_FloatRegister(), "");
duke@0 855 if (sig_bt[i] == T_FLOAT) {
duke@0 856 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@0 857 } else {
duke@0 858 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@0 859 store_c2i_double(r_2, r_1, base, st_off);
duke@0 860 }
duke@0 861 }
duke@0 862 }
duke@0 863
duke@0 864 #ifdef _LP64
duke@0 865 // Need to reload G3_scratch, used for temporary displacements.
duke@0 866 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 867
duke@0 868 // Pass O5_savedSP as an argument to the interpreter.
duke@0 869 // The interpreter will restore SP to this value before returning.
duke@0 870 __ set(extraspace, G1);
duke@0 871 __ add(SP, G1, O5_savedSP);
duke@0 872 #else
duke@0 873 // Pass O5_savedSP as an argument to the interpreter.
duke@0 874 // The interpreter will restore SP to this value before returning.
duke@0 875 __ add(SP, extraspace, O5_savedSP);
duke@0 876 #endif // _LP64
duke@0 877
duke@0 878 __ mov((frame::varargs_offset)*wordSize -
twisti@1401 879 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
duke@0 880 // Jump to the interpreter just as if interpreter was doing it.
duke@0 881 __ jmpl(G3_scratch, 0, G0);
duke@0 882 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@0 883 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@0 884 // the interpreter does not know where its args are without some kind of
duke@0 885 // arg pointer being passed in. Pass it in Gargs.
duke@0 886 __ delayed()->add(SP, G1, Gargs);
duke@0 887 }
duke@0 888
duke@0 889 void AdapterGenerator::gen_i2c_adapter(
duke@0 890 int total_args_passed,
duke@0 891 // VMReg max_arg,
duke@0 892 int comp_args_on_stack, // VMRegStackSlots
duke@0 893 const BasicType *sig_bt,
duke@0 894 const VMRegPair *regs) {
duke@0 895
duke@0 896 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@0 897 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@0 898 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@0 899 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@0 900 // hoist register arguments and repack other args according to the compiled
duke@0 901 // code convention. Finally, end in a jump to the compiled code. The entry
duke@0 902 // point address is the start of the buffer.
duke@0 903
duke@0 904 // We will only enter here from an interpreted frame and never from after
duke@0 905 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@0 906 // race and use a c2i we will remain interpreted for the race loser(s).
duke@0 907 // This removes all sorts of headaches on the x86 side and also eliminates
duke@0 908 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@0 909
duke@0 910 // As you can see from the list of inputs & outputs there are not a lot
duke@0 911 // of temp registers to work with: mostly G1, G3 & G4.
duke@0 912
duke@0 913 // Inputs:
duke@0 914 // G2_thread - TLS
duke@0 915 // G5_method - Method oop
jrose@689 916 // G4 (Gargs) - Pointer to interpreter's args
jrose@689 917 // O0..O4 - free for scratch
jrose@689 918 // O5_savedSP - Caller's saved SP, to be restored if needed
duke@0 919 // O6 - Current SP!
duke@0 920 // O7 - Valid return address
jrose@689 921 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 922
duke@0 923 // Outputs:
duke@0 924 // G2_thread - TLS
duke@0 925 // G1, G4 - Outgoing long args in 32-bit build
duke@0 926 // O0-O5 - Outgoing args in compiled layout
duke@0 927 // O6 - Adjusted or restored SP
duke@0 928 // O7 - Valid return address
twisti@1457 929 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 930 // F0-F7 - more outgoing args
duke@0 931
duke@0 932
jrose@689 933 // Gargs is the incoming argument base, and also an outgoing argument.
duke@0 934 __ sub(Gargs, BytesPerWord, Gargs);
duke@0 935
duke@0 936 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@0 937 // WITH O7 HOLDING A VALID RETURN PC
duke@0 938 //
duke@0 939 // | |
duke@0 940 // : java stack :
duke@0 941 // | |
duke@0 942 // +--------------+ <--- start of outgoing args
duke@0 943 // | receiver | |
duke@0 944 // : rest of args : |---size is java-arg-words
duke@0 945 // | | |
duke@0 946 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@0 947 // | | |
duke@0 948 // : unused : |---Space for max Java stack, plus stack alignment
duke@0 949 // | | |
duke@0 950 // +--------------+ <--- SP + 16*wordsize
duke@0 951 // | |
duke@0 952 // : window :
duke@0 953 // | |
duke@0 954 // +--------------+ <--- SP
duke@0 955
duke@0 956 // WE REPACK THE STACK. We use the common calling convention layout as
duke@0 957 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@0 958 // causes an arbitrary shuffle of memory, which may require some register
duke@0 959 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@0 960 // temps are not needed. We may have to resize the stack slightly, in case
duke@0 961 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@0 962 // misaligned, but the compilers expect them aligned).
duke@0 963 //
duke@0 964 // | |
duke@0 965 // : java stack :
duke@0 966 // | |
duke@0 967 // +--------------+ <--- start of outgoing args
duke@0 968 // | pad, align | |
duke@0 969 // +--------------+ |
duke@0 970 // | ints, floats | |---Outgoing stack args, packed low.
duke@0 971 // +--------------+ | First few args in registers.
duke@0 972 // : doubles : |
duke@0 973 // | longs | |
duke@0 974 // +--------------+ <--- SP' + 16*wordsize
duke@0 975 // | |
duke@0 976 // : window :
duke@0 977 // | |
duke@0 978 // +--------------+ <--- SP'
duke@0 979
duke@0 980 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@0 981 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@0 982 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@0 983
duke@0 984 // Cut-out for having no stack args. Since up to 6 args are passed
duke@0 985 // in registers, we will commonly have no stack args.
duke@0 986 if (comp_args_on_stack > 0) {
duke@0 987
duke@0 988 // Convert VMReg stack slots to words.
duke@0 989 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@0 990 // Round up to miminum stack alignment, in wordSize
duke@0 991 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@0 992 // Now compute the distance from Lesp to SP. This calculation does not
duke@0 993 // include the space for total_args_passed because Lesp has not yet popped
duke@0 994 // the arguments.
duke@0 995 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@0 996 }
duke@0 997
duke@0 998 // Will jump to the compiled code just as if compiled code was doing it.
duke@0 999 // Pre-load the register-jump target early, to schedule it better.
duke@0 1000 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@0 1001
duke@0 1002 // Now generate the shuffle code. Pick up all register args and move the
duke@0 1003 // rest through G1_scratch.
duke@0 1004 for (int i=0; i<total_args_passed; i++) {
duke@0 1005 if (sig_bt[i] == T_VOID) {
duke@0 1006 // Longs and doubles are passed in native word order, but misaligned
duke@0 1007 // in the 32-bit build.
duke@0 1008 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@0 1009 continue;
duke@0 1010 }
duke@0 1011
duke@0 1012 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@0 1013 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@0 1014 // ldx/lddf optimizations.
duke@0 1015
duke@0 1016 // Load in argument order going down.
twisti@1401 1017 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1018 set_Rdisp(G1_scratch);
duke@0 1019
duke@0 1020 VMReg r_1 = regs[i].first();
duke@0 1021 VMReg r_2 = regs[i].second();
duke@0 1022 if (!r_1->is_valid()) {
duke@0 1023 assert(!r_2->is_valid(), "");
duke@0 1024 continue;
duke@0 1025 }
duke@0 1026 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@0 1027 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@0 1028 if (r_2->is_valid()) r_2 = r_1->next();
duke@0 1029 }
duke@0 1030 if (r_1->is_Register()) { // Register argument
duke@0 1031 Register r = r_1->as_Register()->after_restore();
duke@0 1032 if (!r_2->is_valid()) {
duke@0 1033 __ ld(Gargs, arg_slot(ld_off), r);
duke@0 1034 } else {
duke@0 1035 #ifdef _LP64
duke@0 1036 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 1037 // data is passed in only 1 slot.
twisti@991 1038 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
duke@0 1039 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1040 __ ldx(Gargs, slot, r);
duke@0 1041 #else
duke@0 1042 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@0 1043 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@0 1044 #endif
duke@0 1045 }
duke@0 1046 } else {
duke@0 1047 assert(r_1->is_FloatRegister(), "");
duke@0 1048 if (!r_2->is_valid()) {
duke@0 1049 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1050 } else {
duke@0 1051 #ifdef _LP64
duke@0 1052 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 1053 // data is passed in only 1 slot. This code also handles longs that
duke@0 1054 // are passed on the stack, but need a stack-to-stack move through a
duke@0 1055 // spare float register.
twisti@991 1056 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@0 1057 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1058 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@0 1059 #else
duke@0 1060 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1061 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1062 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@0 1063 #endif
duke@0 1064 }
duke@0 1065 }
duke@0 1066 // Was the argument really intended to be on the stack, but was loaded
duke@0 1067 // into F8/F9?
duke@0 1068 if (regs[i].first()->is_stack()) {
duke@0 1069 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@0 1070 // Convert stack slot to an SP offset
duke@0 1071 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@0 1072 // Store down the shuffled stack word. Target address _is_ aligned.
twisti@991 1073 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
twisti@991 1074 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
twisti@991 1075 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
duke@0 1076 }
duke@0 1077 }
duke@0 1078 bool made_space = false;
duke@0 1079 #ifndef _LP64
duke@0 1080 // May need to pick up a few long args in G1/G4
duke@0 1081 bool g4_crushed = false;
duke@0 1082 bool g3_crushed = false;
duke@0 1083 for (int i=0; i<total_args_passed; i++) {
duke@0 1084 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@0 1085 // Load in argument order going down
twisti@1401 1086 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1087 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1088 Register r = regs[i].first()->as_Register()->after_restore();
duke@0 1089 if (r == G1 || r == G4) {
duke@0 1090 assert(!g4_crushed, "ordering problem");
duke@0 1091 if (r == G4){
duke@0 1092 g4_crushed = true;
duke@0 1093 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1094 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1095 } else {
duke@0 1096 // better schedule this way
duke@0 1097 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1098 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1099 }
duke@0 1100 g3_crushed = true;
duke@0 1101 __ sllx(r, 32, r);
duke@0 1102 __ or3(G3_scratch, r, r);
duke@0 1103 } else {
duke@0 1104 assert(r->is_out(), "longs passed in two O registers");
duke@0 1105 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@0 1106 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1107 }
duke@0 1108 }
duke@0 1109 }
duke@0 1110 #endif
duke@0 1111
duke@0 1112 // Jump to the compiled code just as if compiled code was doing it.
duke@0 1113 //
duke@0 1114 #ifndef _LP64
duke@0 1115 if (g3_crushed) {
duke@0 1116 // Rats load was wasted, at least it is in cache...
twisti@720 1117 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
duke@0 1118 }
duke@0 1119 #endif /* _LP64 */
duke@0 1120
duke@0 1121 // 6243940 We might end up in handle_wrong_method if
duke@0 1122 // the callee is deoptimized as we race thru here. If that
duke@0 1123 // happens we don't want to take a safepoint because the
duke@0 1124 // caller frame will look interpreted and arguments are now
duke@0 1125 // "compiled" so it is much better to make this transition
duke@0 1126 // invisible to the stack walking code. Unfortunately if
duke@0 1127 // we try and find the callee by normal means a safepoint
duke@0 1128 // is possible. So we stash the desired callee in the thread
duke@0 1129 // and the vm will find there should this case occur.
twisti@720 1130 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
duke@0 1131 __ st_ptr(G5_method, callee_target_addr);
duke@0 1132
duke@0 1133 if (StressNonEntrant) {
duke@0 1134 // Open a big window for deopt failure
duke@0 1135 __ save_frame(0);
duke@0 1136 __ mov(G0, L0);
duke@0 1137 Label loop;
duke@0 1138 __ bind(loop);
duke@0 1139 __ sub(L0, 1, L0);
kvn@2600 1140 __ br_null_short(L0, Assembler::pt, loop);
duke@0 1141
duke@0 1142 __ restore();
duke@0 1143 }
duke@0 1144
duke@0 1145
duke@0 1146 __ jmpl(G3, 0, G0);
duke@0 1147 __ delayed()->nop();
duke@0 1148 }
duke@0 1149
duke@0 1150 // ---------------------------------------------------------------
duke@0 1151 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@0 1152 int total_args_passed,
duke@0 1153 // VMReg max_arg,
duke@0 1154 int comp_args_on_stack, // VMRegStackSlots
duke@0 1155 const BasicType *sig_bt,
never@1179 1156 const VMRegPair *regs,
never@1179 1157 AdapterFingerPrint* fingerprint) {
duke@0 1158 address i2c_entry = __ pc();
duke@0 1159
duke@0 1160 AdapterGenerator agen(masm);
duke@0 1161
duke@0 1162 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@0 1163
duke@0 1164
duke@0 1165 // -------------------------------------------------------------------------
duke@0 1166 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
duke@0 1167 // args start out packed in the compiled layout. They need to be unpacked
duke@0 1168 // into the interpreter layout. This will almost always require some stack
duke@0 1169 // space. We grow the current (compiled) stack, then repack the args. We
duke@0 1170 // finally end in a jump to the generic interpreter entry point. On exit
duke@0 1171 // from the interpreter, the interpreter will restore our SP (lest the
duke@0 1172 // compiled code, which relys solely on SP and not FP, get sick).
duke@0 1173
duke@0 1174 address c2i_unverified_entry = __ pc();
duke@0 1175 Label skip_fixup;
duke@0 1176 {
duke@0 1177 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1178 Register R_temp = L0; // another scratch register
duke@0 1179 #else
duke@0 1180 Register R_temp = G1; // another scratch register
duke@0 1181 #endif
duke@0 1182
twisti@720 1183 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1184
duke@0 1185 __ verify_oop(O0);
duke@0 1186 __ verify_oop(G5_method);
coleenp@108 1187 __ load_klass(O0, G3_scratch);
duke@0 1188 __ verify_oop(G3_scratch);
duke@0 1189
duke@0 1190 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1191 __ save(SP, -frame::register_save_words*wordSize, SP);
duke@0 1192 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1193 __ verify_oop(R_temp);
duke@0 1194 __ cmp(G3_scratch, R_temp);
duke@0 1195 __ restore();
duke@0 1196 #else
duke@0 1197 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1198 __ verify_oop(R_temp);
duke@0 1199 __ cmp(G3_scratch, R_temp);
duke@0 1200 #endif
duke@0 1201
duke@0 1202 Label ok, ok2;
duke@0 1203 __ brx(Assembler::equal, false, Assembler::pt, ok);
duke@0 1204 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
twisti@720 1205 __ jump_to(ic_miss, G3_scratch);
duke@0 1206 __ delayed()->nop();
duke@0 1207
duke@0 1208 __ bind(ok);
duke@0 1209 // Method might have been compiled since the call site was patched to
duke@0 1210 // interpreted if that is the case treat it as a miss so we can get
duke@0 1211 // the call site corrected.
duke@0 1212 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 1213 __ bind(ok2);
kvn@2600 1214 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup);
duke@0 1215 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
twisti@720 1216 __ jump_to(ic_miss, G3_scratch);
duke@0 1217 __ delayed()->nop();
duke@0 1218
duke@0 1219 }
duke@0 1220
duke@0 1221 address c2i_entry = __ pc();
duke@0 1222
duke@0 1223 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@0 1224
duke@0 1225 __ flush();
never@1179 1226 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
duke@0 1227
duke@0 1228 }
duke@0 1229
duke@0 1230 // Helper function for native calling conventions
duke@0 1231 static VMReg int_stk_helper( int i ) {
duke@0 1232 // Bias any stack based VMReg we get by ignoring the window area
duke@0 1233 // but not the register parameter save area.
duke@0 1234 //
duke@0 1235 // This is strange for the following reasons. We'd normally expect
duke@0 1236 // the calling convention to return an VMReg for a stack slot
duke@0 1237 // completely ignoring any abi reserved area. C2 thinks of that
duke@0 1238 // abi area as only out_preserve_stack_slots. This does not include
duke@0 1239 // the area allocated by the C abi to store down integer arguments
duke@0 1240 // because the java calling convention does not use it. So
duke@0 1241 // since c2 assumes that there are only out_preserve_stack_slots
duke@0 1242 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@0 1243 // location the c calling convention must add in this bias amount
duke@0 1244 // to make up for the fact that the out_preserve_stack_slots is
duke@0 1245 // insufficient for C calls. What a mess. I sure hope those 6
duke@0 1246 // stack words were worth it on every java call!
duke@0 1247
duke@0 1248 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@0 1249 // to take a parameter to say whether it was C or java calling conventions.
duke@0 1250 // Then things might look a little better (but not much).
duke@0 1251
duke@0 1252 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@0 1253 if( mem_parm_offset < 0 ) {
duke@0 1254 return as_oRegister(i)->as_VMReg();
duke@0 1255 } else {
duke@0 1256 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@0 1257 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@0 1258 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@0 1259 }
duke@0 1260 }
duke@0 1261
duke@0 1262
duke@0 1263 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@0 1264 VMRegPair *regs,
duke@0 1265 int total_args_passed) {
duke@0 1266
duke@0 1267 // Return the number of VMReg stack_slots needed for the args.
duke@0 1268 // This value does not include an abi space (like register window
duke@0 1269 // save area).
duke@0 1270
duke@0 1271 // The native convention is V8 if !LP64
duke@0 1272 // The LP64 convention is the V9 convention which is slightly more sane.
duke@0 1273
duke@0 1274 // We return the amount of VMReg stack slots we need to reserve for all
duke@0 1275 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@0 1276 // have space for storing at least 6 registers to memory we start with that.
duke@0 1277 // See int_stk_helper for a further discussion.
duke@0 1278 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@0 1279
duke@0 1280 #ifdef _LP64
duke@0 1281 // V9 convention: All things "as-if" on double-wide stack slots.
duke@0 1282 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@0 1283 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@0 1284 int j = 0; // Count of actual args, not HALVES
duke@0 1285 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@0 1286 switch( sig_bt[i] ) {
duke@0 1287 case T_BOOLEAN:
duke@0 1288 case T_BYTE:
duke@0 1289 case T_CHAR:
duke@0 1290 case T_INT:
duke@0 1291 case T_SHORT:
duke@0 1292 regs[i].set1( int_stk_helper( j ) ); break;
duke@0 1293 case T_LONG:
duke@0 1294 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1295 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1296 case T_ARRAY:
duke@0 1297 case T_OBJECT:
duke@0 1298 regs[i].set2( int_stk_helper( j ) );
duke@0 1299 break;
duke@0 1300 case T_FLOAT:
duke@0 1301 if ( j < 16 ) {
duke@0 1302 // V9ism: floats go in ODD registers
duke@0 1303 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@0 1304 } else {
duke@0 1305 // V9ism: floats go in ODD stack slot
duke@0 1306 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@0 1307 }
duke@0 1308 break;
duke@0 1309 case T_DOUBLE:
duke@0 1310 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1311 if ( j < 16 ) {
duke@0 1312 // V9ism: doubles go in EVEN/ODD regs
duke@0 1313 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@0 1314 } else {
duke@0 1315 // V9ism: doubles go in EVEN/ODD stack slots
duke@0 1316 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@0 1317 }
duke@0 1318 break;
duke@0 1319 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@0 1320 default:
duke@0 1321 ShouldNotReachHere();
duke@0 1322 }
duke@0 1323 if (regs[i].first()->is_stack()) {
duke@0 1324 int off = regs[i].first()->reg2stack();
duke@0 1325 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1326 }
duke@0 1327 if (regs[i].second()->is_stack()) {
duke@0 1328 int off = regs[i].second()->reg2stack();
duke@0 1329 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1330 }
duke@0 1331 }
duke@0 1332
duke@0 1333 #else // _LP64
duke@0 1334 // V8 convention: first 6 things in O-regs, rest on stack.
duke@0 1335 // Alignment is willy-nilly.
duke@0 1336 for( int i=0; i<total_args_passed; i++ ) {
duke@0 1337 switch( sig_bt[i] ) {
duke@0 1338 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1339 case T_ARRAY:
duke@0 1340 case T_BOOLEAN:
duke@0 1341 case T_BYTE:
duke@0 1342 case T_CHAR:
duke@0 1343 case T_FLOAT:
duke@0 1344 case T_INT:
duke@0 1345 case T_OBJECT:
duke@0 1346 case T_SHORT:
duke@0 1347 regs[i].set1( int_stk_helper( i ) );
duke@0 1348 break;
duke@0 1349 case T_DOUBLE:
duke@0 1350 case T_LONG:
duke@0 1351 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1352 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@0 1353 break;
duke@0 1354 case T_VOID: regs[i].set_bad(); break;
duke@0 1355 default:
duke@0 1356 ShouldNotReachHere();
duke@0 1357 }
duke@0 1358 if (regs[i].first()->is_stack()) {
duke@0 1359 int off = regs[i].first()->reg2stack();
duke@0 1360 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1361 }
duke@0 1362 if (regs[i].second()->is_stack()) {
duke@0 1363 int off = regs[i].second()->reg2stack();
duke@0 1364 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1365 }
duke@0 1366 }
duke@0 1367 #endif // _LP64
duke@0 1368
duke@0 1369 return round_to(max_stack_slots + 1, 2);
duke@0 1370
duke@0 1371 }
duke@0 1372
duke@0 1373
duke@0 1374 // ---------------------------------------------------------------------------
duke@0 1375 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1376 switch (ret_type) {
duke@0 1377 case T_FLOAT:
duke@0 1378 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@0 1379 break;
duke@0 1380 case T_DOUBLE:
duke@0 1381 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@0 1382 break;
duke@0 1383 }
duke@0 1384 }
duke@0 1385
duke@0 1386 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1387 switch (ret_type) {
duke@0 1388 case T_FLOAT:
duke@0 1389 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@0 1390 break;
duke@0 1391 case T_DOUBLE:
duke@0 1392 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@0 1393 break;
duke@0 1394 }
duke@0 1395 }
duke@0 1396
duke@0 1397 // Check and forward and pending exception. Thread is stored in
duke@0 1398 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@0 1399 // is no exception handler. We merely pop this frame off and throw the
duke@0 1400 // exception in the caller's frame.
duke@0 1401 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@0 1402 Label L;
duke@0 1403 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@0 1404 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@0 1405 // Since this is a native call, we *know* the proper exception handler
duke@0 1406 // without calling into the VM: it's the empty function. Just pop this
duke@0 1407 // frame and then jump to forward_exception_entry; O7 will contain the
duke@0 1408 // native caller's return PC.
twisti@720 1409 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
twisti@720 1410 __ jump_to(exception_entry, G3_scratch);
duke@0 1411 __ delayed()->restore(); // Pop this frame off.
duke@0 1412 __ bind(L);
duke@0 1413 }
duke@0 1414
duke@0 1415 // A simple move of integer like type
duke@0 1416 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1417 if (src.first()->is_stack()) {
duke@0 1418 if (dst.first()->is_stack()) {
duke@0 1419 // stack to stack
duke@0 1420 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1421 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1422 } else {
duke@0 1423 // stack to reg
duke@0 1424 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1425 }
duke@0 1426 } else if (dst.first()->is_stack()) {
duke@0 1427 // reg to stack
duke@0 1428 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1429 } else {
duke@0 1430 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1431 }
duke@0 1432 }
duke@0 1433
duke@0 1434 // On 64 bit we will store integer like items to the stack as
duke@0 1435 // 64 bits items (sparc abi) even though java would only store
duke@0 1436 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@0 1437 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@0 1438 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1439 if (src.first()->is_stack()) {
duke@0 1440 if (dst.first()->is_stack()) {
duke@0 1441 // stack to stack
duke@0 1442 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1443 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1444 } else {
duke@0 1445 // stack to reg
duke@0 1446 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1447 }
duke@0 1448 } else if (dst.first()->is_stack()) {
duke@0 1449 // reg to stack
duke@0 1450 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1451 } else {
duke@0 1452 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1453 }
duke@0 1454 }
duke@0 1455
duke@0 1456
never@3064 1457 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
never@3064 1458 if (src.first()->is_stack()) {
never@3064 1459 if (dst.first()->is_stack()) {
never@3064 1460 // stack to stack
never@3064 1461 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5);
never@3064 1462 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
never@3064 1463 } else {
never@3064 1464 // stack to reg
never@3064 1465 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
never@3064 1466 }
never@3064 1467 } else if (dst.first()->is_stack()) {
never@3064 1468 // reg to stack
never@3064 1469 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
never@3064 1470 } else {
never@3064 1471 __ mov(src.first()->as_Register(), dst.first()->as_Register());
never@3064 1472 }
never@3064 1473 }
never@3064 1474
never@3064 1475
duke@0 1476 // An oop arg. Must pass a handle not the oop itself
duke@0 1477 static void object_move(MacroAssembler* masm,
duke@0 1478 OopMap* map,
duke@0 1479 int oop_handle_offset,
duke@0 1480 int framesize_in_slots,
duke@0 1481 VMRegPair src,
duke@0 1482 VMRegPair dst,
duke@0 1483 bool is_receiver,
duke@0 1484 int* receiver_offset) {
duke@0 1485
duke@0 1486 // must pass a handle. First figure out the location we use as a handle
duke@0 1487
duke@0 1488 if (src.first()->is_stack()) {
duke@0 1489 // Oop is already on the stack
duke@0 1490 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@0 1491 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@0 1492 __ ld_ptr(rHandle, 0, L4);
duke@0 1493 #ifdef _LP64
duke@0 1494 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@0 1495 #else
duke@0 1496 __ tst( L4 );
duke@0 1497 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1498 #endif
duke@0 1499 if (dst.first()->is_stack()) {
duke@0 1500 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1501 }
duke@0 1502 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@0 1503 if (is_receiver) {
duke@0 1504 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@0 1505 }
duke@0 1506 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@0 1507 } else {
duke@0 1508 // Oop is in an input register pass we must flush it to the stack
duke@0 1509 const Register rOop = src.first()->as_Register();
duke@0 1510 const Register rHandle = L5;
duke@0 1511 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@0 1512 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@0 1513 Label skip;
duke@0 1514 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@0 1515 if (is_receiver) {
duke@0 1516 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@0 1517 }
duke@0 1518 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@0 1519 __ add(SP, offset + STACK_BIAS, rHandle);
duke@0 1520 #ifdef _LP64
duke@0 1521 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@0 1522 #else
duke@0 1523 __ tst( rOop );
duke@0 1524 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1525 #endif
duke@0 1526
duke@0 1527 if (dst.first()->is_stack()) {
duke@0 1528 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1529 } else {
duke@0 1530 __ mov(rHandle, dst.first()->as_Register());
duke@0 1531 }
duke@0 1532 }
duke@0 1533 }
duke@0 1534
duke@0 1535 // A float arg may have to do float reg int reg conversion
duke@0 1536 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1537 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@0 1538
duke@0 1539 if (src.first()->is_stack()) {
duke@0 1540 if (dst.first()->is_stack()) {
duke@0 1541 // stack to stack the easiest of the bunch
duke@0 1542 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1543 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1544 } else {
duke@0 1545 // stack to reg
duke@0 1546 if (dst.first()->is_Register()) {
duke@0 1547 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1548 } else {
duke@0 1549 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1550 }
duke@0 1551 }
duke@0 1552 } else if (dst.first()->is_stack()) {
duke@0 1553 // reg to stack
duke@0 1554 if (src.first()->is_Register()) {
duke@0 1555 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1556 } else {
duke@0 1557 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1558 }
duke@0 1559 } else {
duke@0 1560 // reg to reg
duke@0 1561 if (src.first()->is_Register()) {
duke@0 1562 if (dst.first()->is_Register()) {
duke@0 1563 // gpr -> gpr
duke@0 1564 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1565 } else {
duke@0 1566 // gpr -> fpr
duke@0 1567 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1568 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1569 }
duke@0 1570 } else if (dst.first()->is_Register()) {
duke@0 1571 // fpr -> gpr
duke@0 1572 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@0 1573 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@0 1574 } else {
duke@0 1575 // fpr -> fpr
duke@0 1576 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1577 if ( src.first() != dst.first()) {
duke@0 1578 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1579 }
duke@0 1580 }
duke@0 1581 }
duke@0 1582 }
duke@0 1583
duke@0 1584 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1585 VMRegPair src_lo(src.first());
duke@0 1586 VMRegPair src_hi(src.second());
duke@0 1587 VMRegPair dst_lo(dst.first());
duke@0 1588 VMRegPair dst_hi(dst.second());
duke@0 1589 simple_move32(masm, src_lo, dst_lo);
duke@0 1590 simple_move32(masm, src_hi, dst_hi);
duke@0 1591 }
duke@0 1592
duke@0 1593 // A long move
duke@0 1594 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1595
duke@0 1596 // Do the simple ones here else do two int moves
duke@0 1597 if (src.is_single_phys_reg() ) {
duke@0 1598 if (dst.is_single_phys_reg()) {
duke@0 1599 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1600 } else {
duke@0 1601 // split src into two separate registers
duke@0 1602 // Remember hi means hi address or lsw on sparc
duke@0 1603 // Move msw to lsw
duke@0 1604 if (dst.second()->is_reg()) {
duke@0 1605 // MSW -> MSW
duke@0 1606 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@0 1607 // Now LSW -> LSW
duke@0 1608 // this will only move lo -> lo and ignore hi
duke@0 1609 VMRegPair split(dst.second());
duke@0 1610 simple_move32(masm, src, split);
duke@0 1611 } else {
duke@0 1612 VMRegPair split(src.first(), L4->as_VMReg());
duke@0 1613 // MSW -> MSW (lo ie. first word)
duke@0 1614 __ srax(src.first()->as_Register(), 32, L4);
duke@0 1615 split_long_move(masm, split, dst);
duke@0 1616 }
duke@0 1617 }
duke@0 1618 } else if (dst.is_single_phys_reg()) {
duke@0 1619 if (src.is_adjacent_aligned_on_stack(2)) {
never@297 1620 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1621 } else {
duke@0 1622 // dst is a single reg.
duke@0 1623 // Remember lo is low address not msb for stack slots
duke@0 1624 // and lo is the "real" register for registers
duke@0 1625 // src is
duke@0 1626
duke@0 1627 VMRegPair split;
duke@0 1628
duke@0 1629 if (src.first()->is_reg()) {
duke@0 1630 // src.lo (msw) is a reg, src.hi is stk/reg
duke@0 1631 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@0 1632 split.set_pair(dst.first(), src.first());
duke@0 1633 } else {
duke@0 1634 // msw is stack move to L5
duke@0 1635 // lsw is stack move to dst.lo (real reg)
duke@0 1636 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@0 1637 split.set_pair(dst.first(), L5->as_VMReg());
duke@0 1638 }
duke@0 1639
duke@0 1640 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@0 1641 // msw -> src.lo/L5, lsw -> dst.lo
duke@0 1642 split_long_move(masm, src, split);
duke@0 1643
duke@0 1644 // So dst now has the low order correct position the
duke@0 1645 // msw half
duke@0 1646 __ sllx(split.first()->as_Register(), 32, L5);
duke@0 1647
duke@0 1648 const Register d = dst.first()->as_Register();
duke@0 1649 __ or3(L5, d, d);
duke@0 1650 }
duke@0 1651 } else {
duke@0 1652 // For LP64 we can probably do better.
duke@0 1653 split_long_move(masm, src, dst);
duke@0 1654 }
duke@0 1655 }
duke@0 1656
duke@0 1657 // A double move
duke@0 1658 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1659
duke@0 1660 // The painful thing here is that like long_move a VMRegPair might be
duke@0 1661 // 1: a single physical register
duke@0 1662 // 2: two physical registers (v8)
duke@0 1663 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@0 1664 // 4: two stack slots
duke@0 1665
duke@0 1666 // Since src is always a java calling convention we know that the src pair
duke@0 1667 // is always either all registers or all stack (and aligned?)
duke@0 1668
duke@0 1669 // in a register [lo] and a stack slot [hi]
duke@0 1670 if (src.first()->is_stack()) {
duke@0 1671 if (dst.first()->is_stack()) {
duke@0 1672 // stack to stack the easiest of the bunch
duke@0 1673 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@0 1674 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1675 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1676 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1677 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1678 } else {
duke@0 1679 // stack to reg
duke@0 1680 if (dst.second()->is_stack()) {
duke@0 1681 // stack -> reg, stack -> stack
duke@0 1682 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1683 if (dst.first()->is_Register()) {
duke@0 1684 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1685 } else {
duke@0 1686 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1687 }
duke@0 1688 // This was missing. (very rare case)
duke@0 1689 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1690 } else {
duke@0 1691 // stack -> reg
duke@0 1692 // Eventually optimize for alignment QQQ
duke@0 1693 if (dst.first()->is_Register()) {
duke@0 1694 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1695 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@0 1696 } else {
duke@0 1697 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1698 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1699 }
duke@0 1700 }
duke@0 1701 }
duke@0 1702 } else if (dst.first()->is_stack()) {
duke@0 1703 // reg to stack
duke@0 1704 if (src.first()->is_Register()) {
duke@0 1705 // Eventually optimize for alignment QQQ
duke@0 1706 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1707 if (src.second()->is_stack()) {
duke@0 1708 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1709 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1710 } else {
duke@0 1711 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1712 }
duke@0 1713 } else {
duke@0 1714 // fpr to stack
duke@0 1715 if (src.second()->is_stack()) {
duke@0 1716 ShouldNotReachHere();
duke@0 1717 } else {
duke@0 1718 // Is the stack aligned?
duke@0 1719 if (reg2offset(dst.first()) & 0x7) {
duke@0 1720 // No do as pairs
duke@0 1721 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1722 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1723 } else {
duke@0 1724 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1725 }
duke@0 1726 }
duke@0 1727 }
duke@0 1728 } else {
duke@0 1729 // reg to reg
duke@0 1730 if (src.first()->is_Register()) {
duke@0 1731 if (dst.first()->is_Register()) {
duke@0 1732 // gpr -> gpr
duke@0 1733 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1734 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@0 1735 } else {
duke@0 1736 // gpr -> fpr
duke@0 1737 // ought to be able to do a single store
duke@0 1738 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@0 1739 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1740 // ought to be able to do a single load
duke@0 1741 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1742 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1743 }
duke@0 1744 } else if (dst.first()->is_Register()) {
duke@0 1745 // fpr -> gpr
duke@0 1746 // ought to be able to do a single store
duke@0 1747 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@0 1748 // ought to be able to do a single load
duke@0 1749 // REMEMBER first() is low address not LSB
duke@0 1750 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@0 1751 if (dst.second()->is_Register()) {
duke@0 1752 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@0 1753 } else {
duke@0 1754 __ ld(FP, -4 + STACK_BIAS, L4);
duke@0 1755 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1756 }
duke@0 1757 } else {
duke@0 1758 // fpr -> fpr
duke@0 1759 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1760 if ( src.first() != dst.first()) {
duke@0 1761 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1762 }
duke@0 1763 }
duke@0 1764 }
duke@0 1765 }
duke@0 1766
duke@0 1767 // Creates an inner frame if one hasn't already been created, and
duke@0 1768 // saves a copy of the thread in L7_thread_cache
duke@0 1769 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@0 1770 if (!*already_created) {
duke@0 1771 __ save_frame(0);
duke@0 1772 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@0 1773 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@0 1774 // copy
duke@0 1775 __ mov(G2_thread, L7_thread_cache);
duke@0 1776 *already_created = true;
duke@0 1777 }
duke@0 1778 }
duke@0 1779
never@3064 1780
never@3064 1781 static void save_or_restore_arguments(MacroAssembler* masm,
never@3064 1782 const int stack_slots,
never@3064 1783 const int total_in_args,
never@3064 1784 const int arg_save_area,
never@3064 1785 OopMap* map,
never@3064 1786 VMRegPair* in_regs,
never@3064 1787 BasicType* in_sig_bt) {
never@3064 1788 // if map is non-NULL then the code should store the values,
never@3064 1789 // otherwise it should load them.
never@3064 1790 if (map != NULL) {
never@3064 1791 // Fill in the map
never@3064 1792 for (int i = 0; i < total_in_args; i++) {
never@3064 1793 if (in_sig_bt[i] == T_ARRAY) {
never@3064 1794 if (in_regs[i].first()->is_stack()) {
never@3064 1795 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
never@3064 1796 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
never@3064 1797 } else if (in_regs[i].first()->is_Register()) {
never@3064 1798 map->set_oop(in_regs[i].first());
never@3064 1799 } else {
never@3064 1800 ShouldNotReachHere();
never@3064 1801 }
never@3064 1802 }
never@3064 1803 }
never@3064 1804 }
never@3064 1805
never@3064 1806 // Save or restore double word values
never@3064 1807 int handle_index = 0;
never@3064 1808 for (int i = 0; i < total_in_args; i++) {
never@3064 1809 int slot = handle_index + arg_save_area;
never@3064 1810 int offset = slot * VMRegImpl::stack_slot_size;
never@3064 1811 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) {
never@3064 1812 const Register reg = in_regs[i].first()->as_Register();
never@3064 1813 if (reg->is_global()) {
never@3064 1814 handle_index += 2;
never@3064 1815 assert(handle_index <= stack_slots, "overflow");
never@3064 1816 if (map != NULL) {
never@3064 1817 __ stx(reg, SP, offset + STACK_BIAS);
never@3064 1818 } else {
never@3064 1819 __ ldx(SP, offset + STACK_BIAS, reg);
never@3064 1820 }
never@3064 1821 }
never@3064 1822 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) {
never@3064 1823 handle_index += 2;
never@3064 1824 assert(handle_index <= stack_slots, "overflow");
never@3064 1825 if (map != NULL) {
never@3064 1826 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3064 1827 } else {
never@3064 1828 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3064 1829 }
never@3064 1830 }
never@3064 1831 }
never@3064 1832 // Save floats
never@3064 1833 for (int i = 0; i < total_in_args; i++) {
never@3064 1834 int slot = handle_index + arg_save_area;
never@3064 1835 int offset = slot * VMRegImpl::stack_slot_size;
never@3064 1836 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) {
never@3064 1837 handle_index++;
never@3064 1838 assert(handle_index <= stack_slots, "overflow");
never@3064 1839 if (map != NULL) {
never@3064 1840 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3064 1841 } else {
never@3064 1842 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3064 1843 }
never@3064 1844 }
never@3064 1845 }
never@3064 1846
never@3064 1847 }
never@3064 1848
never@3064 1849
never@3064 1850 // Check GC_locker::needs_gc and enter the runtime if it's true. This
never@3064 1851 // keeps a new JNI critical region from starting until a GC has been
never@3064 1852 // forced. Save down any oops in registers and describe them in an
never@3064 1853 // OopMap.
never@3064 1854 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
never@3064 1855 const int stack_slots,
never@3064 1856 const int total_in_args,
never@3064 1857 const int arg_save_area,
never@3064 1858 OopMapSet* oop_maps,
never@3064 1859 VMRegPair* in_regs,
never@3064 1860 BasicType* in_sig_bt) {
never@3064 1861 __ block_comment("check GC_locker::needs_gc");
never@3064 1862 Label cont;
never@3064 1863 AddressLiteral sync_state(GC_locker::needs_gc_address());
never@3064 1864 __ load_bool_contents(sync_state, G3_scratch);
never@3064 1865 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont);
never@3064 1866 __ delayed()->nop();
never@3064 1867
never@3064 1868 // Save down any values that are live in registers and call into the
never@3064 1869 // runtime to halt for a GC
never@3064 1870 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3064 1871 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1872 arg_save_area, map, in_regs, in_sig_bt);
never@3064 1873
never@3064 1874 __ mov(G2_thread, L7_thread_cache);
never@3064 1875
never@3064 1876 __ set_last_Java_frame(SP, noreg);
never@3064 1877
never@3064 1878 __ block_comment("block_for_jni_critical");
never@3064 1879 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type);
never@3064 1880 __ delayed()->mov(L7_thread_cache, O0);
never@3064 1881 oop_maps->add_gc_map( __ offset(), map);
never@3064 1882
never@3064 1883 __ restore_thread(L7_thread_cache); // restore G2_thread
never@3064 1884 __ reset_last_Java_frame();
never@3064 1885
never@3064 1886 // Reload all the register arguments
never@3064 1887 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1888 arg_save_area, NULL, in_regs, in_sig_bt);
never@3064 1889
never@3064 1890 __ bind(cont);
never@3064 1891 #ifdef ASSERT
never@3064 1892 if (StressCriticalJNINatives) {
never@3064 1893 // Stress register saving
never@3064 1894 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3064 1895 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1896 arg_save_area, map, in_regs, in_sig_bt);
never@3064 1897 // Destroy argument registers
never@3064 1898 for (int i = 0; i < total_in_args; i++) {
never@3064 1899 if (in_regs[i].first()->is_Register()) {
never@3064 1900 const Register reg = in_regs[i].first()->as_Register();
never@3064 1901 if (reg->is_global()) {
never@3064 1902 __ mov(G0, reg);
never@3064 1903 }
never@3064 1904 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3064 1905 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister());
never@3064 1906 }
never@3064 1907 }
never@3064 1908
never@3064 1909 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1910 arg_save_area, NULL, in_regs, in_sig_bt);
never@3064 1911 }
never@3064 1912 #endif
never@3064 1913 }
never@3064 1914
never@3064 1915 // Unpack an array argument into a pointer to the body and the length
never@3064 1916 // if the array is non-null, otherwise pass 0 for both.
never@3064 1917 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
never@3064 1918 // Pass the length, ptr pair
never@3064 1919 Label is_null, done;
never@3064 1920 if (reg.first()->is_stack()) {
never@3064 1921 VMRegPair tmp = reg64_to_VMRegPair(L2);
never@3064 1922 // Load the arg up from the stack
never@3064 1923 move_ptr(masm, reg, tmp);
never@3064 1924 reg = tmp;
never@3064 1925 }
never@3064 1926 __ cmp(reg.first()->as_Register(), G0);
never@3064 1927 __ brx(Assembler::equal, false, Assembler::pt, is_null);
never@3064 1928 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4);
never@3064 1929 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg);
never@3064 1930 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4);
never@3064 1931 move32_64(masm, reg64_to_VMRegPair(L4), length_arg);
never@3064 1932 __ ba_short(done);
never@3064 1933 __ bind(is_null);
never@3064 1934 // Pass zeros
never@3064 1935 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg);
never@3064 1936 move32_64(masm, reg64_to_VMRegPair(G0), length_arg);
never@3064 1937 __ bind(done);
never@3064 1938 }
never@3064 1939
duke@0 1940 // ---------------------------------------------------------------------------
duke@0 1941 // Generate a native wrapper for a given method. The method takes arguments
duke@0 1942 // in the Java compiled code convention, marshals them to the native
duke@0 1943 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@0 1944 // returns to java state (possibly blocking), unhandlizes any result and
duke@0 1945 // returns.
duke@0 1946 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@0 1947 methodHandle method,
twisti@2244 1948 int compile_id,
duke@0 1949 int total_in_args,
duke@0 1950 int comp_args_on_stack, // in VMRegStackSlots
duke@0 1951 BasicType *in_sig_bt,
duke@0 1952 VMRegPair *in_regs,
duke@0 1953 BasicType ret_type) {
never@3064 1954 bool is_critical_native = true;
never@3064 1955 address native_func = method->critical_native_function();
never@3064 1956 if (native_func == NULL) {
never@3064 1957 native_func = method->native_function();
never@3064 1958 is_critical_native = false;
never@3064 1959 }
never@3064 1960 assert(native_func != NULL, "must have function");
duke@0 1961
duke@0 1962 // Native nmethod wrappers never take possesion of the oop arguments.
duke@0 1963 // So the caller will gc the arguments. The only thing we need an
duke@0 1964 // oopMap for is if the call is static
duke@0 1965 //
duke@0 1966 // An OopMap for lock (and class if static), and one for the VM call itself
duke@0 1967 OopMapSet *oop_maps = new OopMapSet();
duke@0 1968 intptr_t start = (intptr_t)__ pc();
duke@0 1969
duke@0 1970 // First thing make an ic check to see if we should even be here
duke@0 1971 {
duke@0 1972 Label L;
duke@0 1973 const Register temp_reg = G3_scratch;
twisti@720 1974 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1975 __ verify_oop(O0);
coleenp@108 1976 __ load_klass(O0, temp_reg);
kvn@2600 1977 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
duke@0 1978
twisti@720 1979 __ jump_to(ic_miss, temp_reg);
duke@0 1980 __ delayed()->nop();
duke@0 1981 __ align(CodeEntryAlignment);
duke@0 1982 __ bind(L);
duke@0 1983 }
duke@0 1984
duke@0 1985 int vep_offset = ((intptr_t)__ pc()) - start;
duke@0 1986
duke@0 1987 #ifdef COMPILER1
duke@0 1988 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@0 1989 // Object.hashCode can pull the hashCode from the header word
duke@0 1990 // instead of doing a full VM transition once it's been computed.
duke@0 1991 // Since hashCode is usually polymorphic at call sites we can't do
duke@0 1992 // this optimization at the call site without a lot of work.
duke@0 1993 Label slowCase;
duke@0 1994 Register receiver = O0;
duke@0 1995 Register result = O0;
duke@0 1996 Register header = G3_scratch;
duke@0 1997 Register hash = G3_scratch; // overwrite header value with hash value
duke@0 1998 Register mask = G1; // to get hash field from header
duke@0 1999
duke@0 2000 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@0 2001 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@0 2002 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@0 2003 // vm: see markOop.hpp.
duke@0 2004 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@0 2005 __ sethi(markOopDesc::hash_mask, mask);
duke@0 2006 __ btst(markOopDesc::unlocked_value, header);
duke@0 2007 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@0 2008 if (UseBiasedLocking) {
duke@0 2009 // Check if biased and fall through to runtime if so
duke@0 2010 __ delayed()->nop();
duke@0 2011 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@0 2012 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@0 2013 }
duke@0 2014 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@0 2015
duke@0 2016 // Check for a valid (non-zero) hash code and get its value.
duke@0 2017 #ifdef _LP64
duke@0 2018 __ srlx(header, markOopDesc::hash_shift, hash);
duke@0 2019 #else
duke@0 2020 __ srl(header, markOopDesc::hash_shift, hash);
duke@0 2021 #endif
duke@0 2022 __ andcc(hash, mask, hash);
duke@0 2023 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@0 2024 __ delayed()->nop();
duke@0 2025
duke@0 2026 // leaf return.
duke@0 2027 __ retl();
duke@0 2028 __ delayed()->mov(hash, result);
duke@0 2029 __ bind(slowCase);
duke@0 2030 }
duke@0 2031 #endif // COMPILER1
duke@0 2032
duke@0 2033
duke@0 2034 // We have received a description of where all the java arg are located
duke@0 2035 // on entry to the wrapper. We need to convert these args to where
duke@0 2036 // the jni function will expect them. To figure out where they go
duke@0 2037 // we convert the java signature to a C signature by inserting
duke@0 2038 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@0 2039
never@3064 2040 int total_c_args = total_in_args;
never@3064 2041 int total_save_slots = 6 * VMRegImpl::slots_per_word;
never@3064 2042 if (!is_critical_native) {
never@3064 2043 total_c_args += 1;
never@3064 2044 if (method->is_static()) {
never@3064 2045 total_c_args++;
never@3064 2046 }
never@3064 2047 } else {
never@3064 2048 for (int i = 0; i < total_in_args; i++) {
never@3064 2049 if (in_sig_bt[i] == T_ARRAY) {
never@3064 2050 // These have to be saved and restored across the safepoint
never@3064 2051 total_c_args++;
never@3064 2052 }
never@3064 2053 }
duke@0 2054 }
duke@0 2055
duke@0 2056 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
never@3064 2057 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
never@3064 2058 BasicType* in_elem_bt = NULL;
duke@0 2059
duke@0 2060 int argc = 0;
never@3064 2061 if (!is_critical_native) {
never@3064 2062 out_sig_bt[argc++] = T_ADDRESS;
never@3064 2063 if (method->is_static()) {
never@3064 2064 out_sig_bt[argc++] = T_OBJECT;
never@3064 2065 }
never@3064 2066
never@3064 2067 for (int i = 0; i < total_in_args ; i++ ) {
never@3064 2068 out_sig_bt[argc++] = in_sig_bt[i];
never@3064 2069 }
never@3064 2070 } else {
never@3064 2071 Thread* THREAD = Thread::current();
never@3064 2072 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
never@3064 2073 SignatureStream ss(method->signature());
never@3064 2074 for (int i = 0; i < total_in_args ; i++ ) {
never@3064 2075 if (in_sig_bt[i] == T_ARRAY) {
never@3064 2076 // Arrays are passed as int, elem* pair
never@3064 2077 out_sig_bt[argc++] = T_INT;
never@3064 2078 out_sig_bt[argc++] = T_ADDRESS;
never@3064 2079 Symbol* atype = ss.as_symbol(CHECK_NULL);
never@3064 2080 const char* at = atype->as_C_string();
never@3064 2081 if (strlen(at) == 2) {
never@3064 2082 assert(at[0] == '[', "must be");
never@3064 2083 switch (at[1]) {
never@3064 2084 case 'B': in_elem_bt[i] = T_BYTE; break;
never@3064 2085 case 'C': in_elem_bt[i] = T_CHAR; break;
never@3064 2086 case 'D': in_elem_bt[i] = T_DOUBLE; break;
never@3064 2087 case 'F': in_elem_bt[i] = T_FLOAT; break;
never@3064 2088 case 'I': in_elem_bt[i] = T_INT; break;
never@3064 2089 case 'J': in_elem_bt[i] = T_LONG; break;
never@3064 2090 case 'S': in_elem_bt[i] = T_SHORT; break;
never@3064 2091 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
never@3064 2092 default: ShouldNotReachHere();
never@3064 2093 }
never@3064 2094 }
never@3064 2095 } else {
never@3064 2096 out_sig_bt[argc++] = in_sig_bt[i];
never@3064 2097 in_elem_bt[i] = T_VOID;
never@3064 2098 }
never@3064 2099 if (in_sig_bt[i] != T_VOID) {
never@3064 2100 assert(in_sig_bt[i] == ss.type(), "must match");
never@3064 2101 ss.next();
never@3064 2102 }
never@3064 2103 }
duke@0 2104 }
duke@0 2105
duke@0 2106 // Now figure out where the args must be stored and how much stack space
duke@0 2107 // they require (neglecting out_preserve_stack_slots but space for storing
duke@0 2108 // the 1st six register arguments). It's weird see int_stk_helper.
duke@0 2109 //
duke@0 2110 int out_arg_slots;
duke@0 2111 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@0 2112
never@3064 2113 if (is_critical_native) {
never@3064 2114 // Critical natives may have to call out so they need a save area
never@3064 2115 // for register arguments.
never@3064 2116 int double_slots = 0;
never@3064 2117 int single_slots = 0;
never@3064 2118 for ( int i = 0; i < total_in_args; i++) {
never@3064 2119 if (in_regs[i].first()->is_Register()) {
never@3064 2120 const Register reg = in_regs[i].first()->as_Register();
never@3064 2121 switch (in_sig_bt[i]) {
never@3064 2122 case T_ARRAY:
never@3064 2123 case T_BOOLEAN:
never@3064 2124 case T_BYTE:
never@3064 2125 case T_SHORT:
never@3064 2126 case T_CHAR:
never@3064 2127 case T_INT: assert(reg->is_in(), "don't need to save these"); break;
never@3064 2128 case T_LONG: if (reg->is_global()) double_slots++; break;
never@3064 2129 default: ShouldNotReachHere();
never@3064 2130 }
never@3064 2131 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3064 2132 switch (in_sig_bt[i]) {
never@3064 2133 case T_FLOAT: single_slots++; break;
never@3064 2134 case T_DOUBLE: double_slots++; break;
never@3064 2135 default: ShouldNotReachHere();
never@3064 2136 }
never@3064 2137 }
never@3064 2138 }
never@3064 2139 total_save_slots = double_slots * 2 + single_slots;
never@3064 2140 }
never@3064 2141
duke@0 2142 // Compute framesize for the wrapper. We need to handlize all oops in
duke@0 2143 // registers. We must create space for them here that is disjoint from
duke@0 2144 // the windowed save area because we have no control over when we might
duke@0 2145 // flush the window again and overwrite values that gc has since modified.
duke@0 2146 // (The live window race)
duke@0 2147 //
duke@0 2148 // We always just allocate 6 word for storing down these object. This allow
duke@0 2149 // us to simply record the base and use the Ireg number to decide which
duke@0 2150 // slot to use. (Note that the reg number is the inbound number not the
duke@0 2151 // outbound number).
duke@0 2152 // We must shuffle args to match the native convention, and include var-args space.
duke@0 2153
duke@0 2154 // Calculate the total number of stack slots we will need.
duke@0 2155
duke@0 2156 // First count the abi requirement plus all of the outgoing args
duke@0 2157 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@0 2158
duke@0 2159 // Now the space for the inbound oop handle area
duke@0 2160
never@3064 2161 int oop_handle_offset = round_to(stack_slots, 2);
never@3064 2162 stack_slots += total_save_slots;
duke@0 2163
duke@0 2164 // Now any space we need for handlizing a klass if static method
duke@0 2165
duke@0 2166 int klass_slot_offset = 0;
duke@0 2167 int klass_offset = -1;
duke@0 2168 int lock_slot_offset = 0;
duke@0 2169 bool is_static = false;
duke@0 2170
duke@0 2171 if (method->is_static()) {
duke@0 2172 klass_slot_offset = stack_slots;
duke@0 2173 stack_slots += VMRegImpl::slots_per_word;
duke@0 2174 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@0 2175 is_static = true;
duke@0 2176 }
duke@0 2177
duke@0 2178 // Plus a lock if needed
duke@0 2179
duke@0 2180 if (method->is_synchronized()) {
duke@0 2181 lock_slot_offset = stack_slots;
duke@0 2182 stack_slots += VMRegImpl::slots_per_word;
duke@0 2183 }
duke@0 2184
duke@0 2185 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@0 2186 stack_slots += 2;
duke@0 2187
duke@0 2188 // Ok The space we have allocated will look like:
duke@0 2189 //
duke@0 2190 //
duke@0 2191 // FP-> | |
duke@0 2192 // |---------------------|
duke@0 2193 // | 2 slots for moves |
duke@0 2194 // |---------------------|
duke@0 2195 // | lock box (if sync) |
duke@0 2196 // |---------------------| <- lock_slot_offset
duke@0 2197 // | klass (if static) |
duke@0 2198 // |---------------------| <- klass_slot_offset
duke@0 2199 // | oopHandle area |
duke@0 2200 // |---------------------| <- oop_handle_offset
duke@0 2201 // | outbound memory |
duke@0 2202 // | based arguments |
duke@0 2203 // | |
duke@0 2204 // |---------------------|
duke@0 2205 // | vararg area |
duke@0 2206 // |---------------------|
duke@0 2207 // | |
duke@0 2208 // SP-> | out_preserved_slots |
duke@0 2209 //
duke@0 2210 //
duke@0 2211
duke@0 2212
duke@0 2213 // Now compute actual number of stack words we need rounding to make
duke@0 2214 // stack properly aligned.
duke@0 2215 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@0 2216
duke@0 2217 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@0 2218
duke@0 2219 // Generate stack overflow check before creating frame
duke@0 2220 __ generate_stack_overflow_check(stack_size);
duke@0 2221
duke@0 2222 // Generate a new frame for the wrapper.
duke@0 2223 __ save(SP, -stack_size, SP);
duke@0 2224
duke@0 2225 int frame_complete = ((intptr_t)__ pc()) - start;
duke@0 2226
duke@0 2227 __ verify_thread();
duke@0 2228
never@3064 2229 if (is_critical_native) {
never@3064 2230 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args,
never@3064 2231 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
never@3064 2232 }
duke@0 2233
duke@0 2234 //
duke@0 2235 // We immediately shuffle the arguments so that any vm call we have to
duke@0 2236 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@0 2237 // captured the oops from our caller and have a valid oopMap for
duke@0 2238 // them.
duke@0 2239
duke@0 2240 // -----------------
duke@0 2241 // The Grand Shuffle
duke@0 2242 //
duke@0 2243 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@0 2244 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@0 2245 // the class mirror instead of a receiver. This pretty much guarantees that
duke@0 2246 // register layout will not match. We ignore these extra arguments during
duke@0 2247 // the shuffle. The shuffle is described by the two calling convention
duke@0 2248 // vectors we have in our possession. We simply walk the java vector to
duke@0 2249 // get the source locations and the c vector to get the destinations.
duke@0 2250 // Because we have a new window and the argument registers are completely
duke@0 2251 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@0 2252 // here.
duke@0 2253
duke@0 2254 // This is a trick. We double the stack slots so we can claim
duke@0 2255 // the oops in the caller's frame. Since we are sure to have
duke@0 2256 // more args than the caller doubling is enough to make
duke@0 2257 // sure we can capture all the incoming oop args from the
duke@0 2258 // caller.
duke@0 2259 //
duke@0 2260 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@0 2261 // Record sp-based slot for receiver on stack for non-static methods
duke@0 2262 int receiver_offset = -1;
duke@0 2263
duke@0 2264 // We move the arguments backward because the floating point registers
duke@0 2265 // destination will always be to a register with a greater or equal register
duke@0 2266 // number or the stack.
duke@0 2267
duke@0 2268 #ifdef ASSERT
duke@0 2269 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@0 2270 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@0 2271 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@0 2272 reg_destroyed[r] = false;
duke@0 2273 }
duke@0 2274 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@0 2275 freg_destroyed[f] = false;
duke@0 2276 }
duke@0 2277
duke@0 2278 #endif /* ASSERT */
duke@0 2279
never@3064 2280 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@0 2281
duke@0 2282 #ifdef ASSERT
duke@0 2283 if (in_regs[i].first()->is_Register()) {
duke@0 2284 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@0 2285 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@0 2286 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@0 2287 }
duke@0 2288 if (out_regs[c_arg].first()->is_Register()) {
duke@0 2289 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@0 2290 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@0 2291 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@0 2292 }
duke@0 2293 #endif /* ASSERT */
duke@0 2294
duke@0 2295 switch (in_sig_bt[i]) {
duke@0 2296 case T_ARRAY:
never@3064 2297 if (is_critical_native) {
never@3064 2298 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]);
never@3064 2299 c_arg--;
never@3064 2300 break;
never@3064 2301 }
duke@0 2302 case T_OBJECT:
never@3064 2303 assert(!is_critical_native, "no oop arguments");
duke@0 2304 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@0 2305 ((i == 0) && (!is_static)),
duke@0 2306 &receiver_offset);
duke@0 2307 break;
duke@0 2308 case T_VOID:
duke@0 2309 break;
duke@0 2310
duke@0 2311 case T_FLOAT:
duke@0 2312 float_move(masm, in_regs[i], out_regs[c_arg]);
never@3064 2313 break;
duke@0 2314
duke@0 2315 case T_DOUBLE:
duke@0 2316 assert( i + 1 < total_in_args &&
duke@0 2317 in_sig_bt[i + 1] == T_VOID &&
duke@0 2318 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@0 2319 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2320 break;
duke@0 2321
duke@0 2322 case T_LONG :
duke@0 2323 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2324 break;
duke@0 2325
duke@0 2326 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@0 2327
duke@0 2328 default:
duke@0 2329 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@0 2330 }
duke@0 2331 }
duke@0 2332
duke@0 2333 // Pre-load a static method's oop into O1. Used both by locking code and
duke@0 2334 // the normal JNI call code.
never@3064 2335 if (method->is_static() && !is_critical_native) {
duke@0 2336 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@0 2337
duke@0 2338 // Now handlize the static class mirror in O1. It's known not-null.
duke@0 2339 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@0 2340 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@0 2341 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@0 2342 }
duke@0 2343
duke@0 2344
duke@0 2345 const Register L6_handle = L6;
duke@0 2346
duke@0 2347 if (method->is_synchronized()) {
never@3064 2348 assert(!is_critical_native, "unhandled");
duke@0 2349 __ mov(O1, L6_handle);
duke@0 2350 }
duke@0 2351
duke@0 2352 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@0 2353 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@0 2354 // push a new frame and flush the windows.
duke@0 2355 #ifdef _LP64
duke@0 2356 intptr_t thepc = (intptr_t) __ pc();
duke@0 2357 {
duke@0 2358 address here = __ pc();
duke@0 2359 // Call the next instruction
duke@0 2360 __ call(here + 8, relocInfo::none);
duke@0 2361 __ delayed()->nop();
duke@0 2362 }
duke@0 2363 #else
duke@0 2364 intptr_t thepc = __ load_pc_address(O7, 0);
duke@0 2365 #endif /* _LP64 */
duke@0 2366
duke@0 2367 // We use the same pc/oopMap repeatedly when we call out
duke@0 2368 oop_maps->add_gc_map(thepc - start, map);
duke@0 2369
duke@0 2370 // O7 now has the pc loaded that we will use when we finally call to native.
duke@0 2371
duke@0 2372 // Save thread in L7; it crosses a bunch of VM calls below
duke@0 2373 // Don't use save_thread because it smashes G2 and we merely
duke@0 2374 // want to save a copy
duke@0 2375 __ mov(G2_thread, L7_thread_cache);
duke@0 2376
duke@0 2377
duke@0 2378 // If we create an inner frame once is plenty
duke@0 2379 // when we create it we must also save G2_thread
duke@0 2380 bool inner_frame_created = false;
duke@0 2381
duke@0 2382 // dtrace method entry support
duke@0 2383 {
duke@0 2384 SkipIfEqual skip_if(
duke@0 2385 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2386 // create inner frame
duke@0 2387 __ save_frame(0);
duke@0 2388 __ mov(G2_thread, L7_thread_cache);
duke@0 2389 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2390 __ call_VM_leaf(L7_thread_cache,
duke@0 2391 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@0 2392 G2_thread, O1);
duke@0 2393 __ restore();
duke@0 2394 }
duke@0 2395
dcubed@606 2396 // RedefineClasses() tracing support for obsolete method entry
dcubed@606 2397 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
dcubed@606 2398 // create inner frame
dcubed@606 2399 __ save_frame(0);
dcubed@606 2400 __ mov(G2_thread, L7_thread_cache);
dcubed@606 2401 __ set_oop_constant(JNIHandles::make_local(method()), O1);
dcubed@606 2402 __ call_VM_leaf(L7_thread_cache,
dcubed@606 2403 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
dcubed@606 2404 G2_thread, O1);
dcubed@606 2405 __ restore();
dcubed@606 2406 }
dcubed@606 2407
duke@0 2408 // We are in the jni frame unless saved_frame is true in which case
duke@0 2409 // we are in one frame deeper (the "inner" frame). If we are in the
duke@0 2410 // "inner" frames the args are in the Iregs and if the jni frame then
duke@0 2411 // they are in the Oregs.
duke@0 2412 // If we ever need to go to the VM (for locking, jvmti) then
duke@0 2413 // we will always be in the "inner" frame.
duke@0 2414
duke@0 2415 // Lock a synchronized method
duke@0 2416 int lock_offset = -1; // Set if locked
duke@0 2417 if (method->is_synchronized()) {
duke@0 2418 Register Roop = O1;
duke@0 2419 const Register L3_box = L3;
duke@0 2420
duke@0 2421 create_inner_frame(masm, &inner_frame_created);
duke@0 2422
duke@0 2423 __ ld_ptr(I1, 0, O1);
duke@0 2424 Label done;
duke@0 2425
duke@0 2426 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@0 2427 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2428 #ifdef ASSERT
duke@0 2429 if (UseBiasedLocking) {
duke@0 2430 // making the box point to itself will make it clear it went unused
duke@0 2431 // but also be obviously invalid
duke@0 2432 __ st_ptr(L3_box, L3_box, 0);
duke@0 2433 }
duke@0 2434 #endif // ASSERT
duke@0 2435 //
duke@0 2436 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@0 2437 //
duke@0 2438 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@0 2439 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2440 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2441
duke@0 2442
duke@0 2443 // None of the above fast optimizations worked so we have to get into the
duke@0 2444 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2445 // disallows any pending_exception.
duke@0 2446 __ mov(Roop, O0); // Need oop in O0
duke@0 2447 __ mov(L3_box, O1);
duke@0 2448
duke@0 2449 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@0 2450
duke@0 2451 __ set_last_Java_frame(FP, I7);
duke@0 2452
duke@0 2453 // do the call
duke@0 2454 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@0 2455 __ delayed()->mov(L7_thread_cache, O2);
duke@0 2456
duke@0 2457 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2458 __ reset_last_Java_frame();
duke@0 2459
duke@0 2460 #ifdef ASSERT
duke@0 2461 { Label L;
duke@0 2462 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2463 __ br_null_short(O0, Assembler::pt, L);
duke@0 2464 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@0 2465 __ bind(L);
duke@0 2466 }
duke@0 2467 #endif
duke@0 2468 __ bind(done);
duke@0 2469 }
duke@0 2470
duke@0 2471
duke@0 2472 // Finally just about ready to make the JNI call
duke@0 2473
duke@0 2474 __ flush_windows();
duke@0 2475 if (inner_frame_created) {
duke@0 2476 __ restore();
duke@0 2477 } else {
duke@0 2478 // Store only what we need from this frame
duke@0 2479 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@0 2480 // either as the flush traps and the current window goes too.
duke@0 2481 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2482 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2483 }
duke@0 2484
duke@0 2485 // get JNIEnv* which is first argument to native
never@3064 2486 if (!is_critical_native) {
never@3064 2487 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
never@3064 2488 }
duke@0 2489
duke@0 2490 // Use that pc we placed in O7 a while back as the current frame anchor
duke@0 2491 __ set_last_Java_frame(SP, O7);
duke@0 2492
never@3064 2493 // We flushed the windows ages ago now mark them as flushed before transitioning.
never@3064 2494 __ set(JavaFrameAnchor::flushed, G3_scratch);
never@3064 2495 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
never@3064 2496
duke@0 2497 // Transition from _thread_in_Java to _thread_in_native.
duke@0 2498 __ set(_thread_in_native, G3_scratch);
duke@0 2499
duke@0 2500 #ifdef _LP64
never@3064 2501 AddressLiteral dest(native_func);
duke@0 2502 __ relocate(relocInfo::runtime_call_type);
twisti@720 2503 __ jumpl_to(dest, O7, O7);
duke@0 2504 #else
never@3064 2505 __ call(native_func, relocInfo::runtime_call_type);
duke@0 2506 #endif
never@3064 2507 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2508
duke@0 2509 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2510
duke@0 2511 // Unpack native results. For int-types, we do any needed sign-extension
duke@0 2512 // and move things into I0. The return value there will survive any VM
duke@0 2513 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@0 2514 // specially in the slow-path code.
duke@0 2515 switch (ret_type) {
duke@0 2516 case T_VOID: break; // Nothing to do!
duke@0 2517 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@0 2518 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@0 2519 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@0 2520 case T_LONG:
duke@0 2521 #ifndef _LP64
duke@0 2522 __ mov(O1, I1);
duke@0 2523 #endif
duke@0 2524 // Fall thru
duke@0 2525 case T_OBJECT: // Really a handle
duke@0 2526 case T_ARRAY:
duke@0 2527 case T_INT:
duke@0 2528 __ mov(O0, I0);
duke@0 2529 break;
duke@0 2530 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@0 2531 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@0 2532 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@0 2533 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@0 2534 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@0 2535 default:
duke@0 2536 ShouldNotReachHere();
duke@0 2537 }
duke@0 2538
never@3064 2539 Label after_transition;
duke@0 2540 // must we block?
duke@0 2541
duke@0 2542 // Block, if necessary, before resuming in _thread_in_Java state.
duke@0 2543 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@0 2544 { Label no_block;
twisti@720 2545 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
duke@0 2546
duke@0 2547 // Switch thread to "native transition" state before reading the synchronization state.
duke@0 2548 // This additional state is necessary because reading and testing the synchronization
duke@0 2549 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@0 2550 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@0 2551 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@0 2552 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@0 2553 // didn't see any synchronization is progress, and escapes.
duke@0 2554 __ set(_thread_in_native_trans, G3_scratch);
twisti@720 2555 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2556 if(os::is_MP()) {
duke@0 2557 if (UseMembar) {
duke@0 2558 // Force this write out before the read below
duke@0 2559 __ membar(Assembler::StoreLoad);
duke@0 2560 } else {
duke@0 2561 // Write serialization page so VM thread can do a pseudo remote membar.
duke@0 2562 // We use the current thread pointer to calculate a thread specific
duke@0 2563 // offset to write to within the page. This minimizes bus traffic
duke@0 2564 // due to cache line collision.
duke@0 2565 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@0 2566 }
duke@0 2567 }
duke@0 2568 __ load_contents(sync_state, G3_scratch);
duke@0 2569 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@0 2570
duke@0 2571 Label L;
twisti@720 2572 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
duke@0 2573 __ br(Assembler::notEqual, false, Assembler::pn, L);
twisti@720 2574 __ delayed()->ld(suspend_state, G3_scratch);
kvn@2600 2575 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
duke@0 2576 __ bind(L);
duke@0 2577
duke@0 2578 // Block. Save any potential method result value before the operation and
duke@0 2579 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@0 2580 // lets us share the oopMap we used when we went native rather the create
duke@0 2581 // a distinct one for this pc
duke@0 2582 //
duke@0 2583 save_native_result(masm, ret_type, stack_slots);
never@3064 2584 if (!is_critical_native) {
never@3064 2585 __ call_VM_leaf(L7_thread_cache,
never@3064 2586 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
never@3064 2587 G2_thread);
never@3064 2588 } else {
never@3064 2589 __ call_VM_leaf(L7_thread_cache,
never@3064 2590 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition),
never@3064 2591 G2_thread);
never@3064 2592 }
duke@0 2593
duke@0 2594 // Restore any method result value
duke@0 2595 restore_native_result(masm, ret_type, stack_slots);
never@3064 2596
never@3064 2597 if (is_critical_native) {
never@3064 2598 // The call above performed the transition to thread_in_Java so
never@3064 2599 // skip the transition logic below.
never@3064 2600 __ ba(after_transition);
never@3064 2601 __ delayed()->nop();
never@3064 2602 }
never@3064 2603
duke@0 2604 __ bind(no_block);
duke@0 2605 }
duke@0 2606
duke@0 2607 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@0 2608 // happened so we can now change state to _thread_in_Java.
duke@0 2609 __ set(_thread_in_Java, G3_scratch);
twisti@720 2610 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
never@3064 2611 __ bind(after_transition);
duke@0 2612
duke@0 2613 Label no_reguard;
twisti@720 2614 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
kvn@2600 2615 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
duke@0 2616
duke@0 2617 save_native_result(masm, ret_type, stack_slots);
duke@0 2618 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@0 2619 __ delayed()->nop();
duke@0 2620
duke@0 2621 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2622 restore_native_result(masm, ret_type, stack_slots);
duke@0 2623
duke@0 2624 __ bind(no_reguard);
duke@0 2625
duke@0 2626 // Handle possible exception (will unlock if necessary)
duke@0 2627
duke@0 2628 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@0 2629
duke@0 2630 // Unlock
duke@0 2631 if (method->is_synchronized()) {
duke@0 2632 Label done;
duke@0 2633 Register I2_ex_oop = I2;
duke@0 2634 const Register L3_box = L3;
duke@0 2635 // Get locked oop from the handle we passed to jni
duke@0 2636 __ ld_ptr(L6_handle, 0, L4);
duke@0 2637 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2638 // Must save pending exception around the slow-path VM call. Since it's a
duke@0 2639 // leaf call, the pending exception (if any) can be kept in a register.
duke@0 2640 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@0 2641 // Now unlock
duke@0 2642 // (Roop, Rmark, Rbox, Rscratch)
duke@0 2643 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@0 2644 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2645 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2646
duke@0 2647 // save and restore any potential method result value around the unlocking
duke@0 2648 // operation. Will save in I0 (or stack for FP returns).
duke@0 2649 save_native_result(masm, ret_type, stack_slots);
duke@0 2650
duke@0 2651 // Must clear pending-exception before re-entering the VM. Since this is
duke@0 2652 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@0 2653 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2654
duke@0 2655 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2656 // disallows any pending_exception.
duke@0 2657 __ mov(L3_box, O1);
duke@0 2658
duke@0 2659 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@0 2660 __ delayed()->mov(L4, O0); // Need oop in O0
duke@0 2661
duke@0 2662 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2663
duke@0 2664 #ifdef ASSERT
duke@0 2665 { Label L;
duke@0 2666 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2667 __ br_null_short(O0, Assembler::pt, L);
duke@0 2668 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@0 2669 __ bind(L);
duke@0 2670 }
duke@0 2671 #endif
duke@0 2672 restore_native_result(masm, ret_type, stack_slots);
duke@0 2673 // check_forward_pending_exception jump to forward_exception if any pending
duke@0 2674 // exception is set. The forward_exception routine expects to see the
duke@0 2675 // exception in pending_exception and not in a register. Kind of clumsy,
duke@0 2676 // since all folks who branch to forward_exception must have tested
duke@0 2677 // pending_exception first and hence have it in a register already.
duke@0 2678 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2679 __ bind(done);
duke@0 2680 }
duke@0 2681
duke@0 2682 // Tell dtrace about this method exit
duke@0 2683 {
duke@0 2684 SkipIfEqual skip_if(
duke@0 2685 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2686 save_native_result(masm, ret_type, stack_slots);
duke@0 2687 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2688 __ call_VM_leaf(L7_thread_cache,
duke@0 2689 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@0 2690 G2_thread, O1);
duke@0 2691 restore_native_result(masm, ret_type, stack_slots);
duke@0 2692 }
duke@0 2693
duke@0 2694 // Clear "last Java frame" SP and PC.
duke@0 2695 __ verify_thread(); // G2_thread must be correct
duke@0 2696 __ reset_last_Java_frame();
duke@0 2697
duke@0 2698 // Unpack oop result
duke@0 2699 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@0 2700 Label L;
duke@0 2701 __ addcc(G0, I0, G0);
duke@0 2702 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@0 2703 __ delayed()->ld_ptr(I0, 0, I0);
duke@0 2704 __ mov(G0, I0);
duke@0 2705 __ bind(L);
duke@0 2706 __ verify_oop(I0);
duke@0 2707 }
duke@0 2708
never@3064 2709 if (!is_critical_native) {
never@3064 2710 // reset handle block
never@3064 2711 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
never@3064 2712 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
never@3064 2713
never@3064 2714 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
never@3064 2715 check_forward_pending_exception(masm, G3_scratch);
never@3064 2716 }
duke@0 2717
duke@0 2718
duke@0 2719 // Return
duke@0 2720
duke@0 2721 #ifndef _LP64
duke@0 2722 if (ret_type == T_LONG) {
duke@0 2723
duke@0 2724 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@0 2725 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 2726 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 2727 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 2728 }
duke@0 2729 #endif
duke@0 2730
duke@0 2731 __ ret();
duke@0 2732 __ delayed()->restore();
duke@0 2733
duke@0 2734 __ flush();
duke@0 2735
duke@0 2736 nmethod *nm = nmethod::new_native_nmethod(method,
twisti@2244 2737 compile_id,
duke@0 2738 masm->code(),
duke@0 2739 vep_offset,
duke@0 2740 frame_complete,
duke@0 2741 stack_slots / VMRegImpl::slots_per_word,
duke@0 2742 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@0 2743 in_ByteSize(lock_offset),
duke@0 2744 oop_maps);
never@3064 2745
never@3064 2746 if (is_critical_native) {
never@3064 2747 nm->set_lazy_critical_native(true);
never@3064 2748 }
duke@0 2749 return nm;
duke@0 2750
duke@0 2751 }
duke@0 2752
kamg@124 2753 #ifdef HAVE_DTRACE_H
kamg@124 2754 // ---------------------------------------------------------------------------
kamg@124 2755 // Generate a dtrace nmethod for a given signature. The method takes arguments
kamg@124 2756 // in the Java compiled code convention, marshals them to the native
kamg@124 2757 // abi and then leaves nops at the position you would expect to call a native
kamg@124 2758 // function. When the probe is enabled the nops are replaced with a trap
kamg@124 2759 // instruction that dtrace inserts and the trace will cause a notification
kamg@124 2760 // to dtrace.
kamg@124 2761 //
kamg@124 2762 // The probes are only able to take primitive types and java/lang/String as
kamg@124 2763 // arguments. No other java types are allowed. Strings are converted to utf8
kamg@124 2764 // strings so that from dtrace point of view java strings are converted to C
kamg@124 2765 // strings. There is an arbitrary fixed limit on the total space that a method
kamg@124 2766 // can use for converting the strings. (256 chars per string in the signature).
kamg@124 2767 // So any java string larger then this is truncated.
kamg@124 2768
kamg@124 2769 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
kamg@124 2770 static bool offsets_initialized = false;
kamg@124 2771
kamg@124 2772 nmethod *SharedRuntime::generate_dtrace_nmethod(
kamg@124 2773 MacroAssembler *masm, methodHandle method) {
kamg@124 2774
kamg@124 2775
kamg@124 2776 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
kamg@124 2777 // be single threaded in this method.
kamg@124 2778 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
kamg@124 2779
kamg@124 2780 // Fill in the signature array, for the calling-convention call.
kamg@124 2781 int total_args_passed = method->size_of_parameters();
kamg@124 2782
kamg@124 2783 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
kamg@124 2784 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
kamg@124 2785
kamg@124 2786 // The signature we are going to use for the trap that dtrace will see
kamg@124 2787 // java/lang/String is converted. We drop "this" and any other object
kamg@124 2788 // is converted to NULL. (A one-slot java/lang/Long object reference
kamg@124 2789 // is converted to a two-slot long, which is why we double the allocation).
kamg@124 2790 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
kamg@124 2791 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
kamg@124 2792
kamg@124 2793 int i=0;
kamg@124 2794 int total_strings = 0;
kamg@124 2795 int first_arg_to_pass = 0;
kamg@124 2796 int total_c_args = 0;
kamg@124 2797
kamg@124 2798 // Skip the receiver as dtrace doesn't want to see it
kamg@124 2799 if( !method->is_static() ) {
kamg@124 2800 in_sig_bt[i++] = T_OBJECT;
kamg@124 2801 first_arg_to_pass = 1;
kamg@124 2802 }
kamg@124 2803
kamg@124 2804 SignatureStream ss(method->signature());
kamg@124 2805 for ( ; !ss.at_return_type(); ss.next()) {
kamg@124 2806 BasicType bt = ss.type();
kamg@124 2807 in_sig_bt[i++] = bt; // Collect remaining bits of signature
kamg@124 2808 out_sig_bt[total_c_args++] = bt;
kamg@124 2809 if( bt == T_OBJECT) {
coleenp@2059 2810 Symbol* s = ss.as_symbol_or_null();
kamg@124 2811 if (s == vmSymbols::java_lang_String()) {
kamg@124 2812 total_strings++;
kamg@124 2813 out_sig_bt[total_c_args-1] = T_ADDRESS;
kamg@124 2814 } else if (s == vmSymbols::java_lang_Boolean() ||
kamg@124 2815 s == vmSymbols::java_lang_Byte()) {
kamg@124 2816 out_sig_bt[total_c_args-1] = T_BYTE;
kamg@124 2817 } else if (s == vmSymbols::java_lang_Character() ||
kamg@124 2818 s == vmSymbols::java_lang_Short()) {
kamg@124 2819 out_sig_bt[total_c_args-1] = T_SHORT;
kamg@124 2820 } else if (s == vmSymbols::java_lang_Integer() ||
kamg@124 2821 s == vmSymbols::java_lang_Float()) {
kamg@124 2822 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2823 } else if (s == vmSymbols::java_lang_Long() ||
kamg@124 2824 s == vmSymbols::java_lang_Double()) {
kamg@124 2825 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2826 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2827 }
kamg@124 2828 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
kamg@124 2829 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
kamg@124 2830 // We convert double to long
kamg@124 2831 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2832 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2833 } else if ( bt == T_FLOAT) {
kamg@124 2834 // We convert float to int
kamg@124 2835 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2836 }
kamg@124 2837 }
kamg@124 2838
kamg@124 2839 assert(i==total_args_passed, "validly parsed signature");
kamg@124 2840
kamg@124 2841 // Now get the compiled-Java layout as input arguments
kamg@124 2842 int comp_args_on_stack;
kamg@124 2843 comp_args_on_stack = SharedRuntime::java_calling_convention(
kamg@124 2844 in_sig_bt, in_regs, total_args_passed, false);
kamg@124 2845
kamg@124 2846 // We have received a description of where all the java arg are located
kamg@124 2847 // on entry to the wrapper. We need to convert these args to where
kamg@124 2848 // the a native (non-jni) function would expect them. To figure out
kamg@124 2849 // where they go we convert the java signature to a C signature and remove
kamg@124 2850 // T_VOID for any long/double we might have received.
kamg@124 2851
kamg@124 2852
kamg@124 2853 // Now figure out where the args must be stored and how much stack space
kamg@124 2854 // they require (neglecting out_preserve_stack_slots but space for storing
kamg@124 2855 // the 1st six register arguments). It's weird see int_stk_helper.
kamg@124 2856 //
kamg@124 2857 int out_arg_slots;
kamg@124 2858 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
kamg@124 2859
kamg@124 2860 // Calculate the total number of stack slots we will need.
kamg@124 2861
kamg@124 2862 // First count the abi requirement plus all of the outgoing args
kamg@124 2863 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
kamg@124 2864
kamg@124 2865 // Plus a temp for possible converion of float/double/long register args
kamg@124 2866
kamg@124 2867 int conversion_temp = stack_slots;
kamg@124 2868 stack_slots += 2;
kamg@124 2869
kamg@124 2870
kamg@124 2871 // Now space for the string(s) we must convert
kamg@124 2872
kamg@124 2873 int string_locs = stack_slots;
kamg@124 2874 stack_slots += total_strings *
kamg@124 2875 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
kamg@124 2876
kamg@124 2877 // Ok The space we have allocated will look like:
kamg@124 2878 //
kamg@124 2879 //
kamg@124 2880 // FP-> | |
kamg@124 2881 // |---------------------|
kamg@124 2882 // | string[n] |
kamg@124 2883 // |---------------------| <- string_locs[n]
kamg@124 2884 // | string[n-1] |
kamg@124 2885 // |---------------------| <- string_locs[n-1]
kamg@124 2886 // | ... |
kamg@124 2887 // | ... |
kamg@124 2888 // |---------------------| <- string_locs[1]
kamg@124 2889 // | string[0] |
kamg@124 2890 // |---------------------| <- string_locs[0]
kamg@124 2891 // | temp |
kamg@124 2892 // |---------------------| <- conversion_temp
kamg@124 2893 // | outbound memory |
kamg@124 2894 // | based arguments |
kamg@124 2895 // | |
kamg@124 2896 // |---------------------|
kamg@124 2897 // | |
kamg@124 2898 // SP-> | out_preserved_slots |
kamg@124 2899 //
kamg@124 2900 //
kamg@124 2901
kamg@124 2902 // Now compute actual number of stack words we need rounding to make
kamg@124 2903 // stack properly aligned.
kamg@124 2904 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
kamg@124 2905
kamg@124 2906 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
kamg@124 2907
kamg@124 2908 intptr_t start = (intptr_t)__ pc();
kamg@124 2909
kamg@124 2910 // First thing make an ic check to see if we should even be here
kamg@124 2911
kamg@124 2912 {
kamg@124 2913 Label L;
kamg@124 2914 const Register temp_reg = G3_scratch;
twisti@720 2915 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
kamg@124 2916 __ verify_oop(O0);
kamg@124 2917 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
kvn@2600 2918 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
kamg@124 2919
twisti@720 2920 __ jump_to(ic_miss, temp_reg);
kamg@124 2921 __ delayed()->nop();
kamg@124 2922 __ align(CodeEntryAlignment);
kamg@124 2923 __ bind(L);
kamg@124 2924 }
kamg@124 2925
kamg@124 2926 int vep_offset = ((intptr_t)__ pc()) - start;
kamg@124 2927
kamg@124 2928
kamg@124 2929 // The instruction at the verified entry point must be 5 bytes or longer
kamg@124 2930 // because it can be patched on the fly by make_non_entrant. The stack bang
kamg@124 2931 // instruction fits that requirement.
kamg@124 2932
kamg@124 2933 // Generate stack overflow check before creating frame
kamg@124 2934 __ generate_stack_overflow_check(stack_size);
kamg@124 2935
kamg@124 2936 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
kamg@124 2937 "valid size for make_non_entrant");
kamg@124 2938
kamg@124 2939 // Generate a new frame for the wrapper.
kamg@124 2940 __ save(SP, -stack_size, SP);
kamg@124 2941
kamg@124 2942 // Frame is now completed as far a size and linkage.
kamg@124 2943
kamg@124 2944 int frame_complete = ((intptr_t)__ pc()) - start;
kamg@124 2945
kamg@124 2946 #ifdef ASSERT
kamg@124 2947 bool reg_destroyed[RegisterImpl::number_of_registers];
kamg@124 2948 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
kamg@124 2949 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
kamg@124 2950 reg_destroyed[r] = false;
kamg@124 2951 }
kamg@124 2952 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
kamg@124 2953 freg_destroyed[f] = false;
kamg@124 2954 }
kamg@124 2955
kamg@124 2956 #endif /* ASSERT */
kamg@124 2957
kamg@124 2958 VMRegPair zero;
kamg@182 2959 const Register g0 = G0; // without this we get a compiler warning (why??)
kamg@182 2960 zero.set2(g0->as_VMReg());
kamg@124 2961
kamg@124 2962 int c_arg, j_arg;
kamg@124 2963
kamg@124 2964 Register conversion_off = noreg;
kamg@124 2965
kamg@124 2966 for (j_arg = first_arg_to_pass, c_arg = 0 ;
kamg@124 2967 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
kamg@124 2968
kamg@124 2969 VMRegPair src = in_regs[j_arg];
kamg@124 2970 VMRegPair dst = out_regs[c_arg];
kamg@124 2971
kamg@124 2972 #ifdef ASSERT
kamg@124 2973 if (src.first()->is_Register()) {
kamg@124 2974 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
kamg@124 2975 } else if (src.first()->is_FloatRegister()) {
kamg@124 2976 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
kamg@124 2977 FloatRegisterImpl::S)], "ack!");
kamg@124 2978 }
kamg@124 2979 if (dst.first()->is_Register()) {
kamg@124 2980 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
kamg@124 2981 } else if (dst.first()->is_FloatRegister()) {
kamg@124 2982 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
kamg@124 2983 FloatRegisterImpl::S)] = true;
kamg@124 2984 }
kamg@124 2985 #endif /* ASSERT */
kamg@124 2986
kamg@124 2987 switch (in_sig_bt[j_arg]) {
kamg@124 2988 case T_ARRAY:
kamg@124 2989 case T_OBJECT:
kamg@124 2990 {
kamg@124 2991 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
kamg@124 2992 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
kamg@124 2993 // need to unbox a one-slot value
kamg@124 2994 Register in_reg = L0;
kamg@124 2995 Register tmp = L2;
kamg@124 2996 if ( src.first()->is_reg() ) {
kamg@124 2997 in_reg = src.first()->as_Register();
kamg@124 2998 } else {
kamg@124 2999 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
kamg@124 3000 "must be");
kamg@124 3001 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
kamg@124 3002 }
kamg@124 3003 // If the final destination is an acceptable register
kamg@124 3004 if ( dst.first()->is_reg() ) {
kamg@124 3005 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
kamg@124 3006 tmp = dst.first()->as_Register();
kamg@124 3007 }
kamg@124 3008 }
kamg@124 3009
kamg@124 3010 Label skipUnbox;
kamg@124 3011 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
kamg@124 3012 __ mov(G0, tmp->successor());
kamg@124 3013 }
kamg@124 3014 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
kamg@124 3015 __ delayed()->mov(G0, tmp);
kamg@124 3016
kvn@153 3017 BasicType bt = out_sig_bt[c_arg];
kvn@153 3018 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
kvn@153 3019 switch (bt) {
kamg@124 3020 case T_BYTE:
kamg@124 3021 __ ldub(in_reg, box_offset, tmp); break;
kamg@124 3022 case T_SHORT:
kamg@124 3023 __ lduh(in_reg, box_offset, tmp); break;
kamg@124 3024 case T_INT:
kamg@124 3025 __ ld(in_reg, box_offset, tmp); break;
kamg@124 3026 case T_LONG:
kamg@124 3027 __ ld_long(in_reg, box_offset, tmp); break;
kamg@124 3028 default: ShouldNotReachHere();
kamg@124 3029 }
kamg@124 3030
kamg@124 3031 __ bind(skipUnbox);
kamg@124 3032 // If tmp wasn't final destination copy to final destination
kamg@124 3033 if (tmp == L2) {
kamg@124 3034 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
kamg@124 3035 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 3036 long_move(masm, tmp_as_VM, dst);
kamg@124 3037 } else {
kamg@124 3038 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
kamg@124 3039 }
kamg@124 3040 }
kamg@124 3041 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 3042 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
kamg@124 3043 ++c_arg; // move over the T_VOID to keep the loop indices in sync
kamg@124 3044 }
kamg@124 3045 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 3046 Register s =
kamg@124 3047 src.first()->is_reg() ? src.first()->as_Register() : L2;
kamg@124 3048 Register d =
kamg@124 3049 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 3050
kamg@124 3051 // We store the oop now so that the conversion pass can reach
kamg@124 3052 // while in the inner frame. This will be the only store if
kamg@124 3053 // the oop is NULL.
kamg@124 3054 if (s != L2) {
kamg@124 3055 // src is register
kamg@124 3056 if (d != L2) {
kamg@124 3057 // dst is register
kamg@124 3058 __ mov(s, d);
kamg@124 3059 } else {
kamg@124 3060 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3061 STACK_BIAS), "must be");
kamg@124 3062 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3063 }
kamg@124 3064 } else {
kamg@124 3065 // src not a register
kamg@124 3066 assert(Assembler::is_simm13(reg2offset(src.first()) +
kamg@124 3067 STACK_BIAS), "must be");
kamg@124 3068 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
kamg@124 3069 if (d == L2) {
kamg@124 3070 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3071 STACK_BIAS), "must be");
kamg@124 3072 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3073 }
kamg@124 3074 }
kamg@124 3075 } else if (out_sig_bt[c_arg] != T_VOID) {
kamg@124 3076 // Convert the arg to NULL
kamg@124 3077 if (dst.first()->is_reg()) {
kamg@124 3078 __ mov(G0, dst.first()->as_Register());
kamg@124 3079 } else {
kamg@124 3080 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3081 STACK_BIAS), "must be");
kamg@124 3082 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3083 }
kamg@124 3084 }
kamg@124 3085 }
kamg@124 3086 break;
kamg@124 3087 case T_VOID:
kamg@124 3088 break;
kamg@124 3089
kamg@124 3090 case T_FLOAT:
kamg@124 3091 if (src.first()->is_stack()) {
kamg@124 3092 // Stack to stack/reg is simple
kamg@124 3093 move32_64(masm, src, dst);
kamg@124 3094 } else {
kamg@124 3095 if (dst.first()->is_reg()) {
kamg@124 3096 // freg -> reg
kamg@124 3097 int off =
kamg@124 3098 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3099 Register d = dst.first()->as_Register();
kamg@124 3100 if (Assembler::is_simm13(off)) {
kamg@124 3101 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3102 SP, off);
kamg@124 3103 __ ld(SP, off, d);
kamg@124 3104 } else {
kamg@124 3105 if (conversion_off == noreg) {
kamg@124 3106 __ set(off, L6);
kamg@124 3107 conversion_off = L6;
kamg@124 3108 }
kamg@124 3109 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3110 SP, conversion_off);
kamg@124 3111 __ ld(SP, conversion_off , d);
kamg@124 3112 }
kamg@124 3113 } else {
kamg@124 3114 // freg -> mem
kamg@124 3115 int off = STACK_BIAS + reg2offset(dst.first());
kamg@124 3116 if (Assembler::is_simm13(off)) {
kamg@124 3117 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3118 SP, off);
kamg@124 3119 } else {
kamg@124 3120 if (conversion_off == noreg) {
kamg@124 3121 __ set(off, L6);
kamg@124 3122 conversion_off = L6;
kamg@124 3123 }
kamg@124 3124 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3125 SP, conversion_off);
kamg@124 3126 }
kamg@124 3127 }
kamg@124 3128 }
kamg@124 3129 break;
kamg@124 3130
kamg@124 3131 case T_DOUBLE:
kamg@124 3132 assert( j_arg + 1 < total_args_passed &&
kamg@124 3133 in_sig_bt[j_arg + 1] == T_VOID &&
kamg@124 3134 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
kamg@124 3135 if (src.first()->is_stack()) {
kamg@124 3136 // Stack to stack/reg is simple
kamg@124 3137 long_move(masm, src, dst);
kamg@124 3138 } else {
kamg@124 3139 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 3140
kamg@124 3141 // Destination could be an odd reg on 32bit in which case
kamg@124 3142 // we can't load direct to the destination.
kamg@124 3143
kamg@124 3144 if (!d->is_even() && wordSize == 4) {
kamg@124 3145 d = L2;
kamg@124 3146 }
kamg@124 3147 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3148 if (Assembler::is_simm13(off)) {
kamg@124 3149 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 3150 SP, off);
kamg@124 3151 __ ld_long(SP, off, d);
kamg@124 3152 } else {
kamg@124 3153 if (conversion_off == noreg) {
kamg@124 3154 __ set(off, L6);
kamg@124 3155 conversion_off = L6;
kamg@124 3156 }
kamg@124 3157 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 3158 SP, conversion_off);
kamg@124 3159 __ ld_long(SP, conversion_off, d);
kamg@124 3160 }
kamg@124 3161 if (d == L2) {
kamg@124 3162 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 3163 }
kamg@124 3164 }
kamg@124 3165 break;
kamg@124 3166
kamg@124 3167 case T_LONG :
kamg@124 3168 // 32bit can't do a split move of something like g1 -> O0, O1
kamg@124 3169 // so use a memory temp
kamg@124 3170 if (src.is_single_phys_reg() && wordSize == 4) {
kamg@124 3171 Register tmp = L2;
kamg@124 3172 if (dst.first()->is_reg() &&
kamg@124 3173 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
kamg@124 3174 tmp = dst.first()->as_Register();
kamg@124 3175 }
kamg@124 3176
kamg@124 3177 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3178 if (Assembler::is_simm13(off)) {
kamg@124 3179 __ stx(src.first()->as_Register(), SP, off);
kamg@124 3180 __ ld_long(SP, off, tmp);
kamg@124 3181 } else {
kamg@124 3182 if (conversion_off == noreg) {
kamg@124 3183 __ set(off, L6);
kamg@124 3184 conversion_off = L6;
kamg@124 3185 }
kamg@124 3186 __ stx(src.first()->as_Register(), SP, conversion_off);
kamg@124 3187 __ ld_long(SP, conversion_off, tmp);
kamg@124 3188 }
kamg@124 3189
kamg@124 3190 if (tmp == L2) {
kamg@124 3191 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 3192 }
kamg@124 3193 } else {
kamg@124 3194 long_move(masm, src, dst);
kamg@124 3195 }
kamg@124 3196 break;
kamg@124 3197
kamg@124 3198 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
kamg@124 3199
kamg@124 3200 default:
kamg@124 3201 move32_64(masm, src, dst);
kamg@124 3202 }
kamg@124 3203 }
kamg@124 3204
kamg@124 3205
kamg@124 3206 // If we have any strings we must store any register based arg to the stack
kamg@124 3207 // This includes any still live xmm registers too.
kamg@124 3208
kamg@124 3209 if (total_strings > 0 ) {
kamg@124 3210
kamg@124 3211 // protect all the arg registers
kamg@124 3212 __ save_frame(0);
kamg@124 3213 __ mov(G2_thread, L7_thread_cache);
kamg@124 3214 const Register L2_string_off = L2;
kamg@124 3215
kamg@124 3216 // Get first string offset
kamg@124 3217 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
kamg@124 3218
kamg@124 3219 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
kamg@124 3220 if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 3221
kamg@124 3222 VMRegPair dst = out_regs[c_arg];
kamg@124 3223 const Register d = dst.first()->is_reg() ?
kamg@124 3224 dst.first()->as_Register()->after_save() : noreg;
kamg@124 3225
kamg@124 3226 // It's a string the oop and it was already copied to the out arg
kamg@124 3227 // position
kamg@124 3228 if (d != noreg) {
kamg@124 3229 __ mov(d, O0);
kamg@124 3230 } else {
kamg@124 3231 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 3232 "must be");
kamg@124 3233 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
kamg@124 3234 }
kamg@124 3235 Label skip;
kamg@124 3236
kamg@124 3237 __ br_null(O0, false, Assembler::pn, skip);
kamg@124 3238 __ delayed()->add(FP, L2_string_off, O1);
kamg@124 3239
kamg@124 3240 if (d != noreg) {
kamg@124 3241 __ mov(O1, d);
kamg@124 3242 } else {
kamg@124 3243 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 3244 "must be");
kamg@124 3245 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3246 }
kamg@124 3247
kamg@124 3248 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
kamg@124 3249 relocInfo::runtime_call_type);
kamg@124 3250 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
kamg@124 3251
kamg@124 3252 __ bind(skip);
kamg@124 3253
kamg@124 3254 }
kamg@124 3255
kamg@124 3256 }
kamg@124 3257 __ mov(L7_thread_cache, G2_thread);
kamg@124 3258 __ restore();
kamg@124 3259
kamg@124 3260 }
kamg@124 3261
kamg@124 3262
kamg@124 3263 // Ok now we are done. Need to place the nop that dtrace wants in order to
kamg@124 3264 // patch in the trap
kamg@124 3265
kamg@124 3266 int patch_offset = ((intptr_t)__ pc()) - start;
kamg@124 3267
kamg@124 3268 __ nop();
kamg@124 3269
kamg@124 3270
kamg@124 3271 // Return
kamg@124 3272
kamg@124 3273 __ ret();
kamg@124 3274 __ delayed()->restore();
kamg@124 3275
kamg@124 3276 __ flush();
kamg@124 3277
kamg@124 3278 nmethod *nm = nmethod::new_dtrace_nmethod(
kamg@124 3279 method, masm->code(), vep_offset, patch_offset, frame_complete,
kamg@124 3280 stack_slots / VMRegImpl::slots_per_word);
kamg@124 3281 return nm;
kamg@124 3282
kamg@124 3283 }
kamg@124 3284
kamg@124 3285 #endif // HAVE_DTRACE_H
kamg@124 3286
duke@0 3287 // this function returns the adjust size (in number of words) to a c2i adapter
duke@0 3288 // activation for use during deoptimization
duke@0 3289 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
duke@0 3290 assert(callee_locals >= callee_parameters,
duke@0 3291 "test and remove; got more parms than locals");
duke@0 3292 if (callee_locals < callee_parameters)
duke@0 3293 return 0; // No adjustment for negative locals
twisti@1401 3294 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
duke@0 3295 return round_to(diff, WordsPerLong);
duke@0 3296 }
duke@0 3297
duke@0 3298 // "Top of Stack" slots that may be unused by the calling convention but must
duke@0 3299 // otherwise be preserved.
duke@0 3300 // On Intel these are not necessary and the value can be zero.
duke@0 3301 // On Sparc this describes the words reserved for storing a register window
duke@0 3302 // when an interrupt occurs.
duke@0 3303 uint SharedRuntime::out_preserve_stack_slots() {
duke@0 3304 return frame::register_save_words * VMRegImpl::slots_per_word;
duke@0 3305 }
duke@0 3306
duke@0 3307 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
duke@0 3308 //
duke@0 3309 // Common out the new frame generation for deopt and uncommon trap
duke@0 3310 //
duke@0 3311 Register G3pcs = G3_scratch; // Array of new pcs (input)
duke@0 3312 Register Oreturn0 = O0;
duke@0 3313 Register Oreturn1 = O1;
duke@0 3314 Register O2UnrollBlock = O2;
duke@0 3315 Register O3array = O3; // Array of frame sizes (input)
duke@0 3316 Register O4array_size = O4; // number of frames (input)
duke@0 3317 Register O7frame_size = O7; // number of frames (input)
duke@0 3318
duke@0 3319 __ ld_ptr(O3array, 0, O7frame_size);
duke@0 3320 __ sub(G0, O7frame_size, O7frame_size);
duke@0 3321 __ save(SP, O7frame_size, SP);
duke@0 3322 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
duke@0 3323
duke@0 3324 #ifdef ASSERT
duke@0 3325 // make sure that the frames are aligned properly
duke@0 3326 #ifndef _LP64
duke@0 3327 __ btst(wordSize*2-1, SP);
duke@0 3328 __ breakpoint_trap(Assembler::notZero);
duke@0 3329 #endif
duke@0 3330 #endif
duke@0 3331
duke@0 3332 // Deopt needs to pass some extra live values from frame to frame
duke@0 3333
duke@0 3334 if (deopt) {
duke@0 3335 __ mov(Oreturn0->after_save(), Oreturn0);
duke@0 3336 __ mov(Oreturn1->after_save(), Oreturn1);
duke@0 3337 }
duke@0 3338
duke@0 3339 __ mov(O4array_size->after_save(), O4array_size);
duke@0 3340 __ sub(O4array_size, 1, O4array_size);
duke@0 3341 __ mov(O3array->after_save(), O3array);
duke@0 3342 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
duke@0 3343 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
duke@0 3344
duke@0 3345 #ifdef ASSERT
duke@0 3346 // trash registers to show a clear pattern in backtraces
duke@0 3347 __ set(0xDEAD0000, I0);
duke@0 3348 __ add(I0, 2, I1);
duke@0 3349 __ add(I0, 4, I2);
duke@0 3350 __ add(I0, 6, I3);
duke@0 3351 __ add(I0, 8, I4);
duke@0 3352 // Don't touch I5 could have valuable savedSP
duke@0 3353 __ set(0xDEADBEEF, L0);
duke@0 3354 __ mov(L0, L1);
duke@0 3355 __ mov(L0, L2);
duke@0 3356 __ mov(L0, L3);
duke@0 3357 __ mov(L0, L4);
duke@0 3358 __ mov(L0, L5);
duke@0 3359
duke@0 3360 // trash the return value as there is nothing to return yet
duke@0 3361 __ set(0xDEAD0001, O7);
duke@0 3362 #endif
duke@0 3363
duke@0 3364 __ mov(SP, O5_savedSP);
duke@0 3365 }
duke@0 3366
duke@0 3367
duke@0 3368 static void make_new_frames(MacroAssembler* masm, bool deopt) {
duke@0 3369 //
duke@0 3370 // loop through the UnrollBlock info and create new frames
duke@0 3371 //
duke@0 3372 Register G3pcs = G3_scratch;
duke@0 3373 Register Oreturn0 = O0;
duke@0 3374 Register Oreturn1 = O1;
duke@0 3375 Register O2UnrollBlock = O2;
duke@0 3376 Register O3array = O3;
duke@0 3377 Register O4array_size = O4;
duke@0 3378 Label loop;
duke@0 3379
duke@0 3380 // Before we make new frames, check to see if stack is available.
duke@0 3381 // Do this after the caller's return address is on top of stack
duke@0 3382 if (UseStackBanging) {
duke@0 3383 // Get total frame size for interpreted frames
twisti@720 3384 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
duke@0 3385 __ bang_stack_size(O4, O3, G3_scratch);
duke@0 3386 }
duke@0 3387
twisti@720 3388 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
twisti@720 3389 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
twisti@720 3390 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
duke@0 3391
duke@0 3392 // Adjust old interpreter frame to make space for new frame's extra java locals
duke@0 3393 //
duke@0 3394 // We capture the original sp for the transition frame only because it is needed in
duke@0 3395 // order to properly calculate interpreter_sp_adjustment. Even though in real life
duke@0 3396 // every interpreter frame captures a savedSP it is only needed at the transition
duke@0 3397 // (fortunately). If we had to have it correct everywhere then we would need to
duke@0 3398 // be told the sp_adjustment for each frame we create. If the frame size array
duke@0 3399 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
duke@0 3400 // for each frame we create and keep up the illusion every where.
duke@0 3401 //
duke@0 3402
twisti@720 3403 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
duke@0 3404 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
duke@0 3405 __ sub(SP, O7, SP);
duke@0 3406
duke@0 3407 #ifdef ASSERT
duke@0 3408 // make sure that there is at least one entry in the array
duke@0 3409 __ tst(O4array_size);
duke@0 3410 __ breakpoint_trap(Assembler::zero);
duke@0 3411 #endif
duke@0 3412
duke@0 3413 // Now push the new interpreter frames
duke@0 3414 __ bind(loop);
duke@0 3415
duke@0 3416 // allocate a new frame, filling the registers
duke@0 3417
duke@0 3418 gen_new_frame(masm, deopt); // allocate an interpreter frame
duke@0 3419
kvn@2600 3420 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop);
duke@0 3421 __ delayed()->add(O3array, wordSize, O3array);
duke@0 3422 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
duke@0 3423
duke@0 3424 }
duke@0 3425
duke@0 3426 //------------------------------generate_deopt_blob----------------------------
duke@0 3427 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 3428 // instead.
duke@0 3429 void SharedRuntime::generate_deopt_blob() {
duke@0 3430 // allocate space for the code
duke@0 3431 ResourceMark rm;
duke@0 3432 // setup code ge