annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 1401:2338d41fbd81

6943304: remove tagged stack interpreter Reviewed-by: coleenp, never, gbenson
author twisti
date Fri, 30 Apr 2010 08:37:24 -0700
parents 576e77447e3c
children 61b2245abf36 c18cbe5936b8
rev   line source
duke@0 1 /*
never@1179 2 * Copyright 2003-2010 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 #include "incls/_precompiled.incl"
duke@0 26 #include "incls/_sharedRuntime_sparc.cpp.incl"
duke@0 27
duke@0 28 #define __ masm->
duke@0 29
duke@0 30 #ifdef COMPILER2
duke@0 31 UncommonTrapBlob* SharedRuntime::_uncommon_trap_blob;
duke@0 32 #endif // COMPILER2
duke@0 33
duke@0 34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
duke@0 35 SafepointBlob* SharedRuntime::_polling_page_safepoint_handler_blob;
duke@0 36 SafepointBlob* SharedRuntime::_polling_page_return_handler_blob;
duke@0 37 RuntimeStub* SharedRuntime::_wrong_method_blob;
duke@0 38 RuntimeStub* SharedRuntime::_ic_miss_blob;
duke@0 39 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
duke@0 40 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
duke@0 41 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
duke@0 42
duke@0 43 class RegisterSaver {
duke@0 44
duke@0 45 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@0 46 // The Oregs are problematic. In the 32bit build the compiler can
duke@0 47 // have O registers live with 64 bit quantities. A window save will
duke@0 48 // cut the heads off of the registers. We have to do a very extensive
duke@0 49 // stack dance to save and restore these properly.
duke@0 50
duke@0 51 // Note that the Oregs problem only exists if we block at either a polling
duke@0 52 // page exception a compiled code safepoint that was not originally a call
duke@0 53 // or deoptimize following one of these kinds of safepoints.
duke@0 54
duke@0 55 // Lots of registers to save. For all builds, a window save will preserve
duke@0 56 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@0 57 // builds a window-save will preserve the %o registers. In the LION build
duke@0 58 // we need to save the 64-bit %o registers which requires we save them
duke@0 59 // before the window-save (as then they become %i registers and get their
duke@0 60 // heads chopped off on interrupt). We have to save some %g registers here
duke@0 61 // as well.
duke@0 62 enum {
duke@0 63 // This frame's save area. Includes extra space for the native call:
duke@0 64 // vararg's layout space and the like. Briefly holds the caller's
duke@0 65 // register save area.
duke@0 66 call_args_area = frame::register_save_words_sp_offset +
duke@0 67 frame::memory_parameter_word_sp_offset*wordSize,
duke@0 68 // Make sure save locations are always 8 byte aligned.
duke@0 69 // can't use round_to because it doesn't produce compile time constant
duke@0 70 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@0 71 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@0 72 g3_offset = g1_offset+8,
duke@0 73 g4_offset = g3_offset+8,
duke@0 74 g5_offset = g4_offset+8,
duke@0 75 o0_offset = g5_offset+8,
duke@0 76 o1_offset = o0_offset+8,
duke@0 77 o2_offset = o1_offset+8,
duke@0 78 o3_offset = o2_offset+8,
duke@0 79 o4_offset = o3_offset+8,
duke@0 80 o5_offset = o4_offset+8,
duke@0 81 start_of_flags_save_area = o5_offset+8,
duke@0 82 ccr_offset = start_of_flags_save_area,
duke@0 83 fsr_offset = ccr_offset + 8,
duke@0 84 d00_offset = fsr_offset+8, // Start of float save area
duke@0 85 register_save_size = d00_offset+8*32
duke@0 86 };
duke@0 87
duke@0 88
duke@0 89 public:
duke@0 90
duke@0 91 static int Oexception_offset() { return o0_offset; };
duke@0 92 static int G3_offset() { return g3_offset; };
duke@0 93 static int G5_offset() { return g5_offset; };
duke@0 94 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@0 95 static void restore_live_registers(MacroAssembler* masm);
duke@0 96
duke@0 97 // During deoptimization only the result register need to be restored
duke@0 98 // all the other values have already been extracted.
duke@0 99
duke@0 100 static void restore_result_registers(MacroAssembler* masm);
duke@0 101 };
duke@0 102
duke@0 103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@0 104 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@0 105 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@0 106 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@0 107 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@0 108 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@0 109 int i;
kvn@992 110 // Always make the frame size 16 byte aligned.
duke@0 111 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@0 112 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@0 113 int frame_size_in_slots = frame_size / sizeof(jint);
duke@0 114 // CodeBlob frame size is in words.
duke@0 115 *total_frame_words = frame_size / wordSize;
duke@0 116 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@0 117 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@0 118
duke@0 119 #if !defined(_LP64)
duke@0 120
duke@0 121 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@0 122 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 123 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 124 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 125 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 126 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 127 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 128 #endif /* _LP64 */
duke@0 129
duke@0 130 __ save(SP, -frame_size, SP);
duke@0 131
duke@0 132 #ifndef _LP64
duke@0 133 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@0 134 // to Oregs here to avoid interrupts cutting off their heads
duke@0 135
duke@0 136 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 137 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 138 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 139 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 140 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 141 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 142
duke@0 143 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@0 144 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@0 145
duke@0 146 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@0 147
duke@0 148 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@0 149
duke@0 150 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@0 151 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@0 152
duke@0 153 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@0 154 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@0 155
duke@0 156 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@0 157 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@0 158
duke@0 159 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@0 160 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@0 161 #endif /* _LP64 */
duke@0 162
coleenp@108 163
coleenp@108 164 #ifdef _LP64
coleenp@108 165 int debug_offset = 0;
coleenp@108 166 #else
coleenp@108 167 int debug_offset = 4;
coleenp@108 168 #endif
duke@0 169 // Save the G's
duke@0 170 __ stx(G1, SP, g1_offset+STACK_BIAS);
coleenp@108 171 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
duke@0 172
duke@0 173 __ stx(G3, SP, g3_offset+STACK_BIAS);
coleenp@108 174 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
duke@0 175
duke@0 176 __ stx(G4, SP, g4_offset+STACK_BIAS);
coleenp@108 177 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
duke@0 178
duke@0 179 __ stx(G5, SP, g5_offset+STACK_BIAS);
coleenp@108 180 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
duke@0 181
duke@0 182 // This is really a waste but we'll keep things as they were for now
duke@0 183 if (true) {
duke@0 184 #ifndef _LP64
duke@0 185 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@0 186 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@0 187 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@0 188 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@0 189 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@0 190 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@0 191 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@0 192 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@0 193 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@0 194 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
coleenp@108 195 #endif /* _LP64 */
duke@0 196 }
duke@0 197
duke@0 198
duke@0 199 // Save the flags
duke@0 200 __ rdccr( G5 );
duke@0 201 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@0 202 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 203
kvn@992 204 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
duke@0 205 int offset = d00_offset;
kvn@992 206 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 207 FloatRegister f = as_FloatRegister(i);
duke@0 208 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
kvn@992 209 // Record as callee saved both halves of double registers (2 float registers).
duke@0 210 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
kvn@992 211 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@0 212 offset += sizeof(double);
duke@0 213 }
duke@0 214
duke@0 215 // And we're done.
duke@0 216
duke@0 217 return map;
duke@0 218 }
duke@0 219
duke@0 220
duke@0 221 // Pop the current frame and restore all the registers that we
duke@0 222 // saved.
duke@0 223 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@0 224
duke@0 225 // Restore all the FP registers
kvn@992 226 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 227 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@0 228 }
duke@0 229
duke@0 230 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@0 231 __ wrccr (G1) ;
duke@0 232
duke@0 233 // Restore the G's
duke@0 234 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@0 235 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@0 236
duke@0 237 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 238 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@0 239 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@0 240 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@0 241
duke@0 242
duke@0 243 #if !defined(_LP64)
duke@0 244 // Restore the 64-bit O's.
duke@0 245 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 246 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 247 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@0 248 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@0 249 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@0 250 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@0 251
duke@0 252 // And temporarily place them in TLS
duke@0 253
duke@0 254 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 255 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 256 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 257 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 258 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 259 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 260 #endif /* _LP64 */
duke@0 261
duke@0 262 // Restore flags
duke@0 263
duke@0 264 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 265
duke@0 266 __ restore();
duke@0 267
duke@0 268 #if !defined(_LP64)
duke@0 269 // Now reload the 64bit Oregs after we've restore the window.
duke@0 270 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 271 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 272 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 273 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 274 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 275 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 276 #endif /* _LP64 */
duke@0 277
duke@0 278 }
duke@0 279
duke@0 280 // Pop the current frame and restore the registers that might be holding
duke@0 281 // a result.
duke@0 282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@0 283
duke@0 284 #if !defined(_LP64)
duke@0 285 // 32bit build returns longs in G1
duke@0 286 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 287
duke@0 288 // Retrieve the 64-bit O's.
duke@0 289 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 290 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 291 // and save to TLS
duke@0 292 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 293 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 294 #endif /* _LP64 */
duke@0 295
duke@0 296 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@0 297
duke@0 298 __ restore();
duke@0 299
duke@0 300 #if !defined(_LP64)
duke@0 301 // Now reload the 64bit Oregs after we've restore the window.
duke@0 302 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 303 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 304 #endif /* _LP64 */
duke@0 305
duke@0 306 }
duke@0 307
duke@0 308 // The java_calling_convention describes stack locations as ideal slots on
duke@0 309 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@0 310 // (like the placement of the register window) the slots must be biased by
duke@0 311 // the following value.
duke@0 312 static int reg2offset(VMReg r) {
duke@0 313 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@0 314 }
duke@0 315
duke@0 316 // ---------------------------------------------------------------------------
duke@0 317 // Read the array of BasicTypes from a signature, and compute where the
duke@0 318 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@0 319 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@0 320 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@0 321 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@0 322 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@0 323 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@0 324 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@0 325 // Each 32-bit quantity is given its own number, so the integer registers
duke@0 326 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@0 327 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@0 328
duke@0 329 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@0 330 // convert to incoming arguments, convert all O's to I's. The regs array
duke@0 331 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@0 332 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@0 333 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@0 334 // passed (used as a placeholder for the other half of longs and doubles in
duke@0 335 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@0 336 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@0 337 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@0 338 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@0 339 // same VMRegPair.
duke@0 340
duke@0 341 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@0 342 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@0 343 // units regardless of build.
duke@0 344
duke@0 345
duke@0 346 // ---------------------------------------------------------------------------
duke@0 347 // The compiled Java calling convention. The Java convention always passes
duke@0 348 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@0 349 // floats in float registers and doubles in aligned float pairs. Values are
duke@0 350 // packed in the registers. There is no backing varargs store for values in
duke@0 351 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@0 352 // passed in I's, because longs in I's get their heads chopped off at
duke@0 353 // interrupt).
duke@0 354 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@0 355 VMRegPair *regs,
duke@0 356 int total_args_passed,
duke@0 357 int is_outgoing) {
duke@0 358 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@0 359
duke@0 360 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@0 361 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@0 362 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@0 363 // align. Then put longs and doubles into the same registers as they fit,
duke@0 364 // else spill to the stack.
duke@0 365 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@0 366 const int flt_reg_max = 8;
duke@0 367 //
duke@0 368 // Where 32-bit 1-reg longs start being passed
duke@0 369 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@0 370 // So make it look like we've filled all the G regs that c2 wants to use.
duke@0 371 Register g_reg = TieredCompilation ? noreg : G1;
duke@0 372
duke@0 373 // Count int/oop and float args. See how many stack slots we'll need and
duke@0 374 // where the longs & doubles will go.
duke@0 375 int int_reg_cnt = 0;
duke@0 376 int flt_reg_cnt = 0;
duke@0 377 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@0 378 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@0 379 int stk_reg_pairs = 0;
duke@0 380 for (int i = 0; i < total_args_passed; i++) {
duke@0 381 switch (sig_bt[i]) {
duke@0 382 case T_LONG: // LP64, longs compete with int args
duke@0 383 assert(sig_bt[i+1] == T_VOID, "");
duke@0 384 #ifdef _LP64
duke@0 385 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 386 #endif
duke@0 387 break;
duke@0 388 case T_OBJECT:
duke@0 389 case T_ARRAY:
duke@0 390 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 391 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 392 #ifndef _LP64
duke@0 393 else stk_reg_pairs++;
duke@0 394 #endif
duke@0 395 break;
duke@0 396 case T_INT:
duke@0 397 case T_SHORT:
duke@0 398 case T_CHAR:
duke@0 399 case T_BYTE:
duke@0 400 case T_BOOLEAN:
duke@0 401 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 402 else stk_reg_pairs++;
duke@0 403 break;
duke@0 404 case T_FLOAT:
duke@0 405 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@0 406 else stk_reg_pairs++;
duke@0 407 break;
duke@0 408 case T_DOUBLE:
duke@0 409 assert(sig_bt[i+1] == T_VOID, "");
duke@0 410 break;
duke@0 411 case T_VOID:
duke@0 412 break;
duke@0 413 default:
duke@0 414 ShouldNotReachHere();
duke@0 415 }
duke@0 416 }
duke@0 417
duke@0 418 // This is where the longs/doubles start on the stack.
duke@0 419 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@0 420
duke@0 421 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
duke@0 422 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@0 423
duke@0 424 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@0 425 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@0 426 int stk_reg = 0;
duke@0 427 int int_reg = 0;
duke@0 428 int flt_reg = 0;
duke@0 429
duke@0 430 // Now do the signature layout
duke@0 431 for (int i = 0; i < total_args_passed; i++) {
duke@0 432 switch (sig_bt[i]) {
duke@0 433 case T_INT:
duke@0 434 case T_SHORT:
duke@0 435 case T_CHAR:
duke@0 436 case T_BYTE:
duke@0 437 case T_BOOLEAN:
duke@0 438 #ifndef _LP64
duke@0 439 case T_OBJECT:
duke@0 440 case T_ARRAY:
duke@0 441 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 442 #endif // _LP64
duke@0 443 if (int_reg < int_reg_max) {
duke@0 444 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 445 regs[i].set1(r->as_VMReg());
duke@0 446 } else {
duke@0 447 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 448 }
duke@0 449 break;
duke@0 450
duke@0 451 #ifdef _LP64
duke@0 452 case T_OBJECT:
duke@0 453 case T_ARRAY:
duke@0 454 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 455 if (int_reg < int_reg_max) {
duke@0 456 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 457 regs[i].set2(r->as_VMReg());
duke@0 458 } else {
duke@0 459 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 460 stk_reg_pairs += 2;
duke@0 461 }
duke@0 462 break;
duke@0 463 #endif // _LP64
duke@0 464
duke@0 465 case T_LONG:
duke@0 466 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@0 467 #ifdef _LP64
duke@0 468 if (int_reg < int_reg_max) {
duke@0 469 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 470 regs[i].set2(r->as_VMReg());
duke@0 471 } else {
duke@0 472 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 473 stk_reg_pairs += 2;
duke@0 474 }
duke@0 475 #else
never@297 476 #ifdef COMPILER2
duke@0 477 // For 32-bit build, can't pass longs in O-regs because they become
duke@0 478 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@0 479 // spare and available. This convention isn't used by the Sparc ABI or
duke@0 480 // anywhere else. If we're tiered then we don't use G-regs because c1
never@297 481 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
duke@0 482 // G0: zero
duke@0 483 // G1: 1st Long arg
duke@0 484 // G2: global allocated to TLS
duke@0 485 // G3: used in inline cache check
duke@0 486 // G4: 2nd Long arg
duke@0 487 // G5: used in inline cache check
duke@0 488 // G6: used by OS
duke@0 489 // G7: used by OS
duke@0 490
duke@0 491 if (g_reg == G1) {
duke@0 492 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@0 493 g_reg = G4; // Where the next arg goes
duke@0 494 } else if (g_reg == G4) {
duke@0 495 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@0 496 g_reg = noreg; // No more longs in registers
duke@0 497 } else {
duke@0 498 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 499 stk_reg_pairs += 2;
duke@0 500 }
duke@0 501 #else // COMPILER2
duke@0 502 if (int_reg_pairs + 1 < int_reg_max) {
duke@0 503 if (is_outgoing) {
duke@0 504 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
duke@0 505 } else {
duke@0 506 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
duke@0 507 }
duke@0 508 int_reg_pairs += 2;
duke@0 509 } else {
duke@0 510 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 511 stk_reg_pairs += 2;
duke@0 512 }
duke@0 513 #endif // COMPILER2
never@297 514 #endif // _LP64
duke@0 515 break;
duke@0 516
duke@0 517 case T_FLOAT:
duke@0 518 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
duke@0 519 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
duke@0 520 break;
duke@0 521 case T_DOUBLE:
duke@0 522 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@0 523 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@0 524 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@0 525 flt_reg_pairs += 2;
duke@0 526 } else {
duke@0 527 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 528 stk_reg_pairs += 2;
duke@0 529 }
duke@0 530 break;
duke@0 531 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@0 532 default:
duke@0 533 ShouldNotReachHere();
duke@0 534 }
duke@0 535 }
duke@0 536
duke@0 537 // retun the amount of stack space these arguments will need.
duke@0 538 return stk_reg_pairs;
duke@0 539
duke@0 540 }
duke@0 541
twisti@991 542 // Helper class mostly to avoid passing masm everywhere, and handle
twisti@991 543 // store displacement overflow logic.
duke@0 544 class AdapterGenerator {
duke@0 545 MacroAssembler *masm;
duke@0 546 Register Rdisp;
duke@0 547 void set_Rdisp(Register r) { Rdisp = r; }
duke@0 548
duke@0 549 void patch_callers_callsite();
duke@0 550
duke@0 551 // base+st_off points to top of argument
twisti@1401 552 int arg_offset(const int st_off) { return st_off; }
duke@0 553 int next_arg_offset(const int st_off) {
twisti@1401 554 return st_off - Interpreter::stackElementSize;
twisti@991 555 }
twisti@991 556
twisti@991 557 // Argument slot values may be loaded first into a register because
twisti@991 558 // they might not fit into displacement.
twisti@991 559 RegisterOrConstant arg_slot(const int st_off);
twisti@991 560 RegisterOrConstant next_arg_slot(const int st_off);
twisti@991 561
duke@0 562 // Stores long into offset pointed to by base
duke@0 563 void store_c2i_long(Register r, Register base,
duke@0 564 const int st_off, bool is_stack);
duke@0 565 void store_c2i_object(Register r, Register base,
duke@0 566 const int st_off);
duke@0 567 void store_c2i_int(Register r, Register base,
duke@0 568 const int st_off);
duke@0 569 void store_c2i_double(VMReg r_2,
duke@0 570 VMReg r_1, Register base, const int st_off);
duke@0 571 void store_c2i_float(FloatRegister f, Register base,
duke@0 572 const int st_off);
duke@0 573
duke@0 574 public:
duke@0 575 void gen_c2i_adapter(int total_args_passed,
duke@0 576 // VMReg max_arg,
duke@0 577 int comp_args_on_stack, // VMRegStackSlots
duke@0 578 const BasicType *sig_bt,
duke@0 579 const VMRegPair *regs,
duke@0 580 Label& skip_fixup);
duke@0 581 void gen_i2c_adapter(int total_args_passed,
duke@0 582 // VMReg max_arg,
duke@0 583 int comp_args_on_stack, // VMRegStackSlots
duke@0 584 const BasicType *sig_bt,
duke@0 585 const VMRegPair *regs);
duke@0 586
duke@0 587 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@0 588 };
duke@0 589
duke@0 590
duke@0 591 // Patch the callers callsite with entry to compiled code if it exists.
duke@0 592 void AdapterGenerator::patch_callers_callsite() {
duke@0 593 Label L;
duke@0 594 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 595 __ br_null(G3_scratch, false, __ pt, L);
duke@0 596 // Schedule the branch target address early.
duke@0 597 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 598 // Call into the VM to patch the caller, then jump to compiled callee
duke@0 599 __ save_frame(4); // Args in compiled layout; do not blow them
duke@0 600
duke@0 601 // Must save all the live Gregs the list is:
duke@0 602 // G1: 1st Long arg (32bit build)
duke@0 603 // G2: global allocated to TLS
duke@0 604 // G3: used in inline cache check (scratch)
duke@0 605 // G4: 2nd Long arg (32bit build);
duke@0 606 // G5: used in inline cache check (methodOop)
duke@0 607
duke@0 608 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@0 609
duke@0 610 #ifdef _LP64
duke@0 611 // mov(s,d)
duke@0 612 __ mov(G1, L1);
duke@0 613 __ mov(G4, L4);
duke@0 614 __ mov(G5_method, L5);
duke@0 615 __ mov(G5_method, O0); // VM needs target method
duke@0 616 __ mov(I7, O1); // VM needs caller's callsite
duke@0 617 // Must be a leaf call...
duke@0 618 // can be very far once the blob has been relocated
twisti@720 619 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@0 620 __ relocate(relocInfo::runtime_call_type);
twisti@720 621 __ jumpl_to(dest, O7, O7);
duke@0 622 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 623 __ mov(L7_thread_cache, G2_thread);
duke@0 624 __ mov(L1, G1);
duke@0 625 __ mov(L4, G4);
duke@0 626 __ mov(L5, G5_method);
duke@0 627 #else
duke@0 628 __ stx(G1, FP, -8 + STACK_BIAS);
duke@0 629 __ stx(G4, FP, -16 + STACK_BIAS);
duke@0 630 __ mov(G5_method, L5);
duke@0 631 __ mov(G5_method, O0); // VM needs target method
duke@0 632 __ mov(I7, O1); // VM needs caller's callsite
duke@0 633 // Must be a leaf call...
duke@0 634 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@0 635 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 636 __ mov(L7_thread_cache, G2_thread);
duke@0 637 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@0 638 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@0 639 __ mov(L5, G5_method);
duke@0 640 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 641 #endif /* _LP64 */
duke@0 642
duke@0 643 __ restore(); // Restore args
duke@0 644 __ bind(L);
duke@0 645 }
duke@0 646
twisti@991 647
twisti@991 648 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
twisti@991 649 RegisterOrConstant roc(arg_offset(st_off));
twisti@991 650 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 651 }
duke@0 652
twisti@991 653 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
twisti@991 654 RegisterOrConstant roc(next_arg_offset(st_off));
twisti@991 655 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 656 }
twisti@991 657
twisti@991 658
duke@0 659 // Stores long into offset pointed to by base
duke@0 660 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@0 661 const int st_off, bool is_stack) {
duke@0 662 #ifdef _LP64
duke@0 663 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 664 // data is passed in only 1 slot.
duke@0 665 __ stx(r, base, next_arg_slot(st_off));
duke@0 666 #else
ysr@344 667 #ifdef COMPILER2
duke@0 668 // Misaligned store of 64-bit data
duke@0 669 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 670 __ srlx(r, 32, r);
duke@0 671 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 672 #else
duke@0 673 if (is_stack) {
duke@0 674 // Misaligned store of 64-bit data
duke@0 675 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 676 __ srlx(r, 32, r);
duke@0 677 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 678 } else {
duke@0 679 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@0 680 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@0 681 }
duke@0 682 #endif // COMPILER2
ysr@344 683 #endif // _LP64
duke@0 684 }
duke@0 685
duke@0 686 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@0 687 const int st_off) {
duke@0 688 __ st_ptr (r, base, arg_slot(st_off));
duke@0 689 }
duke@0 690
duke@0 691 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@0 692 const int st_off) {
duke@0 693 __ st (r, base, arg_slot(st_off));
duke@0 694 }
duke@0 695
duke@0 696 // Stores into offset pointed to by base
duke@0 697 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@0 698 VMReg r_1, Register base, const int st_off) {
duke@0 699 #ifdef _LP64
duke@0 700 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 701 // data is passed in only 1 slot.
duke@0 702 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 703 #else
duke@0 704 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 705 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 706 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@0 707 #endif
duke@0 708 }
duke@0 709
duke@0 710 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@0 711 const int st_off) {
duke@0 712 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@0 713 }
duke@0 714
duke@0 715 void AdapterGenerator::gen_c2i_adapter(
duke@0 716 int total_args_passed,
duke@0 717 // VMReg max_arg,
duke@0 718 int comp_args_on_stack, // VMRegStackSlots
duke@0 719 const BasicType *sig_bt,
duke@0 720 const VMRegPair *regs,
duke@0 721 Label& skip_fixup) {
duke@0 722
duke@0 723 // Before we get into the guts of the C2I adapter, see if we should be here
duke@0 724 // at all. We've come from compiled code and are attempting to jump to the
duke@0 725 // interpreter, which means the caller made a static call to get here
duke@0 726 // (vcalls always get a compiled target if there is one). Check for a
duke@0 727 // compiled target. If there is one, we need to patch the caller's call.
duke@0 728 // However we will run interpreted if we come thru here. The next pass
duke@0 729 // thru the call site will run compiled. If we ran compiled here then
duke@0 730 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@0 731 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@0 732 // we can have at most one and don't need to play any tricks to keep
duke@0 733 // from endlessly growing the stack.
duke@0 734 //
duke@0 735 // Actually if we detected that we had an i2c->c2i transition here we
duke@0 736 // ought to be able to reset the world back to the state of the interpreted
duke@0 737 // call and not bother building another interpreter arg area. We don't
duke@0 738 // do that at this point.
duke@0 739
duke@0 740 patch_callers_callsite();
duke@0 741
duke@0 742 __ bind(skip_fixup);
duke@0 743
duke@0 744 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@0 745 // space we need. Add in varargs area needed by the interpreter. Round up
duke@0 746 // to stack alignment.
twisti@1401 747 const int arg_size = total_args_passed * Interpreter::stackElementSize;
duke@0 748 const int varargs_area =
duke@0 749 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@0 750 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@0 751
duke@0 752 int bias = STACK_BIAS;
duke@0 753 const int interp_arg_offset = frame::varargs_offset*wordSize +
twisti@1401 754 (total_args_passed-1)*Interpreter::stackElementSize;
duke@0 755
duke@0 756 Register base = SP;
duke@0 757
duke@0 758 #ifdef _LP64
duke@0 759 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@0 760 // out of bits in the displacement to do loads and stores. Use g3 as
duke@0 761 // temporary displacement.
duke@0 762 if (! __ is_simm13(extraspace)) {
duke@0 763 __ set(extraspace, G3_scratch);
duke@0 764 __ sub(SP, G3_scratch, SP);
duke@0 765 } else {
duke@0 766 __ sub(SP, extraspace, SP);
duke@0 767 }
duke@0 768 set_Rdisp(G3_scratch);
duke@0 769 #else
duke@0 770 __ sub(SP, extraspace, SP);
duke@0 771 #endif // _LP64
duke@0 772
duke@0 773 // First write G1 (if used) to where ever it must go
duke@0 774 for (int i=0; i<total_args_passed; i++) {
twisti@1401 775 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 776 VMReg r_1 = regs[i].first();
duke@0 777 VMReg r_2 = regs[i].second();
duke@0 778 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 779 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 780 store_c2i_object(G1_scratch, base, st_off);
duke@0 781 } else if (sig_bt[i] == T_LONG) {
duke@0 782 assert(!TieredCompilation, "should not use register args for longs");
duke@0 783 store_c2i_long(G1_scratch, base, st_off, false);
duke@0 784 } else {
duke@0 785 store_c2i_int(G1_scratch, base, st_off);
duke@0 786 }
duke@0 787 }
duke@0 788 }
duke@0 789
duke@0 790 // Now write the args into the outgoing interpreter space
duke@0 791 for (int i=0; i<total_args_passed; i++) {
twisti@1401 792 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 793 VMReg r_1 = regs[i].first();
duke@0 794 VMReg r_2 = regs[i].second();
duke@0 795 if (!r_1->is_valid()) {
duke@0 796 assert(!r_2->is_valid(), "");
duke@0 797 continue;
duke@0 798 }
duke@0 799 // Skip G1 if found as we did it first in order to free it up
duke@0 800 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 801 continue;
duke@0 802 }
duke@0 803 #ifdef ASSERT
duke@0 804 bool G1_forced = false;
duke@0 805 #endif // ASSERT
duke@0 806 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@0 807 #ifdef _LP64
duke@0 808 Register ld_off = Rdisp;
duke@0 809 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@0 810 #else
duke@0 811 int ld_off = reg2offset(r_1) + extraspace + bias;
kvn@1209 812 #endif // _LP64
duke@0 813 #ifdef ASSERT
duke@0 814 G1_forced = true;
duke@0 815 #endif // ASSERT
duke@0 816 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@0 817 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@0 818 else __ ldx(base, ld_off, G1_scratch);
duke@0 819 }
duke@0 820
duke@0 821 if (r_1->is_Register()) {
duke@0 822 Register r = r_1->as_Register()->after_restore();
duke@0 823 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 824 store_c2i_object(r, base, st_off);
duke@0 825 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
kvn@1209 826 #ifndef _LP64
duke@0 827 if (TieredCompilation) {
duke@0 828 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@0 829 }
kvn@1209 830 #endif // _LP64
duke@0 831 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@0 832 } else {
duke@0 833 store_c2i_int(r, base, st_off);
duke@0 834 }
duke@0 835 } else {
duke@0 836 assert(r_1->is_FloatRegister(), "");
duke@0 837 if (sig_bt[i] == T_FLOAT) {
duke@0 838 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@0 839 } else {
duke@0 840 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@0 841 store_c2i_double(r_2, r_1, base, st_off);
duke@0 842 }
duke@0 843 }
duke@0 844 }
duke@0 845
duke@0 846 #ifdef _LP64
duke@0 847 // Need to reload G3_scratch, used for temporary displacements.
duke@0 848 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 849
duke@0 850 // Pass O5_savedSP as an argument to the interpreter.
duke@0 851 // The interpreter will restore SP to this value before returning.
duke@0 852 __ set(extraspace, G1);
duke@0 853 __ add(SP, G1, O5_savedSP);
duke@0 854 #else
duke@0 855 // Pass O5_savedSP as an argument to the interpreter.
duke@0 856 // The interpreter will restore SP to this value before returning.
duke@0 857 __ add(SP, extraspace, O5_savedSP);
duke@0 858 #endif // _LP64
duke@0 859
duke@0 860 __ mov((frame::varargs_offset)*wordSize -
twisti@1401 861 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
duke@0 862 // Jump to the interpreter just as if interpreter was doing it.
duke@0 863 __ jmpl(G3_scratch, 0, G0);
duke@0 864 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@0 865 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@0 866 // the interpreter does not know where its args are without some kind of
duke@0 867 // arg pointer being passed in. Pass it in Gargs.
duke@0 868 __ delayed()->add(SP, G1, Gargs);
duke@0 869 }
duke@0 870
duke@0 871 void AdapterGenerator::gen_i2c_adapter(
duke@0 872 int total_args_passed,
duke@0 873 // VMReg max_arg,
duke@0 874 int comp_args_on_stack, // VMRegStackSlots
duke@0 875 const BasicType *sig_bt,
duke@0 876 const VMRegPair *regs) {
duke@0 877
duke@0 878 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@0 879 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@0 880 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@0 881 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@0 882 // hoist register arguments and repack other args according to the compiled
duke@0 883 // code convention. Finally, end in a jump to the compiled code. The entry
duke@0 884 // point address is the start of the buffer.
duke@0 885
duke@0 886 // We will only enter here from an interpreted frame and never from after
duke@0 887 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@0 888 // race and use a c2i we will remain interpreted for the race loser(s).
duke@0 889 // This removes all sorts of headaches on the x86 side and also eliminates
duke@0 890 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@0 891
duke@0 892 // As you can see from the list of inputs & outputs there are not a lot
duke@0 893 // of temp registers to work with: mostly G1, G3 & G4.
duke@0 894
duke@0 895 // Inputs:
duke@0 896 // G2_thread - TLS
duke@0 897 // G5_method - Method oop
jrose@689 898 // G4 (Gargs) - Pointer to interpreter's args
jrose@689 899 // O0..O4 - free for scratch
jrose@689 900 // O5_savedSP - Caller's saved SP, to be restored if needed
duke@0 901 // O6 - Current SP!
duke@0 902 // O7 - Valid return address
jrose@689 903 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 904
duke@0 905 // Outputs:
duke@0 906 // G2_thread - TLS
duke@0 907 // G1, G4 - Outgoing long args in 32-bit build
duke@0 908 // O0-O5 - Outgoing args in compiled layout
duke@0 909 // O6 - Adjusted or restored SP
duke@0 910 // O7 - Valid return address
duke@0 911 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 912 // F0-F7 - more outgoing args
duke@0 913
duke@0 914
jrose@689 915 // Gargs is the incoming argument base, and also an outgoing argument.
duke@0 916 __ sub(Gargs, BytesPerWord, Gargs);
duke@0 917
duke@0 918 #ifdef ASSERT
duke@0 919 {
duke@0 920 // on entry OsavedSP and SP should be equal
duke@0 921 Label ok;
duke@0 922 __ cmp(O5_savedSP, SP);
duke@0 923 __ br(Assembler::equal, false, Assembler::pt, ok);
duke@0 924 __ delayed()->nop();
duke@0 925 __ stop("I5_savedSP not set");
duke@0 926 __ should_not_reach_here();
duke@0 927 __ bind(ok);
duke@0 928 }
duke@0 929 #endif
duke@0 930
duke@0 931 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@0 932 // WITH O7 HOLDING A VALID RETURN PC
duke@0 933 //
duke@0 934 // | |
duke@0 935 // : java stack :
duke@0 936 // | |
duke@0 937 // +--------------+ <--- start of outgoing args
duke@0 938 // | receiver | |
duke@0 939 // : rest of args : |---size is java-arg-words
duke@0 940 // | | |
duke@0 941 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@0 942 // | | |
duke@0 943 // : unused : |---Space for max Java stack, plus stack alignment
duke@0 944 // | | |
duke@0 945 // +--------------+ <--- SP + 16*wordsize
duke@0 946 // | |
duke@0 947 // : window :
duke@0 948 // | |
duke@0 949 // +--------------+ <--- SP
duke@0 950
duke@0 951 // WE REPACK THE STACK. We use the common calling convention layout as
duke@0 952 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@0 953 // causes an arbitrary shuffle of memory, which may require some register
duke@0 954 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@0 955 // temps are not needed. We may have to resize the stack slightly, in case
duke@0 956 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@0 957 // misaligned, but the compilers expect them aligned).
duke@0 958 //
duke@0 959 // | |
duke@0 960 // : java stack :
duke@0 961 // | |
duke@0 962 // +--------------+ <--- start of outgoing args
duke@0 963 // | pad, align | |
duke@0 964 // +--------------+ |
duke@0 965 // | ints, floats | |---Outgoing stack args, packed low.
duke@0 966 // +--------------+ | First few args in registers.
duke@0 967 // : doubles : |
duke@0 968 // | longs | |
duke@0 969 // +--------------+ <--- SP' + 16*wordsize
duke@0 970 // | |
duke@0 971 // : window :
duke@0 972 // | |
duke@0 973 // +--------------+ <--- SP'
duke@0 974
duke@0 975 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@0 976 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@0 977 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@0 978
duke@0 979 // Cut-out for having no stack args. Since up to 6 args are passed
duke@0 980 // in registers, we will commonly have no stack args.
duke@0 981 if (comp_args_on_stack > 0) {
duke@0 982
duke@0 983 // Convert VMReg stack slots to words.
duke@0 984 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@0 985 // Round up to miminum stack alignment, in wordSize
duke@0 986 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@0 987 // Now compute the distance from Lesp to SP. This calculation does not
duke@0 988 // include the space for total_args_passed because Lesp has not yet popped
duke@0 989 // the arguments.
duke@0 990 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@0 991 }
duke@0 992
duke@0 993 // Will jump to the compiled code just as if compiled code was doing it.
duke@0 994 // Pre-load the register-jump target early, to schedule it better.
duke@0 995 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@0 996
duke@0 997 // Now generate the shuffle code. Pick up all register args and move the
duke@0 998 // rest through G1_scratch.
duke@0 999 for (int i=0; i<total_args_passed; i++) {
duke@0 1000 if (sig_bt[i] == T_VOID) {
duke@0 1001 // Longs and doubles are passed in native word order, but misaligned
duke@0 1002 // in the 32-bit build.
duke@0 1003 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@0 1004 continue;
duke@0 1005 }
duke@0 1006
duke@0 1007 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@0 1008 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@0 1009 // ldx/lddf optimizations.
duke@0 1010
duke@0 1011 // Load in argument order going down.
twisti@1401 1012 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1013 set_Rdisp(G1_scratch);
duke@0 1014
duke@0 1015 VMReg r_1 = regs[i].first();
duke@0 1016 VMReg r_2 = regs[i].second();
duke@0 1017 if (!r_1->is_valid()) {
duke@0 1018 assert(!r_2->is_valid(), "");
duke@0 1019 continue;
duke@0 1020 }
duke@0 1021 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@0 1022 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@0 1023 if (r_2->is_valid()) r_2 = r_1->next();
duke@0 1024 }
duke@0 1025 if (r_1->is_Register()) { // Register argument
duke@0 1026 Register r = r_1->as_Register()->after_restore();
duke@0 1027 if (!r_2->is_valid()) {
duke@0 1028 __ ld(Gargs, arg_slot(ld_off), r);
duke@0 1029 } else {
duke@0 1030 #ifdef _LP64
duke@0 1031 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 1032 // data is passed in only 1 slot.
twisti@991 1033 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
duke@0 1034 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1035 __ ldx(Gargs, slot, r);
duke@0 1036 #else
duke@0 1037 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@0 1038 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@0 1039 #endif
duke@0 1040 }
duke@0 1041 } else {
duke@0 1042 assert(r_1->is_FloatRegister(), "");
duke@0 1043 if (!r_2->is_valid()) {
duke@0 1044 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1045 } else {
duke@0 1046 #ifdef _LP64
duke@0 1047 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 1048 // data is passed in only 1 slot. This code also handles longs that
duke@0 1049 // are passed on the stack, but need a stack-to-stack move through a
duke@0 1050 // spare float register.
twisti@991 1051 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@0 1052 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1053 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@0 1054 #else
duke@0 1055 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1056 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1057 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@0 1058 #endif
duke@0 1059 }
duke@0 1060 }
duke@0 1061 // Was the argument really intended to be on the stack, but was loaded
duke@0 1062 // into F8/F9?
duke@0 1063 if (regs[i].first()->is_stack()) {
duke@0 1064 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@0 1065 // Convert stack slot to an SP offset
duke@0 1066 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@0 1067 // Store down the shuffled stack word. Target address _is_ aligned.
twisti@991 1068 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
twisti@991 1069 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
twisti@991 1070 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
duke@0 1071 }
duke@0 1072 }
duke@0 1073 bool made_space = false;
duke@0 1074 #ifndef _LP64
duke@0 1075 // May need to pick up a few long args in G1/G4
duke@0 1076 bool g4_crushed = false;
duke@0 1077 bool g3_crushed = false;
duke@0 1078 for (int i=0; i<total_args_passed; i++) {
duke@0 1079 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@0 1080 // Load in argument order going down
twisti@1401 1081 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1082 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1083 Register r = regs[i].first()->as_Register()->after_restore();
duke@0 1084 if (r == G1 || r == G4) {
duke@0 1085 assert(!g4_crushed, "ordering problem");
duke@0 1086 if (r == G4){
duke@0 1087 g4_crushed = true;
duke@0 1088 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1089 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1090 } else {
duke@0 1091 // better schedule this way
duke@0 1092 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1093 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1094 }
duke@0 1095 g3_crushed = true;
duke@0 1096 __ sllx(r, 32, r);
duke@0 1097 __ or3(G3_scratch, r, r);
duke@0 1098 } else {
duke@0 1099 assert(r->is_out(), "longs passed in two O registers");
duke@0 1100 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@0 1101 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1102 }
duke@0 1103 }
duke@0 1104 }
duke@0 1105 #endif
duke@0 1106
duke@0 1107 // Jump to the compiled code just as if compiled code was doing it.
duke@0 1108 //
duke@0 1109 #ifndef _LP64
duke@0 1110 if (g3_crushed) {
duke@0 1111 // Rats load was wasted, at least it is in cache...
twisti@720 1112 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
duke@0 1113 }
duke@0 1114 #endif /* _LP64 */
duke@0 1115
duke@0 1116 // 6243940 We might end up in handle_wrong_method if
duke@0 1117 // the callee is deoptimized as we race thru here. If that
duke@0 1118 // happens we don't want to take a safepoint because the
duke@0 1119 // caller frame will look interpreted and arguments are now
duke@0 1120 // "compiled" so it is much better to make this transition
duke@0 1121 // invisible to the stack walking code. Unfortunately if
duke@0 1122 // we try and find the callee by normal means a safepoint
duke@0 1123 // is possible. So we stash the desired callee in the thread
duke@0 1124 // and the vm will find there should this case occur.
twisti@720 1125 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
duke@0 1126 __ st_ptr(G5_method, callee_target_addr);
duke@0 1127
duke@0 1128 if (StressNonEntrant) {
duke@0 1129 // Open a big window for deopt failure
duke@0 1130 __ save_frame(0);
duke@0 1131 __ mov(G0, L0);
duke@0 1132 Label loop;
duke@0 1133 __ bind(loop);
duke@0 1134 __ sub(L0, 1, L0);
duke@0 1135 __ br_null(L0, false, Assembler::pt, loop);
duke@0 1136 __ delayed()->nop();
duke@0 1137
duke@0 1138 __ restore();
duke@0 1139 }
duke@0 1140
duke@0 1141
duke@0 1142 __ jmpl(G3, 0, G0);
duke@0 1143 __ delayed()->nop();
duke@0 1144 }
duke@0 1145
duke@0 1146 // ---------------------------------------------------------------
duke@0 1147 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@0 1148 int total_args_passed,
duke@0 1149 // VMReg max_arg,
duke@0 1150 int comp_args_on_stack, // VMRegStackSlots
duke@0 1151 const BasicType *sig_bt,
never@1179 1152 const VMRegPair *regs,
never@1179 1153 AdapterFingerPrint* fingerprint) {
duke@0 1154 address i2c_entry = __ pc();
duke@0 1155
duke@0 1156 AdapterGenerator agen(masm);
duke@0 1157
duke@0 1158 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@0 1159
duke@0 1160
duke@0 1161 // -------------------------------------------------------------------------
duke@0 1162 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
duke@0 1163 // args start out packed in the compiled layout. They need to be unpacked
duke@0 1164 // into the interpreter layout. This will almost always require some stack
duke@0 1165 // space. We grow the current (compiled) stack, then repack the args. We
duke@0 1166 // finally end in a jump to the generic interpreter entry point. On exit
duke@0 1167 // from the interpreter, the interpreter will restore our SP (lest the
duke@0 1168 // compiled code, which relys solely on SP and not FP, get sick).
duke@0 1169
duke@0 1170 address c2i_unverified_entry = __ pc();
duke@0 1171 Label skip_fixup;
duke@0 1172 {
duke@0 1173 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1174 Register R_temp = L0; // another scratch register
duke@0 1175 #else
duke@0 1176 Register R_temp = G1; // another scratch register
duke@0 1177 #endif
duke@0 1178
twisti@720 1179 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1180
duke@0 1181 __ verify_oop(O0);
duke@0 1182 __ verify_oop(G5_method);
coleenp@108 1183 __ load_klass(O0, G3_scratch);
duke@0 1184 __ verify_oop(G3_scratch);
duke@0 1185
duke@0 1186 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1187 __ save(SP, -frame::register_save_words*wordSize, SP);
duke@0 1188 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1189 __ verify_oop(R_temp);
duke@0 1190 __ cmp(G3_scratch, R_temp);
duke@0 1191 __ restore();
duke@0 1192 #else
duke@0 1193 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1194 __ verify_oop(R_temp);
duke@0 1195 __ cmp(G3_scratch, R_temp);
duke@0 1196 #endif
duke@0 1197
duke@0 1198 Label ok, ok2;
duke@0 1199 __ brx(Assembler::equal, false, Assembler::pt, ok);
duke@0 1200 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
twisti@720 1201 __ jump_to(ic_miss, G3_scratch);
duke@0 1202 __ delayed()->nop();
duke@0 1203
duke@0 1204 __ bind(ok);
duke@0 1205 // Method might have been compiled since the call site was patched to
duke@0 1206 // interpreted if that is the case treat it as a miss so we can get
duke@0 1207 // the call site corrected.
duke@0 1208 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 1209 __ bind(ok2);
duke@0 1210 __ br_null(G3_scratch, false, __ pt, skip_fixup);
duke@0 1211 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
twisti@720 1212 __ jump_to(ic_miss, G3_scratch);
duke@0 1213 __ delayed()->nop();
duke@0 1214
duke@0 1215 }
duke@0 1216
duke@0 1217 address c2i_entry = __ pc();
duke@0 1218
duke@0 1219 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@0 1220
duke@0 1221 __ flush();
never@1179 1222 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
duke@0 1223
duke@0 1224 }
duke@0 1225
duke@0 1226 // Helper function for native calling conventions
duke@0 1227 static VMReg int_stk_helper( int i ) {
duke@0 1228 // Bias any stack based VMReg we get by ignoring the window area
duke@0 1229 // but not the register parameter save area.
duke@0 1230 //
duke@0 1231 // This is strange for the following reasons. We'd normally expect
duke@0 1232 // the calling convention to return an VMReg for a stack slot
duke@0 1233 // completely ignoring any abi reserved area. C2 thinks of that
duke@0 1234 // abi area as only out_preserve_stack_slots. This does not include
duke@0 1235 // the area allocated by the C abi to store down integer arguments
duke@0 1236 // because the java calling convention does not use it. So
duke@0 1237 // since c2 assumes that there are only out_preserve_stack_slots
duke@0 1238 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@0 1239 // location the c calling convention must add in this bias amount
duke@0 1240 // to make up for the fact that the out_preserve_stack_slots is
duke@0 1241 // insufficient for C calls. What a mess. I sure hope those 6
duke@0 1242 // stack words were worth it on every java call!
duke@0 1243
duke@0 1244 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@0 1245 // to take a parameter to say whether it was C or java calling conventions.
duke@0 1246 // Then things might look a little better (but not much).
duke@0 1247
duke@0 1248 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@0 1249 if( mem_parm_offset < 0 ) {
duke@0 1250 return as_oRegister(i)->as_VMReg();
duke@0 1251 } else {
duke@0 1252 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@0 1253 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@0 1254 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@0 1255 }
duke@0 1256 }
duke@0 1257
duke@0 1258
duke@0 1259 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@0 1260 VMRegPair *regs,
duke@0 1261 int total_args_passed) {
duke@0 1262
duke@0 1263 // Return the number of VMReg stack_slots needed for the args.
duke@0 1264 // This value does not include an abi space (like register window
duke@0 1265 // save area).
duke@0 1266
duke@0 1267 // The native convention is V8 if !LP64
duke@0 1268 // The LP64 convention is the V9 convention which is slightly more sane.
duke@0 1269
duke@0 1270 // We return the amount of VMReg stack slots we need to reserve for all
duke@0 1271 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@0 1272 // have space for storing at least 6 registers to memory we start with that.
duke@0 1273 // See int_stk_helper for a further discussion.
duke@0 1274 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@0 1275
duke@0 1276 #ifdef _LP64
duke@0 1277 // V9 convention: All things "as-if" on double-wide stack slots.
duke@0 1278 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@0 1279 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@0 1280 int j = 0; // Count of actual args, not HALVES
duke@0 1281 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@0 1282 switch( sig_bt[i] ) {
duke@0 1283 case T_BOOLEAN:
duke@0 1284 case T_BYTE:
duke@0 1285 case T_CHAR:
duke@0 1286 case T_INT:
duke@0 1287 case T_SHORT:
duke@0 1288 regs[i].set1( int_stk_helper( j ) ); break;
duke@0 1289 case T_LONG:
duke@0 1290 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1291 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1292 case T_ARRAY:
duke@0 1293 case T_OBJECT:
duke@0 1294 regs[i].set2( int_stk_helper( j ) );
duke@0 1295 break;
duke@0 1296 case T_FLOAT:
duke@0 1297 if ( j < 16 ) {
duke@0 1298 // V9ism: floats go in ODD registers
duke@0 1299 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@0 1300 } else {
duke@0 1301 // V9ism: floats go in ODD stack slot
duke@0 1302 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@0 1303 }
duke@0 1304 break;
duke@0 1305 case T_DOUBLE:
duke@0 1306 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1307 if ( j < 16 ) {
duke@0 1308 // V9ism: doubles go in EVEN/ODD regs
duke@0 1309 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@0 1310 } else {
duke@0 1311 // V9ism: doubles go in EVEN/ODD stack slots
duke@0 1312 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@0 1313 }
duke@0 1314 break;
duke@0 1315 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@0 1316 default:
duke@0 1317 ShouldNotReachHere();
duke@0 1318 }
duke@0 1319 if (regs[i].first()->is_stack()) {
duke@0 1320 int off = regs[i].first()->reg2stack();
duke@0 1321 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1322 }
duke@0 1323 if (regs[i].second()->is_stack()) {
duke@0 1324 int off = regs[i].second()->reg2stack();
duke@0 1325 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1326 }
duke@0 1327 }
duke@0 1328
duke@0 1329 #else // _LP64
duke@0 1330 // V8 convention: first 6 things in O-regs, rest on stack.
duke@0 1331 // Alignment is willy-nilly.
duke@0 1332 for( int i=0; i<total_args_passed; i++ ) {
duke@0 1333 switch( sig_bt[i] ) {
duke@0 1334 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1335 case T_ARRAY:
duke@0 1336 case T_BOOLEAN:
duke@0 1337 case T_BYTE:
duke@0 1338 case T_CHAR:
duke@0 1339 case T_FLOAT:
duke@0 1340 case T_INT:
duke@0 1341 case T_OBJECT:
duke@0 1342 case T_SHORT:
duke@0 1343 regs[i].set1( int_stk_helper( i ) );
duke@0 1344 break;
duke@0 1345 case T_DOUBLE:
duke@0 1346 case T_LONG:
duke@0 1347 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1348 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@0 1349 break;
duke@0 1350 case T_VOID: regs[i].set_bad(); break;
duke@0 1351 default:
duke@0 1352 ShouldNotReachHere();
duke@0 1353 }
duke@0 1354 if (regs[i].first()->is_stack()) {
duke@0 1355 int off = regs[i].first()->reg2stack();
duke@0 1356 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1357 }
duke@0 1358 if (regs[i].second()->is_stack()) {
duke@0 1359 int off = regs[i].second()->reg2stack();
duke@0 1360 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1361 }
duke@0 1362 }
duke@0 1363 #endif // _LP64
duke@0 1364
duke@0 1365 return round_to(max_stack_slots + 1, 2);
duke@0 1366
duke@0 1367 }
duke@0 1368
duke@0 1369
duke@0 1370 // ---------------------------------------------------------------------------
duke@0 1371 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1372 switch (ret_type) {
duke@0 1373 case T_FLOAT:
duke@0 1374 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@0 1375 break;
duke@0 1376 case T_DOUBLE:
duke@0 1377 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@0 1378 break;
duke@0 1379 }
duke@0 1380 }
duke@0 1381
duke@0 1382 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1383 switch (ret_type) {
duke@0 1384 case T_FLOAT:
duke@0 1385 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@0 1386 break;
duke@0 1387 case T_DOUBLE:
duke@0 1388 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@0 1389 break;
duke@0 1390 }
duke@0 1391 }
duke@0 1392
duke@0 1393 // Check and forward and pending exception. Thread is stored in
duke@0 1394 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@0 1395 // is no exception handler. We merely pop this frame off and throw the
duke@0 1396 // exception in the caller's frame.
duke@0 1397 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@0 1398 Label L;
duke@0 1399 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@0 1400 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@0 1401 // Since this is a native call, we *know* the proper exception handler
duke@0 1402 // without calling into the VM: it's the empty function. Just pop this
duke@0 1403 // frame and then jump to forward_exception_entry; O7 will contain the
duke@0 1404 // native caller's return PC.
twisti@720 1405 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
twisti@720 1406 __ jump_to(exception_entry, G3_scratch);
duke@0 1407 __ delayed()->restore(); // Pop this frame off.
duke@0 1408 __ bind(L);
duke@0 1409 }
duke@0 1410
duke@0 1411 // A simple move of integer like type
duke@0 1412 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1413 if (src.first()->is_stack()) {
duke@0 1414 if (dst.first()->is_stack()) {
duke@0 1415 // stack to stack
duke@0 1416 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1417 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1418 } else {
duke@0 1419 // stack to reg
duke@0 1420 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1421 }
duke@0 1422 } else if (dst.first()->is_stack()) {
duke@0 1423 // reg to stack
duke@0 1424 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1425 } else {
duke@0 1426 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1427 }
duke@0 1428 }
duke@0 1429
duke@0 1430 // On 64 bit we will store integer like items to the stack as
duke@0 1431 // 64 bits items (sparc abi) even though java would only store
duke@0 1432 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@0 1433 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@0 1434 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1435 if (src.first()->is_stack()) {
duke@0 1436 if (dst.first()->is_stack()) {
duke@0 1437 // stack to stack
duke@0 1438 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1439 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1440 } else {
duke@0 1441 // stack to reg
duke@0 1442 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1443 }
duke@0 1444 } else if (dst.first()->is_stack()) {
duke@0 1445 // reg to stack
duke@0 1446 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1447 } else {
duke@0 1448 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1449 }
duke@0 1450 }
duke@0 1451
duke@0 1452
duke@0 1453 // An oop arg. Must pass a handle not the oop itself
duke@0 1454 static void object_move(MacroAssembler* masm,
duke@0 1455 OopMap* map,
duke@0 1456 int oop_handle_offset,
duke@0 1457 int framesize_in_slots,
duke@0 1458 VMRegPair src,
duke@0 1459 VMRegPair dst,
duke@0 1460 bool is_receiver,
duke@0 1461 int* receiver_offset) {
duke@0 1462
duke@0 1463 // must pass a handle. First figure out the location we use as a handle
duke@0 1464
duke@0 1465 if (src.first()->is_stack()) {
duke@0 1466 // Oop is already on the stack
duke@0 1467 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@0 1468 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@0 1469 __ ld_ptr(rHandle, 0, L4);
duke@0 1470 #ifdef _LP64
duke@0 1471 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@0 1472 #else
duke@0 1473 __ tst( L4 );
duke@0 1474 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1475 #endif
duke@0 1476 if (dst.first()->is_stack()) {
duke@0 1477 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1478 }
duke@0 1479 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@0 1480 if (is_receiver) {
duke@0 1481 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@0 1482 }
duke@0 1483 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@0 1484 } else {
duke@0 1485 // Oop is in an input register pass we must flush it to the stack
duke@0 1486 const Register rOop = src.first()->as_Register();
duke@0 1487 const Register rHandle = L5;
duke@0 1488 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@0 1489 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@0 1490 Label skip;
duke@0 1491 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@0 1492 if (is_receiver) {
duke@0 1493 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@0 1494 }
duke@0 1495 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@0 1496 __ add(SP, offset + STACK_BIAS, rHandle);
duke@0 1497 #ifdef _LP64
duke@0 1498 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@0 1499 #else
duke@0 1500 __ tst( rOop );
duke@0 1501 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1502 #endif
duke@0 1503
duke@0 1504 if (dst.first()->is_stack()) {
duke@0 1505 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1506 } else {
duke@0 1507 __ mov(rHandle, dst.first()->as_Register());
duke@0 1508 }
duke@0 1509 }
duke@0 1510 }
duke@0 1511
duke@0 1512 // A float arg may have to do float reg int reg conversion
duke@0 1513 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1514 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@0 1515
duke@0 1516 if (src.first()->is_stack()) {
duke@0 1517 if (dst.first()->is_stack()) {
duke@0 1518 // stack to stack the easiest of the bunch
duke@0 1519 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1520 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1521 } else {
duke@0 1522 // stack to reg
duke@0 1523 if (dst.first()->is_Register()) {
duke@0 1524 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1525 } else {
duke@0 1526 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1527 }
duke@0 1528 }
duke@0 1529 } else if (dst.first()->is_stack()) {
duke@0 1530 // reg to stack
duke@0 1531 if (src.first()->is_Register()) {
duke@0 1532 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1533 } else {
duke@0 1534 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1535 }
duke@0 1536 } else {
duke@0 1537 // reg to reg
duke@0 1538 if (src.first()->is_Register()) {
duke@0 1539 if (dst.first()->is_Register()) {
duke@0 1540 // gpr -> gpr
duke@0 1541 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1542 } else {
duke@0 1543 // gpr -> fpr
duke@0 1544 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1545 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1546 }
duke@0 1547 } else if (dst.first()->is_Register()) {
duke@0 1548 // fpr -> gpr
duke@0 1549 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@0 1550 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@0 1551 } else {
duke@0 1552 // fpr -> fpr
duke@0 1553 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1554 if ( src.first() != dst.first()) {
duke@0 1555 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1556 }
duke@0 1557 }
duke@0 1558 }
duke@0 1559 }
duke@0 1560
duke@0 1561 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1562 VMRegPair src_lo(src.first());
duke@0 1563 VMRegPair src_hi(src.second());
duke@0 1564 VMRegPair dst_lo(dst.first());
duke@0 1565 VMRegPair dst_hi(dst.second());
duke@0 1566 simple_move32(masm, src_lo, dst_lo);
duke@0 1567 simple_move32(masm, src_hi, dst_hi);
duke@0 1568 }
duke@0 1569
duke@0 1570 // A long move
duke@0 1571 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1572
duke@0 1573 // Do the simple ones here else do two int moves
duke@0 1574 if (src.is_single_phys_reg() ) {
duke@0 1575 if (dst.is_single_phys_reg()) {
duke@0 1576 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1577 } else {
duke@0 1578 // split src into two separate registers
duke@0 1579 // Remember hi means hi address or lsw on sparc
duke@0 1580 // Move msw to lsw
duke@0 1581 if (dst.second()->is_reg()) {
duke@0 1582 // MSW -> MSW
duke@0 1583 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@0 1584 // Now LSW -> LSW
duke@0 1585 // this will only move lo -> lo and ignore hi
duke@0 1586 VMRegPair split(dst.second());
duke@0 1587 simple_move32(masm, src, split);
duke@0 1588 } else {
duke@0 1589 VMRegPair split(src.first(), L4->as_VMReg());
duke@0 1590 // MSW -> MSW (lo ie. first word)
duke@0 1591 __ srax(src.first()->as_Register(), 32, L4);
duke@0 1592 split_long_move(masm, split, dst);
duke@0 1593 }
duke@0 1594 }
duke@0 1595 } else if (dst.is_single_phys_reg()) {
duke@0 1596 if (src.is_adjacent_aligned_on_stack(2)) {
never@297 1597 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1598 } else {
duke@0 1599 // dst is a single reg.
duke@0 1600 // Remember lo is low address not msb for stack slots
duke@0 1601 // and lo is the "real" register for registers
duke@0 1602 // src is
duke@0 1603
duke@0 1604 VMRegPair split;
duke@0 1605
duke@0 1606 if (src.first()->is_reg()) {
duke@0 1607 // src.lo (msw) is a reg, src.hi is stk/reg
duke@0 1608 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@0 1609 split.set_pair(dst.first(), src.first());
duke@0 1610 } else {
duke@0 1611 // msw is stack move to L5
duke@0 1612 // lsw is stack move to dst.lo (real reg)
duke@0 1613 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@0 1614 split.set_pair(dst.first(), L5->as_VMReg());
duke@0 1615 }
duke@0 1616
duke@0 1617 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@0 1618 // msw -> src.lo/L5, lsw -> dst.lo
duke@0 1619 split_long_move(masm, src, split);
duke@0 1620
duke@0 1621 // So dst now has the low order correct position the
duke@0 1622 // msw half
duke@0 1623 __ sllx(split.first()->as_Register(), 32, L5);
duke@0 1624
duke@0 1625 const Register d = dst.first()->as_Register();
duke@0 1626 __ or3(L5, d, d);
duke@0 1627 }
duke@0 1628 } else {
duke@0 1629 // For LP64 we can probably do better.
duke@0 1630 split_long_move(masm, src, dst);
duke@0 1631 }
duke@0 1632 }
duke@0 1633
duke@0 1634 // A double move
duke@0 1635 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1636
duke@0 1637 // The painful thing here is that like long_move a VMRegPair might be
duke@0 1638 // 1: a single physical register
duke@0 1639 // 2: two physical registers (v8)
duke@0 1640 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@0 1641 // 4: two stack slots
duke@0 1642
duke@0 1643 // Since src is always a java calling convention we know that the src pair
duke@0 1644 // is always either all registers or all stack (and aligned?)
duke@0 1645
duke@0 1646 // in a register [lo] and a stack slot [hi]
duke@0 1647 if (src.first()->is_stack()) {
duke@0 1648 if (dst.first()->is_stack()) {
duke@0 1649 // stack to stack the easiest of the bunch
duke@0 1650 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@0 1651 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1652 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1653 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1654 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1655 } else {
duke@0 1656 // stack to reg
duke@0 1657 if (dst.second()->is_stack()) {
duke@0 1658 // stack -> reg, stack -> stack
duke@0 1659 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1660 if (dst.first()->is_Register()) {
duke@0 1661 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1662 } else {
duke@0 1663 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1664 }
duke@0 1665 // This was missing. (very rare case)
duke@0 1666 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1667 } else {
duke@0 1668 // stack -> reg
duke@0 1669 // Eventually optimize for alignment QQQ
duke@0 1670 if (dst.first()->is_Register()) {
duke@0 1671 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1672 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@0 1673 } else {
duke@0 1674 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1675 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1676 }
duke@0 1677 }
duke@0 1678 }
duke@0 1679 } else if (dst.first()->is_stack()) {
duke@0 1680 // reg to stack
duke@0 1681 if (src.first()->is_Register()) {
duke@0 1682 // Eventually optimize for alignment QQQ
duke@0 1683 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1684 if (src.second()->is_stack()) {
duke@0 1685 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1686 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1687 } else {
duke@0 1688 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1689 }
duke@0 1690 } else {
duke@0 1691 // fpr to stack
duke@0 1692 if (src.second()->is_stack()) {
duke@0 1693 ShouldNotReachHere();
duke@0 1694 } else {
duke@0 1695 // Is the stack aligned?
duke@0 1696 if (reg2offset(dst.first()) & 0x7) {
duke@0 1697 // No do as pairs
duke@0 1698 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1699 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1700 } else {
duke@0 1701 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1702 }
duke@0 1703 }
duke@0 1704 }
duke@0 1705 } else {
duke@0 1706 // reg to reg
duke@0 1707 if (src.first()->is_Register()) {
duke@0 1708 if (dst.first()->is_Register()) {
duke@0 1709 // gpr -> gpr
duke@0 1710 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1711 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@0 1712 } else {
duke@0 1713 // gpr -> fpr
duke@0 1714 // ought to be able to do a single store
duke@0 1715 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@0 1716 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1717 // ought to be able to do a single load
duke@0 1718 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1719 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1720 }
duke@0 1721 } else if (dst.first()->is_Register()) {
duke@0 1722 // fpr -> gpr
duke@0 1723 // ought to be able to do a single store
duke@0 1724 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@0 1725 // ought to be able to do a single load
duke@0 1726 // REMEMBER first() is low address not LSB
duke@0 1727 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@0 1728 if (dst.second()->is_Register()) {
duke@0 1729 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@0 1730 } else {
duke@0 1731 __ ld(FP, -4 + STACK_BIAS, L4);
duke@0 1732 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1733 }
duke@0 1734 } else {
duke@0 1735 // fpr -> fpr
duke@0 1736 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1737 if ( src.first() != dst.first()) {
duke@0 1738 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1739 }
duke@0 1740 }
duke@0 1741 }
duke@0 1742 }
duke@0 1743
duke@0 1744 // Creates an inner frame if one hasn't already been created, and
duke@0 1745 // saves a copy of the thread in L7_thread_cache
duke@0 1746 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@0 1747 if (!*already_created) {
duke@0 1748 __ save_frame(0);
duke@0 1749 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@0 1750 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@0 1751 // copy
duke@0 1752 __ mov(G2_thread, L7_thread_cache);
duke@0 1753 *already_created = true;
duke@0 1754 }
duke@0 1755 }
duke@0 1756
duke@0 1757 // ---------------------------------------------------------------------------
duke@0 1758 // Generate a native wrapper for a given method. The method takes arguments
duke@0 1759 // in the Java compiled code convention, marshals them to the native
duke@0 1760 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@0 1761 // returns to java state (possibly blocking), unhandlizes any result and
duke@0 1762 // returns.
duke@0 1763 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@0 1764 methodHandle method,
duke@0 1765 int total_in_args,
duke@0 1766 int comp_args_on_stack, // in VMRegStackSlots
duke@0 1767 BasicType *in_sig_bt,
duke@0 1768 VMRegPair *in_regs,
duke@0 1769 BasicType ret_type) {
duke@0 1770
duke@0 1771 // Native nmethod wrappers never take possesion of the oop arguments.
duke@0 1772 // So the caller will gc the arguments. The only thing we need an
duke@0 1773 // oopMap for is if the call is static
duke@0 1774 //
duke@0 1775 // An OopMap for lock (and class if static), and one for the VM call itself
duke@0 1776 OopMapSet *oop_maps = new OopMapSet();
duke@0 1777 intptr_t start = (intptr_t)__ pc();
duke@0 1778
duke@0 1779 // First thing make an ic check to see if we should even be here
duke@0 1780 {
duke@0 1781 Label L;
duke@0 1782 const Register temp_reg = G3_scratch;
twisti@720 1783 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1784 __ verify_oop(O0);
coleenp@108 1785 __ load_klass(O0, temp_reg);
duke@0 1786 __ cmp(temp_reg, G5_inline_cache_reg);
duke@0 1787 __ brx(Assembler::equal, true, Assembler::pt, L);
duke@0 1788 __ delayed()->nop();
duke@0 1789
twisti@720 1790 __ jump_to(ic_miss, temp_reg);
duke@0 1791 __ delayed()->nop();
duke@0 1792 __ align(CodeEntryAlignment);
duke@0 1793 __ bind(L);
duke@0 1794 }
duke@0 1795
duke@0 1796 int vep_offset = ((intptr_t)__ pc()) - start;
duke@0 1797
duke@0 1798 #ifdef COMPILER1
duke@0 1799 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@0 1800 // Object.hashCode can pull the hashCode from the header word
duke@0 1801 // instead of doing a full VM transition once it's been computed.
duke@0 1802 // Since hashCode is usually polymorphic at call sites we can't do
duke@0 1803 // this optimization at the call site without a lot of work.
duke@0 1804 Label slowCase;
duke@0 1805 Register receiver = O0;
duke@0 1806 Register result = O0;
duke@0 1807 Register header = G3_scratch;
duke@0 1808 Register hash = G3_scratch; // overwrite header value with hash value
duke@0 1809 Register mask = G1; // to get hash field from header
duke@0 1810
duke@0 1811 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@0 1812 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@0 1813 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@0 1814 // vm: see markOop.hpp.
duke@0 1815 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@0 1816 __ sethi(markOopDesc::hash_mask, mask);
duke@0 1817 __ btst(markOopDesc::unlocked_value, header);
duke@0 1818 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@0 1819 if (UseBiasedLocking) {
duke@0 1820 // Check if biased and fall through to runtime if so
duke@0 1821 __ delayed()->nop();
duke@0 1822 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@0 1823 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@0 1824 }
duke@0 1825 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@0 1826
duke@0 1827 // Check for a valid (non-zero) hash code and get its value.
duke@0 1828 #ifdef _LP64
duke@0 1829 __ srlx(header, markOopDesc::hash_shift, hash);
duke@0 1830 #else
duke@0 1831 __ srl(header, markOopDesc::hash_shift, hash);
duke@0 1832 #endif
duke@0 1833 __ andcc(hash, mask, hash);
duke@0 1834 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@0 1835 __ delayed()->nop();
duke@0 1836
duke@0 1837 // leaf return.
duke@0 1838 __ retl();
duke@0 1839 __ delayed()->mov(hash, result);
duke@0 1840 __ bind(slowCase);
duke@0 1841 }
duke@0 1842 #endif // COMPILER1
duke@0 1843
duke@0 1844
duke@0 1845 // We have received a description of where all the java arg are located
duke@0 1846 // on entry to the wrapper. We need to convert these args to where
duke@0 1847 // the jni function will expect them. To figure out where they go
duke@0 1848 // we convert the java signature to a C signature by inserting
duke@0 1849 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@0 1850
duke@0 1851 int total_c_args = total_in_args + 1;
duke@0 1852 if (method->is_static()) {
duke@0 1853 total_c_args++;
duke@0 1854 }
duke@0 1855
duke@0 1856 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
duke@0 1857 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
duke@0 1858
duke@0 1859 int argc = 0;
duke@0 1860 out_sig_bt[argc++] = T_ADDRESS;
duke@0 1861 if (method->is_static()) {
duke@0 1862 out_sig_bt[argc++] = T_OBJECT;
duke@0 1863 }
duke@0 1864
duke@0 1865 for (int i = 0; i < total_in_args ; i++ ) {
duke@0 1866 out_sig_bt[argc++] = in_sig_bt[i];
duke@0 1867 }
duke@0 1868
duke@0 1869 // Now figure out where the args must be stored and how much stack space
duke@0 1870 // they require (neglecting out_preserve_stack_slots but space for storing
duke@0 1871 // the 1st six register arguments). It's weird see int_stk_helper.
duke@0 1872 //
duke@0 1873 int out_arg_slots;
duke@0 1874 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@0 1875
duke@0 1876 // Compute framesize for the wrapper. We need to handlize all oops in
duke@0 1877 // registers. We must create space for them here that is disjoint from
duke@0 1878 // the windowed save area because we have no control over when we might
duke@0 1879 // flush the window again and overwrite values that gc has since modified.
duke@0 1880 // (The live window race)
duke@0 1881 //
duke@0 1882 // We always just allocate 6 word for storing down these object. This allow
duke@0 1883 // us to simply record the base and use the Ireg number to decide which
duke@0 1884 // slot to use. (Note that the reg number is the inbound number not the
duke@0 1885 // outbound number).
duke@0 1886 // We must shuffle args to match the native convention, and include var-args space.
duke@0 1887
duke@0 1888 // Calculate the total number of stack slots we will need.
duke@0 1889
duke@0 1890 // First count the abi requirement plus all of the outgoing args
duke@0 1891 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@0 1892
duke@0 1893 // Now the space for the inbound oop handle area
duke@0 1894
duke@0 1895 int oop_handle_offset = stack_slots;
duke@0 1896 stack_slots += 6*VMRegImpl::slots_per_word;
duke@0 1897
duke@0 1898 // Now any space we need for handlizing a klass if static method
duke@0 1899
duke@0 1900 int oop_temp_slot_offset = 0;
duke@0 1901 int klass_slot_offset = 0;
duke@0 1902 int klass_offset = -1;
duke@0 1903 int lock_slot_offset = 0;
duke@0 1904 bool is_static = false;
duke@0 1905
duke@0 1906 if (method->is_static()) {
duke@0 1907 klass_slot_offset = stack_slots;
duke@0 1908 stack_slots += VMRegImpl::slots_per_word;
duke@0 1909 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@0 1910 is_static = true;
duke@0 1911 }
duke@0 1912
duke@0 1913 // Plus a lock if needed
duke@0 1914
duke@0 1915 if (method->is_synchronized()) {
duke@0 1916 lock_slot_offset = stack_slots;
duke@0 1917 stack_slots += VMRegImpl::slots_per_word;
duke@0 1918 }
duke@0 1919
duke@0 1920 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@0 1921 stack_slots += 2;
duke@0 1922
duke@0 1923 // Ok The space we have allocated will look like:
duke@0 1924 //
duke@0 1925 //
duke@0 1926 // FP-> | |
duke@0 1927 // |---------------------|
duke@0 1928 // | 2 slots for moves |
duke@0 1929 // |---------------------|
duke@0 1930 // | lock box (if sync) |
duke@0 1931 // |---------------------| <- lock_slot_offset
duke@0 1932 // | klass (if static) |
duke@0 1933 // |---------------------| <- klass_slot_offset
duke@0 1934 // | oopHandle area |
duke@0 1935 // |---------------------| <- oop_handle_offset
duke@0 1936 // | outbound memory |
duke@0 1937 // | based arguments |
duke@0 1938 // | |
duke@0 1939 // |---------------------|
duke@0 1940 // | vararg area |
duke@0 1941 // |---------------------|
duke@0 1942 // | |
duke@0 1943 // SP-> | out_preserved_slots |
duke@0 1944 //
duke@0 1945 //
duke@0 1946
duke@0 1947
duke@0 1948 // Now compute actual number of stack words we need rounding to make
duke@0 1949 // stack properly aligned.
duke@0 1950 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@0 1951
duke@0 1952 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@0 1953
duke@0 1954 // Generate stack overflow check before creating frame
duke@0 1955 __ generate_stack_overflow_check(stack_size);
duke@0 1956
duke@0 1957 // Generate a new frame for the wrapper.
duke@0 1958 __ save(SP, -stack_size, SP);
duke@0 1959
duke@0 1960 int frame_complete = ((intptr_t)__ pc()) - start;
duke@0 1961
duke@0 1962 __ verify_thread();
duke@0 1963
duke@0 1964
duke@0 1965 //
duke@0 1966 // We immediately shuffle the arguments so that any vm call we have to
duke@0 1967 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@0 1968 // captured the oops from our caller and have a valid oopMap for
duke@0 1969 // them.
duke@0 1970
duke@0 1971 // -----------------
duke@0 1972 // The Grand Shuffle
duke@0 1973 //
duke@0 1974 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@0 1975 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@0 1976 // the class mirror instead of a receiver. This pretty much guarantees that
duke@0 1977 // register layout will not match. We ignore these extra arguments during
duke@0 1978 // the shuffle. The shuffle is described by the two calling convention
duke@0 1979 // vectors we have in our possession. We simply walk the java vector to
duke@0 1980 // get the source locations and the c vector to get the destinations.
duke@0 1981 // Because we have a new window and the argument registers are completely
duke@0 1982 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@0 1983 // here.
duke@0 1984
duke@0 1985 // This is a trick. We double the stack slots so we can claim
duke@0 1986 // the oops in the caller's frame. Since we are sure to have
duke@0 1987 // more args than the caller doubling is enough to make
duke@0 1988 // sure we can capture all the incoming oop args from the
duke@0 1989 // caller.
duke@0 1990 //
duke@0 1991 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@0 1992 int c_arg = total_c_args - 1;
duke@0 1993 // Record sp-based slot for receiver on stack for non-static methods
duke@0 1994 int receiver_offset = -1;
duke@0 1995
duke@0 1996 // We move the arguments backward because the floating point registers
duke@0 1997 // destination will always be to a register with a greater or equal register
duke@0 1998 // number or the stack.
duke@0 1999
duke@0 2000 #ifdef ASSERT
duke@0 2001 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@0 2002 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@0 2003 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@0 2004 reg_destroyed[r] = false;
duke@0 2005 }
duke@0 2006 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@0 2007 freg_destroyed[f] = false;
duke@0 2008 }
duke@0 2009
duke@0 2010 #endif /* ASSERT */
duke@0 2011
duke@0 2012 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@0 2013
duke@0 2014 #ifdef ASSERT
duke@0 2015 if (in_regs[i].first()->is_Register()) {
duke@0 2016 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@0 2017 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@0 2018 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@0 2019 }
duke@0 2020 if (out_regs[c_arg].first()->is_Register()) {
duke@0 2021 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@0 2022 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@0 2023 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@0 2024 }
duke@0 2025 #endif /* ASSERT */
duke@0 2026
duke@0 2027 switch (in_sig_bt[i]) {
duke@0 2028 case T_ARRAY:
duke@0 2029 case T_OBJECT:
duke@0 2030 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@0 2031 ((i == 0) && (!is_static)),
duke@0 2032 &receiver_offset);
duke@0 2033 break;
duke@0 2034 case T_VOID:
duke@0 2035 break;
duke@0 2036
duke@0 2037 case T_FLOAT:
duke@0 2038 float_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2039 break;
duke@0 2040
duke@0 2041 case T_DOUBLE:
duke@0 2042 assert( i + 1 < total_in_args &&
duke@0 2043 in_sig_bt[i + 1] == T_VOID &&
duke@0 2044 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@0 2045 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2046 break;
duke@0 2047
duke@0 2048 case T_LONG :
duke@0 2049 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2050 break;
duke@0 2051
duke@0 2052 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@0 2053
duke@0 2054 default:
duke@0 2055 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@0 2056 }
duke@0 2057 }
duke@0 2058
duke@0 2059 // Pre-load a static method's oop into O1. Used both by locking code and
duke@0 2060 // the normal JNI call code.
duke@0 2061 if (method->is_static()) {
duke@0 2062 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@0 2063
duke@0 2064 // Now handlize the static class mirror in O1. It's known not-null.
duke@0 2065 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@0 2066 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@0 2067 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@0 2068 }
duke@0 2069
duke@0 2070
duke@0 2071 const Register L6_handle = L6;
duke@0 2072
duke@0 2073 if (method->is_synchronized()) {
duke@0 2074 __ mov(O1, L6_handle);
duke@0 2075 }
duke@0 2076
duke@0 2077 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@0 2078 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@0 2079 // push a new frame and flush the windows.
duke@0 2080
duke@0 2081 #ifdef _LP64
duke@0 2082 intptr_t thepc = (intptr_t) __ pc();
duke@0 2083 {
duke@0 2084 address here = __ pc();
duke@0 2085 // Call the next instruction
duke@0 2086 __ call(here + 8, relocInfo::none);
duke@0 2087 __ delayed()->nop();
duke@0 2088 }
duke@0 2089 #else
duke@0 2090 intptr_t thepc = __ load_pc_address(O7, 0);
duke@0 2091 #endif /* _LP64 */
duke@0 2092
duke@0 2093 // We use the same pc/oopMap repeatedly when we call out
duke@0 2094 oop_maps->add_gc_map(thepc - start, map);
duke@0 2095
duke@0 2096 // O7 now has the pc loaded that we will use when we finally call to native.
duke@0 2097
duke@0 2098 // Save thread in L7; it crosses a bunch of VM calls below
duke@0 2099 // Don't use save_thread because it smashes G2 and we merely
duke@0 2100 // want to save a copy
duke@0 2101 __ mov(G2_thread, L7_thread_cache);
duke@0 2102
duke@0 2103
duke@0 2104 // If we create an inner frame once is plenty
duke@0 2105 // when we create it we must also save G2_thread
duke@0 2106 bool inner_frame_created = false;
duke@0 2107
duke@0 2108 // dtrace method entry support
duke@0 2109 {
duke@0 2110 SkipIfEqual skip_if(
duke@0 2111 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2112 // create inner frame
duke@0 2113 __ save_frame(0);
duke@0 2114 __ mov(G2_thread, L7_thread_cache);
duke@0 2115 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2116 __ call_VM_leaf(L7_thread_cache,
duke@0 2117 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@0 2118 G2_thread, O1);
duke@0 2119 __ restore();
duke@0 2120 }
duke@0 2121
dcubed@606 2122 // RedefineClasses() tracing support for obsolete method entry
dcubed@606 2123 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
dcubed@606 2124 // create inner frame
dcubed@606 2125 __ save_frame(0);
dcubed@606 2126 __ mov(G2_thread, L7_thread_cache);
dcubed@606 2127 __ set_oop_constant(JNIHandles::make_local(method()), O1);
dcubed@606 2128 __ call_VM_leaf(L7_thread_cache,
dcubed@606 2129 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
dcubed@606 2130 G2_thread, O1);
dcubed@606 2131 __ restore();
dcubed@606 2132 }
dcubed@606 2133
duke@0 2134 // We are in the jni frame unless saved_frame is true in which case
duke@0 2135 // we are in one frame deeper (the "inner" frame). If we are in the
duke@0 2136 // "inner" frames the args are in the Iregs and if the jni frame then
duke@0 2137 // they are in the Oregs.
duke@0 2138 // If we ever need to go to the VM (for locking, jvmti) then
duke@0 2139 // we will always be in the "inner" frame.
duke@0 2140
duke@0 2141 // Lock a synchronized method
duke@0 2142 int lock_offset = -1; // Set if locked
duke@0 2143 if (method->is_synchronized()) {
duke@0 2144 Register Roop = O1;
duke@0 2145 const Register L3_box = L3;
duke@0 2146
duke@0 2147 create_inner_frame(masm, &inner_frame_created);
duke@0 2148
duke@0 2149 __ ld_ptr(I1, 0, O1);
duke@0 2150 Label done;
duke@0 2151
duke@0 2152 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@0 2153 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2154 #ifdef ASSERT
duke@0 2155 if (UseBiasedLocking) {
duke@0 2156 // making the box point to itself will make it clear it went unused
duke@0 2157 // but also be obviously invalid
duke@0 2158 __ st_ptr(L3_box, L3_box, 0);
duke@0 2159 }
duke@0 2160 #endif // ASSERT
duke@0 2161 //
duke@0 2162 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@0 2163 //
duke@0 2164 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@0 2165 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2166 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2167
duke@0 2168
duke@0 2169 // None of the above fast optimizations worked so we have to get into the
duke@0 2170 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2171 // disallows any pending_exception.
duke@0 2172 __ mov(Roop, O0); // Need oop in O0
duke@0 2173 __ mov(L3_box, O1);
duke@0 2174
duke@0 2175 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@0 2176
duke@0 2177 __ set_last_Java_frame(FP, I7);
duke@0 2178
duke@0 2179 // do the call
duke@0 2180 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@0 2181 __ delayed()->mov(L7_thread_cache, O2);
duke@0 2182
duke@0 2183 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2184 __ reset_last_Java_frame();
duke@0 2185
duke@0 2186 #ifdef ASSERT
duke@0 2187 { Label L;
duke@0 2188 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
duke@0 2189 __ br_null(O0, false, Assembler::pt, L);
duke@0 2190 __ delayed()->nop();
duke@0 2191 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@0 2192 __ bind(L);
duke@0 2193 }
duke@0 2194 #endif
duke@0 2195 __ bind(done);
duke@0 2196 }
duke@0 2197
duke@0 2198
duke@0 2199 // Finally just about ready to make the JNI call
duke@0 2200
duke@0 2201 __ flush_windows();
duke@0 2202 if (inner_frame_created) {
duke@0 2203 __ restore();
duke@0 2204 } else {
duke@0 2205 // Store only what we need from this frame
duke@0 2206 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@0 2207 // either as the flush traps and the current window goes too.
duke@0 2208 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2209 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2210 }
duke@0 2211
duke@0 2212 // get JNIEnv* which is first argument to native
duke@0 2213
duke@0 2214 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
duke@0 2215
duke@0 2216 // Use that pc we placed in O7 a while back as the current frame anchor
duke@0 2217
duke@0 2218 __ set_last_Java_frame(SP, O7);
duke@0 2219
duke@0 2220 // Transition from _thread_in_Java to _thread_in_native.
duke@0 2221 __ set(_thread_in_native, G3_scratch);
twisti@720 2222 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2223
duke@0 2224 // We flushed the windows ages ago now mark them as flushed
duke@0 2225
duke@0 2226 // mark windows as flushed
duke@0 2227 __ set(JavaFrameAnchor::flushed, G3_scratch);
duke@0 2228
twisti@720 2229 Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
duke@0 2230
duke@0 2231 #ifdef _LP64
twisti@720 2232 AddressLiteral dest(method->native_function());
duke@0 2233 __ relocate(relocInfo::runtime_call_type);
twisti@720 2234 __ jumpl_to(dest, O7, O7);
duke@0 2235 #else
duke@0 2236 __ call(method->native_function(), relocInfo::runtime_call_type);
duke@0 2237 #endif
duke@0 2238 __ delayed()->st(G3_scratch, flags);
duke@0 2239
duke@0 2240 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2241
duke@0 2242 // Unpack native results. For int-types, we do any needed sign-extension
duke@0 2243 // and move things into I0. The return value there will survive any VM
duke@0 2244 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@0 2245 // specially in the slow-path code.
duke@0 2246 switch (ret_type) {
duke@0 2247 case T_VOID: break; // Nothing to do!
duke@0 2248 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@0 2249 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@0 2250 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@0 2251 case T_LONG:
duke@0 2252 #ifndef _LP64
duke@0 2253 __ mov(O1, I1);
duke@0 2254 #endif
duke@0 2255 // Fall thru
duke@0 2256 case T_OBJECT: // Really a handle
duke@0 2257 case T_ARRAY:
duke@0 2258 case T_INT:
duke@0 2259 __ mov(O0, I0);
duke@0 2260 break;
duke@0 2261 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@0 2262 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@0 2263 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@0 2264 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@0 2265 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@0 2266 default:
duke@0 2267 ShouldNotReachHere();
duke@0 2268 }
duke@0 2269
duke@0 2270 // must we block?
duke@0 2271
duke@0 2272 // Block, if necessary, before resuming in _thread_in_Java state.
duke@0 2273 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@0 2274 { Label no_block;
twisti@720 2275 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
duke@0 2276
duke@0 2277 // Switch thread to "native transition" state before reading the synchronization state.
duke@0 2278 // This additional state is necessary because reading and testing the synchronization
duke@0 2279 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@0 2280 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@0 2281 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@0 2282 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@0 2283 // didn't see any synchronization is progress, and escapes.
duke@0 2284 __ set(_thread_in_native_trans, G3_scratch);
twisti@720 2285 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2286 if(os::is_MP()) {
duke@0 2287 if (UseMembar) {
duke@0 2288 // Force this write out before the read below
duke@0 2289 __ membar(Assembler::StoreLoad);
duke@0 2290 } else {
duke@0 2291 // Write serialization page so VM thread can do a pseudo remote membar.
duke@0 2292 // We use the current thread pointer to calculate a thread specific
duke@0 2293 // offset to write to within the page. This minimizes bus traffic
duke@0 2294 // due to cache line collision.
duke@0 2295 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@0 2296 }
duke@0 2297 }
duke@0 2298 __ load_contents(sync_state, G3_scratch);
duke@0 2299 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@0 2300
duke@0 2301 Label L;
twisti@720 2302 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
duke@0 2303 __ br(Assembler::notEqual, false, Assembler::pn, L);
twisti@720 2304 __ delayed()->ld(suspend_state, G3_scratch);
duke@0 2305 __ cmp(G3_scratch, 0);
duke@0 2306 __ br(Assembler::equal, false, Assembler::pt, no_block);
duke@0 2307 __ delayed()->nop();
duke@0 2308 __ bind(L);
duke@0 2309
duke@0 2310 // Block. Save any potential method result value before the operation and
duke@0 2311 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@0 2312 // lets us share the oopMap we used when we went native rather the create
duke@0 2313 // a distinct one for this pc
duke@0 2314 //
duke@0 2315 save_native_result(masm, ret_type, stack_slots);
duke@0 2316 __ call_VM_leaf(L7_thread_cache,
duke@0 2317 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
duke@0 2318 G2_thread);
duke@0 2319
duke@0 2320 // Restore any method result value
duke@0 2321 restore_native_result(masm, ret_type, stack_slots);
duke@0 2322 __ bind(no_block);
duke@0 2323 }
duke@0 2324
duke@0 2325 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@0 2326 // happened so we can now change state to _thread_in_Java.
duke@0 2327
duke@0 2328
duke@0 2329 __ set(_thread_in_Java, G3_scratch);
twisti@720 2330 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2331
duke@0 2332
duke@0 2333 Label no_reguard;
twisti@720 2334 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
duke@0 2335 __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
duke@0 2336 __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
duke@0 2337 __ delayed()->nop();
duke@0 2338
duke@0 2339 save_native_result(masm, ret_type, stack_slots);
duke@0 2340 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@0 2341 __ delayed()->nop();
duke@0 2342
duke@0 2343 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2344 restore_native_result(masm, ret_type, stack_slots);
duke@0 2345
duke@0 2346 __ bind(no_reguard);
duke@0 2347
duke@0 2348 // Handle possible exception (will unlock if necessary)
duke@0 2349
duke@0 2350 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@0 2351
duke@0 2352 // Unlock
duke@0 2353 if (method->is_synchronized()) {
duke@0 2354 Label done;
duke@0 2355 Register I2_ex_oop = I2;
duke@0 2356 const Register L3_box = L3;
duke@0 2357 // Get locked oop from the handle we passed to jni
duke@0 2358 __ ld_ptr(L6_handle, 0, L4);
duke@0 2359 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2360 // Must save pending exception around the slow-path VM call. Since it's a
duke@0 2361 // leaf call, the pending exception (if any) can be kept in a register.
duke@0 2362 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@0 2363 // Now unlock
duke@0 2364 // (Roop, Rmark, Rbox, Rscratch)
duke@0 2365 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@0 2366 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2367 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2368
duke@0 2369 // save and restore any potential method result value around the unlocking
duke@0 2370 // operation. Will save in I0 (or stack for FP returns).
duke@0 2371 save_native_result(masm, ret_type, stack_slots);
duke@0 2372
duke@0 2373 // Must clear pending-exception before re-entering the VM. Since this is
duke@0 2374 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@0 2375 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2376
duke@0 2377 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2378 // disallows any pending_exception.
duke@0 2379 __ mov(L3_box, O1);
duke@0 2380
duke@0 2381 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@0 2382 __ delayed()->mov(L4, O0); // Need oop in O0
duke@0 2383
duke@0 2384 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2385
duke@0 2386 #ifdef ASSERT
duke@0 2387 { Label L;
duke@0 2388 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
duke@0 2389 __ br_null(O0, false, Assembler::pt, L);
duke@0 2390 __ delayed()->nop();
duke@0 2391 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@0 2392 __ bind(L);
duke@0 2393 }
duke@0 2394 #endif
duke@0 2395 restore_native_result(masm, ret_type, stack_slots);
duke@0 2396 // check_forward_pending_exception jump to forward_exception if any pending
duke@0 2397 // exception is set. The forward_exception routine expects to see the
duke@0 2398 // exception in pending_exception and not in a register. Kind of clumsy,
duke@0 2399 // since all folks who branch to forward_exception must have tested
duke@0 2400 // pending_exception first and hence have it in a register already.
duke@0 2401 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2402 __ bind(done);
duke@0 2403 }
duke@0 2404
duke@0 2405 // Tell dtrace about this method exit
duke@0 2406 {
duke@0 2407 SkipIfEqual skip_if(
duke@0 2408 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2409 save_native_result(masm, ret_type, stack_slots);
duke@0 2410 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2411 __ call_VM_leaf(L7_thread_cache,
duke@0 2412 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@0 2413 G2_thread, O1);
duke@0 2414 restore_native_result(masm, ret_type, stack_slots);
duke@0 2415 }
duke@0 2416
duke@0 2417 // Clear "last Java frame" SP and PC.
duke@0 2418 __ verify_thread(); // G2_thread must be correct
duke@0 2419 __ reset_last_Java_frame();
duke@0 2420
duke@0 2421 // Unpack oop result
duke@0 2422 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@0 2423 Label L;
duke@0 2424 __ addcc(G0, I0, G0);
duke@0 2425 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@0 2426 __ delayed()->ld_ptr(I0, 0, I0);
duke@0 2427 __ mov(G0, I0);
duke@0 2428 __ bind(L);
duke@0 2429 __ verify_oop(I0);
duke@0 2430 }
duke@0 2431
duke@0 2432 // reset handle block
duke@0 2433 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
duke@0 2434 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
duke@0 2435
duke@0 2436 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
duke@0 2437 check_forward_pending_exception(masm, G3_scratch);
duke@0 2438
duke@0 2439
duke@0 2440 // Return
duke@0 2441
duke@0 2442 #ifndef _LP64
duke@0 2443 if (ret_type == T_LONG) {
duke@0 2444
duke@0 2445 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@0 2446 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 2447 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 2448 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 2449 }
duke@0 2450 #endif
duke@0 2451
duke@0 2452 __ ret();
duke@0 2453 __ delayed()->restore();
duke@0 2454
duke@0 2455 __ flush();
duke@0 2456
duke@0 2457 nmethod *nm = nmethod::new_native_nmethod(method,
duke@0 2458 masm->code(),
duke@0 2459 vep_offset,
duke@0 2460 frame_complete,
duke@0 2461 stack_slots / VMRegImpl::slots_per_word,
duke@0 2462 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@0 2463 in_ByteSize(lock_offset),
duke@0 2464 oop_maps);
duke@0 2465 return nm;
duke@0 2466
duke@0 2467 }
duke@0 2468
kamg@124 2469 #ifdef HAVE_DTRACE_H
kamg@124 2470 // ---------------------------------------------------------------------------
kamg@124 2471 // Generate a dtrace nmethod for a given signature. The method takes arguments
kamg@124 2472 // in the Java compiled code convention, marshals them to the native
kamg@124 2473 // abi and then leaves nops at the position you would expect to call a native
kamg@124 2474 // function. When the probe is enabled the nops are replaced with a trap
kamg@124 2475 // instruction that dtrace inserts and the trace will cause a notification
kamg@124 2476 // to dtrace.
kamg@124 2477 //
kamg@124 2478 // The probes are only able to take primitive types and java/lang/String as
kamg@124 2479 // arguments. No other java types are allowed. Strings are converted to utf8
kamg@124 2480 // strings so that from dtrace point of view java strings are converted to C
kamg@124 2481 // strings. There is an arbitrary fixed limit on the total space that a method
kamg@124 2482 // can use for converting the strings. (256 chars per string in the signature).
kamg@124 2483 // So any java string larger then this is truncated.
kamg@124 2484
kamg@124 2485 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
kamg@124 2486 static bool offsets_initialized = false;
kamg@124 2487
kamg@124 2488 static VMRegPair reg64_to_VMRegPair(Register r) {
kamg@124 2489 VMRegPair ret;
kamg@124 2490 if (wordSize == 8) {
kamg@124 2491 ret.set2(r->as_VMReg());
kamg@124 2492 } else {
kamg@124 2493 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
kamg@124 2494 }
kamg@124 2495 return ret;
kamg@124 2496 }
kamg@124 2497
kamg@124 2498
kamg@124 2499 nmethod *SharedRuntime::generate_dtrace_nmethod(
kamg@124 2500 MacroAssembler *masm, methodHandle method) {
kamg@124 2501
kamg@124 2502
kamg@124 2503 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
kamg@124 2504 // be single threaded in this method.
kamg@124 2505 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
kamg@124 2506
kamg@124 2507 // Fill in the signature array, for the calling-convention call.
kamg@124 2508 int total_args_passed = method->size_of_parameters();
kamg@124 2509
kamg@124 2510 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
kamg@124 2511 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
kamg@124 2512
kamg@124 2513 // The signature we are going to use for the trap that dtrace will see
kamg@124 2514 // java/lang/String is converted. We drop "this" and any other object
kamg@124 2515 // is converted to NULL. (A one-slot java/lang/Long object reference
kamg@124 2516 // is converted to a two-slot long, which is why we double the allocation).
kamg@124 2517 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
kamg@124 2518 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
kamg@124 2519
kamg@124 2520 int i=0;
kamg@124 2521 int total_strings = 0;
kamg@124 2522 int first_arg_to_pass = 0;
kamg@124 2523 int total_c_args = 0;
kamg@124 2524
kamg@124 2525 // Skip the receiver as dtrace doesn't want to see it
kamg@124 2526 if( !method->is_static() ) {
kamg@124 2527 in_sig_bt[i++] = T_OBJECT;
kamg@124 2528 first_arg_to_pass = 1;
kamg@124 2529 }
kamg@124 2530
kamg@124 2531 SignatureStream ss(method->signature());
kamg@124 2532 for ( ; !ss.at_return_type(); ss.next()) {
kamg@124 2533 BasicType bt = ss.type();
kamg@124 2534 in_sig_bt[i++] = bt; // Collect remaining bits of signature
kamg@124 2535 out_sig_bt[total_c_args++] = bt;
kamg@124 2536 if( bt == T_OBJECT) {
kamg@124 2537 symbolOop s = ss.as_symbol_or_null();
kamg@124 2538 if (s == vmSymbols::java_lang_String()) {
kamg@124 2539 total_strings++;
kamg@124 2540 out_sig_bt[total_c_args-1] = T_ADDRESS;
kamg@124 2541 } else if (s == vmSymbols::java_lang_Boolean() ||
kamg@124 2542 s == vmSymbols::java_lang_Byte()) {
kamg@124 2543 out_sig_bt[total_c_args-1] = T_BYTE;
kamg@124 2544 } else if (s == vmSymbols::java_lang_Character() ||
kamg@124 2545 s == vmSymbols::java_lang_Short()) {
kamg@124 2546 out_sig_bt[total_c_args-1] = T_SHORT;
kamg@124 2547 } else if (s == vmSymbols::java_lang_Integer() ||
kamg@124 2548 s == vmSymbols::java_lang_Float()) {
kamg@124 2549 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2550 } else if (s == vmSymbols::java_lang_Long() ||
kamg@124 2551 s == vmSymbols::java_lang_Double()) {
kamg@124 2552 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2553 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2554 }
kamg@124 2555 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
kamg@124 2556 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
kamg@124 2557 // We convert double to long
kamg@124 2558 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2559 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2560 } else if ( bt == T_FLOAT) {
kamg@124 2561 // We convert float to int
kamg@124 2562 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2563 }
kamg@124 2564 }
kamg@124 2565
kamg@124 2566 assert(i==total_args_passed, "validly parsed signature");
kamg@124 2567
kamg@124 2568 // Now get the compiled-Java layout as input arguments
kamg@124 2569 int comp_args_on_stack;
kamg@124 2570 comp_args_on_stack = SharedRuntime::java_calling_convention(
kamg@124 2571 in_sig_bt, in_regs, total_args_passed, false);
kamg@124 2572
kamg@124 2573 // We have received a description of where all the java arg are located
kamg@124 2574 // on entry to the wrapper. We need to convert these args to where
kamg@124 2575 // the a native (non-jni) function would expect them. To figure out
kamg@124 2576 // where they go we convert the java signature to a C signature and remove
kamg@124 2577 // T_VOID for any long/double we might have received.
kamg@124 2578
kamg@124 2579
kamg@124 2580 // Now figure out where the args must be stored and how much stack space
kamg@124 2581 // they require (neglecting out_preserve_stack_slots but space for storing
kamg@124 2582 // the 1st six register arguments). It's weird see int_stk_helper.
kamg@124 2583 //
kamg@124 2584 int out_arg_slots;
kamg@124 2585 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
kamg@124 2586
kamg@124 2587 // Calculate the total number of stack slots we will need.
kamg@124 2588
kamg@124 2589 // First count the abi requirement plus all of the outgoing args
kamg@124 2590 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
kamg@124 2591
kamg@124 2592 // Plus a temp for possible converion of float/double/long register args
kamg@124 2593
kamg@124 2594 int conversion_temp = stack_slots;
kamg@124 2595 stack_slots += 2;
kamg@124 2596
kamg@124 2597
kamg@124 2598 // Now space for the string(s) we must convert
kamg@124 2599
kamg@124 2600 int string_locs = stack_slots;
kamg@124 2601 stack_slots += total_strings *
kamg@124 2602 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
kamg@124 2603
kamg@124 2604 // Ok The space we have allocated will look like:
kamg@124 2605 //
kamg@124 2606 //
kamg@124 2607 // FP-> | |
kamg@124 2608 // |---------------------|
kamg@124 2609 // | string[n] |
kamg@124 2610 // |---------------------| <- string_locs[n]
kamg@124 2611 // | string[n-1] |
kamg@124 2612 // |---------------------| <- string_locs[n-1]
kamg@124 2613 // | ... |
kamg@124 2614 // | ... |
kamg@124 2615 // |---------------------| <- string_locs[1]
kamg@124 2616 // | string[0] |
kamg@124 2617 // |---------------------| <- string_locs[0]
kamg@124 2618 // | temp |
kamg@124 2619 // |---------------------| <- conversion_temp
kamg@124 2620 // | outbound memory |
kamg@124 2621 // | based arguments |
kamg@124 2622 // | |
kamg@124 2623 // |---------------------|
kamg@124 2624 // | |
kamg@124 2625 // SP-> | out_preserved_slots |
kamg@124 2626 //
kamg@124 2627 //
kamg@124 2628
kamg@124 2629 // Now compute actual number of stack words we need rounding to make
kamg@124 2630 // stack properly aligned.
kamg@124 2631 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
kamg@124 2632
kamg@124 2633 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
kamg@124 2634
kamg@124 2635 intptr_t start = (intptr_t)__ pc();
kamg@124 2636
kamg@124 2637 // First thing make an ic check to see if we should even be here
kamg@124 2638
kamg@124 2639 {
kamg@124 2640 Label L;
kamg@124 2641 const Register temp_reg = G3_scratch;
twisti@720 2642 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
kamg@124 2643 __ verify_oop(O0);
kamg@124 2644 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
kamg@124 2645 __ cmp(temp_reg, G5_inline_cache_reg);
kamg@124 2646 __ brx(Assembler::equal, true, Assembler::pt, L);
kamg@124 2647 __ delayed()->nop();
kamg@124 2648
twisti@720 2649 __ jump_to(ic_miss, temp_reg);
kamg@124 2650 __ delayed()->nop();
kamg@124 2651 __ align(CodeEntryAlignment);
kamg@124 2652 __ bind(L);
kamg@124 2653 }
kamg@124 2654
kamg@124 2655 int vep_offset = ((intptr_t)__ pc()) - start;
kamg@124 2656
kamg@124 2657
kamg@124 2658 // The instruction at the verified entry point must be 5 bytes or longer
kamg@124 2659 // because it can be patched on the fly by make_non_entrant. The stack bang
kamg@124 2660 // instruction fits that requirement.
kamg@124 2661
kamg@124 2662 // Generate stack overflow check before creating frame
kamg@124 2663 __ generate_stack_overflow_check(stack_size);
kamg@124 2664
kamg@124 2665 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
kamg@124 2666 "valid size for make_non_entrant");
kamg@124 2667
kamg@124 2668 // Generate a new frame for the wrapper.
kamg@124 2669 __ save(SP, -stack_size, SP);
kamg@124 2670
kamg@124 2671 // Frame is now completed as far a size and linkage.
kamg@124 2672
kamg@124 2673 int frame_complete = ((intptr_t)__ pc()) - start;
kamg@124 2674
kamg@124 2675 #ifdef ASSERT
kamg@124 2676 bool reg_destroyed[RegisterImpl::number_of_registers];
kamg@124 2677 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
kamg@124 2678 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
kamg@124 2679 reg_destroyed[r] = false;
kamg@124 2680 }
kamg@124 2681 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
kamg@124 2682 freg_destroyed[f] = false;
kamg@124 2683 }
kamg@124 2684
kamg@124 2685 #endif /* ASSERT */
kamg@124 2686
kamg@124 2687 VMRegPair zero;
kamg@182 2688 const Register g0 = G0; // without this we get a compiler warning (why??)
kamg@182 2689 zero.set2(g0->as_VMReg());
kamg@124 2690
kamg@124 2691 int c_arg, j_arg;
kamg@124 2692
kamg@124 2693 Register conversion_off = noreg;
kamg@124 2694
kamg@124 2695 for (j_arg = first_arg_to_pass, c_arg = 0 ;
kamg@124 2696 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
kamg@124 2697
kamg@124 2698 VMRegPair src = in_regs[j_arg];
kamg@124 2699 VMRegPair dst = out_regs[c_arg];
kamg@124 2700
kamg@124 2701 #ifdef ASSERT
kamg@124 2702 if (src.first()->is_Register()) {
kamg@124 2703 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
kamg@124 2704 } else if (src.first()->is_FloatRegister()) {
kamg@124 2705 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
kamg@124 2706 FloatRegisterImpl::S)], "ack!");
kamg@124 2707 }
kamg@124 2708 if (dst.first()->is_Register()) {
kamg@124 2709 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
kamg@124 2710 } else if (dst.first()->is_FloatRegister()) {
kamg@124 2711 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
kamg@124 2712 FloatRegisterImpl::S)] = true;
kamg@124 2713 }
kamg@124 2714 #endif /* ASSERT */
kamg@124 2715
kamg@124 2716 switch (in_sig_bt[j_arg]) {
kamg@124 2717 case T_ARRAY:
kamg@124 2718 case T_OBJECT:
kamg@124 2719 {
kamg@124 2720 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
kamg@124 2721 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
kamg@124 2722 // need to unbox a one-slot value
kamg@124 2723 Register in_reg = L0;
kamg@124 2724 Register tmp = L2;
kamg@124 2725 if ( src.first()->is_reg() ) {
kamg@124 2726 in_reg = src.first()->as_Register();
kamg@124 2727 } else {
kamg@124 2728 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
kamg@124 2729 "must be");
kamg@124 2730 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
kamg@124 2731 }
kamg@124 2732 // If the final destination is an acceptable register
kamg@124 2733 if ( dst.first()->is_reg() ) {
kamg@124 2734 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
kamg@124 2735 tmp = dst.first()->as_Register();
kamg@124 2736 }
kamg@124 2737 }
kamg@124 2738
kamg@124 2739 Label skipUnbox;
kamg@124 2740 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
kamg@124 2741 __ mov(G0, tmp->successor());
kamg@124 2742 }
kamg@124 2743 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
kamg@124 2744 __ delayed()->mov(G0, tmp);
kamg@124 2745
kvn@153 2746 BasicType bt = out_sig_bt[c_arg];
kvn@153 2747 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
kvn@153 2748 switch (bt) {
kamg@124 2749 case T_BYTE:
kamg@124 2750 __ ldub(in_reg, box_offset, tmp); break;
kamg@124 2751 case T_SHORT:
kamg@124 2752 __ lduh(in_reg, box_offset, tmp); break;
kamg@124 2753 case T_INT:
kamg@124 2754 __ ld(in_reg, box_offset, tmp); break;
kamg@124 2755 case T_LONG:
kamg@124 2756 __ ld_long(in_reg, box_offset, tmp); break;
kamg@124 2757 default: ShouldNotReachHere();
kamg@124 2758 }
kamg@124 2759
kamg@124 2760 __ bind(skipUnbox);
kamg@124 2761 // If tmp wasn't final destination copy to final destination
kamg@124 2762 if (tmp == L2) {
kamg@124 2763 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
kamg@124 2764 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 2765 long_move(masm, tmp_as_VM, dst);
kamg@124 2766 } else {
kamg@124 2767 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
kamg@124 2768 }
kamg@124 2769 }
kamg@124 2770 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 2771 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
kamg@124 2772 ++c_arg; // move over the T_VOID to keep the loop indices in sync
kamg@124 2773 }
kamg@124 2774 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 2775 Register s =
kamg@124 2776 src.first()->is_reg() ? src.first()->as_Register() : L2;
kamg@124 2777 Register d =
kamg@124 2778 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 2779
kamg@124 2780 // We store the oop now so that the conversion pass can reach
kamg@124 2781 // while in the inner frame. This will be the only store if
kamg@124 2782 // the oop is NULL.
kamg@124 2783 if (s != L2) {
kamg@124 2784 // src is register
kamg@124 2785 if (d != L2) {
kamg@124 2786 // dst is register
kamg@124 2787 __ mov(s, d);
kamg@124 2788 } else {
kamg@124 2789 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2790 STACK_BIAS), "must be");
kamg@124 2791 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2792 }
kamg@124 2793 } else {
kamg@124 2794 // src not a register
kamg@124 2795 assert(Assembler::is_simm13(reg2offset(src.first()) +
kamg@124 2796 STACK_BIAS), "must be");
kamg@124 2797 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
kamg@124 2798 if (d == L2) {
kamg@124 2799 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2800 STACK_BIAS), "must be");
kamg@124 2801 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2802 }
kamg@124 2803 }
kamg@124 2804 } else if (out_sig_bt[c_arg] != T_VOID) {
kamg@124 2805 // Convert the arg to NULL
kamg@124 2806 if (dst.first()->is_reg()) {
kamg@124 2807 __ mov(G0, dst.first()->as_Register());
kamg@124 2808 } else {
kamg@124 2809 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2810 STACK_BIAS), "must be");
kamg@124 2811 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2812 }
kamg@124 2813 }
kamg@124 2814 }
kamg@124 2815 break;
kamg@124 2816 case T_VOID:
kamg@124 2817 break;
kamg@124 2818
kamg@124 2819 case T_FLOAT:
kamg@124 2820 if (src.first()->is_stack()) {
kamg@124 2821 // Stack to stack/reg is simple
kamg@124 2822 move32_64(masm, src, dst);
kamg@124 2823 } else {
kamg@124 2824 if (dst.first()->is_reg()) {
kamg@124 2825 // freg -> reg
kamg@124 2826 int off =
kamg@124 2827 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2828 Register d = dst.first()->as_Register();
kamg@124 2829 if (Assembler::is_simm13(off)) {
kamg@124 2830 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2831 SP, off);
kamg@124 2832 __ ld(SP, off, d);
kamg@124 2833 } else {
kamg@124 2834 if (conversion_off == noreg) {
kamg@124 2835 __ set(off, L6);
kamg@124 2836 conversion_off = L6;
kamg@124 2837 }
kamg@124 2838 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2839 SP, conversion_off);
kamg@124 2840 __ ld(SP, conversion_off , d);
kamg@124 2841 }
kamg@124 2842 } else {
kamg@124 2843 // freg -> mem
kamg@124 2844 int off = STACK_BIAS + reg2offset(dst.first());
kamg@124 2845 if (Assembler::is_simm13(off)) {
kamg@124 2846 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2847 SP, off);
kamg@124 2848 } else {
kamg@124 2849 if (conversion_off == noreg) {
kamg@124 2850 __ set(off, L6);
kamg@124 2851 conversion_off = L6;
kamg@124 2852 }
kamg@124 2853 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2854 SP, conversion_off);
kamg@124 2855 }
kamg@124 2856 }
kamg@124 2857 }
kamg@124 2858 break;
kamg@124 2859
kamg@124 2860 case T_DOUBLE:
kamg@124 2861 assert( j_arg + 1 < total_args_passed &&
kamg@124 2862 in_sig_bt[j_arg + 1] == T_VOID &&
kamg@124 2863 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
kamg@124 2864 if (src.first()->is_stack()) {
kamg@124 2865 // Stack to stack/reg is simple
kamg@124 2866 long_move(masm, src, dst);
kamg@124 2867 } else {
kamg@124 2868 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 2869
kamg@124 2870 // Destination could be an odd reg on 32bit in which case
kamg@124 2871 // we can't load direct to the destination.
kamg@124 2872
kamg@124 2873 if (!d->is_even() && wordSize == 4) {
kamg@124 2874 d = L2;
kamg@124 2875 }
kamg@124 2876 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2877 if (Assembler::is_simm13(off)) {
kamg@124 2878 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 2879 SP, off);
kamg@124 2880 __ ld_long(SP, off, d);
kamg@124 2881 } else {
kamg@124 2882 if (conversion_off == noreg) {
kamg@124 2883 __ set(off, L6);
kamg@124 2884 conversion_off = L6;
kamg@124 2885 }
kamg@124 2886 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 2887 SP, conversion_off);
kamg@124 2888 __ ld_long(SP, conversion_off, d);
kamg@124 2889 }
kamg@124 2890 if (d == L2) {
kamg@124 2891 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 2892 }
kamg@124 2893 }
kamg@124 2894 break;
kamg@124 2895
kamg@124 2896 case T_LONG :
kamg@124 2897 // 32bit can't do a split move of something like g1 -> O0, O1
kamg@124 2898 // so use a memory temp
kamg@124 2899 if (src.is_single_phys_reg() && wordSize == 4) {
kamg@124 2900 Register tmp = L2;
kamg@124 2901 if (dst.first()->is_reg() &&
kamg@124 2902 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
kamg@124 2903 tmp = dst.first()->as_Register();
kamg@124 2904 }
kamg@124 2905
kamg@124 2906 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2907 if (Assembler::is_simm13(off)) {
kamg@124 2908 __ stx(src.first()->as_Register(), SP, off);
kamg@124 2909 __ ld_long(SP, off, tmp);
kamg@124 2910 } else {
kamg@124 2911 if (conversion_off == noreg) {
kamg@124 2912 __ set(off, L6);
kamg@124 2913 conversion_off = L6;
kamg@124 2914 }
kamg@124 2915 __ stx(src.first()->as_Register(), SP, conversion_off);
kamg@124 2916 __ ld_long(SP, conversion_off, tmp);
kamg@124 2917 }
kamg@124 2918
kamg@124 2919 if (tmp == L2) {
kamg@124 2920 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 2921 }
kamg@124 2922 } else {
kamg@124 2923 long_move(masm, src, dst);
kamg@124 2924 }
kamg@124 2925 break;
kamg@124 2926
kamg@124 2927 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
kamg@124 2928
kamg@124 2929 default:
kamg@124 2930 move32_64(masm, src, dst);
kamg@124 2931 }
kamg@124 2932 }
kamg@124 2933
kamg@124 2934
kamg@124 2935 // If we have any strings we must store any register based arg to the stack
kamg@124 2936 // This includes any still live xmm registers too.
kamg@124 2937
kamg@124 2938 if (total_strings > 0 ) {
kamg@124 2939
kamg@124 2940 // protect all the arg registers
kamg@124 2941 __ save_frame(0);
kamg@124 2942 __ mov(G2_thread, L7_thread_cache);
kamg@124 2943 const Register L2_string_off = L2;
kamg@124 2944
kamg@124 2945 // Get first string offset
kamg@124 2946 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
kamg@124 2947
kamg@124 2948 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
kamg@124 2949 if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 2950
kamg@124 2951 VMRegPair dst = out_regs[c_arg];
kamg@124 2952 const Register d = dst.first()->is_reg() ?
kamg@124 2953 dst.first()->as_Register()->after_save() : noreg;
kamg@124 2954
kamg@124 2955 // It's a string the oop and it was already copied to the out arg
kamg@124 2956 // position
kamg@124 2957 if (d != noreg) {
kamg@124 2958 __ mov(d, O0);
kamg@124 2959 } else {
kamg@124 2960 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 2961 "must be");
kamg@124 2962 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
kamg@124 2963 }
kamg@124 2964 Label skip;
kamg@124 2965
kamg@124 2966 __ br_null(O0, false, Assembler::pn, skip);
kamg@124 2967 __ delayed()->add(FP, L2_string_off, O1);
kamg@124 2968
kamg@124 2969 if (d != noreg) {
kamg@124 2970 __ mov(O1, d);
kamg@124 2971 } else {
kamg@124 2972 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 2973 "must be");
kamg@124 2974 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2975 }
kamg@124 2976
kamg@124 2977 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
kamg@124 2978 relocInfo::runtime_call_type);
kamg@124 2979 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
kamg@124 2980
kamg@124 2981 __ bind(skip);
kamg@124 2982
kamg@124 2983 }
kamg@124 2984
kamg@124 2985 }
kamg@124 2986 __ mov(L7_thread_cache, G2_thread);
kamg@124 2987 __ restore();
kamg@124 2988
kamg@124 2989 }
kamg@124 2990
kamg@124 2991
kamg@124 2992 // Ok now we are done. Need to place the nop that dtrace wants in order to
kamg@124 2993 // patch in the trap
kamg@124 2994
kamg@124 2995 int patch_offset = ((intptr_t)__ pc()) - start;
kamg@124 2996
kamg@124 2997 __ nop();
kamg@124 2998
kamg@124 2999
kamg@124 3000 // Return
kamg@124 3001
kamg@124 3002 __ ret();
kamg@124 3003 __ delayed()->restore();
kamg@124 3004
kamg@124 3005 __ flush();
kamg@124 3006
kamg@124 3007 nmethod *nm = nmethod::new_dtrace_nmethod(
kamg@124 3008 method, masm->code(), vep_offset, patch_offset, frame_complete,
kamg@124 3009 stack_slots / VMRegImpl::slots_per_word);
kamg@124 3010 return nm;
kamg@124 3011
kamg@124 3012 }
kamg@124 3013
kamg@124 3014 #endif // HAVE_DTRACE_H
kamg@124 3015
duke@0 3016 // this function returns the adjust size (in number of words) to a c2i adapter
duke@0 3017 // activation for use during deoptimization
duke@0 3018 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
duke@0 3019 assert(callee_locals >= callee_parameters,
duke@0 3020 "test and remove; got more parms than locals");
duke@0 3021 if (callee_locals < callee_parameters)
duke@0 3022 return 0; // No adjustment for negative locals
twisti@1401 3023 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
duke@0 3024 return round_to(diff, WordsPerLong);
duke@0 3025 }
duke@0 3026
duke@0 3027 // "Top of Stack" slots that may be unused by the calling convention but must
duke@0 3028 // otherwise be preserved.
duke@0 3029 // On Intel these are not necessary and the value can be zero.
duke@0 3030 // On Sparc this describes the words reserved for storing a register window
duke@0 3031 // when an interrupt occurs.
duke@0 3032 uint SharedRuntime::out_preserve_stack_slots() {
duke@0 3033 return frame::register_save_words * VMRegImpl::slots_per_word;
duke@0 3034 }
duke@0 3035
duke@0 3036 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
duke@0 3037 //
duke@0 3038 // Common out the new frame generation for deopt and uncommon trap
duke@0 3039 //
duke@0 3040 Register G3pcs = G3_scratch; // Array of new pcs (input)
duke@0 3041 Register Oreturn0 = O0;
duke@0 3042 Register Oreturn1 = O1;
duke@0 3043 Register O2UnrollBlock = O2;
duke@0 3044 Register O3array = O3; // Array of frame sizes (input)
duke@0 3045 Register O4array_size = O4; // number of frames (input)
duke@0 3046 Register O7frame_size = O7; // number of frames (input)
duke@0 3047
duke@0 3048 __ ld_ptr(O3array, 0, O7frame_size);
duke@0 3049 __ sub(G0, O7frame_size, O7frame_size);
duke@0 3050 __ save(SP, O7frame_size, SP);
duke@0 3051 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
duke@0 3052
duke@0 3053 #ifdef ASSERT
duke@0 3054 // make sure that the frames are aligned properly
duke@0 3055 #ifndef _LP64
duke@0 3056 __ btst(wordSize*2-1, SP);
duke@0 3057 __ breakpoint_trap(Assembler::notZero);
duke@0 3058 #endif
duke@0 3059 #endif
duke@0 3060
duke@0 3061 // Deopt needs to pass some extra live values from frame to frame
duke@0 3062
duke@0 3063 if (deopt) {
duke@0 3064 __ mov(Oreturn0->after_save(), Oreturn0);
duke@0 3065 __ mov(Oreturn1->after_save(), Oreturn1);
duke@0 3066 }
duke@0 3067
duke@0 3068 __ mov(O4array_size->after_save(), O4array_size);
duke@0 3069 __ sub(O4array_size, 1, O4array_size);
duke@0 3070 __ mov(O3array->after_save(), O3array);
duke@0 3071 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
duke@0 3072 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
duke@0 3073
duke@0 3074 #ifdef ASSERT
duke@0 3075 // trash registers to show a clear pattern in backtraces
duke@0 3076 __ set(0xDEAD0000, I0);
duke@0 3077 __ add(I0, 2, I1);
duke@0 3078 __ add(I0, 4, I2);
duke@0 3079 __ add(I0, 6, I3);
duke@0 3080 __ add(I0, 8, I4);
duke@0 3081 // Don't touch I5 could have valuable savedSP
duke@0 3082 __ set(0xDEADBEEF, L0);
duke@0 3083 __ mov(L0, L1);
duke@0 3084 __ mov(L0, L2);
duke@0 3085 __ mov(L0, L3);
duke@0 3086 __ mov(L0, L4);
duke@0 3087 __ mov(L0, L5);
duke@0 3088
duke@0 3089 // trash the return value as there is nothing to return yet
duke@0 3090 __ set(0xDEAD0001, O7);
duke@0 3091 #endif
duke@0 3092
duke@0 3093 __ mov(SP, O5_savedSP);
duke@0 3094 }
duke@0 3095
duke@0 3096
duke@0 3097 static void make_new_frames(MacroAssembler* masm, bool deopt) {
duke@0 3098 //
duke@0 3099 // loop through the UnrollBlock info and create new frames
duke@0 3100 //
duke@0 3101 Register G3pcs = G3_scratch;
duke@0 3102 Register Oreturn0 = O0;
duke@0 3103 Register Oreturn1 = O1;
duke@0 3104 Register O2UnrollBlock = O2;
duke@0 3105 Register O3array = O3;
duke@0 3106 Register O4array_size = O4;
duke@0 3107 Label loop;
duke@0 3108
duke@0 3109 // Before we make new frames, check to see if stack is available.
duke@0 3110 // Do this after the caller's return address is on top of stack
duke@0 3111 if (UseStackBanging) {
duke@0 3112 // Get total frame size for interpreted frames
twisti@720 3113 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
duke@0 3114 __ bang_stack_size(O4, O3, G3_scratch);
duke@0 3115 }
duke@0 3116
twisti@720 3117 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
twisti@720 3118 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
twisti@720 3119 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
duke@0 3120
duke@0 3121 // Adjust old interpreter frame to make space for new frame's extra java locals
duke@0 3122 //
duke@0 3123 // We capture the original sp for the transition frame only because it is needed in
duke@0 3124 // order to properly calculate interpreter_sp_adjustment. Even though in real life
duke@0 3125 // every interpreter frame captures a savedSP it is only needed at the transition
duke@0 3126 // (fortunately). If we had to have it correct everywhere then we would need to
duke@0 3127 // be told the sp_adjustment for each frame we create. If the frame size array
duke@0 3128 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
duke@0 3129 // for each frame we create and keep up the illusion every where.
duke@0 3130 //
duke@0 3131
twisti@720 3132 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
duke@0 3133 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
duke@0 3134 __ sub(SP, O7, SP);
duke@0 3135
duke@0 3136 #ifdef ASSERT
duke@0 3137 // make sure that there is at least one entry in the array
duke@0 3138 __ tst(O4array_size);
duke@0 3139 __ breakpoint_trap(Assembler::zero);
duke@0 3140 #endif
duke@0 3141
duke@0 3142 // Now push the new interpreter frames
duke@0 3143 __ bind(loop);
duke@0 3144
duke@0 3145 // allocate a new frame, filling the registers
duke@0 3146
duke@0 3147 gen_new_frame(masm, deopt); // allocate an interpreter frame
duke@0 3148
duke@0 3149 __ tst(O4array_size);
duke@0 3150 __ br(Assembler::notZero, false, Assembler::pn, loop);
duke@0 3151 __ delayed()->add(O3array, wordSize, O3array);
duke@0 3152 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
duke@0 3153
duke@0 3154 }
duke@0 3155
duke@0 3156 //------------------------------generate_deopt_blob----------------------------
duke@0 3157 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 3158 // instead.
duke@0 3159 void SharedRuntime::generate_deopt_blob() {
duke@0 3160 // allocate space for the code
duke@0 3161 ResourceMark rm;
duke@0 3162 // setup code generation tools
duke@0 3163 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
duke@0 3164 #ifdef _LP64
duke@0 3165 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
duke@0 3166 #else
duke@0 3167 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
duke@0 3168 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
duke@0 3169 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
duke@0 3170 #endif /* _LP64 */
duke@0 3171 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3172 FloatRegister Freturn0 = F0;
duke@0 3173 Register Greturn1 = G1;
duke@0 3174 Register Oreturn0 = O0;
duke@0 3175 Register Oreturn1 = O1;
duke@0 3176 Register O2UnrollBlock = O2;
never@1002 3177 Register L0deopt_mode = L0;
never@1002 3178 Register G4deopt_mode = G4_scratch;
duke@0 3179 int frame_size_words;
twisti@720 3180 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
duke@0 3181 #if !defined(_LP64) && defined(COMPILER2)
twisti@720 3182 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
duke@0 3183 #endif
duke@0 3184 Label cont;
duke@0 3185
duke@0 3186 OopMapSet *oop_maps = new OopMapSet();
duke@0 3187
duke@0 3188 //
duke@0 3189 // This is the entry point for code which is returning to a de-optimized
duke@0 3190 // frame.
duke@0 3191 // The steps taken by this frame are as follows:
duke@0 3192 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
duke@0 3193 // and all potentially live registers (at a pollpoint many registers can be live).
duke@0 3194 //
duke@0 3195 // - call the C routine: Deoptimization::fetch_unroll_info (this function
duke@0 3196 // returns information about the number and size of interpreter frames
duke@0 3197 // which are equivalent to the frame which is being deoptimized)
duke@0 3198 // - deallocate the unpack frame, restoring only results values. Other
duke@0 3199 // volatile registers will now be captured in the vframeArray as needed.
duke@0 3200 // - deallocate the deoptimization frame
duke@0 3201 // - in a loop using the information returned in the previous step
duke@0 3202 // push new interpreter frames (take care to propagate the return
duke@0 3203 // values through each new frame pushed)
duke@0 3204 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
duke@0 3205 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 3206 // lays out values on the interpreter frame which was just created)
duke@0 3207 // - deallocate the dummy unpack_frame
duke@0 3208 // - ensure that all the return values are correctly set and then do
duke@0 3209 // a return to the interpreter entry point
duke@0 3210 //
duke@0 3211 // Refer to the following methods for more information:
duke@0 3212 // - Deoptimization::fetch_unroll_info
duke@0 3213 // - Deoptimization::unpack_frames
duke@0 3214
duke@0 3215 OopMap* map = NULL;
duke@0 3216
duke@0 3217 int start = __ offset();
duke@0 3218
duke@0 3219 // restore G2, the trampoline destroyed it
duke@0 3220 __ get_thread();
duke@0 3221
duke@0 3222 // On entry we have been called by the deoptimized nmethod with a call that
duke@0 3223 // replaced the original call (or safepoint polling location) so the deoptimizing
duke@0 3224 // pc is now in O7. Return values are still in the expected places
duke@0 3225
duke@0 3226 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3227 __ ba(false, cont);
never@1002 3228 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
duke@0 3229
duke@0 3230 int exception_offset = __ offset() - start;
duke@0 3231
duke@0 3232 // restore G2, the trampoline destroyed it
duke@0 3233 __ get_thread();
duke@0 3234
duke@0 3235 // On entry we have been jumped to by the exception handler (or exception_blob
duke@0 3236 // for server). O0 contains the exception oop and O7 contains the original
duke@0 3237 // exception pc. So if we push a frame here it will look to the
duke@0 3238 // stack walking code (fetch_unroll_info) just like a normal call so
duke@0 3239 // state will be extracted normally.
duke@0 3240
duke@0 3241 // save exception oop in JavaThread and fall through into the
duke@0 3242 // exception_in_tls case since they are handled in same way except
duke@0 3243 // for where the pending exception is kept.
twisti@720 3244 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
duke@0 3245
duke@0 3246 //
duke@0 3247 // Vanilla deoptimization with an exception pending in exception_oop
duke@0 3248 //
duke@0 3249 int exception_in_tls_offset = __ offset() - start;
duke@0 3250
duke@0 3251 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 3252 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3253
duke@0 3254 // Restore G2_thread
duke@0 3255 __ get_thread();
duke@0 3256
duke@0 3257 #ifdef ASSERT
duke@0 3258 {
duke@0 3259 // verify that there is really an exception oop in exception_oop
duke@0 3260 Label has_exception;
twisti@720 3261 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
duke@0 3262 __ br_notnull(Oexception, false, Assembler::pt, has_exception);
duke@0 3263 __ delayed()-> nop();
duke@0 3264 __ stop("no exception in thread");
duke@0 3265 __ bind(has_exception);
duke@0 3266
duke@0 3267 // verify that there is no pending exception
duke@0 3268 Label no_pending_exception;
twisti@720 3269 Address exception_addr(G2_thread, Thread::pending_exception_offset());
duke@0 3270 __ ld_ptr(exception_addr, Oexception);
duke@0 3271 __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
duke@0 3272 __ delayed()->nop();
duke@0 3273 __ stop("must not have pending exception here");
duke@0 3274 __ bind(no_pending_exception);
duke@0 3275 }
duke@0 3276 #endif
duke@0 3277
duke@0 3278 __ ba(false, cont);
never@1002 3279 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
duke@0 3280
duke@0 3281 //
duke@0 3282 // Reexecute entry, similar to c2 uncommon trap
duke@0 3283 //
duke@0 3284 int reexecute_offset = __ offset() - start;
duke@0 3285
duke@0 3286 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 3287 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3288
never@1002 3289 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
duke@0 3290
duke@0 3291 __ bind(cont);
duke@0 3292
duke@0 3293 __ set_last_Java_frame(SP, noreg);
duke@0 3294
duke@0 3295 // do the call by hand so we can get the oopmap
duke@0 3296
duke@0 3297 __ mov(G2_thread, L7_thread_cache);
duke@0 3298 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
duke@0 3299 __ delayed()->mov(G2_thread, O0);
duke@0 3300
duke@0 3301 // Set an oopmap for the call site this describes all our saved volatile registers
duke@0 3302
duke@0 3303 oop_maps->add_gc_map( __ offset()-start, map);
duke@0 3304
duke@0 3305 __ mov(L7_thread_cache, G2_thread);
duke@0 3306
duke@0 3307 __ reset_last_Java_frame();
duke@0 3308
duke@0 3309 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
duke@0 3310 // so this move will survive
duke@0 3311
never@1002 3312 __ mov(L0deopt_mode, G4deopt_mode);
duke@0 3313
duke@0 3314 __ mov(O0, O2UnrollBlock->after_save());
duke@0 3315
duke@0 3316 RegisterSaver::restore_result_registers(masm);
duke@0 3317
duke@0 3318 Label noException;
never@1002 3319 __ cmp(G4deopt_mode, Deoptimization::Unpack_exception); // Was exception pending?
duke@0 3320 __ br(Assembler::notEqual, false, Assembler::pt, noException);
duke@0 3321 __ delayed()->nop();
duke@0 3322
duke@0 3323 // Move the pending exception from exception_oop to Oexception so
duke@0 3324 // the pending exception will be picked up the interpreter.
duke@0 3325 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
duke@0 3326 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
duke@0 3327 __ bind(noException);
duke@0 3328
duke@0 3329 // deallocate the deoptimization frame taking care to preserve the return values
duke@0 3330 __ mov(Oreturn0, Oreturn0->after_save());
duke@0 3331 __ mov(Oreturn1, Oreturn1->after_save());
duke@0 3332 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 3333 __ restore();
duke@0 3334
duke@0 3335 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 3336
duke@0 3337 make_new_frames(masm, true);
duke@0 3338
duke@0 3339 // push a dummy "unpack_frame" taking care of float return values and
duke@0 3340 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 3341 // information in the interpreter frames just created and then return
duke@0 3342 // to the interpreter entry point
duke@0 3343 __ save(SP, -frame_size_words*wordSize, SP);
duke@0 3344 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
duke@0 3345 #if !defined(_LP64)
duke@0 3346 #if defined(COMPILER2)
duke@0 3347 if (!TieredCompilation) {
duke@0 3348 // 32-bit 1-register longs return longs in G1
duke@0 3349 __ stx(Greturn1, saved_Greturn1_addr);
duke@0 3350 }
duke@0 3351 #endif
duke@0 3352 __ set_last_Java_frame(SP, noreg);
never@1002 3353 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
duke@0 3354 #else
duke@0 3355 // LP64 uses g4 in set_last_Java_frame
never@1002 3356 __ mov(G4deopt_mode, O1);
duke@0 3357 __ set_last_Java_frame(SP, G0);
duke@0 3358 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
duke@0 3359 #endif
duke@0 3360 __ reset_last_Java_frame();
duke@0 3361 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
duke@0 3362
duke@0 3363 // In tiered we never use C2 to compile methods returning longs so
duke@0 3364 // the result is where we expect it already.
duke@0 3365
duke@0 3366 #if !defined(_LP64) && defined(COMPILER2)
duke@0 3367 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
duke@0 3368 // I0/I1 if the return value is long. In the tiered world there is
duke@0 3369 // a mismatch between how C1 and C2 return longs compiles and so
duke@0 3370 // currently compilation of methods which return longs is disabled
duke@0 3371 // for C2 and so is this code. Eventually C1 and C2 will do the
duke@0 3372 // same thing for longs in the tiered world.
duke@0 3373 if (!TieredCompilation) {
duke@0 3374 Label not_long;
duke@0 3375 __ cmp(O0,T_LONG);
duke@0 3376 __ br(Assembler::notEqual, false, Assembler::pt, not_long);
duke@0 3377 __ delayed()->nop();
duke@0 3378 __ ldd(saved_Greturn1_addr,I0);
duke@0 3379 __ bind(not_long);
duke@0 3380 }
duke@0 3381 #endif
duke@0 3382 __ ret();
duke@0 3383 __ delayed()->restore();
duke@0 3384
duke@0 3385 masm->flush();
duke@0 3386 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
duke@0 3387 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
duke@0 3388 }
duke@0 3389
duke@0 3390 #ifdef COMPILER2
duke@0 3391
duke@0 3392 //------------------------------generate_uncommon_trap_blob--------------------
duke@0 3393 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 3394 // instead.
duke@0 3395 void SharedRuntime::generate_uncommon_trap_blob() {
duke@0 3396 // allocate space for the code
duke@0 3397 ResourceMark rm;
duke@0 3398 // setup code generation tools
duke@0 3399 int pad = VerifyThread ? 512 : 0;
duke@0 3400 #ifdef _LP64
duke@0 3401 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
duke@0 3402 #else
duke@0 3403 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
duke@0 3404 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
duke@0 3405 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
duke@0 3406 #endif
duke@0 3407 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3408 Register O2UnrollBlock = O2;
duke@0 3409 Register O2klass_index = O2;
duke@0 3410
duke@0 3411 //
duke@0 3412 // This is the entry point for all traps the compiler takes when it thinks
duke@0 3413 // it cannot handle further execution of compilation code. The frame is
duke@0 3414 // deoptimized in these cases and converted into interpreter frames for
duke@0 3415 // execution
duke@0 3416 // The steps taken by this frame are as follows:
duke@0 3417 // - push a fake "unpack_frame"
duke@0 3418 // - call the C routine Deoptimization::uncommon_trap (this function
duke@0 3419 // packs the current compiled frame into vframe arrays and returns
duke@0 3420 // information about the number and size of interpreter frames which
duke@0 3421 // are equivalent to the frame which is being deoptimized)
duke@0 3422 // - deallocate the "unpack_frame"
duke@0 3423 // - deallocate the deoptimization frame
duke@0 3424 // - in a loop using the information returned in the previous step
duke@0 3425 // push interpreter frames;
duke@0 3426 // - create a dummy "unpack_frame"
duke@0 3427 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 3428 // lays out values on the interpreter frame which was just created)
duke@0 3429 // - deallocate the dummy unpack_frame
duke@0 3430 // - return to the interpreter entry point
duke@0 3431 //
duke@0 3432 // Refer to the following methods for more information:
duke@0 3433 // - Deoptimization::uncommon_trap
duke@0 3434 // - Deoptimization::unpack_frame
duke@0 3435
duke@0 3436 // the unloaded class index is in O0 (first parameter to this blob)
duke@0 3437
duke@0 3438 // push a dummy "unpack_frame"
duke@0 3439 // and call Deoptimization::uncommon_trap to pack the compiled frame into
duke@0 3440 // vframe array and return the UnrollBlock information
duke@0 3441 __ save_frame(0);
duke@0 3442 __ set_last_Java_frame(SP, noreg);
duke@0 3443 __ mov(I0, O2klass_index);
duke@0 3444 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
duke@0 3445 __ reset_last_Java_frame();
duke@0 3446 __ mov(O0, O2UnrollBlock->after_save());
duke@0 3447 __ restore();
duke@0 3448
duke@0 3449 // deallocate the deoptimized frame taking care to preserve the return values
duke@0 3450 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 3451 __ restore();
duke@0 3452
duke@0 3453 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 3454
duke@0 3455 make_new_frames(masm, false);
duke@0 3456
duke@0 3457 // push a dummy "unpack_frame" taking care of float return values and
duke@0 3458 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 3459 // information in the interpreter frames just created and then return
duke@0 3460 // to the interpreter entry point
duke@0 3461 __ save_frame(0);
duke@0 3462 __ set_last_Java_frame(SP, noreg);
duke@0 3463 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
duke@0 3464 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
duke@0 3465 __ reset_last_Java_frame();
duke@0 3466 __ ret();
duke@0 3467 __ delayed()->restore();
duke@0 3468
duke@0 3469 masm->flush();
duke@0 3470 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
duke@0 3471 }
duke@0 3472
duke@0 3473 #endif // COMPILER2
duke@0 3474
duke@0 3475 //------------------------------generate_handler_blob-------------------
duke@0 3476 //
duke@0 3477 // Generate a special Compile2Runtime blob that saves all registers, and sets
duke@0 3478 // up an OopMap.
duke@0 3479 //
duke@0 3480 // This blob is jumped to (via a breakpoint and the signal handler) from a
duke@0 3481 // safepoint in compiled code. On entry to this blob, O7 contains the
duke@0 3482 // address in the original nmethod at which we should resume normal execution.
duke@0 3483 // Thus, this blob looks like a subroutine which must preserve lots of
duke@0 3484 // registers and return normally. Note that O7 is never register-allocated,
duke@0 3485 // so it is guaranteed to be free here.
duke@0 3486 //
duke@0 3487
duke@0 3488 // The hardest part of what this blob must do is to save the 64-bit %o
duke@0 3489 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
duke@0 3490 // an interrupt will chop off their heads. Making space in the caller's frame
duke@0 3491 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
duke@0 3492 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
duke@0 3493 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
duke@0 3494 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
duke@0 3495 // Tricky, tricky, tricky...
duke@0 3496
duke@0 3497 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
duke@0 3498 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@0 3499
duke@0 3500 // allocate space for the code
duke@0 3501 ResourceMark rm;
duke@0 3502 // setup code generation tools
duke@0 3503 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@0 3504 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@0 3505 // even larger with TraceJumps
duke@0 3506 int pad = TraceJumps ? 512 : 0;
duke@0 3507 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
duke@0 3508 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3509 int f