annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 2600:3d42f82cd811

7063628: Use cbcond on T4 Summary: Add new short branch instruction to Hotspot sparc assembler. Reviewed-by: never, twisti, jrose
author kvn
date Thu, 21 Jul 2011 11:25:07 -0700
parents cba7b5c2d53f
children 6729bbc1fcd6
rev   line source
duke@0 1 /*
twisti@2244 2 * Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1489 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1489 20 * or visit www.oracle.com if you need additional information or have any
trims@1489 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1869 25 #include "precompiled.hpp"
stefank@1869 26 #include "asm/assembler.hpp"
stefank@1869 27 #include "assembler_sparc.inline.hpp"
stefank@1869 28 #include "code/debugInfoRec.hpp"
stefank@1869 29 #include "code/icBuffer.hpp"
stefank@1869 30 #include "code/vtableStubs.hpp"
stefank@1869 31 #include "interpreter/interpreter.hpp"
stefank@1869 32 #include "oops/compiledICHolderOop.hpp"
stefank@1869 33 #include "prims/jvmtiRedefineClassesTrace.hpp"
stefank@1869 34 #include "runtime/sharedRuntime.hpp"
stefank@1869 35 #include "runtime/vframeArray.hpp"
stefank@1869 36 #include "vmreg_sparc.inline.hpp"
stefank@1869 37 #ifdef COMPILER1
stefank@1869 38 #include "c1/c1_Runtime1.hpp"
stefank@1869 39 #endif
stefank@1869 40 #ifdef COMPILER2
stefank@1869 41 #include "opto/runtime.hpp"
stefank@1869 42 #endif
stefank@1869 43 #ifdef SHARK
stefank@1869 44 #include "compiler/compileBroker.hpp"
stefank@1869 45 #include "shark/sharkCompiler.hpp"
stefank@1869 46 #endif
duke@0 47
duke@0 48 #define __ masm->
duke@0 49
duke@0 50
duke@0 51 class RegisterSaver {
duke@0 52
duke@0 53 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@0 54 // The Oregs are problematic. In the 32bit build the compiler can
duke@0 55 // have O registers live with 64 bit quantities. A window save will
duke@0 56 // cut the heads off of the registers. We have to do a very extensive
duke@0 57 // stack dance to save and restore these properly.
duke@0 58
duke@0 59 // Note that the Oregs problem only exists if we block at either a polling
duke@0 60 // page exception a compiled code safepoint that was not originally a call
duke@0 61 // or deoptimize following one of these kinds of safepoints.
duke@0 62
duke@0 63 // Lots of registers to save. For all builds, a window save will preserve
duke@0 64 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@0 65 // builds a window-save will preserve the %o registers. In the LION build
duke@0 66 // we need to save the 64-bit %o registers which requires we save them
duke@0 67 // before the window-save (as then they become %i registers and get their
duke@0 68 // heads chopped off on interrupt). We have to save some %g registers here
duke@0 69 // as well.
duke@0 70 enum {
duke@0 71 // This frame's save area. Includes extra space for the native call:
duke@0 72 // vararg's layout space and the like. Briefly holds the caller's
duke@0 73 // register save area.
duke@0 74 call_args_area = frame::register_save_words_sp_offset +
duke@0 75 frame::memory_parameter_word_sp_offset*wordSize,
duke@0 76 // Make sure save locations are always 8 byte aligned.
duke@0 77 // can't use round_to because it doesn't produce compile time constant
duke@0 78 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@0 79 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@0 80 g3_offset = g1_offset+8,
duke@0 81 g4_offset = g3_offset+8,
duke@0 82 g5_offset = g4_offset+8,
duke@0 83 o0_offset = g5_offset+8,
duke@0 84 o1_offset = o0_offset+8,
duke@0 85 o2_offset = o1_offset+8,
duke@0 86 o3_offset = o2_offset+8,
duke@0 87 o4_offset = o3_offset+8,
duke@0 88 o5_offset = o4_offset+8,
duke@0 89 start_of_flags_save_area = o5_offset+8,
duke@0 90 ccr_offset = start_of_flags_save_area,
duke@0 91 fsr_offset = ccr_offset + 8,
duke@0 92 d00_offset = fsr_offset+8, // Start of float save area
duke@0 93 register_save_size = d00_offset+8*32
duke@0 94 };
duke@0 95
duke@0 96
duke@0 97 public:
duke@0 98
duke@0 99 static int Oexception_offset() { return o0_offset; };
duke@0 100 static int G3_offset() { return g3_offset; };
duke@0 101 static int G5_offset() { return g5_offset; };
duke@0 102 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@0 103 static void restore_live_registers(MacroAssembler* masm);
duke@0 104
duke@0 105 // During deoptimization only the result register need to be restored
duke@0 106 // all the other values have already been extracted.
duke@0 107
duke@0 108 static void restore_result_registers(MacroAssembler* masm);
duke@0 109 };
duke@0 110
duke@0 111 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@0 112 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@0 113 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@0 114 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@0 115 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@0 116 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@0 117 int i;
kvn@992 118 // Always make the frame size 16 byte aligned.
duke@0 119 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@0 120 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@0 121 int frame_size_in_slots = frame_size / sizeof(jint);
duke@0 122 // CodeBlob frame size is in words.
duke@0 123 *total_frame_words = frame_size / wordSize;
duke@0 124 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@0 125 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@0 126
duke@0 127 #if !defined(_LP64)
duke@0 128
duke@0 129 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@0 130 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 131 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 132 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 133 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 134 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 135 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 136 #endif /* _LP64 */
duke@0 137
duke@0 138 __ save(SP, -frame_size, SP);
duke@0 139
duke@0 140 #ifndef _LP64
duke@0 141 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@0 142 // to Oregs here to avoid interrupts cutting off their heads
duke@0 143
duke@0 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 150
duke@0 151 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@0 152 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@0 153
duke@0 154 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@0 155
duke@0 156 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@0 157
duke@0 158 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@0 159 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@0 160
duke@0 161 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@0 162 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@0 163
duke@0 164 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@0 165 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@0 166
duke@0 167 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@0 168 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@0 169 #endif /* _LP64 */
duke@0 170
coleenp@108 171
coleenp@108 172 #ifdef _LP64
coleenp@108 173 int debug_offset = 0;
coleenp@108 174 #else
coleenp@108 175 int debug_offset = 4;
coleenp@108 176 #endif
duke@0 177 // Save the G's
duke@0 178 __ stx(G1, SP, g1_offset+STACK_BIAS);
coleenp@108 179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
duke@0 180
duke@0 181 __ stx(G3, SP, g3_offset+STACK_BIAS);
coleenp@108 182 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
duke@0 183
duke@0 184 __ stx(G4, SP, g4_offset+STACK_BIAS);
coleenp@108 185 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
duke@0 186
duke@0 187 __ stx(G5, SP, g5_offset+STACK_BIAS);
coleenp@108 188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
duke@0 189
duke@0 190 // This is really a waste but we'll keep things as they were for now
duke@0 191 if (true) {
duke@0 192 #ifndef _LP64
duke@0 193 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@0 194 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@0 195 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@0 196 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@0 197 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@0 198 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@0 199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@0 200 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@0 201 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@0 202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
coleenp@108 203 #endif /* _LP64 */
duke@0 204 }
duke@0 205
duke@0 206
duke@0 207 // Save the flags
duke@0 208 __ rdccr( G5 );
duke@0 209 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@0 210 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 211
kvn@992 212 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
duke@0 213 int offset = d00_offset;
kvn@992 214 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 215 FloatRegister f = as_FloatRegister(i);
duke@0 216 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
kvn@992 217 // Record as callee saved both halves of double registers (2 float registers).
duke@0 218 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
kvn@992 219 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@0 220 offset += sizeof(double);
duke@0 221 }
duke@0 222
duke@0 223 // And we're done.
duke@0 224
duke@0 225 return map;
duke@0 226 }
duke@0 227
duke@0 228
duke@0 229 // Pop the current frame and restore all the registers that we
duke@0 230 // saved.
duke@0 231 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@0 232
duke@0 233 // Restore all the FP registers
kvn@992 234 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 235 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@0 236 }
duke@0 237
duke@0 238 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@0 239 __ wrccr (G1) ;
duke@0 240
duke@0 241 // Restore the G's
duke@0 242 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@0 243 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@0 244
duke@0 245 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 246 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@0 247 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@0 248 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@0 249
duke@0 250
duke@0 251 #if !defined(_LP64)
duke@0 252 // Restore the 64-bit O's.
duke@0 253 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 254 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 255 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@0 256 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@0 257 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@0 258 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@0 259
duke@0 260 // And temporarily place them in TLS
duke@0 261
duke@0 262 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 263 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 264 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 265 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 266 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 267 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 268 #endif /* _LP64 */
duke@0 269
duke@0 270 // Restore flags
duke@0 271
duke@0 272 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 273
duke@0 274 __ restore();
duke@0 275
duke@0 276 #if !defined(_LP64)
duke@0 277 // Now reload the 64bit Oregs after we've restore the window.
duke@0 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 284 #endif /* _LP64 */
duke@0 285
duke@0 286 }
duke@0 287
duke@0 288 // Pop the current frame and restore the registers that might be holding
duke@0 289 // a result.
duke@0 290 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@0 291
duke@0 292 #if !defined(_LP64)
duke@0 293 // 32bit build returns longs in G1
duke@0 294 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 295
duke@0 296 // Retrieve the 64-bit O's.
duke@0 297 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 298 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 299 // and save to TLS
duke@0 300 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 301 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 302 #endif /* _LP64 */
duke@0 303
duke@0 304 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@0 305
duke@0 306 __ restore();
duke@0 307
duke@0 308 #if !defined(_LP64)
duke@0 309 // Now reload the 64bit Oregs after we've restore the window.
duke@0 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 311 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 312 #endif /* _LP64 */
duke@0 313
duke@0 314 }
duke@0 315
duke@0 316 // The java_calling_convention describes stack locations as ideal slots on
duke@0 317 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@0 318 // (like the placement of the register window) the slots must be biased by
duke@0 319 // the following value.
duke@0 320 static int reg2offset(VMReg r) {
duke@0 321 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@0 322 }
duke@0 323
duke@0 324 // ---------------------------------------------------------------------------
duke@0 325 // Read the array of BasicTypes from a signature, and compute where the
duke@0 326 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@0 327 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@0 328 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@0 329 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@0 330 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@0 331 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@0 332 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@0 333 // Each 32-bit quantity is given its own number, so the integer registers
duke@0 334 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@0 335 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@0 336
duke@0 337 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@0 338 // convert to incoming arguments, convert all O's to I's. The regs array
duke@0 339 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@0 340 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@0 341 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@0 342 // passed (used as a placeholder for the other half of longs and doubles in
duke@0 343 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@0 344 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@0 345 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@0 346 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@0 347 // same VMRegPair.
duke@0 348
duke@0 349 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@0 350 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@0 351 // units regardless of build.
duke@0 352
duke@0 353
duke@0 354 // ---------------------------------------------------------------------------
duke@0 355 // The compiled Java calling convention. The Java convention always passes
duke@0 356 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@0 357 // floats in float registers and doubles in aligned float pairs. Values are
duke@0 358 // packed in the registers. There is no backing varargs store for values in
duke@0 359 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@0 360 // passed in I's, because longs in I's get their heads chopped off at
duke@0 361 // interrupt).
duke@0 362 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@0 363 VMRegPair *regs,
duke@0 364 int total_args_passed,
duke@0 365 int is_outgoing) {
duke@0 366 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@0 367
duke@0 368 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@0 369 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@0 370 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@0 371 // align. Then put longs and doubles into the same registers as they fit,
duke@0 372 // else spill to the stack.
duke@0 373 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@0 374 const int flt_reg_max = 8;
duke@0 375 //
duke@0 376 // Where 32-bit 1-reg longs start being passed
duke@0 377 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@0 378 // So make it look like we've filled all the G regs that c2 wants to use.
duke@0 379 Register g_reg = TieredCompilation ? noreg : G1;
duke@0 380
duke@0 381 // Count int/oop and float args. See how many stack slots we'll need and
duke@0 382 // where the longs & doubles will go.
duke@0 383 int int_reg_cnt = 0;
duke@0 384 int flt_reg_cnt = 0;
duke@0 385 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@0 386 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@0 387 int stk_reg_pairs = 0;
duke@0 388 for (int i = 0; i < total_args_passed; i++) {
duke@0 389 switch (sig_bt[i]) {
duke@0 390 case T_LONG: // LP64, longs compete with int args
duke@0 391 assert(sig_bt[i+1] == T_VOID, "");
duke@0 392 #ifdef _LP64
duke@0 393 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 394 #endif
duke@0 395 break;
duke@0 396 case T_OBJECT:
duke@0 397 case T_ARRAY:
duke@0 398 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 399 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 400 #ifndef _LP64
duke@0 401 else stk_reg_pairs++;
duke@0 402 #endif
duke@0 403 break;
duke@0 404 case T_INT:
duke@0 405 case T_SHORT:
duke@0 406 case T_CHAR:
duke@0 407 case T_BYTE:
duke@0 408 case T_BOOLEAN:
duke@0 409 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 410 else stk_reg_pairs++;
duke@0 411 break;
duke@0 412 case T_FLOAT:
duke@0 413 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@0 414 else stk_reg_pairs++;
duke@0 415 break;
duke@0 416 case T_DOUBLE:
duke@0 417 assert(sig_bt[i+1] == T_VOID, "");
duke@0 418 break;
duke@0 419 case T_VOID:
duke@0 420 break;
duke@0 421 default:
duke@0 422 ShouldNotReachHere();
duke@0 423 }
duke@0 424 }
duke@0 425
duke@0 426 // This is where the longs/doubles start on the stack.
duke@0 427 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@0 428
duke@0 429 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
duke@0 430 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@0 431
duke@0 432 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@0 433 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@0 434 int stk_reg = 0;
duke@0 435 int int_reg = 0;
duke@0 436 int flt_reg = 0;
duke@0 437
duke@0 438 // Now do the signature layout
duke@0 439 for (int i = 0; i < total_args_passed; i++) {
duke@0 440 switch (sig_bt[i]) {
duke@0 441 case T_INT:
duke@0 442 case T_SHORT:
duke@0 443 case T_CHAR:
duke@0 444 case T_BYTE:
duke@0 445 case T_BOOLEAN:
duke@0 446 #ifndef _LP64
duke@0 447 case T_OBJECT:
duke@0 448 case T_ARRAY:
duke@0 449 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 450 #endif // _LP64
duke@0 451 if (int_reg < int_reg_max) {
duke@0 452 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 453 regs[i].set1(r->as_VMReg());
duke@0 454 } else {
duke@0 455 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 456 }
duke@0 457 break;
duke@0 458
duke@0 459 #ifdef _LP64
duke@0 460 case T_OBJECT:
duke@0 461 case T_ARRAY:
duke@0 462 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 463 if (int_reg < int_reg_max) {
duke@0 464 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 465 regs[i].set2(r->as_VMReg());
duke@0 466 } else {
duke@0 467 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 468 stk_reg_pairs += 2;
duke@0 469 }
duke@0 470 break;
duke@0 471 #endif // _LP64
duke@0 472
duke@0 473 case T_LONG:
duke@0 474 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@0 475 #ifdef _LP64
duke@0 476 if (int_reg < int_reg_max) {
duke@0 477 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 478 regs[i].set2(r->as_VMReg());
duke@0 479 } else {
duke@0 480 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 481 stk_reg_pairs += 2;
duke@0 482 }
duke@0 483 #else
never@297 484 #ifdef COMPILER2
duke@0 485 // For 32-bit build, can't pass longs in O-regs because they become
duke@0 486 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@0 487 // spare and available. This convention isn't used by the Sparc ABI or
duke@0 488 // anywhere else. If we're tiered then we don't use G-regs because c1
never@297 489 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
duke@0 490 // G0: zero
duke@0 491 // G1: 1st Long arg
duke@0 492 // G2: global allocated to TLS
duke@0 493 // G3: used in inline cache check
duke@0 494 // G4: 2nd Long arg
duke@0 495 // G5: used in inline cache check
duke@0 496 // G6: used by OS
duke@0 497 // G7: used by OS
duke@0 498
duke@0 499 if (g_reg == G1) {
duke@0 500 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@0 501 g_reg = G4; // Where the next arg goes
duke@0 502 } else if (g_reg == G4) {
duke@0 503 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@0 504 g_reg = noreg; // No more longs in registers
duke@0 505 } else {
duke@0 506 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 507 stk_reg_pairs += 2;
duke@0 508 }
duke@0 509 #else // COMPILER2
duke@0 510 if (int_reg_pairs + 1 < int_reg_max) {
duke@0 511 if (is_outgoing) {
duke@0 512 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
duke@0 513 } else {
duke@0 514 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
duke@0 515 }
duke@0 516 int_reg_pairs += 2;
duke@0 517 } else {
duke@0 518 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 519 stk_reg_pairs += 2;
duke@0 520 }
duke@0 521 #endif // COMPILER2
never@297 522 #endif // _LP64
duke@0 523 break;
duke@0 524
duke@0 525 case T_FLOAT:
duke@0 526 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
duke@0 527 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
duke@0 528 break;
duke@0 529 case T_DOUBLE:
duke@0 530 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@0 531 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@0 532 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@0 533 flt_reg_pairs += 2;
duke@0 534 } else {
duke@0 535 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 536 stk_reg_pairs += 2;
duke@0 537 }
duke@0 538 break;
duke@0 539 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@0 540 default:
duke@0 541 ShouldNotReachHere();
duke@0 542 }
duke@0 543 }
duke@0 544
duke@0 545 // retun the amount of stack space these arguments will need.
duke@0 546 return stk_reg_pairs;
duke@0 547
duke@0 548 }
duke@0 549
twisti@991 550 // Helper class mostly to avoid passing masm everywhere, and handle
twisti@991 551 // store displacement overflow logic.
duke@0 552 class AdapterGenerator {
duke@0 553 MacroAssembler *masm;
duke@0 554 Register Rdisp;
duke@0 555 void set_Rdisp(Register r) { Rdisp = r; }
duke@0 556
duke@0 557 void patch_callers_callsite();
duke@0 558
duke@0 559 // base+st_off points to top of argument
twisti@1401 560 int arg_offset(const int st_off) { return st_off; }
duke@0 561 int next_arg_offset(const int st_off) {
twisti@1401 562 return st_off - Interpreter::stackElementSize;
twisti@991 563 }
twisti@991 564
twisti@991 565 // Argument slot values may be loaded first into a register because
twisti@991 566 // they might not fit into displacement.
twisti@991 567 RegisterOrConstant arg_slot(const int st_off);
twisti@991 568 RegisterOrConstant next_arg_slot(const int st_off);
twisti@991 569
duke@0 570 // Stores long into offset pointed to by base
duke@0 571 void store_c2i_long(Register r, Register base,
duke@0 572 const int st_off, bool is_stack);
duke@0 573 void store_c2i_object(Register r, Register base,
duke@0 574 const int st_off);
duke@0 575 void store_c2i_int(Register r, Register base,
duke@0 576 const int st_off);
duke@0 577 void store_c2i_double(VMReg r_2,
duke@0 578 VMReg r_1, Register base, const int st_off);
duke@0 579 void store_c2i_float(FloatRegister f, Register base,
duke@0 580 const int st_off);
duke@0 581
duke@0 582 public:
duke@0 583 void gen_c2i_adapter(int total_args_passed,
duke@0 584 // VMReg max_arg,
duke@0 585 int comp_args_on_stack, // VMRegStackSlots
duke@0 586 const BasicType *sig_bt,
duke@0 587 const VMRegPair *regs,
duke@0 588 Label& skip_fixup);
duke@0 589 void gen_i2c_adapter(int total_args_passed,
duke@0 590 // VMReg max_arg,
duke@0 591 int comp_args_on_stack, // VMRegStackSlots
duke@0 592 const BasicType *sig_bt,
duke@0 593 const VMRegPair *regs);
duke@0 594
duke@0 595 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@0 596 };
duke@0 597
duke@0 598
duke@0 599 // Patch the callers callsite with entry to compiled code if it exists.
duke@0 600 void AdapterGenerator::patch_callers_callsite() {
duke@0 601 Label L;
duke@0 602 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
kvn@2600 603 __ br_null(G3_scratch, false, Assembler::pt, L);
duke@0 604 // Schedule the branch target address early.
duke@0 605 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 606 // Call into the VM to patch the caller, then jump to compiled callee
duke@0 607 __ save_frame(4); // Args in compiled layout; do not blow them
duke@0 608
duke@0 609 // Must save all the live Gregs the list is:
duke@0 610 // G1: 1st Long arg (32bit build)
duke@0 611 // G2: global allocated to TLS
duke@0 612 // G3: used in inline cache check (scratch)
duke@0 613 // G4: 2nd Long arg (32bit build);
duke@0 614 // G5: used in inline cache check (methodOop)
duke@0 615
duke@0 616 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@0 617
duke@0 618 #ifdef _LP64
duke@0 619 // mov(s,d)
duke@0 620 __ mov(G1, L1);
duke@0 621 __ mov(G4, L4);
duke@0 622 __ mov(G5_method, L5);
duke@0 623 __ mov(G5_method, O0); // VM needs target method
duke@0 624 __ mov(I7, O1); // VM needs caller's callsite
duke@0 625 // Must be a leaf call...
duke@0 626 // can be very far once the blob has been relocated
twisti@720 627 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@0 628 __ relocate(relocInfo::runtime_call_type);
twisti@720 629 __ jumpl_to(dest, O7, O7);
duke@0 630 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 631 __ mov(L7_thread_cache, G2_thread);
duke@0 632 __ mov(L1, G1);
duke@0 633 __ mov(L4, G4);
duke@0 634 __ mov(L5, G5_method);
duke@0 635 #else
duke@0 636 __ stx(G1, FP, -8 + STACK_BIAS);
duke@0 637 __ stx(G4, FP, -16 + STACK_BIAS);
duke@0 638 __ mov(G5_method, L5);
duke@0 639 __ mov(G5_method, O0); // VM needs target method
duke@0 640 __ mov(I7, O1); // VM needs caller's callsite
duke@0 641 // Must be a leaf call...
duke@0 642 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@0 643 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 644 __ mov(L7_thread_cache, G2_thread);
duke@0 645 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@0 646 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@0 647 __ mov(L5, G5_method);
duke@0 648 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 649 #endif /* _LP64 */
duke@0 650
duke@0 651 __ restore(); // Restore args
duke@0 652 __ bind(L);
duke@0 653 }
duke@0 654
twisti@991 655
twisti@991 656 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
twisti@991 657 RegisterOrConstant roc(arg_offset(st_off));
twisti@991 658 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 659 }
duke@0 660
twisti@991 661 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
twisti@991 662 RegisterOrConstant roc(next_arg_offset(st_off));
twisti@991 663 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 664 }
twisti@991 665
twisti@991 666
duke@0 667 // Stores long into offset pointed to by base
duke@0 668 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@0 669 const int st_off, bool is_stack) {
duke@0 670 #ifdef _LP64
duke@0 671 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 672 // data is passed in only 1 slot.
duke@0 673 __ stx(r, base, next_arg_slot(st_off));
duke@0 674 #else
ysr@344 675 #ifdef COMPILER2
duke@0 676 // Misaligned store of 64-bit data
duke@0 677 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 678 __ srlx(r, 32, r);
duke@0 679 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 680 #else
duke@0 681 if (is_stack) {
duke@0 682 // Misaligned store of 64-bit data
duke@0 683 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 684 __ srlx(r, 32, r);
duke@0 685 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 686 } else {
duke@0 687 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@0 688 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@0 689 }
duke@0 690 #endif // COMPILER2
ysr@344 691 #endif // _LP64
duke@0 692 }
duke@0 693
duke@0 694 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@0 695 const int st_off) {
duke@0 696 __ st_ptr (r, base, arg_slot(st_off));
duke@0 697 }
duke@0 698
duke@0 699 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@0 700 const int st_off) {
duke@0 701 __ st (r, base, arg_slot(st_off));
duke@0 702 }
duke@0 703
duke@0 704 // Stores into offset pointed to by base
duke@0 705 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@0 706 VMReg r_1, Register base, const int st_off) {
duke@0 707 #ifdef _LP64
duke@0 708 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 709 // data is passed in only 1 slot.
duke@0 710 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 711 #else
duke@0 712 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 713 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 714 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@0 715 #endif
duke@0 716 }
duke@0 717
duke@0 718 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@0 719 const int st_off) {
duke@0 720 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@0 721 }
duke@0 722
duke@0 723 void AdapterGenerator::gen_c2i_adapter(
duke@0 724 int total_args_passed,
duke@0 725 // VMReg max_arg,
duke@0 726 int comp_args_on_stack, // VMRegStackSlots
duke@0 727 const BasicType *sig_bt,
duke@0 728 const VMRegPair *regs,
duke@0 729 Label& skip_fixup) {
duke@0 730
duke@0 731 // Before we get into the guts of the C2I adapter, see if we should be here
duke@0 732 // at all. We've come from compiled code and are attempting to jump to the
duke@0 733 // interpreter, which means the caller made a static call to get here
duke@0 734 // (vcalls always get a compiled target if there is one). Check for a
duke@0 735 // compiled target. If there is one, we need to patch the caller's call.
duke@0 736 // However we will run interpreted if we come thru here. The next pass
duke@0 737 // thru the call site will run compiled. If we ran compiled here then
duke@0 738 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@0 739 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@0 740 // we can have at most one and don't need to play any tricks to keep
duke@0 741 // from endlessly growing the stack.
duke@0 742 //
duke@0 743 // Actually if we detected that we had an i2c->c2i transition here we
duke@0 744 // ought to be able to reset the world back to the state of the interpreted
duke@0 745 // call and not bother building another interpreter arg area. We don't
duke@0 746 // do that at this point.
duke@0 747
duke@0 748 patch_callers_callsite();
duke@0 749
duke@0 750 __ bind(skip_fixup);
duke@0 751
duke@0 752 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@0 753 // space we need. Add in varargs area needed by the interpreter. Round up
duke@0 754 // to stack alignment.
twisti@1401 755 const int arg_size = total_args_passed * Interpreter::stackElementSize;
duke@0 756 const int varargs_area =
duke@0 757 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@0 758 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@0 759
duke@0 760 int bias = STACK_BIAS;
duke@0 761 const int interp_arg_offset = frame::varargs_offset*wordSize +
twisti@1401 762 (total_args_passed-1)*Interpreter::stackElementSize;
duke@0 763
duke@0 764 Register base = SP;
duke@0 765
duke@0 766 #ifdef _LP64
duke@0 767 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@0 768 // out of bits in the displacement to do loads and stores. Use g3 as
duke@0 769 // temporary displacement.
duke@0 770 if (! __ is_simm13(extraspace)) {
duke@0 771 __ set(extraspace, G3_scratch);
duke@0 772 __ sub(SP, G3_scratch, SP);
duke@0 773 } else {
duke@0 774 __ sub(SP, extraspace, SP);
duke@0 775 }
duke@0 776 set_Rdisp(G3_scratch);
duke@0 777 #else
duke@0 778 __ sub(SP, extraspace, SP);
duke@0 779 #endif // _LP64
duke@0 780
duke@0 781 // First write G1 (if used) to where ever it must go
duke@0 782 for (int i=0; i<total_args_passed; i++) {
twisti@1401 783 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 784 VMReg r_1 = regs[i].first();
duke@0 785 VMReg r_2 = regs[i].second();
duke@0 786 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 787 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 788 store_c2i_object(G1_scratch, base, st_off);
duke@0 789 } else if (sig_bt[i] == T_LONG) {
duke@0 790 assert(!TieredCompilation, "should not use register args for longs");
duke@0 791 store_c2i_long(G1_scratch, base, st_off, false);
duke@0 792 } else {
duke@0 793 store_c2i_int(G1_scratch, base, st_off);
duke@0 794 }
duke@0 795 }
duke@0 796 }
duke@0 797
duke@0 798 // Now write the args into the outgoing interpreter space
duke@0 799 for (int i=0; i<total_args_passed; i++) {
twisti@1401 800 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 801 VMReg r_1 = regs[i].first();
duke@0 802 VMReg r_2 = regs[i].second();
duke@0 803 if (!r_1->is_valid()) {
duke@0 804 assert(!r_2->is_valid(), "");
duke@0 805 continue;
duke@0 806 }
duke@0 807 // Skip G1 if found as we did it first in order to free it up
duke@0 808 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 809 continue;
duke@0 810 }
duke@0 811 #ifdef ASSERT
duke@0 812 bool G1_forced = false;
duke@0 813 #endif // ASSERT
duke@0 814 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@0 815 #ifdef _LP64
duke@0 816 Register ld_off = Rdisp;
duke@0 817 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@0 818 #else
duke@0 819 int ld_off = reg2offset(r_1) + extraspace + bias;
kvn@1209 820 #endif // _LP64
duke@0 821 #ifdef ASSERT
duke@0 822 G1_forced = true;
duke@0 823 #endif // ASSERT
duke@0 824 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@0 825 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@0 826 else __ ldx(base, ld_off, G1_scratch);
duke@0 827 }
duke@0 828
duke@0 829 if (r_1->is_Register()) {
duke@0 830 Register r = r_1->as_Register()->after_restore();
duke@0 831 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 832 store_c2i_object(r, base, st_off);
duke@0 833 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
kvn@1209 834 #ifndef _LP64
duke@0 835 if (TieredCompilation) {
duke@0 836 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@0 837 }
kvn@1209 838 #endif // _LP64
duke@0 839 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@0 840 } else {
duke@0 841 store_c2i_int(r, base, st_off);
duke@0 842 }
duke@0 843 } else {
duke@0 844 assert(r_1->is_FloatRegister(), "");
duke@0 845 if (sig_bt[i] == T_FLOAT) {
duke@0 846 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@0 847 } else {
duke@0 848 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@0 849 store_c2i_double(r_2, r_1, base, st_off);
duke@0 850 }
duke@0 851 }
duke@0 852 }
duke@0 853
duke@0 854 #ifdef _LP64
duke@0 855 // Need to reload G3_scratch, used for temporary displacements.
duke@0 856 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 857
duke@0 858 // Pass O5_savedSP as an argument to the interpreter.
duke@0 859 // The interpreter will restore SP to this value before returning.
duke@0 860 __ set(extraspace, G1);
duke@0 861 __ add(SP, G1, O5_savedSP);
duke@0 862 #else
duke@0 863 // Pass O5_savedSP as an argument to the interpreter.
duke@0 864 // The interpreter will restore SP to this value before returning.
duke@0 865 __ add(SP, extraspace, O5_savedSP);
duke@0 866 #endif // _LP64
duke@0 867
duke@0 868 __ mov((frame::varargs_offset)*wordSize -
twisti@1401 869 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
duke@0 870 // Jump to the interpreter just as if interpreter was doing it.
duke@0 871 __ jmpl(G3_scratch, 0, G0);
duke@0 872 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@0 873 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@0 874 // the interpreter does not know where its args are without some kind of
duke@0 875 // arg pointer being passed in. Pass it in Gargs.
duke@0 876 __ delayed()->add(SP, G1, Gargs);
duke@0 877 }
duke@0 878
duke@0 879 void AdapterGenerator::gen_i2c_adapter(
duke@0 880 int total_args_passed,
duke@0 881 // VMReg max_arg,
duke@0 882 int comp_args_on_stack, // VMRegStackSlots
duke@0 883 const BasicType *sig_bt,
duke@0 884 const VMRegPair *regs) {
duke@0 885
duke@0 886 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@0 887 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@0 888 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@0 889 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@0 890 // hoist register arguments and repack other args according to the compiled
duke@0 891 // code convention. Finally, end in a jump to the compiled code. The entry
duke@0 892 // point address is the start of the buffer.
duke@0 893
duke@0 894 // We will only enter here from an interpreted frame and never from after
duke@0 895 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@0 896 // race and use a c2i we will remain interpreted for the race loser(s).
duke@0 897 // This removes all sorts of headaches on the x86 side and also eliminates
duke@0 898 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@0 899
duke@0 900 // As you can see from the list of inputs & outputs there are not a lot
duke@0 901 // of temp registers to work with: mostly G1, G3 & G4.
duke@0 902
duke@0 903 // Inputs:
duke@0 904 // G2_thread - TLS
duke@0 905 // G5_method - Method oop
jrose@689 906 // G4 (Gargs) - Pointer to interpreter's args
jrose@689 907 // O0..O4 - free for scratch
jrose@689 908 // O5_savedSP - Caller's saved SP, to be restored if needed
duke@0 909 // O6 - Current SP!
duke@0 910 // O7 - Valid return address
jrose@689 911 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 912
duke@0 913 // Outputs:
duke@0 914 // G2_thread - TLS
duke@0 915 // G1, G4 - Outgoing long args in 32-bit build
duke@0 916 // O0-O5 - Outgoing args in compiled layout
duke@0 917 // O6 - Adjusted or restored SP
duke@0 918 // O7 - Valid return address
twisti@1457 919 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 920 // F0-F7 - more outgoing args
duke@0 921
duke@0 922
jrose@689 923 // Gargs is the incoming argument base, and also an outgoing argument.
duke@0 924 __ sub(Gargs, BytesPerWord, Gargs);
duke@0 925
duke@0 926 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@0 927 // WITH O7 HOLDING A VALID RETURN PC
duke@0 928 //
duke@0 929 // | |
duke@0 930 // : java stack :
duke@0 931 // | |
duke@0 932 // +--------------+ <--- start of outgoing args
duke@0 933 // | receiver | |
duke@0 934 // : rest of args : |---size is java-arg-words
duke@0 935 // | | |
duke@0 936 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@0 937 // | | |
duke@0 938 // : unused : |---Space for max Java stack, plus stack alignment
duke@0 939 // | | |
duke@0 940 // +--------------+ <--- SP + 16*wordsize
duke@0 941 // | |
duke@0 942 // : window :
duke@0 943 // | |
duke@0 944 // +--------------+ <--- SP
duke@0 945
duke@0 946 // WE REPACK THE STACK. We use the common calling convention layout as
duke@0 947 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@0 948 // causes an arbitrary shuffle of memory, which may require some register
duke@0 949 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@0 950 // temps are not needed. We may have to resize the stack slightly, in case
duke@0 951 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@0 952 // misaligned, but the compilers expect them aligned).
duke@0 953 //
duke@0 954 // | |
duke@0 955 // : java stack :
duke@0 956 // | |
duke@0 957 // +--------------+ <--- start of outgoing args
duke@0 958 // | pad, align | |
duke@0 959 // +--------------+ |
duke@0 960 // | ints, floats | |---Outgoing stack args, packed low.
duke@0 961 // +--------------+ | First few args in registers.
duke@0 962 // : doubles : |
duke@0 963 // | longs | |
duke@0 964 // +--------------+ <--- SP' + 16*wordsize
duke@0 965 // | |
duke@0 966 // : window :
duke@0 967 // | |
duke@0 968 // +--------------+ <--- SP'
duke@0 969
duke@0 970 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@0 971 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@0 972 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@0 973
duke@0 974 // Cut-out for having no stack args. Since up to 6 args are passed
duke@0 975 // in registers, we will commonly have no stack args.
duke@0 976 if (comp_args_on_stack > 0) {
duke@0 977
duke@0 978 // Convert VMReg stack slots to words.
duke@0 979 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@0 980 // Round up to miminum stack alignment, in wordSize
duke@0 981 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@0 982 // Now compute the distance from Lesp to SP. This calculation does not
duke@0 983 // include the space for total_args_passed because Lesp has not yet popped
duke@0 984 // the arguments.
duke@0 985 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@0 986 }
duke@0 987
duke@0 988 // Will jump to the compiled code just as if compiled code was doing it.
duke@0 989 // Pre-load the register-jump target early, to schedule it better.
duke@0 990 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@0 991
duke@0 992 // Now generate the shuffle code. Pick up all register args and move the
duke@0 993 // rest through G1_scratch.
duke@0 994 for (int i=0; i<total_args_passed; i++) {
duke@0 995 if (sig_bt[i] == T_VOID) {
duke@0 996 // Longs and doubles are passed in native word order, but misaligned
duke@0 997 // in the 32-bit build.
duke@0 998 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@0 999 continue;
duke@0 1000 }
duke@0 1001
duke@0 1002 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@0 1003 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@0 1004 // ldx/lddf optimizations.
duke@0 1005
duke@0 1006 // Load in argument order going down.
twisti@1401 1007 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1008 set_Rdisp(G1_scratch);
duke@0 1009
duke@0 1010 VMReg r_1 = regs[i].first();
duke@0 1011 VMReg r_2 = regs[i].second();
duke@0 1012 if (!r_1->is_valid()) {
duke@0 1013 assert(!r_2->is_valid(), "");
duke@0 1014 continue;
duke@0 1015 }
duke@0 1016 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@0 1017 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@0 1018 if (r_2->is_valid()) r_2 = r_1->next();
duke@0 1019 }
duke@0 1020 if (r_1->is_Register()) { // Register argument
duke@0 1021 Register r = r_1->as_Register()->after_restore();
duke@0 1022 if (!r_2->is_valid()) {
duke@0 1023 __ ld(Gargs, arg_slot(ld_off), r);
duke@0 1024 } else {
duke@0 1025 #ifdef _LP64
duke@0 1026 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 1027 // data is passed in only 1 slot.
twisti@991 1028 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
duke@0 1029 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1030 __ ldx(Gargs, slot, r);
duke@0 1031 #else
duke@0 1032 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@0 1033 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@0 1034 #endif
duke@0 1035 }
duke@0 1036 } else {
duke@0 1037 assert(r_1->is_FloatRegister(), "");
duke@0 1038 if (!r_2->is_valid()) {
duke@0 1039 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1040 } else {
duke@0 1041 #ifdef _LP64
duke@0 1042 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 1043 // data is passed in only 1 slot. This code also handles longs that
duke@0 1044 // are passed on the stack, but need a stack-to-stack move through a
duke@0 1045 // spare float register.
twisti@991 1046 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@0 1047 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1048 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@0 1049 #else
duke@0 1050 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1051 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1052 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@0 1053 #endif
duke@0 1054 }
duke@0 1055 }
duke@0 1056 // Was the argument really intended to be on the stack, but was loaded
duke@0 1057 // into F8/F9?
duke@0 1058 if (regs[i].first()->is_stack()) {
duke@0 1059 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@0 1060 // Convert stack slot to an SP offset
duke@0 1061 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@0 1062 // Store down the shuffled stack word. Target address _is_ aligned.
twisti@991 1063 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
twisti@991 1064 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
twisti@991 1065 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
duke@0 1066 }
duke@0 1067 }
duke@0 1068 bool made_space = false;
duke@0 1069 #ifndef _LP64
duke@0 1070 // May need to pick up a few long args in G1/G4
duke@0 1071 bool g4_crushed = false;
duke@0 1072 bool g3_crushed = false;
duke@0 1073 for (int i=0; i<total_args_passed; i++) {
duke@0 1074 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@0 1075 // Load in argument order going down
twisti@1401 1076 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1077 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1078 Register r = regs[i].first()->as_Register()->after_restore();
duke@0 1079 if (r == G1 || r == G4) {
duke@0 1080 assert(!g4_crushed, "ordering problem");
duke@0 1081 if (r == G4){
duke@0 1082 g4_crushed = true;
duke@0 1083 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1084 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1085 } else {
duke@0 1086 // better schedule this way
duke@0 1087 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1088 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1089 }
duke@0 1090 g3_crushed = true;
duke@0 1091 __ sllx(r, 32, r);
duke@0 1092 __ or3(G3_scratch, r, r);
duke@0 1093 } else {
duke@0 1094 assert(r->is_out(), "longs passed in two O registers");
duke@0 1095 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@0 1096 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1097 }
duke@0 1098 }
duke@0 1099 }
duke@0 1100 #endif
duke@0 1101
duke@0 1102 // Jump to the compiled code just as if compiled code was doing it.
duke@0 1103 //
duke@0 1104 #ifndef _LP64
duke@0 1105 if (g3_crushed) {
duke@0 1106 // Rats load was wasted, at least it is in cache...
twisti@720 1107 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
duke@0 1108 }
duke@0 1109 #endif /* _LP64 */
duke@0 1110
duke@0 1111 // 6243940 We might end up in handle_wrong_method if
duke@0 1112 // the callee is deoptimized as we race thru here. If that
duke@0 1113 // happens we don't want to take a safepoint because the
duke@0 1114 // caller frame will look interpreted and arguments are now
duke@0 1115 // "compiled" so it is much better to make this transition
duke@0 1116 // invisible to the stack walking code. Unfortunately if
duke@0 1117 // we try and find the callee by normal means a safepoint
duke@0 1118 // is possible. So we stash the desired callee in the thread
duke@0 1119 // and the vm will find there should this case occur.
twisti@720 1120 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
duke@0 1121 __ st_ptr(G5_method, callee_target_addr);
duke@0 1122
duke@0 1123 if (StressNonEntrant) {
duke@0 1124 // Open a big window for deopt failure
duke@0 1125 __ save_frame(0);
duke@0 1126 __ mov(G0, L0);
duke@0 1127 Label loop;
duke@0 1128 __ bind(loop);
duke@0 1129 __ sub(L0, 1, L0);
kvn@2600 1130 __ br_null_short(L0, Assembler::pt, loop);
duke@0 1131
duke@0 1132 __ restore();
duke@0 1133 }
duke@0 1134
duke@0 1135
duke@0 1136 __ jmpl(G3, 0, G0);
duke@0 1137 __ delayed()->nop();
duke@0 1138 }
duke@0 1139
duke@0 1140 // ---------------------------------------------------------------
duke@0 1141 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@0 1142 int total_args_passed,
duke@0 1143 // VMReg max_arg,
duke@0 1144 int comp_args_on_stack, // VMRegStackSlots
duke@0 1145 const BasicType *sig_bt,
never@1179 1146 const VMRegPair *regs,
never@1179 1147 AdapterFingerPrint* fingerprint) {
duke@0 1148 address i2c_entry = __ pc();
duke@0 1149
duke@0 1150 AdapterGenerator agen(masm);
duke@0 1151
duke@0 1152 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@0 1153
duke@0 1154
duke@0 1155 // -------------------------------------------------------------------------
duke@0 1156 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
duke@0 1157 // args start out packed in the compiled layout. They need to be unpacked
duke@0 1158 // into the interpreter layout. This will almost always require some stack
duke@0 1159 // space. We grow the current (compiled) stack, then repack the args. We
duke@0 1160 // finally end in a jump to the generic interpreter entry point. On exit
duke@0 1161 // from the interpreter, the interpreter will restore our SP (lest the
duke@0 1162 // compiled code, which relys solely on SP and not FP, get sick).
duke@0 1163
duke@0 1164 address c2i_unverified_entry = __ pc();
duke@0 1165 Label skip_fixup;
duke@0 1166 {
duke@0 1167 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1168 Register R_temp = L0; // another scratch register
duke@0 1169 #else
duke@0 1170 Register R_temp = G1; // another scratch register
duke@0 1171 #endif
duke@0 1172
twisti@720 1173 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1174
duke@0 1175 __ verify_oop(O0);
duke@0 1176 __ verify_oop(G5_method);
coleenp@108 1177 __ load_klass(O0, G3_scratch);
duke@0 1178 __ verify_oop(G3_scratch);
duke@0 1179
duke@0 1180 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1181 __ save(SP, -frame::register_save_words*wordSize, SP);
duke@0 1182 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1183 __ verify_oop(R_temp);
duke@0 1184 __ cmp(G3_scratch, R_temp);
duke@0 1185 __ restore();
duke@0 1186 #else
duke@0 1187 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1188 __ verify_oop(R_temp);
duke@0 1189 __ cmp(G3_scratch, R_temp);
duke@0 1190 #endif
duke@0 1191
duke@0 1192 Label ok, ok2;
duke@0 1193 __ brx(Assembler::equal, false, Assembler::pt, ok);
duke@0 1194 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
twisti@720 1195 __ jump_to(ic_miss, G3_scratch);
duke@0 1196 __ delayed()->nop();
duke@0 1197
duke@0 1198 __ bind(ok);
duke@0 1199 // Method might have been compiled since the call site was patched to
duke@0 1200 // interpreted if that is the case treat it as a miss so we can get
duke@0 1201 // the call site corrected.
duke@0 1202 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 1203 __ bind(ok2);
kvn@2600 1204 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup);
duke@0 1205 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
twisti@720 1206 __ jump_to(ic_miss, G3_scratch);
duke@0 1207 __ delayed()->nop();
duke@0 1208
duke@0 1209 }
duke@0 1210
duke@0 1211 address c2i_entry = __ pc();
duke@0 1212
duke@0 1213 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@0 1214
duke@0 1215 __ flush();
never@1179 1216 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
duke@0 1217
duke@0 1218 }
duke@0 1219
duke@0 1220 // Helper function for native calling conventions
duke@0 1221 static VMReg int_stk_helper( int i ) {
duke@0 1222 // Bias any stack based VMReg we get by ignoring the window area
duke@0 1223 // but not the register parameter save area.
duke@0 1224 //
duke@0 1225 // This is strange for the following reasons. We'd normally expect
duke@0 1226 // the calling convention to return an VMReg for a stack slot
duke@0 1227 // completely ignoring any abi reserved area. C2 thinks of that
duke@0 1228 // abi area as only out_preserve_stack_slots. This does not include
duke@0 1229 // the area allocated by the C abi to store down integer arguments
duke@0 1230 // because the java calling convention does not use it. So
duke@0 1231 // since c2 assumes that there are only out_preserve_stack_slots
duke@0 1232 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@0 1233 // location the c calling convention must add in this bias amount
duke@0 1234 // to make up for the fact that the out_preserve_stack_slots is
duke@0 1235 // insufficient for C calls. What a mess. I sure hope those 6
duke@0 1236 // stack words were worth it on every java call!
duke@0 1237
duke@0 1238 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@0 1239 // to take a parameter to say whether it was C or java calling conventions.
duke@0 1240 // Then things might look a little better (but not much).
duke@0 1241
duke@0 1242 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@0 1243 if( mem_parm_offset < 0 ) {
duke@0 1244 return as_oRegister(i)->as_VMReg();
duke@0 1245 } else {
duke@0 1246 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@0 1247 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@0 1248 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@0 1249 }
duke@0 1250 }
duke@0 1251
duke@0 1252
duke@0 1253 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@0 1254 VMRegPair *regs,
duke@0 1255 int total_args_passed) {
duke@0 1256
duke@0 1257 // Return the number of VMReg stack_slots needed for the args.
duke@0 1258 // This value does not include an abi space (like register window
duke@0 1259 // save area).
duke@0 1260
duke@0 1261 // The native convention is V8 if !LP64
duke@0 1262 // The LP64 convention is the V9 convention which is slightly more sane.
duke@0 1263
duke@0 1264 // We return the amount of VMReg stack slots we need to reserve for all
duke@0 1265 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@0 1266 // have space for storing at least 6 registers to memory we start with that.
duke@0 1267 // See int_stk_helper for a further discussion.
duke@0 1268 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@0 1269
duke@0 1270 #ifdef _LP64
duke@0 1271 // V9 convention: All things "as-if" on double-wide stack slots.
duke@0 1272 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@0 1273 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@0 1274 int j = 0; // Count of actual args, not HALVES
duke@0 1275 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@0 1276 switch( sig_bt[i] ) {
duke@0 1277 case T_BOOLEAN:
duke@0 1278 case T_BYTE:
duke@0 1279 case T_CHAR:
duke@0 1280 case T_INT:
duke@0 1281 case T_SHORT:
duke@0 1282 regs[i].set1( int_stk_helper( j ) ); break;
duke@0 1283 case T_LONG:
duke@0 1284 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1285 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1286 case T_ARRAY:
duke@0 1287 case T_OBJECT:
duke@0 1288 regs[i].set2( int_stk_helper( j ) );
duke@0 1289 break;
duke@0 1290 case T_FLOAT:
duke@0 1291 if ( j < 16 ) {
duke@0 1292 // V9ism: floats go in ODD registers
duke@0 1293 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@0 1294 } else {
duke@0 1295 // V9ism: floats go in ODD stack slot
duke@0 1296 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@0 1297 }
duke@0 1298 break;
duke@0 1299 case T_DOUBLE:
duke@0 1300 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1301 if ( j < 16 ) {
duke@0 1302 // V9ism: doubles go in EVEN/ODD regs
duke@0 1303 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@0 1304 } else {
duke@0 1305 // V9ism: doubles go in EVEN/ODD stack slots
duke@0 1306 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@0 1307 }
duke@0 1308 break;
duke@0 1309 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@0 1310 default:
duke@0 1311 ShouldNotReachHere();
duke@0 1312 }
duke@0 1313 if (regs[i].first()->is_stack()) {
duke@0 1314 int off = regs[i].first()->reg2stack();
duke@0 1315 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1316 }
duke@0 1317 if (regs[i].second()->is_stack()) {
duke@0 1318 int off = regs[i].second()->reg2stack();
duke@0 1319 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1320 }
duke@0 1321 }
duke@0 1322
duke@0 1323 #else // _LP64
duke@0 1324 // V8 convention: first 6 things in O-regs, rest on stack.
duke@0 1325 // Alignment is willy-nilly.
duke@0 1326 for( int i=0; i<total_args_passed; i++ ) {
duke@0 1327 switch( sig_bt[i] ) {
duke@0 1328 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1329 case T_ARRAY:
duke@0 1330 case T_BOOLEAN:
duke@0 1331 case T_BYTE:
duke@0 1332 case T_CHAR:
duke@0 1333 case T_FLOAT:
duke@0 1334 case T_INT:
duke@0 1335 case T_OBJECT:
duke@0 1336 case T_SHORT:
duke@0 1337 regs[i].set1( int_stk_helper( i ) );
duke@0 1338 break;
duke@0 1339 case T_DOUBLE:
duke@0 1340 case T_LONG:
duke@0 1341 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1342 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@0 1343 break;
duke@0 1344 case T_VOID: regs[i].set_bad(); break;
duke@0 1345 default:
duke@0 1346 ShouldNotReachHere();
duke@0 1347 }
duke@0 1348 if (regs[i].first()->is_stack()) {
duke@0 1349 int off = regs[i].first()->reg2stack();
duke@0 1350 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1351 }
duke@0 1352 if (regs[i].second()->is_stack()) {
duke@0 1353 int off = regs[i].second()->reg2stack();
duke@0 1354 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1355 }
duke@0 1356 }
duke@0 1357 #endif // _LP64
duke@0 1358
duke@0 1359 return round_to(max_stack_slots + 1, 2);
duke@0 1360
duke@0 1361 }
duke@0 1362
duke@0 1363
duke@0 1364 // ---------------------------------------------------------------------------
duke@0 1365 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1366 switch (ret_type) {
duke@0 1367 case T_FLOAT:
duke@0 1368 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@0 1369 break;
duke@0 1370 case T_DOUBLE:
duke@0 1371 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@0 1372 break;
duke@0 1373 }
duke@0 1374 }
duke@0 1375
duke@0 1376 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1377 switch (ret_type) {
duke@0 1378 case T_FLOAT:
duke@0 1379 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@0 1380 break;
duke@0 1381 case T_DOUBLE:
duke@0 1382 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@0 1383 break;
duke@0 1384 }
duke@0 1385 }
duke@0 1386
duke@0 1387 // Check and forward and pending exception. Thread is stored in
duke@0 1388 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@0 1389 // is no exception handler. We merely pop this frame off and throw the
duke@0 1390 // exception in the caller's frame.
duke@0 1391 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@0 1392 Label L;
duke@0 1393 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@0 1394 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@0 1395 // Since this is a native call, we *know* the proper exception handler
duke@0 1396 // without calling into the VM: it's the empty function. Just pop this
duke@0 1397 // frame and then jump to forward_exception_entry; O7 will contain the
duke@0 1398 // native caller's return PC.
twisti@720 1399 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
twisti@720 1400 __ jump_to(exception_entry, G3_scratch);
duke@0 1401 __ delayed()->restore(); // Pop this frame off.
duke@0 1402 __ bind(L);
duke@0 1403 }
duke@0 1404
duke@0 1405 // A simple move of integer like type
duke@0 1406 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1407 if (src.first()->is_stack()) {
duke@0 1408 if (dst.first()->is_stack()) {
duke@0 1409 // stack to stack
duke@0 1410 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1411 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1412 } else {
duke@0 1413 // stack to reg
duke@0 1414 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1415 }
duke@0 1416 } else if (dst.first()->is_stack()) {
duke@0 1417 // reg to stack
duke@0 1418 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1419 } else {
duke@0 1420 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1421 }
duke@0 1422 }
duke@0 1423
duke@0 1424 // On 64 bit we will store integer like items to the stack as
duke@0 1425 // 64 bits items (sparc abi) even though java would only store
duke@0 1426 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@0 1427 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@0 1428 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1429 if (src.first()->is_stack()) {
duke@0 1430 if (dst.first()->is_stack()) {
duke@0 1431 // stack to stack
duke@0 1432 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1433 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1434 } else {
duke@0 1435 // stack to reg
duke@0 1436 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1437 }
duke@0 1438 } else if (dst.first()->is_stack()) {
duke@0 1439 // reg to stack
duke@0 1440 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1441 } else {
duke@0 1442 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1443 }
duke@0 1444 }
duke@0 1445
duke@0 1446
duke@0 1447 // An oop arg. Must pass a handle not the oop itself
duke@0 1448 static void object_move(MacroAssembler* masm,
duke@0 1449 OopMap* map,
duke@0 1450 int oop_handle_offset,
duke@0 1451 int framesize_in_slots,
duke@0 1452 VMRegPair src,
duke@0 1453 VMRegPair dst,
duke@0 1454 bool is_receiver,
duke@0 1455 int* receiver_offset) {
duke@0 1456
duke@0 1457 // must pass a handle. First figure out the location we use as a handle
duke@0 1458
duke@0 1459 if (src.first()->is_stack()) {
duke@0 1460 // Oop is already on the stack
duke@0 1461 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@0 1462 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@0 1463 __ ld_ptr(rHandle, 0, L4);
duke@0 1464 #ifdef _LP64
duke@0 1465 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@0 1466 #else
duke@0 1467 __ tst( L4 );
duke@0 1468 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1469 #endif
duke@0 1470 if (dst.first()->is_stack()) {
duke@0 1471 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1472 }
duke@0 1473 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@0 1474 if (is_receiver) {
duke@0 1475 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@0 1476 }
duke@0 1477 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@0 1478 } else {
duke@0 1479 // Oop is in an input register pass we must flush it to the stack
duke@0 1480 const Register rOop = src.first()->as_Register();
duke@0 1481 const Register rHandle = L5;
duke@0 1482 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@0 1483 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@0 1484 Label skip;
duke@0 1485 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@0 1486 if (is_receiver) {
duke@0 1487 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@0 1488 }
duke@0 1489 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@0 1490 __ add(SP, offset + STACK_BIAS, rHandle);
duke@0 1491 #ifdef _LP64
duke@0 1492 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@0 1493 #else
duke@0 1494 __ tst( rOop );
duke@0 1495 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1496 #endif
duke@0 1497
duke@0 1498 if (dst.first()->is_stack()) {
duke@0 1499 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1500 } else {
duke@0 1501 __ mov(rHandle, dst.first()->as_Register());
duke@0 1502 }
duke@0 1503 }
duke@0 1504 }
duke@0 1505
duke@0 1506 // A float arg may have to do float reg int reg conversion
duke@0 1507 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1508 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@0 1509
duke@0 1510 if (src.first()->is_stack()) {
duke@0 1511 if (dst.first()->is_stack()) {
duke@0 1512 // stack to stack the easiest of the bunch
duke@0 1513 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1514 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1515 } else {
duke@0 1516 // stack to reg
duke@0 1517 if (dst.first()->is_Register()) {
duke@0 1518 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1519 } else {
duke@0 1520 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1521 }
duke@0 1522 }
duke@0 1523 } else if (dst.first()->is_stack()) {
duke@0 1524 // reg to stack
duke@0 1525 if (src.first()->is_Register()) {
duke@0 1526 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1527 } else {
duke@0 1528 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1529 }
duke@0 1530 } else {
duke@0 1531 // reg to reg
duke@0 1532 if (src.first()->is_Register()) {
duke@0 1533 if (dst.first()->is_Register()) {
duke@0 1534 // gpr -> gpr
duke@0 1535 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1536 } else {
duke@0 1537 // gpr -> fpr
duke@0 1538 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1539 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1540 }
duke@0 1541 } else if (dst.first()->is_Register()) {
duke@0 1542 // fpr -> gpr
duke@0 1543 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@0 1544 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@0 1545 } else {
duke@0 1546 // fpr -> fpr
duke@0 1547 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1548 if ( src.first() != dst.first()) {
duke@0 1549 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1550 }
duke@0 1551 }
duke@0 1552 }
duke@0 1553 }
duke@0 1554
duke@0 1555 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1556 VMRegPair src_lo(src.first());
duke@0 1557 VMRegPair src_hi(src.second());
duke@0 1558 VMRegPair dst_lo(dst.first());
duke@0 1559 VMRegPair dst_hi(dst.second());
duke@0 1560 simple_move32(masm, src_lo, dst_lo);
duke@0 1561 simple_move32(masm, src_hi, dst_hi);
duke@0 1562 }
duke@0 1563
duke@0 1564 // A long move
duke@0 1565 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1566
duke@0 1567 // Do the simple ones here else do two int moves
duke@0 1568 if (src.is_single_phys_reg() ) {
duke@0 1569 if (dst.is_single_phys_reg()) {
duke@0 1570 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1571 } else {
duke@0 1572 // split src into two separate registers
duke@0 1573 // Remember hi means hi address or lsw on sparc
duke@0 1574 // Move msw to lsw
duke@0 1575 if (dst.second()->is_reg()) {
duke@0 1576 // MSW -> MSW
duke@0 1577 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@0 1578 // Now LSW -> LSW
duke@0 1579 // this will only move lo -> lo and ignore hi
duke@0 1580 VMRegPair split(dst.second());
duke@0 1581 simple_move32(masm, src, split);
duke@0 1582 } else {
duke@0 1583 VMRegPair split(src.first(), L4->as_VMReg());
duke@0 1584 // MSW -> MSW (lo ie. first word)
duke@0 1585 __ srax(src.first()->as_Register(), 32, L4);
duke@0 1586 split_long_move(masm, split, dst);
duke@0 1587 }
duke@0 1588 }
duke@0 1589 } else if (dst.is_single_phys_reg()) {
duke@0 1590 if (src.is_adjacent_aligned_on_stack(2)) {
never@297 1591 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1592 } else {
duke@0 1593 // dst is a single reg.
duke@0 1594 // Remember lo is low address not msb for stack slots
duke@0 1595 // and lo is the "real" register for registers
duke@0 1596 // src is
duke@0 1597
duke@0 1598 VMRegPair split;
duke@0 1599
duke@0 1600 if (src.first()->is_reg()) {
duke@0 1601 // src.lo (msw) is a reg, src.hi is stk/reg
duke@0 1602 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@0 1603 split.set_pair(dst.first(), src.first());
duke@0 1604 } else {
duke@0 1605 // msw is stack move to L5
duke@0 1606 // lsw is stack move to dst.lo (real reg)
duke@0 1607 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@0 1608 split.set_pair(dst.first(), L5->as_VMReg());
duke@0 1609 }
duke@0 1610
duke@0 1611 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@0 1612 // msw -> src.lo/L5, lsw -> dst.lo
duke@0 1613 split_long_move(masm, src, split);
duke@0 1614
duke@0 1615 // So dst now has the low order correct position the
duke@0 1616 // msw half
duke@0 1617 __ sllx(split.first()->as_Register(), 32, L5);
duke@0 1618
duke@0 1619 const Register d = dst.first()->as_Register();
duke@0 1620 __ or3(L5, d, d);
duke@0 1621 }
duke@0 1622 } else {
duke@0 1623 // For LP64 we can probably do better.
duke@0 1624 split_long_move(masm, src, dst);
duke@0 1625 }
duke@0 1626 }
duke@0 1627
duke@0 1628 // A double move
duke@0 1629 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1630
duke@0 1631 // The painful thing here is that like long_move a VMRegPair might be
duke@0 1632 // 1: a single physical register
duke@0 1633 // 2: two physical registers (v8)
duke@0 1634 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@0 1635 // 4: two stack slots
duke@0 1636
duke@0 1637 // Since src is always a java calling convention we know that the src pair
duke@0 1638 // is always either all registers or all stack (and aligned?)
duke@0 1639
duke@0 1640 // in a register [lo] and a stack slot [hi]
duke@0 1641 if (src.first()->is_stack()) {
duke@0 1642 if (dst.first()->is_stack()) {
duke@0 1643 // stack to stack the easiest of the bunch
duke@0 1644 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@0 1645 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1646 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1647 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1648 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1649 } else {
duke@0 1650 // stack to reg
duke@0 1651 if (dst.second()->is_stack()) {
duke@0 1652 // stack -> reg, stack -> stack
duke@0 1653 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1654 if (dst.first()->is_Register()) {
duke@0 1655 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1656 } else {
duke@0 1657 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1658 }
duke@0 1659 // This was missing. (very rare case)
duke@0 1660 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1661 } else {
duke@0 1662 // stack -> reg
duke@0 1663 // Eventually optimize for alignment QQQ
duke@0 1664 if (dst.first()->is_Register()) {
duke@0 1665 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1666 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@0 1667 } else {
duke@0 1668 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1669 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1670 }
duke@0 1671 }
duke@0 1672 }
duke@0 1673 } else if (dst.first()->is_stack()) {
duke@0 1674 // reg to stack
duke@0 1675 if (src.first()->is_Register()) {
duke@0 1676 // Eventually optimize for alignment QQQ
duke@0 1677 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1678 if (src.second()->is_stack()) {
duke@0 1679 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1680 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1681 } else {
duke@0 1682 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1683 }
duke@0 1684 } else {
duke@0 1685 // fpr to stack
duke@0 1686 if (src.second()->is_stack()) {
duke@0 1687 ShouldNotReachHere();
duke@0 1688 } else {
duke@0 1689 // Is the stack aligned?
duke@0 1690 if (reg2offset(dst.first()) & 0x7) {
duke@0 1691 // No do as pairs
duke@0 1692 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1693 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1694 } else {
duke@0 1695 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1696 }
duke@0 1697 }
duke@0 1698 }
duke@0 1699 } else {
duke@0 1700 // reg to reg
duke@0 1701 if (src.first()->is_Register()) {
duke@0 1702 if (dst.first()->is_Register()) {
duke@0 1703 // gpr -> gpr
duke@0 1704 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1705 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@0 1706 } else {
duke@0 1707 // gpr -> fpr
duke@0 1708 // ought to be able to do a single store
duke@0 1709 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@0 1710 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1711 // ought to be able to do a single load
duke@0 1712 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1713 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1714 }
duke@0 1715 } else if (dst.first()->is_Register()) {
duke@0 1716 // fpr -> gpr
duke@0 1717 // ought to be able to do a single store
duke@0 1718 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@0 1719 // ought to be able to do a single load
duke@0 1720 // REMEMBER first() is low address not LSB
duke@0 1721 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@0 1722 if (dst.second()->is_Register()) {
duke@0 1723 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@0 1724 } else {
duke@0 1725 __ ld(FP, -4 + STACK_BIAS, L4);
duke@0 1726 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1727 }
duke@0 1728 } else {
duke@0 1729 // fpr -> fpr
duke@0 1730 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1731 if ( src.first() != dst.first()) {
duke@0 1732 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1733 }
duke@0 1734 }
duke@0 1735 }
duke@0 1736 }
duke@0 1737
duke@0 1738 // Creates an inner frame if one hasn't already been created, and
duke@0 1739 // saves a copy of the thread in L7_thread_cache
duke@0 1740 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@0 1741 if (!*already_created) {
duke@0 1742 __ save_frame(0);
duke@0 1743 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@0 1744 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@0 1745 // copy
duke@0 1746 __ mov(G2_thread, L7_thread_cache);
duke@0 1747 *already_created = true;
duke@0 1748 }
duke@0 1749 }
duke@0 1750
duke@0 1751 // ---------------------------------------------------------------------------
duke@0 1752 // Generate a native wrapper for a given method. The method takes arguments
duke@0 1753 // in the Java compiled code convention, marshals them to the native
duke@0 1754 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@0 1755 // returns to java state (possibly blocking), unhandlizes any result and
duke@0 1756 // returns.
duke@0 1757 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@0 1758 methodHandle method,
twisti@2244 1759 int compile_id,
duke@0 1760 int total_in_args,
duke@0 1761 int comp_args_on_stack, // in VMRegStackSlots
duke@0 1762 BasicType *in_sig_bt,
duke@0 1763 VMRegPair *in_regs,
duke@0 1764 BasicType ret_type) {
duke@0 1765
duke@0 1766 // Native nmethod wrappers never take possesion of the oop arguments.
duke@0 1767 // So the caller will gc the arguments. The only thing we need an
duke@0 1768 // oopMap for is if the call is static
duke@0 1769 //
duke@0 1770 // An OopMap for lock (and class if static), and one for the VM call itself
duke@0 1771 OopMapSet *oop_maps = new OopMapSet();
duke@0 1772 intptr_t start = (intptr_t)__ pc();
duke@0 1773
duke@0 1774 // First thing make an ic check to see if we should even be here
duke@0 1775 {
duke@0 1776 Label L;
duke@0 1777 const Register temp_reg = G3_scratch;
twisti@720 1778 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1779 __ verify_oop(O0);
coleenp@108 1780 __ load_klass(O0, temp_reg);
kvn@2600 1781 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
duke@0 1782
twisti@720 1783 __ jump_to(ic_miss, temp_reg);
duke@0 1784 __ delayed()->nop();
duke@0 1785 __ align(CodeEntryAlignment);
duke@0 1786 __ bind(L);
duke@0 1787 }
duke@0 1788
duke@0 1789 int vep_offset = ((intptr_t)__ pc()) - start;
duke@0 1790
duke@0 1791 #ifdef COMPILER1
duke@0 1792 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@0 1793 // Object.hashCode can pull the hashCode from the header word
duke@0 1794 // instead of doing a full VM transition once it's been computed.
duke@0 1795 // Since hashCode is usually polymorphic at call sites we can't do
duke@0 1796 // this optimization at the call site without a lot of work.
duke@0 1797 Label slowCase;
duke@0 1798 Register receiver = O0;
duke@0 1799 Register result = O0;
duke@0 1800 Register header = G3_scratch;
duke@0 1801 Register hash = G3_scratch; // overwrite header value with hash value
duke@0 1802 Register mask = G1; // to get hash field from header
duke@0 1803
duke@0 1804 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@0 1805 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@0 1806 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@0 1807 // vm: see markOop.hpp.
duke@0 1808 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@0 1809 __ sethi(markOopDesc::hash_mask, mask);
duke@0 1810 __ btst(markOopDesc::unlocked_value, header);
duke@0 1811 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@0 1812 if (UseBiasedLocking) {
duke@0 1813 // Check if biased and fall through to runtime if so
duke@0 1814 __ delayed()->nop();
duke@0 1815 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@0 1816 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@0 1817 }
duke@0 1818 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@0 1819
duke@0 1820 // Check for a valid (non-zero) hash code and get its value.
duke@0 1821 #ifdef _LP64
duke@0 1822 __ srlx(header, markOopDesc::hash_shift, hash);
duke@0 1823 #else
duke@0 1824 __ srl(header, markOopDesc::hash_shift, hash);
duke@0 1825 #endif
duke@0 1826 __ andcc(hash, mask, hash);
duke@0 1827 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@0 1828 __ delayed()->nop();
duke@0 1829
duke@0 1830 // leaf return.
duke@0 1831 __ retl();
duke@0 1832 __ delayed()->mov(hash, result);
duke@0 1833 __ bind(slowCase);
duke@0 1834 }
duke@0 1835 #endif // COMPILER1
duke@0 1836
duke@0 1837
duke@0 1838 // We have received a description of where all the java arg are located
duke@0 1839 // on entry to the wrapper. We need to convert these args to where
duke@0 1840 // the jni function will expect them. To figure out where they go
duke@0 1841 // we convert the java signature to a C signature by inserting
duke@0 1842 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@0 1843
duke@0 1844 int total_c_args = total_in_args + 1;
duke@0 1845 if (method->is_static()) {
duke@0 1846 total_c_args++;
duke@0 1847 }
duke@0 1848
duke@0 1849 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
duke@0 1850 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
duke@0 1851
duke@0 1852 int argc = 0;
duke@0 1853 out_sig_bt[argc++] = T_ADDRESS;
duke@0 1854 if (method->is_static()) {
duke@0 1855 out_sig_bt[argc++] = T_OBJECT;
duke@0 1856 }
duke@0 1857
duke@0 1858 for (int i = 0; i < total_in_args ; i++ ) {
duke@0 1859 out_sig_bt[argc++] = in_sig_bt[i];
duke@0 1860 }
duke@0 1861
duke@0 1862 // Now figure out where the args must be stored and how much stack space
duke@0 1863 // they require (neglecting out_preserve_stack_slots but space for storing
duke@0 1864 // the 1st six register arguments). It's weird see int_stk_helper.
duke@0 1865 //
duke@0 1866 int out_arg_slots;
duke@0 1867 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@0 1868
duke@0 1869 // Compute framesize for the wrapper. We need to handlize all oops in
duke@0 1870 // registers. We must create space for them here that is disjoint from
duke@0 1871 // the windowed save area because we have no control over when we might
duke@0 1872 // flush the window again and overwrite values that gc has since modified.
duke@0 1873 // (The live window race)
duke@0 1874 //
duke@0 1875 // We always just allocate 6 word for storing down these object. This allow
duke@0 1876 // us to simply record the base and use the Ireg number to decide which
duke@0 1877 // slot to use. (Note that the reg number is the inbound number not the
duke@0 1878 // outbound number).
duke@0 1879 // We must shuffle args to match the native convention, and include var-args space.
duke@0 1880
duke@0 1881 // Calculate the total number of stack slots we will need.
duke@0 1882
duke@0 1883 // First count the abi requirement plus all of the outgoing args
duke@0 1884 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@0 1885
duke@0 1886 // Now the space for the inbound oop handle area
duke@0 1887
duke@0 1888 int oop_handle_offset = stack_slots;
duke@0 1889 stack_slots += 6*VMRegImpl::slots_per_word;
duke@0 1890
duke@0 1891 // Now any space we need for handlizing a klass if static method
duke@0 1892
duke@0 1893 int oop_temp_slot_offset = 0;
duke@0 1894 int klass_slot_offset = 0;
duke@0 1895 int klass_offset = -1;
duke@0 1896 int lock_slot_offset = 0;
duke@0 1897 bool is_static = false;
duke@0 1898
duke@0 1899 if (method->is_static()) {
duke@0 1900 klass_slot_offset = stack_slots;
duke@0 1901 stack_slots += VMRegImpl::slots_per_word;
duke@0 1902 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@0 1903 is_static = true;
duke@0 1904 }
duke@0 1905
duke@0 1906 // Plus a lock if needed
duke@0 1907
duke@0 1908 if (method->is_synchronized()) {
duke@0 1909 lock_slot_offset = stack_slots;
duke@0 1910 stack_slots += VMRegImpl::slots_per_word;
duke@0 1911 }
duke@0 1912
duke@0 1913 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@0 1914 stack_slots += 2;
duke@0 1915
duke@0 1916 // Ok The space we have allocated will look like:
duke@0 1917 //
duke@0 1918 //
duke@0 1919 // FP-> | |
duke@0 1920 // |---------------------|
duke@0 1921 // | 2 slots for moves |
duke@0 1922 // |---------------------|
duke@0 1923 // | lock box (if sync) |
duke@0 1924 // |---------------------| <- lock_slot_offset
duke@0 1925 // | klass (if static) |
duke@0 1926 // |---------------------| <- klass_slot_offset
duke@0 1927 // | oopHandle area |
duke@0 1928 // |---------------------| <- oop_handle_offset
duke@0 1929 // | outbound memory |
duke@0 1930 // | based arguments |
duke@0 1931 // | |
duke@0 1932 // |---------------------|
duke@0 1933 // | vararg area |
duke@0 1934 // |---------------------|
duke@0 1935 // | |
duke@0 1936 // SP-> | out_preserved_slots |
duke@0 1937 //
duke@0 1938 //
duke@0 1939
duke@0 1940
duke@0 1941 // Now compute actual number of stack words we need rounding to make
duke@0 1942 // stack properly aligned.
duke@0 1943 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@0 1944
duke@0 1945 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@0 1946
duke@0 1947 // Generate stack overflow check before creating frame
duke@0 1948 __ generate_stack_overflow_check(stack_size);
duke@0 1949
duke@0 1950 // Generate a new frame for the wrapper.
duke@0 1951 __ save(SP, -stack_size, SP);
duke@0 1952
duke@0 1953 int frame_complete = ((intptr_t)__ pc()) - start;
duke@0 1954
duke@0 1955 __ verify_thread();
duke@0 1956
duke@0 1957
duke@0 1958 //
duke@0 1959 // We immediately shuffle the arguments so that any vm call we have to
duke@0 1960 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@0 1961 // captured the oops from our caller and have a valid oopMap for
duke@0 1962 // them.
duke@0 1963
duke@0 1964 // -----------------
duke@0 1965 // The Grand Shuffle
duke@0 1966 //
duke@0 1967 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@0 1968 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@0 1969 // the class mirror instead of a receiver. This pretty much guarantees that
duke@0 1970 // register layout will not match. We ignore these extra arguments during
duke@0 1971 // the shuffle. The shuffle is described by the two calling convention
duke@0 1972 // vectors we have in our possession. We simply walk the java vector to
duke@0 1973 // get the source locations and the c vector to get the destinations.
duke@0 1974 // Because we have a new window and the argument registers are completely
duke@0 1975 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@0 1976 // here.
duke@0 1977
duke@0 1978 // This is a trick. We double the stack slots so we can claim
duke@0 1979 // the oops in the caller's frame. Since we are sure to have
duke@0 1980 // more args than the caller doubling is enough to make
duke@0 1981 // sure we can capture all the incoming oop args from the
duke@0 1982 // caller.
duke@0 1983 //
duke@0 1984 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@0 1985 int c_arg = total_c_args - 1;
duke@0 1986 // Record sp-based slot for receiver on stack for non-static methods
duke@0 1987 int receiver_offset = -1;
duke@0 1988
duke@0 1989 // We move the arguments backward because the floating point registers
duke@0 1990 // destination will always be to a register with a greater or equal register
duke@0 1991 // number or the stack.
duke@0 1992
duke@0 1993 #ifdef ASSERT
duke@0 1994 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@0 1995 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@0 1996 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@0 1997 reg_destroyed[r] = false;
duke@0 1998 }
duke@0 1999 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@0 2000 freg_destroyed[f] = false;
duke@0 2001 }
duke@0 2002
duke@0 2003 #endif /* ASSERT */
duke@0 2004
duke@0 2005 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@0 2006
duke@0 2007 #ifdef ASSERT
duke@0 2008 if (in_regs[i].first()->is_Register()) {
duke@0 2009 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@0 2010 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@0 2011 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@0 2012 }
duke@0 2013 if (out_regs[c_arg].first()->is_Register()) {
duke@0 2014 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@0 2015 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@0 2016 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@0 2017 }
duke@0 2018 #endif /* ASSERT */
duke@0 2019
duke@0 2020 switch (in_sig_bt[i]) {
duke@0 2021 case T_ARRAY:
duke@0 2022 case T_OBJECT:
duke@0 2023 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@0 2024 ((i == 0) && (!is_static)),
duke@0 2025 &receiver_offset);
duke@0 2026 break;
duke@0 2027 case T_VOID:
duke@0 2028 break;
duke@0 2029
duke@0 2030 case T_FLOAT:
duke@0 2031 float_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2032 break;
duke@0 2033
duke@0 2034 case T_DOUBLE:
duke@0 2035 assert( i + 1 < total_in_args &&
duke@0 2036 in_sig_bt[i + 1] == T_VOID &&
duke@0 2037 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@0 2038 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2039 break;
duke@0 2040
duke@0 2041 case T_LONG :
duke@0 2042 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2043 break;
duke@0 2044
duke@0 2045 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@0 2046
duke@0 2047 default:
duke@0 2048 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@0 2049 }
duke@0 2050 }
duke@0 2051
duke@0 2052 // Pre-load a static method's oop into O1. Used both by locking code and
duke@0 2053 // the normal JNI call code.
duke@0 2054 if (method->is_static()) {
duke@0 2055 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@0 2056
duke@0 2057 // Now handlize the static class mirror in O1. It's known not-null.
duke@0 2058 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@0 2059 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@0 2060 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@0 2061 }
duke@0 2062
duke@0 2063
duke@0 2064 const Register L6_handle = L6;
duke@0 2065
duke@0 2066 if (method->is_synchronized()) {
duke@0 2067 __ mov(O1, L6_handle);
duke@0 2068 }
duke@0 2069
duke@0 2070 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@0 2071 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@0 2072 // push a new frame and flush the windows.
duke@0 2073
duke@0 2074 #ifdef _LP64
duke@0 2075 intptr_t thepc = (intptr_t) __ pc();
duke@0 2076 {
duke@0 2077 address here = __ pc();
duke@0 2078 // Call the next instruction
duke@0 2079 __ call(here + 8, relocInfo::none);
duke@0 2080 __ delayed()->nop();
duke@0 2081 }
duke@0 2082 #else
duke@0 2083 intptr_t thepc = __ load_pc_address(O7, 0);
duke@0 2084 #endif /* _LP64 */
duke@0 2085
duke@0 2086 // We use the same pc/oopMap repeatedly when we call out
duke@0 2087 oop_maps->add_gc_map(thepc - start, map);
duke@0 2088
duke@0 2089 // O7 now has the pc loaded that we will use when we finally call to native.
duke@0 2090
duke@0 2091 // Save thread in L7; it crosses a bunch of VM calls below
duke@0 2092 // Don't use save_thread because it smashes G2 and we merely
duke@0 2093 // want to save a copy
duke@0 2094 __ mov(G2_thread, L7_thread_cache);
duke@0 2095
duke@0 2096
duke@0 2097 // If we create an inner frame once is plenty
duke@0 2098 // when we create it we must also save G2_thread
duke@0 2099 bool inner_frame_created = false;
duke@0 2100
duke@0 2101 // dtrace method entry support
duke@0 2102 {
duke@0 2103 SkipIfEqual skip_if(
duke@0 2104 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2105 // create inner frame
duke@0 2106 __ save_frame(0);
duke@0 2107 __ mov(G2_thread, L7_thread_cache);
duke@0 2108 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2109 __ call_VM_leaf(L7_thread_cache,
duke@0 2110 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@0 2111 G2_thread, O1);
duke@0 2112 __ restore();
duke@0 2113 }
duke@0 2114
dcubed@606 2115 // RedefineClasses() tracing support for obsolete method entry
dcubed@606 2116 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
dcubed@606 2117 // create inner frame
dcubed@606 2118 __ save_frame(0);
dcubed@606 2119 __ mov(G2_thread, L7_thread_cache);
dcubed@606 2120 __ set_oop_constant(JNIHandles::make_local(method()), O1);
dcubed@606 2121 __ call_VM_leaf(L7_thread_cache,
dcubed@606 2122 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
dcubed@606 2123 G2_thread, O1);
dcubed@606 2124 __ restore();
dcubed@606 2125 }
dcubed@606 2126
duke@0 2127 // We are in the jni frame unless saved_frame is true in which case
duke@0 2128 // we are in one frame deeper (the "inner" frame). If we are in the
duke@0 2129 // "inner" frames the args are in the Iregs and if the jni frame then
duke@0 2130 // they are in the Oregs.
duke@0 2131 // If we ever need to go to the VM (for locking, jvmti) then
duke@0 2132 // we will always be in the "inner" frame.
duke@0 2133
duke@0 2134 // Lock a synchronized method
duke@0 2135 int lock_offset = -1; // Set if locked
duke@0 2136 if (method->is_synchronized()) {
duke@0 2137 Register Roop = O1;
duke@0 2138 const Register L3_box = L3;
duke@0 2139
duke@0 2140 create_inner_frame(masm, &inner_frame_created);
duke@0 2141
duke@0 2142 __ ld_ptr(I1, 0, O1);
duke@0 2143 Label done;
duke@0 2144
duke@0 2145 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@0 2146 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2147 #ifdef ASSERT
duke@0 2148 if (UseBiasedLocking) {
duke@0 2149 // making the box point to itself will make it clear it went unused
duke@0 2150 // but also be obviously invalid
duke@0 2151 __ st_ptr(L3_box, L3_box, 0);
duke@0 2152 }
duke@0 2153 #endif // ASSERT
duke@0 2154 //
duke@0 2155 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@0 2156 //
duke@0 2157 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@0 2158 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2159 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2160
duke@0 2161
duke@0 2162 // None of the above fast optimizations worked so we have to get into the
duke@0 2163 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2164 // disallows any pending_exception.
duke@0 2165 __ mov(Roop, O0); // Need oop in O0
duke@0 2166 __ mov(L3_box, O1);
duke@0 2167
duke@0 2168 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@0 2169
duke@0 2170 __ set_last_Java_frame(FP, I7);
duke@0 2171
duke@0 2172 // do the call
duke@0 2173 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@0 2174 __ delayed()->mov(L7_thread_cache, O2);
duke@0 2175
duke@0 2176 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2177 __ reset_last_Java_frame();
duke@0 2178
duke@0 2179 #ifdef ASSERT
duke@0 2180 { Label L;
duke@0 2181 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2182 __ br_null_short(O0, Assembler::pt, L);
duke@0 2183 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@0 2184 __ bind(L);
duke@0 2185 }
duke@0 2186 #endif
duke@0 2187 __ bind(done);
duke@0 2188 }
duke@0 2189
duke@0 2190
duke@0 2191 // Finally just about ready to make the JNI call
duke@0 2192
duke@0 2193 __ flush_windows();
duke@0 2194 if (inner_frame_created) {
duke@0 2195 __ restore();
duke@0 2196 } else {
duke@0 2197 // Store only what we need from this frame
duke@0 2198 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@0 2199 // either as the flush traps and the current window goes too.
duke@0 2200 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2201 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2202 }
duke@0 2203
duke@0 2204 // get JNIEnv* which is first argument to native
duke@0 2205
duke@0 2206 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
duke@0 2207
duke@0 2208 // Use that pc we placed in O7 a while back as the current frame anchor
duke@0 2209
duke@0 2210 __ set_last_Java_frame(SP, O7);
duke@0 2211
duke@0 2212 // Transition from _thread_in_Java to _thread_in_native.
duke@0 2213 __ set(_thread_in_native, G3_scratch);
twisti@720 2214 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2215
duke@0 2216 // We flushed the windows ages ago now mark them as flushed
duke@0 2217
duke@0 2218 // mark windows as flushed
duke@0 2219 __ set(JavaFrameAnchor::flushed, G3_scratch);
duke@0 2220
twisti@720 2221 Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
duke@0 2222
duke@0 2223 #ifdef _LP64
twisti@720 2224 AddressLiteral dest(method->native_function());
duke@0 2225 __ relocate(relocInfo::runtime_call_type);
twisti@720 2226 __ jumpl_to(dest, O7, O7);
duke@0 2227 #else
duke@0 2228 __ call(method->native_function(), relocInfo::runtime_call_type);
duke@0 2229 #endif
duke@0 2230 __ delayed()->st(G3_scratch, flags);
duke@0 2231
duke@0 2232 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2233
duke@0 2234 // Unpack native results. For int-types, we do any needed sign-extension
duke@0 2235 // and move things into I0. The return value there will survive any VM
duke@0 2236 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@0 2237 // specially in the slow-path code.
duke@0 2238 switch (ret_type) {
duke@0 2239 case T_VOID: break; // Nothing to do!
duke@0 2240 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@0 2241 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@0 2242 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@0 2243 case T_LONG:
duke@0 2244 #ifndef _LP64
duke@0 2245 __ mov(O1, I1);
duke@0 2246 #endif
duke@0 2247 // Fall thru
duke@0 2248 case T_OBJECT: // Really a handle
duke@0 2249 case T_ARRAY:
duke@0 2250 case T_INT:
duke@0 2251 __ mov(O0, I0);
duke@0 2252 break;
duke@0 2253 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@0 2254 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@0 2255 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@0 2256 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@0 2257 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@0 2258 default:
duke@0 2259 ShouldNotReachHere();
duke@0 2260 }
duke@0 2261
duke@0 2262 // must we block?
duke@0 2263
duke@0 2264 // Block, if necessary, before resuming in _thread_in_Java state.
duke@0 2265 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@0 2266 { Label no_block;
twisti@720 2267 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
duke@0 2268
duke@0 2269 // Switch thread to "native transition" state before reading the synchronization state.
duke@0 2270 // This additional state is necessary because reading and testing the synchronization
duke@0 2271 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@0 2272 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@0 2273 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@0 2274 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@0 2275 // didn't see any synchronization is progress, and escapes.
duke@0 2276 __ set(_thread_in_native_trans, G3_scratch);
twisti@720 2277 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2278 if(os::is_MP()) {
duke@0 2279 if (UseMembar) {
duke@0 2280 // Force this write out before the read below
duke@0 2281 __ membar(Assembler::StoreLoad);
duke@0 2282 } else {
duke@0 2283 // Write serialization page so VM thread can do a pseudo remote membar.
duke@0 2284 // We use the current thread pointer to calculate a thread specific
duke@0 2285 // offset to write to within the page. This minimizes bus traffic
duke@0 2286 // due to cache line collision.
duke@0 2287 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@0 2288 }
duke@0 2289 }
duke@0 2290 __ load_contents(sync_state, G3_scratch);
duke@0 2291 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@0 2292
duke@0 2293 Label L;
twisti@720 2294 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
duke@0 2295 __ br(Assembler::notEqual, false, Assembler::pn, L);
twisti@720 2296 __ delayed()->ld(suspend_state, G3_scratch);
kvn@2600 2297 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
duke@0 2298 __ bind(L);
duke@0 2299
duke@0 2300 // Block. Save any potential method result value before the operation and
duke@0 2301 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@0 2302 // lets us share the oopMap we used when we went native rather the create
duke@0 2303 // a distinct one for this pc
duke@0 2304 //
duke@0 2305 save_native_result(masm, ret_type, stack_slots);
duke@0 2306 __ call_VM_leaf(L7_thread_cache,
duke@0 2307 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
duke@0 2308 G2_thread);
duke@0 2309
duke@0 2310 // Restore any method result value
duke@0 2311 restore_native_result(masm, ret_type, stack_slots);
duke@0 2312 __ bind(no_block);
duke@0 2313 }
duke@0 2314
duke@0 2315 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@0 2316 // happened so we can now change state to _thread_in_Java.
duke@0 2317
duke@0 2318
duke@0 2319 __ set(_thread_in_Java, G3_scratch);
twisti@720 2320 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2321
duke@0 2322
duke@0 2323 Label no_reguard;
twisti@720 2324 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
kvn@2600 2325 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
duke@0 2326
duke@0 2327 save_native_result(masm, ret_type, stack_slots);
duke@0 2328 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@0 2329 __ delayed()->nop();
duke@0 2330
duke@0 2331 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2332 restore_native_result(masm, ret_type, stack_slots);
duke@0 2333
duke@0 2334 __ bind(no_reguard);
duke@0 2335
duke@0 2336 // Handle possible exception (will unlock if necessary)
duke@0 2337
duke@0 2338 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@0 2339
duke@0 2340 // Unlock
duke@0 2341 if (method->is_synchronized()) {
duke@0 2342 Label done;
duke@0 2343 Register I2_ex_oop = I2;
duke@0 2344 const Register L3_box = L3;
duke@0 2345 // Get locked oop from the handle we passed to jni
duke@0 2346 __ ld_ptr(L6_handle, 0, L4);
duke@0 2347 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2348 // Must save pending exception around the slow-path VM call. Since it's a
duke@0 2349 // leaf call, the pending exception (if any) can be kept in a register.
duke@0 2350 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@0 2351 // Now unlock
duke@0 2352 // (Roop, Rmark, Rbox, Rscratch)
duke@0 2353 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@0 2354 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2355 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2356
duke@0 2357 // save and restore any potential method result value around the unlocking
duke@0 2358 // operation. Will save in I0 (or stack for FP returns).
duke@0 2359 save_native_result(masm, ret_type, stack_slots);
duke@0 2360
duke@0 2361 // Must clear pending-exception before re-entering the VM. Since this is
duke@0 2362 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@0 2363 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2364
duke@0 2365 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2366 // disallows any pending_exception.
duke@0 2367 __ mov(L3_box, O1);
duke@0 2368
duke@0 2369 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@0 2370 __ delayed()->mov(L4, O0); // Need oop in O0
duke@0 2371
duke@0 2372 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2373
duke@0 2374 #ifdef ASSERT
duke@0 2375 { Label L;
duke@0 2376 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2377 __ br_null_short(O0, Assembler::pt, L);
duke@0 2378 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@0 2379 __ bind(L);
duke@0 2380 }
duke@0 2381 #endif
duke@0 2382 restore_native_result(masm, ret_type, stack_slots);
duke@0 2383 // check_forward_pending_exception jump to forward_exception if any pending
duke@0 2384 // exception is set. The forward_exception routine expects to see the
duke@0 2385 // exception in pending_exception and not in a register. Kind of clumsy,
duke@0 2386 // since all folks who branch to forward_exception must have tested
duke@0 2387 // pending_exception first and hence have it in a register already.
duke@0 2388 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2389 __ bind(done);
duke@0 2390 }
duke@0 2391
duke@0 2392 // Tell dtrace about this method exit
duke@0 2393 {
duke@0 2394 SkipIfEqual skip_if(
duke@0 2395 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2396 save_native_result(masm, ret_type, stack_slots);
duke@0 2397 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2398 __ call_VM_leaf(L7_thread_cache,
duke@0 2399 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@0 2400 G2_thread, O1);
duke@0 2401 restore_native_result(masm, ret_type, stack_slots);
duke@0 2402 }
duke@0 2403
duke@0 2404 // Clear "last Java frame" SP and PC.
duke@0 2405 __ verify_thread(); // G2_thread must be correct
duke@0 2406 __ reset_last_Java_frame();
duke@0 2407
duke@0 2408 // Unpack oop result
duke@0 2409 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@0 2410 Label L;
duke@0 2411 __ addcc(G0, I0, G0);
duke@0 2412 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@0 2413 __ delayed()->ld_ptr(I0, 0, I0);
duke@0 2414 __ mov(G0, I0);
duke@0 2415 __ bind(L);
duke@0 2416 __ verify_oop(I0);
duke@0 2417 }
duke@0 2418
duke@0 2419 // reset handle block
duke@0 2420 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
duke@0 2421 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
duke@0 2422
duke@0 2423 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
duke@0 2424 check_forward_pending_exception(masm, G3_scratch);
duke@0 2425
duke@0 2426
duke@0 2427 // Return
duke@0 2428
duke@0 2429 #ifndef _LP64
duke@0 2430 if (ret_type == T_LONG) {
duke@0 2431
duke@0 2432 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@0 2433 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 2434 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 2435 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 2436 }
duke@0 2437 #endif
duke@0 2438
duke@0 2439 __ ret();
duke@0 2440 __ delayed()->restore();
duke@0 2441
duke@0 2442 __ flush();
duke@0 2443
duke@0 2444 nmethod *nm = nmethod::new_native_nmethod(method,
twisti@2244 2445 compile_id,
duke@0 2446 masm->code(),
duke@0 2447 vep_offset,
duke@0 2448 frame_complete,
duke@0 2449 stack_slots / VMRegImpl::slots_per_word,
duke@0 2450 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@0 2451 in_ByteSize(lock_offset),
duke@0 2452 oop_maps);
duke@0 2453 return nm;
duke@0 2454
duke@0 2455 }
duke@0 2456
kamg@124 2457 #ifdef HAVE_DTRACE_H
kamg@124 2458 // ---------------------------------------------------------------------------
kamg@124 2459 // Generate a dtrace nmethod for a given signature. The method takes arguments
kamg@124 2460 // in the Java compiled code convention, marshals them to the native
kamg@124 2461 // abi and then leaves nops at the position you would expect to call a native
kamg@124 2462 // function. When the probe is enabled the nops are replaced with a trap
kamg@124 2463 // instruction that dtrace inserts and the trace will cause a notification
kamg@124 2464 // to dtrace.
kamg@124 2465 //
kamg@124 2466 // The probes are only able to take primitive types and java/lang/String as
kamg@124 2467 // arguments. No other java types are allowed. Strings are converted to utf8
kamg@124 2468 // strings so that from dtrace point of view java strings are converted to C
kamg@124 2469 // strings. There is an arbitrary fixed limit on the total space that a method
kamg@124 2470 // can use for converting the strings. (256 chars per string in the signature).
kamg@124 2471 // So any java string larger then this is truncated.
kamg@124 2472
kamg@124 2473 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
kamg@124 2474 static bool offsets_initialized = false;
kamg@124 2475
kamg@124 2476 static VMRegPair reg64_to_VMRegPair(Register r) {
kamg@124 2477 VMRegPair ret;
kamg@124 2478 if (wordSize == 8) {
kamg@124 2479 ret.set2(r->as_VMReg());
kamg@124 2480 } else {
kamg@124 2481 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
kamg@124 2482 }
kamg@124 2483 return ret;
kamg@124 2484 }
kamg@124 2485
kamg@124 2486
kamg@124 2487 nmethod *SharedRuntime::generate_dtrace_nmethod(
kamg@124 2488 MacroAssembler *masm, methodHandle method) {
kamg@124 2489
kamg@124 2490
kamg@124 2491 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
kamg@124 2492 // be single threaded in this method.
kamg@124 2493 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
kamg@124 2494
kamg@124 2495 // Fill in the signature array, for the calling-convention call.
kamg@124 2496 int total_args_passed = method->size_of_parameters();
kamg@124 2497
kamg@124 2498 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
kamg@124 2499 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
kamg@124 2500
kamg@124 2501 // The signature we are going to use for the trap that dtrace will see
kamg@124 2502 // java/lang/String is converted. We drop "this" and any other object
kamg@124 2503 // is converted to NULL. (A one-slot java/lang/Long object reference
kamg@124 2504 // is converted to a two-slot long, which is why we double the allocation).
kamg@124 2505 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
kamg@124 2506 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
kamg@124 2507
kamg@124 2508 int i=0;
kamg@124 2509 int total_strings = 0;
kamg@124 2510 int first_arg_to_pass = 0;
kamg@124 2511 int total_c_args = 0;
kamg@124 2512
kamg@124 2513 // Skip the receiver as dtrace doesn't want to see it
kamg@124 2514 if( !method->is_static() ) {
kamg@124 2515 in_sig_bt[i++] = T_OBJECT;
kamg@124 2516 first_arg_to_pass = 1;
kamg@124 2517 }
kamg@124 2518
kamg@124 2519 SignatureStream ss(method->signature());
kamg@124 2520 for ( ; !ss.at_return_type(); ss.next()) {
kamg@124 2521 BasicType bt = ss.type();
kamg@124 2522 in_sig_bt[i++] = bt; // Collect remaining bits of signature
kamg@124 2523 out_sig_bt[total_c_args++] = bt;
kamg@124 2524 if( bt == T_OBJECT) {
coleenp@2059 2525 Symbol* s = ss.as_symbol_or_null();
kamg@124 2526 if (s == vmSymbols::java_lang_String()) {
kamg@124 2527 total_strings++;
kamg@124 2528 out_sig_bt[total_c_args-1] = T_ADDRESS;
kamg@124 2529 } else if (s == vmSymbols::java_lang_Boolean() ||
kamg@124 2530 s == vmSymbols::java_lang_Byte()) {
kamg@124 2531 out_sig_bt[total_c_args-1] = T_BYTE;
kamg@124 2532 } else if (s == vmSymbols::java_lang_Character() ||
kamg@124 2533 s == vmSymbols::java_lang_Short()) {
kamg@124 2534 out_sig_bt[total_c_args-1] = T_SHORT;
kamg@124 2535 } else if (s == vmSymbols::java_lang_Integer() ||
kamg@124 2536 s == vmSymbols::java_lang_Float()) {
kamg@124 2537 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2538 } else if (s == vmSymbols::java_lang_Long() ||
kamg@124 2539 s == vmSymbols::java_lang_Double()) {
kamg@124 2540 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2541 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2542 }
kamg@124 2543 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
kamg@124 2544 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
kamg@124 2545 // We convert double to long
kamg@124 2546 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 2547 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 2548 } else if ( bt == T_FLOAT) {
kamg@124 2549 // We convert float to int
kamg@124 2550 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 2551 }
kamg@124 2552 }
kamg@124 2553
kamg@124 2554 assert(i==total_args_passed, "validly parsed signature");
kamg@124 2555
kamg@124 2556 // Now get the compiled-Java layout as input arguments
kamg@124 2557 int comp_args_on_stack;
kamg@124 2558 comp_args_on_stack = SharedRuntime::java_calling_convention(
kamg@124 2559 in_sig_bt, in_regs, total_args_passed, false);
kamg@124 2560
kamg@124 2561 // We have received a description of where all the java arg are located
kamg@124 2562 // on entry to the wrapper. We need to convert these args to where
kamg@124 2563 // the a native (non-jni) function would expect them. To figure out
kamg@124 2564 // where they go we convert the java signature to a C signature and remove
kamg@124 2565 // T_VOID for any long/double we might have received.
kamg@124 2566
kamg@124 2567
kamg@124 2568 // Now figure out where the args must be stored and how much stack space
kamg@124 2569 // they require (neglecting out_preserve_stack_slots but space for storing
kamg@124 2570 // the 1st six register arguments). It's weird see int_stk_helper.
kamg@124 2571 //
kamg@124 2572 int out_arg_slots;
kamg@124 2573 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
kamg@124 2574
kamg@124 2575 // Calculate the total number of stack slots we will need.
kamg@124 2576
kamg@124 2577 // First count the abi requirement plus all of the outgoing args
kamg@124 2578 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
kamg@124 2579
kamg@124 2580 // Plus a temp for possible converion of float/double/long register args
kamg@124 2581
kamg@124 2582 int conversion_temp = stack_slots;
kamg@124 2583 stack_slots += 2;
kamg@124 2584
kamg@124 2585
kamg@124 2586 // Now space for the string(s) we must convert
kamg@124 2587
kamg@124 2588 int string_locs = stack_slots;
kamg@124 2589 stack_slots += total_strings *
kamg@124 2590 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
kamg@124 2591
kamg@124 2592 // Ok The space we have allocated will look like:
kamg@124 2593 //
kamg@124 2594 //
kamg@124 2595 // FP-> | |
kamg@124 2596 // |---------------------|
kamg@124 2597 // | string[n] |
kamg@124 2598 // |---------------------| <- string_locs[n]
kamg@124 2599 // | string[n-1] |
kamg@124 2600 // |---------------------| <- string_locs[n-1]
kamg@124 2601 // | ... |
kamg@124 2602 // | ... |
kamg@124 2603 // |---------------------| <- string_locs[1]
kamg@124 2604 // | string[0] |
kamg@124 2605 // |---------------------| <- string_locs[0]
kamg@124 2606 // | temp |
kamg@124 2607 // |---------------------| <- conversion_temp
kamg@124 2608 // | outbound memory |
kamg@124 2609 // | based arguments |
kamg@124 2610 // | |
kamg@124 2611 // |---------------------|
kamg@124 2612 // | |
kamg@124 2613 // SP-> | out_preserved_slots |
kamg@124 2614 //
kamg@124 2615 //
kamg@124 2616
kamg@124 2617 // Now compute actual number of stack words we need rounding to make
kamg@124 2618 // stack properly aligned.
kamg@124 2619 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
kamg@124 2620
kamg@124 2621 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
kamg@124 2622
kamg@124 2623 intptr_t start = (intptr_t)__ pc();
kamg@124 2624
kamg@124 2625 // First thing make an ic check to see if we should even be here
kamg@124 2626
kamg@124 2627 {
kamg@124 2628 Label L;
kamg@124 2629 const Register temp_reg = G3_scratch;
twisti@720 2630 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
kamg@124 2631 __ verify_oop(O0);
kamg@124 2632 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
kvn@2600 2633 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
kamg@124 2634
twisti@720 2635 __ jump_to(ic_miss, temp_reg);
kamg@124 2636 __ delayed()->nop();
kamg@124 2637 __ align(CodeEntryAlignment);
kamg@124 2638 __ bind(L);
kamg@124 2639 }
kamg@124 2640
kamg@124 2641 int vep_offset = ((intptr_t)__ pc()) - start;
kamg@124 2642
kamg@124 2643
kamg@124 2644 // The instruction at the verified entry point must be 5 bytes or longer
kamg@124 2645 // because it can be patched on the fly by make_non_entrant. The stack bang
kamg@124 2646 // instruction fits that requirement.
kamg@124 2647
kamg@124 2648 // Generate stack overflow check before creating frame
kamg@124 2649 __ generate_stack_overflow_check(stack_size);
kamg@124 2650
kamg@124 2651 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
kamg@124 2652 "valid size for make_non_entrant");
kamg@124 2653
kamg@124 2654 // Generate a new frame for the wrapper.
kamg@124 2655 __ save(SP, -stack_size, SP);
kamg@124 2656
kamg@124 2657 // Frame is now completed as far a size and linkage.
kamg@124 2658
kamg@124 2659 int frame_complete = ((intptr_t)__ pc()) - start;
kamg@124 2660
kamg@124 2661 #ifdef ASSERT
kamg@124 2662 bool reg_destroyed[RegisterImpl::number_of_registers];
kamg@124 2663 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
kamg@124 2664 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
kamg@124 2665 reg_destroyed[r] = false;
kamg@124 2666 }
kamg@124 2667 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
kamg@124 2668 freg_destroyed[f] = false;
kamg@124 2669 }
kamg@124 2670
kamg@124 2671 #endif /* ASSERT */
kamg@124 2672
kamg@124 2673 VMRegPair zero;
kamg@182 2674 const Register g0 = G0; // without this we get a compiler warning (why??)
kamg@182 2675 zero.set2(g0->as_VMReg());
kamg@124 2676
kamg@124 2677 int c_arg, j_arg;
kamg@124 2678
kamg@124 2679 Register conversion_off = noreg;
kamg@124 2680
kamg@124 2681 for (j_arg = first_arg_to_pass, c_arg = 0 ;
kamg@124 2682 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
kamg@124 2683
kamg@124 2684 VMRegPair src = in_regs[j_arg];
kamg@124 2685 VMRegPair dst = out_regs[c_arg];
kamg@124 2686
kamg@124 2687 #ifdef ASSERT
kamg@124 2688 if (src.first()->is_Register()) {
kamg@124 2689 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
kamg@124 2690 } else if (src.first()->is_FloatRegister()) {
kamg@124 2691 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
kamg@124 2692 FloatRegisterImpl::S)], "ack!");
kamg@124 2693 }
kamg@124 2694 if (dst.first()->is_Register()) {
kamg@124 2695 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
kamg@124 2696 } else if (dst.first()->is_FloatRegister()) {
kamg@124 2697 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
kamg@124 2698 FloatRegisterImpl::S)] = true;
kamg@124 2699 }
kamg@124 2700 #endif /* ASSERT */
kamg@124 2701
kamg@124 2702 switch (in_sig_bt[j_arg]) {
kamg@124 2703 case T_ARRAY:
kamg@124 2704 case T_OBJECT:
kamg@124 2705 {
kamg@124 2706 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
kamg@124 2707 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
kamg@124 2708 // need to unbox a one-slot value
kamg@124 2709 Register in_reg = L0;
kamg@124 2710 Register tmp = L2;
kamg@124 2711 if ( src.first()->is_reg() ) {
kamg@124 2712 in_reg = src.first()->as_Register();
kamg@124 2713 } else {
kamg@124 2714 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
kamg@124 2715 "must be");
kamg@124 2716 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
kamg@124 2717 }
kamg@124 2718 // If the final destination is an acceptable register
kamg@124 2719 if ( dst.first()->is_reg() ) {
kamg@124 2720 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
kamg@124 2721 tmp = dst.first()->as_Register();
kamg@124 2722 }
kamg@124 2723 }
kamg@124 2724
kamg@124 2725 Label skipUnbox;
kamg@124 2726 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
kamg@124 2727 __ mov(G0, tmp->successor());
kamg@124 2728 }
kamg@124 2729 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
kamg@124 2730 __ delayed()->mov(G0, tmp);
kamg@124 2731
kvn@153 2732 BasicType bt = out_sig_bt[c_arg];
kvn@153 2733 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
kvn@153 2734 switch (bt) {
kamg@124 2735 case T_BYTE:
kamg@124 2736 __ ldub(in_reg, box_offset, tmp); break;
kamg@124 2737 case T_SHORT:
kamg@124 2738 __ lduh(in_reg, box_offset, tmp); break;
kamg@124 2739 case T_INT:
kamg@124 2740 __ ld(in_reg, box_offset, tmp); break;
kamg@124 2741 case T_LONG:
kamg@124 2742 __ ld_long(in_reg, box_offset, tmp); break;
kamg@124 2743 default: ShouldNotReachHere();
kamg@124 2744 }
kamg@124 2745
kamg@124 2746 __ bind(skipUnbox);
kamg@124 2747 // If tmp wasn't final destination copy to final destination
kamg@124 2748 if (tmp == L2) {
kamg@124 2749 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
kamg@124 2750 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 2751 long_move(masm, tmp_as_VM, dst);
kamg@124 2752 } else {
kamg@124 2753 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
kamg@124 2754 }
kamg@124 2755 }
kamg@124 2756 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 2757 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
kamg@124 2758 ++c_arg; // move over the T_VOID to keep the loop indices in sync
kamg@124 2759 }
kamg@124 2760 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 2761 Register s =
kamg@124 2762 src.first()->is_reg() ? src.first()->as_Register() : L2;
kamg@124 2763 Register d =
kamg@124 2764 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 2765
kamg@124 2766 // We store the oop now so that the conversion pass can reach
kamg@124 2767 // while in the inner frame. This will be the only store if
kamg@124 2768 // the oop is NULL.
kamg@124 2769 if (s != L2) {
kamg@124 2770 // src is register
kamg@124 2771 if (d != L2) {
kamg@124 2772 // dst is register
kamg@124 2773 __ mov(s, d);
kamg@124 2774 } else {
kamg@124 2775 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2776 STACK_BIAS), "must be");
kamg@124 2777 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2778 }
kamg@124 2779 } else {
kamg@124 2780 // src not a register
kamg@124 2781 assert(Assembler::is_simm13(reg2offset(src.first()) +
kamg@124 2782 STACK_BIAS), "must be");
kamg@124 2783 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
kamg@124 2784 if (d == L2) {
kamg@124 2785 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2786 STACK_BIAS), "must be");
kamg@124 2787 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2788 }
kamg@124 2789 }
kamg@124 2790 } else if (out_sig_bt[c_arg] != T_VOID) {
kamg@124 2791 // Convert the arg to NULL
kamg@124 2792 if (dst.first()->is_reg()) {
kamg@124 2793 __ mov(G0, dst.first()->as_Register());
kamg@124 2794 } else {
kamg@124 2795 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 2796 STACK_BIAS), "must be");
kamg@124 2797 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2798 }
kamg@124 2799 }
kamg@124 2800 }
kamg@124 2801 break;
kamg@124 2802 case T_VOID:
kamg@124 2803 break;
kamg@124 2804
kamg@124 2805 case T_FLOAT:
kamg@124 2806 if (src.first()->is_stack()) {
kamg@124 2807 // Stack to stack/reg is simple
kamg@124 2808 move32_64(masm, src, dst);
kamg@124 2809 } else {
kamg@124 2810 if (dst.first()->is_reg()) {
kamg@124 2811 // freg -> reg
kamg@124 2812 int off =
kamg@124 2813 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2814 Register d = dst.first()->as_Register();
kamg@124 2815 if (Assembler::is_simm13(off)) {
kamg@124 2816 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2817 SP, off);
kamg@124 2818 __ ld(SP, off, d);
kamg@124 2819 } else {
kamg@124 2820 if (conversion_off == noreg) {
kamg@124 2821 __ set(off, L6);
kamg@124 2822 conversion_off = L6;
kamg@124 2823 }
kamg@124 2824 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2825 SP, conversion_off);
kamg@124 2826 __ ld(SP, conversion_off , d);
kamg@124 2827 }
kamg@124 2828 } else {
kamg@124 2829 // freg -> mem
kamg@124 2830 int off = STACK_BIAS + reg2offset(dst.first());
kamg@124 2831 if (Assembler::is_simm13(off)) {
kamg@124 2832 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2833 SP, off);
kamg@124 2834 } else {
kamg@124 2835 if (conversion_off == noreg) {
kamg@124 2836 __ set(off, L6);
kamg@124 2837 conversion_off = L6;
kamg@124 2838 }
kamg@124 2839 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 2840 SP, conversion_off);
kamg@124 2841 }
kamg@124 2842 }
kamg@124 2843 }
kamg@124 2844 break;
kamg@124 2845
kamg@124 2846 case T_DOUBLE:
kamg@124 2847 assert( j_arg + 1 < total_args_passed &&
kamg@124 2848 in_sig_bt[j_arg + 1] == T_VOID &&
kamg@124 2849 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
kamg@124 2850 if (src.first()->is_stack()) {
kamg@124 2851 // Stack to stack/reg is simple
kamg@124 2852 long_move(masm, src, dst);
kamg@124 2853 } else {
kamg@124 2854 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 2855
kamg@124 2856 // Destination could be an odd reg on 32bit in which case
kamg@124 2857 // we can't load direct to the destination.
kamg@124 2858
kamg@124 2859 if (!d->is_even() && wordSize == 4) {
kamg@124 2860 d = L2;
kamg@124 2861 }
kamg@124 2862 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2863 if (Assembler::is_simm13(off)) {
kamg@124 2864 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 2865 SP, off);
kamg@124 2866 __ ld_long(SP, off, d);
kamg@124 2867 } else {
kamg@124 2868 if (conversion_off == noreg) {
kamg@124 2869 __ set(off, L6);
kamg@124 2870 conversion_off = L6;
kamg@124 2871 }
kamg@124 2872 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 2873 SP, conversion_off);
kamg@124 2874 __ ld_long(SP, conversion_off, d);
kamg@124 2875 }
kamg@124 2876 if (d == L2) {
kamg@124 2877 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 2878 }
kamg@124 2879 }
kamg@124 2880 break;
kamg@124 2881
kamg@124 2882 case T_LONG :
kamg@124 2883 // 32bit can't do a split move of something like g1 -> O0, O1
kamg@124 2884 // so use a memory temp
kamg@124 2885 if (src.is_single_phys_reg() && wordSize == 4) {
kamg@124 2886 Register tmp = L2;
kamg@124 2887 if (dst.first()->is_reg() &&
kamg@124 2888 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
kamg@124 2889 tmp = dst.first()->as_Register();
kamg@124 2890 }
kamg@124 2891
kamg@124 2892 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 2893 if (Assembler::is_simm13(off)) {
kamg@124 2894 __ stx(src.first()->as_Register(), SP, off);
kamg@124 2895 __ ld_long(SP, off, tmp);
kamg@124 2896 } else {
kamg@124 2897 if (conversion_off == noreg) {
kamg@124 2898 __ set(off, L6);
kamg@124 2899 conversion_off = L6;
kamg@124 2900 }
kamg@124 2901 __ stx(src.first()->as_Register(), SP, conversion_off);
kamg@124 2902 __ ld_long(SP, conversion_off, tmp);
kamg@124 2903 }
kamg@124 2904
kamg@124 2905 if (tmp == L2) {
kamg@124 2906 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 2907 }
kamg@124 2908 } else {
kamg@124 2909 long_move(masm, src, dst);
kamg@124 2910 }
kamg@124 2911 break;
kamg@124 2912
kamg@124 2913 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
kamg@124 2914
kamg@124 2915 default:
kamg@124 2916 move32_64(masm, src, dst);
kamg@124 2917 }
kamg@124 2918 }
kamg@124 2919
kamg@124 2920
kamg@124 2921 // If we have any strings we must store any register based arg to the stack
kamg@124 2922 // This includes any still live xmm registers too.
kamg@124 2923
kamg@124 2924 if (total_strings > 0 ) {
kamg@124 2925
kamg@124 2926 // protect all the arg registers
kamg@124 2927 __ save_frame(0);
kamg@124 2928 __ mov(G2_thread, L7_thread_cache);
kamg@124 2929 const Register L2_string_off = L2;
kamg@124 2930
kamg@124 2931 // Get first string offset
kamg@124 2932 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
kamg@124 2933
kamg@124 2934 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
kamg@124 2935 if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 2936
kamg@124 2937 VMRegPair dst = out_regs[c_arg];
kamg@124 2938 const Register d = dst.first()->is_reg() ?
kamg@124 2939 dst.first()->as_Register()->after_save() : noreg;
kamg@124 2940
kamg@124 2941 // It's a string the oop and it was already copied to the out arg
kamg@124 2942 // position
kamg@124 2943 if (d != noreg) {
kamg@124 2944 __ mov(d, O0);
kamg@124 2945 } else {
kamg@124 2946 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 2947 "must be");
kamg@124 2948 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
kamg@124 2949 }
kamg@124 2950 Label skip;
kamg@124 2951
kamg@124 2952 __ br_null(O0, false, Assembler::pn, skip);
kamg@124 2953 __ delayed()->add(FP, L2_string_off, O1);
kamg@124 2954
kamg@124 2955 if (d != noreg) {
kamg@124 2956 __ mov(O1, d);
kamg@124 2957 } else {
kamg@124 2958 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@124 2959 "must be");
kamg@124 2960 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 2961 }
kamg@124 2962
kamg@124 2963 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
kamg@124 2964 relocInfo::runtime_call_type);
kamg@124 2965 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
kamg@124 2966
kamg@124 2967 __ bind(skip);
kamg@124 2968
kamg@124 2969 }
kamg@124 2970
kamg@124 2971 }
kamg@124 2972 __ mov(L7_thread_cache, G2_thread);
kamg@124 2973 __ restore();
kamg@124 2974
kamg@124 2975 }
kamg@124 2976
kamg@124 2977
kamg@124 2978 // Ok now we are done. Need to place the nop that dtrace wants in order to
kamg@124 2979 // patch in the trap
kamg@124 2980
kamg@124 2981 int patch_offset = ((intptr_t)__ pc()) - start;
kamg@124 2982
kamg@124 2983 __ nop();
kamg@124 2984
kamg@124 2985
kamg@124 2986 // Return
kamg@124 2987
kamg@124 2988 __ ret();
kamg@124 2989 __ delayed()->restore();
kamg@124 2990
kamg@124 2991 __ flush();
kamg@124 2992
kamg@124 2993 nmethod *nm = nmethod::new_dtrace_nmethod(
kamg@124 2994 method, masm->code(), vep_offset, patch_offset, frame_complete,
kamg@124 2995 stack_slots / VMRegImpl::slots_per_word);
kamg@124 2996 return nm;
kamg@124 2997
kamg@124 2998 }
kamg@124 2999
kamg@124 3000 #endif // HAVE_DTRACE_H
kamg@124 3001
duke@0 3002 // this function returns the adjust size (in number of words) to a c2i adapter
duke@0 3003 // activation for use during deoptimization
duke@0 3004 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
duke@0 3005 assert(callee_locals >= callee_parameters,
duke@0 3006 "test and remove; got more parms than locals");
duke@0 3007 if (callee_locals < callee_parameters)
duke@0 3008 return 0; // No adjustment for negative locals
twisti@1401 3009 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
duke@0 3010 return round_to(diff, WordsPerLong);
duke@0 3011 }
duke@0 3012
duke@0 3013 // "Top of Stack" slots that may be unused by the calling convention but must
duke@0 3014 // otherwise be preserved.
duke@0 3015 // On Intel these are not necessary and the value can be zero.
duke@0 3016 // On Sparc this describes the words reserved for storing a register window
duke@0 3017 // when an interrupt occurs.
duke@0 3018 uint SharedRuntime::out_preserve_stack_slots() {
duke@0 3019 return frame::register_save_words * VMRegImpl::slots_per_word;
duke@0 3020 }
duke@0 3021
duke@0 3022 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
duke@0 3023 //
duke@0 3024 // Common out the new frame generation for deopt and uncommon trap
duke@0 3025 //
duke@0 3026 Register G3pcs = G3_scratch; // Array of new pcs (input)
duke@0 3027 Register Oreturn0 = O0;
duke@0 3028 Register Oreturn1 = O1;
duke@0 3029 Register O2UnrollBlock = O2;
duke@0 3030 Register O3array = O3; // Array of frame sizes (input)
duke@0 3031 Register O4array_size = O4; // number of frames (input)
duke@0 3032 Register O7frame_size = O7; // number of frames (input)
duke@0 3033
duke@0 3034 __ ld_ptr(O3array, 0, O7frame_size);
duke@0 3035 __ sub(G0, O7frame_size, O7frame_size);
duke@0 3036 __ save(SP, O7frame_size, SP);
duke@0 3037 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
duke@0 3038
duke@0 3039 #ifdef ASSERT
duke@0 3040 // make sure that the frames are aligned properly
duke@0 3041 #ifndef _LP64
duke@0 3042 __ btst(wordSize*2-1, SP);
duke@0 3043 __ breakpoint_trap(Assembler::notZero);
duke@0 3044 #endif
duke@0 3045 #endif
duke@0 3046
duke@0 3047 // Deopt needs to pass some extra live values from frame to frame
duke@0 3048
duke@0 3049 if (deopt) {
duke@0 3050 __ mov(Oreturn0->after_save(), Oreturn0);
duke@0 3051 __ mov(Oreturn1->after_save(), Oreturn1);
duke@0 3052 }
duke@0 3053
duke@0 3054 __ mov(O4array_size->after_save(), O4array_size);
duke@0 3055 __ sub(O4array_size, 1, O4array_size);
duke@0 3056 __ mov(O3array->after_save(), O3array);
duke@0 3057 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
duke@0 3058 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
duke@0 3059
duke@0 3060 #ifdef ASSERT
duke@0 3061 // trash registers to show a clear pattern in backtraces
duke@0 3062 __ set(0xDEAD0000, I0);
duke@0 3063 __ add(I0, 2, I1);
duke@0 3064 __ add(I0, 4, I2);
duke@0 3065 __ add(I0, 6, I3);
duke@0 3066 __ add(I0, 8, I4);
duke@0 3067 // Don't touch I5 could have valuable savedSP
duke@0 3068 __ set(0xDEADBEEF, L0);
duke@0 3069 __ mov(L0, L1);
duke@0 3070 __ mov(L0, L2);
duke@0 3071 __ mov(L0, L3);
duke@0 3072 __ mov(L0, L4);
duke@0 3073 __ mov(L0, L5);
duke@0 3074
duke@0 3075 // trash the return value as there is nothing to return yet
duke@0 3076 __ set(0xDEAD0001, O7);
duke@0 3077 #endif
duke@0 3078
duke@0 3079 __ mov(SP, O5_savedSP);
duke@0 3080 }
duke@0 3081
duke@0 3082
duke@0 3083 static void make_new_frames(MacroAssembler* masm, bool deopt) {
duke@0 3084 //
duke@0 3085 // loop through the UnrollBlock info and create new frames
duke@0 3086 //
duke@0 3087 Register G3pcs = G3_scratch;
duke@0 3088 Register Oreturn0 = O0;
duke@0 3089 Register Oreturn1 = O1;
duke@0 3090 Register O2UnrollBlock = O2;
duke@0 3091 Register O3array = O3;
duke@0 3092 Register O4array_size = O4;
duke@0 3093 Label loop;
duke@0 3094
duke@0 3095 // Before we make new frames, check to see if stack is available.
duke@0 3096 // Do this after the caller's return address is on top of stack
duke@0 3097 if (UseStackBanging) {
duke@0 3098 // Get total frame size for interpreted frames
twisti@720 3099 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
duke@0 3100 __ bang_stack_size(O4, O3, G3_scratch);
duke@0 3101 }
duke@0 3102
twisti@720 3103 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
twisti@720 3104 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
twisti@720 3105 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
duke@0 3106
duke@0 3107 // Adjust old interpreter frame to make space for new frame's extra java locals
duke@0 3108 //
duke@0 3109 // We capture the original sp for the transition frame only because it is needed in
duke@0 3110 // order to properly calculate interpreter_sp_adjustment. Even though in real life
duke@0 3111 // every interpreter frame captures a savedSP it is only needed at the transition
duke@0 3112 // (fortunately). If we had to have it correct everywhere then we would need to
duke@0 3113 // be told the sp_adjustment for each frame we create. If the frame size array
duke@0 3114 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
duke@0 3115 // for each frame we create and keep up the illusion every where.
duke@0 3116 //
duke@0 3117
twisti@720 3118 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
duke@0 3119 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
duke@0 3120 __ sub(SP, O7, SP);
duke@0 3121
duke@0 3122 #ifdef ASSERT
duke@0 3123 // make sure that there is at least one entry in the array
duke@0 3124 __ tst(O4array_size);
duke@0 3125 __ breakpoint_trap(Assembler::zero);
duke@0 3126 #endif
duke@0 3127
duke@0 3128 // Now push the new interpreter frames
duke@0 3129 __ bind(loop);
duke@0 3130
duke@0 3131 // allocate a new frame, filling the registers
duke@0 3132
duke@0 3133 gen_new_frame(masm, deopt); // allocate an interpreter frame
duke@0 3134
kvn@2600 3135 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop);
duke@0 3136 __ delayed()->add(O3array, wordSize, O3array);
duke@0 3137 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
duke@0 3138
duke@0 3139 }
duke@0 3140
duke@0 3141 //------------------------------generate_deopt_blob----------------------------
duke@0 3142 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 3143 // instead.
duke@0 3144 void SharedRuntime::generate_deopt_blob() {
duke@0 3145 // allocate space for the code
duke@0 3146 ResourceMark rm;
duke@0 3147 // setup code generation tools
duke@0 3148 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
duke@0 3149 #ifdef _LP64
duke@0 3150 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
duke@0 3151 #else
duke@0 3152 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
duke@0 3153 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
duke@0 3154 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
duke@0 3155 #endif /* _LP64 */
duke@0 3156 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3157 FloatRegister Freturn0 = F0;
duke@0 3158 Register Greturn1 = G1;
duke@0 3159 Register Oreturn0 = O0;
duke@0 3160 Register Oreturn1 = O1;
duke@0 3161 Register O2UnrollBlock = O2;
never@1002 3162 Register L0deopt_mode = L0;
never@1002 3163 Register G4deopt_mode = G4_scratch;
duke@0 3164 int frame_size_words;
twisti@720 3165 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
duke@0 3166 #if !defined(_LP64) && defined(COMPILER2)
twisti@720 3167 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
duke@0 3168 #endif
duke@0 3169 Label cont;
duke@0 3170
duke@0 3171 OopMapSet *oop_maps = new OopMapSet();
duke@0 3172
duke@0 3173 //
duke@0 3174 // This is the entry point for code which is returning to a de-optimized
duke@0 3175 // frame.
duke@0 3176 // The steps taken by this frame are as follows:
duke@0 3177 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
duke@0 3178 // and all potentially live registers (at a pollpoint many registers can be live).
duke@0 3179 //
duke@0 3180 // - call the C routine: Deoptimization::fetch_unroll_info (this function
duke@0 3181 // returns information about the number and size of interpreter frames
duke@0 3182 // which are equivalent to the frame which is being deoptimized)
duke@0 3183 // - deallocate the unpack frame, restoring only results values. Other
duke@0 3184 // volatile registers will now be captured in the vframeArray as needed.
duke@0 3185 // - deallocate the deoptimization frame
duke@0 3186 // - in a loop using the information returned in the previous step
duke@0 3187 // push new interpreter frames (take care to propagate the return
duke@0 3188 // values through each new frame pushed)
duke@0 3189 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
duke@0 3190 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 3191 // lays out values on the interpreter frame which was just created)
duke@0 3192 // - deallocate the dummy unpack_frame
duke@0 3193 // - ensure that all the return values are correctly set and then do
duke@0 3194 // a return to the interpreter entry point
duke@0 3195 //
duke@0 3196 // Refer to the following methods for more information:
duke@0 3197 // - Deoptimization::fetch_unroll_info
duke@0 3198 // - Deoptimization::unpack_frames
duke@0 3199
duke@0 3200 OopMap* map = NULL;
duke@0 3201
duke@0 3202 int start = __ offset();
duke@0 3203
duke@0 3204 // restore G2, the trampoline destroyed it
duke@0 3205 __ get_thread();
duke@0 3206
duke@0 3207 // On entry we have been called by the deoptimized nmethod with a call that
duke@0 3208 // replaced the original call (or safepoint polling location) so the deoptimizing
duke@0 3209 // pc is now in O7. Return values are still in the expected places
duke@0 3210
duke@0 3211 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
kvn@2600 3212 __ ba(cont);
never@1002 3213 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
duke@0 3214
duke@0 3215 int exception_offset = __ offset() - start;
duke@0 3216
duke@0 3217 // restore G2, the trampoline destroyed it
duke@0 3218 __ get_thread();
duke@0 3219
duke@0 3220 // On entry we have been jumped to by the exception handler (or exception_blob
duke@0 3221 // for server). O0 contains the exception oop and O7 contains the original
duke@0 3222 // exception pc. So if we push a frame here it will look to the
duke@0 3223 // stack walking code (fetch_unroll_info) just like a normal call so
duke@0 3224 // state will be extracted normally.
duke@0 3225
duke@0 3226 // save exception oop in JavaThread and fall through into the
duke@0 3227 // exception_in_tls case since they are handled in same way except
duke@0 3228 // for where the pending exception is kept.
twisti@720 3229 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
duke@0 3230
duke@0 3231 //
duke@0 3232 // Vanilla deoptimization with an exception pending in exception_oop
duke@0 3233 //
duke@0 3234 int exception_in_tls_offset = __ offset() - start;
duke@0 3235
duke@0 3236 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 3237 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3238
duke@0 3239 // Restore G2_thread
duke@0 3240 __ get_thread();
duke@0 3241
duke@0 3242 #ifdef ASSERT
duke@0 3243 {
duke@0 3244 // verify that there is really an exception oop in exception_oop
duke@0 3245 Label has_exception;
twisti@720 3246 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
kvn@2600 3247 __ br_notnull_short(Oexception, Assembler::pt, has_exception);
duke@0 3248 __ stop("no exception in thread");
duke@0 3249 __ bind(has_exception);
duke@0 3250
duke@0 3251 // verify that there is no pending exception
duke@0 3252 Label no_pending_exception;
twisti@720 3253 Address exception_addr(G2_thread, Thread::pending_exception_offset());
duke@0 3254 __ ld_ptr(exception_addr, Oexception);
kvn@2600 3255 __ br_null_short(Oexception, Assembler::pt, no_pending_exception);
duke@0 3256 __ stop("must not have pending exception here");
duke@0 3257 __ bind(no_pending_exception);
duke@0 3258 }
duke@0 3259 #endif
duke@0 3260
kvn@2600 3261 __ ba(cont);
never@1002 3262 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
duke@0 3263
duke@0 3264 //
duke@0 3265 // Reexecute entry, similar to c2 uncommon trap
duke@0 3266 //
duke@0 3267 int reexecute_offset = __ offset() - start;
duke@0 3268
duke@0 3269 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 3270 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3271
never@1002 3272 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
duke@0 3273
duke@0 3274 __ bind(cont);
duke@0 3275
duke@0 3276 __ set_last_Java_frame(SP, noreg);
duke@0 3277
duke@0 3278 // do the call by hand so we can get the oopmap
duke@0 3279
duke@0 3280 __ mov(G2_thread, L7_thread_cache);
duke@0 3281 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
duke@0 3282 __ delayed()->mov(G2_thread, O0);
duke@0 3283
duke@0 3284 // Set an oopmap for the call site this describes all our saved volatile registers
duke@0 3285
duke@0 3286 oop_maps->add_gc_map( __ offset()-start, map);
duke@0 3287
duke@0 3288 __ mov(L7_thread_cache, G2_thread);
duke@0 3289
duke@0 3290 __ reset_last_Java_frame();
duke@0 3291
duke@0 3292 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
duke@0 3293 // so this move will survive
duke@0 3294
never@1002 3295 __ mov(L0deopt_mode, G4deopt_mode);
duke@0 3296
duke@0 3297 __ mov(O0, O2UnrollBlock->after_save());
duke@0 3298
duke@0 3299 RegisterSaver::restore_result_registers(masm);
duke@0 3300
duke@0 3301 Label noException;
kvn@2600 3302 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException);
duke@0 3303
duke@0 3304 // Move the pending exception from exception_oop to Oexception so
duke@0 3305 // the pending exception will be picked up the interpreter.
duke@0 3306 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
duke@0 3307 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
duke@0 3308 __ bind(noException);
duke@0 3309
duke@0 3310 // deallocate the deoptimization frame taking care to preserve the return values
duke@0 3311 __ mov(Oreturn0, Oreturn0->after_save());
duke@0 3312 __ mov(Oreturn1, Oreturn1->after_save());
duke@0 3313 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 3314 __ restore();
duke@0 3315
duke@0 3316 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 3317
duke@0 3318 make_new_frames(masm, true);
duke@0 3319
duke@0 3320 // push a dummy "unpack_frame" taking care of float return values and
duke@0 3321 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 3322 // information in the interpreter frames just created and then return
duke@0 3323 // to the interpreter entry point
duke@0 3324 __ save(SP, -frame_size_words*wordSize, SP);
duke@0 3325 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
duke@0 3326 #if !defined(_LP64)
duke@0 3327 #if defined(COMPILER2)
iveresov@1681 3328 // 32-bit 1-register longs return longs in G1
iveresov@1681 3329 __ stx(Greturn1, saved_Greturn1_addr);
duke@0 3330 #endif
duke@0 3331 __ set_last_Java_frame(SP, noreg);
never@1002 3332 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
duke@0 3333 #else
duke@0 3334 // LP64 uses g4 in set_last_Java_frame
never@1002 3335 __ mov(G4deopt_mode, O1);
duke@0 3336 __ set_last_Java_frame(SP, G0);
duke@0 3337 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
duke@0 3338 #endif
duke@0 3339 __ reset_last_Java_frame();
duke@0 3340 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
duke@0 3341
duke@0 3342 #if !defined(_LP64) && defined(COMPILER2)
duke@0 3343 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
iveresov@1681 3344 // I0/I1 if the return value is long.
iveresov@1681 3345 Label not_long;
kvn@2600 3346 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long);
iveresov@1681 3347 __ ldd(saved_Greturn1_addr,I0);
iveresov@1681 3348 __ bind(not_long);
duke@0 3349 #endif
duke@0 3350 __ ret();
duke@0 3351 __ delayed()->restore();
duke@0 3352
duke@0 3353 masm->flush();
duke@0 3354 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
duke@0 3355 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
duke@0 3356 }
duke@0 3357
duke@0 3358 #ifdef COMPILER2
duke@0 3359
duke@0 3360 //------------------------------generate_uncommon_trap_blob--------------------
duke@0 3361 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 3362 // instead.
duke@0 3363 void SharedRuntime::generate_uncommon_trap_blob() {
duke@0 3364 // allocate space for the code
duke@0 3365 ResourceMark rm;
duke@0 3366 // setup code generation tools
duke@0 3367 int pad = VerifyThread ? 512 : 0;
duke@0 3368 #ifdef _LP64
duke@0 3369 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
duke@0 3370 #else
duke@0 3371 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
duke@0 3372 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
duke@0 3373 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
duke@0 3374 #endif
duke@0 3375 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3376 Register O2UnrollBlock = O2;
duke@0 3377 Register O2klass_index = O2;
duke@0 3378
duke@0 3379 //
duke@0 3380 // This is the entry point for all traps the compiler takes when it thinks
duke@0 3381 // it cannot handle further execution of compilation code. The frame is
duke@0 3382 // deoptimized in these cases and converted into interpreter frames for
duke@0 3383 // execution
duke@0 3384 // The steps taken by this frame are as follows:
duke@0 3385 // - push a fake "unpack_frame"
duke@0 3386 // - call the C routine Deoptimization::uncommon_trap (this function
duke@0 3387 // packs the current compiled frame into vframe arrays and returns
duke@0 3388 // information about the number and size of interpreter frames which
duke@0 3389 // are equivalent to the frame which is being deoptimized)
duke@0 3390 // - deallocate the "unpack_frame"
duke@0 3391 // - deallocate the deoptimization frame
duke@0 3392 // - in a loop using the information returned in the previous step
duke@0 3393 // push interpreter frames;
duke@0 3394 // - create a dummy "unpack_frame"
duke@0 3395 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 3396 // lays out values on the interpreter frame which was just created)
duke@0 3397 // - deallocate the dummy unpack_frame
duke@0 3398 // - return to the interpreter entry point
duke@0 3399 //
duke@0 3400 // Refer to the following methods for more information:
duke@0 3401 // - Deoptimization::uncommon_trap
duke@0 3402 // - Deoptimization::unpack_frame
duke@0 3403
duke@0 3404 // the unloaded class index is in O0 (first parameter to this blob)
duke@0 3405
duke@0 3406 // push a dummy "unpack_frame"
duke@0 3407 // and call Deoptimization::uncommon_trap to pack the compiled frame into
duke@0 3408 // vframe array and return the UnrollBlock information
duke@0 3409 __ save_frame(0);
duke@0 3410 __ set_last_Java_frame(SP, noreg);
duke@0 3411 __ mov(I0, O2klass_index);
duke@0 3412 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
duke@0 3413 __ reset_last_Java_frame();
duke@0 3414 __ mov(O0, O2UnrollBlock->after_save());
duke@0 3415 __ restore();
duke@0 3416
duke@0 3417 // deallocate the deoptimized frame taking care to preserve the return values
duke@0 3418 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 3419 __ restore();
duke@0 3420
duke@0 3421 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 3422
duke@0 3423 make_new_frames(masm, false);
duke@0 3424
duke@0 3425 // push a dummy "unpack_frame" taking care of float return values and
duke@0 3426 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 3427 // information in the interpreter frames just created and then return
duke@0 3428 // to the interpreter entry point
duke@0 3429 __ save_frame(0);
duke@0 3430 __ set_last_Java_frame(SP, noreg);
duke@0 3431 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
duke@0 3432 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
duke@0 3433 __ reset_last_Java_frame();
duke@0 3434 __ ret();
duke@0 3435 __ delayed()->restore();
duke@0 3436
duke@0 3437 masm->flush();
duke@0 3438 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
duke@0 3439 }
duke@0 3440
duke@0 3441 #endif // COMPILER2
duke@0 3442
duke@0 3443 //------------------------------generate_handler_blob-------------------
duke@0 3444 //
duke@0 3445 // Generate a special Compile2Runtime blob that saves all registers, and sets
duke@0 3446 // up an OopMap.
duke@0 3447 //
duke@0 3448 // This blob is jumped to (via a breakpoint and the signal handler) from a
duke@0 3449 // safepoint in compiled code. On entry to this blob, O7 contains the
duke@0 3450 // address in the original nmethod at which we should resume normal execution.
duke@0 3451 // Thus, this blob looks like a subroutine which must preserve lots of
duke@0 3452 // registers and return normally. Note that O7 is never register-allocated,
duke@0 3453 // so it is guaranteed to be free here.
duke@0 3454 //
duke@0 3455
duke@0 3456 // The hardest part of what this blob must do is to save the 64-bit %o
duke@0 3457 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
duke@0 3458 // an interrupt will chop off their heads. Making space in the caller's frame
duke@0 3459 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
duke@0 3460 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
duke@0 3461 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
duke@0 3462 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
duke@0 3463 // Tricky, tricky, tricky...
duke@0 3464
never@2511 3465 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
duke@0 3466 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@0 3467
duke@0 3468 // allocate space for the code
duke@0 3469 ResourceMark rm;
duke@0 3470 // setup code generation tools
duke@0 3471 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@0 3472 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@0 3473 // even larger with TraceJumps
duke@0 3474 int pad = TraceJumps ? 512 : 0;
duke@0 3475 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
duke@0 3476 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3477 int frame_size_words;
duke@0 3478 OopMapSet *oop_maps = new OopMapSet();
duke@0 3479 OopMap* map = NULL;
duke@0 3480
duke@0 3481 int start = __ offset();
duke@0 3482
duke@0 3483 // If this causes a return before the processing, then do a "restore"
duke@0 3484 if (cause_return) {
duke@0 3485 __ restore();
duke@0 3486 } else {
duke@0 3487 // Make it look like we were called via the poll
duke@0 3488 // so that frame constructor always sees a valid return address
duke@0 3489 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
duke@0 3490 __ sub(O7, frame::pc_return_offset, O7);
duke@0 3491 }
duke@0 3492
duke@0 3493 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3494
duke@0 3495 // setup last_Java_sp (blows G4)
duke@0 3496 __ set_last_Java_frame(SP, noreg);
duke@0 3497
duke@0 3498 // call into the runtime to handle illegal instructions exception
duke@0 3499 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
duke@0 3500 __ mov(G2_thread, O0);
duke@0 3501 __ save_thread(L7_thread_cache);
duke@0 3502 __ call(call_ptr);
duke@0 3503 __ delayed()->nop();
duke@0 <