annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 0:a61af66fc99e

Initial load
author duke
date Sat, 01 Dec 2007 00:00:00 +0000
parents
children ba764ed4b6f2
rev   line source
duke@0 1 /*
duke@0 2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 #include "incls/_precompiled.incl"
duke@0 26 #include "incls/_sharedRuntime_sparc.cpp.incl"
duke@0 27
duke@0 28 #define __ masm->
duke@0 29
duke@0 30 #ifdef COMPILER2
duke@0 31 UncommonTrapBlob* SharedRuntime::_uncommon_trap_blob;
duke@0 32 #endif // COMPILER2
duke@0 33
duke@0 34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
duke@0 35 SafepointBlob* SharedRuntime::_polling_page_safepoint_handler_blob;
duke@0 36 SafepointBlob* SharedRuntime::_polling_page_return_handler_blob;
duke@0 37 RuntimeStub* SharedRuntime::_wrong_method_blob;
duke@0 38 RuntimeStub* SharedRuntime::_ic_miss_blob;
duke@0 39 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
duke@0 40 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
duke@0 41 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
duke@0 42
duke@0 43 class RegisterSaver {
duke@0 44
duke@0 45 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@0 46 // The Oregs are problematic. In the 32bit build the compiler can
duke@0 47 // have O registers live with 64 bit quantities. A window save will
duke@0 48 // cut the heads off of the registers. We have to do a very extensive
duke@0 49 // stack dance to save and restore these properly.
duke@0 50
duke@0 51 // Note that the Oregs problem only exists if we block at either a polling
duke@0 52 // page exception a compiled code safepoint that was not originally a call
duke@0 53 // or deoptimize following one of these kinds of safepoints.
duke@0 54
duke@0 55 // Lots of registers to save. For all builds, a window save will preserve
duke@0 56 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@0 57 // builds a window-save will preserve the %o registers. In the LION build
duke@0 58 // we need to save the 64-bit %o registers which requires we save them
duke@0 59 // before the window-save (as then they become %i registers and get their
duke@0 60 // heads chopped off on interrupt). We have to save some %g registers here
duke@0 61 // as well.
duke@0 62 enum {
duke@0 63 // This frame's save area. Includes extra space for the native call:
duke@0 64 // vararg's layout space and the like. Briefly holds the caller's
duke@0 65 // register save area.
duke@0 66 call_args_area = frame::register_save_words_sp_offset +
duke@0 67 frame::memory_parameter_word_sp_offset*wordSize,
duke@0 68 // Make sure save locations are always 8 byte aligned.
duke@0 69 // can't use round_to because it doesn't produce compile time constant
duke@0 70 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@0 71 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@0 72 g3_offset = g1_offset+8,
duke@0 73 g4_offset = g3_offset+8,
duke@0 74 g5_offset = g4_offset+8,
duke@0 75 o0_offset = g5_offset+8,
duke@0 76 o1_offset = o0_offset+8,
duke@0 77 o2_offset = o1_offset+8,
duke@0 78 o3_offset = o2_offset+8,
duke@0 79 o4_offset = o3_offset+8,
duke@0 80 o5_offset = o4_offset+8,
duke@0 81 start_of_flags_save_area = o5_offset+8,
duke@0 82 ccr_offset = start_of_flags_save_area,
duke@0 83 fsr_offset = ccr_offset + 8,
duke@0 84 d00_offset = fsr_offset+8, // Start of float save area
duke@0 85 register_save_size = d00_offset+8*32
duke@0 86 };
duke@0 87
duke@0 88
duke@0 89 public:
duke@0 90
duke@0 91 static int Oexception_offset() { return o0_offset; };
duke@0 92 static int G3_offset() { return g3_offset; };
duke@0 93 static int G5_offset() { return g5_offset; };
duke@0 94 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@0 95 static void restore_live_registers(MacroAssembler* masm);
duke@0 96
duke@0 97 // During deoptimization only the result register need to be restored
duke@0 98 // all the other values have already been extracted.
duke@0 99
duke@0 100 static void restore_result_registers(MacroAssembler* masm);
duke@0 101 };
duke@0 102
duke@0 103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@0 104 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@0 105 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@0 106 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@0 107 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@0 108 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@0 109 int i;
duke@0 110 // Always make the frame size 16 bytr aligned.
duke@0 111 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@0 112 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@0 113 int frame_size_in_slots = frame_size / sizeof(jint);
duke@0 114 // CodeBlob frame size is in words.
duke@0 115 *total_frame_words = frame_size / wordSize;
duke@0 116 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@0 117 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@0 118
duke@0 119 #if !defined(_LP64)
duke@0 120
duke@0 121 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@0 122 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 123 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 124 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 125 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 126 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 127 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 128 #endif /* _LP64 */
duke@0 129
duke@0 130 __ save(SP, -frame_size, SP);
duke@0 131
duke@0 132 #ifndef _LP64
duke@0 133 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@0 134 // to Oregs here to avoid interrupts cutting off their heads
duke@0 135
duke@0 136 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 137 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 138 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 139 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 140 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 141 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 142
duke@0 143 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@0 144 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@0 145
duke@0 146 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@0 147
duke@0 148 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@0 149
duke@0 150 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@0 151 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@0 152
duke@0 153 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@0 154 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@0 155
duke@0 156 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@0 157 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@0 158
duke@0 159 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@0 160 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@0 161 #endif /* _LP64 */
duke@0 162
duke@0 163 // Save the G's
duke@0 164 __ stx(G1, SP, g1_offset+STACK_BIAS);
duke@0 165 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + 4)>>2), G1->as_VMReg());
duke@0 166
duke@0 167 __ stx(G3, SP, g3_offset+STACK_BIAS);
duke@0 168 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + 4)>>2), G3->as_VMReg());
duke@0 169
duke@0 170 __ stx(G4, SP, g4_offset+STACK_BIAS);
duke@0 171 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + 4)>>2), G4->as_VMReg());
duke@0 172
duke@0 173 __ stx(G5, SP, g5_offset+STACK_BIAS);
duke@0 174 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + 4)>>2), G5->as_VMReg());
duke@0 175
duke@0 176 // This is really a waste but we'll keep things as they were for now
duke@0 177 if (true) {
duke@0 178 #ifndef _LP64
duke@0 179 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@0 180 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@0 181 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@0 182 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@0 183 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@0 184 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@0 185 #endif /* _LP64 */
duke@0 186 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@0 187 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@0 188 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@0 189 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
duke@0 190 }
duke@0 191
duke@0 192
duke@0 193 // Save the flags
duke@0 194 __ rdccr( G5 );
duke@0 195 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@0 196 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 197
duke@0 198 // Save all the FP registers
duke@0 199 int offset = d00_offset;
duke@0 200 for( int i=0; i<64; i+=2 ) {
duke@0 201 FloatRegister f = as_FloatRegister(i);
duke@0 202 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
duke@0 203 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
duke@0 204 if (true) {
duke@0 205 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@0 206 }
duke@0 207 offset += sizeof(double);
duke@0 208 }
duke@0 209
duke@0 210 // And we're done.
duke@0 211
duke@0 212 return map;
duke@0 213 }
duke@0 214
duke@0 215
duke@0 216 // Pop the current frame and restore all the registers that we
duke@0 217 // saved.
duke@0 218 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@0 219
duke@0 220 // Restore all the FP registers
duke@0 221 for( int i=0; i<64; i+=2 ) {
duke@0 222 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@0 223 }
duke@0 224
duke@0 225 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@0 226 __ wrccr (G1) ;
duke@0 227
duke@0 228 // Restore the G's
duke@0 229 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@0 230 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@0 231
duke@0 232 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 233 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@0 234 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@0 235 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@0 236
duke@0 237
duke@0 238 #if !defined(_LP64)
duke@0 239 // Restore the 64-bit O's.
duke@0 240 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 241 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 242 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@0 243 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@0 244 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@0 245 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@0 246
duke@0 247 // And temporarily place them in TLS
duke@0 248
duke@0 249 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 250 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 251 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 252 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 253 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 254 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 255 #endif /* _LP64 */
duke@0 256
duke@0 257 // Restore flags
duke@0 258
duke@0 259 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 260
duke@0 261 __ restore();
duke@0 262
duke@0 263 #if !defined(_LP64)
duke@0 264 // Now reload the 64bit Oregs after we've restore the window.
duke@0 265 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 266 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 267 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 268 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 269 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 270 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 271 #endif /* _LP64 */
duke@0 272
duke@0 273 }
duke@0 274
duke@0 275 // Pop the current frame and restore the registers that might be holding
duke@0 276 // a result.
duke@0 277 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@0 278
duke@0 279 #if !defined(_LP64)
duke@0 280 // 32bit build returns longs in G1
duke@0 281 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 282
duke@0 283 // Retrieve the 64-bit O's.
duke@0 284 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 285 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 286 // and save to TLS
duke@0 287 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 288 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 289 #endif /* _LP64 */
duke@0 290
duke@0 291 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@0 292
duke@0 293 __ restore();
duke@0 294
duke@0 295 #if !defined(_LP64)
duke@0 296 // Now reload the 64bit Oregs after we've restore the window.
duke@0 297 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 298 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 299 #endif /* _LP64 */
duke@0 300
duke@0 301 }
duke@0 302
duke@0 303 // The java_calling_convention describes stack locations as ideal slots on
duke@0 304 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@0 305 // (like the placement of the register window) the slots must be biased by
duke@0 306 // the following value.
duke@0 307 static int reg2offset(VMReg r) {
duke@0 308 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@0 309 }
duke@0 310
duke@0 311 // ---------------------------------------------------------------------------
duke@0 312 // Read the array of BasicTypes from a signature, and compute where the
duke@0 313 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@0 314 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@0 315 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@0 316 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@0 317 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@0 318 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@0 319 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@0 320 // Each 32-bit quantity is given its own number, so the integer registers
duke@0 321 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@0 322 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@0 323
duke@0 324 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@0 325 // convert to incoming arguments, convert all O's to I's. The regs array
duke@0 326 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@0 327 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@0 328 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@0 329 // passed (used as a placeholder for the other half of longs and doubles in
duke@0 330 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@0 331 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@0 332 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@0 333 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@0 334 // same VMRegPair.
duke@0 335
duke@0 336 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@0 337 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@0 338 // units regardless of build.
duke@0 339
duke@0 340
duke@0 341 // ---------------------------------------------------------------------------
duke@0 342 // The compiled Java calling convention. The Java convention always passes
duke@0 343 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@0 344 // floats in float registers and doubles in aligned float pairs. Values are
duke@0 345 // packed in the registers. There is no backing varargs store for values in
duke@0 346 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@0 347 // passed in I's, because longs in I's get their heads chopped off at
duke@0 348 // interrupt).
duke@0 349 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@0 350 VMRegPair *regs,
duke@0 351 int total_args_passed,
duke@0 352 int is_outgoing) {
duke@0 353 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@0 354
duke@0 355 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@0 356 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@0 357 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@0 358 // align. Then put longs and doubles into the same registers as they fit,
duke@0 359 // else spill to the stack.
duke@0 360 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@0 361 const int flt_reg_max = 8;
duke@0 362 //
duke@0 363 // Where 32-bit 1-reg longs start being passed
duke@0 364 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@0 365 // So make it look like we've filled all the G regs that c2 wants to use.
duke@0 366 Register g_reg = TieredCompilation ? noreg : G1;
duke@0 367
duke@0 368 // Count int/oop and float args. See how many stack slots we'll need and
duke@0 369 // where the longs & doubles will go.
duke@0 370 int int_reg_cnt = 0;
duke@0 371 int flt_reg_cnt = 0;
duke@0 372 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@0 373 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@0 374 int stk_reg_pairs = 0;
duke@0 375 for (int i = 0; i < total_args_passed; i++) {
duke@0 376 switch (sig_bt[i]) {
duke@0 377 case T_LONG: // LP64, longs compete with int args
duke@0 378 assert(sig_bt[i+1] == T_VOID, "");
duke@0 379 #ifdef _LP64
duke@0 380 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 381 #endif
duke@0 382 break;
duke@0 383 case T_OBJECT:
duke@0 384 case T_ARRAY:
duke@0 385 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 386 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 387 #ifndef _LP64
duke@0 388 else stk_reg_pairs++;
duke@0 389 #endif
duke@0 390 break;
duke@0 391 case T_INT:
duke@0 392 case T_SHORT:
duke@0 393 case T_CHAR:
duke@0 394 case T_BYTE:
duke@0 395 case T_BOOLEAN:
duke@0 396 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 397 else stk_reg_pairs++;
duke@0 398 break;
duke@0 399 case T_FLOAT:
duke@0 400 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@0 401 else stk_reg_pairs++;
duke@0 402 break;
duke@0 403 case T_DOUBLE:
duke@0 404 assert(sig_bt[i+1] == T_VOID, "");
duke@0 405 break;
duke@0 406 case T_VOID:
duke@0 407 break;
duke@0 408 default:
duke@0 409 ShouldNotReachHere();
duke@0 410 }
duke@0 411 }
duke@0 412
duke@0 413 // This is where the longs/doubles start on the stack.
duke@0 414 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@0 415
duke@0 416 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
duke@0 417 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@0 418
duke@0 419 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@0 420 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@0 421 int stk_reg = 0;
duke@0 422 int int_reg = 0;
duke@0 423 int flt_reg = 0;
duke@0 424
duke@0 425 // Now do the signature layout
duke@0 426 for (int i = 0; i < total_args_passed; i++) {
duke@0 427 switch (sig_bt[i]) {
duke@0 428 case T_INT:
duke@0 429 case T_SHORT:
duke@0 430 case T_CHAR:
duke@0 431 case T_BYTE:
duke@0 432 case T_BOOLEAN:
duke@0 433 #ifndef _LP64
duke@0 434 case T_OBJECT:
duke@0 435 case T_ARRAY:
duke@0 436 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 437 #endif // _LP64
duke@0 438 if (int_reg < int_reg_max) {
duke@0 439 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 440 regs[i].set1(r->as_VMReg());
duke@0 441 } else {
duke@0 442 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 443 }
duke@0 444 break;
duke@0 445
duke@0 446 #ifdef _LP64
duke@0 447 case T_OBJECT:
duke@0 448 case T_ARRAY:
duke@0 449 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 450 if (int_reg < int_reg_max) {
duke@0 451 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 452 regs[i].set2(r->as_VMReg());
duke@0 453 } else {
duke@0 454 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 455 stk_reg_pairs += 2;
duke@0 456 }
duke@0 457 break;
duke@0 458 #endif // _LP64
duke@0 459
duke@0 460 case T_LONG:
duke@0 461 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@0 462 #ifdef COMPILER2
duke@0 463 #ifdef _LP64
duke@0 464 // Can't be tiered (yet)
duke@0 465 if (int_reg < int_reg_max) {
duke@0 466 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 467 regs[i].set2(r->as_VMReg());
duke@0 468 } else {
duke@0 469 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 470 stk_reg_pairs += 2;
duke@0 471 }
duke@0 472 #else
duke@0 473 // For 32-bit build, can't pass longs in O-regs because they become
duke@0 474 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@0 475 // spare and available. This convention isn't used by the Sparc ABI or
duke@0 476 // anywhere else. If we're tiered then we don't use G-regs because c1
duke@0 477 // can't deal with them as a "pair".
duke@0 478 // G0: zero
duke@0 479 // G1: 1st Long arg
duke@0 480 // G2: global allocated to TLS
duke@0 481 // G3: used in inline cache check
duke@0 482 // G4: 2nd Long arg
duke@0 483 // G5: used in inline cache check
duke@0 484 // G6: used by OS
duke@0 485 // G7: used by OS
duke@0 486
duke@0 487 if (g_reg == G1) {
duke@0 488 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@0 489 g_reg = G4; // Where the next arg goes
duke@0 490 } else if (g_reg == G4) {
duke@0 491 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@0 492 g_reg = noreg; // No more longs in registers
duke@0 493 } else {
duke@0 494 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 495 stk_reg_pairs += 2;
duke@0 496 }
duke@0 497 #endif // _LP64
duke@0 498 #else // COMPILER2
duke@0 499 if (int_reg_pairs + 1 < int_reg_max) {
duke@0 500 if (is_outgoing) {
duke@0 501 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
duke@0 502 } else {
duke@0 503 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
duke@0 504 }
duke@0 505 int_reg_pairs += 2;
duke@0 506 } else {
duke@0 507 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 508 stk_reg_pairs += 2;
duke@0 509 }
duke@0 510 #endif // COMPILER2
duke@0 511 break;
duke@0 512
duke@0 513 case T_FLOAT:
duke@0 514 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
duke@0 515 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
duke@0 516 break;
duke@0 517 case T_DOUBLE:
duke@0 518 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@0 519 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@0 520 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@0 521 flt_reg_pairs += 2;
duke@0 522 } else {
duke@0 523 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 524 stk_reg_pairs += 2;
duke@0 525 }
duke@0 526 break;
duke@0 527 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@0 528 default:
duke@0 529 ShouldNotReachHere();
duke@0 530 }
duke@0 531 }
duke@0 532
duke@0 533 // retun the amount of stack space these arguments will need.
duke@0 534 return stk_reg_pairs;
duke@0 535
duke@0 536 }
duke@0 537
duke@0 538 // Helper class mostly to avoid passing masm everywhere, and handle store
duke@0 539 // displacement overflow logic for LP64
duke@0 540 class AdapterGenerator {
duke@0 541 MacroAssembler *masm;
duke@0 542 #ifdef _LP64
duke@0 543 Register Rdisp;
duke@0 544 void set_Rdisp(Register r) { Rdisp = r; }
duke@0 545 #endif // _LP64
duke@0 546
duke@0 547 void patch_callers_callsite();
duke@0 548 void tag_c2i_arg(frame::Tag t, Register base, int st_off, Register scratch);
duke@0 549
duke@0 550 // base+st_off points to top of argument
duke@0 551 int arg_offset(const int st_off) { return st_off + Interpreter::value_offset_in_bytes(); }
duke@0 552 int next_arg_offset(const int st_off) {
duke@0 553 return st_off - Interpreter::stackElementSize() + Interpreter::value_offset_in_bytes();
duke@0 554 }
duke@0 555
duke@0 556 #ifdef _LP64
duke@0 557 // On _LP64 argument slot values are loaded first into a register
duke@0 558 // because they might not fit into displacement.
duke@0 559 Register arg_slot(const int st_off);
duke@0 560 Register next_arg_slot(const int st_off);
duke@0 561 #else
duke@0 562 int arg_slot(const int st_off) { return arg_offset(st_off); }
duke@0 563 int next_arg_slot(const int st_off) { return next_arg_offset(st_off); }
duke@0 564 #endif // _LP64
duke@0 565
duke@0 566 // Stores long into offset pointed to by base
duke@0 567 void store_c2i_long(Register r, Register base,
duke@0 568 const int st_off, bool is_stack);
duke@0 569 void store_c2i_object(Register r, Register base,
duke@0 570 const int st_off);
duke@0 571 void store_c2i_int(Register r, Register base,
duke@0 572 const int st_off);
duke@0 573 void store_c2i_double(VMReg r_2,
duke@0 574 VMReg r_1, Register base, const int st_off);
duke@0 575 void store_c2i_float(FloatRegister f, Register base,
duke@0 576 const int st_off);
duke@0 577
duke@0 578 public:
duke@0 579 void gen_c2i_adapter(int total_args_passed,
duke@0 580 // VMReg max_arg,
duke@0 581 int comp_args_on_stack, // VMRegStackSlots
duke@0 582 const BasicType *sig_bt,
duke@0 583 const VMRegPair *regs,
duke@0 584 Label& skip_fixup);
duke@0 585 void gen_i2c_adapter(int total_args_passed,
duke@0 586 // VMReg max_arg,
duke@0 587 int comp_args_on_stack, // VMRegStackSlots
duke@0 588 const BasicType *sig_bt,
duke@0 589 const VMRegPair *regs);
duke@0 590
duke@0 591 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@0 592 };
duke@0 593
duke@0 594
duke@0 595 // Patch the callers callsite with entry to compiled code if it exists.
duke@0 596 void AdapterGenerator::patch_callers_callsite() {
duke@0 597 Label L;
duke@0 598 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 599 __ br_null(G3_scratch, false, __ pt, L);
duke@0 600 // Schedule the branch target address early.
duke@0 601 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 602 // Call into the VM to patch the caller, then jump to compiled callee
duke@0 603 __ save_frame(4); // Args in compiled layout; do not blow them
duke@0 604
duke@0 605 // Must save all the live Gregs the list is:
duke@0 606 // G1: 1st Long arg (32bit build)
duke@0 607 // G2: global allocated to TLS
duke@0 608 // G3: used in inline cache check (scratch)
duke@0 609 // G4: 2nd Long arg (32bit build);
duke@0 610 // G5: used in inline cache check (methodOop)
duke@0 611
duke@0 612 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@0 613
duke@0 614 #ifdef _LP64
duke@0 615 // mov(s,d)
duke@0 616 __ mov(G1, L1);
duke@0 617 __ mov(G4, L4);
duke@0 618 __ mov(G5_method, L5);
duke@0 619 __ mov(G5_method, O0); // VM needs target method
duke@0 620 __ mov(I7, O1); // VM needs caller's callsite
duke@0 621 // Must be a leaf call...
duke@0 622 // can be very far once the blob has been relocated
duke@0 623 Address dest(O7, CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@0 624 __ relocate(relocInfo::runtime_call_type);
duke@0 625 __ jumpl_to(dest, O7);
duke@0 626 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 627 __ mov(L7_thread_cache, G2_thread);
duke@0 628 __ mov(L1, G1);
duke@0 629 __ mov(L4, G4);
duke@0 630 __ mov(L5, G5_method);
duke@0 631 #else
duke@0 632 __ stx(G1, FP, -8 + STACK_BIAS);
duke@0 633 __ stx(G4, FP, -16 + STACK_BIAS);
duke@0 634 __ mov(G5_method, L5);
duke@0 635 __ mov(G5_method, O0); // VM needs target method
duke@0 636 __ mov(I7, O1); // VM needs caller's callsite
duke@0 637 // Must be a leaf call...
duke@0 638 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@0 639 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 640 __ mov(L7_thread_cache, G2_thread);
duke@0 641 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@0 642 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@0 643 __ mov(L5, G5_method);
duke@0 644 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 645 #endif /* _LP64 */
duke@0 646
duke@0 647 __ restore(); // Restore args
duke@0 648 __ bind(L);
duke@0 649 }
duke@0 650
duke@0 651 void AdapterGenerator::tag_c2i_arg(frame::Tag t, Register base, int st_off,
duke@0 652 Register scratch) {
duke@0 653 if (TaggedStackInterpreter) {
duke@0 654 int tag_off = st_off + Interpreter::tag_offset_in_bytes();
duke@0 655 #ifdef _LP64
duke@0 656 Register tag_slot = Rdisp;
duke@0 657 __ set(tag_off, tag_slot);
duke@0 658 #else
duke@0 659 int tag_slot = tag_off;
duke@0 660 #endif // _LP64
duke@0 661 // have to store zero because local slots can be reused (rats!)
duke@0 662 if (t == frame::TagValue) {
duke@0 663 __ st_ptr(G0, base, tag_slot);
duke@0 664 } else if (t == frame::TagCategory2) {
duke@0 665 __ st_ptr(G0, base, tag_slot);
duke@0 666 int next_tag_off = st_off - Interpreter::stackElementSize() +
duke@0 667 Interpreter::tag_offset_in_bytes();
duke@0 668 #ifdef _LP64
duke@0 669 __ set(next_tag_off, tag_slot);
duke@0 670 #else
duke@0 671 tag_slot = next_tag_off;
duke@0 672 #endif // _LP64
duke@0 673 __ st_ptr(G0, base, tag_slot);
duke@0 674 } else {
duke@0 675 __ mov(t, scratch);
duke@0 676 __ st_ptr(scratch, base, tag_slot);
duke@0 677 }
duke@0 678 }
duke@0 679 }
duke@0 680
duke@0 681 #ifdef _LP64
duke@0 682 Register AdapterGenerator::arg_slot(const int st_off) {
duke@0 683 __ set( arg_offset(st_off), Rdisp);
duke@0 684 return Rdisp;
duke@0 685 }
duke@0 686
duke@0 687 Register AdapterGenerator::next_arg_slot(const int st_off){
duke@0 688 __ set( next_arg_offset(st_off), Rdisp);
duke@0 689 return Rdisp;
duke@0 690 }
duke@0 691 #endif // _LP64
duke@0 692
duke@0 693 // Stores long into offset pointed to by base
duke@0 694 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@0 695 const int st_off, bool is_stack) {
duke@0 696 #ifdef COMPILER2
duke@0 697 #ifdef _LP64
duke@0 698 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 699 // data is passed in only 1 slot.
duke@0 700 __ stx(r, base, next_arg_slot(st_off));
duke@0 701 #else
duke@0 702 // Misaligned store of 64-bit data
duke@0 703 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 704 __ srlx(r, 32, r);
duke@0 705 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 706 #endif // _LP64
duke@0 707 #else
duke@0 708 if (is_stack) {
duke@0 709 // Misaligned store of 64-bit data
duke@0 710 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 711 __ srlx(r, 32, r);
duke@0 712 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 713 } else {
duke@0 714 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@0 715 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@0 716 }
duke@0 717 #endif // COMPILER2
duke@0 718 tag_c2i_arg(frame::TagCategory2, base, st_off, r);
duke@0 719 }
duke@0 720
duke@0 721 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@0 722 const int st_off) {
duke@0 723 __ st_ptr (r, base, arg_slot(st_off));
duke@0 724 tag_c2i_arg(frame::TagReference, base, st_off, r);
duke@0 725 }
duke@0 726
duke@0 727 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@0 728 const int st_off) {
duke@0 729 __ st (r, base, arg_slot(st_off));
duke@0 730 tag_c2i_arg(frame::TagValue, base, st_off, r);
duke@0 731 }
duke@0 732
duke@0 733 // Stores into offset pointed to by base
duke@0 734 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@0 735 VMReg r_1, Register base, const int st_off) {
duke@0 736 #ifdef _LP64
duke@0 737 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 738 // data is passed in only 1 slot.
duke@0 739 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 740 #else
duke@0 741 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 742 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 743 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@0 744 #endif
duke@0 745 tag_c2i_arg(frame::TagCategory2, base, st_off, G1_scratch);
duke@0 746 }
duke@0 747
duke@0 748 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@0 749 const int st_off) {
duke@0 750 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@0 751 tag_c2i_arg(frame::TagValue, base, st_off, G1_scratch);
duke@0 752 }
duke@0 753
duke@0 754 void AdapterGenerator::gen_c2i_adapter(
duke@0 755 int total_args_passed,
duke@0 756 // VMReg max_arg,
duke@0 757 int comp_args_on_stack, // VMRegStackSlots
duke@0 758 const BasicType *sig_bt,
duke@0 759 const VMRegPair *regs,
duke@0 760 Label& skip_fixup) {
duke@0 761
duke@0 762 // Before we get into the guts of the C2I adapter, see if we should be here
duke@0 763 // at all. We've come from compiled code and are attempting to jump to the
duke@0 764 // interpreter, which means the caller made a static call to get here
duke@0 765 // (vcalls always get a compiled target if there is one). Check for a
duke@0 766 // compiled target. If there is one, we need to patch the caller's call.
duke@0 767 // However we will run interpreted if we come thru here. The next pass
duke@0 768 // thru the call site will run compiled. If we ran compiled here then
duke@0 769 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@0 770 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@0 771 // we can have at most one and don't need to play any tricks to keep
duke@0 772 // from endlessly growing the stack.
duke@0 773 //
duke@0 774 // Actually if we detected that we had an i2c->c2i transition here we
duke@0 775 // ought to be able to reset the world back to the state of the interpreted
duke@0 776 // call and not bother building another interpreter arg area. We don't
duke@0 777 // do that at this point.
duke@0 778
duke@0 779 patch_callers_callsite();
duke@0 780
duke@0 781 __ bind(skip_fixup);
duke@0 782
duke@0 783 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@0 784 // space we need. Add in varargs area needed by the interpreter. Round up
duke@0 785 // to stack alignment.
duke@0 786 const int arg_size = total_args_passed * Interpreter::stackElementSize();
duke@0 787 const int varargs_area =
duke@0 788 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@0 789 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@0 790
duke@0 791 int bias = STACK_BIAS;
duke@0 792 const int interp_arg_offset = frame::varargs_offset*wordSize +
duke@0 793 (total_args_passed-1)*Interpreter::stackElementSize();
duke@0 794
duke@0 795 Register base = SP;
duke@0 796
duke@0 797 #ifdef _LP64
duke@0 798 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@0 799 // out of bits in the displacement to do loads and stores. Use g3 as
duke@0 800 // temporary displacement.
duke@0 801 if (! __ is_simm13(extraspace)) {
duke@0 802 __ set(extraspace, G3_scratch);
duke@0 803 __ sub(SP, G3_scratch, SP);
duke@0 804 } else {
duke@0 805 __ sub(SP, extraspace, SP);
duke@0 806 }
duke@0 807 set_Rdisp(G3_scratch);
duke@0 808 #else
duke@0 809 __ sub(SP, extraspace, SP);
duke@0 810 #endif // _LP64
duke@0 811
duke@0 812 // First write G1 (if used) to where ever it must go
duke@0 813 for (int i=0; i<total_args_passed; i++) {
duke@0 814 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
duke@0 815 VMReg r_1 = regs[i].first();
duke@0 816 VMReg r_2 = regs[i].second();
duke@0 817 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 818 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 819 store_c2i_object(G1_scratch, base, st_off);
duke@0 820 } else if (sig_bt[i] == T_LONG) {
duke@0 821 assert(!TieredCompilation, "should not use register args for longs");
duke@0 822 store_c2i_long(G1_scratch, base, st_off, false);
duke@0 823 } else {
duke@0 824 store_c2i_int(G1_scratch, base, st_off);
duke@0 825 }
duke@0 826 }
duke@0 827 }
duke@0 828
duke@0 829 // Now write the args into the outgoing interpreter space
duke@0 830 for (int i=0; i<total_args_passed; i++) {
duke@0 831 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize()) + bias;
duke@0 832 VMReg r_1 = regs[i].first();
duke@0 833 VMReg r_2 = regs[i].second();
duke@0 834 if (!r_1->is_valid()) {
duke@0 835 assert(!r_2->is_valid(), "");
duke@0 836 continue;
duke@0 837 }
duke@0 838 // Skip G1 if found as we did it first in order to free it up
duke@0 839 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 840 continue;
duke@0 841 }
duke@0 842 #ifdef ASSERT
duke@0 843 bool G1_forced = false;
duke@0 844 #endif // ASSERT
duke@0 845 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@0 846 #ifdef _LP64
duke@0 847 Register ld_off = Rdisp;
duke@0 848 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@0 849 #else
duke@0 850 int ld_off = reg2offset(r_1) + extraspace + bias;
duke@0 851 #ifdef ASSERT
duke@0 852 G1_forced = true;
duke@0 853 #endif // ASSERT
duke@0 854 #endif // _LP64
duke@0 855 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@0 856 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@0 857 else __ ldx(base, ld_off, G1_scratch);
duke@0 858 }
duke@0 859
duke@0 860 if (r_1->is_Register()) {
duke@0 861 Register r = r_1->as_Register()->after_restore();
duke@0 862 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 863 store_c2i_object(r, base, st_off);
duke@0 864 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
duke@0 865 if (TieredCompilation) {
duke@0 866 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@0 867 }
duke@0 868 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@0 869 } else {
duke@0 870 store_c2i_int(r, base, st_off);
duke@0 871 }
duke@0 872 } else {
duke@0 873 assert(r_1->is_FloatRegister(), "");
duke@0 874 if (sig_bt[i] == T_FLOAT) {
duke@0 875 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@0 876 } else {
duke@0 877 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@0 878 store_c2i_double(r_2, r_1, base, st_off);
duke@0 879 }
duke@0 880 }
duke@0 881 }
duke@0 882
duke@0 883 #ifdef _LP64
duke@0 884 // Need to reload G3_scratch, used for temporary displacements.
duke@0 885 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 886
duke@0 887 // Pass O5_savedSP as an argument to the interpreter.
duke@0 888 // The interpreter will restore SP to this value before returning.
duke@0 889 __ set(extraspace, G1);
duke@0 890 __ add(SP, G1, O5_savedSP);
duke@0 891 #else
duke@0 892 // Pass O5_savedSP as an argument to the interpreter.
duke@0 893 // The interpreter will restore SP to this value before returning.
duke@0 894 __ add(SP, extraspace, O5_savedSP);
duke@0 895 #endif // _LP64
duke@0 896
duke@0 897 __ mov((frame::varargs_offset)*wordSize -
duke@0 898 1*Interpreter::stackElementSize()+bias+BytesPerWord, G1);
duke@0 899 // Jump to the interpreter just as if interpreter was doing it.
duke@0 900 __ jmpl(G3_scratch, 0, G0);
duke@0 901 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@0 902 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@0 903 // the interpreter does not know where its args are without some kind of
duke@0 904 // arg pointer being passed in. Pass it in Gargs.
duke@0 905 __ delayed()->add(SP, G1, Gargs);
duke@0 906 }
duke@0 907
duke@0 908 void AdapterGenerator::gen_i2c_adapter(
duke@0 909 int total_args_passed,
duke@0 910 // VMReg max_arg,
duke@0 911 int comp_args_on_stack, // VMRegStackSlots
duke@0 912 const BasicType *sig_bt,
duke@0 913 const VMRegPair *regs) {
duke@0 914
duke@0 915 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@0 916 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@0 917 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@0 918 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@0 919 // hoist register arguments and repack other args according to the compiled
duke@0 920 // code convention. Finally, end in a jump to the compiled code. The entry
duke@0 921 // point address is the start of the buffer.
duke@0 922
duke@0 923 // We will only enter here from an interpreted frame and never from after
duke@0 924 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@0 925 // race and use a c2i we will remain interpreted for the race loser(s).
duke@0 926 // This removes all sorts of headaches on the x86 side and also eliminates
duke@0 927 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@0 928
duke@0 929 // As you can see from the list of inputs & outputs there are not a lot
duke@0 930 // of temp registers to work with: mostly G1, G3 & G4.
duke@0 931
duke@0 932 // Inputs:
duke@0 933 // G2_thread - TLS
duke@0 934 // G5_method - Method oop
duke@0 935 // O0 - Flag telling us to restore SP from O5
duke@0 936 // O4_args - Pointer to interpreter's args
duke@0 937 // O5 - Caller's saved SP, to be restored if needed
duke@0 938 // O6 - Current SP!
duke@0 939 // O7 - Valid return address
duke@0 940 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 941
duke@0 942 // Outputs:
duke@0 943 // G2_thread - TLS
duke@0 944 // G1, G4 - Outgoing long args in 32-bit build
duke@0 945 // O0-O5 - Outgoing args in compiled layout
duke@0 946 // O6 - Adjusted or restored SP
duke@0 947 // O7 - Valid return address
duke@0 948 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 949 // F0-F7 - more outgoing args
duke@0 950
duke@0 951
duke@0 952 // O4 is about to get loaded up with compiled callee's args
duke@0 953 __ sub(Gargs, BytesPerWord, Gargs);
duke@0 954
duke@0 955 #ifdef ASSERT
duke@0 956 {
duke@0 957 // on entry OsavedSP and SP should be equal
duke@0 958 Label ok;
duke@0 959 __ cmp(O5_savedSP, SP);
duke@0 960 __ br(Assembler::equal, false, Assembler::pt, ok);
duke@0 961 __ delayed()->nop();
duke@0 962 __ stop("I5_savedSP not set");
duke@0 963 __ should_not_reach_here();
duke@0 964 __ bind(ok);
duke@0 965 }
duke@0 966 #endif
duke@0 967
duke@0 968 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@0 969 // WITH O7 HOLDING A VALID RETURN PC
duke@0 970 //
duke@0 971 // | |
duke@0 972 // : java stack :
duke@0 973 // | |
duke@0 974 // +--------------+ <--- start of outgoing args
duke@0 975 // | receiver | |
duke@0 976 // : rest of args : |---size is java-arg-words
duke@0 977 // | | |
duke@0 978 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@0 979 // | | |
duke@0 980 // : unused : |---Space for max Java stack, plus stack alignment
duke@0 981 // | | |
duke@0 982 // +--------------+ <--- SP + 16*wordsize
duke@0 983 // | |
duke@0 984 // : window :
duke@0 985 // | |
duke@0 986 // +--------------+ <--- SP
duke@0 987
duke@0 988 // WE REPACK THE STACK. We use the common calling convention layout as
duke@0 989 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@0 990 // causes an arbitrary shuffle of memory, which may require some register
duke@0 991 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@0 992 // temps are not needed. We may have to resize the stack slightly, in case
duke@0 993 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@0 994 // misaligned, but the compilers expect them aligned).
duke@0 995 //
duke@0 996 // | |
duke@0 997 // : java stack :
duke@0 998 // | |
duke@0 999 // +--------------+ <--- start of outgoing args
duke@0 1000 // | pad, align | |
duke@0 1001 // +--------------+ |
duke@0 1002 // | ints, floats | |---Outgoing stack args, packed low.
duke@0 1003 // +--------------+ | First few args in registers.
duke@0 1004 // : doubles : |
duke@0 1005 // | longs | |
duke@0 1006 // +--------------+ <--- SP' + 16*wordsize
duke@0 1007 // | |
duke@0 1008 // : window :
duke@0 1009 // | |
duke@0 1010 // +--------------+ <--- SP'
duke@0 1011
duke@0 1012 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@0 1013 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@0 1014 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@0 1015
duke@0 1016 // Cut-out for having no stack args. Since up to 6 args are passed
duke@0 1017 // in registers, we will commonly have no stack args.
duke@0 1018 if (comp_args_on_stack > 0) {
duke@0 1019
duke@0 1020 // Convert VMReg stack slots to words.
duke@0 1021 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@0 1022 // Round up to miminum stack alignment, in wordSize
duke@0 1023 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@0 1024 // Now compute the distance from Lesp to SP. This calculation does not
duke@0 1025 // include the space for total_args_passed because Lesp has not yet popped
duke@0 1026 // the arguments.
duke@0 1027 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@0 1028 }
duke@0 1029
duke@0 1030 // Will jump to the compiled code just as if compiled code was doing it.
duke@0 1031 // Pre-load the register-jump target early, to schedule it better.
duke@0 1032 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@0 1033
duke@0 1034 // Now generate the shuffle code. Pick up all register args and move the
duke@0 1035 // rest through G1_scratch.
duke@0 1036 for (int i=0; i<total_args_passed; i++) {
duke@0 1037 if (sig_bt[i] == T_VOID) {
duke@0 1038 // Longs and doubles are passed in native word order, but misaligned
duke@0 1039 // in the 32-bit build.
duke@0 1040 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@0 1041 continue;
duke@0 1042 }
duke@0 1043
duke@0 1044 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@0 1045 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@0 1046 // ldx/lddf optimizations.
duke@0 1047
duke@0 1048 // Load in argument order going down.
duke@0 1049 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
duke@0 1050 #ifdef _LP64
duke@0 1051 set_Rdisp(G1_scratch);
duke@0 1052 #endif // _LP64
duke@0 1053
duke@0 1054 VMReg r_1 = regs[i].first();
duke@0 1055 VMReg r_2 = regs[i].second();
duke@0 1056 if (!r_1->is_valid()) {
duke@0 1057 assert(!r_2->is_valid(), "");
duke@0 1058 continue;
duke@0 1059 }
duke@0 1060 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@0 1061 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@0 1062 if (r_2->is_valid()) r_2 = r_1->next();
duke@0 1063 }
duke@0 1064 if (r_1->is_Register()) { // Register argument
duke@0 1065 Register r = r_1->as_Register()->after_restore();
duke@0 1066 if (!r_2->is_valid()) {
duke@0 1067 __ ld(Gargs, arg_slot(ld_off), r);
duke@0 1068 } else {
duke@0 1069 #ifdef _LP64
duke@0 1070 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 1071 // data is passed in only 1 slot.
duke@0 1072 Register slot = (sig_bt[i]==T_LONG) ?
duke@0 1073 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1074 __ ldx(Gargs, slot, r);
duke@0 1075 #else
duke@0 1076 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@0 1077 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@0 1078 #endif
duke@0 1079 }
duke@0 1080 } else {
duke@0 1081 assert(r_1->is_FloatRegister(), "");
duke@0 1082 if (!r_2->is_valid()) {
duke@0 1083 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1084 } else {
duke@0 1085 #ifdef _LP64
duke@0 1086 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 1087 // data is passed in only 1 slot. This code also handles longs that
duke@0 1088 // are passed on the stack, but need a stack-to-stack move through a
duke@0 1089 // spare float register.
duke@0 1090 Register slot = (sig_bt[i]==T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@0 1091 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1092 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@0 1093 #else
duke@0 1094 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1095 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1096 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@0 1097 #endif
duke@0 1098 }
duke@0 1099 }
duke@0 1100 // Was the argument really intended to be on the stack, but was loaded
duke@0 1101 // into F8/F9?
duke@0 1102 if (regs[i].first()->is_stack()) {
duke@0 1103 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@0 1104 // Convert stack slot to an SP offset
duke@0 1105 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@0 1106 // Store down the shuffled stack word. Target address _is_ aligned.
duke@0 1107 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, st_off);
duke@0 1108 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, st_off);
duke@0 1109 }
duke@0 1110 }
duke@0 1111 bool made_space = false;
duke@0 1112 #ifndef _LP64
duke@0 1113 // May need to pick up a few long args in G1/G4
duke@0 1114 bool g4_crushed = false;
duke@0 1115 bool g3_crushed = false;
duke@0 1116 for (int i=0; i<total_args_passed; i++) {
duke@0 1117 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@0 1118 // Load in argument order going down
duke@0 1119 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize();
duke@0 1120 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1121 Register r = regs[i].first()->as_Register()->after_restore();
duke@0 1122 if (r == G1 || r == G4) {
duke@0 1123 assert(!g4_crushed, "ordering problem");
duke@0 1124 if (r == G4){
duke@0 1125 g4_crushed = true;
duke@0 1126 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1127 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1128 } else {
duke@0 1129 // better schedule this way
duke@0 1130 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1131 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1132 }
duke@0 1133 g3_crushed = true;
duke@0 1134 __ sllx(r, 32, r);
duke@0 1135 __ or3(G3_scratch, r, r);
duke@0 1136 } else {
duke@0 1137 assert(r->is_out(), "longs passed in two O registers");
duke@0 1138 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@0 1139 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1140 }
duke@0 1141 }
duke@0 1142 }
duke@0 1143 #endif
duke@0 1144
duke@0 1145 // Jump to the compiled code just as if compiled code was doing it.
duke@0 1146 //
duke@0 1147 #ifndef _LP64
duke@0 1148 if (g3_crushed) {
duke@0 1149 // Rats load was wasted, at least it is in cache...
duke@0 1150 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@0 1151 }
duke@0 1152 #endif /* _LP64 */
duke@0 1153
duke@0 1154 // 6243940 We might end up in handle_wrong_method if
duke@0 1155 // the callee is deoptimized as we race thru here. If that
duke@0 1156 // happens we don't want to take a safepoint because the
duke@0 1157 // caller frame will look interpreted and arguments are now
duke@0 1158 // "compiled" so it is much better to make this transition
duke@0 1159 // invisible to the stack walking code. Unfortunately if
duke@0 1160 // we try and find the callee by normal means a safepoint
duke@0 1161 // is possible. So we stash the desired callee in the thread
duke@0 1162 // and the vm will find there should this case occur.
duke@0 1163 Address callee_target_addr(G2_thread, 0, in_bytes(JavaThread::callee_target_offset()));
duke@0 1164 __ st_ptr(G5_method, callee_target_addr);
duke@0 1165
duke@0 1166 if (StressNonEntrant) {
duke@0 1167 // Open a big window for deopt failure
duke@0 1168 __ save_frame(0);
duke@0 1169 __ mov(G0, L0);
duke@0 1170 Label loop;
duke@0 1171 __ bind(loop);
duke@0 1172 __ sub(L0, 1, L0);
duke@0 1173 __ br_null(L0, false, Assembler::pt, loop);
duke@0 1174 __ delayed()->nop();
duke@0 1175
duke@0 1176 __ restore();
duke@0 1177 }
duke@0 1178
duke@0 1179
duke@0 1180 __ jmpl(G3, 0, G0);
duke@0 1181 __ delayed()->nop();
duke@0 1182 }
duke@0 1183
duke@0 1184 // ---------------------------------------------------------------
duke@0 1185 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@0 1186 int total_args_passed,
duke@0 1187 // VMReg max_arg,
duke@0 1188 int comp_args_on_stack, // VMRegStackSlots
duke@0 1189 const BasicType *sig_bt,
duke@0 1190 const VMRegPair *regs) {
duke@0 1191 address i2c_entry = __ pc();
duke@0 1192
duke@0 1193 AdapterGenerator agen(masm);
duke@0 1194
duke@0 1195 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@0 1196
duke@0 1197
duke@0 1198 // -------------------------------------------------------------------------
duke@0 1199 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
duke@0 1200 // args start out packed in the compiled layout. They need to be unpacked
duke@0 1201 // into the interpreter layout. This will almost always require some stack
duke@0 1202 // space. We grow the current (compiled) stack, then repack the args. We
duke@0 1203 // finally end in a jump to the generic interpreter entry point. On exit
duke@0 1204 // from the interpreter, the interpreter will restore our SP (lest the
duke@0 1205 // compiled code, which relys solely on SP and not FP, get sick).
duke@0 1206
duke@0 1207 address c2i_unverified_entry = __ pc();
duke@0 1208 Label skip_fixup;
duke@0 1209 {
duke@0 1210 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1211 Register R_temp = L0; // another scratch register
duke@0 1212 #else
duke@0 1213 Register R_temp = G1; // another scratch register
duke@0 1214 #endif
duke@0 1215
duke@0 1216 Address ic_miss(G3_scratch, SharedRuntime::get_ic_miss_stub());
duke@0 1217
duke@0 1218 __ verify_oop(O0);
duke@0 1219 __ verify_oop(G5_method);
duke@0 1220 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
duke@0 1221 __ verify_oop(G3_scratch);
duke@0 1222
duke@0 1223 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1224 __ save(SP, -frame::register_save_words*wordSize, SP);
duke@0 1225 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1226 __ verify_oop(R_temp);
duke@0 1227 __ cmp(G3_scratch, R_temp);
duke@0 1228 __ restore();
duke@0 1229 #else
duke@0 1230 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@0 1231 __ verify_oop(R_temp);
duke@0 1232 __ cmp(G3_scratch, R_temp);
duke@0 1233 #endif
duke@0 1234
duke@0 1235 Label ok, ok2;
duke@0 1236 __ brx(Assembler::equal, false, Assembler::pt, ok);
duke@0 1237 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
duke@0 1238 __ jump_to(ic_miss);
duke@0 1239 __ delayed()->nop();
duke@0 1240
duke@0 1241 __ bind(ok);
duke@0 1242 // Method might have been compiled since the call site was patched to
duke@0 1243 // interpreted if that is the case treat it as a miss so we can get
duke@0 1244 // the call site corrected.
duke@0 1245 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@0 1246 __ bind(ok2);
duke@0 1247 __ br_null(G3_scratch, false, __ pt, skip_fixup);
duke@0 1248 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@0 1249 __ jump_to(ic_miss);
duke@0 1250 __ delayed()->nop();
duke@0 1251
duke@0 1252 }
duke@0 1253
duke@0 1254 address c2i_entry = __ pc();
duke@0 1255
duke@0 1256 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@0 1257
duke@0 1258 __ flush();
duke@0 1259 return new AdapterHandlerEntry(i2c_entry, c2i_entry, c2i_unverified_entry);
duke@0 1260
duke@0 1261 }
duke@0 1262
duke@0 1263 // Helper function for native calling conventions
duke@0 1264 static VMReg int_stk_helper( int i ) {
duke@0 1265 // Bias any stack based VMReg we get by ignoring the window area
duke@0 1266 // but not the register parameter save area.
duke@0 1267 //
duke@0 1268 // This is strange for the following reasons. We'd normally expect
duke@0 1269 // the calling convention to return an VMReg for a stack slot
duke@0 1270 // completely ignoring any abi reserved area. C2 thinks of that
duke@0 1271 // abi area as only out_preserve_stack_slots. This does not include
duke@0 1272 // the area allocated by the C abi to store down integer arguments
duke@0 1273 // because the java calling convention does not use it. So
duke@0 1274 // since c2 assumes that there are only out_preserve_stack_slots
duke@0 1275 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@0 1276 // location the c calling convention must add in this bias amount
duke@0 1277 // to make up for the fact that the out_preserve_stack_slots is
duke@0 1278 // insufficient for C calls. What a mess. I sure hope those 6
duke@0 1279 // stack words were worth it on every java call!
duke@0 1280
duke@0 1281 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@0 1282 // to take a parameter to say whether it was C or java calling conventions.
duke@0 1283 // Then things might look a little better (but not much).
duke@0 1284
duke@0 1285 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@0 1286 if( mem_parm_offset < 0 ) {
duke@0 1287 return as_oRegister(i)->as_VMReg();
duke@0 1288 } else {
duke@0 1289 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@0 1290 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@0 1291 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@0 1292 }
duke@0 1293 }
duke@0 1294
duke@0 1295
duke@0 1296 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@0 1297 VMRegPair *regs,
duke@0 1298 int total_args_passed) {
duke@0 1299
duke@0 1300 // Return the number of VMReg stack_slots needed for the args.
duke@0 1301 // This value does not include an abi space (like register window
duke@0 1302 // save area).
duke@0 1303
duke@0 1304 // The native convention is V8 if !LP64
duke@0 1305 // The LP64 convention is the V9 convention which is slightly more sane.
duke@0 1306
duke@0 1307 // We return the amount of VMReg stack slots we need to reserve for all
duke@0 1308 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@0 1309 // have space for storing at least 6 registers to memory we start with that.
duke@0 1310 // See int_stk_helper for a further discussion.
duke@0 1311 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@0 1312
duke@0 1313 #ifdef _LP64
duke@0 1314 // V9 convention: All things "as-if" on double-wide stack slots.
duke@0 1315 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@0 1316 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@0 1317 int j = 0; // Count of actual args, not HALVES
duke@0 1318 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@0 1319 switch( sig_bt[i] ) {
duke@0 1320 case T_BOOLEAN:
duke@0 1321 case T_BYTE:
duke@0 1322 case T_CHAR:
duke@0 1323 case T_INT:
duke@0 1324 case T_SHORT:
duke@0 1325 regs[i].set1( int_stk_helper( j ) ); break;
duke@0 1326 case T_LONG:
duke@0 1327 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1328 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1329 case T_ARRAY:
duke@0 1330 case T_OBJECT:
duke@0 1331 regs[i].set2( int_stk_helper( j ) );
duke@0 1332 break;
duke@0 1333 case T_FLOAT:
duke@0 1334 if ( j < 16 ) {
duke@0 1335 // V9ism: floats go in ODD registers
duke@0 1336 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@0 1337 } else {
duke@0 1338 // V9ism: floats go in ODD stack slot
duke@0 1339 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@0 1340 }
duke@0 1341 break;
duke@0 1342 case T_DOUBLE:
duke@0 1343 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1344 if ( j < 16 ) {
duke@0 1345 // V9ism: doubles go in EVEN/ODD regs
duke@0 1346 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@0 1347 } else {
duke@0 1348 // V9ism: doubles go in EVEN/ODD stack slots
duke@0 1349 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@0 1350 }
duke@0 1351 break;
duke@0 1352 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@0 1353 default:
duke@0 1354 ShouldNotReachHere();
duke@0 1355 }
duke@0 1356 if (regs[i].first()->is_stack()) {
duke@0 1357 int off = regs[i].first()->reg2stack();
duke@0 1358 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1359 }
duke@0 1360 if (regs[i].second()->is_stack()) {
duke@0 1361 int off = regs[i].second()->reg2stack();
duke@0 1362 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1363 }
duke@0 1364 }
duke@0 1365
duke@0 1366 #else // _LP64
duke@0 1367 // V8 convention: first 6 things in O-regs, rest on stack.
duke@0 1368 // Alignment is willy-nilly.
duke@0 1369 for( int i=0; i<total_args_passed; i++ ) {
duke@0 1370 switch( sig_bt[i] ) {
duke@0 1371 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1372 case T_ARRAY:
duke@0 1373 case T_BOOLEAN:
duke@0 1374 case T_BYTE:
duke@0 1375 case T_CHAR:
duke@0 1376 case T_FLOAT:
duke@0 1377 case T_INT:
duke@0 1378 case T_OBJECT:
duke@0 1379 case T_SHORT:
duke@0 1380 regs[i].set1( int_stk_helper( i ) );
duke@0 1381 break;
duke@0 1382 case T_DOUBLE:
duke@0 1383 case T_LONG:
duke@0 1384 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1385 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@0 1386 break;
duke@0 1387 case T_VOID: regs[i].set_bad(); break;
duke@0 1388 default:
duke@0 1389 ShouldNotReachHere();
duke@0 1390 }
duke@0 1391 if (regs[i].first()->is_stack()) {
duke@0 1392 int off = regs[i].first()->reg2stack();
duke@0 1393 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1394 }
duke@0 1395 if (regs[i].second()->is_stack()) {
duke@0 1396 int off = regs[i].second()->reg2stack();
duke@0 1397 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1398 }
duke@0 1399 }
duke@0 1400 #endif // _LP64
duke@0 1401
duke@0 1402 return round_to(max_stack_slots + 1, 2);
duke@0 1403
duke@0 1404 }
duke@0 1405
duke@0 1406
duke@0 1407 // ---------------------------------------------------------------------------
duke@0 1408 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1409 switch (ret_type) {
duke@0 1410 case T_FLOAT:
duke@0 1411 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@0 1412 break;
duke@0 1413 case T_DOUBLE:
duke@0 1414 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@0 1415 break;
duke@0 1416 }
duke@0 1417 }
duke@0 1418
duke@0 1419 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1420 switch (ret_type) {
duke@0 1421 case T_FLOAT:
duke@0 1422 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@0 1423 break;
duke@0 1424 case T_DOUBLE:
duke@0 1425 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@0 1426 break;
duke@0 1427 }
duke@0 1428 }
duke@0 1429
duke@0 1430 // Check and forward and pending exception. Thread is stored in
duke@0 1431 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@0 1432 // is no exception handler. We merely pop this frame off and throw the
duke@0 1433 // exception in the caller's frame.
duke@0 1434 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@0 1435 Label L;
duke@0 1436 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@0 1437 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@0 1438 // Since this is a native call, we *know* the proper exception handler
duke@0 1439 // without calling into the VM: it's the empty function. Just pop this
duke@0 1440 // frame and then jump to forward_exception_entry; O7 will contain the
duke@0 1441 // native caller's return PC.
duke@0 1442 Address exception_entry(G3_scratch, StubRoutines::forward_exception_entry());
duke@0 1443 __ jump_to(exception_entry);
duke@0 1444 __ delayed()->restore(); // Pop this frame off.
duke@0 1445 __ bind(L);
duke@0 1446 }
duke@0 1447
duke@0 1448 // A simple move of integer like type
duke@0 1449 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1450 if (src.first()->is_stack()) {
duke@0 1451 if (dst.first()->is_stack()) {
duke@0 1452 // stack to stack
duke@0 1453 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1454 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1455 } else {
duke@0 1456 // stack to reg
duke@0 1457 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1458 }
duke@0 1459 } else if (dst.first()->is_stack()) {
duke@0 1460 // reg to stack
duke@0 1461 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1462 } else {
duke@0 1463 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1464 }
duke@0 1465 }
duke@0 1466
duke@0 1467 // On 64 bit we will store integer like items to the stack as
duke@0 1468 // 64 bits items (sparc abi) even though java would only store
duke@0 1469 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@0 1470 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@0 1471 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1472 if (src.first()->is_stack()) {
duke@0 1473 if (dst.first()->is_stack()) {
duke@0 1474 // stack to stack
duke@0 1475 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1476 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1477 } else {
duke@0 1478 // stack to reg
duke@0 1479 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1480 }
duke@0 1481 } else if (dst.first()->is_stack()) {
duke@0 1482 // reg to stack
duke@0 1483 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1484 } else {
duke@0 1485 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1486 }
duke@0 1487 }
duke@0 1488
duke@0 1489
duke@0 1490 // An oop arg. Must pass a handle not the oop itself
duke@0 1491 static void object_move(MacroAssembler* masm,
duke@0 1492 OopMap* map,
duke@0 1493 int oop_handle_offset,
duke@0 1494 int framesize_in_slots,
duke@0 1495 VMRegPair src,
duke@0 1496 VMRegPair dst,
duke@0 1497 bool is_receiver,
duke@0 1498 int* receiver_offset) {
duke@0 1499
duke@0 1500 // must pass a handle. First figure out the location we use as a handle
duke@0 1501
duke@0 1502 if (src.first()->is_stack()) {
duke@0 1503 // Oop is already on the stack
duke@0 1504 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@0 1505 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@0 1506 __ ld_ptr(rHandle, 0, L4);
duke@0 1507 #ifdef _LP64
duke@0 1508 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@0 1509 #else
duke@0 1510 __ tst( L4 );
duke@0 1511 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1512 #endif
duke@0 1513 if (dst.first()->is_stack()) {
duke@0 1514 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1515 }
duke@0 1516 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@0 1517 if (is_receiver) {
duke@0 1518 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@0 1519 }
duke@0 1520 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@0 1521 } else {
duke@0 1522 // Oop is in an input register pass we must flush it to the stack
duke@0 1523 const Register rOop = src.first()->as_Register();
duke@0 1524 const Register rHandle = L5;
duke@0 1525 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@0 1526 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@0 1527 Label skip;
duke@0 1528 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@0 1529 if (is_receiver) {
duke@0 1530 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@0 1531 }
duke@0 1532 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@0 1533 __ add(SP, offset + STACK_BIAS, rHandle);
duke@0 1534 #ifdef _LP64
duke@0 1535 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@0 1536 #else
duke@0 1537 __ tst( rOop );
duke@0 1538 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1539 #endif
duke@0 1540
duke@0 1541 if (dst.first()->is_stack()) {
duke@0 1542 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1543 } else {
duke@0 1544 __ mov(rHandle, dst.first()->as_Register());
duke@0 1545 }
duke@0 1546 }
duke@0 1547 }
duke@0 1548
duke@0 1549 // A float arg may have to do float reg int reg conversion
duke@0 1550 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1551 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@0 1552
duke@0 1553 if (src.first()->is_stack()) {
duke@0 1554 if (dst.first()->is_stack()) {
duke@0 1555 // stack to stack the easiest of the bunch
duke@0 1556 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1557 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1558 } else {
duke@0 1559 // stack to reg
duke@0 1560 if (dst.first()->is_Register()) {
duke@0 1561 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1562 } else {
duke@0 1563 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1564 }
duke@0 1565 }
duke@0 1566 } else if (dst.first()->is_stack()) {
duke@0 1567 // reg to stack
duke@0 1568 if (src.first()->is_Register()) {
duke@0 1569 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1570 } else {
duke@0 1571 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1572 }
duke@0 1573 } else {
duke@0 1574 // reg to reg
duke@0 1575 if (src.first()->is_Register()) {
duke@0 1576 if (dst.first()->is_Register()) {
duke@0 1577 // gpr -> gpr
duke@0 1578 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1579 } else {
duke@0 1580 // gpr -> fpr
duke@0 1581 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1582 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1583 }
duke@0 1584 } else if (dst.first()->is_Register()) {
duke@0 1585 // fpr -> gpr
duke@0 1586 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@0 1587 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@0 1588 } else {
duke@0 1589 // fpr -> fpr
duke@0 1590 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1591 if ( src.first() != dst.first()) {
duke@0 1592 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1593 }
duke@0 1594 }
duke@0 1595 }
duke@0 1596 }
duke@0 1597
duke@0 1598 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1599 VMRegPair src_lo(src.first());
duke@0 1600 VMRegPair src_hi(src.second());
duke@0 1601 VMRegPair dst_lo(dst.first());
duke@0 1602 VMRegPair dst_hi(dst.second());
duke@0 1603 simple_move32(masm, src_lo, dst_lo);
duke@0 1604 simple_move32(masm, src_hi, dst_hi);
duke@0 1605 }
duke@0 1606
duke@0 1607 // A long move
duke@0 1608 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1609
duke@0 1610 // Do the simple ones here else do two int moves
duke@0 1611 if (src.is_single_phys_reg() ) {
duke@0 1612 if (dst.is_single_phys_reg()) {
duke@0 1613 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1614 } else {
duke@0 1615 // split src into two separate registers
duke@0 1616 // Remember hi means hi address or lsw on sparc
duke@0 1617 // Move msw to lsw
duke@0 1618 if (dst.second()->is_reg()) {
duke@0 1619 // MSW -> MSW
duke@0 1620 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@0 1621 // Now LSW -> LSW
duke@0 1622 // this will only move lo -> lo and ignore hi
duke@0 1623 VMRegPair split(dst.second());
duke@0 1624 simple_move32(masm, src, split);
duke@0 1625 } else {
duke@0 1626 VMRegPair split(src.first(), L4->as_VMReg());
duke@0 1627 // MSW -> MSW (lo ie. first word)
duke@0 1628 __ srax(src.first()->as_Register(), 32, L4);
duke@0 1629 split_long_move(masm, split, dst);
duke@0 1630 }
duke@0 1631 }
duke@0 1632 } else if (dst.is_single_phys_reg()) {
duke@0 1633 if (src.is_adjacent_aligned_on_stack(2)) {
duke@0 1634 __ ldd(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1635 } else {
duke@0 1636 // dst is a single reg.
duke@0 1637 // Remember lo is low address not msb for stack slots
duke@0 1638 // and lo is the "real" register for registers
duke@0 1639 // src is
duke@0 1640
duke@0 1641 VMRegPair split;
duke@0 1642
duke@0 1643 if (src.first()->is_reg()) {
duke@0 1644 // src.lo (msw) is a reg, src.hi is stk/reg
duke@0 1645 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@0 1646 split.set_pair(dst.first(), src.first());
duke@0 1647 } else {
duke@0 1648 // msw is stack move to L5
duke@0 1649 // lsw is stack move to dst.lo (real reg)
duke@0 1650 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@0 1651 split.set_pair(dst.first(), L5->as_VMReg());
duke@0 1652 }
duke@0 1653
duke@0 1654 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@0 1655 // msw -> src.lo/L5, lsw -> dst.lo
duke@0 1656 split_long_move(masm, src, split);
duke@0 1657
duke@0 1658 // So dst now has the low order correct position the
duke@0 1659 // msw half
duke@0 1660 __ sllx(split.first()->as_Register(), 32, L5);
duke@0 1661
duke@0 1662 const Register d = dst.first()->as_Register();
duke@0 1663 __ or3(L5, d, d);
duke@0 1664 }
duke@0 1665 } else {
duke@0 1666 // For LP64 we can probably do better.
duke@0 1667 split_long_move(masm, src, dst);
duke@0 1668 }
duke@0 1669 }
duke@0 1670
duke@0 1671 // A double move
duke@0 1672 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1673
duke@0 1674 // The painful thing here is that like long_move a VMRegPair might be
duke@0 1675 // 1: a single physical register
duke@0 1676 // 2: two physical registers (v8)
duke@0 1677 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@0 1678 // 4: two stack slots
duke@0 1679
duke@0 1680 // Since src is always a java calling convention we know that the src pair
duke@0 1681 // is always either all registers or all stack (and aligned?)
duke@0 1682
duke@0 1683 // in a register [lo] and a stack slot [hi]
duke@0 1684 if (src.first()->is_stack()) {
duke@0 1685 if (dst.first()->is_stack()) {
duke@0 1686 // stack to stack the easiest of the bunch
duke@0 1687 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@0 1688 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1689 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1690 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1691 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1692 } else {
duke@0 1693 // stack to reg
duke@0 1694 if (dst.second()->is_stack()) {
duke@0 1695 // stack -> reg, stack -> stack
duke@0 1696 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1697 if (dst.first()->is_Register()) {
duke@0 1698 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1699 } else {
duke@0 1700 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1701 }
duke@0 1702 // This was missing. (very rare case)
duke@0 1703 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1704 } else {
duke@0 1705 // stack -> reg
duke@0 1706 // Eventually optimize for alignment QQQ
duke@0 1707 if (dst.first()->is_Register()) {
duke@0 1708 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1709 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@0 1710 } else {
duke@0 1711 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1712 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1713 }
duke@0 1714 }
duke@0 1715 }
duke@0 1716 } else if (dst.first()->is_stack()) {
duke@0 1717 // reg to stack
duke@0 1718 if (src.first()->is_Register()) {
duke@0 1719 // Eventually optimize for alignment QQQ
duke@0 1720 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1721 if (src.second()->is_stack()) {
duke@0 1722 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1723 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1724 } else {
duke@0 1725 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1726 }
duke@0 1727 } else {
duke@0 1728 // fpr to stack
duke@0 1729 if (src.second()->is_stack()) {
duke@0 1730 ShouldNotReachHere();
duke@0 1731 } else {
duke@0 1732 // Is the stack aligned?
duke@0 1733 if (reg2offset(dst.first()) & 0x7) {
duke@0 1734 // No do as pairs
duke@0 1735 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1736 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1737 } else {
duke@0 1738 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1739 }
duke@0 1740 }
duke@0 1741 }
duke@0 1742 } else {
duke@0 1743 // reg to reg
duke@0 1744 if (src.first()->is_Register()) {
duke@0 1745 if (dst.first()->is_Register()) {
duke@0 1746 // gpr -> gpr
duke@0 1747 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1748 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@0 1749 } else {
duke@0 1750 // gpr -> fpr
duke@0 1751 // ought to be able to do a single store
duke@0 1752 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@0 1753 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1754 // ought to be able to do a single load
duke@0 1755 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1756 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1757 }
duke@0 1758 } else if (dst.first()->is_Register()) {
duke@0 1759 // fpr -> gpr
duke@0 1760 // ought to be able to do a single store
duke@0 1761 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@0 1762 // ought to be able to do a single load
duke@0 1763 // REMEMBER first() is low address not LSB
duke@0 1764 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@0 1765 if (dst.second()->is_Register()) {
duke@0 1766 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@0 1767 } else {
duke@0 1768 __ ld(FP, -4 + STACK_BIAS, L4);
duke@0 1769 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1770 }
duke@0 1771 } else {
duke@0 1772 // fpr -> fpr
duke@0 1773 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1774 if ( src.first() != dst.first()) {
duke@0 1775 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1776 }
duke@0 1777 }
duke@0 1778 }
duke@0 1779 }
duke@0 1780
duke@0 1781 // Creates an inner frame if one hasn't already been created, and
duke@0 1782 // saves a copy of the thread in L7_thread_cache
duke@0 1783 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@0 1784 if (!*already_created) {
duke@0 1785 __ save_frame(0);
duke@0 1786 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@0 1787 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@0 1788 // copy
duke@0 1789 __ mov(G2_thread, L7_thread_cache);
duke@0 1790 *already_created = true;
duke@0 1791 }
duke@0 1792 }
duke@0 1793
duke@0 1794 // ---------------------------------------------------------------------------
duke@0 1795 // Generate a native wrapper for a given method. The method takes arguments
duke@0 1796 // in the Java compiled code convention, marshals them to the native
duke@0 1797 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@0 1798 // returns to java state (possibly blocking), unhandlizes any result and
duke@0 1799 // returns.
duke@0 1800 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@0 1801 methodHandle method,
duke@0 1802 int total_in_args,
duke@0 1803 int comp_args_on_stack, // in VMRegStackSlots
duke@0 1804 BasicType *in_sig_bt,
duke@0 1805 VMRegPair *in_regs,
duke@0 1806 BasicType ret_type) {
duke@0 1807
duke@0 1808
duke@0 1809 // Native nmethod wrappers never take possesion of the oop arguments.
duke@0 1810 // So the caller will gc the arguments. The only thing we need an
duke@0 1811 // oopMap for is if the call is static
duke@0 1812 //
duke@0 1813 // An OopMap for lock (and class if static), and one for the VM call itself
duke@0 1814 OopMapSet *oop_maps = new OopMapSet();
duke@0 1815 intptr_t start = (intptr_t)__ pc();
duke@0 1816
duke@0 1817 // First thing make an ic check to see if we should even be here
duke@0 1818 {
duke@0 1819 Label L;
duke@0 1820 const Register temp_reg = G3_scratch;
duke@0 1821 Address ic_miss(temp_reg, SharedRuntime::get_ic_miss_stub());
duke@0 1822 __ verify_oop(O0);
duke@0 1823 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
duke@0 1824 __ cmp(temp_reg, G5_inline_cache_reg);
duke@0 1825 __ brx(Assembler::equal, true, Assembler::pt, L);
duke@0 1826 __ delayed()->nop();
duke@0 1827
duke@0 1828 __ jump_to(ic_miss, 0);
duke@0 1829 __ delayed()->nop();
duke@0 1830 __ align(CodeEntryAlignment);
duke@0 1831 __ bind(L);
duke@0 1832 }
duke@0 1833
duke@0 1834 int vep_offset = ((intptr_t)__ pc()) - start;
duke@0 1835
duke@0 1836 #ifdef COMPILER1
duke@0 1837 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@0 1838 // Object.hashCode can pull the hashCode from the header word
duke@0 1839 // instead of doing a full VM transition once it's been computed.
duke@0 1840 // Since hashCode is usually polymorphic at call sites we can't do
duke@0 1841 // this optimization at the call site without a lot of work.
duke@0 1842 Label slowCase;
duke@0 1843 Register receiver = O0;
duke@0 1844 Register result = O0;
duke@0 1845 Register header = G3_scratch;
duke@0 1846 Register hash = G3_scratch; // overwrite header value with hash value
duke@0 1847 Register mask = G1; // to get hash field from header
duke@0 1848
duke@0 1849 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@0 1850 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@0 1851 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@0 1852 // vm: see markOop.hpp.
duke@0 1853 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@0 1854 __ sethi(markOopDesc::hash_mask, mask);
duke@0 1855 __ btst(markOopDesc::unlocked_value, header);
duke@0 1856 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@0 1857 if (UseBiasedLocking) {
duke@0 1858 // Check if biased and fall through to runtime if so
duke@0 1859 __ delayed()->nop();
duke@0 1860 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@0 1861 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@0 1862 }
duke@0 1863 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@0 1864
duke@0 1865 // Check for a valid (non-zero) hash code and get its value.
duke@0 1866 #ifdef _LP64
duke@0 1867 __ srlx(header, markOopDesc::hash_shift, hash);
duke@0 1868 #else
duke@0 1869 __ srl(header, markOopDesc::hash_shift, hash);
duke@0 1870 #endif
duke@0 1871 __ andcc(hash, mask, hash);
duke@0 1872 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@0 1873 __ delayed()->nop();
duke@0 1874
duke@0 1875 // leaf return.
duke@0 1876 __ retl();
duke@0 1877 __ delayed()->mov(hash, result);
duke@0 1878 __ bind(slowCase);
duke@0 1879 }
duke@0 1880 #endif // COMPILER1
duke@0 1881
duke@0 1882
duke@0 1883 // We have received a description of where all the java arg are located
duke@0 1884 // on entry to the wrapper. We need to convert these args to where
duke@0 1885 // the jni function will expect them. To figure out where they go
duke@0 1886 // we convert the java signature to a C signature by inserting
duke@0 1887 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@0 1888
duke@0 1889 int total_c_args = total_in_args + 1;
duke@0 1890 if (method->is_static()) {
duke@0 1891 total_c_args++;
duke@0 1892 }
duke@0 1893
duke@0 1894 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
duke@0 1895 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
duke@0 1896
duke@0 1897 int argc = 0;
duke@0 1898 out_sig_bt[argc++] = T_ADDRESS;
duke@0 1899 if (method->is_static()) {
duke@0 1900 out_sig_bt[argc++] = T_OBJECT;
duke@0 1901 }
duke@0 1902
duke@0 1903 for (int i = 0; i < total_in_args ; i++ ) {
duke@0 1904 out_sig_bt[argc++] = in_sig_bt[i];
duke@0 1905 }
duke@0 1906
duke@0 1907 // Now figure out where the args must be stored and how much stack space
duke@0 1908 // they require (neglecting out_preserve_stack_slots but space for storing
duke@0 1909 // the 1st six register arguments). It's weird see int_stk_helper.
duke@0 1910 //
duke@0 1911 int out_arg_slots;
duke@0 1912 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@0 1913
duke@0 1914 // Compute framesize for the wrapper. We need to handlize all oops in
duke@0 1915 // registers. We must create space for them here that is disjoint from
duke@0 1916 // the windowed save area because we have no control over when we might
duke@0 1917 // flush the window again and overwrite values that gc has since modified.
duke@0 1918 // (The live window race)
duke@0 1919 //
duke@0 1920 // We always just allocate 6 word for storing down these object. This allow
duke@0 1921 // us to simply record the base and use the Ireg number to decide which
duke@0 1922 // slot to use. (Note that the reg number is the inbound number not the
duke@0 1923 // outbound number).
duke@0 1924 // We must shuffle args to match the native convention, and include var-args space.
duke@0 1925
duke@0 1926 // Calculate the total number of stack slots we will need.
duke@0 1927
duke@0 1928 // First count the abi requirement plus all of the outgoing args
duke@0 1929 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@0 1930
duke@0 1931 // Now the space for the inbound oop handle area
duke@0 1932
duke@0 1933 int oop_handle_offset = stack_slots;
duke@0 1934 stack_slots += 6*VMRegImpl::slots_per_word;
duke@0 1935
duke@0 1936 // Now any space we need for handlizing a klass if static method
duke@0 1937
duke@0 1938 int oop_temp_slot_offset = 0;
duke@0 1939 int klass_slot_offset = 0;
duke@0 1940 int klass_offset = -1;
duke@0 1941 int lock_slot_offset = 0;
duke@0 1942 bool is_static = false;
duke@0 1943
duke@0 1944 if (method->is_static()) {
duke@0 1945 klass_slot_offset = stack_slots;
duke@0 1946 stack_slots += VMRegImpl::slots_per_word;
duke@0 1947 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@0 1948 is_static = true;
duke@0 1949 }
duke@0 1950
duke@0 1951 // Plus a lock if needed
duke@0 1952
duke@0 1953 if (method->is_synchronized()) {
duke@0 1954 lock_slot_offset = stack_slots;
duke@0 1955 stack_slots += VMRegImpl::slots_per_word;
duke@0 1956 }
duke@0 1957
duke@0 1958 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@0 1959 stack_slots += 2;
duke@0 1960
duke@0 1961 // Ok The space we have allocated will look like:
duke@0 1962 //
duke@0 1963 //
duke@0 1964 // FP-> | |
duke@0 1965 // |---------------------|
duke@0 1966 // | 2 slots for moves |
duke@0 1967 // |---------------------|
duke@0 1968 // | lock box (if sync) |
duke@0 1969 // |---------------------| <- lock_slot_offset
duke@0 1970 // | klass (if static) |
duke@0 1971 // |---------------------| <- klass_slot_offset
duke@0 1972 // | oopHandle area |
duke@0 1973 // |---------------------| <- oop_handle_offset
duke@0 1974 // | outbound memory |
duke@0 1975 // | based arguments |
duke@0 1976 // | |
duke@0 1977 // |---------------------|
duke@0 1978 // | vararg area |
duke@0 1979 // |---------------------|
duke@0 1980 // | |
duke@0 1981 // SP-> | out_preserved_slots |
duke@0 1982 //
duke@0 1983 //
duke@0 1984
duke@0 1985
duke@0 1986 // Now compute actual number of stack words we need rounding to make
duke@0 1987 // stack properly aligned.
duke@0 1988 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@0 1989
duke@0 1990 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@0 1991
duke@0 1992 // Generate stack overflow check before creating frame
duke@0 1993 __ generate_stack_overflow_check(stack_size);
duke@0 1994
duke@0 1995 // Generate a new frame for the wrapper.
duke@0 1996 __ save(SP, -stack_size, SP);
duke@0 1997
duke@0 1998 int frame_complete = ((intptr_t)__ pc()) - start;
duke@0 1999
duke@0 2000 __ verify_thread();
duke@0 2001
duke@0 2002
duke@0 2003 //
duke@0 2004 // We immediately shuffle the arguments so that any vm call we have to
duke@0 2005 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@0 2006 // captured the oops from our caller and have a valid oopMap for
duke@0 2007 // them.
duke@0 2008
duke@0 2009 // -----------------
duke@0 2010 // The Grand Shuffle
duke@0 2011 //
duke@0 2012 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@0 2013 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@0 2014 // the class mirror instead of a receiver. This pretty much guarantees that
duke@0 2015 // register layout will not match. We ignore these extra arguments during
duke@0 2016 // the shuffle. The shuffle is described by the two calling convention
duke@0 2017 // vectors we have in our possession. We simply walk the java vector to
duke@0 2018 // get the source locations and the c vector to get the destinations.
duke@0 2019 // Because we have a new window and the argument registers are completely
duke@0 2020 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@0 2021 // here.
duke@0 2022
duke@0 2023 // This is a trick. We double the stack slots so we can claim
duke@0 2024 // the oops in the caller's frame. Since we are sure to have
duke@0 2025 // more args than the caller doubling is enough to make
duke@0 2026 // sure we can capture all the incoming oop args from the
duke@0 2027 // caller.
duke@0 2028 //
duke@0 2029 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@0 2030 int c_arg = total_c_args - 1;
duke@0 2031 // Record sp-based slot for receiver on stack for non-static methods
duke@0 2032 int receiver_offset = -1;
duke@0 2033
duke@0 2034 // We move the arguments backward because the floating point registers
duke@0 2035 // destination will always be to a register with a greater or equal register
duke@0 2036 // number or the stack.
duke@0 2037
duke@0 2038 #ifdef ASSERT
duke@0 2039 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@0 2040 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@0 2041 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@0 2042 reg_destroyed[r] = false;
duke@0 2043 }
duke@0 2044 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@0 2045 freg_destroyed[f] = false;
duke@0 2046 }
duke@0 2047
duke@0 2048 #endif /* ASSERT */
duke@0 2049
duke@0 2050 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@0 2051
duke@0 2052 #ifdef ASSERT
duke@0 2053 if (in_regs[i].first()->is_Register()) {
duke@0 2054 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@0 2055 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@0 2056 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@0 2057 }
duke@0 2058 if (out_regs[c_arg].first()->is_Register()) {
duke@0 2059 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@0 2060 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@0 2061 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@0 2062 }
duke@0 2063 #endif /* ASSERT */
duke@0 2064
duke@0 2065 switch (in_sig_bt[i]) {
duke@0 2066 case T_ARRAY:
duke@0 2067 case T_OBJECT:
duke@0 2068 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@0 2069 ((i == 0) && (!is_static)),
duke@0 2070 &receiver_offset);
duke@0 2071 break;
duke@0 2072 case T_VOID:
duke@0 2073 break;
duke@0 2074
duke@0 2075 case T_FLOAT:
duke@0 2076 float_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2077 break;
duke@0 2078
duke@0 2079 case T_DOUBLE:
duke@0 2080 assert( i + 1 < total_in_args &&
duke@0 2081 in_sig_bt[i + 1] == T_VOID &&
duke@0 2082 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@0 2083 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2084 break;
duke@0 2085
duke@0 2086 case T_LONG :
duke@0 2087 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2088 break;
duke@0 2089
duke@0 2090 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@0 2091
duke@0 2092 default:
duke@0 2093 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@0 2094 }
duke@0 2095 }
duke@0 2096
duke@0 2097 // Pre-load a static method's oop into O1. Used both by locking code and
duke@0 2098 // the normal JNI call code.
duke@0 2099 if (method->is_static()) {
duke@0 2100 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@0 2101
duke@0 2102 // Now handlize the static class mirror in O1. It's known not-null.
duke@0 2103 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@0 2104 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@0 2105 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@0 2106 }
duke@0 2107
duke@0 2108
duke@0 2109 const Register L6_handle = L6;
duke@0 2110
duke@0 2111 if (method->is_synchronized()) {
duke@0 2112 __ mov(O1, L6_handle);
duke@0 2113 }
duke@0 2114
duke@0 2115 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@0 2116 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@0 2117 // push a new frame and flush the windows.
duke@0 2118
duke@0 2119 #ifdef _LP64
duke@0 2120 intptr_t thepc = (intptr_t) __ pc();
duke@0 2121 {
duke@0 2122 address here = __ pc();
duke@0 2123 // Call the next instruction
duke@0 2124 __ call(here + 8, relocInfo::none);
duke@0 2125 __ delayed()->nop();
duke@0 2126 }
duke@0 2127 #else
duke@0 2128 intptr_t thepc = __ load_pc_address(O7, 0);
duke@0 2129 #endif /* _LP64 */
duke@0 2130
duke@0 2131 // We use the same pc/oopMap repeatedly when we call out
duke@0 2132 oop_maps->add_gc_map(thepc - start, map);
duke@0 2133
duke@0 2134 // O7 now has the pc loaded that we will use when we finally call to native.
duke@0 2135
duke@0 2136 // Save thread in L7; it crosses a bunch of VM calls below
duke@0 2137 // Don't use save_thread because it smashes G2 and we merely
duke@0 2138 // want to save a copy
duke@0 2139 __ mov(G2_thread, L7_thread_cache);
duke@0 2140
duke@0 2141
duke@0 2142 // If we create an inner frame once is plenty
duke@0 2143 // when we create it we must also save G2_thread
duke@0 2144 bool inner_frame_created = false;
duke@0 2145
duke@0 2146 // dtrace method entry support
duke@0 2147 {
duke@0 2148 SkipIfEqual skip_if(
duke@0 2149 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2150 // create inner frame
duke@0 2151 __ save_frame(0);
duke@0 2152 __ mov(G2_thread, L7_thread_cache);
duke@0 2153 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2154 __ call_VM_leaf(L7_thread_cache,
duke@0 2155 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@0 2156 G2_thread, O1);
duke@0 2157 __ restore();
duke@0 2158 }
duke@0 2159
duke@0 2160 // We are in the jni frame unless saved_frame is true in which case
duke@0 2161 // we are in one frame deeper (the "inner" frame). If we are in the
duke@0 2162 // "inner" frames the args are in the Iregs and if the jni frame then
duke@0 2163 // they are in the Oregs.
duke@0 2164 // If we ever need to go to the VM (for locking, jvmti) then
duke@0 2165 // we will always be in the "inner" frame.
duke@0 2166
duke@0 2167 // Lock a synchronized method
duke@0 2168 int lock_offset = -1; // Set if locked
duke@0 2169 if (method->is_synchronized()) {
duke@0 2170 Register Roop = O1;
duke@0 2171 const Register L3_box = L3;
duke@0 2172
duke@0 2173 create_inner_frame(masm, &inner_frame_created);
duke@0 2174
duke@0 2175 __ ld_ptr(I1, 0, O1);
duke@0 2176 Label done;
duke@0 2177
duke@0 2178 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@0 2179 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2180 #ifdef ASSERT
duke@0 2181 if (UseBiasedLocking) {
duke@0 2182 // making the box point to itself will make it clear it went unused
duke@0 2183 // but also be obviously invalid
duke@0 2184 __ st_ptr(L3_box, L3_box, 0);
duke@0 2185 }
duke@0 2186 #endif // ASSERT
duke@0 2187 //
duke@0 2188 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@0 2189 //
duke@0 2190 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@0 2191 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2192 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2193
duke@0 2194
duke@0 2195 // None of the above fast optimizations worked so we have to get into the
duke@0 2196 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2197 // disallows any pending_exception.
duke@0 2198 __ mov(Roop, O0); // Need oop in O0
duke@0 2199 __ mov(L3_box, O1);
duke@0 2200
duke@0 2201 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@0 2202
duke@0 2203 __ set_last_Java_frame(FP, I7);
duke@0 2204
duke@0 2205 // do the call
duke@0 2206 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@0 2207 __ delayed()->mov(L7_thread_cache, O2);
duke@0 2208
duke@0 2209 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2210 __ reset_last_Java_frame();
duke@0 2211
duke@0 2212 #ifdef ASSERT
duke@0 2213 { Label L;
duke@0 2214 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
duke@0 2215 __ br_null(O0, false, Assembler::pt, L);
duke@0 2216 __ delayed()->nop();
duke@0 2217 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@0 2218 __ bind(L);
duke@0 2219 }
duke@0 2220 #endif
duke@0 2221 __ bind(done);
duke@0 2222 }
duke@0 2223
duke@0 2224
duke@0 2225 // Finally just about ready to make the JNI call
duke@0 2226
duke@0 2227 __ flush_windows();
duke@0 2228 if (inner_frame_created) {
duke@0 2229 __ restore();
duke@0 2230 } else {
duke@0 2231 // Store only what we need from this frame
duke@0 2232 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@0 2233 // either as the flush traps and the current window goes too.
duke@0 2234 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2235 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2236 }
duke@0 2237
duke@0 2238 // get JNIEnv* which is first argument to native
duke@0 2239
duke@0 2240 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
duke@0 2241
duke@0 2242 // Use that pc we placed in O7 a while back as the current frame anchor
duke@0 2243
duke@0 2244 __ set_last_Java_frame(SP, O7);
duke@0 2245
duke@0 2246 // Transition from _thread_in_Java to _thread_in_native.
duke@0 2247 __ set(_thread_in_native, G3_scratch);
duke@0 2248 __ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
duke@0 2249
duke@0 2250 // We flushed the windows ages ago now mark them as flushed
duke@0 2251
duke@0 2252 // mark windows as flushed
duke@0 2253 __ set(JavaFrameAnchor::flushed, G3_scratch);
duke@0 2254
duke@0 2255 Address flags(G2_thread,
duke@0 2256 0,
duke@0 2257 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset()));
duke@0 2258
duke@0 2259 #ifdef _LP64
duke@0 2260 Address dest(O7, method->native_function());
duke@0 2261 __ relocate(relocInfo::runtime_call_type);
duke@0 2262 __ jumpl_to(dest, O7);
duke@0 2263 #else
duke@0 2264 __ call(method->native_function(), relocInfo::runtime_call_type);
duke@0 2265 #endif
duke@0 2266 __ delayed()->st(G3_scratch, flags);
duke@0 2267
duke@0 2268 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2269
duke@0 2270 // Unpack native results. For int-types, we do any needed sign-extension
duke@0 2271 // and move things into I0. The return value there will survive any VM
duke@0 2272 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@0 2273 // specially in the slow-path code.
duke@0 2274 switch (ret_type) {
duke@0 2275 case T_VOID: break; // Nothing to do!
duke@0 2276 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@0 2277 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@0 2278 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@0 2279 case T_LONG:
duke@0 2280 #ifndef _LP64
duke@0 2281 __ mov(O1, I1);
duke@0 2282 #endif
duke@0 2283 // Fall thru
duke@0 2284 case T_OBJECT: // Really a handle
duke@0 2285 case T_ARRAY:
duke@0 2286 case T_INT:
duke@0 2287 __ mov(O0, I0);
duke@0 2288 break;
duke@0 2289 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@0 2290 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@0 2291 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@0 2292 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@0 2293 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@0 2294 default:
duke@0 2295 ShouldNotReachHere();
duke@0 2296 }
duke@0 2297
duke@0 2298 // must we block?
duke@0 2299
duke@0 2300 // Block, if necessary, before resuming in _thread_in_Java state.
duke@0 2301 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@0 2302 { Label no_block;
duke@0 2303 Address sync_state(G3_scratch, SafepointSynchronize::address_of_state());
duke@0 2304
duke@0 2305 // Switch thread to "native transition" state before reading the synchronization state.
duke@0 2306 // This additional state is necessary because reading and testing the synchronization
duke@0 2307 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@0 2308 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@0 2309 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@0 2310 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@0 2311 // didn't see any synchronization is progress, and escapes.
duke@0 2312 __ set(_thread_in_native_trans, G3_scratch);
duke@0 2313 __ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
duke@0 2314 if(os::is_MP()) {
duke@0 2315 if (UseMembar) {
duke@0 2316 // Force this write out before the read below
duke@0 2317 __ membar(Assembler::StoreLoad);
duke@0 2318 } else {
duke@0 2319 // Write serialization page so VM thread can do a pseudo remote membar.
duke@0 2320 // We use the current thread pointer to calculate a thread specific
duke@0 2321 // offset to write to within the page. This minimizes bus traffic
duke@0 2322 // due to cache line collision.
duke@0 2323 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@0 2324 }
duke@0 2325 }
duke@0 2326 __ load_contents(sync_state, G3_scratch);
duke@0 2327 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@0 2328
duke@0 2329 Label L;
duke@0 2330 Address suspend_state(G2_thread, 0, in_bytes(JavaThread::suspend_flags_offset()));
duke@0 2331 __ br(Assembler::notEqual, false, Assembler::pn, L);
duke@0 2332 __ delayed()->
duke@0 2333 ld(suspend_state, G3_scratch);
duke@0 2334 __ cmp(G3_scratch, 0);
duke@0 2335 __ br(Assembler::equal, false, Assembler::pt, no_block);
duke@0 2336 __ delayed()->nop();
duke@0 2337 __ bind(L);
duke@0 2338
duke@0 2339 // Block. Save any potential method result value before the operation and
duke@0 2340 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@0 2341 // lets us share the oopMap we used when we went native rather the create
duke@0 2342 // a distinct one for this pc
duke@0 2343 //
duke@0 2344 save_native_result(masm, ret_type, stack_slots);
duke@0 2345 __ call_VM_leaf(L7_thread_cache,
duke@0 2346 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
duke@0 2347 G2_thread);
duke@0 2348
duke@0 2349 // Restore any method result value
duke@0 2350 restore_native_result(masm, ret_type, stack_slots);
duke@0 2351 __ bind(no_block);
duke@0 2352 }
duke@0 2353
duke@0 2354 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@0 2355 // happened so we can now change state to _thread_in_Java.
duke@0 2356
duke@0 2357
duke@0 2358 __ set(_thread_in_Java, G3_scratch);
duke@0 2359 __ st(G3_scratch, G2_thread, in_bytes(JavaThread::thread_state_offset()));
duke@0 2360
duke@0 2361
duke@0 2362 Label no_reguard;
duke@0 2363 __ ld(G2_thread, in_bytes(JavaThread::stack_guard_state_offset()), G3_scratch);
duke@0 2364 __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
duke@0 2365 __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
duke@0 2366 __ delayed()->nop();
duke@0 2367
duke@0 2368 save_native_result(masm, ret_type, stack_slots);
duke@0 2369 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@0 2370 __ delayed()->nop();
duke@0 2371
duke@0 2372 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2373 restore_native_result(masm, ret_type, stack_slots);
duke@0 2374
duke@0 2375 __ bind(no_reguard);
duke@0 2376
duke@0 2377 // Handle possible exception (will unlock if necessary)
duke@0 2378
duke@0 2379 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@0 2380
duke@0 2381 // Unlock
duke@0 2382 if (method->is_synchronized()) {
duke@0 2383 Label done;
duke@0 2384 Register I2_ex_oop = I2;
duke@0 2385 const Register L3_box = L3;
duke@0 2386 // Get locked oop from the handle we passed to jni
duke@0 2387 __ ld_ptr(L6_handle, 0, L4);
duke@0 2388 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2389 // Must save pending exception around the slow-path VM call. Since it's a
duke@0 2390 // leaf call, the pending exception (if any) can be kept in a register.
duke@0 2391 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@0 2392 // Now unlock
duke@0 2393 // (Roop, Rmark, Rbox, Rscratch)
duke@0 2394 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@0 2395 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2396 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2397
duke@0 2398 // save and restore any potential method result value around the unlocking
duke@0 2399 // operation. Will save in I0 (or stack for FP returns).
duke@0 2400 save_native_result(masm, ret_type, stack_slots);
duke@0 2401
duke@0 2402 // Must clear pending-exception before re-entering the VM. Since this is
duke@0 2403 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@0 2404 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2405
duke@0 2406 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2407 // disallows any pending_exception.
duke@0 2408 __ mov(L3_box, O1);
duke@0 2409
duke@0 2410 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@0 2411 __ delayed()->mov(L4, O0); // Need oop in O0
duke@0 2412
duke@0 2413 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2414
duke@0 2415 #ifdef ASSERT
duke@0 2416 { Label L;
duke@0 2417 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
duke@0 2418 __ br_null(O0, false, Assembler::pt, L);
duke@0 2419 __ delayed()->nop();
duke@0 2420 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@0 2421 __ bind(L);
duke@0 2422 }
duke@0 2423 #endif
duke@0 2424 restore_native_result(masm, ret_type, stack_slots);
duke@0 2425 // check_forward_pending_exception jump to forward_exception if any pending
duke@0 2426 // exception is set. The forward_exception routine expects to see the
duke@0 2427 // exception in pending_exception and not in a register. Kind of clumsy,
duke@0 2428 // since all folks who branch to forward_exception must have tested
duke@0 2429 // pending_exception first and hence have it in a register already.
duke@0 2430 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2431 __ bind(done);
duke@0 2432 }
duke@0 2433
duke@0 2434 // Tell dtrace about this method exit
duke@0 2435 {
duke@0 2436 SkipIfEqual skip_if(
duke@0 2437 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2438 save_native_result(masm, ret_type, stack_slots);
duke@0 2439 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@0 2440 __ call_VM_leaf(L7_thread_cache,
duke@0 2441 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@0 2442 G2_thread, O1);
duke@0 2443 restore_native_result(masm, ret_type, stack_slots);
duke@0 2444 }
duke@0 2445
duke@0 2446 // Clear "last Java frame" SP and PC.
duke@0 2447 __ verify_thread(); // G2_thread must be correct
duke@0 2448 __ reset_last_Java_frame();
duke@0 2449
duke@0 2450 // Unpack oop result
duke@0 2451 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@0 2452 Label L;
duke@0 2453 __ addcc(G0, I0, G0);
duke@0 2454 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@0 2455 __ delayed()->ld_ptr(I0, 0, I0);
duke@0 2456 __ mov(G0, I0);
duke@0 2457 __ bind(L);
duke@0 2458 __ verify_oop(I0);
duke@0 2459 }
duke@0 2460
duke@0 2461 // reset handle block
duke@0 2462 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
duke@0 2463 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
duke@0 2464
duke@0 2465 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
duke@0 2466 check_forward_pending_exception(masm, G3_scratch);
duke@0 2467
duke@0 2468
duke@0 2469 // Return
duke@0 2470
duke@0 2471 #ifndef _LP64
duke@0 2472 if (ret_type == T_LONG) {
duke@0 2473
duke@0 2474 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@0 2475 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 2476 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 2477 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 2478 }
duke@0 2479 #endif
duke@0 2480
duke@0 2481 __ ret();
duke@0 2482 __ delayed()->restore();
duke@0 2483
duke@0 2484 __ flush();
duke@0 2485
duke@0 2486 nmethod *nm = nmethod::new_native_nmethod(method,
duke@0 2487 masm->code(),
duke@0 2488 vep_offset,
duke@0 2489 frame_complete,
duke@0 2490 stack_slots / VMRegImpl::slots_per_word,
duke@0 2491 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@0 2492 in_ByteSize(lock_offset),
duke@0 2493 oop_maps);
duke@0 2494 return nm;
duke@0 2495
duke@0 2496 }
duke@0 2497
duke@0 2498 // this function returns the adjust size (in number of words) to a c2i adapter
duke@0 2499 // activation for use during deoptimization
duke@0 2500 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
duke@0 2501 assert(callee_locals >= callee_parameters,
duke@0 2502 "test and remove; got more parms than locals");
duke@0 2503 if (callee_locals < callee_parameters)
duke@0 2504 return 0; // No adjustment for negative locals
duke@0 2505 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords();
duke@0 2506 return round_to(diff, WordsPerLong);
duke@0 2507 }
duke@0 2508
duke@0 2509 // "Top of Stack" slots that may be unused by the calling convention but must
duke@0 2510 // otherwise be preserved.
duke@0 2511 // On Intel these are not necessary and the value can be zero.
duke@0 2512 // On Sparc this describes the words reserved for storing a register window
duke@0 2513 // when an interrupt occurs.
duke@0 2514 uint SharedRuntime::out_preserve_stack_slots() {
duke@0 2515 return frame::register_save_words * VMRegImpl::slots_per_word;
duke@0 2516 }
duke@0 2517
duke@0 2518 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
duke@0 2519 //
duke@0 2520 // Common out the new frame generation for deopt and uncommon trap
duke@0 2521 //
duke@0 2522 Register G3pcs = G3_scratch; // Array of new pcs (input)
duke@0 2523 Register Oreturn0 = O0;
duke@0 2524 Register Oreturn1 = O1;
duke@0 2525 Register O2UnrollBlock = O2;
duke@0 2526 Register O3array = O3; // Array of frame sizes (input)
duke@0 2527 Register O4array_size = O4; // number of frames (input)
duke@0 2528 Register O7frame_size = O7; // number of frames (input)
duke@0 2529
duke@0 2530 __ ld_ptr(O3array, 0, O7frame_size);
duke@0 2531 __ sub(G0, O7frame_size, O7frame_size);
duke@0 2532 __ save(SP, O7frame_size, SP);
duke@0 2533 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
duke@0 2534
duke@0 2535 #ifdef ASSERT
duke@0 2536 // make sure that the frames are aligned properly
duke@0 2537 #ifndef _LP64
duke@0 2538 __ btst(wordSize*2-1, SP);
duke@0 2539 __ breakpoint_trap(Assembler::notZero);
duke@0 2540 #endif
duke@0 2541 #endif
duke@0 2542
duke@0 2543 // Deopt needs to pass some extra live values from frame to frame
duke@0 2544
duke@0 2545 if (deopt) {
duke@0 2546 __ mov(Oreturn0->after_save(), Oreturn0);
duke@0 2547 __ mov(Oreturn1->after_save(), Oreturn1);
duke@0 2548 }
duke@0 2549
duke@0 2550 __ mov(O4array_size->after_save(), O4array_size);
duke@0 2551 __ sub(O4array_size, 1, O4array_size);
duke@0 2552 __ mov(O3array->after_save(), O3array);
duke@0 2553 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
duke@0 2554 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
duke@0 2555
duke@0 2556 #ifdef ASSERT
duke@0 2557 // trash registers to show a clear pattern in backtraces
duke@0 2558 __ set(0xDEAD0000, I0);
duke@0 2559 __ add(I0, 2, I1);
duke@0 2560 __ add(I0, 4, I2);
duke@0 2561 __ add(I0, 6, I3);
duke@0 2562 __ add(I0, 8, I4);
duke@0 2563 // Don't touch I5 could have valuable savedSP
duke@0 2564 __ set(0xDEADBEEF, L0);
duke@0 2565 __ mov(L0, L1);
duke@0 2566 __ mov(L0, L2);
duke@0 2567 __ mov(L0, L3);
duke@0 2568 __ mov(L0, L4);
duke@0 2569 __ mov(L0, L5);
duke@0 2570
duke@0 2571 // trash the return value as there is nothing to return yet
duke@0 2572 __ set(0xDEAD0001, O7);
duke@0 2573 #endif
duke@0 2574
duke@0 2575 __ mov(SP, O5_savedSP);
duke@0 2576 }
duke@0 2577
duke@0 2578
duke@0 2579 static void make_new_frames(MacroAssembler* masm, bool deopt) {
duke@0 2580 //
duke@0 2581 // loop through the UnrollBlock info and create new frames
duke@0 2582 //
duke@0 2583 Register G3pcs = G3_scratch;
duke@0 2584 Register Oreturn0 = O0;
duke@0 2585 Register Oreturn1 = O1;
duke@0 2586 Register O2UnrollBlock = O2;
duke@0 2587 Register O3array = O3;
duke@0 2588 Register O4array_size = O4;
duke@0 2589 Label loop;
duke@0 2590
duke@0 2591 // Before we make new frames, check to see if stack is available.
duke@0 2592 // Do this after the caller's return address is on top of stack
duke@0 2593 if (UseStackBanging) {
duke@0 2594 // Get total frame size for interpreted frames
duke@0 2595 __ ld(Address(O2UnrollBlock, 0,
duke@0 2596 Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()), O4);
duke@0 2597 __ bang_stack_size(O4, O3, G3_scratch);
duke@0 2598 }
duke@0 2599
duke@0 2600 __ ld(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()), O4array_size);
duke@0 2601 __ ld_ptr(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()), G3pcs);
duke@0 2602
duke@0 2603 __ ld_ptr(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()), O3array);
duke@0 2604
duke@0 2605 // Adjust old interpreter frame to make space for new frame's extra java locals
duke@0 2606 //
duke@0 2607 // We capture the original sp for the transition frame only because it is needed in
duke@0 2608 // order to properly calculate interpreter_sp_adjustment. Even though in real life
duke@0 2609 // every interpreter frame captures a savedSP it is only needed at the transition
duke@0 2610 // (fortunately). If we had to have it correct everywhere then we would need to
duke@0 2611 // be told the sp_adjustment for each frame we create. If the frame size array
duke@0 2612 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
duke@0 2613 // for each frame we create and keep up the illusion every where.
duke@0 2614 //
duke@0 2615
duke@0 2616 __ ld(Address(O2UnrollBlock, 0, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()), O7);
duke@0 2617 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
duke@0 2618 __ sub(SP, O7, SP);
duke@0 2619
duke@0 2620 #ifdef ASSERT
duke@0 2621 // make sure that there is at least one entry in the array
duke@0 2622 __ tst(O4array_size);
duke@0 2623 __ breakpoint_trap(Assembler::zero);
duke@0 2624 #endif
duke@0 2625
duke@0 2626 // Now push the new interpreter frames
duke@0 2627 __ bind(loop);
duke@0 2628
duke@0 2629 // allocate a new frame, filling the registers
duke@0 2630
duke@0 2631 gen_new_frame(masm, deopt); // allocate an interpreter frame
duke@0 2632
duke@0 2633 __ tst(O4array_size);
duke@0 2634 __ br(Assembler::notZero, false, Assembler::pn, loop);
duke@0 2635 __ delayed()->add(O3array, wordSize, O3array);
duke@0 2636 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
duke@0 2637
duke@0 2638 }
duke@0 2639
duke@0 2640 //------------------------------generate_deopt_blob----------------------------
duke@0 2641 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 2642 // instead.
duke@0 2643 void SharedRuntime::generate_deopt_blob() {
duke@0 2644 // allocate space for the code
duke@0 2645 ResourceMark rm;
duke@0 2646 // setup code generation tools
duke@0 2647 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
duke@0 2648 #ifdef _LP64
duke@0 2649 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
duke@0 2650 #else
duke@0 2651 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
duke@0 2652 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
duke@0 2653 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
duke@0 2654 #endif /* _LP64 */
duke@0 2655 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 2656 FloatRegister Freturn0 = F0;
duke@0 2657 Register Greturn1 = G1;
duke@0 2658 Register Oreturn0 = O0;
duke@0 2659 Register Oreturn1 = O1;
duke@0 2660 Register O2UnrollBlock = O2;
duke@0 2661 Register O3tmp = O3;
duke@0 2662 Register I5exception_tmp = I5;
duke@0 2663 Register G4exception_tmp = G4_scratch;
duke@0 2664 int frame_size_words;
duke@0 2665 Address saved_Freturn0_addr(FP, 0, -sizeof(double) + STACK_BIAS);
duke@0 2666 #if !defined(_LP64) && defined(COMPILER2)
duke@0 2667 Address saved_Greturn1_addr(FP, 0, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
duke@0 2668 #endif
duke@0 2669 Label cont;
duke@0 2670
duke@0 2671 OopMapSet *oop_maps = new OopMapSet();
duke@0 2672
duke@0 2673 //
duke@0 2674 // This is the entry point for code which is returning to a de-optimized
duke@0 2675 // frame.
duke@0 2676 // The steps taken by this frame are as follows:
duke@0 2677 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
duke@0 2678 // and all potentially live registers (at a pollpoint many registers can be live).
duke@0 2679 //
duke@0 2680 // - call the C routine: Deoptimization::fetch_unroll_info (this function
duke@0 2681 // returns information about the number and size of interpreter frames
duke@0 2682 // which are equivalent to the frame which is being deoptimized)
duke@0 2683 // - deallocate the unpack frame, restoring only results values. Other
duke@0 2684 // volatile registers will now be captured in the vframeArray as needed.
duke@0 2685 // - deallocate the deoptimization frame
duke@0 2686 // - in a loop using the information returned in the previous step
duke@0 2687 // push new interpreter frames (take care to propagate the return
duke@0 2688 // values through each new frame pushed)
duke@0 2689 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
duke@0 2690 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 2691 // lays out values on the interpreter frame which was just created)
duke@0 2692 // - deallocate the dummy unpack_frame
duke@0 2693 // - ensure that all the return values are correctly set and then do
duke@0 2694 // a return to the interpreter entry point
duke@0 2695 //
duke@0 2696 // Refer to the following methods for more information:
duke@0 2697 // - Deoptimization::fetch_unroll_info
duke@0 2698 // - Deoptimization::unpack_frames
duke@0 2699
duke@0 2700 OopMap* map = NULL;
duke@0 2701
duke@0 2702 int start = __ offset();
duke@0 2703
duke@0 2704 // restore G2, the trampoline destroyed it
duke@0 2705 __ get_thread();
duke@0 2706
duke@0 2707 // On entry we have been called by the deoptimized nmethod with a call that
duke@0 2708 // replaced the original call (or safepoint polling location) so the deoptimizing
duke@0 2709 // pc is now in O7. Return values are still in the expected places
duke@0 2710
duke@0 2711 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 2712 __ ba(false, cont);
duke@0 2713 __ delayed()->mov(Deoptimization::Unpack_deopt, I5exception_tmp);
duke@0 2714
duke@0 2715 int exception_offset = __ offset() - start;
duke@0 2716
duke@0 2717 // restore G2, the trampoline destroyed it
duke@0 2718 __ get_thread();
duke@0 2719
duke@0 2720 // On entry we have been jumped to by the exception handler (or exception_blob
duke@0 2721 // for server). O0 contains the exception oop and O7 contains the original
duke@0 2722 // exception pc. So if we push a frame here it will look to the
duke@0 2723 // stack walking code (fetch_unroll_info) just like a normal call so
duke@0 2724 // state will be extracted normally.
duke@0 2725
duke@0 2726 // save exception oop in JavaThread and fall through into the
duke@0 2727 // exception_in_tls case since they are handled in same way except
duke@0 2728 // for where the pending exception is kept.
duke@0 2729 __ st_ptr(Oexception, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
duke@0 2730
duke@0 2731 //
duke@0 2732 // Vanilla deoptimization with an exception pending in exception_oop
duke@0 2733 //
duke@0 2734 int exception_in_tls_offset = __ offset() - start;
duke@0 2735
duke@0 2736 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 2737 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 2738
duke@0 2739 // Restore G2_thread
duke@0 2740 __ get_thread();
duke@0 2741
duke@0 2742 #ifdef ASSERT
duke@0 2743 {
duke@0 2744 // verify that there is really an exception oop in exception_oop
duke@0 2745 Label has_exception;
duke@0 2746 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
duke@0 2747 __ br_notnull(Oexception, false, Assembler::pt, has_exception);
duke@0 2748 __ delayed()-> nop();
duke@0 2749 __ stop("no exception in thread");
duke@0 2750 __ bind(has_exception);
duke@0 2751
duke@0 2752 // verify that there is no pending exception
duke@0 2753 Label no_pending_exception;
duke@0 2754 Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset()));
duke@0 2755 __ ld_ptr(exception_addr, Oexception);
duke@0 2756 __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
duke@0 2757 __ delayed()->nop();
duke@0 2758 __ stop("must not have pending exception here");
duke@0 2759 __ bind(no_pending_exception);
duke@0 2760 }
duke@0 2761 #endif
duke@0 2762
duke@0 2763 __ ba(false, cont);
duke@0 2764 __ delayed()->mov(Deoptimization::Unpack_exception, I5exception_tmp);;
duke@0 2765
duke@0 2766 //
duke@0 2767 // Reexecute entry, similar to c2 uncommon trap
duke@0 2768 //
duke@0 2769 int reexecute_offset = __ offset() - start;
duke@0 2770
duke@0 2771 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@0 2772 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 2773
duke@0 2774 __ mov(Deoptimization::Unpack_reexecute, I5exception_tmp);
duke@0 2775
duke@0 2776 __ bind(cont);
duke@0 2777
duke@0 2778 __ set_last_Java_frame(SP, noreg);
duke@0 2779
duke@0 2780 // do the call by hand so we can get the oopmap
duke@0 2781
duke@0 2782 __ mov(G2_thread, L7_thread_cache);
duke@0 2783 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
duke@0 2784 __ delayed()->mov(G2_thread, O0);
duke@0 2785
duke@0 2786 // Set an oopmap for the call site this describes all our saved volatile registers
duke@0 2787
duke@0 2788 oop_maps->add_gc_map( __ offset()-start, map);
duke@0 2789
duke@0 2790 __ mov(L7_thread_cache, G2_thread);
duke@0 2791
duke@0 2792 __ reset_last_Java_frame();
duke@0 2793
duke@0 2794 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
duke@0 2795 // so this move will survive
duke@0 2796
duke@0 2797 __ mov(I5exception_tmp, G4exception_tmp);
duke@0 2798
duke@0 2799 __ mov(O0, O2UnrollBlock->after_save());
duke@0 2800
duke@0 2801 RegisterSaver::restore_result_registers(masm);
duke@0 2802
duke@0 2803 Label noException;
duke@0 2804 __ cmp(G4exception_tmp, Deoptimization::Unpack_exception); // Was exception pending?
duke@0 2805 __ br(Assembler::notEqual, false, Assembler::pt, noException);
duke@0 2806 __ delayed()->nop();
duke@0 2807
duke@0 2808 // Move the pending exception from exception_oop to Oexception so
duke@0 2809 // the pending exception will be picked up the interpreter.
duke@0 2810 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
duke@0 2811 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
duke@0 2812 __ bind(noException);
duke@0 2813
duke@0 2814 // deallocate the deoptimization frame taking care to preserve the return values
duke@0 2815 __ mov(Oreturn0, Oreturn0->after_save());
duke@0 2816 __ mov(Oreturn1, Oreturn1->after_save());
duke@0 2817 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 2818 __ restore();
duke@0 2819
duke@0 2820 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 2821
duke@0 2822 make_new_frames(masm, true);
duke@0 2823
duke@0 2824 // push a dummy "unpack_frame" taking care of float return values and
duke@0 2825 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 2826 // information in the interpreter frames just created and then return
duke@0 2827 // to the interpreter entry point
duke@0 2828 __ save(SP, -frame_size_words*wordSize, SP);
duke@0 2829 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
duke@0 2830 #if !defined(_LP64)
duke@0 2831 #if defined(COMPILER2)
duke@0 2832 if (!TieredCompilation) {
duke@0 2833 // 32-bit 1-register longs return longs in G1
duke@0 2834 __ stx(Greturn1, saved_Greturn1_addr);
duke@0 2835 }
duke@0 2836 #endif
duke@0 2837 __ set_last_Java_frame(SP, noreg);
duke@0 2838 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4exception_tmp);
duke@0 2839 #else
duke@0 2840 // LP64 uses g4 in set_last_Java_frame
duke@0 2841 __ mov(G4exception_tmp, O1);
duke@0 2842 __ set_last_Java_frame(SP, G0);
duke@0 2843 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
duke@0 2844 #endif
duke@0 2845 __ reset_last_Java_frame();
duke@0 2846 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
duke@0 2847
duke@0 2848 // In tiered we never use C2 to compile methods returning longs so
duke@0 2849 // the result is where we expect it already.
duke@0 2850
duke@0 2851 #if !defined(_LP64) && defined(COMPILER2)
duke@0 2852 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
duke@0 2853 // I0/I1 if the return value is long. In the tiered world there is
duke@0 2854 // a mismatch between how C1 and C2 return longs compiles and so
duke@0 2855 // currently compilation of methods which return longs is disabled
duke@0 2856 // for C2 and so is this code. Eventually C1 and C2 will do the
duke@0 2857 // same thing for longs in the tiered world.
duke@0 2858 if (!TieredCompilation) {
duke@0 2859 Label not_long;
duke@0 2860 __ cmp(O0,T_LONG);
duke@0 2861 __ br(Assembler::notEqual, false, Assembler::pt, not_long);
duke@0 2862 __ delayed()->nop();
duke@0 2863 __ ldd(saved_Greturn1_addr,I0);
duke@0 2864 __ bind(not_long);
duke@0 2865 }
duke@0 2866 #endif
duke@0 2867 __ ret();
duke@0 2868 __ delayed()->restore();
duke@0 2869
duke@0 2870 masm->flush();
duke@0 2871 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
duke@0 2872 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
duke@0 2873 }
duke@0 2874
duke@0 2875 #ifdef COMPILER2
duke@0 2876
duke@0 2877 //------------------------------generate_uncommon_trap_blob--------------------
duke@0 2878 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@0 2879 // instead.
duke@0 2880 void SharedRuntime::generate_uncommon_trap_blob() {
duke@0 2881 // allocate space for the code
duke@0 2882 ResourceMark rm;
duke@0 2883 // setup code generation tools
duke@0 2884 int pad = VerifyThread ? 512 : 0;
duke@0 2885 #ifdef _LP64
duke@0 2886 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
duke@0 2887 #else
duke@0 2888 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
duke@0 2889 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
duke@0 2890 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
duke@0 2891 #endif
duke@0 2892 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 2893 Register O2UnrollBlock = O2;
duke@0 2894 Register O3tmp = O3;
duke@0 2895 Register O2klass_index = O2;
duke@0 2896
duke@0 2897 //
duke@0 2898 // This is the entry point for all traps the compiler takes when it thinks
duke@0 2899 // it cannot handle further execution of compilation code. The frame is
duke@0 2900 // deoptimized in these cases and converted into interpreter frames for
duke@0 2901 // execution
duke@0 2902 // The steps taken by this frame are as follows:
duke@0 2903 // - push a fake "unpack_frame"
duke@0 2904 // - call the C routine Deoptimization::uncommon_trap (this function
duke@0 2905 // packs the current compiled frame into vframe arrays and returns
duke@0 2906 // information about the number and size of interpreter frames which
duke@0 2907 // are equivalent to the frame which is being deoptimized)
duke@0 2908 // - deallocate the "unpack_frame"
duke@0 2909 // - deallocate the deoptimization frame
duke@0 2910 // - in a loop using the information returned in the previous step
duke@0 2911 // push interpreter frames;
duke@0 2912 // - create a dummy "unpack_frame"
duke@0 2913 // - call the C routine: Deoptimization::unpack_frames (this function
duke@0 2914 // lays out values on the interpreter frame which was just created)
duke@0 2915 // - deallocate the dummy unpack_frame
duke@0 2916 // - return to the interpreter entry point
duke@0 2917 //
duke@0 2918 // Refer to the following methods for more information:
duke@0 2919 // - Deoptimization::uncommon_trap
duke@0 2920 // - Deoptimization::unpack_frame
duke@0 2921
duke@0 2922 // the unloaded class index is in O0 (first parameter to this blob)
duke@0 2923
duke@0 2924 // push a dummy "unpack_frame"
duke@0 2925 // and call Deoptimization::uncommon_trap to pack the compiled frame into
duke@0 2926 // vframe array and return the UnrollBlock information
duke@0 2927 __ save_frame(0);
duke@0 2928 __ set_last_Java_frame(SP, noreg);
duke@0 2929 __ mov(I0, O2klass_index);
duke@0 2930 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
duke@0 2931 __ reset_last_Java_frame();
duke@0 2932 __ mov(O0, O2UnrollBlock->after_save());
duke@0 2933 __ restore();
duke@0 2934
duke@0 2935 // deallocate the deoptimized frame taking care to preserve the return values
duke@0 2936 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@0 2937 __ restore();
duke@0 2938
duke@0 2939 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@0 2940
duke@0 2941 make_new_frames(masm, false);
duke@0 2942
duke@0 2943 // push a dummy "unpack_frame" taking care of float return values and
duke@0 2944 // call Deoptimization::unpack_frames to have the unpacker layout
duke@0 2945 // information in the interpreter frames just created and then return
duke@0 2946 // to the interpreter entry point
duke@0 2947 __ save_frame(0);
duke@0 2948 __ set_last_Java_frame(SP, noreg);
duke@0 2949 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
duke@0 2950 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
duke@0 2951 __ reset_last_Java_frame();
duke@0 2952 __ ret();
duke@0 2953 __ delayed()->restore();
duke@0 2954
duke@0 2955 masm->flush();
duke@0 2956 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
duke@0 2957 }
duke@0 2958
duke@0 2959 #endif // COMPILER2
duke@0 2960
duke@0 2961 //------------------------------generate_handler_blob-------------------
duke@0 2962 //
duke@0 2963 // Generate a special Compile2Runtime blob that saves all registers, and sets
duke@0 2964 // up an OopMap.
duke@0 2965 //
duke@0 2966 // This blob is jumped to (via a breakpoint and the signal handler) from a
duke@0 2967 // safepoint in compiled code. On entry to this blob, O7 contains the
duke@0 2968 // address in the original nmethod at which we should resume normal execution.
duke@0 2969 // Thus, this blob looks like a subroutine which must preserve lots of
duke@0 2970 // registers and return normally. Note that O7 is never register-allocated,
duke@0 2971 // so it is guaranteed to be free here.
duke@0 2972 //
duke@0 2973
duke@0 2974 // The hardest part of what this blob must do is to save the 64-bit %o
duke@0 2975 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
duke@0 2976 // an interrupt will chop off their heads. Making space in the caller's frame
duke@0 2977 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
duke@0 2978 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
duke@0 2979 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
duke@0 2980 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
duke@0 2981 // Tricky, tricky, tricky...
duke@0 2982
duke@0 2983 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
duke@0 2984 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@0 2985
duke@0 2986 // allocate space for the code
duke@0 2987 ResourceMark rm;
duke@0 2988 // setup code generation tools
duke@0 2989 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@0 2990 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@0 2991 // even larger with TraceJumps
duke@0 2992 int pad = TraceJumps ? 512 : 0;
duke@0 2993 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
duke@0 2994 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 2995 int frame_size_words;
duke@0 2996 OopMapSet *oop_maps = new OopMapSet();
duke@0 2997 OopMap* map = NULL;
duke@0 2998
duke@0 2999 int start = __ offset();
duke@0 3000
duke@0 3001 // If this causes a return before the processing, then do a "restore"
duke@0 3002 if (cause_return) {
duke@0 3003 __ restore();
duke@0 3004 } else {
duke@0 3005 // Make it look like we were called via the poll
duke@0 3006 // so that frame constructor always sees a valid return address
duke@0 3007 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
duke@0 3008 __ sub(O7, frame::pc_return_offset, O7);
duke@0 3009 }
duke@0 3010
duke@0 3011 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3012
duke@0 3013 // setup last_Java_sp (blows G4)
duke@0 3014 __ set_last_Java_frame(SP, noreg);
duke@0 3015
duke@0 3016 // call into the runtime to handle illegal instructions exception
duke@0 3017 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
duke@0 3018 __ mov(G2_thread, O0);
duke@0 3019 __ save_thread(L7_thread_cache);
duke@0 3020 __ call(call_ptr);
duke@0 3021 __ delayed()->nop();
duke@0 3022
duke@0 3023 // Set an oopmap for the call site.
duke@0 3024 // We need this not only for callee-saved registers, but also for volatile
duke@0 3025 // registers that the compiler might be keeping live across a safepoint.
duke@0 3026
duke@0 3027 oop_maps->add_gc_map( __ offset() - start, map);
duke@0 3028
duke@0 3029 __ restore_thread(L7_thread_cache);
duke@0 3030 // clear last_Java_sp
duke@0 3031 __ reset_last_Java_frame();
duke@0 3032
duke@0 3033 // Check for exceptions
duke@0 3034 Label pending;
duke@0 3035
duke@0 3036 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
duke@0 3037 __ tst(O1);
duke@0 3038 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
duke@0 3039 __ delayed()->nop();
duke@0 3040
duke@0 3041 RegisterSaver::restore_live_registers(masm);
duke@0 3042
duke@0 3043 // We are back the the original state on entry and ready to go.
duke@0 3044
duke@0 3045 __ retl();
duke@0 3046 __ delayed()->nop();
duke@0 3047
duke@0 3048 // Pending exception after the safepoint
duke@0 3049
duke@0 3050 __ bind(pending);
duke@0 3051
duke@0 3052 RegisterSaver::restore_live_registers(masm);
duke@0 3053
duke@0 3054 // We are back the the original state on entry.
duke@0 3055
duke@0 3056 // Tail-call forward_exception_entry, with the issuing PC in O7,
duke@0 3057 // so it looks like the original nmethod called forward_exception_entry.
duke@0 3058 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
duke@0 3059 __ JMP(O0, 0);
duke@0 3060 __ delayed()->nop();
duke@0 3061
duke@0 3062 // -------------
duke@0 3063 // make sure all code is generated
duke@0 3064 masm->flush();
duke@0 3065
duke@0 3066 // return exception blob
duke@0 3067 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
duke@0 3068 }
duke@0 3069
duke@0 3070 //
duke@0 3071 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
duke@0 3072 //
duke@0 3073 // Generate a stub that calls into vm to find out the proper destination
duke@0 3074 // of a java call. All the argument registers are live at this point
duke@0 3075 // but since this is generic code we don't know what they are and the caller
duke@0 3076 // must do any gc of the args.
duke@0 3077 //
duke@0 3078 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
duke@0 3079 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@0 3080
duke@0 3081 // allocate space for the code
duke@0 3082 ResourceMark rm;
duke@0 3083 // setup code generation tools
duke@0 3084 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@0 3085 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@0 3086 // even larger with TraceJumps
duke@0 3087 int pad = TraceJumps ? 512 : 0;
duke@0 3088 CodeBuffer buffer(name, 1600 + pad, 512);
duke@0 3089 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@0 3090 int frame_size_words;
duke@0 3091 OopMapSet *oop_maps = new OopMapSet();
duke@0 3092 OopMap* map = NULL;
duke@0 3093
duke@0 3094 int start = __ offset();
duke@0 3095
duke@0 3096 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@0 3097
duke@0 3098 int frame_complete = __ offset();
duke@0 3099
duke@0 3100 // setup last_Java_sp (blows G4)
duke@0 3101 __ set_last_Java_frame(SP, noreg);
duke@0 3102
duke@0 3103 // call into the runtime to handle illegal instructions exception
duke@0 3104 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
duke@0 3105 __ mov(G2_thread, O0);
duke@0 3106 __ save_thread(L7_thread_cache);
duke@0 3107 __ call(destination, relocInfo::runtime_call_type);
duke@0 3108 __ delayed()->nop();
duke@0 3109
duke@0 3110 // O0 contains the address we are going to jump to assuming no exception got installed
duke@0 3111
duke@0 3112 // Set an oopmap for the call site.
duke@0 3113 // We need this not only for callee-saved registers, but also for volatile
duke@0 3114 // registers that the compiler might be keeping live across a safepoint.
duke@0 3115
duke@0 3116 oop_maps->add_gc_map( __ offset() - start, map);
duke@0 3117
duke@0 3118 __ restore_thread(L7_thread_cache);
duke@0 3119 // clear last_Java_sp
duke@0 3120 __ reset_last_Java_frame();
duke@0 3121
duke@0 3122 // Check for exceptions
duke@0 3123 Label pending;
duke@0 3124
duke@0 3125 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
duke@0 3126 __ tst(O1);
duke@0 3127 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
duke@0 3128 __ delayed()->nop();
duke@0 3129
duke@0 3130 // get the returned methodOop
duke@0 3131
duke@0 3132 __ get_vm_result(G5_method);
duke@0 3133 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
duke@0 3134
duke@0 3135 // O0 is where we want to jump, overwrite G3 which is saved and scratch
duke@0 3136
duke@0 3137 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
duke@0 3138
duke@0 3139 RegisterSaver::restore_live_registers(masm);
duke@0 3140
duke@0 3141 // We are back the the original state on entry and ready to go.
duke@0 3142
duke@0 3143 __ JMP(G3, 0);
duke@0 3144 __ delayed()->nop();
duke@0 3145
duke@0 3146 // Pending exception after the safepoint
duke@0 3147
duke@0 3148 __ bind(pending);
duke@0 3149
duke@0 3150 RegisterSaver::restore_live_registers(masm);
duke@0 3151
duke@0 3152 // We are back the the original state on entry.
duke@0 3153
duke@0 3154 // Tail-call forward_exception_entry, with the issuing PC in O7,
duke@0 3155 // so it looks like the original nmethod called forward_exception_entry.
duke@0 3156 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
duke@0 3157 __ JMP(O0, 0);
duke@0 3158 __ delayed()->nop();
duke@0 3159
duke@0 3160 // -------------
duke@0 3161 // make sure all code is generated
duke@0 3162 masm->flush();
duke@0 3163
duke@0 3164 // return the blob
duke@0 3165 // frame_size_words or bytes??
duke@0 3166 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
duke@0 3167 }
duke@0 3168
duke@0 3169 void SharedRuntime::generate_stubs() {
duke@0 3170
duke@0 3171 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
duke@0 3172 "wrong_method_stub");
duke@0 3173
duke@0 3174 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
duke@0 3175 "ic_miss_stub");
duke@0 3176
duke@0 3177 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
duke@0 3178 "resolve_opt_virtual_call");
duke@0 3179
duke@0 3180 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
duke@0 3181 "resolve_virtual_call");
duke@0 3182
duke@0 3183 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
duke@0 3184 "resolve_static_call");
duke@0 3185
duke@0 3186 _polling_page_safepoint_handler_blob =
duke@0 3187 generate_handler_blob(CAST_FROM_FN_PTR(address,
duke@0 3188 SafepointSynchronize::handle_polling_page_exception), false);
duke@0 3189
duke@0 3190 _polling_page_return_handler_blob =
duke@0 3191 generate_handler_blob(CAST_FROM_FN_PTR(address,
duke@0 3192 SafepointSynchronize::handle_polling_page_exception), true);
duke@0 3193
duke@0 3194 generate_deopt_blob();
duke@0 3195
duke@0 3196 #ifdef COMPILER2
duke@0 3197 generate_uncommon_trap_blob();
duke@0 3198 #endif // COMPILER2
duke@0 3199 }