annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 3601:da91efe96a93

6964458: Reimplement class meta-data storage to use native memory Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
author coleenp
date Sat, 01 Sep 2012 13:25:18 -0400
parents 1d7922586cf6
children 8a02ca5e5576
rev   line source
duke@0 1 /*
never@3064 2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1489 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1489 20 * or visit www.oracle.com if you need additional information or have any
trims@1489 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1869 25 #include "precompiled.hpp"
stefank@1869 26 #include "asm/assembler.hpp"
stefank@1869 27 #include "assembler_sparc.inline.hpp"
stefank@1869 28 #include "code/debugInfoRec.hpp"
stefank@1869 29 #include "code/icBuffer.hpp"
stefank@1869 30 #include "code/vtableStubs.hpp"
stefank@1869 31 #include "interpreter/interpreter.hpp"
coleenp@3601 32 #include "oops/compiledICHolder.hpp"
stefank@1869 33 #include "prims/jvmtiRedefineClassesTrace.hpp"
stefank@1869 34 #include "runtime/sharedRuntime.hpp"
stefank@1869 35 #include "runtime/vframeArray.hpp"
stefank@1869 36 #include "vmreg_sparc.inline.hpp"
stefank@1869 37 #ifdef COMPILER1
stefank@1869 38 #include "c1/c1_Runtime1.hpp"
stefank@1869 39 #endif
stefank@1869 40 #ifdef COMPILER2
stefank@1869 41 #include "opto/runtime.hpp"
stefank@1869 42 #endif
stefank@1869 43 #ifdef SHARK
stefank@1869 44 #include "compiler/compileBroker.hpp"
stefank@1869 45 #include "shark/sharkCompiler.hpp"
stefank@1869 46 #endif
duke@0 47
duke@0 48 #define __ masm->
duke@0 49
duke@0 50
duke@0 51 class RegisterSaver {
duke@0 52
duke@0 53 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@0 54 // The Oregs are problematic. In the 32bit build the compiler can
duke@0 55 // have O registers live with 64 bit quantities. A window save will
duke@0 56 // cut the heads off of the registers. We have to do a very extensive
duke@0 57 // stack dance to save and restore these properly.
duke@0 58
duke@0 59 // Note that the Oregs problem only exists if we block at either a polling
duke@0 60 // page exception a compiled code safepoint that was not originally a call
duke@0 61 // or deoptimize following one of these kinds of safepoints.
duke@0 62
duke@0 63 // Lots of registers to save. For all builds, a window save will preserve
duke@0 64 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@0 65 // builds a window-save will preserve the %o registers. In the LION build
duke@0 66 // we need to save the 64-bit %o registers which requires we save them
duke@0 67 // before the window-save (as then they become %i registers and get their
duke@0 68 // heads chopped off on interrupt). We have to save some %g registers here
duke@0 69 // as well.
duke@0 70 enum {
duke@0 71 // This frame's save area. Includes extra space for the native call:
duke@0 72 // vararg's layout space and the like. Briefly holds the caller's
duke@0 73 // register save area.
duke@0 74 call_args_area = frame::register_save_words_sp_offset +
duke@0 75 frame::memory_parameter_word_sp_offset*wordSize,
duke@0 76 // Make sure save locations are always 8 byte aligned.
duke@0 77 // can't use round_to because it doesn't produce compile time constant
duke@0 78 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@0 79 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@0 80 g3_offset = g1_offset+8,
duke@0 81 g4_offset = g3_offset+8,
duke@0 82 g5_offset = g4_offset+8,
duke@0 83 o0_offset = g5_offset+8,
duke@0 84 o1_offset = o0_offset+8,
duke@0 85 o2_offset = o1_offset+8,
duke@0 86 o3_offset = o2_offset+8,
duke@0 87 o4_offset = o3_offset+8,
duke@0 88 o5_offset = o4_offset+8,
duke@0 89 start_of_flags_save_area = o5_offset+8,
duke@0 90 ccr_offset = start_of_flags_save_area,
duke@0 91 fsr_offset = ccr_offset + 8,
duke@0 92 d00_offset = fsr_offset+8, // Start of float save area
duke@0 93 register_save_size = d00_offset+8*32
duke@0 94 };
duke@0 95
duke@0 96
duke@0 97 public:
duke@0 98
duke@0 99 static int Oexception_offset() { return o0_offset; };
duke@0 100 static int G3_offset() { return g3_offset; };
duke@0 101 static int G5_offset() { return g5_offset; };
duke@0 102 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@0 103 static void restore_live_registers(MacroAssembler* masm);
duke@0 104
duke@0 105 // During deoptimization only the result register need to be restored
duke@0 106 // all the other values have already been extracted.
duke@0 107
duke@0 108 static void restore_result_registers(MacroAssembler* masm);
duke@0 109 };
duke@0 110
duke@0 111 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@0 112 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@0 113 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@0 114 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@0 115 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@0 116 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@0 117 int i;
kvn@992 118 // Always make the frame size 16 byte aligned.
duke@0 119 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@0 120 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@0 121 int frame_size_in_slots = frame_size / sizeof(jint);
duke@0 122 // CodeBlob frame size is in words.
duke@0 123 *total_frame_words = frame_size / wordSize;
duke@0 124 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@0 125 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@0 126
duke@0 127 #if !defined(_LP64)
duke@0 128
duke@0 129 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@0 130 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 131 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 132 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 133 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 134 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 135 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 136 #endif /* _LP64 */
duke@0 137
duke@0 138 __ save(SP, -frame_size, SP);
duke@0 139
duke@0 140 #ifndef _LP64
duke@0 141 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@0 142 // to Oregs here to avoid interrupts cutting off their heads
duke@0 143
duke@0 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 150
duke@0 151 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@0 152 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@0 153
duke@0 154 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@0 155
duke@0 156 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@0 157
duke@0 158 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@0 159 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@0 160
duke@0 161 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@0 162 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@0 163
duke@0 164 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@0 165 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@0 166
duke@0 167 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@0 168 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@0 169 #endif /* _LP64 */
duke@0 170
coleenp@108 171
coleenp@108 172 #ifdef _LP64
coleenp@108 173 int debug_offset = 0;
coleenp@108 174 #else
coleenp@108 175 int debug_offset = 4;
coleenp@108 176 #endif
duke@0 177 // Save the G's
duke@0 178 __ stx(G1, SP, g1_offset+STACK_BIAS);
coleenp@108 179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
duke@0 180
duke@0 181 __ stx(G3, SP, g3_offset+STACK_BIAS);
coleenp@108 182 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
duke@0 183
duke@0 184 __ stx(G4, SP, g4_offset+STACK_BIAS);
coleenp@108 185 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
duke@0 186
duke@0 187 __ stx(G5, SP, g5_offset+STACK_BIAS);
coleenp@108 188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
duke@0 189
duke@0 190 // This is really a waste but we'll keep things as they were for now
duke@0 191 if (true) {
duke@0 192 #ifndef _LP64
duke@0 193 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@0 194 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@0 195 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@0 196 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@0 197 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@0 198 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@0 199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@0 200 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@0 201 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@0 202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
coleenp@108 203 #endif /* _LP64 */
duke@0 204 }
duke@0 205
duke@0 206
duke@0 207 // Save the flags
duke@0 208 __ rdccr( G5 );
duke@0 209 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@0 210 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 211
kvn@992 212 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
duke@0 213 int offset = d00_offset;
kvn@992 214 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 215 FloatRegister f = as_FloatRegister(i);
duke@0 216 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
kvn@992 217 // Record as callee saved both halves of double registers (2 float registers).
duke@0 218 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
kvn@992 219 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@0 220 offset += sizeof(double);
duke@0 221 }
duke@0 222
duke@0 223 // And we're done.
duke@0 224
duke@0 225 return map;
duke@0 226 }
duke@0 227
duke@0 228
duke@0 229 // Pop the current frame and restore all the registers that we
duke@0 230 // saved.
duke@0 231 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@0 232
duke@0 233 // Restore all the FP registers
kvn@992 234 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@0 235 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@0 236 }
duke@0 237
duke@0 238 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@0 239 __ wrccr (G1) ;
duke@0 240
duke@0 241 // Restore the G's
duke@0 242 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@0 243 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@0 244
duke@0 245 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 246 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@0 247 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@0 248 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@0 249
duke@0 250
duke@0 251 #if !defined(_LP64)
duke@0 252 // Restore the 64-bit O's.
duke@0 253 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 254 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 255 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@0 256 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@0 257 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@0 258 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@0 259
duke@0 260 // And temporarily place them in TLS
duke@0 261
duke@0 262 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 263 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 264 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@0 265 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@0 266 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@0 267 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@0 268 #endif /* _LP64 */
duke@0 269
duke@0 270 // Restore flags
duke@0 271
duke@0 272 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@0 273
duke@0 274 __ restore();
duke@0 275
duke@0 276 #if !defined(_LP64)
duke@0 277 // Now reload the 64bit Oregs after we've restore the window.
duke@0 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@0 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@0 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@0 283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@0 284 #endif /* _LP64 */
duke@0 285
duke@0 286 }
duke@0 287
duke@0 288 // Pop the current frame and restore the registers that might be holding
duke@0 289 // a result.
duke@0 290 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@0 291
duke@0 292 #if !defined(_LP64)
duke@0 293 // 32bit build returns longs in G1
duke@0 294 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@0 295
duke@0 296 // Retrieve the 64-bit O's.
duke@0 297 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@0 298 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@0 299 // and save to TLS
duke@0 300 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@0 301 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@0 302 #endif /* _LP64 */
duke@0 303
duke@0 304 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@0 305
duke@0 306 __ restore();
duke@0 307
duke@0 308 #if !defined(_LP64)
duke@0 309 // Now reload the 64bit Oregs after we've restore the window.
duke@0 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@0 311 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@0 312 #endif /* _LP64 */
duke@0 313
duke@0 314 }
duke@0 315
duke@0 316 // The java_calling_convention describes stack locations as ideal slots on
duke@0 317 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@0 318 // (like the placement of the register window) the slots must be biased by
duke@0 319 // the following value.
duke@0 320 static int reg2offset(VMReg r) {
duke@0 321 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@0 322 }
duke@0 323
never@3064 324 static VMRegPair reg64_to_VMRegPair(Register r) {
never@3064 325 VMRegPair ret;
never@3064 326 if (wordSize == 8) {
never@3064 327 ret.set2(r->as_VMReg());
never@3064 328 } else {
never@3064 329 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
never@3064 330 }
never@3064 331 return ret;
never@3064 332 }
never@3064 333
duke@0 334 // ---------------------------------------------------------------------------
duke@0 335 // Read the array of BasicTypes from a signature, and compute where the
duke@0 336 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@0 337 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@0 338 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@0 339 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@0 340 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@0 341 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@0 342 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@0 343 // Each 32-bit quantity is given its own number, so the integer registers
duke@0 344 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@0 345 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@0 346
duke@0 347 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@0 348 // convert to incoming arguments, convert all O's to I's. The regs array
duke@0 349 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@0 350 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@0 351 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@0 352 // passed (used as a placeholder for the other half of longs and doubles in
duke@0 353 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@0 354 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@0 355 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@0 356 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@0 357 // same VMRegPair.
duke@0 358
duke@0 359 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@0 360 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@0 361 // units regardless of build.
duke@0 362
duke@0 363
duke@0 364 // ---------------------------------------------------------------------------
duke@0 365 // The compiled Java calling convention. The Java convention always passes
duke@0 366 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@0 367 // floats in float registers and doubles in aligned float pairs. Values are
duke@0 368 // packed in the registers. There is no backing varargs store for values in
duke@0 369 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@0 370 // passed in I's, because longs in I's get their heads chopped off at
duke@0 371 // interrupt).
duke@0 372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@0 373 VMRegPair *regs,
duke@0 374 int total_args_passed,
duke@0 375 int is_outgoing) {
duke@0 376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@0 377
duke@0 378 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@0 379 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@0 380 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@0 381 // align. Then put longs and doubles into the same registers as they fit,
duke@0 382 // else spill to the stack.
duke@0 383 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@0 384 const int flt_reg_max = 8;
duke@0 385 //
duke@0 386 // Where 32-bit 1-reg longs start being passed
duke@0 387 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@0 388 // So make it look like we've filled all the G regs that c2 wants to use.
duke@0 389 Register g_reg = TieredCompilation ? noreg : G1;
duke@0 390
duke@0 391 // Count int/oop and float args. See how many stack slots we'll need and
duke@0 392 // where the longs & doubles will go.
duke@0 393 int int_reg_cnt = 0;
duke@0 394 int flt_reg_cnt = 0;
duke@0 395 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@0 396 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@0 397 int stk_reg_pairs = 0;
duke@0 398 for (int i = 0; i < total_args_passed; i++) {
duke@0 399 switch (sig_bt[i]) {
duke@0 400 case T_LONG: // LP64, longs compete with int args
duke@0 401 assert(sig_bt[i+1] == T_VOID, "");
duke@0 402 #ifdef _LP64
twisti@3534 403 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 404 #endif
duke@0 405 break;
duke@0 406 case T_OBJECT:
duke@0 407 case T_ARRAY:
duke@0 408 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
twisti@3534 409 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 410 #ifndef _LP64
duke@0 411 else stk_reg_pairs++;
duke@0 412 #endif
duke@0 413 break;
duke@0 414 case T_INT:
duke@0 415 case T_SHORT:
duke@0 416 case T_CHAR:
duke@0 417 case T_BYTE:
duke@0 418 case T_BOOLEAN:
twisti@3534 419 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@0 420 else stk_reg_pairs++;
duke@0 421 break;
duke@0 422 case T_FLOAT:
twisti@3534 423 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@0 424 else stk_reg_pairs++;
duke@0 425 break;
duke@0 426 case T_DOUBLE:
duke@0 427 assert(sig_bt[i+1] == T_VOID, "");
duke@0 428 break;
duke@0 429 case T_VOID:
duke@0 430 break;
duke@0 431 default:
duke@0 432 ShouldNotReachHere();
duke@0 433 }
duke@0 434 }
duke@0 435
duke@0 436 // This is where the longs/doubles start on the stack.
duke@0 437 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@0 438
duke@0 439 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@0 440
duke@0 441 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@0 442 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@0 443 int stk_reg = 0;
duke@0 444 int int_reg = 0;
duke@0 445 int flt_reg = 0;
duke@0 446
duke@0 447 // Now do the signature layout
duke@0 448 for (int i = 0; i < total_args_passed; i++) {
duke@0 449 switch (sig_bt[i]) {
duke@0 450 case T_INT:
duke@0 451 case T_SHORT:
duke@0 452 case T_CHAR:
duke@0 453 case T_BYTE:
duke@0 454 case T_BOOLEAN:
duke@0 455 #ifndef _LP64
duke@0 456 case T_OBJECT:
duke@0 457 case T_ARRAY:
duke@0 458 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 459 #endif // _LP64
duke@0 460 if (int_reg < int_reg_max) {
duke@0 461 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 462 regs[i].set1(r->as_VMReg());
duke@0 463 } else {
duke@0 464 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 465 }
duke@0 466 break;
duke@0 467
duke@0 468 #ifdef _LP64
duke@0 469 case T_OBJECT:
duke@0 470 case T_ARRAY:
duke@0 471 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@0 472 if (int_reg < int_reg_max) {
duke@0 473 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 474 regs[i].set2(r->as_VMReg());
duke@0 475 } else {
duke@0 476 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 477 stk_reg_pairs += 2;
duke@0 478 }
duke@0 479 break;
duke@0 480 #endif // _LP64
duke@0 481
duke@0 482 case T_LONG:
duke@0 483 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@0 484 #ifdef _LP64
duke@0 485 if (int_reg < int_reg_max) {
duke@0 486 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@0 487 regs[i].set2(r->as_VMReg());
duke@0 488 } else {
duke@0 489 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 490 stk_reg_pairs += 2;
duke@0 491 }
duke@0 492 #else
never@297 493 #ifdef COMPILER2
duke@0 494 // For 32-bit build, can't pass longs in O-regs because they become
duke@0 495 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@0 496 // spare and available. This convention isn't used by the Sparc ABI or
duke@0 497 // anywhere else. If we're tiered then we don't use G-regs because c1
never@297 498 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
duke@0 499 // G0: zero
duke@0 500 // G1: 1st Long arg
duke@0 501 // G2: global allocated to TLS
duke@0 502 // G3: used in inline cache check
duke@0 503 // G4: 2nd Long arg
duke@0 504 // G5: used in inline cache check
duke@0 505 // G6: used by OS
duke@0 506 // G7: used by OS
duke@0 507
duke@0 508 if (g_reg == G1) {
duke@0 509 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@0 510 g_reg = G4; // Where the next arg goes
duke@0 511 } else if (g_reg == G4) {
duke@0 512 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@0 513 g_reg = noreg; // No more longs in registers
duke@0 514 } else {
duke@0 515 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 516 stk_reg_pairs += 2;
duke@0 517 }
duke@0 518 #else // COMPILER2
duke@0 519 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 520 stk_reg_pairs += 2;
duke@0 521 #endif // COMPILER2
never@297 522 #endif // _LP64
duke@0 523 break;
duke@0 524
duke@0 525 case T_FLOAT:
duke@0 526 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
twisti@3534 527 else regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@0 528 break;
duke@0 529 case T_DOUBLE:
duke@0 530 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@0 531 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@0 532 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@0 533 flt_reg_pairs += 2;
duke@0 534 } else {
duke@0 535 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@0 536 stk_reg_pairs += 2;
duke@0 537 }
duke@0 538 break;
duke@0 539 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@0 540 default:
duke@0 541 ShouldNotReachHere();
duke@0 542 }
duke@0 543 }
duke@0 544
duke@0 545 // retun the amount of stack space these arguments will need.
duke@0 546 return stk_reg_pairs;
duke@0 547
duke@0 548 }
duke@0 549
twisti@991 550 // Helper class mostly to avoid passing masm everywhere, and handle
twisti@991 551 // store displacement overflow logic.
duke@0 552 class AdapterGenerator {
duke@0 553 MacroAssembler *masm;
duke@0 554 Register Rdisp;
duke@0 555 void set_Rdisp(Register r) { Rdisp = r; }
duke@0 556
duke@0 557 void patch_callers_callsite();
duke@0 558
duke@0 559 // base+st_off points to top of argument
twisti@1401 560 int arg_offset(const int st_off) { return st_off; }
duke@0 561 int next_arg_offset(const int st_off) {
twisti@1401 562 return st_off - Interpreter::stackElementSize;
twisti@991 563 }
twisti@991 564
twisti@991 565 // Argument slot values may be loaded first into a register because
twisti@991 566 // they might not fit into displacement.
twisti@991 567 RegisterOrConstant arg_slot(const int st_off);
twisti@991 568 RegisterOrConstant next_arg_slot(const int st_off);
twisti@991 569
duke@0 570 // Stores long into offset pointed to by base
duke@0 571 void store_c2i_long(Register r, Register base,
duke@0 572 const int st_off, bool is_stack);
duke@0 573 void store_c2i_object(Register r, Register base,
duke@0 574 const int st_off);
duke@0 575 void store_c2i_int(Register r, Register base,
duke@0 576 const int st_off);
duke@0 577 void store_c2i_double(VMReg r_2,
duke@0 578 VMReg r_1, Register base, const int st_off);
duke@0 579 void store_c2i_float(FloatRegister f, Register base,
duke@0 580 const int st_off);
duke@0 581
duke@0 582 public:
duke@0 583 void gen_c2i_adapter(int total_args_passed,
duke@0 584 // VMReg max_arg,
duke@0 585 int comp_args_on_stack, // VMRegStackSlots
duke@0 586 const BasicType *sig_bt,
duke@0 587 const VMRegPair *regs,
duke@0 588 Label& skip_fixup);
duke@0 589 void gen_i2c_adapter(int total_args_passed,
duke@0 590 // VMReg max_arg,
duke@0 591 int comp_args_on_stack, // VMRegStackSlots
duke@0 592 const BasicType *sig_bt,
duke@0 593 const VMRegPair *regs);
duke@0 594
duke@0 595 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@0 596 };
duke@0 597
duke@0 598
duke@0 599 // Patch the callers callsite with entry to compiled code if it exists.
duke@0 600 void AdapterGenerator::patch_callers_callsite() {
duke@0 601 Label L;
coleenp@3601 602 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
kvn@2600 603 __ br_null(G3_scratch, false, Assembler::pt, L);
duke@0 604 // Schedule the branch target address early.
coleenp@3601 605 __ delayed()->ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
duke@0 606 // Call into the VM to patch the caller, then jump to compiled callee
duke@0 607 __ save_frame(4); // Args in compiled layout; do not blow them
duke@0 608
duke@0 609 // Must save all the live Gregs the list is:
duke@0 610 // G1: 1st Long arg (32bit build)
duke@0 611 // G2: global allocated to TLS
duke@0 612 // G3: used in inline cache check (scratch)
duke@0 613 // G4: 2nd Long arg (32bit build);
coleenp@3601 614 // G5: used in inline cache check (Method*)
duke@0 615
duke@0 616 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@0 617
duke@0 618 #ifdef _LP64
duke@0 619 // mov(s,d)
duke@0 620 __ mov(G1, L1);
duke@0 621 __ mov(G4, L4);
duke@0 622 __ mov(G5_method, L5);
duke@0 623 __ mov(G5_method, O0); // VM needs target method
duke@0 624 __ mov(I7, O1); // VM needs caller's callsite
duke@0 625 // Must be a leaf call...
duke@0 626 // can be very far once the blob has been relocated
twisti@720 627 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@0 628 __ relocate(relocInfo::runtime_call_type);
twisti@720 629 __ jumpl_to(dest, O7, O7);
duke@0 630 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 631 __ mov(L7_thread_cache, G2_thread);
duke@0 632 __ mov(L1, G1);
duke@0 633 __ mov(L4, G4);
duke@0 634 __ mov(L5, G5_method);
duke@0 635 #else
duke@0 636 __ stx(G1, FP, -8 + STACK_BIAS);
duke@0 637 __ stx(G4, FP, -16 + STACK_BIAS);
duke@0 638 __ mov(G5_method, L5);
duke@0 639 __ mov(G5_method, O0); // VM needs target method
duke@0 640 __ mov(I7, O1); // VM needs caller's callsite
duke@0 641 // Must be a leaf call...
duke@0 642 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@0 643 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@0 644 __ mov(L7_thread_cache, G2_thread);
duke@0 645 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@0 646 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@0 647 __ mov(L5, G5_method);
coleenp@3601 648 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
duke@0 649 #endif /* _LP64 */
duke@0 650
duke@0 651 __ restore(); // Restore args
duke@0 652 __ bind(L);
duke@0 653 }
duke@0 654
twisti@991 655
twisti@991 656 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
twisti@991 657 RegisterOrConstant roc(arg_offset(st_off));
twisti@991 658 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 659 }
duke@0 660
twisti@991 661 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
twisti@991 662 RegisterOrConstant roc(next_arg_offset(st_off));
twisti@991 663 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@0 664 }
twisti@991 665
twisti@991 666
duke@0 667 // Stores long into offset pointed to by base
duke@0 668 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@0 669 const int st_off, bool is_stack) {
duke@0 670 #ifdef _LP64
duke@0 671 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 672 // data is passed in only 1 slot.
duke@0 673 __ stx(r, base, next_arg_slot(st_off));
duke@0 674 #else
ysr@344 675 #ifdef COMPILER2
duke@0 676 // Misaligned store of 64-bit data
duke@0 677 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 678 __ srlx(r, 32, r);
duke@0 679 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 680 #else
duke@0 681 if (is_stack) {
duke@0 682 // Misaligned store of 64-bit data
duke@0 683 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@0 684 __ srlx(r, 32, r);
duke@0 685 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@0 686 } else {
duke@0 687 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@0 688 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@0 689 }
duke@0 690 #endif // COMPILER2
ysr@344 691 #endif // _LP64
duke@0 692 }
duke@0 693
duke@0 694 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@0 695 const int st_off) {
duke@0 696 __ st_ptr (r, base, arg_slot(st_off));
duke@0 697 }
duke@0 698
duke@0 699 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@0 700 const int st_off) {
duke@0 701 __ st (r, base, arg_slot(st_off));
duke@0 702 }
duke@0 703
duke@0 704 // Stores into offset pointed to by base
duke@0 705 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@0 706 VMReg r_1, Register base, const int st_off) {
duke@0 707 #ifdef _LP64
duke@0 708 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 709 // data is passed in only 1 slot.
duke@0 710 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 711 #else
duke@0 712 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 713 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@0 714 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@0 715 #endif
duke@0 716 }
duke@0 717
duke@0 718 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@0 719 const int st_off) {
duke@0 720 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@0 721 }
duke@0 722
duke@0 723 void AdapterGenerator::gen_c2i_adapter(
duke@0 724 int total_args_passed,
duke@0 725 // VMReg max_arg,
duke@0 726 int comp_args_on_stack, // VMRegStackSlots
duke@0 727 const BasicType *sig_bt,
duke@0 728 const VMRegPair *regs,
duke@0 729 Label& skip_fixup) {
duke@0 730
duke@0 731 // Before we get into the guts of the C2I adapter, see if we should be here
duke@0 732 // at all. We've come from compiled code and are attempting to jump to the
duke@0 733 // interpreter, which means the caller made a static call to get here
duke@0 734 // (vcalls always get a compiled target if there is one). Check for a
duke@0 735 // compiled target. If there is one, we need to patch the caller's call.
duke@0 736 // However we will run interpreted if we come thru here. The next pass
duke@0 737 // thru the call site will run compiled. If we ran compiled here then
duke@0 738 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@0 739 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@0 740 // we can have at most one and don't need to play any tricks to keep
duke@0 741 // from endlessly growing the stack.
duke@0 742 //
duke@0 743 // Actually if we detected that we had an i2c->c2i transition here we
duke@0 744 // ought to be able to reset the world back to the state of the interpreted
duke@0 745 // call and not bother building another interpreter arg area. We don't
duke@0 746 // do that at this point.
duke@0 747
duke@0 748 patch_callers_callsite();
duke@0 749
duke@0 750 __ bind(skip_fixup);
duke@0 751
duke@0 752 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@0 753 // space we need. Add in varargs area needed by the interpreter. Round up
duke@0 754 // to stack alignment.
twisti@1401 755 const int arg_size = total_args_passed * Interpreter::stackElementSize;
duke@0 756 const int varargs_area =
duke@0 757 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@0 758 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@0 759
duke@0 760 int bias = STACK_BIAS;
duke@0 761 const int interp_arg_offset = frame::varargs_offset*wordSize +
twisti@1401 762 (total_args_passed-1)*Interpreter::stackElementSize;
duke@0 763
duke@0 764 Register base = SP;
duke@0 765
duke@0 766 #ifdef _LP64
duke@0 767 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@0 768 // out of bits in the displacement to do loads and stores. Use g3 as
duke@0 769 // temporary displacement.
twisti@2872 770 if (!Assembler::is_simm13(extraspace)) {
duke@0 771 __ set(extraspace, G3_scratch);
duke@0 772 __ sub(SP, G3_scratch, SP);
duke@0 773 } else {
duke@0 774 __ sub(SP, extraspace, SP);
duke@0 775 }
duke@0 776 set_Rdisp(G3_scratch);
duke@0 777 #else
duke@0 778 __ sub(SP, extraspace, SP);
duke@0 779 #endif // _LP64
duke@0 780
duke@0 781 // First write G1 (if used) to where ever it must go
duke@0 782 for (int i=0; i<total_args_passed; i++) {
twisti@1401 783 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 784 VMReg r_1 = regs[i].first();
duke@0 785 VMReg r_2 = regs[i].second();
duke@0 786 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 787 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 788 store_c2i_object(G1_scratch, base, st_off);
duke@0 789 } else if (sig_bt[i] == T_LONG) {
duke@0 790 assert(!TieredCompilation, "should not use register args for longs");
duke@0 791 store_c2i_long(G1_scratch, base, st_off, false);
duke@0 792 } else {
duke@0 793 store_c2i_int(G1_scratch, base, st_off);
duke@0 794 }
duke@0 795 }
duke@0 796 }
duke@0 797
duke@0 798 // Now write the args into the outgoing interpreter space
duke@0 799 for (int i=0; i<total_args_passed; i++) {
twisti@1401 800 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@0 801 VMReg r_1 = regs[i].first();
duke@0 802 VMReg r_2 = regs[i].second();
duke@0 803 if (!r_1->is_valid()) {
duke@0 804 assert(!r_2->is_valid(), "");
duke@0 805 continue;
duke@0 806 }
duke@0 807 // Skip G1 if found as we did it first in order to free it up
duke@0 808 if (r_1 == G1_scratch->as_VMReg()) {
duke@0 809 continue;
duke@0 810 }
duke@0 811 #ifdef ASSERT
duke@0 812 bool G1_forced = false;
duke@0 813 #endif // ASSERT
duke@0 814 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@0 815 #ifdef _LP64
duke@0 816 Register ld_off = Rdisp;
duke@0 817 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@0 818 #else
duke@0 819 int ld_off = reg2offset(r_1) + extraspace + bias;
kvn@1209 820 #endif // _LP64
duke@0 821 #ifdef ASSERT
duke@0 822 G1_forced = true;
duke@0 823 #endif // ASSERT
duke@0 824 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@0 825 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@0 826 else __ ldx(base, ld_off, G1_scratch);
duke@0 827 }
duke@0 828
duke@0 829 if (r_1->is_Register()) {
duke@0 830 Register r = r_1->as_Register()->after_restore();
duke@0 831 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@0 832 store_c2i_object(r, base, st_off);
duke@0 833 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
kvn@1209 834 #ifndef _LP64
duke@0 835 if (TieredCompilation) {
duke@0 836 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@0 837 }
kvn@1209 838 #endif // _LP64
duke@0 839 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@0 840 } else {
duke@0 841 store_c2i_int(r, base, st_off);
duke@0 842 }
duke@0 843 } else {
duke@0 844 assert(r_1->is_FloatRegister(), "");
duke@0 845 if (sig_bt[i] == T_FLOAT) {
duke@0 846 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@0 847 } else {
duke@0 848 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@0 849 store_c2i_double(r_2, r_1, base, st_off);
duke@0 850 }
duke@0 851 }
duke@0 852 }
duke@0 853
duke@0 854 #ifdef _LP64
duke@0 855 // Need to reload G3_scratch, used for temporary displacements.
coleenp@3601 856 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
duke@0 857
duke@0 858 // Pass O5_savedSP as an argument to the interpreter.
duke@0 859 // The interpreter will restore SP to this value before returning.
duke@0 860 __ set(extraspace, G1);
duke@0 861 __ add(SP, G1, O5_savedSP);
duke@0 862 #else
duke@0 863 // Pass O5_savedSP as an argument to the interpreter.
duke@0 864 // The interpreter will restore SP to this value before returning.
duke@0 865 __ add(SP, extraspace, O5_savedSP);
duke@0 866 #endif // _LP64
duke@0 867
duke@0 868 __ mov((frame::varargs_offset)*wordSize -
twisti@1401 869 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
duke@0 870 // Jump to the interpreter just as if interpreter was doing it.
duke@0 871 __ jmpl(G3_scratch, 0, G0);
duke@0 872 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@0 873 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@0 874 // the interpreter does not know where its args are without some kind of
duke@0 875 // arg pointer being passed in. Pass it in Gargs.
duke@0 876 __ delayed()->add(SP, G1, Gargs);
duke@0 877 }
duke@0 878
twisti@3534 879 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg,
twisti@3534 880 address code_start, address code_end,
twisti@3534 881 Label& L_ok) {
twisti@3534 882 Label L_fail;
twisti@3534 883 __ set(ExternalAddress(code_start), temp_reg);
twisti@3534 884 __ set(pointer_delta(code_end, code_start, 1), temp2_reg);
twisti@3534 885 __ cmp(pc_reg, temp_reg);
twisti@3534 886 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail);
twisti@3534 887 __ delayed()->add(temp_reg, temp2_reg, temp_reg);
twisti@3534 888 __ cmp(pc_reg, temp_reg);
twisti@3534 889 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok);
twisti@3534 890 __ bind(L_fail);
twisti@3534 891 }
twisti@3534 892
duke@0 893 void AdapterGenerator::gen_i2c_adapter(
duke@0 894 int total_args_passed,
duke@0 895 // VMReg max_arg,
duke@0 896 int comp_args_on_stack, // VMRegStackSlots
duke@0 897 const BasicType *sig_bt,
duke@0 898 const VMRegPair *regs) {
duke@0 899
duke@0 900 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@0 901 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@0 902 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@0 903 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@0 904 // hoist register arguments and repack other args according to the compiled
duke@0 905 // code convention. Finally, end in a jump to the compiled code. The entry
duke@0 906 // point address is the start of the buffer.
duke@0 907
duke@0 908 // We will only enter here from an interpreted frame and never from after
duke@0 909 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@0 910 // race and use a c2i we will remain interpreted for the race loser(s).
duke@0 911 // This removes all sorts of headaches on the x86 side and also eliminates
duke@0 912 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@0 913
twisti@3534 914 // More detail:
twisti@3534 915 // Adapters can be frameless because they do not require the caller
twisti@3534 916 // to perform additional cleanup work, such as correcting the stack pointer.
twisti@3534 917 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
twisti@3534 918 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
twisti@3534 919 // even if a callee has modified the stack pointer.
twisti@3534 920 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
twisti@3534 921 // routinely repairs its caller's stack pointer (from sender_sp, which is set
twisti@3534 922 // up via the senderSP register).
twisti@3534 923 // In other words, if *either* the caller or callee is interpreted, we can
twisti@3534 924 // get the stack pointer repaired after a call.
twisti@3534 925 // This is why c2i and i2c adapters cannot be indefinitely composed.
twisti@3534 926 // In particular, if a c2i adapter were to somehow call an i2c adapter,
twisti@3534 927 // both caller and callee would be compiled methods, and neither would
twisti@3534 928 // clean up the stack pointer changes performed by the two adapters.
twisti@3534 929 // If this happens, control eventually transfers back to the compiled
twisti@3534 930 // caller, but with an uncorrected stack, causing delayed havoc.
twisti@3534 931
twisti@3534 932 if (VerifyAdapterCalls &&
twisti@3534 933 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
twisti@3534 934 // So, let's test for cascading c2i/i2c adapters right now.
twisti@3534 935 // assert(Interpreter::contains($return_addr) ||
twisti@3534 936 // StubRoutines::contains($return_addr),
twisti@3534 937 // "i2c adapter must return to an interpreter frame");
twisti@3534 938 __ block_comment("verify_i2c { ");
twisti@3534 939 Label L_ok;
twisti@3534 940 if (Interpreter::code() != NULL)
twisti@3534 941 range_check(masm, O7, O0, O1,
twisti@3534 942 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
twisti@3534 943 L_ok);
twisti@3534 944 if (StubRoutines::code1() != NULL)
twisti@3534 945 range_check(masm, O7, O0, O1,
twisti@3534 946 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
twisti@3534 947 L_ok);
twisti@3534 948 if (StubRoutines::code2() != NULL)
twisti@3534 949 range_check(masm, O7, O0, O1,
twisti@3534 950 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
twisti@3534 951 L_ok);
twisti@3534 952 const char* msg = "i2c adapter must return to an interpreter frame";
twisti@3534 953 __ block_comment(msg);
twisti@3534 954 __ stop(msg);
twisti@3534 955 __ bind(L_ok);
twisti@3534 956 __ block_comment("} verify_i2ce ");
twisti@3534 957 }
twisti@3534 958
duke@0 959 // As you can see from the list of inputs & outputs there are not a lot
duke@0 960 // of temp registers to work with: mostly G1, G3 & G4.
duke@0 961
duke@0 962 // Inputs:
duke@0 963 // G2_thread - TLS
duke@0 964 // G5_method - Method oop
jrose@689 965 // G4 (Gargs) - Pointer to interpreter's args
jrose@689 966 // O0..O4 - free for scratch
jrose@689 967 // O5_savedSP - Caller's saved SP, to be restored if needed
duke@0 968 // O6 - Current SP!
duke@0 969 // O7 - Valid return address
jrose@689 970 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 971
duke@0 972 // Outputs:
duke@0 973 // G2_thread - TLS
duke@0 974 // G1, G4 - Outgoing long args in 32-bit build
duke@0 975 // O0-O5 - Outgoing args in compiled layout
duke@0 976 // O6 - Adjusted or restored SP
duke@0 977 // O7 - Valid return address
twisti@1457 978 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@0 979 // F0-F7 - more outgoing args
duke@0 980
duke@0 981
jrose@689 982 // Gargs is the incoming argument base, and also an outgoing argument.
duke@0 983 __ sub(Gargs, BytesPerWord, Gargs);
duke@0 984
duke@0 985 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@0 986 // WITH O7 HOLDING A VALID RETURN PC
duke@0 987 //
duke@0 988 // | |
duke@0 989 // : java stack :
duke@0 990 // | |
duke@0 991 // +--------------+ <--- start of outgoing args
duke@0 992 // | receiver | |
duke@0 993 // : rest of args : |---size is java-arg-words
duke@0 994 // | | |
duke@0 995 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@0 996 // | | |
duke@0 997 // : unused : |---Space for max Java stack, plus stack alignment
duke@0 998 // | | |
duke@0 999 // +--------------+ <--- SP + 16*wordsize
duke@0 1000 // | |
duke@0 1001 // : window :
duke@0 1002 // | |
duke@0 1003 // +--------------+ <--- SP
duke@0 1004
duke@0 1005 // WE REPACK THE STACK. We use the common calling convention layout as
duke@0 1006 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@0 1007 // causes an arbitrary shuffle of memory, which may require some register
duke@0 1008 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@0 1009 // temps are not needed. We may have to resize the stack slightly, in case
duke@0 1010 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@0 1011 // misaligned, but the compilers expect them aligned).
duke@0 1012 //
duke@0 1013 // | |
duke@0 1014 // : java stack :
duke@0 1015 // | |
duke@0 1016 // +--------------+ <--- start of outgoing args
duke@0 1017 // | pad, align | |
duke@0 1018 // +--------------+ |
duke@0 1019 // | ints, floats | |---Outgoing stack args, packed low.
duke@0 1020 // +--------------+ | First few args in registers.
duke@0 1021 // : doubles : |
duke@0 1022 // | longs | |
duke@0 1023 // +--------------+ <--- SP' + 16*wordsize
duke@0 1024 // | |
duke@0 1025 // : window :
duke@0 1026 // | |
duke@0 1027 // +--------------+ <--- SP'
duke@0 1028
duke@0 1029 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@0 1030 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@0 1031 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@0 1032
duke@0 1033 // Cut-out for having no stack args. Since up to 6 args are passed
duke@0 1034 // in registers, we will commonly have no stack args.
duke@0 1035 if (comp_args_on_stack > 0) {
duke@0 1036
duke@0 1037 // Convert VMReg stack slots to words.
duke@0 1038 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@0 1039 // Round up to miminum stack alignment, in wordSize
duke@0 1040 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@0 1041 // Now compute the distance from Lesp to SP. This calculation does not
duke@0 1042 // include the space for total_args_passed because Lesp has not yet popped
duke@0 1043 // the arguments.
duke@0 1044 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@0 1045 }
duke@0 1046
duke@0 1047 // Will jump to the compiled code just as if compiled code was doing it.
duke@0 1048 // Pre-load the register-jump target early, to schedule it better.
coleenp@3601 1049 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3);
duke@0 1050
duke@0 1051 // Now generate the shuffle code. Pick up all register args and move the
duke@0 1052 // rest through G1_scratch.
duke@0 1053 for (int i=0; i<total_args_passed; i++) {
duke@0 1054 if (sig_bt[i] == T_VOID) {
duke@0 1055 // Longs and doubles are passed in native word order, but misaligned
duke@0 1056 // in the 32-bit build.
duke@0 1057 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@0 1058 continue;
duke@0 1059 }
duke@0 1060
duke@0 1061 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@0 1062 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@0 1063 // ldx/lddf optimizations.
duke@0 1064
duke@0 1065 // Load in argument order going down.
twisti@1401 1066 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1067 set_Rdisp(G1_scratch);
duke@0 1068
duke@0 1069 VMReg r_1 = regs[i].first();
duke@0 1070 VMReg r_2 = regs[i].second();
duke@0 1071 if (!r_1->is_valid()) {
duke@0 1072 assert(!r_2->is_valid(), "");
duke@0 1073 continue;
duke@0 1074 }
duke@0 1075 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@0 1076 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@0 1077 if (r_2->is_valid()) r_2 = r_1->next();
duke@0 1078 }
duke@0 1079 if (r_1->is_Register()) { // Register argument
duke@0 1080 Register r = r_1->as_Register()->after_restore();
duke@0 1081 if (!r_2->is_valid()) {
duke@0 1082 __ ld(Gargs, arg_slot(ld_off), r);
duke@0 1083 } else {
duke@0 1084 #ifdef _LP64
duke@0 1085 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@0 1086 // data is passed in only 1 slot.
twisti@991 1087 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
duke@0 1088 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1089 __ ldx(Gargs, slot, r);
duke@0 1090 #else
duke@0 1091 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@0 1092 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@0 1093 #endif
duke@0 1094 }
duke@0 1095 } else {
duke@0 1096 assert(r_1->is_FloatRegister(), "");
duke@0 1097 if (!r_2->is_valid()) {
duke@0 1098 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1099 } else {
duke@0 1100 #ifdef _LP64
duke@0 1101 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@0 1102 // data is passed in only 1 slot. This code also handles longs that
duke@0 1103 // are passed on the stack, but need a stack-to-stack move through a
duke@0 1104 // spare float register.
twisti@991 1105 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@0 1106 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@0 1107 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@0 1108 #else
duke@0 1109 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1110 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@0 1111 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@0 1112 #endif
duke@0 1113 }
duke@0 1114 }
duke@0 1115 // Was the argument really intended to be on the stack, but was loaded
duke@0 1116 // into F8/F9?
duke@0 1117 if (regs[i].first()->is_stack()) {
duke@0 1118 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@0 1119 // Convert stack slot to an SP offset
duke@0 1120 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@0 1121 // Store down the shuffled stack word. Target address _is_ aligned.
twisti@991 1122 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
twisti@991 1123 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
twisti@991 1124 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
duke@0 1125 }
duke@0 1126 }
duke@0 1127 bool made_space = false;
duke@0 1128 #ifndef _LP64
duke@0 1129 // May need to pick up a few long args in G1/G4
duke@0 1130 bool g4_crushed = false;
duke@0 1131 bool g3_crushed = false;
duke@0 1132 for (int i=0; i<total_args_passed; i++) {
duke@0 1133 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@0 1134 // Load in argument order going down
twisti@1401 1135 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@0 1136 // Need to marshal 64-bit value from misaligned Lesp loads
duke@0 1137 Register r = regs[i].first()->as_Register()->after_restore();
duke@0 1138 if (r == G1 || r == G4) {
duke@0 1139 assert(!g4_crushed, "ordering problem");
duke@0 1140 if (r == G4){
duke@0 1141 g4_crushed = true;
duke@0 1142 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1143 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1144 } else {
duke@0 1145 // better schedule this way
duke@0 1146 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1147 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@0 1148 }
duke@0 1149 g3_crushed = true;
duke@0 1150 __ sllx(r, 32, r);
duke@0 1151 __ or3(G3_scratch, r, r);
duke@0 1152 } else {
duke@0 1153 assert(r->is_out(), "longs passed in two O registers");
duke@0 1154 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@0 1155 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@0 1156 }
duke@0 1157 }
duke@0 1158 }
duke@0 1159 #endif
duke@0 1160
duke@0 1161 // Jump to the compiled code just as if compiled code was doing it.
duke@0 1162 //
duke@0 1163 #ifndef _LP64
duke@0 1164 if (g3_crushed) {
duke@0 1165 // Rats load was wasted, at least it is in cache...
coleenp@3601 1166 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3);
duke@0 1167 }
duke@0 1168 #endif /* _LP64 */
duke@0 1169
duke@0 1170 // 6243940 We might end up in handle_wrong_method if
duke@0 1171 // the callee is deoptimized as we race thru here. If that
duke@0 1172 // happens we don't want to take a safepoint because the
duke@0 1173 // caller frame will look interpreted and arguments are now
duke@0 1174 // "compiled" so it is much better to make this transition
duke@0 1175 // invisible to the stack walking code. Unfortunately if
duke@0 1176 // we try and find the callee by normal means a safepoint
duke@0 1177 // is possible. So we stash the desired callee in the thread
duke@0 1178 // and the vm will find there should this case occur.
twisti@720 1179 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
duke@0 1180 __ st_ptr(G5_method, callee_target_addr);
duke@0 1181
duke@0 1182 if (StressNonEntrant) {
duke@0 1183 // Open a big window for deopt failure
duke@0 1184 __ save_frame(0);
duke@0 1185 __ mov(G0, L0);
duke@0 1186 Label loop;
duke@0 1187 __ bind(loop);
duke@0 1188 __ sub(L0, 1, L0);
kvn@2600 1189 __ br_null_short(L0, Assembler::pt, loop);
duke@0 1190
duke@0 1191 __ restore();
duke@0 1192 }
duke@0 1193
duke@0 1194
duke@0 1195 __ jmpl(G3, 0, G0);
duke@0 1196 __ delayed()->nop();
duke@0 1197 }
duke@0 1198
duke@0 1199 // ---------------------------------------------------------------
duke@0 1200 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@0 1201 int total_args_passed,
duke@0 1202 // VMReg max_arg,
duke@0 1203 int comp_args_on_stack, // VMRegStackSlots
duke@0 1204 const BasicType *sig_bt,
never@1179 1205 const VMRegPair *regs,
never@1179 1206 AdapterFingerPrint* fingerprint) {
duke@0 1207 address i2c_entry = __ pc();
duke@0 1208
duke@0 1209 AdapterGenerator agen(masm);
duke@0 1210
duke@0 1211 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@0 1212
duke@0 1213
duke@0 1214 // -------------------------------------------------------------------------
coleenp@3601 1215 // Generate a C2I adapter. On entry we know G5 holds the Method*. The
duke@0 1216 // args start out packed in the compiled layout. They need to be unpacked
duke@0 1217 // into the interpreter layout. This will almost always require some stack
duke@0 1218 // space. We grow the current (compiled) stack, then repack the args. We
duke@0 1219 // finally end in a jump to the generic interpreter entry point. On exit
duke@0 1220 // from the interpreter, the interpreter will restore our SP (lest the
duke@0 1221 // compiled code, which relys solely on SP and not FP, get sick).
duke@0 1222
duke@0 1223 address c2i_unverified_entry = __ pc();
duke@0 1224 Label skip_fixup;
duke@0 1225 {
duke@0 1226 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1227 Register R_temp = L0; // another scratch register
duke@0 1228 #else
duke@0 1229 Register R_temp = G1; // another scratch register
duke@0 1230 #endif
duke@0 1231
twisti@720 1232 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 1233
duke@0 1234 __ verify_oop(O0);
coleenp@108 1235 __ load_klass(O0, G3_scratch);
duke@0 1236
duke@0 1237 #if !defined(_LP64) && defined(COMPILER2)
duke@0 1238 __ save(SP, -frame::register_save_words*wordSize, SP);
coleenp@3601 1239 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp);
duke@0 1240 __ cmp(G3_scratch, R_temp);
duke@0 1241 __ restore();
duke@0 1242 #else
coleenp@3601 1243 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp);
duke@0 1244 __ cmp(G3_scratch, R_temp);
duke@0 1245 #endif
duke@0 1246
duke@0 1247 Label ok, ok2;
duke@0 1248 __ brx(Assembler::equal, false, Assembler::pt, ok);
coleenp@3601 1249 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method);
twisti@720 1250 __ jump_to(ic_miss, G3_scratch);
duke@0 1251 __ delayed()->nop();
duke@0 1252
duke@0 1253 __ bind(ok);
duke@0 1254 // Method might have been compiled since the call site was patched to
duke@0 1255 // interpreted if that is the case treat it as a miss so we can get
duke@0 1256 // the call site corrected.
coleenp@3601 1257 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch);
duke@0 1258 __ bind(ok2);
kvn@2600 1259 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup);
coleenp@3601 1260 __ delayed()->ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch);
twisti@720 1261 __ jump_to(ic_miss, G3_scratch);
duke@0 1262 __ delayed()->nop();
duke@0 1263
duke@0 1264 }
duke@0 1265
duke@0 1266 address c2i_entry = __ pc();
duke@0 1267
duke@0 1268 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@0 1269
duke@0 1270 __ flush();
never@1179 1271 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
duke@0 1272
duke@0 1273 }
duke@0 1274
duke@0 1275 // Helper function for native calling conventions
duke@0 1276 static VMReg int_stk_helper( int i ) {
duke@0 1277 // Bias any stack based VMReg we get by ignoring the window area
duke@0 1278 // but not the register parameter save area.
duke@0 1279 //
duke@0 1280 // This is strange for the following reasons. We'd normally expect
duke@0 1281 // the calling convention to return an VMReg for a stack slot
duke@0 1282 // completely ignoring any abi reserved area. C2 thinks of that
duke@0 1283 // abi area as only out_preserve_stack_slots. This does not include
duke@0 1284 // the area allocated by the C abi to store down integer arguments
duke@0 1285 // because the java calling convention does not use it. So
duke@0 1286 // since c2 assumes that there are only out_preserve_stack_slots
duke@0 1287 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@0 1288 // location the c calling convention must add in this bias amount
duke@0 1289 // to make up for the fact that the out_preserve_stack_slots is
duke@0 1290 // insufficient for C calls. What a mess. I sure hope those 6
duke@0 1291 // stack words were worth it on every java call!
duke@0 1292
duke@0 1293 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@0 1294 // to take a parameter to say whether it was C or java calling conventions.
duke@0 1295 // Then things might look a little better (but not much).
duke@0 1296
duke@0 1297 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@0 1298 if( mem_parm_offset < 0 ) {
duke@0 1299 return as_oRegister(i)->as_VMReg();
duke@0 1300 } else {
duke@0 1301 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@0 1302 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@0 1303 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@0 1304 }
duke@0 1305 }
duke@0 1306
duke@0 1307
duke@0 1308 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@0 1309 VMRegPair *regs,
duke@0 1310 int total_args_passed) {
duke@0 1311
duke@0 1312 // Return the number of VMReg stack_slots needed for the args.
duke@0 1313 // This value does not include an abi space (like register window
duke@0 1314 // save area).
duke@0 1315
duke@0 1316 // The native convention is V8 if !LP64
duke@0 1317 // The LP64 convention is the V9 convention which is slightly more sane.
duke@0 1318
duke@0 1319 // We return the amount of VMReg stack slots we need to reserve for all
duke@0 1320 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@0 1321 // have space for storing at least 6 registers to memory we start with that.
duke@0 1322 // See int_stk_helper for a further discussion.
duke@0 1323 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@0 1324
duke@0 1325 #ifdef _LP64
duke@0 1326 // V9 convention: All things "as-if" on double-wide stack slots.
duke@0 1327 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@0 1328 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@0 1329 int j = 0; // Count of actual args, not HALVES
duke@0 1330 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@0 1331 switch( sig_bt[i] ) {
duke@0 1332 case T_BOOLEAN:
duke@0 1333 case T_BYTE:
duke@0 1334 case T_CHAR:
duke@0 1335 case T_INT:
duke@0 1336 case T_SHORT:
duke@0 1337 regs[i].set1( int_stk_helper( j ) ); break;
duke@0 1338 case T_LONG:
duke@0 1339 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1340 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1341 case T_ARRAY:
duke@0 1342 case T_OBJECT:
duke@0 1343 regs[i].set2( int_stk_helper( j ) );
duke@0 1344 break;
duke@0 1345 case T_FLOAT:
duke@0 1346 if ( j < 16 ) {
duke@0 1347 // V9ism: floats go in ODD registers
duke@0 1348 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@0 1349 } else {
duke@0 1350 // V9ism: floats go in ODD stack slot
duke@0 1351 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@0 1352 }
duke@0 1353 break;
duke@0 1354 case T_DOUBLE:
duke@0 1355 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1356 if ( j < 16 ) {
duke@0 1357 // V9ism: doubles go in EVEN/ODD regs
duke@0 1358 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@0 1359 } else {
duke@0 1360 // V9ism: doubles go in EVEN/ODD stack slots
duke@0 1361 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@0 1362 }
duke@0 1363 break;
duke@0 1364 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@0 1365 default:
duke@0 1366 ShouldNotReachHere();
duke@0 1367 }
duke@0 1368 if (regs[i].first()->is_stack()) {
duke@0 1369 int off = regs[i].first()->reg2stack();
duke@0 1370 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1371 }
duke@0 1372 if (regs[i].second()->is_stack()) {
duke@0 1373 int off = regs[i].second()->reg2stack();
duke@0 1374 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1375 }
duke@0 1376 }
duke@0 1377
duke@0 1378 #else // _LP64
duke@0 1379 // V8 convention: first 6 things in O-regs, rest on stack.
duke@0 1380 // Alignment is willy-nilly.
duke@0 1381 for( int i=0; i<total_args_passed; i++ ) {
duke@0 1382 switch( sig_bt[i] ) {
duke@0 1383 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@0 1384 case T_ARRAY:
duke@0 1385 case T_BOOLEAN:
duke@0 1386 case T_BYTE:
duke@0 1387 case T_CHAR:
duke@0 1388 case T_FLOAT:
duke@0 1389 case T_INT:
duke@0 1390 case T_OBJECT:
duke@0 1391 case T_SHORT:
duke@0 1392 regs[i].set1( int_stk_helper( i ) );
duke@0 1393 break;
duke@0 1394 case T_DOUBLE:
duke@0 1395 case T_LONG:
duke@0 1396 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@0 1397 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@0 1398 break;
duke@0 1399 case T_VOID: regs[i].set_bad(); break;
duke@0 1400 default:
duke@0 1401 ShouldNotReachHere();
duke@0 1402 }
duke@0 1403 if (regs[i].first()->is_stack()) {
duke@0 1404 int off = regs[i].first()->reg2stack();
duke@0 1405 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1406 }
duke@0 1407 if (regs[i].second()->is_stack()) {
duke@0 1408 int off = regs[i].second()->reg2stack();
duke@0 1409 if (off > max_stack_slots) max_stack_slots = off;
duke@0 1410 }
duke@0 1411 }
duke@0 1412 #endif // _LP64
duke@0 1413
duke@0 1414 return round_to(max_stack_slots + 1, 2);
duke@0 1415
duke@0 1416 }
duke@0 1417
duke@0 1418
duke@0 1419 // ---------------------------------------------------------------------------
duke@0 1420 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1421 switch (ret_type) {
duke@0 1422 case T_FLOAT:
duke@0 1423 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@0 1424 break;
duke@0 1425 case T_DOUBLE:
duke@0 1426 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@0 1427 break;
duke@0 1428 }
duke@0 1429 }
duke@0 1430
duke@0 1431 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@0 1432 switch (ret_type) {
duke@0 1433 case T_FLOAT:
duke@0 1434 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@0 1435 break;
duke@0 1436 case T_DOUBLE:
duke@0 1437 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@0 1438 break;
duke@0 1439 }
duke@0 1440 }
duke@0 1441
duke@0 1442 // Check and forward and pending exception. Thread is stored in
duke@0 1443 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@0 1444 // is no exception handler. We merely pop this frame off and throw the
duke@0 1445 // exception in the caller's frame.
duke@0 1446 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@0 1447 Label L;
duke@0 1448 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@0 1449 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@0 1450 // Since this is a native call, we *know* the proper exception handler
duke@0 1451 // without calling into the VM: it's the empty function. Just pop this
duke@0 1452 // frame and then jump to forward_exception_entry; O7 will contain the
duke@0 1453 // native caller's return PC.
twisti@720 1454 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
twisti@720 1455 __ jump_to(exception_entry, G3_scratch);
duke@0 1456 __ delayed()->restore(); // Pop this frame off.
duke@0 1457 __ bind(L);
duke@0 1458 }
duke@0 1459
duke@0 1460 // A simple move of integer like type
duke@0 1461 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1462 if (src.first()->is_stack()) {
duke@0 1463 if (dst.first()->is_stack()) {
duke@0 1464 // stack to stack
duke@0 1465 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1466 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1467 } else {
duke@0 1468 // stack to reg
duke@0 1469 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1470 }
duke@0 1471 } else if (dst.first()->is_stack()) {
duke@0 1472 // reg to stack
duke@0 1473 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1474 } else {
duke@0 1475 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1476 }
duke@0 1477 }
duke@0 1478
duke@0 1479 // On 64 bit we will store integer like items to the stack as
duke@0 1480 // 64 bits items (sparc abi) even though java would only store
duke@0 1481 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@0 1482 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@0 1483 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1484 if (src.first()->is_stack()) {
duke@0 1485 if (dst.first()->is_stack()) {
duke@0 1486 // stack to stack
duke@0 1487 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1488 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1489 } else {
duke@0 1490 // stack to reg
duke@0 1491 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1492 }
duke@0 1493 } else if (dst.first()->is_stack()) {
duke@0 1494 // reg to stack
duke@0 1495 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1496 } else {
duke@0 1497 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1498 }
duke@0 1499 }
duke@0 1500
duke@0 1501
never@3064 1502 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
never@3064 1503 if (src.first()->is_stack()) {
never@3064 1504 if (dst.first()->is_stack()) {
never@3064 1505 // stack to stack
never@3064 1506 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5);
never@3064 1507 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
never@3064 1508 } else {
never@3064 1509 // stack to reg
never@3064 1510 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
never@3064 1511 }
never@3064 1512 } else if (dst.first()->is_stack()) {
never@3064 1513 // reg to stack
never@3064 1514 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
never@3064 1515 } else {
never@3064 1516 __ mov(src.first()->as_Register(), dst.first()->as_Register());
never@3064 1517 }
never@3064 1518 }
never@3064 1519
never@3064 1520
duke@0 1521 // An oop arg. Must pass a handle not the oop itself
duke@0 1522 static void object_move(MacroAssembler* masm,
duke@0 1523 OopMap* map,
duke@0 1524 int oop_handle_offset,
duke@0 1525 int framesize_in_slots,
duke@0 1526 VMRegPair src,
duke@0 1527 VMRegPair dst,
duke@0 1528 bool is_receiver,
duke@0 1529 int* receiver_offset) {
duke@0 1530
duke@0 1531 // must pass a handle. First figure out the location we use as a handle
duke@0 1532
duke@0 1533 if (src.first()->is_stack()) {
duke@0 1534 // Oop is already on the stack
duke@0 1535 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@0 1536 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@0 1537 __ ld_ptr(rHandle, 0, L4);
duke@0 1538 #ifdef _LP64
duke@0 1539 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@0 1540 #else
duke@0 1541 __ tst( L4 );
duke@0 1542 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1543 #endif
duke@0 1544 if (dst.first()->is_stack()) {
duke@0 1545 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1546 }
duke@0 1547 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@0 1548 if (is_receiver) {
duke@0 1549 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@0 1550 }
duke@0 1551 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@0 1552 } else {
duke@0 1553 // Oop is in an input register pass we must flush it to the stack
duke@0 1554 const Register rOop = src.first()->as_Register();
duke@0 1555 const Register rHandle = L5;
duke@0 1556 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@0 1557 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@0 1558 Label skip;
duke@0 1559 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@0 1560 if (is_receiver) {
duke@0 1561 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@0 1562 }
duke@0 1563 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@0 1564 __ add(SP, offset + STACK_BIAS, rHandle);
duke@0 1565 #ifdef _LP64
duke@0 1566 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@0 1567 #else
duke@0 1568 __ tst( rOop );
duke@0 1569 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@0 1570 #endif
duke@0 1571
duke@0 1572 if (dst.first()->is_stack()) {
duke@0 1573 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1574 } else {
duke@0 1575 __ mov(rHandle, dst.first()->as_Register());
duke@0 1576 }
duke@0 1577 }
duke@0 1578 }
duke@0 1579
duke@0 1580 // A float arg may have to do float reg int reg conversion
duke@0 1581 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1582 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@0 1583
duke@0 1584 if (src.first()->is_stack()) {
duke@0 1585 if (dst.first()->is_stack()) {
duke@0 1586 // stack to stack the easiest of the bunch
duke@0 1587 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1588 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1589 } else {
duke@0 1590 // stack to reg
duke@0 1591 if (dst.first()->is_Register()) {
duke@0 1592 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1593 } else {
duke@0 1594 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1595 }
duke@0 1596 }
duke@0 1597 } else if (dst.first()->is_stack()) {
duke@0 1598 // reg to stack
duke@0 1599 if (src.first()->is_Register()) {
duke@0 1600 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1601 } else {
duke@0 1602 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1603 }
duke@0 1604 } else {
duke@0 1605 // reg to reg
duke@0 1606 if (src.first()->is_Register()) {
duke@0 1607 if (dst.first()->is_Register()) {
duke@0 1608 // gpr -> gpr
duke@0 1609 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1610 } else {
duke@0 1611 // gpr -> fpr
duke@0 1612 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1613 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1614 }
duke@0 1615 } else if (dst.first()->is_Register()) {
duke@0 1616 // fpr -> gpr
duke@0 1617 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@0 1618 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@0 1619 } else {
duke@0 1620 // fpr -> fpr
duke@0 1621 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1622 if ( src.first() != dst.first()) {
duke@0 1623 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1624 }
duke@0 1625 }
duke@0 1626 }
duke@0 1627 }
duke@0 1628
duke@0 1629 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1630 VMRegPair src_lo(src.first());
duke@0 1631 VMRegPair src_hi(src.second());
duke@0 1632 VMRegPair dst_lo(dst.first());
duke@0 1633 VMRegPair dst_hi(dst.second());
duke@0 1634 simple_move32(masm, src_lo, dst_lo);
duke@0 1635 simple_move32(masm, src_hi, dst_hi);
duke@0 1636 }
duke@0 1637
duke@0 1638 // A long move
duke@0 1639 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1640
duke@0 1641 // Do the simple ones here else do two int moves
duke@0 1642 if (src.is_single_phys_reg() ) {
duke@0 1643 if (dst.is_single_phys_reg()) {
duke@0 1644 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1645 } else {
duke@0 1646 // split src into two separate registers
duke@0 1647 // Remember hi means hi address or lsw on sparc
duke@0 1648 // Move msw to lsw
duke@0 1649 if (dst.second()->is_reg()) {
duke@0 1650 // MSW -> MSW
duke@0 1651 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@0 1652 // Now LSW -> LSW
duke@0 1653 // this will only move lo -> lo and ignore hi
duke@0 1654 VMRegPair split(dst.second());
duke@0 1655 simple_move32(masm, src, split);
duke@0 1656 } else {
duke@0 1657 VMRegPair split(src.first(), L4->as_VMReg());
duke@0 1658 // MSW -> MSW (lo ie. first word)
duke@0 1659 __ srax(src.first()->as_Register(), 32, L4);
duke@0 1660 split_long_move(masm, split, dst);
duke@0 1661 }
duke@0 1662 }
duke@0 1663 } else if (dst.is_single_phys_reg()) {
duke@0 1664 if (src.is_adjacent_aligned_on_stack(2)) {
never@297 1665 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1666 } else {
duke@0 1667 // dst is a single reg.
duke@0 1668 // Remember lo is low address not msb for stack slots
duke@0 1669 // and lo is the "real" register for registers
duke@0 1670 // src is
duke@0 1671
duke@0 1672 VMRegPair split;
duke@0 1673
duke@0 1674 if (src.first()->is_reg()) {
duke@0 1675 // src.lo (msw) is a reg, src.hi is stk/reg
duke@0 1676 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@0 1677 split.set_pair(dst.first(), src.first());
duke@0 1678 } else {
duke@0 1679 // msw is stack move to L5
duke@0 1680 // lsw is stack move to dst.lo (real reg)
duke@0 1681 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@0 1682 split.set_pair(dst.first(), L5->as_VMReg());
duke@0 1683 }
duke@0 1684
duke@0 1685 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@0 1686 // msw -> src.lo/L5, lsw -> dst.lo
duke@0 1687 split_long_move(masm, src, split);
duke@0 1688
duke@0 1689 // So dst now has the low order correct position the
duke@0 1690 // msw half
duke@0 1691 __ sllx(split.first()->as_Register(), 32, L5);
duke@0 1692
duke@0 1693 const Register d = dst.first()->as_Register();
duke@0 1694 __ or3(L5, d, d);
duke@0 1695 }
duke@0 1696 } else {
duke@0 1697 // For LP64 we can probably do better.
duke@0 1698 split_long_move(masm, src, dst);
duke@0 1699 }
duke@0 1700 }
duke@0 1701
duke@0 1702 // A double move
duke@0 1703 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@0 1704
duke@0 1705 // The painful thing here is that like long_move a VMRegPair might be
duke@0 1706 // 1: a single physical register
duke@0 1707 // 2: two physical registers (v8)
duke@0 1708 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@0 1709 // 4: two stack slots
duke@0 1710
duke@0 1711 // Since src is always a java calling convention we know that the src pair
duke@0 1712 // is always either all registers or all stack (and aligned?)
duke@0 1713
duke@0 1714 // in a register [lo] and a stack slot [hi]
duke@0 1715 if (src.first()->is_stack()) {
duke@0 1716 if (dst.first()->is_stack()) {
duke@0 1717 // stack to stack the easiest of the bunch
duke@0 1718 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@0 1719 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@0 1720 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1721 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1722 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1723 } else {
duke@0 1724 // stack to reg
duke@0 1725 if (dst.second()->is_stack()) {
duke@0 1726 // stack -> reg, stack -> stack
duke@0 1727 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1728 if (dst.first()->is_Register()) {
duke@0 1729 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1730 } else {
duke@0 1731 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1732 }
duke@0 1733 // This was missing. (very rare case)
duke@0 1734 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1735 } else {
duke@0 1736 // stack -> reg
duke@0 1737 // Eventually optimize for alignment QQQ
duke@0 1738 if (dst.first()->is_Register()) {
duke@0 1739 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@0 1740 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@0 1741 } else {
duke@0 1742 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1743 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1744 }
duke@0 1745 }
duke@0 1746 }
duke@0 1747 } else if (dst.first()->is_stack()) {
duke@0 1748 // reg to stack
duke@0 1749 if (src.first()->is_Register()) {
duke@0 1750 // Eventually optimize for alignment QQQ
duke@0 1751 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1752 if (src.second()->is_stack()) {
duke@0 1753 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@0 1754 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1755 } else {
duke@0 1756 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1757 }
duke@0 1758 } else {
duke@0 1759 // fpr to stack
duke@0 1760 if (src.second()->is_stack()) {
duke@0 1761 ShouldNotReachHere();
duke@0 1762 } else {
duke@0 1763 // Is the stack aligned?
duke@0 1764 if (reg2offset(dst.first()) & 0x7) {
duke@0 1765 // No do as pairs
duke@0 1766 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1767 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1768 } else {
duke@0 1769 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@0 1770 }
duke@0 1771 }
duke@0 1772 }
duke@0 1773 } else {
duke@0 1774 // reg to reg
duke@0 1775 if (src.first()->is_Register()) {
duke@0 1776 if (dst.first()->is_Register()) {
duke@0 1777 // gpr -> gpr
duke@0 1778 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@0 1779 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@0 1780 } else {
duke@0 1781 // gpr -> fpr
duke@0 1782 // ought to be able to do a single store
duke@0 1783 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@0 1784 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@0 1785 // ought to be able to do a single load
duke@0 1786 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@0 1787 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@0 1788 }
duke@0 1789 } else if (dst.first()->is_Register()) {
duke@0 1790 // fpr -> gpr
duke@0 1791 // ought to be able to do a single store
duke@0 1792 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@0 1793 // ought to be able to do a single load
duke@0 1794 // REMEMBER first() is low address not LSB
duke@0 1795 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@0 1796 if (dst.second()->is_Register()) {
duke@0 1797 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@0 1798 } else {
duke@0 1799 __ ld(FP, -4 + STACK_BIAS, L4);
duke@0 1800 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@0 1801 }
duke@0 1802 } else {
duke@0 1803 // fpr -> fpr
duke@0 1804 // In theory these overlap but the ordering is such that this is likely a nop
duke@0 1805 if ( src.first() != dst.first()) {
duke@0 1806 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@0 1807 }
duke@0 1808 }
duke@0 1809 }
duke@0 1810 }
duke@0 1811
duke@0 1812 // Creates an inner frame if one hasn't already been created, and
duke@0 1813 // saves a copy of the thread in L7_thread_cache
duke@0 1814 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@0 1815 if (!*already_created) {
duke@0 1816 __ save_frame(0);
duke@0 1817 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@0 1818 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@0 1819 // copy
duke@0 1820 __ mov(G2_thread, L7_thread_cache);
duke@0 1821 *already_created = true;
duke@0 1822 }
duke@0 1823 }
duke@0 1824
never@3064 1825
never@3064 1826 static void save_or_restore_arguments(MacroAssembler* masm,
never@3064 1827 const int stack_slots,
never@3064 1828 const int total_in_args,
never@3064 1829 const int arg_save_area,
never@3064 1830 OopMap* map,
never@3064 1831 VMRegPair* in_regs,
never@3064 1832 BasicType* in_sig_bt) {
never@3064 1833 // if map is non-NULL then the code should store the values,
never@3064 1834 // otherwise it should load them.
never@3064 1835 if (map != NULL) {
never@3064 1836 // Fill in the map
never@3064 1837 for (int i = 0; i < total_in_args; i++) {
never@3064 1838 if (in_sig_bt[i] == T_ARRAY) {
never@3064 1839 if (in_regs[i].first()->is_stack()) {
never@3064 1840 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
never@3064 1841 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
never@3064 1842 } else if (in_regs[i].first()->is_Register()) {
never@3064 1843 map->set_oop(in_regs[i].first());
never@3064 1844 } else {
never@3064 1845 ShouldNotReachHere();
never@3064 1846 }
never@3064 1847 }
never@3064 1848 }
never@3064 1849 }
never@3064 1850
never@3064 1851 // Save or restore double word values
never@3064 1852 int handle_index = 0;
never@3064 1853 for (int i = 0; i < total_in_args; i++) {
never@3064 1854 int slot = handle_index + arg_save_area;
never@3064 1855 int offset = slot * VMRegImpl::stack_slot_size;
never@3064 1856 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) {
never@3064 1857 const Register reg = in_regs[i].first()->as_Register();
never@3064 1858 if (reg->is_global()) {
never@3064 1859 handle_index += 2;
never@3064 1860 assert(handle_index <= stack_slots, "overflow");
never@3064 1861 if (map != NULL) {
never@3064 1862 __ stx(reg, SP, offset + STACK_BIAS);
never@3064 1863 } else {
never@3064 1864 __ ldx(SP, offset + STACK_BIAS, reg);
never@3064 1865 }
never@3064 1866 }
never@3064 1867 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) {
never@3064 1868 handle_index += 2;
never@3064 1869 assert(handle_index <= stack_slots, "overflow");
never@3064 1870 if (map != NULL) {
never@3064 1871 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3064 1872 } else {
never@3064 1873 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3064 1874 }
never@3064 1875 }
never@3064 1876 }
never@3064 1877 // Save floats
never@3064 1878 for (int i = 0; i < total_in_args; i++) {
never@3064 1879 int slot = handle_index + arg_save_area;
never@3064 1880 int offset = slot * VMRegImpl::stack_slot_size;
never@3064 1881 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) {
never@3064 1882 handle_index++;
never@3064 1883 assert(handle_index <= stack_slots, "overflow");
never@3064 1884 if (map != NULL) {
never@3064 1885 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3064 1886 } else {
never@3064 1887 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3064 1888 }
never@3064 1889 }
never@3064 1890 }
never@3064 1891
never@3064 1892 }
never@3064 1893
never@3064 1894
never@3064 1895 // Check GC_locker::needs_gc and enter the runtime if it's true. This
never@3064 1896 // keeps a new JNI critical region from starting until a GC has been
never@3064 1897 // forced. Save down any oops in registers and describe them in an
never@3064 1898 // OopMap.
never@3064 1899 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
never@3064 1900 const int stack_slots,
never@3064 1901 const int total_in_args,
never@3064 1902 const int arg_save_area,
never@3064 1903 OopMapSet* oop_maps,
never@3064 1904 VMRegPair* in_regs,
never@3064 1905 BasicType* in_sig_bt) {
never@3064 1906 __ block_comment("check GC_locker::needs_gc");
never@3064 1907 Label cont;
never@3064 1908 AddressLiteral sync_state(GC_locker::needs_gc_address());
never@3064 1909 __ load_bool_contents(sync_state, G3_scratch);
never@3064 1910 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont);
never@3064 1911 __ delayed()->nop();
never@3064 1912
never@3064 1913 // Save down any values that are live in registers and call into the
never@3064 1914 // runtime to halt for a GC
never@3064 1915 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3064 1916 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1917 arg_save_area, map, in_regs, in_sig_bt);
never@3064 1918
never@3064 1919 __ mov(G2_thread, L7_thread_cache);
never@3064 1920
never@3064 1921 __ set_last_Java_frame(SP, noreg);
never@3064 1922
never@3064 1923 __ block_comment("block_for_jni_critical");
never@3064 1924 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type);
never@3064 1925 __ delayed()->mov(L7_thread_cache, O0);
never@3064 1926 oop_maps->add_gc_map( __ offset(), map);
never@3064 1927
never@3064 1928 __ restore_thread(L7_thread_cache); // restore G2_thread
never@3064 1929 __ reset_last_Java_frame();
never@3064 1930
never@3064 1931 // Reload all the register arguments
never@3064 1932 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1933 arg_save_area, NULL, in_regs, in_sig_bt);
never@3064 1934
never@3064 1935 __ bind(cont);
never@3064 1936 #ifdef ASSERT
never@3064 1937 if (StressCriticalJNINatives) {
never@3064 1938 // Stress register saving
never@3064 1939 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3064 1940 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1941 arg_save_area, map, in_regs, in_sig_bt);
never@3064 1942 // Destroy argument registers
never@3064 1943 for (int i = 0; i < total_in_args; i++) {
never@3064 1944 if (in_regs[i].first()->is_Register()) {
never@3064 1945 const Register reg = in_regs[i].first()->as_Register();
never@3064 1946 if (reg->is_global()) {
never@3064 1947 __ mov(G0, reg);
never@3064 1948 }
never@3064 1949 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3064 1950 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister());
never@3064 1951 }
never@3064 1952 }
never@3064 1953
never@3064 1954 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3064 1955 arg_save_area, NULL, in_regs, in_sig_bt);
never@3064 1956 }
never@3064 1957 #endif
never@3064 1958 }
never@3064 1959
never@3064 1960 // Unpack an array argument into a pointer to the body and the length
never@3064 1961 // if the array is non-null, otherwise pass 0 for both.
never@3064 1962 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
never@3064 1963 // Pass the length, ptr pair
never@3064 1964 Label is_null, done;
never@3064 1965 if (reg.first()->is_stack()) {
never@3064 1966 VMRegPair tmp = reg64_to_VMRegPair(L2);
never@3064 1967 // Load the arg up from the stack
never@3064 1968 move_ptr(masm, reg, tmp);
never@3064 1969 reg = tmp;
never@3064 1970 }
never@3064 1971 __ cmp(reg.first()->as_Register(), G0);
never@3064 1972 __ brx(Assembler::equal, false, Assembler::pt, is_null);
never@3064 1973 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4);
never@3064 1974 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg);
never@3064 1975 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4);
never@3064 1976 move32_64(masm, reg64_to_VMRegPair(L4), length_arg);
never@3064 1977 __ ba_short(done);
never@3064 1978 __ bind(is_null);
never@3064 1979 // Pass zeros
never@3064 1980 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg);
never@3064 1981 move32_64(masm, reg64_to_VMRegPair(G0), length_arg);
never@3064 1982 __ bind(done);
never@3064 1983 }
never@3064 1984
twisti@3534 1985 static void verify_oop_args(MacroAssembler* masm,
twisti@3534 1986 int total_args_passed,
twisti@3534 1987 const BasicType* sig_bt,
twisti@3534 1988 const VMRegPair* regs) {
twisti@3534 1989 Register temp_reg = G5_method; // not part of any compiled calling seq
twisti@3534 1990 if (VerifyOops) {
twisti@3534 1991 for (int i = 0; i < total_args_passed; i++) {
twisti@3534 1992 if (sig_bt[i] == T_OBJECT ||
twisti@3534 1993 sig_bt[i] == T_ARRAY) {
twisti@3534 1994 VMReg r = regs[i].first();
twisti@3534 1995 assert(r->is_valid(), "bad oop arg");
twisti@3534 1996 if (r->is_stack()) {
twisti@3534 1997 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3534 1998 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg);
twisti@3534 1999 __ ld_ptr(SP, ld_off, temp_reg);
twisti@3534 2000 __ verify_oop(temp_reg);
twisti@3534 2001 } else {
twisti@3534 2002 __ verify_oop(r->as_Register());
twisti@3534 2003 }
twisti@3534 2004 }
twisti@3534 2005 }
twisti@3534 2006 }
twisti@3534 2007 }
twisti@3534 2008
twisti@3534 2009 static void gen_special_dispatch(MacroAssembler* masm,
twisti@3534 2010 int total_args_passed,
twisti@3534 2011 int comp_args_on_stack,
twisti@3534 2012 vmIntrinsics::ID special_dispatch,
twisti@3534 2013 const BasicType* sig_bt,
twisti@3534 2014 const VMRegPair* regs) {
twisti@3534 2015 verify_oop_args(masm, total_args_passed, sig_bt, regs);
twisti@3534 2016
twisti@3534 2017 // Now write the args into the outgoing interpreter space
twisti@3534 2018 bool has_receiver = false;
twisti@3534 2019 Register receiver_reg = noreg;
twisti@3534 2020 int member_arg_pos = -1;
twisti@3534 2021 Register member_reg = noreg;
twisti@3534 2022 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(special_dispatch);
twisti@3534 2023 if (ref_kind != 0) {
twisti@3534 2024 member_arg_pos = total_args_passed - 1; // trailing MemberName argument
twisti@3534 2025 member_reg = G5_method; // known to be free at this point
twisti@3534 2026 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
twisti@3534 2027 } else if (special_dispatch == vmIntrinsics::_invokeBasic) {
twisti@3534 2028 has_receiver = true;
twisti@3534 2029 } else {
twisti@3534 2030 fatal(err_msg("special_dispatch=%d", special_dispatch));
twisti@3534 2031 }
twisti@3534 2032
twisti@3534 2033 if (member_reg != noreg) {
twisti@3534 2034 // Load the member_arg into register, if necessary.
twisti@3534 2035 assert(member_arg_pos >= 0 && member_arg_pos < total_args_passed, "oob");
twisti@3534 2036 assert(sig_bt[member_arg_pos] == T_OBJECT, "dispatch argument must be an object");
twisti@3534 2037 VMReg r = regs[member_arg_pos].first();
twisti@3534 2038 assert(r->is_valid(), "bad member arg");
twisti@3534 2039 if (r->is_stack()) {
twisti@3534 2040 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3534 2041 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
twisti@3534 2042 __ ld_ptr(SP, ld_off, member_reg);
twisti@3534 2043 } else {
twisti@3534 2044 // no data motion is needed
twisti@3534 2045 member_reg = r->as_Register();
twisti@3534 2046 }
twisti@3534 2047 }
twisti@3534 2048
twisti@3534 2049 if (has_receiver) {
twisti@3534 2050 // Make sure the receiver is loaded into a register.
twisti@3534 2051 assert(total_args_passed > 0, "oob");
twisti@3534 2052 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
twisti@3534 2053 VMReg r = regs[0].first();
twisti@3534 2054 assert(r->is_valid(), "bad receiver arg");
twisti@3534 2055 if (r->is_stack()) {
twisti@3534 2056 // Porting note: This assumes that compiled calling conventions always
twisti@3534 2057 // pass the receiver oop in a register. If this is not true on some
twisti@3534 2058 // platform, pick a temp and load the receiver from stack.
twisti@3534 2059 assert(false, "receiver always in a register");
twisti@3534 2060 receiver_reg = G3_scratch; // known to be free at this point
twisti@3534 2061 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3534 2062 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
twisti@3534 2063 __ ld_ptr(SP, ld_off, receiver_reg);
twisti@3534 2064 } else {
twisti@3534 2065 // no data motion is needed
twisti@3534 2066 receiver_reg = r->as_Register();
twisti@3534 2067 }
twisti@3534 2068 }
twisti@3534 2069
twisti@3534 2070 // Figure out which address we are really jumping to:
twisti@3534 2071 MethodHandles::generate_method_handle_dispatch(masm, special_dispatch,
twisti@3534 2072 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
twisti@3534 2073 }
twisti@3534 2074
duke@0 2075 // ---------------------------------------------------------------------------
duke@0 2076 // Generate a native wrapper for a given method. The method takes arguments
duke@0 2077 // in the Java compiled code convention, marshals them to the native
duke@0 2078 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@0 2079 // returns to java state (possibly blocking), unhandlizes any result and
duke@0 2080 // returns.
twisti@3534 2081 //
twisti@3534 2082 // Critical native functions are a shorthand for the use of
twisti@3534 2083 // GetPrimtiveArrayCritical and disallow the use of any other JNI
twisti@3534 2084 // functions. The wrapper is expected to unpack the arguments before
twisti@3534 2085 // passing them to the callee and perform checks before and after the
twisti@3534 2086 // native call to ensure that they GC_locker
twisti@3534 2087 // lock_critical/unlock_critical semantics are followed. Some other
twisti@3534 2088 // parts of JNI setup are skipped like the tear down of the JNI handle
twisti@3534 2089 // block and the check for pending exceptions it's impossible for them
twisti@3534 2090 // to be thrown.
twisti@3534 2091 //
twisti@3534 2092 // They are roughly structured like this:
twisti@3534 2093 // if (GC_locker::needs_gc())
twisti@3534 2094 // SharedRuntime::block_for_jni_critical();
twisti@3534 2095 // tranistion to thread_in_native
twisti@3534 2096 // unpack arrray arguments and call native entry point
twisti@3534 2097 // check for safepoint in progress
twisti@3534 2098 // check if any thread suspend flags are set
twisti@3534 2099 // call into JVM and possible unlock the JNI critical
twisti@3534 2100 // if a GC was suppressed while in the critical native.
twisti@3534 2101 // transition back to thread_in_Java
twisti@3534 2102 // return to caller
twisti@3534 2103 //
duke@0 2104 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@0 2105 methodHandle method,
twisti@2244 2106 int compile_id,
duke@0 2107 int total_in_args,
duke@0 2108 int comp_args_on_stack, // in VMRegStackSlots
twisti@3534 2109 BasicType* in_sig_bt,
twisti@3534 2110 VMRegPair* in_regs,
duke@0 2111 BasicType ret_type) {
twisti@3534 2112 if (method->is_method_handle_intrinsic()) {
twisti@3534 2113 vmIntrinsics::ID iid = method->intrinsic_id();
twisti@3534 2114 intptr_t start = (intptr_t)__ pc();
twisti@3534 2115 int vep_offset = ((intptr_t)__ pc()) - start;
twisti@3534 2116 gen_special_dispatch(masm,
twisti@3534 2117 total_in_args,
twisti@3534 2118 comp_args_on_stack,
twisti@3534 2119 method->intrinsic_id(),
twisti@3534 2120 in_sig_bt,
twisti@3534 2121 in_regs);
twisti@3534 2122 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
twisti@3534 2123 __ flush();
twisti@3534 2124 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
twisti@3534 2125 return nmethod::new_native_nmethod(method,
twisti@3534 2126 compile_id,
twisti@3534 2127 masm->code(),
twisti@3534 2128 vep_offset,
twisti@3534 2129 frame_complete,
twisti@3534 2130 stack_slots / VMRegImpl::slots_per_word,
twisti@3534 2131 in_ByteSize(-1),
twisti@3534 2132 in_ByteSize(-1),
twisti@3534 2133 (OopMapSet*)NULL);
twisti@3534 2134 }
never@3064 2135 bool is_critical_native = true;
never@3064 2136 address native_func = method->critical_native_function();
never@3064 2137 if (native_func == NULL) {
never@3064 2138 native_func = method->native_function();
never@3064 2139 is_critical_native = false;
never@3064 2140 }
never@3064 2141 assert(native_func != NULL, "must have function");
duke@0 2142
duke@0 2143 // Native nmethod wrappers never take possesion of the oop arguments.
duke@0 2144 // So the caller will gc the arguments. The only thing we need an
duke@0 2145 // oopMap for is if the call is static
duke@0 2146 //
duke@0 2147 // An OopMap for lock (and class if static), and one for the VM call itself
duke@0 2148 OopMapSet *oop_maps = new OopMapSet();
duke@0 2149 intptr_t start = (intptr_t)__ pc();
duke@0 2150
duke@0 2151 // First thing make an ic check to see if we should even be here
duke@0 2152 {
duke@0 2153 Label L;
duke@0 2154 const Register temp_reg = G3_scratch;
twisti@720 2155 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@0 2156 __ verify_oop(O0);
coleenp@108 2157 __ load_klass(O0, temp_reg);
kvn@2600 2158 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
duke@0 2159
twisti@720 2160 __ jump_to(ic_miss, temp_reg);
duke@0 2161 __ delayed()->nop();
duke@0 2162 __ align(CodeEntryAlignment);
duke@0 2163 __ bind(L);
duke@0 2164 }
duke@0 2165
duke@0 2166 int vep_offset = ((intptr_t)__ pc()) - start;
duke@0 2167
duke@0 2168 #ifdef COMPILER1
duke@0 2169 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@0 2170 // Object.hashCode can pull the hashCode from the header word
duke@0 2171 // instead of doing a full VM transition once it's been computed.
duke@0 2172 // Since hashCode is usually polymorphic at call sites we can't do
duke@0 2173 // this optimization at the call site without a lot of work.
duke@0 2174 Label slowCase;
duke@0 2175 Register receiver = O0;
duke@0 2176 Register result = O0;
duke@0 2177 Register header = G3_scratch;
duke@0 2178 Register hash = G3_scratch; // overwrite header value with hash value
duke@0 2179 Register mask = G1; // to get hash field from header
duke@0 2180
duke@0 2181 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@0 2182 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@0 2183 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@0 2184 // vm: see markOop.hpp.
duke@0 2185 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@0 2186 __ sethi(markOopDesc::hash_mask, mask);
duke@0 2187 __ btst(markOopDesc::unlocked_value, header);
duke@0 2188 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@0 2189 if (UseBiasedLocking) {
duke@0 2190 // Check if biased and fall through to runtime if so
duke@0 2191 __ delayed()->nop();
duke@0 2192 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@0 2193 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@0 2194 }
duke@0 2195 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@0 2196
duke@0 2197 // Check for a valid (non-zero) hash code and get its value.
duke@0 2198 #ifdef _LP64
duke@0 2199 __ srlx(header, markOopDesc::hash_shift, hash);
duke@0 2200 #else
duke@0 2201 __ srl(header, markOopDesc::hash_shift, hash);
duke@0 2202 #endif
duke@0 2203 __ andcc(hash, mask, hash);
duke@0 2204 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@0 2205 __ delayed()->nop();
duke@0 2206
duke@0 2207 // leaf return.
duke@0 2208 __ retl();
duke@0 2209 __ delayed()->mov(hash, result);
duke@0 2210 __ bind(slowCase);
duke@0 2211 }
duke@0 2212 #endif // COMPILER1
duke@0 2213
duke@0 2214
duke@0 2215 // We have received a description of where all the java arg are located
duke@0 2216 // on entry to the wrapper. We need to convert these args to where
duke@0 2217 // the jni function will expect them. To figure out where they go
duke@0 2218 // we convert the java signature to a C signature by inserting
duke@0 2219 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@0 2220
never@3064 2221 int total_c_args = total_in_args;
never@3064 2222 int total_save_slots = 6 * VMRegImpl::slots_per_word;
never@3064 2223 if (!is_critical_native) {
never@3064 2224 total_c_args += 1;
never@3064 2225 if (method->is_static()) {
never@3064 2226 total_c_args++;
never@3064 2227 }
never@3064 2228 } else {
never@3064 2229 for (int i = 0; i < total_in_args; i++) {
never@3064 2230 if (in_sig_bt[i] == T_ARRAY) {
never@3064 2231 // These have to be saved and restored across the safepoint
never@3064 2232 total_c_args++;
never@3064 2233 }
never@3064 2234 }
duke@0 2235 }
duke@0 2236
duke@0 2237 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
never@3064 2238 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
never@3064 2239 BasicType* in_elem_bt = NULL;
duke@0 2240
duke@0 2241 int argc = 0;
never@3064 2242 if (!is_critical_native) {
never@3064 2243 out_sig_bt[argc++] = T_ADDRESS;
never@3064 2244 if (method->is_static()) {
never@3064 2245 out_sig_bt[argc++] = T_OBJECT;
never@3064 2246 }
never@3064 2247
never@3064 2248 for (int i = 0; i < total_in_args ; i++ ) {
never@3064 2249 out_sig_bt[argc++] = in_sig_bt[i];
never@3064 2250 }
never@3064 2251 } else {
never@3064 2252 Thread* THREAD = Thread::current();
never@3064 2253 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
never@3064 2254 SignatureStream ss(method->signature());
never@3064 2255 for (int i = 0; i < total_in_args ; i++ ) {
never@3064 2256 if (in_sig_bt[i] == T_ARRAY) {
never@3064 2257 // Arrays are passed as int, elem* pair
never@3064 2258 out_sig_bt[argc++] = T_INT;
never@3064 2259 out_sig_bt[argc++] = T_ADDRESS;
never@3064 2260 Symbol* atype = ss.as_symbol(CHECK_NULL);
never@3064 2261 const char* at = atype->as_C_string();
never@3064 2262 if (strlen(at) == 2) {
never@3064 2263 assert(at[0] == '[', "must be");
never@3064 2264 switch (at[1]) {
never@3064 2265 case 'B': in_elem_bt[i] = T_BYTE; break;
never@3064 2266 case 'C': in_elem_bt[i] = T_CHAR; break;
never@3064 2267 case 'D': in_elem_bt[i] = T_DOUBLE; break;
never@3064 2268 case 'F': in_elem_bt[i] = T_FLOAT; break;
never@3064 2269 case 'I': in_elem_bt[i] = T_INT; break;
never@3064 2270 case 'J': in_elem_bt[i] = T_LONG; break;
never@3064 2271 case 'S': in_elem_bt[i] = T_SHORT; break;
never@3064 2272 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
never@3064 2273 default: ShouldNotReachHere();
never@3064 2274 }
never@3064 2275 }
never@3064 2276 } else {
never@3064 2277 out_sig_bt[argc++] = in_sig_bt[i];
never@3064 2278 in_elem_bt[i] = T_VOID;
never@3064 2279 }
never@3064 2280 if (in_sig_bt[i] != T_VOID) {
never@3064 2281 assert(in_sig_bt[i] == ss.type(), "must match");
never@3064 2282 ss.next();
never@3064 2283 }
never@3064 2284 }
duke@0 2285 }
duke@0 2286
duke@0 2287 // Now figure out where the args must be stored and how much stack space
duke@0 2288 // they require (neglecting out_preserve_stack_slots but space for storing
duke@0 2289 // the 1st six register arguments). It's weird see int_stk_helper.
duke@0 2290 //
duke@0 2291 int out_arg_slots;
duke@0 2292 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@0 2293
never@3064 2294 if (is_critical_native) {
never@3064 2295 // Critical natives may have to call out so they need a save area
never@3064 2296 // for register arguments.
never@3064 2297 int double_slots = 0;
never@3064 2298 int single_slots = 0;
never@3064 2299 for ( int i = 0; i < total_in_args; i++) {
never@3064 2300 if (in_regs[i].first()->is_Register()) {
never@3064 2301 const Register reg = in_regs[i].first()->as_Register();
never@3064 2302 switch (in_sig_bt[i]) {
never@3064 2303 case T_ARRAY:
never@3064 2304 case T_BOOLEAN:
never@3064 2305 case T_BYTE:
never@3064 2306 case T_SHORT:
never@3064 2307 case T_CHAR:
never@3064 2308 case T_INT: assert(reg->is_in(), "don't need to save these"); break;
never@3064 2309 case T_LONG: if (reg->is_global()) double_slots++; break;
never@3064 2310 default: ShouldNotReachHere();
never@3064 2311 }
never@3064 2312 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3064 2313 switch (in_sig_bt[i]) {
never@3064 2314 case T_FLOAT: single_slots++; break;
never@3064 2315 case T_DOUBLE: double_slots++; break;
never@3064 2316 default: ShouldNotReachHere();
never@3064 2317 }
never@3064 2318 }
never@3064 2319 }
never@3064 2320 total_save_slots = double_slots * 2 + single_slots;
never@3064 2321 }
never@3064 2322
duke@0 2323 // Compute framesize for the wrapper. We need to handlize all oops in
duke@0 2324 // registers. We must create space for them here that is disjoint from
duke@0 2325 // the windowed save area because we have no control over when we might
duke@0 2326 // flush the window again and overwrite values that gc has since modified.
duke@0 2327 // (The live window race)
duke@0 2328 //
duke@0 2329 // We always just allocate 6 word for storing down these object. This allow
duke@0 2330 // us to simply record the base and use the Ireg number to decide which
duke@0 2331 // slot to use. (Note that the reg number is the inbound number not the
duke@0 2332 // outbound number).
duke@0 2333 // We must shuffle args to match the native convention, and include var-args space.
duke@0 2334
duke@0 2335 // Calculate the total number of stack slots we will need.
duke@0 2336
duke@0 2337 // First count the abi requirement plus all of the outgoing args
duke@0 2338 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@0 2339
duke@0 2340 // Now the space for the inbound oop handle area
duke@0 2341
never@3064 2342 int oop_handle_offset = round_to(stack_slots, 2);
never@3064 2343 stack_slots += total_save_slots;
duke@0 2344
duke@0 2345 // Now any space we need for handlizing a klass if static method
duke@0 2346
duke@0 2347 int klass_slot_offset = 0;
duke@0 2348 int klass_offset = -1;
duke@0 2349 int lock_slot_offset = 0;
duke@0 2350 bool is_static = false;
duke@0 2351
duke@0 2352 if (method->is_static()) {
duke@0 2353 klass_slot_offset = stack_slots;
duke@0 2354 stack_slots += VMRegImpl::slots_per_word;
duke@0 2355 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@0 2356 is_static = true;
duke@0 2357 }
duke@0 2358
duke@0 2359 // Plus a lock if needed
duke@0 2360
duke@0 2361 if (method->is_synchronized()) {
duke@0 2362 lock_slot_offset = stack_slots;
duke@0 2363 stack_slots += VMRegImpl::slots_per_word;
duke@0 2364 }
duke@0 2365
duke@0 2366 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@0 2367 stack_slots += 2;
duke@0 2368
duke@0 2369 // Ok The space we have allocated will look like:
duke@0 2370 //
duke@0 2371 //
duke@0 2372 // FP-> | |
duke@0 2373 // |---------------------|
duke@0 2374 // | 2 slots for moves |
duke@0 2375 // |---------------------|
duke@0 2376 // | lock box (if sync) |
duke@0 2377 // |---------------------| <- lock_slot_offset
duke@0 2378 // | klass (if static) |
duke@0 2379 // |---------------------| <- klass_slot_offset
duke@0 2380 // | oopHandle area |
duke@0 2381 // |---------------------| <- oop_handle_offset
duke@0 2382 // | outbound memory |
duke@0 2383 // | based arguments |
duke@0 2384 // | |
duke@0 2385 // |---------------------|
duke@0 2386 // | vararg area |
duke@0 2387 // |---------------------|
duke@0 2388 // | |
duke@0 2389 // SP-> | out_preserved_slots |
duke@0 2390 //
duke@0 2391 //
duke@0 2392
duke@0 2393
duke@0 2394 // Now compute actual number of stack words we need rounding to make
duke@0 2395 // stack properly aligned.
duke@0 2396 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@0 2397
duke@0 2398 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@0 2399
duke@0 2400 // Generate stack overflow check before creating frame
duke@0 2401 __ generate_stack_overflow_check(stack_size);
duke@0 2402
duke@0 2403 // Generate a new frame for the wrapper.
duke@0 2404 __ save(SP, -stack_size, SP);
duke@0 2405
duke@0 2406 int frame_complete = ((intptr_t)__ pc()) - start;
duke@0 2407
duke@0 2408 __ verify_thread();
duke@0 2409
never@3064 2410 if (is_critical_native) {
never@3064 2411 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args,
never@3064 2412 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
never@3064 2413 }
duke@0 2414
duke@0 2415 //
duke@0 2416 // We immediately shuffle the arguments so that any vm call we have to
duke@0 2417 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@0 2418 // captured the oops from our caller and have a valid oopMap for
duke@0 2419 // them.
duke@0 2420
duke@0 2421 // -----------------
duke@0 2422 // The Grand Shuffle
duke@0 2423 //
duke@0 2424 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@0 2425 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@0 2426 // the class mirror instead of a receiver. This pretty much guarantees that
duke@0 2427 // register layout will not match. We ignore these extra arguments during
duke@0 2428 // the shuffle. The shuffle is described by the two calling convention
duke@0 2429 // vectors we have in our possession. We simply walk the java vector to
duke@0 2430 // get the source locations and the c vector to get the destinations.
duke@0 2431 // Because we have a new window and the argument registers are completely
duke@0 2432 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@0 2433 // here.
duke@0 2434
duke@0 2435 // This is a trick. We double the stack slots so we can claim
duke@0 2436 // the oops in the caller's frame. Since we are sure to have
duke@0 2437 // more args than the caller doubling is enough to make
duke@0 2438 // sure we can capture all the incoming oop args from the
duke@0 2439 // caller.
duke@0 2440 //
duke@0 2441 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@0 2442 // Record sp-based slot for receiver on stack for non-static methods
duke@0 2443 int receiver_offset = -1;
duke@0 2444
duke@0 2445 // We move the arguments backward because the floating point registers
duke@0 2446 // destination will always be to a register with a greater or equal register
duke@0 2447 // number or the stack.
duke@0 2448
duke@0 2449 #ifdef ASSERT
duke@0 2450 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@0 2451 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@0 2452 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@0 2453 reg_destroyed[r] = false;
duke@0 2454 }
duke@0 2455 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@0 2456 freg_destroyed[f] = false;
duke@0 2457 }
duke@0 2458
duke@0 2459 #endif /* ASSERT */
duke@0 2460
never@3064 2461 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@0 2462
duke@0 2463 #ifdef ASSERT
duke@0 2464 if (in_regs[i].first()->is_Register()) {
duke@0 2465 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@0 2466 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@0 2467 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@0 2468 }
duke@0 2469 if (out_regs[c_arg].first()->is_Register()) {
duke@0 2470 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@0 2471 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@0 2472 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@0 2473 }
duke@0 2474 #endif /* ASSERT */
duke@0 2475
duke@0 2476 switch (in_sig_bt[i]) {
duke@0 2477 case T_ARRAY:
never@3064 2478 if (is_critical_native) {
never@3064 2479 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]);
never@3064 2480 c_arg--;
never@3064 2481 break;
never@3064 2482 }
duke@0 2483 case T_OBJECT:
never@3064 2484 assert(!is_critical_native, "no oop arguments");
duke@0 2485 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@0 2486 ((i == 0) && (!is_static)),
duke@0 2487 &receiver_offset);
duke@0 2488 break;
duke@0 2489 case T_VOID:
duke@0 2490 break;
duke@0 2491
duke@0 2492 case T_FLOAT:
duke@0 2493 float_move(masm, in_regs[i], out_regs[c_arg]);
never@3064 2494 break;
duke@0 2495
duke@0 2496 case T_DOUBLE:
duke@0 2497 assert( i + 1 < total_in_args &&
duke@0 2498 in_sig_bt[i + 1] == T_VOID &&
duke@0 2499 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@0 2500 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2501 break;
duke@0 2502
duke@0 2503 case T_LONG :
duke@0 2504 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@0 2505 break;
duke@0 2506
duke@0 2507 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@0 2508
duke@0 2509 default:
duke@0 2510 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@0 2511 }
duke@0 2512 }
duke@0 2513
duke@0 2514 // Pre-load a static method's oop into O1. Used both by locking code and
duke@0 2515 // the normal JNI call code.
never@3064 2516 if (method->is_static() && !is_critical_native) {
duke@0 2517 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@0 2518
duke@0 2519 // Now handlize the static class mirror in O1. It's known not-null.
duke@0 2520 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@0 2521 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@0 2522 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@0 2523 }
duke@0 2524
duke@0 2525
duke@0 2526 const Register L6_handle = L6;
duke@0 2527
duke@0 2528 if (method->is_synchronized()) {
never@3064 2529 assert(!is_critical_native, "unhandled");
duke@0 2530 __ mov(O1, L6_handle);
duke@0 2531 }
duke@0 2532
duke@0 2533 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@0 2534 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@0 2535 // push a new frame and flush the windows.
duke@0 2536 #ifdef _LP64
duke@0 2537 intptr_t thepc = (intptr_t) __ pc();
duke@0 2538 {
duke@0 2539 address here = __ pc();
duke@0 2540 // Call the next instruction
duke@0 2541 __ call(here + 8, relocInfo::none);
duke@0 2542 __ delayed()->nop();
duke@0 2543 }
duke@0 2544 #else
duke@0 2545 intptr_t thepc = __ load_pc_address(O7, 0);
duke@0 2546 #endif /* _LP64 */
duke@0 2547
duke@0 2548 // We use the same pc/oopMap repeatedly when we call out
duke@0 2549 oop_maps->add_gc_map(thepc - start, map);
duke@0 2550
duke@0 2551 // O7 now has the pc loaded that we will use when we finally call to native.
duke@0 2552
duke@0 2553 // Save thread in L7; it crosses a bunch of VM calls below
duke@0 2554 // Don't use save_thread because it smashes G2 and we merely
duke@0 2555 // want to save a copy
duke@0 2556 __ mov(G2_thread, L7_thread_cache);
duke@0 2557
duke@0 2558
duke@0 2559 // If we create an inner frame once is plenty
duke@0 2560 // when we create it we must also save G2_thread
duke@0 2561 bool inner_frame_created = false;
duke@0 2562
duke@0 2563 // dtrace method entry support
duke@0 2564 {
duke@0 2565 SkipIfEqual skip_if(
duke@0 2566 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2567 // create inner frame
duke@0 2568 __ save_frame(0);
duke@0 2569 __ mov(G2_thread, L7_thread_cache);
coleenp@3601 2570 __ set_metadata_constant(method(), O1);
duke@0 2571 __ call_VM_leaf(L7_thread_cache,
duke@0 2572 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@0 2573 G2_thread, O1);
duke@0 2574 __ restore();
duke@0 2575 }
duke@0 2576
dcubed@606 2577 // RedefineClasses() tracing support for obsolete method entry
dcubed@606 2578 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
dcubed@606 2579 // create inner frame
dcubed@606 2580 __ save_frame(0);
dcubed@606 2581 __ mov(G2_thread, L7_thread_cache);
coleenp@3601 2582 __ set_metadata_constant(method(), O1);
dcubed@606 2583 __ call_VM_leaf(L7_thread_cache,
dcubed@606 2584 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
dcubed@606 2585 G2_thread, O1);
dcubed@606 2586 __ restore();
dcubed@606 2587 }
dcubed@606 2588
duke@0 2589 // We are in the jni frame unless saved_frame is true in which case
duke@0 2590 // we are in one frame deeper (the "inner" frame). If we are in the
duke@0 2591 // "inner" frames the args are in the Iregs and if the jni frame then
duke@0 2592 // they are in the Oregs.
duke@0 2593 // If we ever need to go to the VM (for locking, jvmti) then
duke@0 2594 // we will always be in the "inner" frame.
duke@0 2595
duke@0 2596 // Lock a synchronized method
duke@0 2597 int lock_offset = -1; // Set if locked
duke@0 2598 if (method->is_synchronized()) {
duke@0 2599 Register Roop = O1;
duke@0 2600 const Register L3_box = L3;
duke@0 2601
duke@0 2602 create_inner_frame(masm, &inner_frame_created);
duke@0 2603
duke@0 2604 __ ld_ptr(I1, 0, O1);
duke@0 2605 Label done;
duke@0 2606
duke@0 2607 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@0 2608 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2609 #ifdef ASSERT
duke@0 2610 if (UseBiasedLocking) {
duke@0 2611 // making the box point to itself will make it clear it went unused
duke@0 2612 // but also be obviously invalid
duke@0 2613 __ st_ptr(L3_box, L3_box, 0);
duke@0 2614 }
duke@0 2615 #endif // ASSERT
duke@0 2616 //
duke@0 2617 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@0 2618 //
duke@0 2619 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@0 2620 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2621 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@0 2622
duke@0 2623
duke@0 2624 // None of the above fast optimizations worked so we have to get into the
duke@0 2625 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2626 // disallows any pending_exception.
duke@0 2627 __ mov(Roop, O0); // Need oop in O0
duke@0 2628 __ mov(L3_box, O1);
duke@0 2629
duke@0 2630 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@0 2631
duke@0 2632 __ set_last_Java_frame(FP, I7);
duke@0 2633
duke@0 2634 // do the call
duke@0 2635 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@0 2636 __ delayed()->mov(L7_thread_cache, O2);
duke@0 2637
duke@0 2638 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2639 __ reset_last_Java_frame();
duke@0 2640
duke@0 2641 #ifdef ASSERT
duke@0 2642 { Label L;
duke@0 2643 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2644 __ br_null_short(O0, Assembler::pt, L);
duke@0 2645 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@0 2646 __ bind(L);
duke@0 2647 }
duke@0 2648 #endif
duke@0 2649 __ bind(done);
duke@0 2650 }
duke@0 2651
duke@0 2652
duke@0 2653 // Finally just about ready to make the JNI call
duke@0 2654
duke@0 2655 __ flush_windows();
duke@0 2656 if (inner_frame_created) {
duke@0 2657 __ restore();
duke@0 2658 } else {
duke@0 2659 // Store only what we need from this frame
duke@0 2660 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@0 2661 // either as the flush traps and the current window goes too.
duke@0 2662 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2663 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@0 2664 }
duke@0 2665
duke@0 2666 // get JNIEnv* which is first argument to native
never@3064 2667 if (!is_critical_native) {
never@3064 2668 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
never@3064 2669 }
duke@0 2670
duke@0 2671 // Use that pc we placed in O7 a while back as the current frame anchor
duke@0 2672 __ set_last_Java_frame(SP, O7);
duke@0 2673
never@3064 2674 // We flushed the windows ages ago now mark them as flushed before transitioning.
never@3064 2675 __ set(JavaFrameAnchor::flushed, G3_scratch);
never@3064 2676 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
never@3064 2677
duke@0 2678 // Transition from _thread_in_Java to _thread_in_native.
duke@0 2679 __ set(_thread_in_native, G3_scratch);
duke@0 2680
duke@0 2681 #ifdef _LP64
never@3064 2682 AddressLiteral dest(native_func);
duke@0 2683 __ relocate(relocInfo::runtime_call_type);
twisti@720 2684 __ jumpl_to(dest, O7, O7);
duke@0 2685 #else
never@3064 2686 __ call(native_func, relocInfo::runtime_call_type);
duke@0 2687 #endif
never@3064 2688 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2689
duke@0 2690 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2691
duke@0 2692 // Unpack native results. For int-types, we do any needed sign-extension
duke@0 2693 // and move things into I0. The return value there will survive any VM
duke@0 2694 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@0 2695 // specially in the slow-path code.
duke@0 2696 switch (ret_type) {
duke@0 2697 case T_VOID: break; // Nothing to do!
duke@0 2698 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@0 2699 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@0 2700 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@0 2701 case T_LONG:
duke@0 2702 #ifndef _LP64
duke@0 2703 __ mov(O1, I1);
duke@0 2704 #endif
duke@0 2705 // Fall thru
duke@0 2706 case T_OBJECT: // Really a handle
duke@0 2707 case T_ARRAY:
duke@0 2708 case T_INT:
duke@0 2709 __ mov(O0, I0);
duke@0 2710 break;
duke@0 2711 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@0 2712 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@0 2713 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@0 2714 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@0 2715 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@0 2716 default:
duke@0 2717 ShouldNotReachHere();
duke@0 2718 }
duke@0 2719
never@3064 2720 Label after_transition;
duke@0 2721 // must we block?
duke@0 2722
duke@0 2723 // Block, if necessary, before resuming in _thread_in_Java state.
duke@0 2724 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@0 2725 { Label no_block;
twisti@720 2726 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
duke@0 2727
duke@0 2728 // Switch thread to "native transition" state before reading the synchronization state.
duke@0 2729 // This additional state is necessary because reading and testing the synchronization
duke@0 2730 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@0 2731 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@0 2732 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@0 2733 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@0 2734 // didn't see any synchronization is progress, and escapes.
duke@0 2735 __ set(_thread_in_native_trans, G3_scratch);
twisti@720 2736 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@0 2737 if(os::is_MP()) {
duke@0 2738 if (UseMembar) {
duke@0 2739 // Force this write out before the read below
duke@0 2740 __ membar(Assembler::StoreLoad);
duke@0 2741 } else {
duke@0 2742 // Write serialization page so VM thread can do a pseudo remote membar.
duke@0 2743 // We use the current thread pointer to calculate a thread specific
duke@0 2744 // offset to write to within the page. This minimizes bus traffic
duke@0 2745 // due to cache line collision.
duke@0 2746 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@0 2747 }
duke@0 2748 }
duke@0 2749 __ load_contents(sync_state, G3_scratch);
duke@0 2750 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@0 2751
duke@0 2752 Label L;
twisti@720 2753 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
duke@0 2754 __ br(Assembler::notEqual, false, Assembler::pn, L);
twisti@720 2755 __ delayed()->ld(suspend_state, G3_scratch);
kvn@2600 2756 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
duke@0 2757 __ bind(L);
duke@0 2758
duke@0 2759 // Block. Save any potential method result value before the operation and
duke@0 2760 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@0 2761 // lets us share the oopMap we used when we went native rather the create
duke@0 2762 // a distinct one for this pc
duke@0 2763 //
duke@0 2764 save_native_result(masm, ret_type, stack_slots);
never@3064 2765 if (!is_critical_native) {
never@3064 2766 __ call_VM_leaf(L7_thread_cache,
never@3064 2767 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
never@3064 2768 G2_thread);
never@3064 2769 } else {
never@3064 2770 __ call_VM_leaf(L7_thread_cache,
never@3064 2771 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition),
never@3064 2772 G2_thread);
never@3064 2773 }
duke@0 2774
duke@0 2775 // Restore any method result value
duke@0 2776 restore_native_result(masm, ret_type, stack_slots);
never@3064 2777
never@3064 2778 if (is_critical_native) {
never@3064 2779 // The call above performed the transition to thread_in_Java so
never@3064 2780 // skip the transition logic below.
never@3064 2781 __ ba(after_transition);
never@3064 2782 __ delayed()->nop();
never@3064 2783 }
never@3064 2784
duke@0 2785 __ bind(no_block);
duke@0 2786 }
duke@0 2787
duke@0 2788 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@0 2789 // happened so we can now change state to _thread_in_Java.
duke@0 2790 __ set(_thread_in_Java, G3_scratch);
twisti@720 2791 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
never@3064 2792 __ bind(after_transition);
duke@0 2793
duke@0 2794 Label no_reguard;
twisti@720 2795 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
kvn@2600 2796 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
duke@0 2797
duke@0 2798 save_native_result(masm, ret_type, stack_slots);
duke@0 2799 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@0 2800 __ delayed()->nop();
duke@0 2801
duke@0 2802 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2803 restore_native_result(masm, ret_type, stack_slots);
duke@0 2804
duke@0 2805 __ bind(no_reguard);
duke@0 2806
duke@0 2807 // Handle possible exception (will unlock if necessary)
duke@0 2808
duke@0 2809 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@0 2810
duke@0 2811 // Unlock
duke@0 2812 if (method->is_synchronized()) {
duke@0 2813 Label done;
duke@0 2814 Register I2_ex_oop = I2;
duke@0 2815 const Register L3_box = L3;
duke@0 2816 // Get locked oop from the handle we passed to jni
duke@0 2817 __ ld_ptr(L6_handle, 0, L4);
duke@0 2818 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2819 // Must save pending exception around the slow-path VM call. Since it's a
duke@0 2820 // leaf call, the pending exception (if any) can be kept in a register.
duke@0 2821 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@0 2822 // Now unlock
duke@0 2823 // (Roop, Rmark, Rbox, Rscratch)
duke@0 2824 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@0 2825 __ br(Assembler::equal, false, Assembler::pt, done);
duke@0 2826 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@0 2827
duke@0 2828 // save and restore any potential method result value around the unlocking
duke@0 2829 // operation. Will save in I0 (or stack for FP returns).
duke@0 2830 save_native_result(masm, ret_type, stack_slots);
duke@0 2831
duke@0 2832 // Must clear pending-exception before re-entering the VM. Since this is
duke@0 2833 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@0 2834 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2835
duke@0 2836 // slow case of monitor enter. Inline a special case of call_VM that
duke@0 2837 // disallows any pending_exception.
duke@0 2838 __ mov(L3_box, O1);
duke@0 2839
duke@0 2840 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@0 2841 __ delayed()->mov(L4, O0); // Need oop in O0
duke@0 2842
duke@0 2843 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@0 2844
duke@0 2845 #ifdef ASSERT
duke@0 2846 { Label L;
duke@0 2847 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@2600 2848 __ br_null_short(O0, Assembler::pt, L);
duke@0 2849 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@0 2850 __ bind(L);
duke@0 2851 }
duke@0 2852 #endif
duke@0 2853 restore_native_result(masm, ret_type, stack_slots);
duke@0 2854 // check_forward_pending_exception jump to forward_exception if any pending
duke@0 2855 // exception is set. The forward_exception routine expects to see the
duke@0 2856 // exception in pending_exception and not in a register. Kind of clumsy,
duke@0 2857 // since all folks who branch to forward_exception must have tested
duke@0 2858 // pending_exception first and hence have it in a register already.
duke@0 2859 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@0 2860 __ bind(done);
duke@0 2861 }
duke@0 2862
duke@0 2863 // Tell dtrace about this method exit
duke@0 2864 {
duke@0 2865 SkipIfEqual skip_if(
duke@0 2866 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@0 2867 save_native_result(masm, ret_type, stack_slots);
coleenp@3601 2868 __ set_metadata_constant(method(), O1);
duke@0 2869 __ call_VM_leaf(L7_thread_cache,
duke@0 2870 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@0 2871 G2_thread, O1);
duke@0 2872 restore_native_result(masm, ret_type, stack_slots);
duke@0 2873 }
duke@0 2874
duke@0 2875 // Clear "last Java frame" SP and PC.
duke@0 2876 __ verify_thread(); // G2_thread must be correct
duke@0 2877 __ reset_last_Java_frame();
duke@0 2878
duke@0 2879 // Unpack oop result
duke@0 2880 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@0 2881 Label L;
duke@0 2882 __ addcc(G0, I0, G0);
duke@0 2883 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@0 2884 __ delayed()->ld_ptr(I0, 0, I0);
duke@0 2885 __ mov(G0, I0);
duke@0 2886 __ bind(L);
duke@0 2887 __ verify_oop(I0);
duke@0 2888 }
duke@0 2889
never@3064 2890 if (!is_critical_native) {
never@3064 2891 // reset handle block
never@3064 2892 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
never@3064 2893 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
never@3064 2894
never@3064 2895 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
never@3064 2896 check_forward_pending_exception(masm, G3_scratch);
never@3064 2897 }
duke@0 2898
duke@0 2899
duke@0 2900 // Return
duke@0 2901
duke@0 2902 #ifndef _LP64
duke@0 2903 if (ret_type == T_LONG) {
duke@0 2904
duke@0 2905 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@0 2906 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@0 2907 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@0 2908 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@0 2909 }
duke@0 2910 #endif
duke@0 2911
duke@0 2912 __ ret();
duke@0 2913 __ delayed()->restore();
duke@0 2914
duke@0 2915 __ flush();
duke@0 2916
duke@0 2917 nmethod *nm = nmethod::new_native_nmethod(method,
twisti@2244 2918 compile_id,
duke@0 2919 masm->code(),
duke@0 2920 vep_offset,
duke@0 2921 frame_complete,
duke@0 2922 stack_slots / VMRegImpl::slots_per_word,
duke@0 2923 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@0 2924 in_ByteSize(lock_offset),
duke@0 2925 oop_maps);
never@3064 2926
never@3064 2927 if (is_critical_native) {
never@3064 2928 nm->set_lazy_critical_native(true);
never@3064 2929 }
duke@0 2930 return nm;
duke@0 2931
duke@0 2932 }
duke@0 2933
kamg@124 2934 #ifdef HAVE_DTRACE_H
kamg@124 2935 // ---------------------------------------------------------------------------
kamg@124 2936 // Generate a dtrace nmethod for a given signature. The method takes arguments
kamg@124 2937 // in the Java compiled code convention, marshals them to the native
kamg@124 2938 // abi and then leaves nops at the position you would expect to call a native
kamg@124 2939 // function. When the probe is enabled the nops are replaced with a trap
kamg@124 2940 // instruction that dtrace inserts and the trace will cause a notification
kamg@124 2941 // to dtrace.
kamg@124 2942 //
kamg@124 2943 // The probes are only able to take primitive types and java/lang/String as
kamg@124 2944 // arguments. No other java types are allowed. Strings are converted to utf8
kamg@124 2945 // strings so that from dtrace point of view java strings are converted to C
kamg@124 2946 // strings. There is an arbitrary fixed limit on the total space that a method
kamg@124 2947 // can use for converting the strings. (256 chars per string in the signature).
kamg@124 2948 // So any java string larger then this is truncated.
kamg@124 2949
kamg@124 2950 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
kamg@124 2951 static bool offsets_initialized = false;
kamg@124 2952
kamg@124 2953 nmethod *SharedRuntime::generate_dtrace_nmethod(
kamg@124 2954 MacroAssembler *masm, methodHandle method) {
kamg@124 2955
kamg@124 2956
kamg@124 2957 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
kamg@124 2958 // be single threaded in this method.
kamg@124 2959 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
kamg@124 2960
kamg@124 2961 // Fill in the signature array, for the calling-convention call.
kamg@124 2962 int total_args_passed = method->size_of_parameters();
kamg@124 2963
kamg@124 2964 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
kamg@124 2965 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
kamg@124 2966
kamg@124 2967 // The signature we are going to use for the trap that dtrace will see
kamg@124 2968 // java/lang/String is converted. We drop "this" and any other object
kamg@124 2969 // is converted to NULL. (A one-slot java/lang/Long object reference
kamg@124 2970 // is converted to a two-slot long, which is why we double the allocation).
kamg@124 2971 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
kamg@124 2972 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
kamg@124 2973
kamg@124 2974 int i=0;
kamg@124 2975 int total_strings = 0;
kamg@124 2976 int first_arg_to_pass = 0;
kamg@124 2977 int total_c_args = 0;
kamg@124 2978
kamg@124 2979 // Skip the receiver as dtrace doesn't want to see it
kamg@124 2980 if( !method->is_static() ) {
kamg@124 2981 in_sig_bt[i++] = T_OBJECT;
kamg@124 2982 first_arg_to_pass = 1;
kamg@124 2983 }
kamg@124 2984
kamg@124 2985 SignatureStream ss(method->signature());
kamg@124 2986 for ( ; !ss.at_return_type(); ss.next()) {
kamg@124 2987 BasicType bt = ss.type();
kamg@124 2988 in_sig_bt[i++] = bt; // Collect remaining bits of signature
kamg@124 2989 out_sig_bt[total_c_args++] = bt;
kamg@124 2990 if( bt == T_OBJECT) {
coleenp@2059 2991 Symbol* s = ss.as_symbol_or_null();
kamg@124 2992 if (s == vmSymbols::java_lang_String()) {
kamg@124 2993 total_strings++;
kamg@124 2994 out_sig_bt[total_c_args-1] = T_ADDRESS;
kamg@124 2995 } else if (s == vmSymbols::java_lang_Boolean() ||
kamg@124 2996 s == vmSymbols::java_lang_Byte()) {
kamg@124 2997 out_sig_bt[total_c_args-1] = T_BYTE;
kamg@124 2998 } else if (s == vmSymbols::java_lang_Character() ||
kamg@124 2999 s == vmSymbols::java_lang_Short()) {
kamg@124 3000 out_sig_bt[total_c_args-1] = T_SHORT;
kamg@124 3001 } else if (s == vmSymbols::java_lang_Integer() ||
kamg@124 3002 s == vmSymbols::java_lang_Float()) {
kamg@124 3003 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 3004 } else if (s == vmSymbols::java_lang_Long() ||
kamg@124 3005 s == vmSymbols::java_lang_Double()) {
kamg@124 3006 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 3007 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 3008 }
kamg@124 3009 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
kamg@124 3010 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
kamg@124 3011 // We convert double to long
kamg@124 3012 out_sig_bt[total_c_args-1] = T_LONG;
kamg@124 3013 out_sig_bt[total_c_args++] = T_VOID;
kamg@124 3014 } else if ( bt == T_FLOAT) {
kamg@124 3015 // We convert float to int
kamg@124 3016 out_sig_bt[total_c_args-1] = T_INT;
kamg@124 3017 }
kamg@124 3018 }
kamg@124 3019
kamg@124 3020 assert(i==total_args_passed, "validly parsed signature");
kamg@124 3021
kamg@124 3022 // Now get the compiled-Java layout as input arguments
kamg@124 3023 int comp_args_on_stack;
kamg@124 3024 comp_args_on_stack = SharedRuntime::java_calling_convention(
kamg@124 3025 in_sig_bt, in_regs, total_args_passed, false);
kamg@124 3026
kamg@124 3027 // We have received a description of where all the java arg are located
kamg@124 3028 // on entry to the wrapper. We need to convert these args to where
kamg@124 3029 // the a native (non-jni) function would expect them. To figure out
kamg@124 3030 // where they go we convert the java signature to a C signature and remove
kamg@124 3031 // T_VOID for any long/double we might have received.
kamg@124 3032
kamg@124 3033
kamg@124 3034 // Now figure out where the args must be stored and how much stack space
kamg@124 3035 // they require (neglecting out_preserve_stack_slots but space for storing
kamg@124 3036 // the 1st six register arguments). It's weird see int_stk_helper.
kamg@124 3037 //
kamg@124 3038 int out_arg_slots;
kamg@124 3039 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
kamg@124 3040
kamg@124 3041 // Calculate the total number of stack slots we will need.
kamg@124 3042
kamg@124 3043 // First count the abi requirement plus all of the outgoing args
kamg@124 3044 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
kamg@124 3045
kamg@124 3046 // Plus a temp for possible converion of float/double/long register args
kamg@124 3047
kamg@124 3048 int conversion_temp = stack_slots;
kamg@124 3049 stack_slots += 2;
kamg@124 3050
kamg@124 3051
kamg@124 3052 // Now space for the string(s) we must convert
kamg@124 3053
kamg@124 3054 int string_locs = stack_slots;
kamg@124 3055 stack_slots += total_strings *
kamg@124 3056 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
kamg@124 3057
kamg@124 3058 // Ok The space we have allocated will look like:
kamg@124 3059 //
kamg@124 3060 //
kamg@124 3061 // FP-> | |
kamg@124 3062 // |---------------------|
kamg@124 3063 // | string[n] |
kamg@124 3064 // |---------------------| <- string_locs[n]
kamg@124 3065 // | string[n-1] |
kamg@124 3066 // |---------------------| <- string_locs[n-1]
kamg@124 3067 // | ... |
kamg@124 3068 // | ... |
kamg@124 3069 // |---------------------| <- string_locs[1]
kamg@124 3070 // | string[0] |
kamg@124 3071 // |---------------------| <- string_locs[0]
kamg@124 3072 // | temp |
kamg@124 3073 // |---------------------| <- conversion_temp
kamg@124 3074 // | outbound memory |
kamg@124 3075 // | based arguments |
kamg@124 3076 // | |
kamg@124 3077 // |---------------------|
kamg@124 3078 // | |
kamg@124 3079 // SP-> | out_preserved_slots |
kamg@124 3080 //
kamg@124 3081 //
kamg@124 3082
kamg@124 3083 // Now compute actual number of stack words we need rounding to make
kamg@124 3084 // stack properly aligned.
kamg@124 3085 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
kamg@124 3086
kamg@124 3087 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
kamg@124 3088
kamg@124 3089 intptr_t start = (intptr_t)__ pc();
kamg@124 3090
kamg@124 3091 // First thing make an ic check to see if we should even be here
kamg@124 3092
kamg@124 3093 {
kamg@124 3094 Label L;
kamg@124 3095 const Register temp_reg = G3_scratch;
twisti@720 3096 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
kamg@124 3097 __ verify_oop(O0);
kamg@124 3098 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
kvn@2600 3099 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
kamg@124 3100
twisti@720 3101 __ jump_to(ic_miss, temp_reg);
kamg@124 3102 __ delayed()->nop();
kamg@124 3103 __ align(CodeEntryAlignment);
kamg@124 3104 __ bind(L);
kamg@124 3105 }
kamg@124 3106
kamg@124 3107 int vep_offset = ((intptr_t)__ pc()) - start;
kamg@124 3108
kamg@124 3109
kamg@124 3110 // The instruction at the verified entry point must be 5 bytes or longer
kamg@124 3111 // because it can be patched on the fly by make_non_entrant. The stack bang
kamg@124 3112 // instruction fits that requirement.
kamg@124 3113
kamg@124 3114 // Generate stack overflow check before creating frame
kamg@124 3115 __ generate_stack_overflow_check(stack_size);
kamg@124 3116
kamg@124 3117 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
kamg@124 3118 "valid size for make_non_entrant");
kamg@124 3119
kamg@124 3120 // Generate a new frame for the wrapper.
kamg@124 3121 __ save(SP, -stack_size, SP);
kamg@124 3122
kamg@124 3123 // Frame is now completed as far a size and linkage.
kamg@124 3124
kamg@124 3125 int frame_complete = ((intptr_t)__ pc()) - start;
kamg@124 3126
kamg@124 3127 #ifdef ASSERT
kamg@124 3128 bool reg_destroyed[RegisterImpl::number_of_registers];
kamg@124 3129 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
kamg@124 3130 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
kamg@124 3131 reg_destroyed[r] = false;
kamg@124 3132 }
kamg@124 3133 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
kamg@124 3134 freg_destroyed[f] = false;
kamg@124 3135 }
kamg@124 3136
kamg@124 3137 #endif /* ASSERT */
kamg@124 3138
kamg@124 3139 VMRegPair zero;
kamg@182 3140 const Register g0 = G0; // without this we get a compiler warning (why??)
kamg@182 3141 zero.set2(g0->as_VMReg());
kamg@124 3142
kamg@124 3143 int c_arg, j_arg;
kamg@124 3144
kamg@124 3145 Register conversion_off = noreg;
kamg@124 3146
kamg@124 3147 for (j_arg = first_arg_to_pass, c_arg = 0 ;
kamg@124 3148 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
kamg@124 3149
kamg@124 3150 VMRegPair src = in_regs[j_arg];
kamg@124 3151 VMRegPair dst = out_regs[c_arg];
kamg@124 3152
kamg@124 3153 #ifdef ASSERT
kamg@124 3154 if (src.first()->is_Register()) {
kamg@124 3155 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
kamg@124 3156 } else if (src.first()->is_FloatRegister()) {
kamg@124 3157 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
kamg@124 3158 FloatRegisterImpl::S)], "ack!");
kamg@124 3159 }
kamg@124 3160 if (dst.first()->is_Register()) {
kamg@124 3161 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
kamg@124 3162 } else if (dst.first()->is_FloatRegister()) {
kamg@124 3163 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
kamg@124 3164 FloatRegisterImpl::S)] = true;
kamg@124 3165 }
kamg@124 3166 #endif /* ASSERT */
kamg@124 3167
kamg@124 3168 switch (in_sig_bt[j_arg]) {
kamg@124 3169 case T_ARRAY:
kamg@124 3170 case T_OBJECT:
kamg@124 3171 {
kamg@124 3172 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
kamg@124 3173 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
kamg@124 3174 // need to unbox a one-slot value
kamg@124 3175 Register in_reg = L0;
kamg@124 3176 Register tmp = L2;
kamg@124 3177 if ( src.first()->is_reg() ) {
kamg@124 3178 in_reg = src.first()->as_Register();
kamg@124 3179 } else {
kamg@124 3180 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
kamg@124 3181 "must be");
kamg@124 3182 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
kamg@124 3183 }
kamg@124 3184 // If the final destination is an acceptable register
kamg@124 3185 if ( dst.first()->is_reg() ) {
kamg@124 3186 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
kamg@124 3187 tmp = dst.first()->as_Register();
kamg@124 3188 }
kamg@124 3189 }
kamg@124 3190
kamg@124 3191 Label skipUnbox;
kamg@124 3192 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
kamg@124 3193 __ mov(G0, tmp->successor());
kamg@124 3194 }
kamg@124 3195 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
kamg@124 3196 __ delayed()->mov(G0, tmp);
kamg@124 3197
kvn@153 3198 BasicType bt = out_sig_bt[c_arg];
kvn@153 3199 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
kvn@153 3200 switch (bt) {
kamg@124 3201 case T_BYTE:
kamg@124 3202 __ ldub(in_reg, box_offset, tmp); break;
kamg@124 3203 case T_SHORT:
kamg@124 3204 __ lduh(in_reg, box_offset, tmp); break;
kamg@124 3205 case T_INT:
kamg@124 3206 __ ld(in_reg, box_offset, tmp); break;
kamg@124 3207 case T_LONG:
kamg@124 3208 __ ld_long(in_reg, box_offset, tmp); break;
kamg@124 3209 default: ShouldNotReachHere();
kamg@124 3210 }
kamg@124 3211
kamg@124 3212 __ bind(skipUnbox);
kamg@124 3213 // If tmp wasn't final destination copy to final destination
kamg@124 3214 if (tmp == L2) {
kamg@124 3215 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
kamg@124 3216 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 3217 long_move(masm, tmp_as_VM, dst);
kamg@124 3218 } else {
kamg@124 3219 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
kamg@124 3220 }
kamg@124 3221 }
kamg@124 3222 if (out_sig_bt[c_arg] == T_LONG) {
kamg@124 3223 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
kamg@124 3224 ++c_arg; // move over the T_VOID to keep the loop indices in sync
kamg@124 3225 }
kamg@124 3226 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@124 3227 Register s =
kamg@124 3228 src.first()->is_reg() ? src.first()->as_Register() : L2;
kamg@124 3229 Register d =
kamg@124 3230 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 3231
kamg@124 3232 // We store the oop now so that the conversion pass can reach
kamg@124 3233 // while in the inner frame. This will be the only store if
kamg@124 3234 // the oop is NULL.
kamg@124 3235 if (s != L2) {
kamg@124 3236 // src is register
kamg@124 3237 if (d != L2) {
kamg@124 3238 // dst is register
kamg@124 3239 __ mov(s, d);
kamg@124 3240 } else {
kamg@124 3241 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3242 STACK_BIAS), "must be");
kamg@124 3243 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3244 }
kamg@124 3245 } else {
kamg@124 3246 // src not a register
kamg@124 3247 assert(Assembler::is_simm13(reg2offset(src.first()) +
kamg@124 3248 STACK_BIAS), "must be");
kamg@124 3249 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
kamg@124 3250 if (d == L2) {
kamg@124 3251 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3252 STACK_BIAS), "must be");
kamg@124 3253 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3254 }
kamg@124 3255 }
kamg@124 3256 } else if (out_sig_bt[c_arg] != T_VOID) {
kamg@124 3257 // Convert the arg to NULL
kamg@124 3258 if (dst.first()->is_reg()) {
kamg@124 3259 __ mov(G0, dst.first()->as_Register());
kamg@124 3260 } else {
kamg@124 3261 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@124 3262 STACK_BIAS), "must be");
kamg@124 3263 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@124 3264 }
kamg@124 3265 }
kamg@124 3266 }
kamg@124 3267 break;
kamg@124 3268 case T_VOID:
kamg@124 3269 break;
kamg@124 3270
kamg@124 3271 case T_FLOAT:
kamg@124 3272 if (src.first()->is_stack()) {
kamg@124 3273 // Stack to stack/reg is simple
kamg@124 3274 move32_64(masm, src, dst);
kamg@124 3275 } else {
kamg@124 3276 if (dst.first()->is_reg()) {
kamg@124 3277 // freg -> reg
kamg@124 3278 int off =
kamg@124 3279 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3280 Register d = dst.first()->as_Register();
kamg@124 3281 if (Assembler::is_simm13(off)) {
kamg@124 3282 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3283 SP, off);
kamg@124 3284 __ ld(SP, off, d);
kamg@124 3285 } else {
kamg@124 3286 if (conversion_off == noreg) {
kamg@124 3287 __ set(off, L6);
kamg@124 3288 conversion_off = L6;
kamg@124 3289 }
kamg@124 3290 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3291 SP, conversion_off);
kamg@124 3292 __ ld(SP, conversion_off , d);
kamg@124 3293 }
kamg@124 3294 } else {
kamg@124 3295 // freg -> mem
kamg@124 3296 int off = STACK_BIAS + reg2offset(dst.first());
kamg@124 3297 if (Assembler::is_simm13(off)) {
kamg@124 3298 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3299 SP, off);
kamg@124 3300 } else {
kamg@124 3301 if (conversion_off == noreg) {
kamg@124 3302 __ set(off, L6);
kamg@124 3303 conversion_off = L6;
kamg@124 3304 }
kamg@124 3305 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@124 3306 SP, conversion_off);
kamg@124 3307 }
kamg@124 3308 }
kamg@124 3309 }
kamg@124 3310 break;
kamg@124 3311
kamg@124 3312 case T_DOUBLE:
kamg@124 3313 assert( j_arg + 1 < total_args_passed &&
kamg@124 3314 in_sig_bt[j_arg + 1] == T_VOID &&
kamg@124 3315 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
kamg@124 3316 if (src.first()->is_stack()) {
kamg@124 3317 // Stack to stack/reg is simple
kamg@124 3318 long_move(masm, src, dst);
kamg@124 3319 } else {
kamg@124 3320 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@124 3321
kamg@124 3322 // Destination could be an odd reg on 32bit in which case
kamg@124 3323 // we can't load direct to the destination.
kamg@124 3324
kamg@124 3325 if (!d->is_even() && wordSize == 4) {
kamg@124 3326 d = L2;
kamg@124 3327 }
kamg@124 3328 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3329 if (Assembler::is_simm13(off)) {
kamg@124 3330 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 3331 SP, off);
kamg@124 3332 __ ld_long(SP, off, d);
kamg@124 3333 } else {
kamg@124 3334 if (conversion_off == noreg) {
kamg@124 3335 __ set(off, L6);
kamg@124 3336 conversion_off = L6;
kamg@124 3337 }
kamg@124 3338 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@124 3339 SP, conversion_off);
kamg@124 3340 __ ld_long(SP, conversion_off, d);
kamg@124 3341 }
kamg@124 3342 if (d == L2) {
kamg@124 3343 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 3344 }
kamg@124 3345 }
kamg@124 3346 break;
kamg@124 3347
kamg@124 3348 case T_LONG :
kamg@124 3349 // 32bit can't do a split move of something like g1 -> O0, O1
kamg@124 3350 // so use a memory temp
kamg@124 3351 if (src.is_single_phys_reg() && wordSize == 4) {
kamg@124 3352 Register tmp = L2;
kamg@124 3353 if (dst.first()->is_reg() &&
kamg@124 3354 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
kamg@124 3355 tmp = dst.first()->as_Register();
kamg@124 3356 }
kamg@124 3357
kamg@124 3358 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@124 3359 if (Assembler::is_simm13(off)) {
kamg@124 3360 __ stx(src.first()->as_Register(), SP, off);
kamg@124 3361 __ ld_long(SP, off, tmp);
kamg@124 3362 } else {
kamg@124 3363 if (conversion_off == noreg) {
kamg@124 3364 __ set(off, L6);
kamg@124 3365 conversion_off = L6;
kamg@124 3366 }
kamg@124 3367 __ stx(src.first()->as_Register(), SP, conversion_off);
kamg@124 3368 __ ld_long(SP, conversion_off, tmp);
kamg@124 3369 }
kamg@124 3370
kamg@124 3371 if (tmp == L2) {
kamg@124 3372 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@124 3373 }
kamg@124 3374 } else {
kamg@124 3375 long_move(masm, src, dst);
kamg@124 3376 }
kamg@124 3377 break;
kamg@124 3378
kamg@124 3379 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
kamg@124 3380
kamg@124 3381 default:
kamg@124 3382 move32_64(masm, src, dst);
kamg@124 3383 }
kamg@124 3384 }
kamg@124 3385
kamg@124 3386
kamg@124 3387 // If we have any strings we must store any register based arg to the stack
kamg@124 3388 // This includes any still live xmm registers too.
kamg@124 3389