view src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp @ 56154:be5865bda5b9

8229422: Taskqueue: Outdated selection of weak memory model platforms Reviewed-by: tschatzl, dholmes, drwhite
author mdoerr
date Mon, 12 Aug 2019 19:20:12 +0200
parents 9807daeb47c4
children dd4b4f273274
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const int StackAlignmentInBytes  = 16;

// Indicates whether the C calling conventions require that
// 32-bit integer argument values are extended to 64 bits.
const bool CCallingConventionRequiresIntsAsLongs = false;


// Aarch64 was not originally defined as multi-copy-atomic, but now is.
// See: "Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and
// Operational Models for ARMv8"
// So we could #define CPU_MULTI_COPY_ATOMIC but historically we have
// not done so.

// According to the ARMv8 ARM, "Concurrent modification and execution
// of instructions can lead to the resulting instruction performing
// any behavior that can be achieved by executing any sequence of
// instructions that can be executed from the same Exception level,
// except where the instruction before modification and the
// instruction after modification is a B, BL, NOP, BKPT, SVC, HVC, or
// SMC instruction."
// This makes the games we play when patching difficult, so when we
// come across an access that needs patching we deoptimize.  There are
// ways we can avoid this, but these would slow down C1-compiled code
// in the defauilt case.  We could revisit this decision if we get any
// evidence that it's worth doing.