changeset 49723:06ef6db47ec7

8201185: AARCH64: bfm instruction encoding hits assert on zero register Reviewed-by: dsamersoff
author dpochepk
date Mon, 09 Apr 2018 18:40:20 +0300
parents a47d1e21b3f1
children bf7f42f2f025
files src/hotspot/cpu/aarch64/assembler_aarch64.hpp
diffstat 1 files changed, 1 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Thu Apr 05 10:54:53 2018 +0200
+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp	Mon Apr 09 18:40:20 2018 +0300
@@ -819,7 +819,7 @@
   void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
     starti;                                                             \
     f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
-    rf(Rn, 5), rf(Rd, 0);                                               \
+    zrf(Rn, 5), rf(Rd, 0);                                              \
   }
 
   INSN(sbfmw, 0b0001001100);