changeset 49729:78d797e04484

8201359: Incorrect header guards after JDK-8198949 (Modularize arraycopy stub routine GC barriers) Reviewed-by: stefank, dholmes
author shade
date Tue, 10 Apr 2018 12:12:43 +0200
parents a1617a75c231
children c2761ef9fd95
files src/hotspot/cpu/s390/gc/shared/barrierSetAssembler_s390.hpp src/hotspot/cpu/s390/gc/shared/cardTableBarrierSetAssembler_s390.hpp src/hotspot/cpu/s390/gc/shared/modRefBarrierSetAssembler_s390.hpp src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp src/hotspot/cpu/zero/gc/shared/barrierSetAssembler_zero.hpp src/hotspot/share/gc/g1/g1BarrierSetAssembler.hpp
diffstat 6 files changed, 18 insertions(+), 18 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/s390/gc/shared/barrierSetAssembler_s390.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/cpu/s390/gc/shared/barrierSetAssembler_s390.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef CPU_S390_GC_G1_BARRIERSETASSEMBLER_S390_HPP
-#define CPU_S390_GC_G1_BARRIERSETASSEMBLER_S390_HPP
+#ifndef CPU_S390_GC_SHARED_BARRIERSETASSEMBLER_S390_HPP
+#define CPU_S390_GC_SHARED_BARRIERSETASSEMBLER_S390_HPP
 
 #include "asm/macroAssembler.hpp"
 #include "memory/allocation.hpp"
@@ -40,4 +40,4 @@
                                   Register dst, Register count, bool do_return = false);
 };
 
-#endif // CPU_S390_GC_G1_BARRIERSETASSEMBLER_S390_HPP
+#endif // CPU_S390_GC_SHARED_BARRIERSETASSEMBLER_S390_HPP
--- a/src/hotspot/cpu/s390/gc/shared/cardTableBarrierSetAssembler_s390.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/cpu/s390/gc/shared/cardTableBarrierSetAssembler_s390.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef CPU_X86_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_X86_HPP
-#define CPU_X86_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_X86_HPP
+#ifndef CPU_S390_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_S390_HPP
+#define CPU_S390_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_S390_HPP
 
 #include "asm/macroAssembler.hpp"
 #include "gc/shared/modRefBarrierSetAssembler.hpp"
@@ -35,4 +35,4 @@
                                                 bool do_return);
 };
 
-#endif // CPU_X86_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_X86_HPP
+#endif // CPU_S390_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_S390_HPP
--- a/src/hotspot/cpu/s390/gc/shared/modRefBarrierSetAssembler_s390.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/cpu/s390/gc/shared/modRefBarrierSetAssembler_s390.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef CPU_X86_GC_SHARED_MODREFBARRIERSETASSEMBLER_X86_HPP
-#define CPU_X86_GC_SHARED_MODREFBARRIERSETASSEMBLER_X86_HPP
+#ifndef CPU_S390_GC_SHARED_MODREFBARRIERSETASSEMBLER_S390_HPP
+#define CPU_S390_GC_SHARED_MODREFBARRIERSETASSEMBLER_S390_HPP
 
 #include "asm/macroAssembler.hpp"
 #include "gc/shared/barrierSetAssembler.hpp"
@@ -42,4 +42,4 @@
                                   Register dst, Register count, bool do_return = false);
 };
 
-#endif // CPU_X86_GC_SHARED_MODREFBARRIERSETASSEMBLER_X86_HPP
+#endif // CPU_S390_GC_SHARED_MODREFBARRIERSETASSEMBLER_S390_HPP
--- a/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/cpu/x86/gc/shared/barrierSetAssembler_x86.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP
-#define CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP
+#ifndef CPU_X86_GC_SHARED_BARRIERSETASSEMBLER_X86_HPP
+#define CPU_X86_GC_SHARED_BARRIERSETASSEMBLER_X86_HPP
 
 #include "asm/macroAssembler.hpp"
 #include "memory/allocation.hpp"
@@ -40,4 +40,4 @@
                                   Register src, Register dst, Register count) {}
 };
 
-#endif // CPU_X86_GC_G1_BARRIERSETASSEMBLER_X86_HPP
+#endif // CPU_X86_GC_SHARED_BARRIERSETASSEMBLER_X86_HPP
--- a/src/hotspot/cpu/zero/gc/shared/barrierSetAssembler_zero.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/cpu/zero/gc/shared/barrierSetAssembler_zero.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -22,9 +22,9 @@
  *
  */
 
-#ifndef CPU_ZERO_GC_G1_BARRIERSETASSEMBLER_ZERO_HPP
-#define CPU_ZERO_GC_G1_BARRIERSETASSEMBLER_ZERO_HPP
+#ifndef CPU_ZERO_GC_SHARED_BARRIERSETASSEMBLER_ZERO_HPP
+#define CPU_ZERO_GC_SHARED_BARRIERSETASSEMBLER_ZERO_HPP
 
 class BarrierSetAssembler;
 
-#endif // CPU_ZERO_GC_G1_BARRIERSETASSEMBLER_ZERO_HPP
+#endif // CPU_ZERO_GC_SHARED_BARRIERSETASSEMBLER_ZERO_HPP
--- a/src/hotspot/share/gc/g1/g1BarrierSetAssembler.hpp	Thu Apr 05 20:09:33 2018 -0400
+++ b/src/hotspot/share/gc/g1/g1BarrierSetAssembler.hpp	Tue Apr 10 12:12:43 2018 +0200
@@ -22,11 +22,11 @@
  *
  */
 
-#ifndef SHARE_GC_SHARED_G1BARRIERSETASSEMBLER_HPP
-#define SHARE_GC_SHARED_G1BARRIERSETASSEMBLER_HPP
+#ifndef SHARE_GC_G1_G1BARRIERSETASSEMBLER_HPP
+#define SHARE_GC_G1_G1BARRIERSETASSEMBLER_HPP
 
 #include "utilities/macros.hpp"
 
 #include CPU_HEADER(gc/g1/g1BarrierSetAssembler)
 
-#endif // SHARE_GC_SHARED_G1BARRIERSETASSEMBLER_HPP
+#endif // SHARE_GC_G1_G1BARRIERSETASSEMBLER_HPP