changeset 49173:cf4562e8a3f9

8198293: AARCH64 - Add CPU detection code for Cavium Thunder X2 Reviewed-by: dsamersoff
author dchuyko
date Tue, 27 Feb 2018 15:56:40 +0300
parents f047fae0169c
children f842bb1e3885
files src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
diffstat 1 files changed, 17 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp	Tue Feb 27 11:45:04 2018 +0100
+++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp	Tue Feb 27 15:56:40 2018 +0300
@@ -193,7 +193,9 @@
   }
 
   // Enable vendor specific features
-  if (_cpu == CPU_CAVIUM) {
+
+  // ThunderX
+  if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
     if (_variant == 0) _features |= CPU_DMB_ATOMICS;
     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
@@ -202,6 +204,20 @@
       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
     }
   }
+  // ThunderX2
+  if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
+      (_cpu == CPU_BROADCOM && (_model == 0x516))) {
+    if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
+      FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
+    }
+    if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
+      FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
+    }
+    if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
+      FLAG_SET_DEFAULT(UseFPUForSpilling, true);
+    }
+  }
+
   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
   if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
   // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)