annotate src/cpu/x86/vm/x86_64.ad @ 8290:382e9e4b3b71

8068945: Use RBP register as proper frame pointer in JIT compiled code on x86 Summary: Introduce the PreserveFramePointer flag to control if RBP is used as the frame pointer or as a general purpose register. Reviewed-by: kvn, roland, dlong, enevill, shade
author zmajo
date Mon, 27 Apr 2015 10:49:43 +0200
parents e78935d6bd88
children bd72804c91d6
rev   line source
duke@0 1 //
psandoz@7844 2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // Specify priority of register selection within phases of register
duke@0 135 // allocation. Highest priority is first. A useful heuristic is to
duke@0 136 // give registers a low priority when they are required by machine
duke@0 137 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 138 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 139 // which participate in fixed calling sequences should come last.
duke@0 140 // Registers which are used as pairs must fall on an even boundary.
duke@0 141
duke@0 142 alloc_class chunk0(R10, R10_H,
duke@0 143 R11, R11_H,
duke@0 144 R8, R8_H,
duke@0 145 R9, R9_H,
duke@0 146 R12, R12_H,
duke@0 147 RCX, RCX_H,
duke@0 148 RBX, RBX_H,
duke@0 149 RDI, RDI_H,
duke@0 150 RDX, RDX_H,
duke@0 151 RSI, RSI_H,
duke@0 152 RAX, RAX_H,
duke@0 153 RBP, RBP_H,
duke@0 154 R13, R13_H,
duke@0 155 R14, R14_H,
duke@0 156 R15, R15_H,
duke@0 157 RSP, RSP_H);
duke@0 158
duke@0 159
duke@0 160 //----------Architecture Description Register Classes--------------------------
duke@0 161 // Several register classes are automatically defined based upon information in
duke@0 162 // this architecture description.
duke@0 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 167 //
duke@0 168
zmajo@8290 169 // Empty register class.
zmajo@8290 170 reg_class no_reg();
zmajo@8290 171
zmajo@8290 172 // Class for all pointer registers (including RSP and RBP)
zmajo@8290 173 reg_class any_reg_with_rbp(RAX, RAX_H,
zmajo@8290 174 RDX, RDX_H,
zmajo@8290 175 RBP, RBP_H,
zmajo@8290 176 RDI, RDI_H,
zmajo@8290 177 RSI, RSI_H,
zmajo@8290 178 RCX, RCX_H,
zmajo@8290 179 RBX, RBX_H,
zmajo@8290 180 RSP, RSP_H,
zmajo@8290 181 R8, R8_H,
zmajo@8290 182 R9, R9_H,
zmajo@8290 183 R10, R10_H,
zmajo@8290 184 R11, R11_H,
zmajo@8290 185 R12, R12_H,
zmajo@8290 186 R13, R13_H,
zmajo@8290 187 R14, R14_H,
zmajo@8290 188 R15, R15_H);
zmajo@8290 189
zmajo@8290 190 // Class for all pointer registers (including RSP, but excluding RBP)
zmajo@8290 191 reg_class any_reg_no_rbp(RAX, RAX_H,
zmajo@8290 192 RDX, RDX_H,
zmajo@8290 193 RDI, RDI_H,
zmajo@8290 194 RSI, RSI_H,
zmajo@8290 195 RCX, RCX_H,
zmajo@8290 196 RBX, RBX_H,
zmajo@8290 197 RSP, RSP_H,
zmajo@8290 198 R8, R8_H,
zmajo@8290 199 R9, R9_H,
zmajo@8290 200 R10, R10_H,
zmajo@8290 201 R11, R11_H,
zmajo@8290 202 R12, R12_H,
zmajo@8290 203 R13, R13_H,
zmajo@8290 204 R14, R14_H,
zmajo@8290 205 R15, R15_H);
zmajo@8290 206
zmajo@8290 207 // Dynamic register class that selects at runtime between register classes
zmajo@8290 208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
zmajo@8290 209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
zmajo@8290 210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 211
zmajo@8290 212 // Class for all pointer registers (excluding RSP)
zmajo@8290 213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
zmajo@8290 214 RDX, RDX_H,
zmajo@8290 215 RBP, RBP_H,
zmajo@8290 216 RDI, RDI_H,
zmajo@8290 217 RSI, RSI_H,
zmajo@8290 218 RCX, RCX_H,
zmajo@8290 219 RBX, RBX_H,
zmajo@8290 220 R8, R8_H,
zmajo@8290 221 R9, R9_H,
zmajo@8290 222 R10, R10_H,
zmajo@8290 223 R11, R11_H,
zmajo@8290 224 R13, R13_H,
zmajo@8290 225 R14, R14_H);
zmajo@8290 226
zmajo@8290 227 // Class for all pointer registers (excluding RSP and RBP)
zmajo@8290 228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
zmajo@8290 229 RDX, RDX_H,
duke@0 230 RDI, RDI_H,
duke@0 231 RSI, RSI_H,
duke@0 232 RCX, RCX_H,
duke@0 233 RBX, RBX_H,
duke@0 234 R8, R8_H,
duke@0 235 R9, R9_H,
duke@0 236 R10, R10_H,
duke@0 237 R11, R11_H,
duke@0 238 R13, R13_H,
duke@0 239 R14, R14_H);
duke@0 240
zmajo@8290 241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
zmajo@8290 242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 243
zmajo@8290 244 // Class for all pointer registers (excluding RAX and RSP)
zmajo@8290 245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
zmajo@8290 246 RBP, RBP_H,
zmajo@8290 247 RDI, RDI_H,
zmajo@8290 248 RSI, RSI_H,
zmajo@8290 249 RCX, RCX_H,
zmajo@8290 250 RBX, RBX_H,
zmajo@8290 251 R8, R8_H,
zmajo@8290 252 R9, R9_H,
zmajo@8290 253 R10, R10_H,
zmajo@8290 254 R11, R11_H,
zmajo@8290 255 R13, R13_H,
zmajo@8290 256 R14, R14_H);
zmajo@8290 257
zmajo@8290 258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
zmajo@8290 259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
zmajo@8290 260 RDI, RDI_H,
zmajo@8290 261 RSI, RSI_H,
zmajo@8290 262 RCX, RCX_H,
zmajo@8290 263 RBX, RBX_H,
zmajo@8290 264 R8, R8_H,
zmajo@8290 265 R9, R9_H,
zmajo@8290 266 R10, R10_H,
zmajo@8290 267 R11, R11_H,
zmajo@8290 268 R13, R13_H,
zmajo@8290 269 R14, R14_H);
zmajo@8290 270
zmajo@8290 271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
zmajo@8290 272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 273
zmajo@8290 274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
zmajo@8290 275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
zmajo@8290 276 RBP, RBP_H,
zmajo@8290 277 RDI, RDI_H,
zmajo@8290 278 RSI, RSI_H,
zmajo@8290 279 RCX, RCX_H,
zmajo@8290 280 R8, R8_H,
zmajo@8290 281 R9, R9_H,
zmajo@8290 282 R10, R10_H,
zmajo@8290 283 R11, R11_H,
zmajo@8290 284 R13, R13_H,
zmajo@8290 285 R14, R14_H);
zmajo@8290 286
zmajo@8290 287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
zmajo@8290 288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
zmajo@8290 289 RDI, RDI_H,
zmajo@8290 290 RSI, RSI_H,
zmajo@8290 291 RCX, RCX_H,
zmajo@8290 292 R8, R8_H,
zmajo@8290 293 R9, R9_H,
zmajo@8290 294 R10, R10_H,
zmajo@8290 295 R11, R11_H,
zmajo@8290 296 R13, R13_H,
zmajo@8290 297 R14, R14_H);
zmajo@8290 298
zmajo@8290 299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
zmajo@8290 300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
duke@0 301
duke@0 302 // Singleton class for RAX pointer register
duke@0 303 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 304
duke@0 305 // Singleton class for RBX pointer register
duke@0 306 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 307
duke@0 308 // Singleton class for RSI pointer register
duke@0 309 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 310
duke@0 311 // Singleton class for RDI pointer register
duke@0 312 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 313
duke@0 314 // Singleton class for stack pointer
duke@0 315 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 316
duke@0 317 // Singleton class for TLS pointer
duke@0 318 reg_class ptr_r15_reg(R15, R15_H);
duke@0 319
zmajo@8290 320 // Class for all long registers (excluding RSP)
zmajo@8290 321 reg_class long_reg_with_rbp(RAX, RAX_H,
zmajo@8290 322 RDX, RDX_H,
zmajo@8290 323 RBP, RBP_H,
zmajo@8290 324 RDI, RDI_H,
zmajo@8290 325 RSI, RSI_H,
zmajo@8290 326 RCX, RCX_H,
zmajo@8290 327 RBX, RBX_H,
zmajo@8290 328 R8, R8_H,
zmajo@8290 329 R9, R9_H,
zmajo@8290 330 R10, R10_H,
zmajo@8290 331 R11, R11_H,
zmajo@8290 332 R13, R13_H,
zmajo@8290 333 R14, R14_H);
zmajo@8290 334
zmajo@8290 335 // Class for all long registers (excluding RSP and RBP)
zmajo@8290 336 reg_class long_reg_no_rbp(RAX, RAX_H,
duke@0 337 RDX, RDX_H,
duke@0 338 RDI, RDI_H,
duke@0 339 RSI, RSI_H,
duke@0 340 RCX, RCX_H,
duke@0 341 RBX, RBX_H,
duke@0 342 R8, R8_H,
duke@0 343 R9, R9_H,
duke@0 344 R10, R10_H,
duke@0 345 R11, R11_H,
duke@0 346 R13, R13_H,
duke@0 347 R14, R14_H);
duke@0 348
zmajo@8290 349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
zmajo@8290 350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 351
zmajo@8290 352 // Class for all long registers (excluding RAX, RDX and RSP)
zmajo@8290 353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
zmajo@8290 354 RDI, RDI_H,
zmajo@8290 355 RSI, RSI_H,
zmajo@8290 356 RCX, RCX_H,
zmajo@8290 357 RBX, RBX_H,
zmajo@8290 358 R8, R8_H,
zmajo@8290 359 R9, R9_H,
zmajo@8290 360 R10, R10_H,
zmajo@8290 361 R11, R11_H,
zmajo@8290 362 R13, R13_H,
zmajo@8290 363 R14, R14_H);
zmajo@8290 364
zmajo@8290 365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
zmajo@8290 366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
zmajo@8290 367 RSI, RSI_H,
zmajo@8290 368 RCX, RCX_H,
zmajo@8290 369 RBX, RBX_H,
zmajo@8290 370 R8, R8_H,
zmajo@8290 371 R9, R9_H,
zmajo@8290 372 R10, R10_H,
zmajo@8290 373 R11, R11_H,
zmajo@8290 374 R13, R13_H,
zmajo@8290 375 R14, R14_H);
zmajo@8290 376
zmajo@8290 377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
zmajo@8290 378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 379
zmajo@8290 380 // Class for all long registers (excluding RCX and RSP)
zmajo@8290 381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
zmajo@8290 382 RDI, RDI_H,
zmajo@8290 383 RSI, RSI_H,
zmajo@8290 384 RAX, RAX_H,
zmajo@8290 385 RDX, RDX_H,
zmajo@8290 386 RBX, RBX_H,
zmajo@8290 387 R8, R8_H,
zmajo@8290 388 R9, R9_H,
zmajo@8290 389 R10, R10_H,
zmajo@8290 390 R11, R11_H,
zmajo@8290 391 R13, R13_H,
zmajo@8290 392 R14, R14_H);
zmajo@8290 393
zmajo@8290 394 // Class for all long registers (excluding RCX, RSP, and RBP)
zmajo@8290 395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
zmajo@8290 396 RSI, RSI_H,
zmajo@8290 397 RAX, RAX_H,
zmajo@8290 398 RDX, RDX_H,
zmajo@8290 399 RBX, RBX_H,
zmajo@8290 400 R8, R8_H,
zmajo@8290 401 R9, R9_H,
zmajo@8290 402 R10, R10_H,
zmajo@8290 403 R11, R11_H,
zmajo@8290 404 R13, R13_H,
zmajo@8290 405 R14, R14_H);
zmajo@8290 406
zmajo@8290 407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
zmajo@8290 408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 409
duke@0 410 // Singleton class for RAX long register
duke@0 411 reg_class long_rax_reg(RAX, RAX_H);
duke@0 412
duke@0 413 // Singleton class for RCX long register
duke@0 414 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 415
duke@0 416 // Singleton class for RDX long register
duke@0 417 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 418
zmajo@8290 419 // Class for all int registers (excluding RSP)
zmajo@8290 420 reg_class int_reg_with_rbp(RAX,
zmajo@8290 421 RDX,
zmajo@8290 422 RBP,
zmajo@8290 423 RDI,
zmajo@8290 424 RSI,
zmajo@8290 425 RCX,
zmajo@8290 426 RBX,
zmajo@8290 427 R8,
zmajo@8290 428 R9,
zmajo@8290 429 R10,
zmajo@8290 430 R11,
zmajo@8290 431 R13,
zmajo@8290 432 R14);
zmajo@8290 433
zmajo@8290 434 // Class for all int registers (excluding RSP and RBP)
zmajo@8290 435 reg_class int_reg_no_rbp(RAX,
duke@0 436 RDX,
duke@0 437 RDI,
duke@0 438 RSI,
zmajo@8290 439 RCX,
duke@0 440 RBX,
duke@0 441 R8,
duke@0 442 R9,
duke@0 443 R10,
duke@0 444 R11,
duke@0 445 R13,
duke@0 446 R14);
duke@0 447
zmajo@8290 448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
zmajo@8290 449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 450
zmajo@8290 451 // Class for all int registers (excluding RCX and RSP)
zmajo@8290 452 reg_class int_no_rcx_reg_with_rbp(RAX,
zmajo@8290 453 RDX,
zmajo@8290 454 RBP,
zmajo@8290 455 RDI,
zmajo@8290 456 RSI,
zmajo@8290 457 RBX,
zmajo@8290 458 R8,
zmajo@8290 459 R9,
zmajo@8290 460 R10,
zmajo@8290 461 R11,
zmajo@8290 462 R13,
zmajo@8290 463 R14);
zmajo@8290 464
zmajo@8290 465 // Class for all int registers (excluding RCX, RSP, and RBP)
zmajo@8290 466 reg_class int_no_rcx_reg_no_rbp(RAX,
zmajo@8290 467 RDX,
zmajo@8290 468 RDI,
zmajo@8290 469 RSI,
zmajo@8290 470 RBX,
zmajo@8290 471 R8,
zmajo@8290 472 R9,
zmajo@8290 473 R10,
zmajo@8290 474 R11,
zmajo@8290 475 R13,
zmajo@8290 476 R14);
zmajo@8290 477
zmajo@8290 478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
zmajo@8290 479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 480
zmajo@8290 481 // Class for all int registers (excluding RAX, RDX, and RSP)
zmajo@8290 482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
zmajo@8290 483 RDI,
zmajo@8290 484 RSI,
zmajo@8290 485 RCX,
zmajo@8290 486 RBX,
zmajo@8290 487 R8,
zmajo@8290 488 R9,
zmajo@8290 489 R10,
zmajo@8290 490 R11,
zmajo@8290 491 R13,
zmajo@8290 492 R14);
zmajo@8290 493
zmajo@8290 494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
zmajo@8290 495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
zmajo@8290 496 RSI,
zmajo@8290 497 RCX,
zmajo@8290 498 RBX,
zmajo@8290 499 R8,
zmajo@8290 500 R9,
zmajo@8290 501 R10,
zmajo@8290 502 R11,
zmajo@8290 503 R13,
zmajo@8290 504 R14);
zmajo@8290 505
zmajo@8290 506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
zmajo@8290 507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
duke@0 508
duke@0 509 // Singleton class for RAX int register
duke@0 510 reg_class int_rax_reg(RAX);
duke@0 511
duke@0 512 // Singleton class for RBX int register
duke@0 513 reg_class int_rbx_reg(RBX);
duke@0 514
duke@0 515 // Singleton class for RCX int register
duke@0 516 reg_class int_rcx_reg(RCX);
duke@0 517
duke@0 518 // Singleton class for RCX int register
duke@0 519 reg_class int_rdx_reg(RDX);
duke@0 520
duke@0 521 // Singleton class for RCX int register
duke@0 522 reg_class int_rdi_reg(RDI);
duke@0 523
duke@0 524 // Singleton class for instruction pointer
duke@0 525 // reg_class ip_reg(RIP);
duke@0 526
kvn@3447 527 %}
duke@0 528
duke@0 529 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 530 // This is a block of C++ code which provides values, functions, and
duke@0 531 // definitions necessary in the rest of the architecture description
duke@0 532 source %{
never@304 533 #define RELOC_IMM64 Assembler::imm_operand
duke@0 534 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 535
duke@0 536 #define __ _masm.
duke@0 537
kvn@4438 538 static int clear_avx_size() {
kvn@4438 539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
kvn@4438 540 }
twisti@1137 541
duke@0 542 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 543 // from the start of the call to the point where the return address
duke@0 544 // will point.
duke@0 545 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 546 {
twisti@1137 547 int offset = 5; // 5 bytes from start of call to where return address points
zmajo@8290 548 offset += clear_avx_size();
twisti@1137 549 return offset;
duke@0 550 }
duke@0 551
duke@0 552 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 553 {
kvn@4438 554 int offset = 15; // 15 bytes from start of call to where return address points
kvn@4438 555 offset += clear_avx_size();
kvn@4438 556 return offset;
duke@0 557 }
duke@0 558
kvn@4438 559 int MachCallRuntimeNode::ret_addr_offset() {
kvn@4438 560 int offset = 13; // movq r10,#addr; callq (r10)
kvn@4438 561 offset += clear_avx_size();
kvn@4438 562 return offset;
kvn@4438 563 }
duke@0 564
iveresov@2251 565 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 566 // it does if the polling page is more than disp32 away.
duke@0 567 bool SafePointNode::needs_polling_address_input()
duke@0 568 {
iveresov@2251 569 return Assembler::is_polling_page_far();
duke@0 570 }
duke@0 571
duke@0 572 //
duke@0 573 // Compute padding required for nodes which need alignment
duke@0 574 //
duke@0 575
duke@0 576 // The address of the call instruction needs to be 4-byte aligned to
duke@0 577 // ensure that it does not span a cache line so that it can be patched.
duke@0 578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 579 {
kvn@4438 580 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 581 current_offset += 1; // skip call opcode byte
duke@0 582 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 583 }
duke@0 584
duke@0 585 // The address of the call instruction needs to be 4-byte aligned to
duke@0 586 // ensure that it does not span a cache line so that it can be patched.
duke@0 587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 588 {
kvn@4438 589 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 590 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 591 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 592 }
duke@0 593
duke@0 594 // EMIT_RM()
twisti@1668 595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 597 cbuf.insts()->emit_int8(c);
duke@0 598 }
duke@0 599
duke@0 600 // EMIT_CC()
twisti@1668 601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 602 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 603 cbuf.insts()->emit_int8(c);
duke@0 604 }
duke@0 605
duke@0 606 // EMIT_OPCODE()
twisti@1668 607 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 608 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 609 }
duke@0 610
duke@0 611 // EMIT_OPCODE() w/ relocation information
duke@0 612 void emit_opcode(CodeBuffer &cbuf,
duke@0 613 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 614 {
twisti@1668 615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 616 emit_opcode(cbuf, code);
duke@0 617 }
duke@0 618
duke@0 619 // EMIT_D8()
twisti@1668 620 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 621 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 622 }
duke@0 623
duke@0 624 // EMIT_D16()
twisti@1668 625 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 626 cbuf.insts()->emit_int16(d16);
duke@0 627 }
duke@0 628
duke@0 629 // EMIT_D32()
twisti@1668 630 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 631 cbuf.insts()->emit_int32(d32);
duke@0 632 }
duke@0 633
duke@0 634 // EMIT_D64()
twisti@1668 635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 636 cbuf.insts()->emit_int64(d64);
duke@0 637 }
duke@0 638
duke@0 639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 640 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 641 int d32,
duke@0 642 relocInfo::relocType reloc,
duke@0 643 int format)
duke@0 644 {
duke@0 645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 647 cbuf.insts()->emit_int32(d32);
duke@0 648 }
duke@0 649
duke@0 650 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 652 #ifdef ASSERT
duke@0 653 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
coleenp@3602 655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
hseigel@5349 656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 657 }
duke@0 658 #endif
twisti@1668 659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 660 cbuf.insts()->emit_int32(d32);
duke@0 661 }
duke@0 662
duke@0 663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 664 address next_ip = cbuf.insts_end() + 4;
duke@0 665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 666 external_word_Relocation::spec(addr),
duke@0 667 RELOC_DISP32);
duke@0 668 }
duke@0 669
duke@0 670
duke@0 671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 674 cbuf.insts()->emit_int64(d64);
duke@0 675 }
duke@0 676
duke@0 677 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 679 #ifdef ASSERT
duke@0 680 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
coleenp@3602 682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
hseigel@5349 683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
jrose@989 684 "cannot embed scavengable oops in code");
duke@0 685 }
duke@0 686 #endif
twisti@1668 687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 688 cbuf.insts()->emit_int64(d64);
duke@0 689 }
duke@0 690
duke@0 691 // Access stack slot for load or store
duke@0 692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 693 {
duke@0 694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 695 if (-0x80 <= disp && disp < 0x80) {
duke@0 696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 698 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 699 } else {
duke@0 700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 702 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 703 }
duke@0 704 }
duke@0 705
duke@0 706 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 707 void encode_RegMem(CodeBuffer &cbuf,
duke@0 708 int reg,
coleenp@3602 709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
duke@0 710 {
coleenp@3602 711 assert(disp_reloc == relocInfo::none, "cannot have disp");
duke@0 712 int regenc = reg & 7;
duke@0 713 int baseenc = base & 7;
duke@0 714 int indexenc = index & 7;
duke@0 715
duke@0 716 // There is no index & no scale, use form without SIB byte
duke@0 717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
coleenp@3602 721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 722 // If 8-bit displacement, mode 0x1
duke@0 723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 724 emit_d8(cbuf, disp);
duke@0 725 } else {
duke@0 726 // If 32-bit displacement
duke@0 727 if (base == -1) { // Special flag for absolute address
duke@0 728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
coleenp@3602 729 if (disp_reloc != relocInfo::none) {
duke@0 730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 731 } else {
duke@0 732 emit_d32(cbuf, disp);
duke@0 733 }
duke@0 734 } else {
duke@0 735 // Normal base + offset
duke@0 736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
coleenp@3602 737 if (disp_reloc != relocInfo::none) {
duke@0 738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 739 } else {
duke@0 740 emit_d32(cbuf, disp);
duke@0 741 }
duke@0 742 }
duke@0 743 }
duke@0 744 } else {
duke@0 745 // Else, encode with the SIB byte
duke@0 746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 748 // If no displacement
duke@0 749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 750 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 751 } else {
coleenp@3602 752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 753 // If 8-bit displacement, mode 0x1
duke@0 754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 755 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 756 emit_d8(cbuf, disp);
duke@0 757 } else {
duke@0 758 // If 32-bit displacement
duke@0 759 if (base == 0x04 ) {
duke@0 760 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 762 } else {
duke@0 763 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 764 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 765 }
coleenp@3602 766 if (disp_reloc != relocInfo::none) {
duke@0 767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 768 } else {
duke@0 769 emit_d32(cbuf, disp);
duke@0 770 }
duke@0 771 }
duke@0 772 }
duke@0 773 }
duke@0 774 }
duke@0 775
never@2545 776 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 778 Label exit;
never@2545 779 __ jccb(Assembler::noParity, exit);
never@2545 780 __ pushf();
kvn@2953 781 //
kvn@2953 782 // comiss/ucomiss instructions set ZF,PF,CF flags and
kvn@2953 783 // zero OF,AF,SF for NaN values.
kvn@2953 784 // Fixup flags by zeroing ZF,PF so that compare of NaN
kvn@2953 785 // values returns 'less than' result (CF is set).
kvn@2953 786 // Leave the rest of flags unchanged.
kvn@2953 787 //
kvn@2953 788 // 7 6 5 4 3 2 1 0
kvn@2953 789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
kvn@2953 790 // 0 0 1 0 1 0 1 1 (0x2B)
kvn@2953 791 //
never@2545 792 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 793 __ popf();
never@2545 794 __ bind(exit);
kvn@2953 795 }
kvn@2953 796
kvn@2953 797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
kvn@2953 798 Label done;
kvn@2953 799 __ movl(dst, -1);
kvn@2953 800 __ jcc(Assembler::parity, done);
kvn@2953 801 __ jcc(Assembler::below, done);
kvn@2953 802 __ setb(Assembler::notEqual, dst);
kvn@2953 803 __ movzbl(dst, dst);
kvn@2953 804 __ bind(done);
never@2545 805 }
never@2545 806
duke@0 807
duke@0 808 //=============================================================================
twisti@1915 809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 810
twisti@2875 811 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 812 return 0; // absolute addressing, no offset
twisti@2875 813 }
twisti@2875 814
goetz@5982 815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
goetz@5982 816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
goetz@5982 817 ShouldNotReachHere();
goetz@5982 818 }
goetz@5982 819
twisti@1915 820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 821 // Empty encoding
twisti@1915 822 }
twisti@1915 823
twisti@1915 824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 825 return 0;
twisti@1915 826 }
twisti@1915 827
twisti@1915 828 #ifndef PRODUCT
twisti@1915 829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 830 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 831 }
twisti@1915 832 #endif
twisti@1915 833
twisti@1915 834
twisti@1915 835 //=============================================================================
duke@0 836 #ifndef PRODUCT
kvn@3139 837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
duke@0 838 Compile* C = ra_->C;
duke@0 839
roland@6307 840 int framesize = C->frame_size_in_bytes();
roland@6307 841 int bangsize = C->bang_size_in_bytes();
duke@0 842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
kvn@3139 843 // Remove wordSize for return addr which is already pushed.
kvn@3139 844 framesize -= wordSize;
kvn@3139 845
roland@6307 846 if (C->need_stack_bang(bangsize)) {
kvn@3139 847 framesize -= wordSize;
roland@6307 848 st->print("# stack bang (%d bytes)", bangsize);
kvn@3139 849 st->print("\n\t");
kvn@3139 850 st->print("pushq rbp\t# Save rbp");
zmajo@8290 851 if (PreserveFramePointer) {
zmajo@8290 852 st->print("\n\t");
zmajo@8290 853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
zmajo@8290 854 }
kvn@3139 855 if (framesize) {
kvn@3139 856 st->print("\n\t");
kvn@3139 857 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 858 }
kvn@3139 859 } else {
kvn@3139 860 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 861 st->print("\n\t");
kvn@3139 862 framesize -= wordSize;
zmajo@8290 863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
zmajo@8290 864 if (PreserveFramePointer) {
zmajo@8290 865 st->print("\n\t");
zmajo@8290 866 st->print("movq rbp, [rsp + #%d]\t# Save the caller's SP into rbp", (framesize + wordSize));
zmajo@8290 867 }
duke@0 868 }
duke@0 869
duke@0 870 if (VerifyStackAtCalls) {
kvn@3139 871 st->print("\n\t");
kvn@3139 872 framesize -= wordSize;
kvn@3139 873 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
kvn@3139 874 #ifdef ASSERT
kvn@3139 875 st->print("\n\t");
kvn@3139 876 st->print("# stack alignment check");
kvn@3139 877 #endif
duke@0 878 }
kvn@3139 879 st->cr();
duke@0 880 }
duke@0 881 #endif
duke@0 882
kvn@3139 883 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 884 Compile* C = ra_->C;
kvn@3139 885 MacroAssembler _masm(&cbuf);
duke@0 886
roland@6307 887 int framesize = C->frame_size_in_bytes();
roland@6307 888 int bangsize = C->bang_size_in_bytes();
roland@6307 889
roland@6307 890 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
duke@0 891
twisti@1668 892 C->set_frame_complete(cbuf.insts_size());
duke@0 893
twisti@2875 894 if (C->has_mach_constant_base_node()) {
twisti@2875 895 // NOTE: We set the table base offset here because users might be
twisti@2875 896 // emitted before MachConstantBaseNode.
twisti@2875 897 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 898 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 899 }
duke@0 900 }
duke@0 901
duke@0 902 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 903 {
duke@0 904 return MachNode::size(ra_); // too many variables; just compute it
duke@0 905 // the hard way
duke@0 906 }
duke@0 907
duke@0 908 int MachPrologNode::reloc() const
duke@0 909 {
duke@0 910 return 0; // a large enough number
duke@0 911 }
duke@0 912
duke@0 913 //=============================================================================
duke@0 914 #ifndef PRODUCT
duke@0 915 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 916 {
duke@0 917 Compile* C = ra_->C;
kvn@4438 918 if (C->max_vector_size() > 16) {
kvn@4438 919 st->print("vzeroupper");
kvn@4438 920 st->cr(); st->print("\t");
kvn@4438 921 }
kvn@4438 922
roland@6307 923 int framesize = C->frame_size_in_bytes();
duke@0 924 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 925 // Remove word for return adr already pushed
duke@0 926 // and RBP
duke@0 927 framesize -= 2*wordSize;
duke@0 928
duke@0 929 if (framesize) {
iveresov@2251 930 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 931 st->print("\t");
duke@0 932 }
duke@0 933
iveresov@2251 934 st->print_cr("popq rbp");
duke@0 935 if (do_polling() && C->is_method_compilation()) {
duke@0 936 st->print("\t");
iveresov@2251 937 if (Assembler::is_polling_page_far()) {
iveresov@2251 938 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 939 "testl rax, [rscratch1]\t"
iveresov@2251 940 "# Safepoint: poll for GC");
iveresov@2251 941 } else {
iveresov@2251 942 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 943 "# Safepoint: poll for GC");
iveresov@2251 944 }
duke@0 945 }
duke@0 946 }
duke@0 947 #endif
duke@0 948
duke@0 949 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 950 {
duke@0 951 Compile* C = ra_->C;
kvn@4438 952 if (C->max_vector_size() > 16) {
kvn@4438 953 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 954 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 955 MacroAssembler _masm(&cbuf);
kvn@4438 956 __ vzeroupper();
kvn@4438 957 }
kvn@4438 958
roland@6307 959 int framesize = C->frame_size_in_bytes();
duke@0 960 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 961 // Remove word for return adr already pushed
duke@0 962 // and RBP
duke@0 963 framesize -= 2*wordSize;
duke@0 964
duke@0 965 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 966
duke@0 967 if (framesize) {
duke@0 968 emit_opcode(cbuf, Assembler::REX_W);
duke@0 969 if (framesize < 0x80) {
duke@0 970 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 971 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 972 emit_d8(cbuf, framesize);
duke@0 973 } else {
duke@0 974 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 975 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 976 emit_d32(cbuf, framesize);
duke@0 977 }
duke@0 978 }
duke@0 979
duke@0 980 // popq rbp
duke@0 981 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 982
duke@0 983 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 984 MacroAssembler _masm(&cbuf);
iveresov@2251 985 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 986 if (Assembler::is_polling_page_far()) {
iveresov@2251 987 __ lea(rscratch1, polling_page);
iveresov@2251 988 __ relocate(relocInfo::poll_return_type);
iveresov@2251 989 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 990 } else {
iveresov@2251 991 __ testl(rax, polling_page);
iveresov@2251 992 }
duke@0 993 }
duke@0 994 }
duke@0 995
duke@0 996 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 997 {
iveresov@2251 998 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 999 // the hard way
duke@0 1000 }
duke@0 1001
duke@0 1002 int MachEpilogNode::reloc() const
duke@0 1003 {
duke@0 1004 return 2; // a large enough number
duke@0 1005 }
duke@0 1006
duke@0 1007 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1008 {
duke@0 1009 return MachNode::pipeline_class();
duke@0 1010 }
duke@0 1011
duke@0 1012 int MachEpilogNode::safepoint_offset() const
duke@0 1013 {
duke@0 1014 return 0;
duke@0 1015 }
duke@0 1016
duke@0 1017 //=============================================================================
duke@0 1018
duke@0 1019 enum RC {
duke@0 1020 rc_bad,
duke@0 1021 rc_int,
duke@0 1022 rc_float,
duke@0 1023 rc_stack
duke@0 1024 };
duke@0 1025
duke@0 1026 static enum RC rc_class(OptoReg::Name reg)
duke@0 1027 {
duke@0 1028 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1029
duke@0 1030 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1031
duke@0 1032 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1033
duke@0 1034 if (r->is_Register()) return rc_int;
duke@0 1035
duke@0 1036 assert(r->is_XMMRegister(), "must be");
duke@0 1037 return rc_float;
duke@0 1038 }
duke@0 1039
kvn@3447 1040 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
kvn@3447 1041 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
kvn@3447 1042 int src_hi, int dst_hi, uint ireg, outputStream* st);
kvn@3447 1043
kvn@3447 1044 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
kvn@3447 1045 int stack_offset, int reg, uint ireg, outputStream* st);
kvn@3447 1046
kvn@3447 1047 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
kvn@3447 1048 int dst_offset, uint ireg, outputStream* st) {
kvn@3447 1049 if (cbuf) {
kvn@3447 1050 MacroAssembler _masm(cbuf);
kvn@3447 1051 switch (ireg) {
kvn@3447 1052 case Op_VecS:
kvn@3447 1053 __ movq(Address(rsp, -8), rax);
kvn@3447 1054 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1055 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1056 __ movq(rax, Address(rsp, -8));
kvn@3447 1057 break;
kvn@3447 1058 case Op_VecD:
kvn@3447 1059 __ pushq(Address(rsp, src_offset));
kvn@3447 1060 __ popq (Address(rsp, dst_offset));
kvn@3447 1061 break;
kvn@3447 1062 case Op_VecX:
kvn@3447 1063 __ pushq(Address(rsp, src_offset));
kvn@3447 1064 __ popq (Address(rsp, dst_offset));
kvn@3447 1065 __ pushq(Address(rsp, src_offset+8));
kvn@3447 1066 __ popq (Address(rsp, dst_offset+8));
kvn@3447 1067 break;
kvn@3447 1068 case Op_VecY:
kvn@3447 1069 __ vmovdqu(Address(rsp, -32), xmm0);
kvn@3447 1070 __ vmovdqu(xmm0, Address(rsp, src_offset));
kvn@3447 1071 __ vmovdqu(Address(rsp, dst_offset), xmm0);
kvn@3447 1072 __ vmovdqu(xmm0, Address(rsp, -32));
kvn@3447 1073 break;
kvn@3447 1074 default:
kvn@3447 1075 ShouldNotReachHere();
kvn@3447 1076 }
kvn@3447 1077 #ifndef PRODUCT
kvn@3447 1078 } else {
kvn@3447 1079 switch (ireg) {
kvn@3447 1080 case Op_VecS:
kvn@3447 1081 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1082 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1083 "movl [rsp + #%d], rax\n\t"
kvn@3447 1084 "movq rax, [rsp - #8]",
kvn@3447 1085 src_offset, dst_offset);
kvn@3447 1086 break;
kvn@3447 1087 case Op_VecD:
kvn@3447 1088 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1089 "popq [rsp + #%d]",
kvn@3447 1090 src_offset, dst_offset);
kvn@3447 1091 break;
kvn@3447 1092 case Op_VecX:
kvn@3447 1093 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
kvn@3447 1094 "popq [rsp + #%d]\n\t"
kvn@3447 1095 "pushq [rsp + #%d]\n\t"
kvn@3447 1096 "popq [rsp + #%d]",
kvn@3447 1097 src_offset, dst_offset, src_offset+8, dst_offset+8);
kvn@3447 1098 break;
kvn@3447 1099 case Op_VecY:
kvn@3447 1100 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
kvn@3447 1101 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@3447 1102 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@3447 1103 "vmovdqu xmm0, [rsp - #32]",
kvn@3447 1104 src_offset, dst_offset);
kvn@3447 1105 break;
kvn@3447 1106 default:
kvn@3447 1107 ShouldNotReachHere();
kvn@3447 1108 }
kvn@3447 1109 #endif
kvn@3447 1110 }
kvn@3447 1111 }
kvn@3447 1112
duke@0 1113 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1114 PhaseRegAlloc* ra_,
duke@0 1115 bool do_size,
kvn@3447 1116 outputStream* st) const {
kvn@3447 1117 assert(cbuf != NULL || st != NULL, "sanity");
duke@0 1118 // Get registers to move
duke@0 1119 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1120 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1121 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1122 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1123
duke@0 1124 enum RC src_second_rc = rc_class(src_second);
duke@0 1125 enum RC src_first_rc = rc_class(src_first);
duke@0 1126 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1127 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1128
duke@0 1129 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1130 "must move at least 1 register" );
duke@0 1131
duke@0 1132 if (src_first == dst_first && src_second == dst_second) {
duke@0 1133 // Self copy, no move
duke@0 1134 return 0;
kvn@3447 1135 }
kvn@3447 1136 if (bottom_type()->isa_vect() != NULL) {
kvn@3447 1137 uint ireg = ideal_reg();
kvn@3447 1138 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
kvn@3447 1139 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
kvn@3447 1140 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
kvn@3447 1141 // mem -> mem
kvn@3447 1142 int src_offset = ra_->reg2offset(src_first);
kvn@3447 1143 int dst_offset = ra_->reg2offset(dst_first);
kvn@3447 1144 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
kvn@3447 1145 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
kvn@3447 1146 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
kvn@3447 1147 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
kvn@3447 1148 int stack_offset = ra_->reg2offset(dst_first);
kvn@3447 1149 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
kvn@3447 1150 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
kvn@3447 1151 int stack_offset = ra_->reg2offset(src_first);
kvn@3447 1152 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
kvn@3447 1153 } else {
kvn@3447 1154 ShouldNotReachHere();
kvn@3447 1155 }
kvn@3447 1156 return 0;
kvn@3447 1157 }
kvn@3447 1158 if (src_first_rc == rc_stack) {
duke@0 1159 // mem ->
duke@0 1160 if (dst_first_rc == rc_stack) {
duke@0 1161 // mem -> mem
duke@0 1162 assert(src_second != dst_first, "overlap");
duke@0 1163 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1164 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1165 // 64-bit
duke@0 1166 int src_offset = ra_->reg2offset(src_first);
duke@0 1167 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1168 if (cbuf) {
kvn@3447 1169 MacroAssembler _masm(cbuf);
kvn@3447 1170 __ pushq(Address(rsp, src_offset));
kvn@3447 1171 __ popq (Address(rsp, dst_offset));
duke@0 1172 #ifndef PRODUCT
kvn@3447 1173 } else {
duke@0 1174 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1175 "popq [rsp + #%d]",
kvn@3447 1176 src_offset, dst_offset);
duke@0 1177 #endif
duke@0 1178 }
duke@0 1179 } else {
duke@0 1180 // 32-bit
duke@0 1181 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1182 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1183 // No pushl/popl, so:
duke@0 1184 int src_offset = ra_->reg2offset(src_first);
duke@0 1185 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1186 if (cbuf) {
kvn@3447 1187 MacroAssembler _masm(cbuf);
kvn@3447 1188 __ movq(Address(rsp, -8), rax);
kvn@3447 1189 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1190 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1191 __ movq(rax, Address(rsp, -8));
duke@0 1192 #ifndef PRODUCT
kvn@3447 1193 } else {
duke@0 1194 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1195 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1196 "movl [rsp + #%d], rax\n\t"
kvn@3447 1197 "movq rax, [rsp - #8]",
kvn@3447 1198 src_offset, dst_offset);
duke@0 1199 #endif
duke@0 1200 }
duke@0 1201 }
kvn@3447 1202 return 0;
duke@0 1203 } else if (dst_first_rc == rc_int) {
duke@0 1204 // mem -> gpr
duke@0 1205 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1206 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1207 // 64-bit
duke@0 1208 int offset = ra_->reg2offset(src_first);
duke@0 1209 if (cbuf) {
kvn@3447 1210 MacroAssembler _masm(cbuf);
kvn@3447 1211 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1212 #ifndef PRODUCT
kvn@3447 1213 } else {
duke@0 1214 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1215 Matcher::regName[dst_first],
duke@0 1216 offset);
duke@0 1217 #endif
duke@0 1218 }
duke@0 1219 } else {
duke@0 1220 // 32-bit
duke@0 1221 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1222 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1223 int offset = ra_->reg2offset(src_first);
duke@0 1224 if (cbuf) {
kvn@3447 1225 MacroAssembler _masm(cbuf);
kvn@3447 1226 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1227 #ifndef PRODUCT
kvn@3447 1228 } else {
duke@0 1229 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1230 Matcher::regName[dst_first],
duke@0 1231 offset);
duke@0 1232 #endif
duke@0 1233 }
duke@0 1234 }
kvn@3447 1235 return 0;
duke@0 1236 } else if (dst_first_rc == rc_float) {
duke@0 1237 // mem-> xmm
duke@0 1238 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1239 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1240 // 64-bit
duke@0 1241 int offset = ra_->reg2offset(src_first);
duke@0 1242 if (cbuf) {
kvn@2953 1243 MacroAssembler _masm(cbuf);
kvn@2953 1244 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1245 #ifndef PRODUCT
kvn@3447 1246 } else {
duke@0 1247 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1248 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1249 Matcher::regName[dst_first],
duke@0 1250 offset);
duke@0 1251 #endif
duke@0 1252 }
duke@0 1253 } else {
duke@0 1254 // 32-bit
duke@0 1255 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1256 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1257 int offset = ra_->reg2offset(src_first);
duke@0 1258 if (cbuf) {
kvn@2953 1259 MacroAssembler _masm(cbuf);
kvn@2953 1260 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1261 #ifndef PRODUCT
kvn@3447 1262 } else {
duke@0 1263 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1264 Matcher::regName[dst_first],
duke@0 1265 offset);
duke@0 1266 #endif
duke@0 1267 }
duke@0 1268 }
kvn@3447 1269 return 0;
duke@0 1270 }
duke@0 1271 } else if (src_first_rc == rc_int) {
duke@0 1272 // gpr ->
duke@0 1273 if (dst_first_rc == rc_stack) {
duke@0 1274 // gpr -> mem
duke@0 1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1277 // 64-bit
duke@0 1278 int offset = ra_->reg2offset(dst_first);
duke@0 1279 if (cbuf) {
kvn@3447 1280 MacroAssembler _masm(cbuf);
kvn@3447 1281 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1282 #ifndef PRODUCT
kvn@3447 1283 } else {
duke@0 1284 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1285 offset,
duke@0 1286 Matcher::regName[src_first]);
duke@0 1287 #endif
duke@0 1288 }
duke@0 1289 } else {
duke@0 1290 // 32-bit
duke@0 1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1293 int offset = ra_->reg2offset(dst_first);
duke@0 1294 if (cbuf) {
kvn@3447 1295 MacroAssembler _masm(cbuf);
kvn@3447 1296 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1297 #ifndef PRODUCT
kvn@3447 1298 } else {
duke@0 1299 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1300 offset,
duke@0 1301 Matcher::regName[src_first]);
duke@0 1302 #endif
duke@0 1303 }
duke@0 1304 }
kvn@3447 1305 return 0;
duke@0 1306 } else if (dst_first_rc == rc_int) {
duke@0 1307 // gpr -> gpr
duke@0 1308 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1309 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1310 // 64-bit
duke@0 1311 if (cbuf) {
kvn@3447 1312 MacroAssembler _masm(cbuf);
kvn@3447 1313 __ movq(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1314 as_Register(Matcher::_regEncode[src_first]));
duke@0 1315 #ifndef PRODUCT
kvn@3447 1316 } else {
duke@0 1317 st->print("movq %s, %s\t# spill",
duke@0 1318 Matcher::regName[dst_first],
duke@0 1319 Matcher::regName[src_first]);
duke@0 1320 #endif
duke@0 1321 }
kvn@3447 1322 return 0;
duke@0 1323 } else {
duke@0 1324 // 32-bit
duke@0 1325 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1326 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1327 if (cbuf) {
kvn@3447 1328 MacroAssembler _masm(cbuf);
kvn@3447 1329 __ movl(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1330 as_Register(Matcher::_regEncode[src_first]));
duke@0 1331 #ifndef PRODUCT
kvn@3447 1332 } else {
duke@0 1333 st->print("movl %s, %s\t# spill",
duke@0 1334 Matcher::regName[dst_first],
duke@0 1335 Matcher::regName[src_first]);
duke@0 1336 #endif
duke@0 1337 }
kvn@3447 1338 return 0;
duke@0 1339 }
duke@0 1340 } else if (dst_first_rc == rc_float) {
duke@0 1341 // gpr -> xmm
duke@0 1342 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1343 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1344 // 64-bit
duke@0 1345 if (cbuf) {
kvn@2953 1346 MacroAssembler _masm(cbuf);
kvn@2953 1347 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1348 #ifndef PRODUCT
kvn@3447 1349 } else {
duke@0 1350 st->print("movdq %s, %s\t# spill",
duke@0 1351 Matcher::regName[dst_first],
duke@0 1352 Matcher::regName[src_first]);
duke@0 1353 #endif
duke@0 1354 }
duke@0 1355 } else {
duke@0 1356 // 32-bit
duke@0 1357 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1358 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1359 if (cbuf) {
kvn@2953 1360 MacroAssembler _masm(cbuf);
kvn@2953 1361 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1362 #ifndef PRODUCT
kvn@3447 1363 } else {
duke@0 1364 st->print("movdl %s, %s\t# spill",
duke@0 1365 Matcher::regName[dst_first],
duke@0 1366 Matcher::regName[src_first]);
duke@0 1367 #endif
duke@0 1368 }
duke@0 1369 }
kvn@3447 1370 return 0;
duke@0 1371 }
duke@0 1372 } else if (src_first_rc == rc_float) {
duke@0 1373 // xmm ->
duke@0 1374 if (dst_first_rc == rc_stack) {
duke@0 1375 // xmm -> mem
duke@0 1376 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1377 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1378 // 64-bit
duke@0 1379 int offset = ra_->reg2offset(dst_first);
duke@0 1380 if (cbuf) {
kvn@2953 1381 MacroAssembler _masm(cbuf);
kvn@2953 1382 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1383 #ifndef PRODUCT
kvn@3447 1384 } else {
duke@0 1385 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1386 offset,
duke@0 1387 Matcher::regName[src_first]);
duke@0 1388 #endif
duke@0 1389 }
duke@0 1390 } else {
duke@0 1391 // 32-bit
duke@0 1392 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1393 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1394 int offset = ra_->reg2offset(dst_first);
duke@0 1395 if (cbuf) {
kvn@2953 1396 MacroAssembler _masm(cbuf);
kvn@2953 1397 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1398 #ifndef PRODUCT
kvn@3447 1399 } else {
duke@0 1400 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1401 offset,
duke@0 1402 Matcher::regName[src_first]);
duke@0 1403 #endif
duke@0 1404 }
duke@0 1405 }
kvn@3447 1406 return 0;
duke@0 1407 } else if (dst_first_rc == rc_int) {
duke@0 1408 // xmm -> gpr
duke@0 1409 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1410 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1411 // 64-bit
duke@0 1412 if (cbuf) {
kvn@2953 1413 MacroAssembler _masm(cbuf);
kvn@2953 1414 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1415 #ifndef PRODUCT
kvn@3447 1416 } else {
duke@0 1417 st->print("movdq %s, %s\t# spill",
duke@0 1418 Matcher::regName[dst_first],
duke@0 1419 Matcher::regName[src_first]);
duke@0 1420 #endif
duke@0 1421 }
duke@0 1422 } else {
duke@0 1423 // 32-bit
duke@0 1424 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1425 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1426 if (cbuf) {
kvn@2953 1427 MacroAssembler _masm(cbuf);
kvn@2953 1428 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1429 #ifndef PRODUCT
kvn@3447 1430 } else {
duke@0 1431 st->print("movdl %s, %s\t# spill",
duke@0 1432 Matcher::regName[dst_first],
duke@0 1433 Matcher::regName[src_first]);
duke@0 1434 #endif
duke@0 1435 }
duke@0 1436 }
kvn@3447 1437 return 0;
duke@0 1438 } else if (dst_first_rc == rc_float) {
duke@0 1439 // xmm -> xmm
duke@0 1440 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1441 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1442 // 64-bit
duke@0 1443 if (cbuf) {
kvn@2953 1444 MacroAssembler _masm(cbuf);
kvn@2953 1445 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1446 #ifndef PRODUCT
kvn@3447 1447 } else {
duke@0 1448 st->print("%s %s, %s\t# spill",
duke@0 1449 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1450 Matcher::regName[dst_first],
duke@0 1451 Matcher::regName[src_first]);
duke@0 1452 #endif
duke@0 1453 }
duke@0 1454 } else {
duke@0 1455 // 32-bit
duke@0 1456 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1457 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1458 if (cbuf) {
kvn@2953 1459 MacroAssembler _masm(cbuf);
kvn@2953 1460 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1461 #ifndef PRODUCT
kvn@3447 1462 } else {
duke@0 1463 st->print("%s %s, %s\t# spill",
duke@0 1464 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1465 Matcher::regName[dst_first],
duke@0 1466 Matcher::regName[src_first]);
duke@0 1467 #endif
duke@0 1468 }
duke@0 1469 }
kvn@3447 1470 return 0;
duke@0 1471 }
duke@0 1472 }
duke@0 1473
duke@0 1474 assert(0," foo ");
duke@0 1475 Unimplemented();
duke@0 1476 return 0;
duke@0 1477 }
duke@0 1478
duke@0 1479 #ifndef PRODUCT
kvn@3447 1480 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
duke@0 1481 implementation(NULL, ra_, false, st);
duke@0 1482 }
duke@0 1483 #endif
duke@0 1484
kvn@3447 1485 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1486 implementation(&cbuf, ra_, false, NULL);
duke@0 1487 }
duke@0 1488
kvn@3447 1489 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
kvn@3447 1490 return MachNode::size(ra_);
duke@0 1491 }
duke@0 1492
duke@0 1493 //=============================================================================
duke@0 1494 #ifndef PRODUCT
duke@0 1495 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1496 {
duke@0 1497 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1498 int reg = ra_->get_reg_first(this);
duke@0 1499 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1500 Matcher::regName[reg], offset);
duke@0 1501 }
duke@0 1502 #endif
duke@0 1503
duke@0 1504 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1505 {
duke@0 1506 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1507 int reg = ra_->get_encode(this);
duke@0 1508 if (offset >= 0x80) {
duke@0 1509 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1510 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1511 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1512 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1513 emit_d32(cbuf, offset);
duke@0 1514 } else {
duke@0 1515 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1516 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1517 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1518 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1519 emit_d8(cbuf, offset);
duke@0 1520 }
duke@0 1521 }
duke@0 1522
duke@0 1523 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1524 {
duke@0 1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1526 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1527 }
duke@0 1528
duke@0 1529 //=============================================================================
duke@0 1530 #ifndef PRODUCT
duke@0 1531 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1532 {
ehelin@5259 1533 if (UseCompressedClassPointers) {
kvn@1491 1534 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
hseigel@5093 1535 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
kvn@1491 1536 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1537 } else {
kvn@1491 1538 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1539 "# Inline cache check");
coleenp@113 1540 }
duke@0 1541 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1542 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1543 }
duke@0 1544 #endif
duke@0 1545
duke@0 1546 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1547 {
duke@0 1548 MacroAssembler masm(&cbuf);
twisti@1668 1549 uint insts_size = cbuf.insts_size();
ehelin@5259 1550 if (UseCompressedClassPointers) {
coleenp@113 1551 masm.load_klass(rscratch1, j_rarg0);
never@304 1552 masm.cmpptr(rax, rscratch1);
coleenp@113 1553 } else {
never@304 1554 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1555 }
duke@0 1556
duke@0 1557 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1558
duke@0 1559 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1560 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1561 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1562 if (OptoBreakpoint) {
duke@0 1563 // Leave space for int3
kvn@1491 1564 nops_cnt -= 1;
duke@0 1565 }
kvn@1491 1566 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1567 if (nops_cnt > 0)
kvn@1491 1568 masm.nop(nops_cnt);
duke@0 1569 }
duke@0 1570
duke@0 1571 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1572 {
kvn@1491 1573 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1574 // the hard way
duke@0 1575 }
goetz@6189 1576
duke@0 1577
duke@0 1578 //=============================================================================
duke@0 1579
duke@0 1580 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1581 {
duke@0 1582 return regnum - 32; // The FP registers are in the second chunk
duke@0 1583 }
duke@0 1584
duke@0 1585 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1586 const bool Matcher::convL2FSupported(void) {
duke@0 1587 return true;
duke@0 1588 }
duke@0 1589
duke@0 1590 // Is this branch offset short enough that a short branch can be used?
duke@0 1591 //
duke@0 1592 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1593 // this method should return false for offset 0.
kvn@2614 1594 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1595 // The passed offset is relative to address of the branch.
kvn@2614 1596 // On 86 a branch displacement is calculated relative to address
kvn@2614 1597 // of a next instruction.
kvn@2614 1598 offset -= br_size;
kvn@2614 1599
never@415 1600 // the short version of jmpConUCF2 contains multiple branches,
never@415 1601 // making the reach slightly less
never@415 1602 if (rule == jmpConUCF2_rule)
never@415 1603 return (-126 <= offset && offset <= 125);
never@415 1604 return (-128 <= offset && offset <= 127);
duke@0 1605 }
duke@0 1606
duke@0 1607 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1608 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1609 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1610
duke@0 1611 // Probably always true, even if a temp register is required.
duke@0 1612 return true;
duke@0 1613 }
duke@0 1614
duke@0 1615 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1616 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1617
duke@0 1618 // Threshold size for cleararray.
duke@0 1619 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1620
kvn@2808 1621 // No additional cost for CMOVL.
kvn@2808 1622 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 1623
kvn@2808 1624 // No CMOVF/CMOVD with SSE2
kvn@2808 1625 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 1626
goetz@5982 1627 // Does the CPU require late expand (see block.cpp for description of late expand)?
goetz@5982 1628 const bool Matcher::require_postalloc_expand = false;
goetz@5982 1629
duke@0 1630 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1631 // to be subsumed into complex addressing expressions or compute them
duke@0 1632 // into registers? True for Intel but false for most RISCs
duke@0 1633 const bool Matcher::clone_shift_expressions = true;
duke@0 1634
roland@2248 1635 // Do we need to mask the count passed to shift instructions or does
roland@2248 1636 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 1637 const bool Matcher::need_masked_shift_count = false;
roland@2248 1638
kvn@1495 1639 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 1640 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 1641 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 1642 }
kvn@1495 1643
roland@3724 1644 bool Matcher::narrow_klass_use_complex_address() {
ehelin@5259 1645 assert(UseCompressedClassPointers, "only for compressed klass code");
roland@3724 1646 return (LogKlassAlignmentInBytes <= 3);
roland@3724 1647 }
roland@3724 1648
duke@0 1649 // Is it better to copy float constants, or load them directly from
duke@0 1650 // memory? Intel can load a float constant from a direct address,
duke@0 1651 // requiring no extra registers. Most RISCs will have to materialize
duke@0 1652 // an address into a register first, so they would do better to copy
duke@0 1653 // the constant from stack.
duke@0 1654 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 1655
duke@0 1656 // If CPU can load and store mis-aligned doubles directly then no
duke@0 1657 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 1658 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 1659 // C code as the Java calling convention forces doubles to be aligned.
duke@0 1660 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1661
duke@0 1662 // No-op on amd64
duke@0 1663 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 1664
duke@0 1665 // Advertise here if the CPU requires explicit rounding operations to
duke@0 1666 // implement the UseStrictFP mode.
duke@0 1667 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 1668
kvn@1274 1669 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 1670 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 1671 bool Matcher::float_in_double() { return false; }
kvn@1274 1672
duke@0 1673 // Do ints take an entire long register or just half?
duke@0 1674 const bool Matcher::int_in_long = true;
duke@0 1675
duke@0 1676 // Return whether or not this register is ever used as an argument.
duke@0 1677 // This function is used on startup to build the trampoline stubs in
duke@0 1678 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 1679 // call in the trampoline, and arguments in those registers not be
duke@0 1680 // available to the callee.
duke@0 1681 bool Matcher::can_be_java_arg(int reg)
duke@0 1682 {
duke@0 1683 return
kvn@3447 1684 reg == RDI_num || reg == RDI_H_num ||
kvn@3447 1685 reg == RSI_num || reg == RSI_H_num ||
kvn@3447 1686 reg == RDX_num || reg == RDX_H_num ||
kvn@3447 1687 reg == RCX_num || reg == RCX_H_num ||
kvn@3447 1688 reg == R8_num || reg == R8_H_num ||
kvn@3447 1689 reg == R9_num || reg == R9_H_num ||
kvn@3447 1690 reg == R12_num || reg == R12_H_num ||
kvn@3447 1691 reg == XMM0_num || reg == XMM0b_num ||
kvn@3447 1692 reg == XMM1_num || reg == XMM1b_num ||
kvn@3447 1693 reg == XMM2_num || reg == XMM2b_num ||
kvn@3447 1694 reg == XMM3_num || reg == XMM3b_num ||
kvn@3447 1695 reg == XMM4_num || reg == XMM4b_num ||
kvn@3447 1696 reg == XMM5_num || reg == XMM5b_num ||
kvn@3447 1697 reg == XMM6_num || reg == XMM6b_num ||
kvn@3447 1698 reg == XMM7_num || reg == XMM7b_num;
duke@0 1699 }
duke@0 1700
duke@0 1701 bool Matcher::is_spillable_arg(int reg)
duke@0 1702 {
duke@0 1703 return can_be_java_arg(reg);
duke@0 1704 }
duke@0 1705
kvn@1834 1706 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 1707 // In 64 bit mode a code which use multiply when
kvn@1834 1708 // devisor is constant is faster than hardware
kvn@1834 1709 // DIV instruction (it uses MulHiL).
kvn@1834 1710 return false;
kvn@1834 1711 }
kvn@1834 1712
duke@0 1713 // Register for DIVI projection of divmodI
duke@0 1714 RegMask Matcher::divI_proj_mask() {
roland@2882 1715 return INT_RAX_REG_mask();
duke@0 1716 }
duke@0 1717
duke@0 1718 // Register for MODI projection of divmodI
duke@0 1719 RegMask Matcher::modI_proj_mask() {
roland@2882 1720 return INT_RDX_REG_mask();
duke@0 1721 }
duke@0 1722
duke@0 1723 // Register for DIVL projection of divmodL
duke@0 1724 RegMask Matcher::divL_proj_mask() {
roland@2882 1725 return LONG_RAX_REG_mask();
duke@0 1726 }
duke@0 1727
duke@0 1728 // Register for MODL projection of divmodL
duke@0 1729 RegMask Matcher::modL_proj_mask() {
roland@2882 1730 return LONG_RDX_REG_mask();
duke@0 1731 }
duke@0 1732
zmajo@8290 1733 // Register for saving SP into on method handle invokes. Not used on x86_64.
twisti@1137 1734 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
zmajo@8290 1735 return NO_REG_mask();
twisti@1137 1736 }
twisti@1137 1737
duke@0 1738 %}
duke@0 1739
duke@0 1740 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1741 // This block specifies the encoding classes used by the compiler to
duke@0 1742 // output byte streams. Encoding classes are parameterized macros
duke@0 1743 // used by Machine Instruction Nodes in order to generate the bit
duke@0 1744 // encoding of the instruction. Operands specify their base encoding
duke@0 1745 // interface with the interface keyword. There are currently
duke@0 1746 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 1747 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 1748 // which returns its register number when queried. CONST_INTER causes
duke@0 1749 // an operand to generate a function which returns the value of the
duke@0 1750 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 1751 // four functions which return the Base Register, the Index Register,
duke@0 1752 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 1753 // COND_INTER causes an operand to generate six functions which return
duke@0 1754 // the encoding code (ie - encoding bits for the instruction)
duke@0 1755 // associated with each basic boolean condition for a conditional
duke@0 1756 // instruction.
duke@0 1757 //
duke@0 1758 // Instructions specify two basic values for encoding. Again, a
duke@0 1759 // function is available to check if the constant displacement is an
duke@0 1760 // oop. They use the ins_encode keyword to specify their encoding
duke@0 1761 // classes (which must be a sequence of enc_class names, and their
duke@0 1762 // parameters, specified in the encoding block), and they use the
duke@0 1763 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1764 // tertiary opcode. Only the opcode sections which a particular
duke@0 1765 // instruction needs for encoding need to be specified.
duke@0 1766 encode %{
duke@0 1767 // Build emit functions for each basic byte or larger field in the
duke@0 1768 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 1769 // from C++ code in the enc_class source block. Emit functions will
duke@0 1770 // live in the main source block for now. In future, we can
duke@0 1771 // generalize this by adding a syntax that specifies the sizes of
duke@0 1772 // fields in an order, so that the adlc can build the emit functions
duke@0 1773 // automagically
duke@0 1774
duke@0 1775 // Emit primary opcode
duke@0 1776 enc_class OpcP
duke@0 1777 %{
duke@0 1778 emit_opcode(cbuf, $primary);
duke@0 1779 %}
duke@0 1780
duke@0 1781 // Emit secondary opcode
duke@0 1782 enc_class OpcS
duke@0 1783 %{
duke@0 1784 emit_opcode(cbuf, $secondary);
duke@0 1785 %}
duke@0 1786
duke@0 1787 // Emit tertiary opcode
duke@0 1788 enc_class OpcT
duke@0 1789 %{
duke@0 1790 emit_opcode(cbuf, $tertiary);
duke@0 1791 %}
duke@0 1792
duke@0 1793 // Emit opcode directly
duke@0 1794 enc_class Opcode(immI d8)
duke@0 1795 %{
duke@0 1796 emit_opcode(cbuf, $d8$$constant);
duke@0 1797 %}
duke@0 1798
duke@0 1799 // Emit size prefix
duke@0 1800 enc_class SizePrefix
duke@0 1801 %{
duke@0 1802 emit_opcode(cbuf, 0x66);
duke@0 1803 %}
duke@0 1804
duke@0 1805 enc_class reg(rRegI reg)
duke@0 1806 %{
duke@0 1807 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 1808 %}
duke@0 1809
duke@0 1810 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 1811 %{
duke@0 1812 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1813 %}
duke@0 1814
duke@0 1815 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 1816 %{
duke@0 1817 emit_opcode(cbuf, $opcode$$constant);
duke@0 1818 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1819 %}
duke@0 1820
duke@0 1821 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 1822 %{
duke@0 1823 // Full implementation of Java idiv and irem; checks for
duke@0 1824 // special case as described in JVM spec., p.243 & p.271.
duke@0 1825 //
duke@0 1826 // normal case special case
duke@0 1827 //
duke@0 1828 // input : rax: dividend min_int
duke@0 1829 // reg: divisor -1
duke@0 1830 //
duke@0 1831 // output: rax: quotient (= rax idiv reg) min_int
duke@0 1832 // rdx: remainder (= rax irem reg) 0
duke@0 1833 //
duke@0 1834 // Code sequnce:
duke@0 1835 //
duke@0 1836 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 1837 // 5: 75 07/08 jne e <normal>
duke@0 1838 // 7: 33 d2 xor %edx,%edx
duke@0 1839 // [div >= 8 -> offset + 1]
duke@0 1840 // [REX_B]
duke@0 1841 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1842 // c: 74 03/04 je 11 <done>
duke@0 1843 // 000000000000000e <normal>:
duke@0 1844 // e: 99 cltd
duke@0 1845 // [div >= 8 -> offset + 1]
duke@0 1846 // [REX_B]
duke@0 1847 // f: f7 f9 idiv $div
duke@0 1848 // 0000000000000011 <done>:
duke@0 1849
duke@0 1850 // cmp $0x80000000,%eax
duke@0 1851 emit_opcode(cbuf, 0x3d);
duke@0 1852 emit_d8(cbuf, 0x00);
duke@0 1853 emit_d8(cbuf, 0x00);
duke@0 1854 emit_d8(cbuf, 0x00);
duke@0 1855 emit_d8(cbuf, 0x80);
duke@0 1856
duke@0 1857 // jne e <normal>
duke@0 1858 emit_opcode(cbuf, 0x75);
duke@0 1859 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 1860
duke@0 1861 // xor %edx,%edx
duke@0 1862 emit_opcode(cbuf, 0x33);
duke@0 1863 emit_d8(cbuf, 0xD2);
duke@0 1864
duke@0 1865 // cmp $0xffffffffffffffff,%ecx
duke@0 1866 if ($div$$reg >= 8) {
duke@0 1867 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1868 }
duke@0 1869 emit_opcode(cbuf, 0x83);
duke@0 1870 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1871 emit_d8(cbuf, 0xFF);
duke@0 1872
duke@0 1873 // je 11 <done>
duke@0 1874 emit_opcode(cbuf, 0x74);
duke@0 1875 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 1876
duke@0 1877 // <normal>
duke@0 1878 // cltd
duke@0 1879 emit_opcode(cbuf, 0x99);
duke@0 1880
duke@0 1881 // idivl (note: must be emitted by the user of this rule)
duke@0 1882 // <done>
duke@0 1883 %}
duke@0 1884
duke@0 1885 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 1886 %{
duke@0 1887 // Full implementation of Java ldiv and lrem; checks for
duke@0 1888 // special case as described in JVM spec., p.243 & p.271.
duke@0 1889 //
duke@0 1890 // normal case special case
duke@0 1891 //
duke@0 1892 // input : rax: dividend min_long
duke@0 1893 // reg: divisor -1
duke@0 1894 //
duke@0 1895 // output: rax: quotient (= rax idiv reg) min_long
duke@0 1896 // rdx: remainder (= rax irem reg) 0
duke@0 1897 //
duke@0 1898 // Code sequnce:
duke@0 1899 //
duke@0 1900 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 1901 // 7: 00 00 80
duke@0 1902 // a: 48 39 d0 cmp %rdx,%rax
duke@0 1903 // d: 75 08 jne 17 <normal>
duke@0 1904 // f: 33 d2 xor %edx,%edx
duke@0 1905 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1906 // 15: 74 05 je 1c <done>
duke@0 1907 // 0000000000000017 <normal>:
duke@0 1908 // 17: 48 99 cqto
duke@0 1909 // 19: 48 f7 f9 idiv $div
duke@0 1910 // 000000000000001c <done>:
duke@0 1911
duke@0 1912 // mov $0x8000000000000000,%rdx
duke@0 1913 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1914 emit_opcode(cbuf, 0xBA);
duke@0 1915 emit_d8(cbuf, 0x00);
duke@0 1916 emit_d8(cbuf, 0x00);
duke@0 1917 emit_d8(cbuf, 0x00);
duke@0 1918 emit_d8(cbuf, 0x00);
duke@0 1919 emit_d8(cbuf, 0x00);
duke@0 1920 emit_d8(cbuf, 0x00);
duke@0 1921 emit_d8(cbuf, 0x00);
duke@0 1922 emit_d8(cbuf, 0x80);
duke@0 1923
duke@0 1924 // cmp %rdx,%rax
duke@0 1925 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1926 emit_opcode(cbuf, 0x39);
duke@0 1927 emit_d8(cbuf, 0xD0);
duke@0 1928
duke@0 1929 // jne 17 <normal>
duke@0 1930 emit_opcode(cbuf, 0x75);
duke@0 1931 emit_d8(cbuf, 0x08);
duke@0 1932
duke@0 1933 // xor %edx,%edx
duke@0 1934 emit_opcode(cbuf, 0x33);
duke@0 1935 emit_d8(cbuf, 0xD2);
duke@0 1936
duke@0 1937 // cmp $0xffffffffffffffff,$div
duke@0 1938 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 1939 emit_opcode(cbuf, 0x83);
duke@0 1940 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1941 emit_d8(cbuf, 0xFF);
duke@0 1942
duke@0 1943 // je 1e <done>
duke@0 1944 emit_opcode(cbuf, 0x74);
duke@0 1945 emit_d8(cbuf, 0x05);
duke@0 1946
duke@0 1947 // <normal>
duke@0 1948 // cqto
duke@0 1949 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1950 emit_opcode(cbuf, 0x99);
duke@0 1951
duke@0 1952 // idivq (note: must be emitted by the user of this rule)
duke@0 1953 // <done>
duke@0 1954 %}
duke@0 1955
duke@0 1956 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 1957 enc_class OpcSE(immI imm)
duke@0 1958 %{
duke@0 1959 // Emit primary opcode and set sign-extend bit
duke@0 1960 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1961 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1962 emit_opcode(cbuf, $primary | 0x02);
duke@0 1963 } else {
duke@0 1964 // 32-bit immediate
duke@0 1965 emit_opcode(cbuf, $primary);
duke@0 1966 }
duke@0 1967 %}
duke@0 1968
duke@0 1969 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 1970 %{
duke@0 1971 // OpcSEr/m
duke@0 1972 int dstenc = $dst$$reg;
duke@0 1973 if (dstenc >= 8) {
duke@0 1974 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1975 dstenc -= 8;
duke@0 1976 }
duke@0 1977 // Emit primary opcode and set sign-extend bit
duke@0 1978 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1979 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1980 emit_opcode(cbuf, $primary | 0x02);
duke@0 1981 } else {
duke@0 1982 // 32-bit immediate
duke@0 1983 emit_opcode(cbuf, $primary);
duke@0 1984 }
duke@0 1985 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1986 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1987 %}
duke@0 1988
duke@0 1989 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 1990 %{
duke@0 1991 // OpcSEr/m
duke@0 1992 int dstenc = $dst$$reg;
duke@0 1993 if (dstenc < 8) {
duke@0 1994 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1995 } else {
duke@0 1996 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 1997 dstenc -= 8;
duke@0 1998 }
duke@0 1999 // Emit primary opcode and set sign-extend bit
duke@0 2000 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2001 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2002 emit_opcode(cbuf, $primary | 0x02);
duke@0 2003 } else {
duke@0 2004 // 32-bit immediate
duke@0 2005 emit_opcode(cbuf, $primary);
duke@0 2006 }
duke@0 2007 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2008 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2009 %}
duke@0 2010
duke@0 2011 enc_class Con8or32(immI imm)
duke@0 2012 %{
duke@0 2013 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2015 $$$emit8$imm$$constant;
duke@0 2016 } else {
duke@0 2017 // 32-bit immediate
duke@0 2018 $$$emit32$imm$$constant;
duke@0 2019 }
duke@0 2020 %}
duke@0 2021
duke@0 2022 enc_class opc2_reg(rRegI dst)
duke@0 2023 %{
duke@0 2024 // BSWAP
duke@0 2025 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2026 %}
duke@0 2027
duke@0 2028 enc_class opc3_reg(rRegI dst)
duke@0 2029 %{
duke@0 2030 // BSWAP
duke@0 2031 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2032 %}
duke@0 2033
duke@0 2034 enc_class reg_opc(rRegI div)
duke@0 2035 %{
duke@0 2036 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2037 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2038 %}
duke@0 2039
duke@0 2040 enc_class enc_cmov(cmpOp cop)
duke@0 2041 %{
duke@0 2042 // CMOV
duke@0 2043 $$$emit8$primary;
duke@0 2044 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2045 %}
duke@0 2046
duke@0 2047 enc_class enc_PartialSubtypeCheck()
duke@0 2048 %{
duke@0 2049 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2050 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2051 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2052 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2053 Label miss;
jrose@644 2054 const bool set_cond_codes = true;
duke@0 2055
duke@0 2056 MacroAssembler _masm(&cbuf);
jrose@644 2057 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2058 NULL, &miss,
jrose@644 2059 /*set_cond_codes:*/ true);
duke@0 2060 if ($primary) {
never@304 2061 __ xorptr(Rrdi, Rrdi);
duke@0 2062 }
duke@0 2063 __ bind(miss);
duke@0 2064 %}
duke@0 2065
kvn@4438 2066 enc_class clear_avx %{
kvn@4438 2067 debug_only(int off0 = cbuf.insts_size());
kvn@4438 2068 if (ra_->C->max_vector_size() > 16) {
kvn@4438 2069 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 2070 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 2071 MacroAssembler _masm(&cbuf);
kvn@4438 2072 __ vzeroupper();
kvn@4438 2073 }
kvn@4438 2074 debug_only(int off1 = cbuf.insts_size());
kvn@4438 2075 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
kvn@4438 2076 %}
kvn@4438 2077
kvn@4438 2078 enc_class Java_To_Runtime(method meth) %{
kvn@4438 2079 // No relocation needed
kvn@4438 2080 MacroAssembler _masm(&cbuf);
kvn@4438 2081 __ mov64(r10, (int64_t) $meth$$method);
kvn@4438 2082 __ call(r10);
kvn@4438 2083 %}
kvn@4438 2084
duke@0 2085 enc_class Java_To_Interpreter(method meth)
duke@0 2086 %{
duke@0 2087 // CALL Java_To_Interpreter
duke@0 2088 // This is the instruction starting address for relocation info.
twisti@1668 2089 cbuf.set_insts_mark();
duke@0 2090 $$$emit8$primary;
duke@0 2091 // CALL directly to the runtime
duke@0 2092 emit_d32_reloc(cbuf,
twisti@1668 2093 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2094 runtime_call_Relocation::spec(),
duke@0 2095 RELOC_DISP32);
duke@0 2096 %}
duke@0 2097
duke@0 2098 enc_class Java_Static_Call(method meth)
duke@0 2099 %{
duke@0 2100 // JAVA STATIC CALL
duke@0 2101 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2102 // determine who we intended to call.
twisti@1668 2103 cbuf.set_insts_mark();
duke@0 2104 $$$emit8$primary;
duke@0 2105
duke@0 2106 if (!_method) {
duke@0 2107 emit_d32_reloc(cbuf,
twisti@1668 2108 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2109 runtime_call_Relocation::spec(),
duke@0 2110 RELOC_DISP32);
duke@0 2111 } else if (_optimized_virtual) {
duke@0 2112 emit_d32_reloc(cbuf,
twisti@1668 2113 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2114 opt_virtual_call_Relocation::spec(),
duke@0 2115 RELOC_DISP32);
duke@0 2116 } else {
duke@0 2117 emit_d32_reloc(cbuf,
twisti@1668 2118 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2119 static_call_Relocation::spec(),
duke@0 2120 RELOC_DISP32);
duke@0 2121 }
duke@0 2122 if (_method) {
dlong@4565 2123 // Emit stub for static call.
dlong@4565 2124 CompiledStaticCall::emit_to_interp_stub(cbuf);
duke@0 2125 }
duke@0 2126 %}
duke@0 2127
coleenp@3602 2128 enc_class Java_Dynamic_Call(method meth) %{
coleenp@3602 2129 MacroAssembler _masm(&cbuf);
coleenp@3602 2130 __ ic_call((address)$meth$$method);
duke@0 2131 %}
duke@0 2132
duke@0 2133 enc_class Java_Compiled_Call(method meth)
duke@0 2134 %{
duke@0 2135 // JAVA COMPILED CALL
coleenp@3602 2136 int disp = in_bytes(Method:: from_compiled_offset());
duke@0 2137
duke@0 2138 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2139 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2140
duke@0 2141 // callq *disp(%rax)
twisti@1668 2142 cbuf.set_insts_mark();
duke@0 2143 $$$emit8$primary;
duke@0 2144 if (disp < 0x80) {
duke@0 2145 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2146 emit_d8(cbuf, disp); // Displacement
duke@0 2147 } else {
duke@0 2148 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2149 emit_d32(cbuf, disp); // Displacement
duke@0 2150 }
duke@0 2151 %}
duke@0 2152
duke@0 2153 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2154 %{
duke@0 2155 // SAL, SAR, SHR
duke@0 2156 int dstenc = $dst$$reg;
duke@0 2157 if (dstenc >= 8) {
duke@0 2158 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2159 dstenc -= 8;
duke@0 2160 }
duke@0 2161 $$$emit8$primary;
duke@0 2162 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2163 $$$emit8$shift$$constant;
duke@0 2164 %}
duke@0 2165
duke@0 2166 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2167 %{
duke@0 2168 // SAL, SAR, SHR
duke@0 2169 int dstenc = $dst$$reg;
duke@0 2170 if (dstenc < 8) {
duke@0 2171 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2172 } else {
duke@0 2173 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2174 dstenc -= 8;
duke@0 2175 }
duke@0 2176 $$$emit8$primary;
duke@0 2177 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2178 $$$emit8$shift$$constant;
duke@0 2179 %}
duke@0 2180
duke@0 2181 enc_class load_immI(rRegI dst, immI src)
duke@0 2182 %{
duke@0 2183 int dstenc = $dst$$reg;
duke@0 2184 if (dstenc >= 8) {
duke@0 2185 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2186 dstenc -= 8;
duke@0 2187 }
duke@0 2188 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2189 $$$emit32$src$$constant;
duke@0 2190 %}
duke@0 2191
duke@0 2192 enc_class load_immL(rRegL dst, immL src)
duke@0 2193 %{
duke@0 2194 int dstenc = $dst$$reg;
duke@0 2195 if (dstenc < 8) {
duke@0 2196 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2197 } else {
duke@0 2198 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2199 dstenc -= 8;
duke@0 2200 }
duke@0 2201 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2202 emit_d64(cbuf, $src$$constant);
duke@0 2203 %}
duke@0 2204
duke@0 2205 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2206 %{
duke@0 2207 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2208 int dstenc = $dst$$reg;
duke@0 2209 if (dstenc >= 8) {
duke@0 2210 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2211 dstenc -= 8;
duke@0 2212 }
duke@0 2213 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2214 $$$emit32$src$$constant;
duke@0 2215 %}
duke@0 2216
duke@0 2217 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2218 %{
duke@0 2219 int dstenc = $dst$$reg;
duke@0 2220 if (dstenc < 8) {
duke@0 2221 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2222 } else {
duke@0 2223 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2224 dstenc -= 8;
duke@0 2225 }
duke@0 2226 emit_opcode(cbuf, 0xC7);
duke@0 2227 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2228 $$$emit32$src$$constant;
duke@0 2229 %}
duke@0 2230
duke@0 2231 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2232 %{
duke@0 2233 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2234 int dstenc = $dst$$reg;
duke@0 2235 if (dstenc >= 8) {
duke@0 2236 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2237 dstenc -= 8;
duke@0 2238 }
duke@0 2239 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2240 $$$emit32$src$$constant;
duke@0 2241 %}
duke@0 2242
duke@0 2243 enc_class load_immP(rRegP dst, immP src)
duke@0 2244 %{
duke@0 2245 int dstenc = $dst$$reg;
duke@0 2246 if (dstenc < 8) {
duke@0 2247 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2248 } else {
duke@0 2249 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2250 dstenc -= 8;
duke@0 2251 }
duke@0 2252 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2253 // This next line should be generated from ADLC
coleenp@3602 2254 if ($src->constant_reloc() != relocInfo::none) {
coleenp@3602 2255 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
duke@0 2256 } else {
duke@0 2257 emit_d64(cbuf, $src$$constant);
duke@0 2258 }
duke@0 2259 %}
duke@0 2260
duke@0 2261 enc_class Con32(immI src)
duke@0 2262 %{
duke@0 2263 // Output immediate
duke@0 2264 $$$emit32$src$$constant;
duke@0 2265 %}
duke@0 2266
duke@0 2267 enc_class Con32F_as_bits(immF src)
duke@0 2268 %{
duke@0 2269 // Output Float immediate bits
duke@0 2270 jfloat jf = $src$$constant;
duke@0 2271 jint jf_as_bits = jint_cast(jf);
duke@0 2272 emit_d32(cbuf, jf_as_bits);
duke@0 2273 %}
duke@0 2274
duke@0 2275 enc_class Con16(immI src)
duke@0 2276 %{
duke@0 2277 // Output immediate
duke@0 2278 $$$emit16$src$$constant;
duke@0 2279 %}
duke@0 2280
duke@0 2281 // How is this different from Con32??? XXX
duke@0 2282 enc_class Con_d32(immI src)
duke@0 2283 %{
duke@0 2284 emit_d32(cbuf,$src$$constant);
duke@0 2285 %}
duke@0 2286
duke@0 2287 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2288 // Output immediate memory reference
duke@0 2289 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2290 emit_d32(cbuf, 0x00);
duke@0 2291 %}
duke@0 2292
duke@0 2293 enc_class lock_prefix()
duke@0 2294 %{
duke@0 2295 if (os::is_MP()) {
duke@0 2296 emit_opcode(cbuf, 0xF0); // lock
duke@0 2297 }
duke@0 2298 %}
duke@0 2299
duke@0 2300 enc_class REX_mem(memory mem)
duke@0 2301 %{
duke@0 2302 if ($mem$$base >= 8) {
duke@0 2303 if ($mem$$index < 8) {
duke@0 2304 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2305 } else {
duke@0 2306 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2307 }
duke@0 2308 } else {
duke@0 2309 if ($mem$$index >= 8) {
duke@0 2310 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2311 }
duke@0 2312 }
duke@0 2313 %}
duke@0 2314
duke@0 2315 enc_class REX_mem_wide(memory mem)
duke@0 2316 %{
duke@0 2317 if ($mem$$base >= 8) {
duke@0 2318 if ($mem$$index < 8) {
duke@0 2319 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2320 } else {
duke@0 2321 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2322 }
duke@0 2323 } else {
duke@0 2324 if ($mem$$index < 8) {
duke@0 2325 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2326 } else {
duke@0 2327 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2328 }
duke@0 2329 }
duke@0 2330 %}
duke@0 2331
duke@0 2332 // for byte regs
duke@0 2333 enc_class REX_breg(rRegI reg)
duke@0 2334 %{
duke@0 2335 if ($reg$$reg >= 4) {
duke@0 2336 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2337 }
duke@0 2338 %}
duke@0 2339
duke@0 2340 // for byte regs
duke@0 2341 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2342 %{
duke@0 2343 if ($dst$$reg < 8) {
duke@0 2344 if ($src$$reg >= 4) {
duke@0 2345 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2346 }
duke@0 2347 } else {
duke@0 2348 if ($src$$reg < 8) {
duke@0 2349 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2350 } else {
duke@0 2351 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2352 }
duke@0 2353 }
duke@0 2354 %}
duke@0 2355
duke@0 2356 // for byte regs
duke@0 2357 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2358 %{
duke@0 2359 if ($reg$$reg < 8) {
duke@0 2360 if ($mem$$base < 8) {
duke@0 2361 if ($mem$$index >= 8) {
duke@0 2362 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2363 } else if ($reg$$reg >= 4) {
duke@0 2364 emit_opcode(cbuf, Assembler::REX);
duke@0 2365 }
duke@0 2366 } else {
duke@0 2367 if ($mem$$index < 8) {
duke@0 2368 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2369 } else {
duke@0 2370 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2371 }
duke@0 2372 }
duke@0 2373 } else {
duke@0 2374 if ($mem$$base < 8) {
duke@0 2375 if ($mem$$index < 8) {
duke@0 2376 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2377 } else {
duke@0 2378 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2379 }
duke@0 2380 } else {
duke@0 2381 if ($mem$$index < 8) {
duke@0 2382 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2383 } else {
duke@0 2384 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2385 }
duke@0 2386 }
duke@0 2387 }
duke@0 2388 %}
duke@0 2389
duke@0 2390 enc_class REX_reg(rRegI reg)
duke@0 2391 %{
duke@0 2392 if ($reg$$reg >= 8) {
duke@0 2393 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2394 }
duke@0 2395 %}
duke@0 2396
duke@0 2397 enc_class REX_reg_wide(rRegI reg)
duke@0 2398 %{
duke@0 2399 if ($reg$$reg < 8) {
duke@0 2400 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2401 } else {
duke@0 2402 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2403 }
duke@0 2404 %}
duke@0 2405
duke@0 2406 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2407 %{
duke@0 2408 if ($dst$$reg < 8) {
duke@0 2409 if ($src$$reg >= 8) {
duke@0 2410 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2411 }
duke@0 2412 } else {
duke@0 2413 if ($src$$reg < 8) {
duke@0 2414 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2415 } else {
duke@0 2416 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2417 }
duke@0 2418 }
duke@0 2419 %}
duke@0 2420
duke@0 2421 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2422 %{
duke@0 2423 if ($dst$$reg < 8) {
duke@0 2424 if ($src$$reg < 8) {
duke@0 2425 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2426 } else {
duke@0 2427 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2428 }
duke@0 2429 } else {
duke@0 2430 if ($src$$reg < 8) {
duke@0 2431 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2432 } else {
duke@0 2433 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2434 }
duke@0 2435 }
duke@0 2436 %}
duke@0 2437
duke@0 2438 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 2439 %{
duke@0 2440 if ($reg$$reg < 8) {
duke@0 2441 if ($mem$$base < 8) {
duke@0 2442 if ($mem$$index >= 8) {
duke@0 2443 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2444 }
duke@0 2445 } else {
duke@0 2446 if ($mem$$index < 8) {
duke@0 2447 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2448 } else {
duke@0 2449 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2450 }
duke@0 2451 }
duke@0 2452 } else {
duke@0 2453 if ($mem$$base < 8) {
duke@0 2454 if ($mem$$index < 8) {
duke@0 2455 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2456 } else {
duke@0 2457 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2458 }
duke@0 2459 } else {
duke@0 2460 if ($mem$$index < 8) {
duke@0 2461 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2462 } else {
duke@0 2463 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2464 }
duke@0 2465 }
duke@0 2466 }
duke@0 2467 %}
duke@0 2468
duke@0 2469 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 2470 %{
duke@0 2471 if ($reg$$reg < 8) {
duke@0 2472 if ($mem$$base < 8) {
duke@0 2473 if ($mem$$index < 8) {
duke@0 2474 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2475 } else {
duke@0 2476 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2477 }
duke@0 2478 } else {
duke@0 2479 if ($mem$$index < 8) {
duke@0 2480 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2481 } else {
duke@0 2482 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2483 }
duke@0 2484 }
duke@0 2485 } else {
duke@0 2486 if ($mem$$base < 8) {
duke@0 2487 if ($mem$$index < 8) {
duke@0 2488 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2489 } else {
duke@0 2490 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 2491 }
duke@0 2492 } else {
duke@0 2493 if ($mem$$index < 8) {
duke@0 2494 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2495 } else {
duke@0 2496 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 2497 }
duke@0 2498 }
duke@0 2499 }
duke@0 2500 %}
duke@0 2501
duke@0 2502 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 2503 %{
duke@0 2504 // High registers handle in encode_RegMem
duke@0 2505 int reg = $ereg$$reg;
duke@0 2506 int base = $mem$$base;
duke@0 2507 int index = $mem$$index;
duke@0 2508 int scale = $mem$$scale;
duke@0 2509 int disp = $mem$$disp;
coleenp@3602 2510 relocInfo::relocType disp_reloc = $mem->disp_reloc();
coleenp@3602 2511
coleenp@3602 2512 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
duke@0 2513 %}
duke@0 2514
duke@0 2515 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 2516 %{
duke@0 2517 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 2518
duke@0 2519 // High registers handle in encode_RegMem
duke@0 2520 int base = $mem$$base;
duke@0 2521 int index = $mem$$index;
duke@0 2522 int scale = $mem$$scale;
duke@0 2523 int displace = $mem$$disp;
duke@0 2524
coleenp@3602 2525 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
duke@0 2526 // working with static
duke@0 2527 // globals
duke@0 2528 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
coleenp@3602 2529 disp_reloc);
duke@0 2530 %}
duke@0 2531
duke@0 2532 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 2533 %{
duke@0 2534 int reg_encoding = $dst$$reg;
duke@0 2535 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 2536 int index = 0x04; // 0x04 indicates no index
duke@0 2537 int scale = 0x00; // 0x00 indicates no scale
duke@0 2538 int displace = $src1$$constant; // 0x00 indicates no displacement
coleenp@3602 2539 relocInfo::relocType disp_reloc = relocInfo::none;
duke@0 2540 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
coleenp@3602 2541 disp_reloc);
duke@0 2542 %}
duke@0 2543
duke@0 2544 enc_class neg_reg(rRegI dst)
duke@0 2545 %{
duke@0 2546 int dstenc = $dst$$reg;
duke@0 2547 if (dstenc >= 8) {
duke@0 2548 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2549 dstenc -= 8;
duke@0 2550 }
duke@0 2551 // NEG $dst
duke@0 2552 emit_opcode(cbuf, 0xF7);
duke@0 2553 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2554 %}
duke@0 2555
duke@0 2556 enc_class neg_reg_wide(rRegI dst)
duke@0 2557 %{
duke@0 2558 int dstenc = $dst$$reg;
duke@0 2559 if (dstenc < 8) {
duke@0 2560 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2561 } else {
duke@0 2562 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2563 dstenc -= 8;
duke@0 2564 }
duke@0 2565 // NEG $dst
duke@0 2566 emit_opcode(cbuf, 0xF7);
duke@0 2567 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2568 %}
duke@0 2569
duke@0 2570 enc_class setLT_reg(rRegI dst)
duke@0 2571 %{
duke@0 2572 int dstenc = $dst$$reg;
duke@0 2573 if (dstenc >= 8) {
duke@0 2574 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2575 dstenc -= 8;
duke@0 2576 } else if (dstenc >= 4) {
duke@0 2577 emit_opcode(cbuf, Assembler::REX);
duke@0 2578 }
duke@0 2579 // SETLT $dst
duke@0 2580 emit_opcode(cbuf, 0x0F);
duke@0 2581 emit_opcode(cbuf, 0x9C);
duke@0 2582 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2583 %}
duke@0 2584
duke@0 2585 enc_class setNZ_reg(rRegI dst)
duke@0 2586 %{
duke@0 2587 int dstenc = $dst$$reg;
duke@0 2588 if (dstenc >= 8) {
duke@0 2589 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2590 dstenc -= 8;
duke@0 2591 } else if (dstenc >= 4) {
duke@0 2592 emit_opcode(cbuf, Assembler::REX);
duke@0 2593 }
duke@0 2594 // SETNZ $dst
duke@0 2595 emit_opcode(cbuf, 0x0F);
duke@0 2596 emit_opcode(cbuf, 0x95);
duke@0 2597 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2598 %}
duke@0 2599
duke@0 2600
duke@0 2601 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 2602 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 2603 %{
duke@0 2604 int src1enc = $src1$$reg;
duke@0 2605 int src2enc = $src2$$reg;
duke@0 2606 int dstenc = $dst$$reg;
duke@0 2607
duke@0 2608 // cmpq $src1, $src2
duke@0 2609 if (src1enc < 8) {
duke@0 2610 if (src2enc < 8) {
duke@0 2611 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2612 } else {
duke@0 2613 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2614 }
duke@0 2615 } else {
duke@0 2616 if (src2enc < 8) {
duke@0 2617 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2618 } else {
duke@0 2619 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2620 }
duke@0 2621 }
duke@0 2622 emit_opcode(cbuf, 0x3B);
duke@0 2623 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 2624
duke@0 2625 // movl $dst, -1
duke@0 2626 if (dstenc >= 8) {
duke@0 2627 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2628 }
duke@0 2629 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2630 emit_d32(cbuf, -1);
duke@0 2631
duke@0 2632 // jl,s done
duke@0 2633 emit_opcode(cbuf, 0x7C);
duke@0 2634 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2635
duke@0 2636 // setne $dst
duke@0 2637 if (dstenc >= 4) {
duke@0 2638 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2639 }
duke@0 2640 emit_opcode(cbuf, 0x0F);
duke@0 2641 emit_opcode(cbuf, 0x95);
duke@0 2642 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2643
duke@0 2644 // movzbl $dst, $dst
duke@0 2645 if (dstenc >= 4) {
duke@0 2646 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2647 }
duke@0 2648 emit_opcode(cbuf, 0x0F);
duke@0 2649 emit_opcode(cbuf, 0xB6);
duke@0 2650 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2651 %}
duke@0 2652
duke@0 2653 enc_class Push_ResultXD(regD dst) %{
kvn@2953 2654 MacroAssembler _masm(&cbuf);
kvn@2953 2655 __ fstp_d(Address(rsp, 0));
kvn@2953 2656 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
kvn@2953 2657 __ addptr(rsp, 8);
duke@0 2658 %}
duke@0 2659
duke@0 2660 enc_class Push_SrcXD(regD src) %{
duke@0 2661 MacroAssembler _masm(&cbuf);
kvn@2953 2662 __ subptr(rsp, 8);
kvn@2953 2663 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
kvn@2953 2664 __ fld_d(Address(rsp, 0));
kvn@2953 2665 %}
kvn@2953 2666
duke@0 2667
duke@0 2668 enc_class enc_rethrow()
duke@0 2669 %{
twisti@1668 2670 cbuf.set_insts_mark();
duke@0 2671 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 2672 emit_d32_reloc(cbuf,
twisti@1668 2673 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 2674 runtime_call_Relocation::spec(),
duke@0 2675 RELOC_DISP32);
duke@0 2676 %}
duke@0 2677
duke@0 2678 %}
duke@0 2679
duke@0 2680
coleenp@113 2681
duke@0 2682 //----------FRAME--------------------------------------------------------------
duke@0 2683 // Definition of frame structure and management information.
duke@0 2684 //
duke@0 2685 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 2686 // | (to get allocators register number
duke@0 2687 // G Owned by | | v add OptoReg::stack0())
duke@0 2688 // r CALLER | |
duke@0 2689 // o | +--------+ pad to even-align allocators stack-slot
duke@0 2690 // w V | pad0 | numbers; owned by CALLER
duke@0 2691 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 2692 // h ^ | in | 5
duke@0 2693 // | | args | 4 Holes in incoming args owned by SELF
duke@0 2694 // | | | | 3
duke@0 2695 // | | +--------+
duke@0 2696 // V | | old out| Empty on Intel, window on Sparc
duke@0 2697 // | old |preserve| Must be even aligned.
duke@0 2698 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 2699 // | | in | 3 area for Intel ret address
duke@0 2700 // Owned by |preserve| Empty on Sparc.
duke@0 2701 // SELF +--------+
duke@0 2702 // | | pad2 | 2 pad to align old SP
duke@0 2703 // | +--------+ 1
duke@0 2704 // | | locks | 0
duke@0 2705 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 2706 // | | pad1 | 11 pad to align new SP
duke@0 2707 // | +--------+
duke@0 2708 // | | | 10
duke@0 2709 // | | spills | 9 spills
duke@0 2710 // V | | 8 (pad0 slot for callee)
duke@0 2711 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 2712 // ^ | out | 7
duke@0 2713 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 2714 // Owned by +--------+
duke@0 2715 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 2716 // | new |preserve| Must be even-aligned.
duke@0 2717 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 2718 // | | |
duke@0 2719 //
duke@0 2720 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 2721 // known from SELF's arguments and the Java calling convention.
duke@0 2722 // Region 6-7 is determined per call site.
duke@0 2723 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 2724 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 2725 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 2726 // incoming area, as the Java calling convention is completely under
duke@0 2727 // the control of the AD file. Doubles can be sorted and packed to
duke@0 2728 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 2729 // varargs C calling conventions.
duke@0 2730 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 2731 // even aligned with pad0 as needed.
duke@0 2732 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 2733 // region 6-11 is even aligned; it may be padded out more so that
duke@0 2734 // the region from SP to FP meets the minimum stack alignment.
duke@0 2735 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
duke@0 2736 // alignment. Region 11, pad1, may be dynamically extended so that
duke@0 2737 // SP meets the minimum alignment.
duke@0 2738
duke@0 2739 frame
duke@0 2740 %{
duke@0 2741 // What direction does stack grow in (assumed to be same for C & Java)
duke@0 2742 stack_direction(TOWARDS_LOW);
duke@0 2743
duke@0 2744 // These three registers define part of the calling convention
duke@0 2745 // between compiled code and the interpreter.
duke@0 2746 inline_cache_reg(RAX); // Inline Cache Register
duke@0 2747 interpreter_method_oop_reg(RBX); // Method Oop Register when
duke@0 2748 // calling interpreter
duke@0 2749
duke@0 2750 // Optional: name the operand used by cisc-spilling to access
duke@0 2751 // [stack_pointer + offset]
duke@0 2752 cisc_spilling_operand_name(indOffset32);
duke@0 2753
duke@0 2754 // Number of stack slots consumed by locking an object
duke@0 2755 sync_stack_slots(2);
duke@0 2756
duke@0 2757 // Compiled code's Frame Pointer
duke@0 2758 frame_pointer(RSP);
duke@0 2759
duke@0 2760 // Interpreter stores its frame pointer in a register which is
duke@0 2761 // stored to the stack by I2CAdaptors.
duke@0 2762 // I2CAdaptors convert from interpreted java to compiled java.
duke@0 2763 interpreter_frame_pointer(RBP);
duke@0 2764
duke@0 2765 // Stack alignment requirement
duke@0 2766 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
duke@0 2767
duke@0 2768 // Number of stack slots between incoming argument block and the start of
duke@0 2769 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 2770 // EPILOG must remove this many slots. amd64 needs two slots for
duke@0 2771 // return address.
duke@0 2772 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
duke@0 2773
duke@0 2774 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 2775 // for calls to C. Supports the var-args backing area for register parms.
duke@0 2776 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
duke@0 2777
duke@0 2778 // The after-PROLOG location of the return address. Location of
duke@0 2779 // return address specifies a type (REG or STACK) and a number
duke@0 2780 // representing the register number (i.e. - use a register name) or
duke@0 2781 // stack slot.
duke@0 2782 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
duke@0 2783 // Otherwise, it is above the locks and verification slot and alignment word
duke@0 2784 return_addr(STACK - 2 +
kvn@3142 2785 round_to((Compile::current()->in_preserve_stack_slots() +
kvn@3142 2786 Compile::current()->fixed_slots()),
kvn@3142 2787 stack_alignment_in_slots()));
duke@0 2788
duke@0 2789 // Body of function which returns an integer array locating
duke@0 2790 // arguments either in registers or in stack slots. Passed an array
duke@0 2791 // of ideal registers called "sig" and a "length" count. Stack-slot
duke@0 2792 // offsets are based on outgoing arguments, i.e. a CALLER setting up
duke@0 2793 // arguments for a CALLEE. Incoming stack arguments are
duke@0 2794 // automatically biased by the preserve_stack_slots field above.
duke@0 2795
duke@0 2796 calling_convention
duke@0 2797 %{
duke@0 2798 // No difference between ingoing/outgoing just pass false
duke@0 2799 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
duke@0 2800 %}
duke@0 2801
duke@0 2802 c_calling_convention
duke@0 2803 %{
duke@0 2804 // This is obviously always outgoing
goetz@5970 2805 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
duke@0 2806 %}
duke@0 2807
duke@0 2808 // Location of compiled Java return values. Same as C for now.
duke@0 2809 return_value
duke@0 2810 %{
duke@0 2811 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
duke@0 2812 "only return normal values");
duke@0 2813
duke@0 2814 static const int lo[Op_RegL + 1] = {
duke@0 2815 0,
duke@0 2816 0,
coleenp@113 2817 RAX_num, // Op_RegN
duke@0 2818 RAX_num, // Op_RegI
duke@0 2819 RAX_num, // Op_RegP
duke@0 2820 XMM0_num, // Op_RegF
duke@0 2821 XMM0_num, // Op_RegD
duke@0 2822 RAX_num // Op_RegL
duke@0 2823 };
duke@0 2824 static const int hi[Op_RegL + 1] = {
duke@0 2825 0,
duke@0 2826 0,
coleenp@113 2827 OptoReg::Bad, // Op_RegN
duke@0 2828 OptoReg::Bad, // Op_RegI
duke@0 2829 RAX_H_num, // Op_RegP
duke@0 2830 OptoReg::Bad, // Op_RegF
kvn@3447 2831 XMM0b_num, // Op_RegD
duke@0 2832 RAX_H_num // Op_RegL
duke@0 2833 };
kvn@3447 2834 // Excluded flags and vector registers.
kvn@3447 2835 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
duke@0 2836 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
duke@0 2837 %}
duke@0 2838 %}
duke@0 2839
duke@0 2840 //----------ATTRIBUTES---------------------------------------------------------
duke@0 2841 //----------Operand Attributes-------------------------------------------------
duke@0 2842 op_attrib op_cost(0); // Required cost attribute
duke@0 2843
duke@0 2844 //----------Instruction Attributes---------------------------------------------
duke@0 2845 ins_attrib ins_cost(100); // Required cost attribute
duke@0 2846 ins_attrib ins_size(8); // Required size attribute (in bits)
duke@0 2847 ins_attrib ins_short_branch(0); // Required flag: is this instruction
duke@0 2848 // a non-matching short branch variant
duke@0 2849 // of some long branch?
duke@0 2850 ins_attrib ins_alignment(1); // Required alignment attribute (must
duke@0 2851 // be a power of 2) specifies the
duke@0 2852 // alignment that some part of the
duke@0 2853 // instruction (not necessarily the
duke@0 2854 // start) requires. If > 1, a
duke@0 2855 // compute_padding() function must be
duke@0 2856 // provided for the instruction
duke@0 2857
duke@0 2858 //----------OPERANDS-----------------------------------------------------------
duke@0 2859 // Operand definitions must precede instruction definitions for correct parsing
duke@0 2860 // in the ADLC because operands constitute user defined types which are used in
duke@0 2861 // instruction definitions.
duke@0 2862
duke@0 2863 //----------Simple Operands----------------------------------------------------
duke@0 2864 // Immediate Operands
duke@0 2865 // Integer Immediate
duke@0 2866 operand immI()
duke@0 2867 %{
duke@0 2868 match(ConI);
duke@0 2869
duke@0 2870 op_cost(10);
duke@0 2871 format %{ %}
duke@0 2872 interface(CONST_INTER);
duke@0 2873 %}
duke@0 2874
duke@0 2875 // Constant for test vs zero
duke@0 2876 operand immI0()
duke@0 2877 %{
duke@0 2878 predicate(n->get_int() == 0);
duke@0 2879 match(ConI);
duke@0 2880
duke@0 2881 op_cost(0);
duke@0 2882 format %{ %}
duke@0 2883 interface(CONST_INTER);
duke@0 2884 %}
duke@0 2885
duke@0 2886 // Constant for increment
duke@0 2887 operand immI1()
duke@0 2888 %{
duke@0 2889 predicate(n->get_int() == 1);
duke@0 2890 match(ConI);
duke@0 2891
duke@0 2892 op_cost(0);
duke@0 2893 format %{ %}
duke@0 2894 interface(CONST_INTER);
duke@0 2895 %}
duke@0 2896
duke@0 2897 // Constant for decrement
duke@0 2898 operand immI_M1()
duke@0 2899 %{
duke@0 2900 predicate(n->get_int() == -1);
duke@0 2901 match(ConI);
duke@0 2902
duke@0 2903 op_cost(0);
duke@0 2904 format %{ %}
duke@0 2905 interface(CONST_INTER);
duke@0 2906 %}
duke@0 2907
duke@0 2908 // Valid scale values for addressing modes
duke@0 2909 operand immI2()
duke@0 2910 %{
duke@0 2911 predicate(0 <= n->get_int() && (n->get_int() <= 3));
duke@0 2912 match(ConI);
duke@0 2913
duke@0 2914 format %{ %}
duke@0 2915 interface(CONST_INTER);
duke@0 2916 %}
duke@0 2917
duke@0 2918 operand immI8()
duke@0 2919 %{
duke@0 2920 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
duke@0 2921 match(ConI);
duke@0 2922
duke@0 2923 op_cost(5);
duke@0 2924 format %{ %}
duke@0 2925 interface(CONST_INTER);
duke@0 2926 %}
duke@0 2927
duke@0 2928 operand immI16()
duke@0 2929 %{
duke@0 2930 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
duke@0 2931 match(ConI);
duke@0 2932
duke@0 2933 op_cost(10);
duke@0 2934 format %{ %}
duke@0 2935 interface(CONST_INTER);
duke@0 2936 %}
duke@0 2937
iveresov@5824 2938 // Int Immediate non-negative
iveresov@5824 2939 operand immU31()
iveresov@5824 2940 %{
iveresov@5824 2941 predicate(n->get_int() >= 0);
iveresov@5824 2942 match(ConI);
iveresov@5824 2943
iveresov@5824 2944 op_cost(0);
iveresov@5824 2945 format %{ %}
iveresov@5824 2946 interface(CONST_INTER);
iveresov@5824 2947 %}
iveresov@5824 2948
duke@0 2949 // Constant for long shifts
duke@0 2950 operand immI_32()
duke@0 2951 %{
duke@0 2952 predicate( n->get_int() == 32 );
duke@0 2953 match(ConI);
duke@0 2954
duke@0 2955 op_cost(0);
duke@0 2956 format %{ %}
duke@0 2957 interface(CONST_INTER);
duke@0 2958 %}
duke@0 2959
duke@0 2960 // Constant for long shifts
duke@0 2961 operand immI_64()
duke@0 2962 %{
duke@0 2963 predicate( n->get_int() == 64 );
duke@0 2964 match(ConI);
duke@0 2965
duke@0 2966 op_cost(0);
duke@0 2967 format %{ %}
duke@0 2968 interface(CONST_INTER);
duke@0 2969 %}
duke@0 2970
duke@0 2971 // Pointer Immediate
duke@0 2972 operand immP()
duke@0 2973 %{
duke@0 2974 match(ConP);
duke@0 2975
duke@0 2976 op_cost(10);
duke@0 2977 format %{ %}
duke@0 2978 interface(CONST_INTER);
duke@0 2979 %}
duke@0 2980
duke@0 2981 // NULL Pointer Immediate
duke@0 2982 operand immP0()
duke@0 2983 %{
duke@0 2984 predicate(n->get_ptr() == 0);
duke@0 2985 match(ConP);
duke@0 2986
duke@0 2987 op_cost(5);
duke@0 2988 format %{ %}
duke@0 2989 interface(CONST_INTER);
duke@0 2990 %}
duke@0 2991
coleenp@113 2992 // Pointer Immediate
coleenp@113 2993 operand immN() %{
coleenp@113 2994 match(ConN);
coleenp@113 2995
coleenp@113 2996 op_cost(10);
coleenp@113 2997 format %{ %}
coleenp@113 2998 interface(CONST_INTER);
coleenp@113 2999 %}
coleenp@113 3000
roland@3724 3001 operand immNKlass() %{
roland@3724 3002 match(ConNKlass);
roland@3724 3003
roland@3724 3004 op_cost(10);
roland@3724 3005 format %{ %}
roland@3724 3006 interface(CONST_INTER);
roland@3724 3007 %}
roland@3724 3008
coleenp@113 3009 // NULL Pointer Immediate
coleenp@113 3010 operand immN0() %{
coleenp@113 3011 predicate(n->get_narrowcon() == 0);
coleenp@113 3012 match(ConN);
coleenp@113 3013
coleenp@113 3014 op_cost(5);
coleenp@113 3015 format %{ %}
coleenp@113 3016 interface(CONST_INTER);
coleenp@113 3017 %}
coleenp@113 3018
duke@0 3019 operand immP31()
duke@0 3020 %{
coleenp@3602 3021 predicate(n->as_Type()->type()->reloc() == relocInfo::none
duke@0 3022 && (n->get_ptr() >> 31) == 0);
duke@0 3023 match(ConP);
duke@0 3024
duke@0 3025 op_cost(5);
duke@0 3026 format %{ %}
duke@0 3027 interface(CONST_INTER);
duke@0 3028 %}
duke@0 3029
coleenp@113 3030
duke@0 3031 // Long Immediate
duke@0 3032 operand immL()
duke@0 3033 %{
duke@0 3034 match(ConL);
duke@0 3035
duke@0 3036 op_cost(20);
duke@0 3037 format %{ %}
duke@0 3038 interface(CONST_INTER);
duke@0 3039 %}
duke@0 3040
duke@0 3041 // Long Immediate 8-bit
duke@0 3042 operand immL8()
duke@0 3043 %{
duke@0 3044 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
duke@0 3045 match(ConL);
duke@0 3046
duke@0 3047 op_cost(5);
duke@0 3048 format %{ %}
duke@0 3049 interface(CONST_INTER);
duke@0 3050 %}
duke@0 3051
duke@0 3052 // Long Immediate 32-bit unsigned
duke@0 3053 operand immUL32()
duke@0 3054 %{
duke@0 3055 predicate(n->get_long() == (unsigned int) (n->get_long()));
duke@0 3056 match(ConL);
duke@0 3057
duke@0 3058 op_cost(10);
duke@0 3059 format %{ %}
duke@0 3060 interface(CONST_INTER);
duke@0 3061 %}
duke@0 3062
duke@0 3063 // Long Immediate 32-bit signed
duke@0 3064 operand immL32()
duke@0 3065 %{
duke@0 3066 predicate(n->get_long() == (int) (n->get_long()));
duke@0 3067 match(ConL);
duke@0 3068
duke@0 3069 op_cost(15);
duke@0 3070 format %{ %}
duke@0 3071 interface(CONST_INTER);
duke@0 3072 %}
duke@0 3073
duke@0 3074 // Long Immediate zero
duke@0 3075 operand immL0()
duke@0 3076 %{
duke@0 3077 predicate(n->get_long() == 0L);
duke@0 3078 match(ConL);
duke@0 3079
duke@0 3080 op_cost(10);
duke@0 3081 format %{ %}
duke@0 3082 interface(CONST_INTER);
duke@0 3083 %}
duke@0 3084
duke@0 3085 // Constant for increment
duke@0 3086 operand immL1()
duke@0 3087 %{
duke@0 3088 predicate(n->get_long() == 1);
duke@0 3089 match(ConL);
duke@0 3090
duke@0 3091 format %{ %}
duke@0 3092 interface(CONST_INTER);
duke@0 3093 %}
duke@0 3094
duke@0 3095 // Constant for decrement
duke@0 3096 operand immL_M1()
duke@0 3097 %{
duke@0 3098 predicate(n->get_long() == -1);
duke@0 3099 match(ConL);
duke@0 3100
duke@0 3101 format %{ %}
duke@0 3102 interface(CONST_INTER);
duke@0 3103 %}
duke@0 3104
duke@0 3105 // Long Immediate: the value 10
duke@0 3106 operand immL10()
duke@0 3107 %{
duke@0 3108 predicate(n->get_long() == 10);
duke@0 3109 match(ConL);
duke@0 3110
duke@0 3111 format %{ %}
duke@0 3112 interface(CONST_INTER);
duke@0 3113 %}
duke@0 3114
duke@0 3115 // Long immediate from 0 to 127.
duke@0 3116 // Used for a shorter form of long mul by 10.
duke@0 3117 operand immL_127()
duke@0 3118 %{
duke@0 3119 predicate(0 <= n->get_long() && n->get_long() < 0x80);
duke@0 3120 match(ConL);
duke@0 3121
duke@0 3122 op_cost(10);
duke@0 3123 format %{ %}
duke@0 3124 interface(CONST_INTER);
duke@0 3125 %}
duke@0 3126
duke@0 3127 // Long Immediate: low 32-bit mask
duke@0 3128 operand immL_32bits()
duke@0 3129 %{
duke@0 3130 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 3131 match(ConL);
duke@0 3132 op_cost(20);
duke@0 3133
duke@0 3134 format %{ %}
duke@0 3135 interface(CONST_INTER);
duke@0 3136 %}
duke@0 3137
duke@0 3138 // Float Immediate zero
duke@0 3139 operand immF0()
duke@0 3140 %{
duke@0 3141 predicate(jint_cast(n->getf()) == 0);
duke@0 3142 match(ConF);
duke@0 3143
duke@0 3144 op_cost(5);
duke@0 3145 format %{ %}
duke@0 3146 interface(CONST_INTER);
duke@0 3147 %}
duke@0 3148
duke@0 3149 // Float Immediate
duke@0 3150 operand immF()
duke@0 3151 %{
duke@0 3152 match(ConF);
duke@0 3153
duke@0 3154 op_cost(15);
duke@0 3155 format %{ %}
duke@0 3156 interface(CONST_INTER);
duke@0 3157 %}
duke@0 3158
duke@0 3159 // Double Immediate zero
duke@0 3160 operand immD0()
duke@0 3161 %{
duke@0 3162 predicate(jlong_cast(n->getd()) == 0);
duke@0 3163 match(ConD);
duke@0 3164
duke@0 3165 op_cost(5);
duke@0 3166 format %{ %}
duke@0 3167 interface(CONST_INTER);
duke@0 3168 %}
duke@0 3169
duke@0 3170 // Double Immediate
duke@0 3171 operand immD()
duke@0 3172 %{
duke@0 3173 match(ConD);
duke@0 3174
duke@0 3175 op_cost(15);
duke@0 3176 format %{ %}
duke@0 3177 interface(CONST_INTER);
duke@0 3178 %}
duke@0 3179
duke@0 3180 // Immediates for special shifts (sign extend)
duke@0 3181
duke@0 3182 // Constants for increment
duke@0 3183 operand immI_16()
duke@0 3184 %{
duke@0 3185 predicate(n->get_int() == 16);
duke@0 3186 match(ConI);
duke@0 3187
duke@0 3188 format %{ %}
duke@0 3189 interface(CONST_INTER);
duke@0 3190 %}
duke@0 3191
duke@0 3192 operand immI_24()
duke@0 3193 %{
duke@0 3194 predicate(n->get_int() == 24);
duke@0 3195 match(ConI);
duke@0 3196
duke@0 3197 format %{ %}
duke@0 3198 interface(CONST_INTER);
duke@0 3199 %}
duke@0 3200
duke@0 3201 // Constant for byte-wide masking
duke@0 3202 operand immI_255()
duke@0 3203 %{
duke@0 3204 predicate(n->get_int() == 255);
duke@0 3205 match(ConI);
duke@0 3206
duke@0 3207 format %{ %}
duke@0 3208 interface(CONST_INTER);
duke@0 3209 %}
duke@0 3210
duke@0 3211 // Constant for short-wide masking
duke@0 3212 operand immI_65535()
duke@0 3213 %{
duke@0 3214 predicate(n->get_int() == 65535);
duke@0 3215 match(ConI);
duke@0 3216
duke@0 3217 format %{ %}
duke@0 3218 interface(CONST_INTER);
duke@0 3219 %}
duke@0 3220
duke@0 3221 // Constant for byte-wide masking
duke@0 3222 operand immL_255()
duke@0 3223 %{
duke@0 3224 predicate(n->get_long() == 255);
duke@0 3225 match(ConL);
duke@0 3226
duke@0 3227 format %{ %}
duke@0 3228 interface(CONST_INTER);
duke@0 3229 %}
duke@0 3230
duke@0 3231 // Constant for short-wide masking
duke@0 3232 operand immL_65535()
duke@0 3233 %{
duke@0 3234 predicate(n->get_long() == 65535);
duke@0 3235 match(ConL);
duke@0 3236
duke@0 3237 format %{ %}
duke@0 3238 interface(CONST_INTER);
duke@0 3239 %}
duke@0 3240
duke@0 3241 // Register Operands
duke@0 3242 // Integer Register
duke@0 3243 operand rRegI()
duke@0 3244 %{
duke@0 3245 constraint(ALLOC_IN_RC(int_reg));
duke@0 3246 match(RegI);
duke@0 3247
duke@0 3248 match(rax_RegI);
duke@0 3249 match(rbx_RegI);
duke@0 3250 match(rcx_RegI);
duke@0 3251 match(rdx_RegI);
duke@0 3252 match(rdi_RegI);
duke@0 3253
duke@0 3254 format %{ %}
duke@0 3255 interface(REG_INTER);
duke@0 3256 %}
duke@0 3257
duke@0 3258 // Special Registers
duke@0 3259 operand rax_RegI()
duke@0 3260 %{
duke@0 3261 constraint(ALLOC_IN_RC(int_rax_reg));
duke@0 3262 match(RegI);
duke@0 3263 match(rRegI);
duke@0 3264
duke@0 3265 format %{ "RAX" %}
duke@0 3266 interface(REG_INTER);
duke@0 3267 %}
duke@0 3268
duke@0 3269 // Special Registers
duke@0 3270 operand rbx_RegI()
duke@0 3271 %{
duke@0 3272 constraint(ALLOC_IN_RC(int_rbx_reg));
duke@0 3273 match(RegI);
duke@0 3274 match(rRegI);
duke@0 3275
duke@0 3276 format %{ "RBX" %}
duke@0 3277 interface(REG_INTER);
duke@0 3278 %}
duke@0 3279
duke@0 3280 operand rcx_RegI()
duke@0 3281 %{
duke@0 3282 constraint(ALLOC_IN_RC(int_rcx_reg));
duke@0 3283 match(RegI);
duke@0 3284 match(rRegI);
duke@0 3285
duke@0 3286 format %{ "RCX" %}
duke@0 3287 interface(REG_INTER);
duke@0 3288 %}
duke@0 3289
duke@0 3290 operand rdx_RegI()
duke@0 3291 %{
duke@0 3292 constraint(ALLOC_IN_RC(int_rdx_reg));
duke@0 3293 match(RegI);
duke@0 3294 match(rRegI);
duke@0 3295
duke@0 3296 format %{ "RDX" %}
duke@0 3297 interface(REG_INTER);
duke@0 3298 %}
duke@0 3299
duke@0 3300 operand rdi_RegI()
duke@0 3301 %{
duke@0 3302 constraint(ALLOC_IN_RC(int_rdi_reg));
duke@0 3303 match(RegI);
duke@0 3304 match(rRegI);
duke@0 3305
duke@0 3306 format %{ "RDI" %}
duke@0 3307 interface(REG_INTER);
duke@0 3308 %}
duke@0 3309
duke@0 3310 operand no_rcx_RegI()
duke@0 3311 %{
duke@0 3312 constraint(ALLOC_IN_RC(int_no_rcx_reg));
duke@0 3313 match(RegI);
duke@0 3314 match(rax_RegI);
duke@0 3315 match(rbx_RegI);
duke@0 3316 match(rdx_RegI);
duke@0 3317 match(rdi_RegI);
duke@0 3318
duke@0 3319 format %{ %}
duke@0 3320 interface(REG_INTER);
duke@0 3321 %}
duke@0 3322
duke@0 3323 operand no_rax_rdx_RegI()
duke@0 3324 %{
duke@0 3325 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
duke@0 3326 match(RegI);
duke@0 3327 match(rbx_RegI);
duke@0 3328 match(rcx_RegI);
duke@0 3329 match(rdi_RegI);
duke@0 3330
duke@0 3331 format %{ %}
duke@0 3332 interface(REG_INTER);
duke@0 3333 %}
duke@0 3334
duke@0 3335 // Pointer Register
duke@0 3336 operand any_RegP()
duke@0 3337 %{
zmajo@8290 3338 constraint(ALLOC_IN_RC(any_reg));
duke@0 3339 match(RegP);
duke@0 3340 match(rax_RegP);
duke@0 3341 match(rbx_RegP);
duke@0 3342 match(rdi_RegP);
duke@0 3343 match(rsi_RegP);
duke@0 3344 match(rbp_RegP);
duke@0 3345 match(r15_RegP);
duke@0 3346 match(rRegP);
duke@0 3347
duke@0 3348 format %{ %}
duke@0 3349 interface(REG_INTER);
duke@0 3350 %}
duke@0 3351
duke@0 3352 operand rRegP()
duke@0 3353 %{
duke@0 3354 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3355 match(RegP);
duke@0 3356 match(rax_RegP);
duke@0 3357 match(rbx_RegP);
duke@0 3358 match(rdi_RegP);
duke@0 3359 match(rsi_RegP);
zmajo@8290 3360 match(rbp_RegP); // See Q&A below about
zmajo@8290 3361 match(r15_RegP); // r15_RegP and rbp_RegP.
duke@0 3362
duke@0 3363 format %{ %}
duke@0 3364 interface(REG_INTER);
duke@0 3365 %}
duke@0 3366
coleenp@113 3367 operand rRegN() %{
coleenp@113 3368 constraint(ALLOC_IN_RC(int_reg));
coleenp@113 3369 match(RegN);
coleenp@113 3370
coleenp@113 3371 format %{ %}
coleenp@113 3372 interface(REG_INTER);
coleenp@113 3373 %}
coleenp@113 3374
duke@0 3375 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
duke@0 3376 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
zmajo@8290 3377 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
duke@0 3378 // The output of an instruction is controlled by the allocator, which respects
duke@0 3379 // register class masks, not match rules. Unless an instruction mentions
duke@0 3380 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
duke@0 3381 // by the allocator as an input.
zmajo@8290 3382 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
zmajo@8290 3383 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
zmajo@8290 3384 // result, RBP is not included in the output of the instruction either.
duke@0 3385
duke@0 3386 operand no_rax_RegP()
duke@0 3387 %{
duke@0 3388 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
duke@0 3389 match(RegP);
duke@0 3390 match(rbx_RegP);
duke@0 3391 match(rsi_RegP);
duke@0 3392 match(rdi_RegP);
duke@0 3393
duke@0 3394 format %{ %}
duke@0 3395 interface(REG_INTER);
duke@0 3396 %}
duke@0 3397
zmajo@8290 3398 // This operand is not allowed to use RBP even if
zmajo@8290 3399 // RBP is not used to hold the frame pointer.
duke@0 3400 operand no_rbp_RegP()
duke@0 3401 %{
zmajo@8290 3402 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
duke@0 3403 match(RegP);
duke@0 3404 match(rbx_RegP);
duke@0 3405 match(rsi_RegP);
duke@0 3406 match(rdi_RegP);
duke@0 3407
duke@0 3408 format %{ %}
duke@0 3409 interface(REG_INTER);
duke@0 3410 %}
duke@0 3411
duke@0 3412 operand no_rax_rbx_RegP()
duke@0 3413 %{
duke@0 3414 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
duke@0 3415 match(RegP);
duke@0 3416 match(rsi_RegP);
duke@0 3417 match(rdi_RegP);
duke@0 3418
duke@0 3419 format %{ %}
duke@0 3420 interface(REG_INTER);
duke@0 3421 %}
duke@0 3422
duke@0 3423 // Special Registers
duke@0 3424 // Return a pointer value
duke@0 3425 operand rax_RegP()
duke@0 3426 %{
duke@0 3427 constraint(ALLOC_IN_RC(ptr_rax_reg));
duke@0 3428 match(RegP);
duke@0 3429 match(rRegP);
duke@0 3430
duke@0 3431 format %{ %}
duke@0 3432 interface(REG_INTER);
duke@0 3433 %}
duke@0 3434
coleenp@113 3435 // Special Registers
coleenp@113 3436 // Return a compressed pointer value
coleenp@113 3437 operand rax_RegN()
coleenp@113 3438 %{
coleenp@113 3439 constraint(ALLOC_IN_RC(int_rax_reg));
coleenp@113 3440 match(RegN);
coleenp@113 3441 match(rRegN);
coleenp@113 3442
coleenp@113 3443 format %{ %}
coleenp@113 3444 interface(REG_INTER);
coleenp@113 3445 %}
coleenp@113 3446
duke@0 3447 // Used in AtomicAdd
duke@0 3448 operand rbx_RegP()
duke@0 3449 %{
duke@0 3450 constraint(ALLOC_IN_RC(ptr_rbx_reg));
duke@0 3451 match(RegP);
duke@0 3452 match(rRegP);
duke@0 3453
duke@0 3454 format %{ %}
duke@0 3455 interface(REG_INTER);
duke@0 3456 %}
duke@0 3457
duke@0 3458 operand rsi_RegP()
duke@0 3459 %{
duke@0 3460 constraint(ALLOC_IN_RC(ptr_rsi_reg));
duke@0 3461 match(RegP);
duke@0 3462 match(rRegP);
duke@0 3463
duke@0 3464 format %{ %}
duke@0 3465 interface(REG_INTER);
duke@0 3466 %}
duke@0 3467
duke@0 3468 // Used in rep stosq
duke@0 3469 operand rdi_RegP()
duke@0 3470 %{
duke@0 3471 constraint(ALLOC_IN_RC(ptr_rdi_reg));
duke@0 3472 match(RegP);
duke@0 3473 match(rRegP);
duke@0 3474
duke@0 3475 format %{ %}
duke@0 3476 interface(REG_INTER);
duke@0 3477 %}
duke@0 3478
duke@0 3479 operand r15_RegP()
duke@0 3480 %{
duke@0 3481 constraint(ALLOC_IN_RC(ptr_r15_reg));
duke@0 3482 match(RegP);
duke@0 3483 match(rRegP);
duke@0 3484
duke@0 3485 format %{ %}
duke@0 3486 interface(REG_INTER);
duke@0 3487 %}
duke@0 3488
duke@0 3489 operand rRegL()
duke@0 3490 %{
duke@0 3491 constraint(ALLOC_IN_RC(long_reg));
duke@0 3492 match(RegL);
duke@0 3493 match(rax_RegL);
duke@0 3494 match(rdx_RegL);
duke@0 3495
duke@0 3496 format %{ %}
duke@0 3497 interface(REG_INTER);
duke@0 3498 %}
duke@0 3499
duke@0 3500 // Special Registers
duke@0 3501 operand no_rax_rdx_RegL()
duke@0 3502 %{
duke@0 3503 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3504 match(RegL);
duke@0 3505 match(rRegL);
duke@0 3506
duke@0 3507 format %{ %}
duke@0 3508 interface(REG_INTER);
duke@0 3509 %}
duke@0 3510
duke@0 3511 operand no_rax_RegL()
duke@0 3512 %{
duke@0 3513 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3514 match(RegL);
duke@0 3515 match(rRegL);
duke@0 3516 match(rdx_RegL);
duke@0 3517
duke@0 3518 format %{ %}
duke@0 3519 interface(REG_INTER);
duke@0 3520 %}
duke@0 3521
duke@0 3522 operand no_rcx_RegL()
duke@0 3523 %{
duke@0 3524 constraint(ALLOC_IN_RC(long_no_rcx_reg));
duke@0 3525 match(RegL);
duke@0 3526 match(rRegL);
duke@0 3527
duke@0 3528 format %{ %}
duke@0 3529 interface(REG_INTER);
duke@0 3530 %}
duke@0 3531
duke@0 3532 operand rax_RegL()
duke@0 3533 %{
duke@0 3534 constraint(ALLOC_IN_RC(long_rax_reg));
duke@0 3535 match(RegL);
duke@0 3536 match(rRegL);
duke@0 3537
duke@0 3538 format %{ "RAX" %}
duke@0 3539 interface(REG_INTER);
duke@0 3540 %}
duke@0 3541
duke@0 3542 operand rcx_RegL()
duke@0 3543 %{
duke@0 3544 constraint(ALLOC_IN_RC(long_rcx_reg));
duke@0 3545 match(RegL);
duke@0 3546 match(rRegL);
duke@0 3547
duke@0 3548 format %{ %}
duke@0 3549 interface(REG_INTER);
duke@0 3550 %}
duke@0 3551
duke@0 3552 operand rdx_RegL()
duke@0 3553 %{
duke@0 3554 constraint(ALLOC_IN_RC(long_rdx_reg));
duke@0 3555 match(RegL);
duke@0 3556 match(rRegL);
duke@0 3557
duke@0 3558 format %{ %}
duke@0 3559 interface(REG_INTER);
duke@0 3560 %}
duke@0 3561
duke@0 3562 // Flags register, used as output of compare instructions
duke@0 3563 operand rFlagsReg()
duke@0 3564 %{
duke@0 3565 constraint(ALLOC_IN_RC(int_flags));
duke@0 3566 match(RegFlags);
duke@0 3567
duke@0 3568 format %{ "RFLAGS" %}
duke@0 3569 interface(REG_INTER);
duke@0 3570 %}
duke@0 3571
duke@0 3572 // Flags register, used as output of FLOATING POINT compare instructions
duke@0 3573 operand rFlagsRegU()
duke@0 3574 %{
duke@0 3575 constraint(ALLOC_IN_RC(int_flags));
duke@0 3576 match(RegFlags);
duke@0 3577
duke@0 3578 format %{ "RFLAGS_U" %}
duke@0 3579 interface(REG_INTER);
duke@0 3580 %}
duke@0 3581
never@415 3582 operand rFlagsRegUCF() %{
never@415 3583 constraint(ALLOC_IN_RC(int_flags));
never@415 3584 match(RegFlags);
never@415 3585 predicate(false);
never@415 3586
never@415 3587 format %{ "RFLAGS_U_CF" %}
never@415 3588 interface(REG_INTER);
never@415 3589 %}
never@415 3590
duke@0 3591 // Float register operands
duke@0 3592 operand regF()
duke@0 3593 %{
duke@0 3594 constraint(ALLOC_IN_RC(float_reg));
duke@0 3595 match(RegF);
duke@0 3596
duke@0 3597 format %{ %}
duke@0 3598 interface(REG_INTER);
duke@0 3599 %}
duke@0 3600
duke@0 3601 // Double register operands
iveresov@2251 3602 operand regD()
duke@0 3603 %{
duke@0 3604 constraint(ALLOC_IN_RC(double_reg));
duke@0 3605 match(RegD);
duke@0 3606
duke@0 3607 format %{ %}
duke@0 3608 interface(REG_INTER);
duke@0 3609 %}
duke@0 3610
duke@0 3611 //----------Memory Operands----------------------------------------------------
duke@0 3612 // Direct Memory Operand
duke@0 3613 // operand direct(immP addr)
duke@0 3614 // %{
duke@0 3615 // match(addr);
duke@0 3616
duke@0 3617 // format %{ "[$addr]" %}
duke@0 3618 // interface(MEMORY_INTER) %{
duke@0 3619 // base(0xFFFFFFFF);
duke@0 3620 // index(0x4);
duke@0 3621 // scale(0x0);
duke@0 3622 // disp($addr);
duke@0 3623 // %}
duke@0 3624 // %}
duke@0 3625
duke@0 3626 // Indirect Memory Operand
duke@0 3627 operand indirect(any_RegP reg)
duke@0 3628 %{
duke@0 3629 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3630 match(reg);
duke@0 3631
duke@0 3632 format %{ "[$reg]" %}
duke@0 3633 interface(MEMORY_INTER) %{
duke@0 3634 base($reg);
duke@0 3635 index(0x4);
duke@0 3636 scale(0x0);
duke@0 3637 disp(0x0);
duke@0 3638 %}
duke@0 3639 %}
duke@0 3640
duke@0 3641 // Indirect Memory Plus Short Offset Operand
duke@0 3642 operand indOffset8(any_RegP reg, immL8 off)
duke@0 3643 %{
duke@0 3644 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3645 match(AddP reg off);
duke@0 3646
duke@0 3647 format %{ "[$reg + $off (8-bit)]" %}
duke@0 3648 interface(MEMORY_INTER) %{
duke@0 3649 base($reg);
duke@0 3650 index(0x4);
duke@0 3651 scale(0x0);
duke@0 3652 disp($off);
duke@0 3653 %}
duke@0 3654 %}
duke@0 3655
duke@0 3656 // Indirect Memory Plus Long Offset Operand
duke@0 3657 operand indOffset32(any_RegP reg, immL32 off)
duke@0 3658 %{
duke@0 3659 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3660 match(AddP reg off);
duke@0 3661
duke@0 3662 format %{ "[$reg + $off (32-bit)]" %}
duke@0 3663 interface(MEMORY_INTER) %{
duke@0 3664 base($reg);
duke@0 3665 index(0x4);
duke@0 3666 scale(0x0);
duke@0 3667 disp($off);
duke@0 3668 %}
duke@0 3669 %}
duke@0 3670
duke@0 3671 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3672 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
duke@0 3673 %{
duke@0 3674 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3675 match(AddP (AddP reg lreg) off);
duke@0 3676
duke@0 3677 op_cost(10);
duke@0 3678 format %{"[$reg + $off + $lreg]" %}
duke@0 3679 interface(MEMORY_INTER) %{
duke@0 3680 base($reg);
duke@0 3681 index($lreg);
duke@0 3682 scale(0x0);
duke@0 3683 disp($off);
duke@0 3684 %}
duke@0 3685 %}
duke@0 3686
duke@0 3687 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3688 operand indIndex(any_RegP reg, rRegL lreg)
duke@0 3689 %{
duke@0 3690 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3691 match(AddP reg lreg);
duke@0 3692
duke@0 3693 op_cost(10);
duke@0 3694 format %{"[$reg + $lreg]" %}
duke@0 3695 interface(MEMORY_INTER) %{
duke@0 3696 base($reg);
duke@0 3697 index($lreg);
duke@0 3698 scale(0x0);
duke@0 3699 disp(0x0);
duke@0 3700 %}
duke@0 3701 %}
duke@0 3702
duke@0 3703 // Indirect Memory Times Scale Plus Index Register
duke@0 3704 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
duke@0 3705 %{
duke@0 3706 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3707 match(AddP reg (LShiftL lreg scale));
duke@0 3708
duke@0 3709 op_cost(10);
duke@0 3710 format %{"[$reg + $lreg << $scale]" %}
duke@0 3711 interface(MEMORY_INTER) %{
duke@0 3712 base($reg);
duke@0 3713 index($lreg);
duke@0 3714 scale($scale);
duke@0 3715 disp(0x0);
duke@0 3716 %}
duke@0 3717 %}
duke@0 3718
duke@0 3719 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
duke@0 3720 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
duke@0 3721 %{
duke@0 3722 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3723 match(AddP (AddP reg (LShiftL lreg scale)) off);
duke@0 3724
duke@0 3725 op_cost(10);
duke@0 3726 format %{"[$reg + $off + $lreg << $scale]" %}
duke@0 3727 interface(MEMORY_INTER) %{
duke@0 3728 base($reg);
duke@0 3729 index($lreg);
duke@0 3730 scale($scale);
duke@0 3731 disp($off);
duke@0 3732 %}
duke@0 3733 %}
duke@0 3734
thartmann@8179 3735 // Indirect Memory Plus Positive Index Register Plus Offset Operand
thartmann@8179 3736 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
thartmann@8179 3737 %{
thartmann@8179 3738 constraint(ALLOC_IN_RC(ptr_reg));
thartmann@8179 3739 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
thartmann@8179 3740 match(AddP (AddP reg (ConvI2L idx)) off);
thartmann@8179 3741
thartmann@8179 3742 op_cost(10);
thartmann@8179 3743 format %{"[$reg + $off + $idx]" %}
thartmann@8179 3744 interface(MEMORY_INTER) %{
thartmann@8179 3745 base($reg);
thartmann@8179 3746 index($idx);
thartmann@8179 3747 scale(0x0);
thartmann@8179 3748 disp($off);
thartmann@8179 3749 %}
thartmann@8179 3750 %}
thartmann@8179 3751
duke@0 3752 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
duke@0 3753 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
duke@0 3754 %{
duke@0 3755 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3756 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
duke@0 3757 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
duke@0 3758
duke@0 3759 op_cost(10);
duke@0 3760 format %{"[$reg + $off + $idx << $scale]" %}
duke@0 3761 interface(MEMORY_INTER) %{
duke@0 3762 base($reg);
duke@0 3763 index($idx);
duke@0 3764 scale($scale);
duke@0 3765 disp($off);
duke@0 3766 %}
duke@0 3767 %}
duke@0 3768
kvn@642 3769 // Indirect Narrow Oop Plus Offset Operand
kvn@642 3770 // Note: x86 architecture doesn't support "scale * index + offset" without a base
kvn@642 3771 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
kvn@642 3772 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
kvn@1491 3773 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
kvn@642 3774 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3775 match(AddP (DecodeN reg) off);
kvn@642 3776
kvn@642 3777 op_cost(10);
kvn@642 3778 format %{"[R12 + $reg << 3 + $off] (comp