annotate src/cpu/x86/vm/x86_64.ad @ 1668:3e8fbc61cee8

6978355: renaming for 6961697 Summary: This is the renaming part of 6961697 to keep the actual changes small for review. Reviewed-by: kvn, never
author twisti
date Wed, 25 Aug 2010 05:27:54 -0700
parents f55c4f82ab9d
children 52e82a6bedaf
rev   line source
duke@0 1 //
trims@1472 2 // Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
duke@0 135 // Word a in each register holds a Float, words ab hold a Double. We
duke@0 136 // currently do not use the SIMD capabilities, so registers cd are
duke@0 137 // unused at the moment.
duke@0 138 // XMM8-XMM15 must be encoded with REX.
duke@0 139 // Linux ABI: No register preserved across function calls
duke@0 140 // XMM0-XMM7 might hold parameters
duke@0 141 // Windows ABI: XMM6-XMM15 preserved across function calls
duke@0 142 // XMM0-XMM3 might hold parameters
duke@0 143
duke@0 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
duke@0 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
duke@0 146
duke@0 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
duke@0 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
duke@0 149
duke@0 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
duke@0 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
duke@0 152
duke@0 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
duke@0 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
duke@0 155
duke@0 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
duke@0 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
duke@0 158
duke@0 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
duke@0 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
duke@0 161
duke@0 162 #ifdef _WIN64
duke@0 163
duke@0 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
duke@0 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 166
duke@0 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
duke@0 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 169
duke@0 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
duke@0 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 172
duke@0 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
duke@0 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 175
duke@0 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
duke@0 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 178
duke@0 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
duke@0 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 181
duke@0 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
duke@0 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 184
duke@0 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
duke@0 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 187
duke@0 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
duke@0 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 190
duke@0 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
duke@0 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 193
duke@0 194 #else
duke@0 195
duke@0 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
duke@0 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 198
duke@0 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
duke@0 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 201
duke@0 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
duke@0 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 204
duke@0 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
duke@0 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 207
duke@0 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
duke@0 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 210
duke@0 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
duke@0 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 213
duke@0 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
duke@0 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 216
duke@0 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
duke@0 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 219
duke@0 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
duke@0 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 222
duke@0 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
duke@0 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 225
duke@0 226 #endif // _WIN64
duke@0 227
duke@0 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
duke@0 229
duke@0 230 // Specify priority of register selection within phases of register
duke@0 231 // allocation. Highest priority is first. A useful heuristic is to
duke@0 232 // give registers a low priority when they are required by machine
duke@0 233 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 234 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 235 // which participate in fixed calling sequences should come last.
duke@0 236 // Registers which are used as pairs must fall on an even boundary.
duke@0 237
duke@0 238 alloc_class chunk0(R10, R10_H,
duke@0 239 R11, R11_H,
duke@0 240 R8, R8_H,
duke@0 241 R9, R9_H,
duke@0 242 R12, R12_H,
duke@0 243 RCX, RCX_H,
duke@0 244 RBX, RBX_H,
duke@0 245 RDI, RDI_H,
duke@0 246 RDX, RDX_H,
duke@0 247 RSI, RSI_H,
duke@0 248 RAX, RAX_H,
duke@0 249 RBP, RBP_H,
duke@0 250 R13, R13_H,
duke@0 251 R14, R14_H,
duke@0 252 R15, R15_H,
duke@0 253 RSP, RSP_H);
duke@0 254
duke@0 255 // XXX probably use 8-15 first on Linux
duke@0 256 alloc_class chunk1(XMM0, XMM0_H,
duke@0 257 XMM1, XMM1_H,
duke@0 258 XMM2, XMM2_H,
duke@0 259 XMM3, XMM3_H,
duke@0 260 XMM4, XMM4_H,
duke@0 261 XMM5, XMM5_H,
duke@0 262 XMM6, XMM6_H,
duke@0 263 XMM7, XMM7_H,
duke@0 264 XMM8, XMM8_H,
duke@0 265 XMM9, XMM9_H,
duke@0 266 XMM10, XMM10_H,
duke@0 267 XMM11, XMM11_H,
duke@0 268 XMM12, XMM12_H,
duke@0 269 XMM13, XMM13_H,
duke@0 270 XMM14, XMM14_H,
duke@0 271 XMM15, XMM15_H);
duke@0 272
duke@0 273 alloc_class chunk2(RFLAGS);
duke@0 274
duke@0 275
duke@0 276 //----------Architecture Description Register Classes--------------------------
duke@0 277 // Several register classes are automatically defined based upon information in
duke@0 278 // this architecture description.
duke@0 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 283 //
duke@0 284
duke@0 285 // Class for all pointer registers (including RSP)
duke@0 286 reg_class any_reg(RAX, RAX_H,
duke@0 287 RDX, RDX_H,
duke@0 288 RBP, RBP_H,
duke@0 289 RDI, RDI_H,
duke@0 290 RSI, RSI_H,
duke@0 291 RCX, RCX_H,
duke@0 292 RBX, RBX_H,
duke@0 293 RSP, RSP_H,
duke@0 294 R8, R8_H,
duke@0 295 R9, R9_H,
duke@0 296 R10, R10_H,
duke@0 297 R11, R11_H,
duke@0 298 R12, R12_H,
duke@0 299 R13, R13_H,
duke@0 300 R14, R14_H,
duke@0 301 R15, R15_H);
duke@0 302
duke@0 303 // Class for all pointer registers except RSP
duke@0 304 reg_class ptr_reg(RAX, RAX_H,
duke@0 305 RDX, RDX_H,
duke@0 306 RBP, RBP_H,
duke@0 307 RDI, RDI_H,
duke@0 308 RSI, RSI_H,
duke@0 309 RCX, RCX_H,
duke@0 310 RBX, RBX_H,
duke@0 311 R8, R8_H,
duke@0 312 R9, R9_H,
duke@0 313 R10, R10_H,
duke@0 314 R11, R11_H,
duke@0 315 R13, R13_H,
duke@0 316 R14, R14_H);
duke@0 317
duke@0 318 // Class for all pointer registers except RAX and RSP
duke@0 319 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 320 RBP, RBP_H,
duke@0 321 RDI, RDI_H,
duke@0 322 RSI, RSI_H,
duke@0 323 RCX, RCX_H,
duke@0 324 RBX, RBX_H,
duke@0 325 R8, R8_H,
duke@0 326 R9, R9_H,
duke@0 327 R10, R10_H,
duke@0 328 R11, R11_H,
duke@0 329 R13, R13_H,
duke@0 330 R14, R14_H);
duke@0 331
duke@0 332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 333 RAX, RAX_H,
duke@0 334 RDI, RDI_H,
duke@0 335 RSI, RSI_H,
duke@0 336 RCX, RCX_H,
duke@0 337 RBX, RBX_H,
duke@0 338 R8, R8_H,
duke@0 339 R9, R9_H,
duke@0 340 R10, R10_H,
duke@0 341 R11, R11_H,
duke@0 342 R13, R13_H,
duke@0 343 R14, R14_H);
duke@0 344
duke@0 345 // Class for all pointer registers except RAX, RBX and RSP
duke@0 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 347 RBP, RBP_H,
duke@0 348 RDI, RDI_H,
duke@0 349 RSI, RSI_H,
duke@0 350 RCX, RCX_H,
duke@0 351 R8, R8_H,
duke@0 352 R9, R9_H,
duke@0 353 R10, R10_H,
duke@0 354 R11, R11_H,
duke@0 355 R13, R13_H,
duke@0 356 R14, R14_H);
duke@0 357
duke@0 358 // Singleton class for RAX pointer register
duke@0 359 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 360
duke@0 361 // Singleton class for RBX pointer register
duke@0 362 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 363
duke@0 364 // Singleton class for RSI pointer register
duke@0 365 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 366
duke@0 367 // Singleton class for RDI pointer register
duke@0 368 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 369
duke@0 370 // Singleton class for RBP pointer register
duke@0 371 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 372
duke@0 373 // Singleton class for stack pointer
duke@0 374 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 375
duke@0 376 // Singleton class for TLS pointer
duke@0 377 reg_class ptr_r15_reg(R15, R15_H);
duke@0 378
duke@0 379 // Class for all long registers (except RSP)
duke@0 380 reg_class long_reg(RAX, RAX_H,
duke@0 381 RDX, RDX_H,
duke@0 382 RBP, RBP_H,
duke@0 383 RDI, RDI_H,
duke@0 384 RSI, RSI_H,
duke@0 385 RCX, RCX_H,
duke@0 386 RBX, RBX_H,
duke@0 387 R8, R8_H,
duke@0 388 R9, R9_H,
duke@0 389 R10, R10_H,
duke@0 390 R11, R11_H,
duke@0 391 R13, R13_H,
duke@0 392 R14, R14_H);
duke@0 393
duke@0 394 // Class for all long registers except RAX, RDX (and RSP)
duke@0 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 396 RDI, RDI_H,
duke@0 397 RSI, RSI_H,
duke@0 398 RCX, RCX_H,
duke@0 399 RBX, RBX_H,
duke@0 400 R8, R8_H,
duke@0 401 R9, R9_H,
duke@0 402 R10, R10_H,
duke@0 403 R11, R11_H,
duke@0 404 R13, R13_H,
duke@0 405 R14, R14_H);
duke@0 406
duke@0 407 // Class for all long registers except RCX (and RSP)
duke@0 408 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 409 RDI, RDI_H,
duke@0 410 RSI, RSI_H,
duke@0 411 RAX, RAX_H,
duke@0 412 RDX, RDX_H,
duke@0 413 RBX, RBX_H,
duke@0 414 R8, R8_H,
duke@0 415 R9, R9_H,
duke@0 416 R10, R10_H,
duke@0 417 R11, R11_H,
duke@0 418 R13, R13_H,
duke@0 419 R14, R14_H);
duke@0 420
duke@0 421 // Class for all long registers except RAX (and RSP)
duke@0 422 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 423 RDX, RDX_H,
duke@0 424 RDI, RDI_H,
duke@0 425 RSI, RSI_H,
duke@0 426 RCX, RCX_H,
duke@0 427 RBX, RBX_H,
duke@0 428 R8, R8_H,
duke@0 429 R9, R9_H,
duke@0 430 R10, R10_H,
duke@0 431 R11, R11_H,
duke@0 432 R13, R13_H,
duke@0 433 R14, R14_H);
duke@0 434
duke@0 435 // Singleton class for RAX long register
duke@0 436 reg_class long_rax_reg(RAX, RAX_H);
duke@0 437
duke@0 438 // Singleton class for RCX long register
duke@0 439 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 440
duke@0 441 // Singleton class for RDX long register
duke@0 442 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 443
duke@0 444 // Class for all int registers (except RSP)
duke@0 445 reg_class int_reg(RAX,
duke@0 446 RDX,
duke@0 447 RBP,
duke@0 448 RDI,
duke@0 449 RSI,
duke@0 450 RCX,
duke@0 451 RBX,
duke@0 452 R8,
duke@0 453 R9,
duke@0 454 R10,
duke@0 455 R11,
duke@0 456 R13,
duke@0 457 R14);
duke@0 458
duke@0 459 // Class for all int registers except RCX (and RSP)
duke@0 460 reg_class int_no_rcx_reg(RAX,
duke@0 461 RDX,
duke@0 462 RBP,
duke@0 463 RDI,
duke@0 464 RSI,
duke@0 465 RBX,
duke@0 466 R8,
duke@0 467 R9,
duke@0 468 R10,
duke@0 469 R11,
duke@0 470 R13,
duke@0 471 R14);
duke@0 472
duke@0 473 // Class for all int registers except RAX, RDX (and RSP)
duke@0 474 reg_class int_no_rax_rdx_reg(RBP,
never@304 475 RDI,
duke@0 476 RSI,
duke@0 477 RCX,
duke@0 478 RBX,
duke@0 479 R8,
duke@0 480 R9,
duke@0 481 R10,
duke@0 482 R11,
duke@0 483 R13,
duke@0 484 R14);
duke@0 485
duke@0 486 // Singleton class for RAX int register
duke@0 487 reg_class int_rax_reg(RAX);
duke@0 488
duke@0 489 // Singleton class for RBX int register
duke@0 490 reg_class int_rbx_reg(RBX);
duke@0 491
duke@0 492 // Singleton class for RCX int register
duke@0 493 reg_class int_rcx_reg(RCX);
duke@0 494
duke@0 495 // Singleton class for RCX int register
duke@0 496 reg_class int_rdx_reg(RDX);
duke@0 497
duke@0 498 // Singleton class for RCX int register
duke@0 499 reg_class int_rdi_reg(RDI);
duke@0 500
duke@0 501 // Singleton class for instruction pointer
duke@0 502 // reg_class ip_reg(RIP);
duke@0 503
duke@0 504 // Singleton class for condition codes
duke@0 505 reg_class int_flags(RFLAGS);
duke@0 506
duke@0 507 // Class for all float registers
duke@0 508 reg_class float_reg(XMM0,
duke@0 509 XMM1,
duke@0 510 XMM2,
duke@0 511 XMM3,
duke@0 512 XMM4,
duke@0 513 XMM5,
duke@0 514 XMM6,
duke@0 515 XMM7,
duke@0 516 XMM8,
duke@0 517 XMM9,
duke@0 518 XMM10,
duke@0 519 XMM11,
duke@0 520 XMM12,
duke@0 521 XMM13,
duke@0 522 XMM14,
duke@0 523 XMM15);
duke@0 524
duke@0 525 // Class for all double registers
duke@0 526 reg_class double_reg(XMM0, XMM0_H,
duke@0 527 XMM1, XMM1_H,
duke@0 528 XMM2, XMM2_H,
duke@0 529 XMM3, XMM3_H,
duke@0 530 XMM4, XMM4_H,
duke@0 531 XMM5, XMM5_H,
duke@0 532 XMM6, XMM6_H,
duke@0 533 XMM7, XMM7_H,
duke@0 534 XMM8, XMM8_H,
duke@0 535 XMM9, XMM9_H,
duke@0 536 XMM10, XMM10_H,
duke@0 537 XMM11, XMM11_H,
duke@0 538 XMM12, XMM12_H,
duke@0 539 XMM13, XMM13_H,
duke@0 540 XMM14, XMM14_H,
duke@0 541 XMM15, XMM15_H);
duke@0 542 %}
duke@0 543
duke@0 544
duke@0 545 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 546 // This is a block of C++ code which provides values, functions, and
duke@0 547 // definitions necessary in the rest of the architecture description
duke@0 548 source %{
never@304 549 #define RELOC_IMM64 Assembler::imm_operand
duke@0 550 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 551
duke@0 552 #define __ _masm.
duke@0 553
twisti@1137 554 static int preserve_SP_size() {
twisti@1137 555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
twisti@1137 556 }
twisti@1137 557
duke@0 558 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 559 // from the start of the call to the point where the return address
duke@0 560 // will point.
duke@0 561 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 562 {
twisti@1137 563 int offset = 5; // 5 bytes from start of call to where return address points
twisti@1137 564 if (_method_handle_invoke)
twisti@1137 565 offset += preserve_SP_size();
twisti@1137 566 return offset;
duke@0 567 }
duke@0 568
duke@0 569 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 570 {
duke@0 571 return 15; // 15 bytes from start of call to where return address points
duke@0 572 }
duke@0 573
duke@0 574 // In os_cpu .ad file
duke@0 575 // int MachCallRuntimeNode::ret_addr_offset()
duke@0 576
duke@0 577 // Indicate if the safepoint node needs the polling page as an input.
duke@0 578 // Since amd64 does not have absolute addressing but RIP-relative
duke@0 579 // addressing and the polling page is within 2G, it doesn't.
duke@0 580 bool SafePointNode::needs_polling_address_input()
duke@0 581 {
duke@0 582 return false;
duke@0 583 }
duke@0 584
duke@0 585 //
duke@0 586 // Compute padding required for nodes which need alignment
duke@0 587 //
duke@0 588
duke@0 589 // The address of the call instruction needs to be 4-byte aligned to
duke@0 590 // ensure that it does not span a cache line so that it can be patched.
duke@0 591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 592 {
duke@0 593 current_offset += 1; // skip call opcode byte
duke@0 594 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 595 }
duke@0 596
duke@0 597 // The address of the call instruction needs to be 4-byte aligned to
duke@0 598 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 599 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 600 {
twisti@1137 601 current_offset += preserve_SP_size(); // skip mov rbp, rsp
twisti@1137 602 current_offset += 1; // skip call opcode byte
twisti@1137 603 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 604 }
twisti@1137 605
twisti@1137 606 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 607 // ensure that it does not span a cache line so that it can be patched.
duke@0 608 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 609 {
duke@0 610 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 611 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 612 }
duke@0 613
duke@0 614 #ifndef PRODUCT
duke@0 615 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 616 {
duke@0 617 st->print("INT3");
duke@0 618 }
duke@0 619 #endif
duke@0 620
duke@0 621 // EMIT_RM()
twisti@1668 622 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 623 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 624 cbuf.insts()->emit_int8(c);
duke@0 625 }
duke@0 626
duke@0 627 // EMIT_CC()
twisti@1668 628 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 629 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 630 cbuf.insts()->emit_int8(c);
duke@0 631 }
duke@0 632
duke@0 633 // EMIT_OPCODE()
twisti@1668 634 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 635 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 636 }
duke@0 637
duke@0 638 // EMIT_OPCODE() w/ relocation information
duke@0 639 void emit_opcode(CodeBuffer &cbuf,
duke@0 640 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 641 {
twisti@1668 642 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 643 emit_opcode(cbuf, code);
duke@0 644 }
duke@0 645
duke@0 646 // EMIT_D8()
twisti@1668 647 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 648 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 649 }
duke@0 650
duke@0 651 // EMIT_D16()
twisti@1668 652 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 653 cbuf.insts()->emit_int16(d16);
duke@0 654 }
duke@0 655
duke@0 656 // EMIT_D32()
twisti@1668 657 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 658 cbuf.insts()->emit_int32(d32);
duke@0 659 }
duke@0 660
duke@0 661 // EMIT_D64()
twisti@1668 662 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 663 cbuf.insts()->emit_int64(d64);
duke@0 664 }
duke@0 665
duke@0 666 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 667 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 668 int d32,
duke@0 669 relocInfo::relocType reloc,
duke@0 670 int format)
duke@0 671 {
duke@0 672 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 674 cbuf.insts()->emit_int32(d32);
duke@0 675 }
duke@0 676
duke@0 677 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 678 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 679 #ifdef ASSERT
duke@0 680 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 681 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
jrose@989 682 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 683 }
duke@0 684 #endif
twisti@1668 685 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 686 cbuf.insts()->emit_int32(d32);
duke@0 687 }
duke@0 688
duke@0 689 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 690 address next_ip = cbuf.insts_end() + 4;
duke@0 691 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 692 external_word_Relocation::spec(addr),
duke@0 693 RELOC_DISP32);
duke@0 694 }
duke@0 695
duke@0 696
duke@0 697 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 698 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 699 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 700 cbuf.insts()->emit_int64(d64);
duke@0 701 }
duke@0 702
duke@0 703 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 704 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 705 #ifdef ASSERT
duke@0 706 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 707 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
jrose@989 708 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
jrose@989 709 "cannot embed scavengable oops in code");
duke@0 710 }
duke@0 711 #endif
twisti@1668 712 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 713 cbuf.insts()->emit_int64(d64);
duke@0 714 }
duke@0 715
duke@0 716 // Access stack slot for load or store
duke@0 717 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 718 {
duke@0 719 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 720 if (-0x80 <= disp && disp < 0x80) {
duke@0 721 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 722 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 723 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 724 } else {
duke@0 725 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 726 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 727 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 728 }
duke@0 729 }
duke@0 730
duke@0 731 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 732 void encode_RegMem(CodeBuffer &cbuf,
duke@0 733 int reg,
duke@0 734 int base, int index, int scale, int disp, bool disp_is_oop)
duke@0 735 {
duke@0 736 assert(!disp_is_oop, "cannot have disp");
duke@0 737 int regenc = reg & 7;
duke@0 738 int baseenc = base & 7;
duke@0 739 int indexenc = index & 7;
duke@0 740
duke@0 741 // There is no index & no scale, use form without SIB byte
duke@0 742 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 743 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 744 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 745 emit_rm(cbuf, 0x0, regenc, baseenc); // *
duke@0 746 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 747 // If 8-bit displacement, mode 0x1
duke@0 748 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 749 emit_d8(cbuf, disp);
duke@0 750 } else {
duke@0 751 // If 32-bit displacement
duke@0 752 if (base == -1) { // Special flag for absolute address
duke@0 753 emit_rm(cbuf, 0x0, regenc, 0x5); // *
duke@0 754 if (disp_is_oop) {
duke@0 755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 756 } else {
duke@0 757 emit_d32(cbuf, disp);
duke@0 758 }
duke@0 759 } else {
duke@0 760 // Normal base + offset
duke@0 761 emit_rm(cbuf, 0x2, regenc, baseenc); // *
duke@0 762 if (disp_is_oop) {
duke@0 763 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 764 } else {
duke@0 765 emit_d32(cbuf, disp);
duke@0 766 }
duke@0 767 }
duke@0 768 }
duke@0 769 } else {
duke@0 770 // Else, encode with the SIB byte
duke@0 771 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 772 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 773 // If no displacement
duke@0 774 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 775 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 776 } else {
duke@0 777 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 778 // If 8-bit displacement, mode 0x1
duke@0 779 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 780 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 781 emit_d8(cbuf, disp);
duke@0 782 } else {
duke@0 783 // If 32-bit displacement
duke@0 784 if (base == 0x04 ) {
duke@0 785 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 786 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 787 } else {
duke@0 788 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 789 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 790 }
duke@0 791 if (disp_is_oop) {
duke@0 792 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 793 } else {
duke@0 794 emit_d32(cbuf, disp);
duke@0 795 }
duke@0 796 }
duke@0 797 }
duke@0 798 }
duke@0 799 }
duke@0 800
duke@0 801 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
duke@0 802 {
duke@0 803 if (dstenc != srcenc) {
duke@0 804 if (dstenc < 8) {
duke@0 805 if (srcenc >= 8) {
duke@0 806 emit_opcode(cbuf, Assembler::REX_B);
duke@0 807 srcenc -= 8;
duke@0 808 }
duke@0 809 } else {
duke@0 810 if (srcenc < 8) {
duke@0 811 emit_opcode(cbuf, Assembler::REX_R);
duke@0 812 } else {
duke@0 813 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 814 srcenc -= 8;
duke@0 815 }
duke@0 816 dstenc -= 8;
duke@0 817 }
duke@0 818
duke@0 819 emit_opcode(cbuf, 0x8B);
duke@0 820 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 821 }
duke@0 822 }
duke@0 823
duke@0 824 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
duke@0 825 if( dst_encoding == src_encoding ) {
duke@0 826 // reg-reg copy, use an empty encoding
duke@0 827 } else {
duke@0 828 MacroAssembler _masm(&cbuf);
duke@0 829
duke@0 830 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
duke@0 831 }
duke@0 832 }
duke@0 833
duke@0 834
duke@0 835 //=============================================================================
duke@0 836 #ifndef PRODUCT
duke@0 837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 838 {
duke@0 839 Compile* C = ra_->C;
duke@0 840
duke@0 841 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 843 // Remove wordSize for return adr already pushed
duke@0 844 // and another for the RBP we are going to save
duke@0 845 framesize -= 2*wordSize;
duke@0 846 bool need_nop = true;
duke@0 847
duke@0 848 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 849 // We require that their callers must bang for them. But be
duke@0 850 // careful, because some VM calls (such as call site linkage) can
duke@0 851 // use several kilobytes of stack. But the stack safety zone should
duke@0 852 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 853 if (C->need_stack_bang(framesize)) {
duke@0 854 st->print_cr("# stack bang"); st->print("\t");
duke@0 855 need_nop = false;
duke@0 856 }
duke@0 857 st->print_cr("pushq rbp"); st->print("\t");
duke@0 858
duke@0 859 if (VerifyStackAtCalls) {
duke@0 860 // Majik cookie to verify stack depth
duke@0 861 st->print_cr("pushq 0xffffffffbadb100d"
duke@0 862 "\t# Majik cookie for stack depth check");
duke@0 863 st->print("\t");
duke@0 864 framesize -= wordSize; // Remove 2 for cookie
duke@0 865 need_nop = false;
duke@0 866 }
duke@0 867
duke@0 868 if (framesize) {
duke@0 869 st->print("subq rsp, #%d\t# Create frame", framesize);
duke@0 870 if (framesize < 0x80 && need_nop) {
duke@0 871 st->print("\n\tnop\t# nop for patch_verified_entry");
duke@0 872 }
duke@0 873 }
duke@0 874 }
duke@0 875 #endif
duke@0 876
duke@0 877 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 878 {
duke@0 879 Compile* C = ra_->C;
duke@0 880
duke@0 881 // WARNING: Initial instruction MUST be 5 bytes or longer so that
duke@0 882 // NativeJump::patch_verified_entry will be able to patch out the entry
duke@0 883 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
duke@0 884 // depth is ok at 5 bytes, the frame allocation can be either 3 or
duke@0 885 // 6 bytes. So if we don't do the fldcw or the push then we must
duke@0 886 // use the 6 byte frame allocation even if we have no frame. :-(
duke@0 887 // If method sets FPU control word do it now
duke@0 888
duke@0 889 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 890 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 891 // Remove wordSize for return adr already pushed
duke@0 892 // and another for the RBP we are going to save
duke@0 893 framesize -= 2*wordSize;
duke@0 894 bool need_nop = true;
duke@0 895
duke@0 896 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 897 // We require that their callers must bang for them. But be
duke@0 898 // careful, because some VM calls (such as call site linkage) can
duke@0 899 // use several kilobytes of stack. But the stack safety zone should
duke@0 900 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 901 if (C->need_stack_bang(framesize)) {
duke@0 902 MacroAssembler masm(&cbuf);
duke@0 903 masm.generate_stack_overflow_check(framesize);
duke@0 904 need_nop = false;
duke@0 905 }
duke@0 906
duke@0 907 // We always push rbp so that on return to interpreter rbp will be
duke@0 908 // restored correctly and we can correct the stack.
duke@0 909 emit_opcode(cbuf, 0x50 | RBP_enc);
duke@0 910
duke@0 911 if (VerifyStackAtCalls) {
duke@0 912 // Majik cookie to verify stack depth
duke@0 913 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
duke@0 914 emit_d32(cbuf, 0xbadb100d);
duke@0 915 framesize -= wordSize; // Remove 2 for cookie
duke@0 916 need_nop = false;
duke@0 917 }
duke@0 918
duke@0 919 if (framesize) {
duke@0 920 emit_opcode(cbuf, Assembler::REX_W);
duke@0 921 if (framesize < 0x80) {
duke@0 922 emit_opcode(cbuf, 0x83); // sub SP,#framesize
duke@0 923 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 924 emit_d8(cbuf, framesize);
duke@0 925 if (need_nop) {
duke@0 926 emit_opcode(cbuf, 0x90); // nop
duke@0 927 }
duke@0 928 } else {
duke@0 929 emit_opcode(cbuf, 0x81); // sub SP,#framesize
duke@0 930 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 931 emit_d32(cbuf, framesize);
duke@0 932 }
duke@0 933 }
duke@0 934
twisti@1668 935 C->set_frame_complete(cbuf.insts_size());
duke@0 936
duke@0 937 #ifdef ASSERT
duke@0 938 if (VerifyStackAtCalls) {
duke@0 939 Label L;
duke@0 940 MacroAssembler masm(&cbuf);
never@304 941 masm.push(rax);
never@304 942 masm.mov(rax, rsp);
never@304 943 masm.andptr(rax, StackAlignmentInBytes-1);
never@304 944 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
never@304 945 masm.pop(rax);
duke@0 946 masm.jcc(Assembler::equal, L);
duke@0 947 masm.stop("Stack is not properly aligned!");
duke@0 948 masm.bind(L);
duke@0 949 }
duke@0 950 #endif
duke@0 951 }
duke@0 952
duke@0 953 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 954 {
duke@0 955 return MachNode::size(ra_); // too many variables; just compute it
duke@0 956 // the hard way
duke@0 957 }
duke@0 958
duke@0 959 int MachPrologNode::reloc() const
duke@0 960 {
duke@0 961 return 0; // a large enough number
duke@0 962 }
duke@0 963
duke@0 964 //=============================================================================
duke@0 965 #ifndef PRODUCT
duke@0 966 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 967 {
duke@0 968 Compile* C = ra_->C;
duke@0 969 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 970 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 971 // Remove word for return adr already pushed
duke@0 972 // and RBP
duke@0 973 framesize -= 2*wordSize;
duke@0 974
duke@0 975 if (framesize) {
duke@0 976 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
duke@0 977 st->print("\t");
duke@0 978 }
duke@0 979
duke@0 980 st->print_cr("popq\trbp");
duke@0 981 if (do_polling() && C->is_method_compilation()) {
duke@0 982 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
duke@0 983 "# Safepoint: poll for GC");
duke@0 984 st->print("\t");
duke@0 985 }
duke@0 986 }
duke@0 987 #endif
duke@0 988
duke@0 989 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 990 {
duke@0 991 Compile* C = ra_->C;
duke@0 992 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 993 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 994 // Remove word for return adr already pushed
duke@0 995 // and RBP
duke@0 996 framesize -= 2*wordSize;
duke@0 997
duke@0 998 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 999
duke@0 1000 if (framesize) {
duke@0 1001 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1002 if (framesize < 0x80) {
duke@0 1003 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 1004 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1005 emit_d8(cbuf, framesize);
duke@0 1006 } else {
duke@0 1007 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 1008 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1009 emit_d32(cbuf, framesize);
duke@0 1010 }
duke@0 1011 }
duke@0 1012
duke@0 1013 // popq rbp
duke@0 1014 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 1015
duke@0 1016 if (do_polling() && C->is_method_compilation()) {
duke@0 1017 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
duke@0 1018 // XXX reg_mem doesn't support RIP-relative addressing yet
twisti@1668 1019 cbuf.set_insts_mark();
twisti@1668 1020 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_return_type, 0); // XXX
duke@0 1021 emit_opcode(cbuf, 0x85); // testl
duke@0 1022 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
twisti@1668 1023 // cbuf.insts_mark() is beginning of instruction
duke@0 1024 emit_d32_reloc(cbuf, os::get_polling_page());
duke@0 1025 // relocInfo::poll_return_type,
duke@0 1026 }
duke@0 1027 }
duke@0 1028
duke@0 1029 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 1030 {
duke@0 1031 Compile* C = ra_->C;
duke@0 1032 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1033 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1034 // Remove word for return adr already pushed
duke@0 1035 // and RBP
duke@0 1036 framesize -= 2*wordSize;
duke@0 1037
duke@0 1038 uint size = 0;
duke@0 1039
duke@0 1040 if (do_polling() && C->is_method_compilation()) {
duke@0 1041 size += 6;
duke@0 1042 }
duke@0 1043
duke@0 1044 // count popq rbp
duke@0 1045 size++;
duke@0 1046
duke@0 1047 if (framesize) {
duke@0 1048 if (framesize < 0x80) {
duke@0 1049 size += 4;
duke@0 1050 } else if (framesize) {
duke@0 1051 size += 7;
duke@0 1052 }
duke@0 1053 }
duke@0 1054
duke@0 1055 return size;
duke@0 1056 }
duke@0 1057
duke@0 1058 int MachEpilogNode::reloc() const
duke@0 1059 {
duke@0 1060 return 2; // a large enough number
duke@0 1061 }
duke@0 1062
duke@0 1063 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1064 {
duke@0 1065 return MachNode::pipeline_class();
duke@0 1066 }
duke@0 1067
duke@0 1068 int MachEpilogNode::safepoint_offset() const
duke@0 1069 {
duke@0 1070 return 0;
duke@0 1071 }
duke@0 1072
duke@0 1073 //=============================================================================
duke@0 1074
duke@0 1075 enum RC {
duke@0 1076 rc_bad,
duke@0 1077 rc_int,
duke@0 1078 rc_float,
duke@0 1079 rc_stack
duke@0 1080 };
duke@0 1081
duke@0 1082 static enum RC rc_class(OptoReg::Name reg)
duke@0 1083 {
duke@0 1084 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1085
duke@0 1086 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1087
duke@0 1088 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1089
duke@0 1090 if (r->is_Register()) return rc_int;
duke@0 1091
duke@0 1092 assert(r->is_XMMRegister(), "must be");
duke@0 1093 return rc_float;
duke@0 1094 }
duke@0 1095
duke@0 1096 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1097 PhaseRegAlloc* ra_,
duke@0 1098 bool do_size,
duke@0 1099 outputStream* st) const
duke@0 1100 {
duke@0 1101
duke@0 1102 // Get registers to move
duke@0 1103 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1104 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1105 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1106 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1107
duke@0 1108 enum RC src_second_rc = rc_class(src_second);
duke@0 1109 enum RC src_first_rc = rc_class(src_first);
duke@0 1110 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1111 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1112
duke@0 1113 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1114 "must move at least 1 register" );
duke@0 1115
duke@0 1116 if (src_first == dst_first && src_second == dst_second) {
duke@0 1117 // Self copy, no move
duke@0 1118 return 0;
duke@0 1119 } else if (src_first_rc == rc_stack) {
duke@0 1120 // mem ->
duke@0 1121 if (dst_first_rc == rc_stack) {
duke@0 1122 // mem -> mem
duke@0 1123 assert(src_second != dst_first, "overlap");
duke@0 1124 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1125 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1126 // 64-bit
duke@0 1127 int src_offset = ra_->reg2offset(src_first);
duke@0 1128 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1129 if (cbuf) {
duke@0 1130 emit_opcode(*cbuf, 0xFF);
duke@0 1131 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
duke@0 1132
duke@0 1133 emit_opcode(*cbuf, 0x8F);
duke@0 1134 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
duke@0 1135
duke@0 1136 #ifndef PRODUCT
duke@0 1137 } else if (!do_size) {
duke@0 1138 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
duke@0 1139 "popq [rsp + #%d]",
duke@0 1140 src_offset,
duke@0 1141 dst_offset);
duke@0 1142 #endif
duke@0 1143 }
duke@0 1144 return
duke@0 1145 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
duke@0 1146 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
duke@0 1147 } else {
duke@0 1148 // 32-bit
duke@0 1149 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1150 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1151 // No pushl/popl, so:
duke@0 1152 int src_offset = ra_->reg2offset(src_first);
duke@0 1153 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1154 if (cbuf) {
duke@0 1155 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1156 emit_opcode(*cbuf, 0x89);
duke@0 1157 emit_opcode(*cbuf, 0x44);
duke@0 1158 emit_opcode(*cbuf, 0x24);
duke@0 1159 emit_opcode(*cbuf, 0xF8);
duke@0 1160
duke@0 1161 emit_opcode(*cbuf, 0x8B);
duke@0 1162 encode_RegMem(*cbuf,
duke@0 1163 RAX_enc,
duke@0 1164 RSP_enc, 0x4, 0, src_offset,
duke@0 1165 false);
duke@0 1166
duke@0 1167 emit_opcode(*cbuf, 0x89);
duke@0 1168 encode_RegMem(*cbuf,
duke@0 1169 RAX_enc,
duke@0 1170 RSP_enc, 0x4, 0, dst_offset,
duke@0 1171 false);
duke@0 1172
duke@0 1173 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1174 emit_opcode(*cbuf, 0x8B);
duke@0 1175 emit_opcode(*cbuf, 0x44);
duke@0 1176 emit_opcode(*cbuf, 0x24);
duke@0 1177 emit_opcode(*cbuf, 0xF8);
duke@0 1178
duke@0 1179 #ifndef PRODUCT
duke@0 1180 } else if (!do_size) {
duke@0 1181 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
duke@0 1182 "movl rax, [rsp + #%d]\n\t"
duke@0 1183 "movl [rsp + #%d], rax\n\t"
duke@0 1184 "movq rax, [rsp - #8]",
duke@0 1185 src_offset,
duke@0 1186 dst_offset);
duke@0 1187 #endif
duke@0 1188 }
duke@0 1189 return
duke@0 1190 5 + // movq
duke@0 1191 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1192 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1193 5; // movq
duke@0 1194 }
duke@0 1195 } else if (dst_first_rc == rc_int) {
duke@0 1196 // mem -> gpr
duke@0 1197 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1198 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1199 // 64-bit
duke@0 1200 int offset = ra_->reg2offset(src_first);
duke@0 1201 if (cbuf) {
duke@0 1202 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1203 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1204 } else {
duke@0 1205 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1206 }
duke@0 1207 emit_opcode(*cbuf, 0x8B);
duke@0 1208 encode_RegMem(*cbuf,
duke@0 1209 Matcher::_regEncode[dst_first],
duke@0 1210 RSP_enc, 0x4, 0, offset,
duke@0 1211 false);
duke@0 1212 #ifndef PRODUCT
duke@0 1213 } else if (!do_size) {
duke@0 1214 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1215 Matcher::regName[dst_first],
duke@0 1216 offset);
duke@0 1217 #endif
duke@0 1218 }
duke@0 1219 return
duke@0 1220 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1221 } else {
duke@0 1222 // 32-bit
duke@0 1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1225 int offset = ra_->reg2offset(src_first);
duke@0 1226 if (cbuf) {
duke@0 1227 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1228 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1229 }
duke@0 1230 emit_opcode(*cbuf, 0x8B);
duke@0 1231 encode_RegMem(*cbuf,
duke@0 1232 Matcher::_regEncode[dst_first],
duke@0 1233 RSP_enc, 0x4, 0, offset,
duke@0 1234 false);
duke@0 1235 #ifndef PRODUCT
duke@0 1236 } else if (!do_size) {
duke@0 1237 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1238 Matcher::regName[dst_first],
duke@0 1239 offset);
duke@0 1240 #endif
duke@0 1241 }
duke@0 1242 return
duke@0 1243 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1244 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1245 ? 3
duke@0 1246 : 4); // REX
duke@0 1247 }
duke@0 1248 } else if (dst_first_rc == rc_float) {
duke@0 1249 // mem-> xmm
duke@0 1250 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1252 // 64-bit
duke@0 1253 int offset = ra_->reg2offset(src_first);
duke@0 1254 if (cbuf) {
duke@0 1255 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 1256 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1257 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1258 }
duke@0 1259 emit_opcode(*cbuf, 0x0F);
duke@0 1260 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 1261 encode_RegMem(*cbuf,
duke@0 1262 Matcher::_regEncode[dst_first],
duke@0 1263 RSP_enc, 0x4, 0, offset,
duke@0 1264 false);
duke@0 1265 #ifndef PRODUCT
duke@0 1266 } else if (!do_size) {
duke@0 1267 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1268 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1269 Matcher::regName[dst_first],
duke@0 1270 offset);
duke@0 1271 #endif
duke@0 1272 }
duke@0 1273 return
duke@0 1274 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1275 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1276 ? 5
duke@0 1277 : 6); // REX
duke@0 1278 } else {
duke@0 1279 // 32-bit
duke@0 1280 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1281 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1282 int offset = ra_->reg2offset(src_first);
duke@0 1283 if (cbuf) {
duke@0 1284 emit_opcode(*cbuf, 0xF3);
duke@0 1285 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1286 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1287 }
duke@0 1288 emit_opcode(*cbuf, 0x0F);
duke@0 1289 emit_opcode(*cbuf, 0x10);
duke@0 1290 encode_RegMem(*cbuf,
duke@0 1291 Matcher::_regEncode[dst_first],
duke@0 1292 RSP_enc, 0x4, 0, offset,
duke@0 1293 false);
duke@0 1294 #ifndef PRODUCT
duke@0 1295 } else if (!do_size) {
duke@0 1296 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1297 Matcher::regName[dst_first],
duke@0 1298 offset);
duke@0 1299 #endif
duke@0 1300 }
duke@0 1301 return
duke@0 1302 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1303 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1304 ? 5
duke@0 1305 : 6); // REX
duke@0 1306 }
duke@0 1307 }
duke@0 1308 } else if (src_first_rc == rc_int) {
duke@0 1309 // gpr ->
duke@0 1310 if (dst_first_rc == rc_stack) {
duke@0 1311 // gpr -> mem
duke@0 1312 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1313 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1314 // 64-bit
duke@0 1315 int offset = ra_->reg2offset(dst_first);
duke@0 1316 if (cbuf) {
duke@0 1317 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1318 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1319 } else {
duke@0 1320 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1321 }
duke@0 1322 emit_opcode(*cbuf, 0x89);
duke@0 1323 encode_RegMem(*cbuf,
duke@0 1324 Matcher::_regEncode[src_first],
duke@0 1325 RSP_enc, 0x4, 0, offset,
duke@0 1326 false);
duke@0 1327 #ifndef PRODUCT
duke@0 1328 } else if (!do_size) {
duke@0 1329 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1330 offset,
duke@0 1331 Matcher::regName[src_first]);
duke@0 1332 #endif
duke@0 1333 }
duke@0 1334 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1335 } else {
duke@0 1336 // 32-bit
duke@0 1337 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1338 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1339 int offset = ra_->reg2offset(dst_first);
duke@0 1340 if (cbuf) {
duke@0 1341 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1342 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1343 }
duke@0 1344 emit_opcode(*cbuf, 0x89);
duke@0 1345 encode_RegMem(*cbuf,
duke@0 1346 Matcher::_regEncode[src_first],
duke@0 1347 RSP_enc, 0x4, 0, offset,
duke@0 1348 false);
duke@0 1349 #ifndef PRODUCT
duke@0 1350 } else if (!do_size) {
duke@0 1351 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1352 offset,
duke@0 1353 Matcher::regName[src_first]);
duke@0 1354 #endif
duke@0 1355 }
duke@0 1356 return
duke@0 1357 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1358 ((Matcher::_regEncode[src_first] < 8)
duke@0 1359 ? 3
duke@0 1360 : 4); // REX
duke@0 1361 }
duke@0 1362 } else if (dst_first_rc == rc_int) {
duke@0 1363 // gpr -> gpr
duke@0 1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1366 // 64-bit
duke@0 1367 if (cbuf) {
duke@0 1368 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1369 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1370 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1371 } else {
duke@0 1372 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1373 }
duke@0 1374 } else {
duke@0 1375 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1376 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1377 } else {
duke@0 1378 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1379 }
duke@0 1380 }
duke@0 1381 emit_opcode(*cbuf, 0x8B);
duke@0 1382 emit_rm(*cbuf, 0x3,
duke@0 1383 Matcher::_regEncode[dst_first] & 7,
duke@0 1384 Matcher::_regEncode[src_first] & 7);
duke@0 1385 #ifndef PRODUCT
duke@0 1386 } else if (!do_size) {
duke@0 1387 st->print("movq %s, %s\t# spill",
duke@0 1388 Matcher::regName[dst_first],
duke@0 1389 Matcher::regName[src_first]);
duke@0 1390 #endif
duke@0 1391 }
duke@0 1392 return 3; // REX
duke@0 1393 } else {
duke@0 1394 // 32-bit
duke@0 1395 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1396 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1397 if (cbuf) {
duke@0 1398 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1399 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1400 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1401 }
duke@0 1402 } else {
duke@0 1403 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1404 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1405 } else {
duke@0 1406 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1407 }
duke@0 1408 }
duke@0 1409 emit_opcode(*cbuf, 0x8B);
duke@0 1410 emit_rm(*cbuf, 0x3,
duke@0 1411 Matcher::_regEncode[dst_first] & 7,
duke@0 1412 Matcher::_regEncode[src_first] & 7);
duke@0 1413 #ifndef PRODUCT
duke@0 1414 } else if (!do_size) {
duke@0 1415 st->print("movl %s, %s\t# spill",
duke@0 1416 Matcher::regName[dst_first],
duke@0 1417 Matcher::regName[src_first]);
duke@0 1418 #endif
duke@0 1419 }
duke@0 1420 return
duke@0 1421 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1422 ? 2
duke@0 1423 : 3; // REX
duke@0 1424 }
duke@0 1425 } else if (dst_first_rc == rc_float) {
duke@0 1426 // gpr -> xmm
duke@0 1427 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1428 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1429 // 64-bit
duke@0 1430 if (cbuf) {
duke@0 1431 emit_opcode(*cbuf, 0x66);
duke@0 1432 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1433 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1434 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1435 } else {
duke@0 1436 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1437 }
duke@0 1438 } else {
duke@0 1439 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1440 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1441 } else {
duke@0 1442 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1443 }
duke@0 1444 }
duke@0 1445 emit_opcode(*cbuf, 0x0F);
duke@0 1446 emit_opcode(*cbuf, 0x6E);
duke@0 1447 emit_rm(*cbuf, 0x3,
duke@0 1448 Matcher::_regEncode[dst_first] & 7,
duke@0 1449 Matcher::_regEncode[src_first] & 7);
duke@0 1450 #ifndef PRODUCT
duke@0 1451 } else if (!do_size) {
duke@0 1452 st->print("movdq %s, %s\t# spill",
duke@0 1453 Matcher::regName[dst_first],
duke@0 1454 Matcher::regName[src_first]);
duke@0 1455 #endif
duke@0 1456 }
duke@0 1457 return 5; // REX
duke@0 1458 } else {
duke@0 1459 // 32-bit
duke@0 1460 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1461 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1462 if (cbuf) {
duke@0 1463 emit_opcode(*cbuf, 0x66);
duke@0 1464 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1465 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1466 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1467 }
duke@0 1468 } else {
duke@0 1469 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1470 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1471 } else {
duke@0 1472 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1473 }
duke@0 1474 }
duke@0 1475 emit_opcode(*cbuf, 0x0F);
duke@0 1476 emit_opcode(*cbuf, 0x6E);
duke@0 1477 emit_rm(*cbuf, 0x3,
duke@0 1478 Matcher::_regEncode[dst_first] & 7,
duke@0 1479 Matcher::_regEncode[src_first] & 7);
duke@0 1480 #ifndef PRODUCT
duke@0 1481 } else if (!do_size) {
duke@0 1482 st->print("movdl %s, %s\t# spill",
duke@0 1483 Matcher::regName[dst_first],
duke@0 1484 Matcher::regName[src_first]);
duke@0 1485 #endif
duke@0 1486 }
duke@0 1487 return
duke@0 1488 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1489 ? 4
duke@0 1490 : 5; // REX
duke@0 1491 }
duke@0 1492 }
duke@0 1493 } else if (src_first_rc == rc_float) {
duke@0 1494 // xmm ->
duke@0 1495 if (dst_first_rc == rc_stack) {
duke@0 1496 // xmm -> mem
duke@0 1497 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1498 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1499 // 64-bit
duke@0 1500 int offset = ra_->reg2offset(dst_first);
duke@0 1501 if (cbuf) {
duke@0 1502 emit_opcode(*cbuf, 0xF2);
duke@0 1503 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1504 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1505 }
duke@0 1506 emit_opcode(*cbuf, 0x0F);
duke@0 1507 emit_opcode(*cbuf, 0x11);
duke@0 1508 encode_RegMem(*cbuf,
duke@0 1509 Matcher::_regEncode[src_first],
duke@0 1510 RSP_enc, 0x4, 0, offset,
duke@0 1511 false);
duke@0 1512 #ifndef PRODUCT
duke@0 1513 } else if (!do_size) {
duke@0 1514 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1515 offset,
duke@0 1516 Matcher::regName[src_first]);
duke@0 1517 #endif
duke@0 1518 }
duke@0 1519 return
duke@0 1520 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1521 ((Matcher::_regEncode[src_first] < 8)
duke@0 1522 ? 5
duke@0 1523 : 6); // REX
duke@0 1524 } else {
duke@0 1525 // 32-bit
duke@0 1526 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1527 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1528 int offset = ra_->reg2offset(dst_first);
duke@0 1529 if (cbuf) {
duke@0 1530 emit_opcode(*cbuf, 0xF3);
duke@0 1531 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1532 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1533 }
duke@0 1534 emit_opcode(*cbuf, 0x0F);
duke@0 1535 emit_opcode(*cbuf, 0x11);
duke@0 1536 encode_RegMem(*cbuf,
duke@0 1537 Matcher::_regEncode[src_first],
duke@0 1538 RSP_enc, 0x4, 0, offset,
duke@0 1539 false);
duke@0 1540 #ifndef PRODUCT
duke@0 1541 } else if (!do_size) {
duke@0 1542 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1543 offset,
duke@0 1544 Matcher::regName[src_first]);
duke@0 1545 #endif
duke@0 1546 }
duke@0 1547 return
duke@0 1548 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1549 ((Matcher::_regEncode[src_first] < 8)
duke@0 1550 ? 5
duke@0 1551 : 6); // REX
duke@0 1552 }
duke@0 1553 } else if (dst_first_rc == rc_int) {
duke@0 1554 // xmm -> gpr
duke@0 1555 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1556 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1557 // 64-bit
duke@0 1558 if (cbuf) {
duke@0 1559 emit_opcode(*cbuf, 0x66);
duke@0 1560 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1561 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1562 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1563 } else {
duke@0 1564 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
duke@0 1565 }
duke@0 1566 } else {
duke@0 1567 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1568 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
duke@0 1569 } else {
duke@0 1570 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1571 }
duke@0 1572 }
duke@0 1573 emit_opcode(*cbuf, 0x0F);
duke@0 1574 emit_opcode(*cbuf, 0x7E);
duke@0 1575 emit_rm(*cbuf, 0x3,
never@1650 1576 Matcher::_regEncode[src_first] & 7,
never@1650 1577 Matcher::_regEncode[dst_first] & 7);
duke@0 1578 #ifndef PRODUCT
duke@0 1579 } else if (!do_size) {
duke@0 1580 st->print("movdq %s, %s\t# spill",
duke@0 1581 Matcher::regName[dst_first],
duke@0 1582 Matcher::regName[src_first]);
duke@0 1583 #endif
duke@0 1584 }
duke@0 1585 return 5; // REX
duke@0 1586 } else {
duke@0 1587 // 32-bit
duke@0 1588 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1589 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1590 if (cbuf) {
duke@0 1591 emit_opcode(*cbuf, 0x66);
duke@0 1592 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1593 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1594 emit_opcode(*cbuf, Assembler::REX_R); // attention!
duke@0 1595 }
duke@0 1596 } else {
duke@0 1597 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1598 emit_opcode(*cbuf, Assembler::REX_B); // attention!
duke@0 1599 } else {
duke@0 1600 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1601 }
duke@0 1602 }
duke@0 1603 emit_opcode(*cbuf, 0x0F);
duke@0 1604 emit_opcode(*cbuf, 0x7E);
duke@0 1605 emit_rm(*cbuf, 0x3,
never@1650 1606 Matcher::_regEncode[src_first] & 7,
never@1650 1607 Matcher::_regEncode[dst_first] & 7);
duke@0 1608 #ifndef PRODUCT
duke@0 1609 } else if (!do_size) {
duke@0 1610 st->print("movdl %s, %s\t# spill",
duke@0 1611 Matcher::regName[dst_first],
duke@0 1612 Matcher::regName[src_first]);
duke@0 1613 #endif
duke@0 1614 }
duke@0 1615 return
duke@0 1616 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1617 ? 4
duke@0 1618 : 5; // REX
duke@0 1619 }
duke@0 1620 } else if (dst_first_rc == rc_float) {
duke@0 1621 // xmm -> xmm
duke@0 1622 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1623 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1624 // 64-bit
duke@0 1625 if (cbuf) {
duke@0 1626 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 1627 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1628 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1629 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1630 }
duke@0 1631 } else {
duke@0 1632 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1633 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1634 } else {
duke@0 1635 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1636 }
duke@0 1637 }
duke@0 1638 emit_opcode(*cbuf, 0x0F);
duke@0 1639 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1640 emit_rm(*cbuf, 0x3,
duke@0 1641 Matcher::_regEncode[dst_first] & 7,
duke@0 1642 Matcher::_regEncode[src_first] & 7);
duke@0 1643 #ifndef PRODUCT
duke@0 1644 } else if (!do_size) {
duke@0 1645 st->print("%s %s, %s\t# spill",
duke@0 1646 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1647 Matcher::regName[dst_first],
duke@0 1648 Matcher::regName[src_first]);
duke@0 1649 #endif
duke@0 1650 }
duke@0 1651 return
duke@0 1652 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1653 ? 4
duke@0 1654 : 5; // REX
duke@0 1655 } else {
duke@0 1656 // 32-bit
duke@0 1657 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1658 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1659 if (cbuf) {
duke@0 1660 if (!UseXmmRegToRegMoveAll)
duke@0 1661 emit_opcode(*cbuf, 0xF3);
duke@0 1662 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1663 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1664 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1665 }
duke@0 1666 } else {
duke@0 1667 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1668 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1669 } else {
duke@0 1670 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1671 }
duke@0 1672 }
duke@0 1673 emit_opcode(*cbuf, 0x0F);
duke@0 1674 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1675 emit_rm(*cbuf, 0x3,
duke@0 1676 Matcher::_regEncode[dst_first] & 7,
duke@0 1677 Matcher::_regEncode[src_first] & 7);
duke@0 1678 #ifndef PRODUCT
duke@0 1679 } else if (!do_size) {
duke@0 1680 st->print("%s %s, %s\t# spill",
duke@0 1681 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1682 Matcher::regName[dst_first],
duke@0 1683 Matcher::regName[src_first]);
duke@0 1684 #endif
duke@0 1685 }
duke@0 1686 return
duke@0 1687 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1688 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 1689 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
duke@0 1690 }
duke@0 1691 }
duke@0 1692 }
duke@0 1693
duke@0 1694 assert(0," foo ");
duke@0 1695 Unimplemented();
duke@0 1696
duke@0 1697 return 0;
duke@0 1698 }
duke@0 1699
duke@0 1700 #ifndef PRODUCT
duke@0 1701 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
duke@0 1702 {
duke@0 1703 implementation(NULL, ra_, false, st);
duke@0 1704 }
duke@0 1705 #endif
duke@0 1706
duke@0 1707 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 1708 {
duke@0 1709 implementation(&cbuf, ra_, false, NULL);
duke@0 1710 }
duke@0 1711
duke@0 1712 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
duke@0 1713 {
duke@0 1714 return implementation(NULL, ra_, true, NULL);
duke@0 1715 }
duke@0 1716
duke@0 1717 //=============================================================================
duke@0 1718 #ifndef PRODUCT
duke@0 1719 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 1720 {
duke@0 1721 st->print("nop \t# %d bytes pad for loops and calls", _count);
duke@0 1722 }
duke@0 1723 #endif
duke@0 1724
duke@0 1725 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
duke@0 1726 {
duke@0 1727 MacroAssembler _masm(&cbuf);
duke@0 1728 __ nop(_count);
duke@0 1729 }
duke@0 1730
duke@0 1731 uint MachNopNode::size(PhaseRegAlloc*) const
duke@0 1732 {
duke@0 1733 return _count;
duke@0 1734 }
duke@0 1735
duke@0 1736
duke@0 1737 //=============================================================================
duke@0 1738 #ifndef PRODUCT
duke@0 1739 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1740 {
duke@0 1741 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1742 int reg = ra_->get_reg_first(this);
duke@0 1743 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1744 Matcher::regName[reg], offset);
duke@0 1745 }
duke@0 1746 #endif
duke@0 1747
duke@0 1748 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1749 {
duke@0 1750 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1751 int reg = ra_->get_encode(this);
duke@0 1752 if (offset >= 0x80) {
duke@0 1753 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1754 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1755 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1756 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1757 emit_d32(cbuf, offset);
duke@0 1758 } else {
duke@0 1759 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1760 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1761 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1762 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1763 emit_d8(cbuf, offset);
duke@0 1764 }
duke@0 1765 }
duke@0 1766
duke@0 1767 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1768 {
duke@0 1769 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1770 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1771 }
duke@0 1772
duke@0 1773 //=============================================================================
duke@0 1774
duke@0 1775 // emit call stub, compiled java to interpreter
duke@0 1776 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1777 {
duke@0 1778 // Stub is fixed up when the corresponding call is converted from
duke@0 1779 // calling compiled code to calling interpreted code.
duke@0 1780 // movq rbx, 0
duke@0 1781 // jmp -5 # to self
duke@0 1782
twisti@1668 1783 address mark = cbuf.insts_mark(); // get mark within main instrs section
twisti@1668 1784
twisti@1668 1785 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1786 // That's why we must use the macroassembler to generate a stub.
duke@0 1787 MacroAssembler _masm(&cbuf);
duke@0 1788
duke@0 1789 address base =
duke@0 1790 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1791 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1792 // static stub relocation stores the instruction address of the call
duke@0 1793 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
duke@0 1794 // static stub relocation also tags the methodOop in the code-stream.
duke@0 1795 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
never@304 1796 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1797 __ jump(RuntimeAddress(__ pc()));
duke@0 1798
twisti@1668 1799 // Update current stubs pointer and restore insts_end.
duke@0 1800 __ end_a_stub();
duke@0 1801 }
duke@0 1802
duke@0 1803 // size of call stub, compiled java to interpretor
duke@0 1804 uint size_java_to_interp()
duke@0 1805 {
duke@0 1806 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1807 }
duke@0 1808
duke@0 1809 // relocation entries for call stub, compiled java to interpretor
duke@0 1810 uint reloc_java_to_interp()
duke@0 1811 {
duke@0 1812 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1813 }
duke@0 1814
duke@0 1815 //=============================================================================
duke@0 1816 #ifndef PRODUCT
duke@0 1817 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1818 {
coleenp@113 1819 if (UseCompressedOops) {
kvn@1491 1820 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
kvn@642 1821 if (Universe::narrow_oop_shift() != 0) {
kvn@1491 1822 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
kvn@1491 1823 }
kvn@1491 1824 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1825 } else {
kvn@1491 1826 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1827 "# Inline cache check");
coleenp@113 1828 }
duke@0 1829 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1830 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1831 }
duke@0 1832 #endif
duke@0 1833
duke@0 1834 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1835 {
duke@0 1836 MacroAssembler masm(&cbuf);
twisti@1668 1837 uint insts_size = cbuf.insts_size();
coleenp@113 1838 if (UseCompressedOops) {
coleenp@113 1839 masm.load_klass(rscratch1, j_rarg0);
never@304 1840 masm.cmpptr(rax, rscratch1);
coleenp@113 1841 } else {
never@304 1842 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1843 }
duke@0 1844
duke@0 1845 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1846
duke@0 1847 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1848 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1849 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1850 if (OptoBreakpoint) {
duke@0 1851 // Leave space for int3
kvn@1491 1852 nops_cnt -= 1;
duke@0 1853 }
kvn@1491 1854 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1855 if (nops_cnt > 0)
kvn@1491 1856 masm.nop(nops_cnt);
duke@0 1857 }
duke@0 1858
duke@0 1859 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1860 {
kvn@1491 1861 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1862 // the hard way
duke@0 1863 }
duke@0 1864
duke@0 1865
duke@0 1866 //=============================================================================
duke@0 1867 uint size_exception_handler()
duke@0 1868 {
duke@0 1869 // NativeCall instruction size is the same as NativeJump.
duke@0 1870 // Note that this value is also credited (in output.cpp) to
duke@0 1871 // the size of the code section.
duke@0 1872 return NativeJump::instruction_size;
duke@0 1873 }
duke@0 1874
duke@0 1875 // Emit exception handler code.
duke@0 1876 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1877 {
duke@0 1878
twisti@1668 1879 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1880 // That's why we must use the macroassembler to generate a handler.
duke@0 1881 MacroAssembler _masm(&cbuf);
duke@0 1882 address base =
duke@0 1883 __ start_a_stub(size_exception_handler());
duke@0 1884 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1885 int offset = __ offset();
twisti@1668 1886 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
duke@0 1887 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1888 __ end_a_stub();
duke@0 1889 return offset;
duke@0 1890 }
duke@0 1891
duke@0 1892 uint size_deopt_handler()
duke@0 1893 {
duke@0 1894 // three 5 byte instructions
duke@0 1895 return 15;
duke@0 1896 }
duke@0 1897
duke@0 1898 // Emit deopt handler code.
duke@0 1899 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1900 {
duke@0 1901
twisti@1668 1902 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1903 // That's why we must use the macroassembler to generate a handler.
duke@0 1904 MacroAssembler _masm(&cbuf);
duke@0 1905 address base =
duke@0 1906 __ start_a_stub(size_deopt_handler());
duke@0 1907 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1908 int offset = __ offset();
duke@0 1909 address the_pc = (address) __ pc();
duke@0 1910 Label next;
duke@0 1911 // push a "the_pc" on the stack without destroying any registers
duke@0 1912 // as they all may be live.
duke@0 1913
duke@0 1914 // push address of "next"
duke@0 1915 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1916 __ bind(next);
duke@0 1917 // adjust it so it matches "the_pc"
never@304 1918 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1919 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1920 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1921 __ end_a_stub();
duke@0 1922 return offset;
duke@0 1923 }
duke@0 1924
duke@0 1925 static void emit_double_constant(CodeBuffer& cbuf, double x) {
duke@0 1926 int mark = cbuf.insts()->mark_off();
duke@0 1927 MacroAssembler _masm(&cbuf);
duke@0 1928 address double_address = __ double_constant(x);
duke@0 1929 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
duke@0 1930 emit_d32_reloc(cbuf,
twisti@1668 1931 (int) (double_address - cbuf.insts_end() - 4),
duke@0 1932 internal_word_Relocation::spec(double_address),
duke@0 1933 RELOC_DISP32);
duke@0 1934 }
duke@0 1935
duke@0 1936 static void emit_float_constant(CodeBuffer& cbuf, float x) {
duke@0 1937 int mark = cbuf.insts()->mark_off();
duke@0 1938 MacroAssembler _masm(&cbuf);
duke@0 1939 address float_address = __ float_constant(x);
duke@0 1940 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
duke@0 1941 emit_d32_reloc(cbuf,
twisti@1668 1942 (int) (float_address - cbuf.insts_end() - 4),
duke@0 1943 internal_word_Relocation::spec(float_address),
duke@0 1944 RELOC_DISP32);
duke@0 1945 }
duke@0 1946
duke@0 1947
twisti@775 1948 const bool Matcher::match_rule_supported(int opcode) {
twisti@775 1949 if (!has_match_rule(opcode))
twisti@775 1950 return false;
twisti@775 1951
twisti@775 1952 return true; // Per default match rules are supported.
twisti@775 1953 }
twisti@775 1954
duke@0 1955 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1956 {
duke@0 1957 return regnum - 32; // The FP registers are in the second chunk
duke@0 1958 }
duke@0 1959
duke@0 1960 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1961 const bool Matcher::convL2FSupported(void) {
duke@0 1962 return true;
duke@0 1963 }
duke@0 1964
duke@0 1965 // Vector width in bytes
duke@0 1966 const uint Matcher::vector_width_in_bytes(void) {
duke@0 1967 return 8;
duke@0 1968 }
duke@0 1969
duke@0 1970 // Vector ideal reg
duke@0 1971 const uint Matcher::vector_ideal_reg(void) {
duke@0 1972 return Op_RegD;
duke@0 1973 }
duke@0 1974
duke@0 1975 // Is this branch offset short enough that a short branch can be used?
duke@0 1976 //
duke@0 1977 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1978 // this method should return false for offset 0.
never@415 1979 bool Matcher::is_short_branch_offset(int rule, int offset) {
never@415 1980 // the short version of jmpConUCF2 contains multiple branches,
never@415 1981 // making the reach slightly less
never@415 1982 if (rule == jmpConUCF2_rule)
never@415 1983 return (-126 <= offset && offset <= 125);
never@415 1984 return (-128 <= offset && offset <= 127);
duke@0 1985 }
duke@0 1986
duke@0 1987 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1988 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1989 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1990
duke@0 1991 // Probably always true, even if a temp register is required.
duke@0 1992 return true;
duke@0 1993 }
duke@0 1994
duke@0 1995 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1996 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1997
duke@0 1998 // Threshold size for cleararray.
duke@0 1999 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 2000
duke@0 2001 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 2002 // to be subsumed into complex addressing expressions or compute them
duke@0 2003 // into registers? True for Intel but false for most RISCs
duke@0 2004 const bool Matcher::clone_shift_expressions = true;
duke@0 2005
kvn@1495 2006 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 2007 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 2008 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 2009 }
kvn@1495 2010
duke@0 2011 // Is it better to copy float constants, or load them directly from
duke@0 2012 // memory? Intel can load a float constant from a direct address,
duke@0 2013 // requiring no extra registers. Most RISCs will have to materialize
duke@0 2014 // an address into a register first, so they would do better to copy
duke@0 2015 // the constant from stack.
duke@0 2016 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 2017
duke@0 2018 // If CPU can load and store mis-aligned doubles directly then no
duke@0 2019 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 2020 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 2021 // C code as the Java calling convention forces doubles to be aligned.
duke@0 2022 const bool Matcher::misaligned_doubles_ok = true;
duke@0 2023
duke@0 2024 // No-op on amd64
duke@0 2025 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 2026
duke@0 2027 // Advertise here if the CPU requires explicit rounding operations to
duke@0 2028 // implement the UseStrictFP mode.
duke@0 2029 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 2030
kvn@1274 2031 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 2032 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 2033 bool Matcher::float_in_double() { return false; }
kvn@1274 2034
duke@0 2035 // Do ints take an entire long register or just half?
duke@0 2036 const bool Matcher::int_in_long = true;
duke@0 2037
duke@0 2038 // Return whether or not this register is ever used as an argument.
duke@0 2039 // This function is used on startup to build the trampoline stubs in
duke@0 2040 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 2041 // call in the trampoline, and arguments in those registers not be
duke@0 2042 // available to the callee.
duke@0 2043 bool Matcher::can_be_java_arg(int reg)
duke@0 2044 {
duke@0 2045 return
duke@0 2046 reg == RDI_num || reg == RDI_H_num ||
duke@0 2047 reg == RSI_num || reg == RSI_H_num ||
duke@0 2048 reg == RDX_num || reg == RDX_H_num ||
duke@0 2049 reg == RCX_num || reg == RCX_H_num ||
duke@0 2050 reg == R8_num || reg == R8_H_num ||
duke@0 2051 reg == R9_num || reg == R9_H_num ||
coleenp@113 2052 reg == R12_num || reg == R12_H_num ||
duke@0 2053 reg == XMM0_num || reg == XMM0_H_num ||
duke@0 2054 reg == XMM1_num || reg == XMM1_H_num ||
duke@0 2055 reg == XMM2_num || reg == XMM2_H_num ||
duke@0 2056 reg == XMM3_num || reg == XMM3_H_num ||
duke@0 2057 reg == XMM4_num || reg == XMM4_H_num ||
duke@0 2058 reg == XMM5_num || reg == XMM5_H_num ||
duke@0 2059 reg == XMM6_num || reg == XMM6_H_num ||
duke@0 2060 reg == XMM7_num || reg == XMM7_H_num;
duke@0 2061 }
duke@0 2062
duke@0 2063 bool Matcher::is_spillable_arg(int reg)
duke@0 2064 {
duke@0 2065 return can_be_java_arg(reg);
duke@0 2066 }
duke@0 2067
duke@0 2068 // Register for DIVI projection of divmodI
duke@0 2069 RegMask Matcher::divI_proj_mask() {
duke@0 2070 return INT_RAX_REG_mask;
duke@0 2071 }
duke@0 2072
duke@0 2073 // Register for MODI projection of divmodI
duke@0 2074 RegMask Matcher::modI_proj_mask() {
duke@0 2075 return INT_RDX_REG_mask;
duke@0 2076 }
duke@0 2077
duke@0 2078 // Register for DIVL projection of divmodL
duke@0 2079 RegMask Matcher::divL_proj_mask() {
duke@0 2080 return LONG_RAX_REG_mask;
duke@0 2081 }
duke@0 2082
duke@0 2083 // Register for MODL projection of divmodL
duke@0 2084 RegMask Matcher::modL_proj_mask() {
duke@0 2085 return LONG_RDX_REG_mask;
duke@0 2086 }
duke@0 2087
twisti@1137 2088 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
twisti@1137 2089 return PTR_RBP_REG_mask;
twisti@1137 2090 }
twisti@1137 2091
coleenp@113 2092 static Address build_address(int b, int i, int s, int d) {
coleenp@113 2093 Register index = as_Register(i);
coleenp@113 2094 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 2095 if (index == rsp) {
coleenp@113 2096 index = noreg;
coleenp@113 2097 scale = Address::no_scale;
coleenp@113 2098 }
coleenp@113 2099 Address addr(as_Register(b), index, scale, d);
coleenp@113 2100 return addr;
coleenp@113 2101 }
coleenp@113 2102
duke@0 2103 %}
duke@0 2104
duke@0 2105 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 2106 // This block specifies the encoding classes used by the compiler to
duke@0 2107 // output byte streams. Encoding classes are parameterized macros
duke@0 2108 // used by Machine Instruction Nodes in order to generate the bit
duke@0 2109 // encoding of the instruction. Operands specify their base encoding
duke@0 2110 // interface with the interface keyword. There are currently
duke@0 2111 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 2112 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 2113 // which returns its register number when queried. CONST_INTER causes
duke@0 2114 // an operand to generate a function which returns the value of the
duke@0 2115 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 2116 // four functions which return the Base Register, the Index Register,
duke@0 2117 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 2118 // COND_INTER causes an operand to generate six functions which return
duke@0 2119 // the encoding code (ie - encoding bits for the instruction)
duke@0 2120 // associated with each basic boolean condition for a conditional
duke@0 2121 // instruction.
duke@0 2122 //
duke@0 2123 // Instructions specify two basic values for encoding. Again, a
duke@0 2124 // function is available to check if the constant displacement is an
duke@0 2125 // oop. They use the ins_encode keyword to specify their encoding
duke@0 2126 // classes (which must be a sequence of enc_class names, and their
duke@0 2127 // parameters, specified in the encoding block), and they use the
duke@0 2128 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 2129 // tertiary opcode. Only the opcode sections which a particular
duke@0 2130 // instruction needs for encoding need to be specified.
duke@0 2131 encode %{
duke@0 2132 // Build emit functions for each basic byte or larger field in the
duke@0 2133 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 2134 // from C++ code in the enc_class source block. Emit functions will
duke@0 2135 // live in the main source block for now. In future, we can
duke@0 2136 // generalize this by adding a syntax that specifies the sizes of
duke@0 2137 // fields in an order, so that the adlc can build the emit functions
duke@0 2138 // automagically
duke@0 2139
duke@0 2140 // Emit primary opcode
duke@0 2141 enc_class OpcP
duke@0 2142 %{
duke@0 2143 emit_opcode(cbuf, $primary);
duke@0 2144 %}
duke@0 2145
duke@0 2146 // Emit secondary opcode
duke@0 2147 enc_class OpcS
duke@0 2148 %{
duke@0 2149 emit_opcode(cbuf, $secondary);
duke@0 2150 %}
duke@0 2151
duke@0 2152 // Emit tertiary opcode
duke@0 2153 enc_class OpcT
duke@0 2154 %{
duke@0 2155 emit_opcode(cbuf, $tertiary);
duke@0 2156 %}
duke@0 2157
duke@0 2158 // Emit opcode directly
duke@0 2159 enc_class Opcode(immI d8)
duke@0 2160 %{
duke@0 2161 emit_opcode(cbuf, $d8$$constant);
duke@0 2162 %}
duke@0 2163
duke@0 2164 // Emit size prefix
duke@0 2165 enc_class SizePrefix
duke@0 2166 %{
duke@0 2167 emit_opcode(cbuf, 0x66);
duke@0 2168 %}
duke@0 2169
duke@0 2170 enc_class reg(rRegI reg)
duke@0 2171 %{
duke@0 2172 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 2173 %}
duke@0 2174
duke@0 2175 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 2176 %{
duke@0 2177 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2178 %}
duke@0 2179
duke@0 2180 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 2181 %{
duke@0 2182 emit_opcode(cbuf, $opcode$$constant);
duke@0 2183 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2184 %}
duke@0 2185
duke@0 2186 enc_class cmpfp_fixup()
duke@0 2187 %{
duke@0 2188 // jnp,s exit
duke@0 2189 emit_opcode(cbuf, 0x7B);
duke@0 2190 emit_d8(cbuf, 0x0A);
duke@0 2191
duke@0 2192 // pushfq
duke@0 2193 emit_opcode(cbuf, 0x9C);
duke@0 2194
duke@0 2195 // andq $0xffffff2b, (%rsp)
duke@0 2196 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2197 emit_opcode(cbuf, 0x81);
duke@0 2198 emit_opcode(cbuf, 0x24);
duke@0 2199 emit_opcode(cbuf, 0x24);
duke@0 2200 emit_d32(cbuf, 0xffffff2b);
duke@0 2201
duke@0 2202 // popfq
duke@0 2203 emit_opcode(cbuf, 0x9D);
duke@0 2204
duke@0 2205 // nop (target for branch to avoid branch to branch)
duke@0 2206 emit_opcode(cbuf, 0x90);
duke@0 2207 %}
duke@0 2208
duke@0 2209 enc_class cmpfp3(rRegI dst)
duke@0 2210 %{
duke@0 2211 int dstenc = $dst$$reg;
duke@0 2212
duke@0 2213 // movl $dst, -1
duke@0 2214 if (dstenc >= 8) {
duke@0 2215 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2216 }
duke@0 2217 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2218 emit_d32(cbuf, -1);
duke@0 2219
duke@0 2220 // jp,s done
duke@0 2221 emit_opcode(cbuf, 0x7A);
duke@0 2222 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
duke@0 2223
duke@0 2224 // jb,s done
duke@0 2225 emit_opcode(cbuf, 0x72);
duke@0 2226 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2227
duke@0 2228 // setne $dst
duke@0 2229 if (dstenc >= 4) {
duke@0 2230 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2231 }
duke@0 2232 emit_opcode(cbuf, 0x0F);
duke@0 2233 emit_opcode(cbuf, 0x95);
duke@0 2234 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2235
duke@0 2236 // movzbl $dst, $dst
duke@0 2237 if (dstenc >= 4) {
duke@0 2238 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2239 }
duke@0 2240 emit_opcode(cbuf, 0x0F);
duke@0 2241 emit_opcode(cbuf, 0xB6);
duke@0 2242 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2243 %}
duke@0 2244
duke@0 2245 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 2246 %{
duke@0 2247 // Full implementation of Java idiv and irem; checks for
duke@0 2248 // special case as described in JVM spec., p.243 & p.271.
duke@0 2249 //
duke@0 2250 // normal case special case
duke@0 2251 //
duke@0 2252 // input : rax: dividend min_int
duke@0 2253 // reg: divisor -1
duke@0 2254 //
duke@0 2255 // output: rax: quotient (= rax idiv reg) min_int
duke@0 2256 // rdx: remainder (= rax irem reg) 0
duke@0 2257 //
duke@0 2258 // Code sequnce:
duke@0 2259 //
duke@0 2260 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 2261 // 5: 75 07/08 jne e <normal>
duke@0 2262 // 7: 33 d2 xor %edx,%edx
duke@0 2263 // [div >= 8 -> offset + 1]
duke@0 2264 // [REX_B]
duke@0 2265 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2266 // c: 74 03/04 je 11 <done>
duke@0 2267 // 000000000000000e <normal>:
duke@0 2268 // e: 99 cltd
duke@0 2269 // [div >= 8 -> offset + 1]
duke@0 2270 // [REX_B]
duke@0 2271 // f: f7 f9 idiv $div
duke@0 2272 // 0000000000000011 <done>:
duke@0 2273
duke@0 2274 // cmp $0x80000000,%eax
duke@0 2275 emit_opcode(cbuf, 0x3d);
duke@0 2276 emit_d8(cbuf, 0x00);
duke@0 2277 emit_d8(cbuf, 0x00);
duke@0 2278 emit_d8(cbuf, 0x00);
duke@0 2279 emit_d8(cbuf, 0x80);
duke@0 2280
duke@0 2281 // jne e <normal>
duke@0 2282 emit_opcode(cbuf, 0x75);
duke@0 2283 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 2284
duke@0 2285 // xor %edx,%edx
duke@0 2286 emit_opcode(cbuf, 0x33);
duke@0 2287 emit_d8(cbuf, 0xD2);
duke@0 2288
duke@0 2289 // cmp $0xffffffffffffffff,%ecx
duke@0 2290 if ($div$$reg >= 8) {
duke@0 2291 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2292 }
duke@0 2293 emit_opcode(cbuf, 0x83);
duke@0 2294 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2295 emit_d8(cbuf, 0xFF);
duke@0 2296
duke@0 2297 // je 11 <done>
duke@0 2298 emit_opcode(cbuf, 0x74);
duke@0 2299 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 2300
duke@0 2301 // <normal>
duke@0 2302 // cltd
duke@0 2303 emit_opcode(cbuf, 0x99);
duke@0 2304
duke@0 2305 // idivl (note: must be emitted by the user of this rule)
duke@0 2306 // <done>
duke@0 2307 %}
duke@0 2308
duke@0 2309 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 2310 %{
duke@0 2311 // Full implementation of Java ldiv and lrem; checks for
duke@0 2312 // special case as described in JVM spec., p.243 & p.271.
duke@0 2313 //
duke@0 2314 // normal case special case
duke@0 2315 //
duke@0 2316 // input : rax: dividend min_long
duke@0 2317 // reg: divisor -1
duke@0 2318 //
duke@0 2319 // output: rax: quotient (= rax idiv reg) min_long
duke@0 2320 // rdx: remainder (= rax irem reg) 0
duke@0 2321 //
duke@0 2322 // Code sequnce:
duke@0 2323 //
duke@0 2324 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 2325 // 7: 00 00 80
duke@0 2326 // a: 48 39 d0 cmp %rdx,%rax
duke@0 2327 // d: 75 08 jne 17 <normal>
duke@0 2328 // f: 33 d2 xor %edx,%edx
duke@0 2329 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2330 // 15: 74 05 je 1c <done>
duke@0 2331 // 0000000000000017 <normal>:
duke@0 2332 // 17: 48 99 cqto
duke@0 2333 // 19: 48 f7 f9 idiv $div
duke@0 2334 // 000000000000001c <done>:
duke@0 2335
duke@0 2336 // mov $0x8000000000000000,%rdx
duke@0 2337 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2338 emit_opcode(cbuf, 0xBA);
duke@0 2339 emit_d8(cbuf, 0x00);
duke@0 2340 emit_d8(cbuf, 0x00);
duke@0 2341 emit_d8(cbuf, 0x00);
duke@0 2342 emit_d8(cbuf, 0x00);
duke@0 2343 emit_d8(cbuf, 0x00);
duke@0 2344 emit_d8(cbuf, 0x00);
duke@0 2345 emit_d8(cbuf, 0x00);
duke@0 2346 emit_d8(cbuf, 0x80);
duke@0 2347
duke@0 2348 // cmp %rdx,%rax
duke@0 2349 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2350 emit_opcode(cbuf, 0x39);
duke@0 2351 emit_d8(cbuf, 0xD0);
duke@0 2352
duke@0 2353 // jne 17 <normal>
duke@0 2354 emit_opcode(cbuf, 0x75);
duke@0 2355 emit_d8(cbuf, 0x08);
duke@0 2356
duke@0 2357 // xor %edx,%edx
duke@0 2358 emit_opcode(cbuf, 0x33);
duke@0 2359 emit_d8(cbuf, 0xD2);
duke@0 2360
duke@0 2361 // cmp $0xffffffffffffffff,$div
duke@0 2362 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 2363 emit_opcode(cbuf, 0x83);
duke@0 2364 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2365 emit_d8(cbuf, 0xFF);
duke@0 2366
duke@0 2367 // je 1e <done>
duke@0 2368 emit_opcode(cbuf, 0x74);
duke@0 2369 emit_d8(cbuf, 0x05);
duke@0 2370
duke@0 2371 // <normal>
duke@0 2372 // cqto
duke@0 2373 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2374 emit_opcode(cbuf, 0x99);
duke@0 2375
duke@0 2376 // idivq (note: must be emitted by the user of this rule)
duke@0 2377 // <done>
duke@0 2378 %}
duke@0 2379
duke@0 2380 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 2381 enc_class OpcSE(immI imm)
duke@0 2382 %{
duke@0 2383 // Emit primary opcode and set sign-extend bit
duke@0 2384 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2385 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2386 emit_opcode(cbuf, $primary | 0x02);
duke@0 2387 } else {
duke@0 2388 // 32-bit immediate
duke@0 2389 emit_opcode(cbuf, $primary);
duke@0 2390 }
duke@0 2391 %}
duke@0 2392
duke@0 2393 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 2394 %{
duke@0 2395 // OpcSEr/m
duke@0 2396 int dstenc = $dst$$reg;
duke@0 2397 if (dstenc >= 8) {
duke@0 2398 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2399 dstenc -= 8;
duke@0 2400 }
duke@0 2401 // Emit primary opcode and set sign-extend bit
duke@0 2402 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2403 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2404 emit_opcode(cbuf, $primary | 0x02);
duke@0 2405 } else {
duke@0 2406 // 32-bit immediate
duke@0 2407 emit_opcode(cbuf, $primary);
duke@0 2408 }
duke@0 2409 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2410 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2411 %}
duke@0 2412
duke@0 2413 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 2414 %{
duke@0 2415 // OpcSEr/m
duke@0 2416 int dstenc = $dst$$reg;
duke@0 2417 if (dstenc < 8) {
duke@0 2418 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2419 } else {
duke@0 2420 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2421 dstenc -= 8;
duke@0 2422 }
duke@0 2423 // Emit primary opcode and set sign-extend bit
duke@0 2424 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2425 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2426 emit_opcode(cbuf, $primary | 0x02);
duke@0 2427 } else {
duke@0 2428 // 32-bit immediate
duke@0 2429 emit_opcode(cbuf, $primary);
duke@0 2430 }
duke@0 2431 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2432 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2433 %}
duke@0 2434
duke@0 2435 enc_class Con8or32(immI imm)
duke@0 2436 %{
duke@0 2437 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2438 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2439 $$$emit8$imm$$constant;
duke@0 2440 } else {
duke@0 2441 // 32-bit immediate
duke@0 2442 $$$emit32$imm$$constant;
duke@0 2443 }
duke@0 2444 %}
duke@0 2445
duke@0 2446 enc_class Lbl(label labl)
duke@0 2447 %{
duke@0 2448 // JMP, CALL
duke@0 2449 Label* l = $labl$$label;
twisti@1668 2450 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
duke@0 2451 %}
duke@0 2452
duke@0 2453 enc_class LblShort(label labl)
duke@0 2454 %{
duke@0 2455 // JMP, CALL
duke@0 2456 Label* l = $labl$$label;
twisti@1668 2457 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
duke@0 2458 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2459 emit_d8(cbuf, disp);
duke@0 2460 %}
duke@0 2461
duke@0 2462 enc_class opc2_reg(rRegI dst)
duke@0 2463 %{
duke@0 2464 // BSWAP
duke@0 2465 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2466 %}
duke@0 2467
duke@0 2468 enc_class opc3_reg(rRegI dst)
duke@0 2469 %{
duke@0 2470 // BSWAP
duke@0 2471 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2472 %}
duke@0 2473
duke@0 2474 enc_class reg_opc(rRegI div)
duke@0 2475 %{
duke@0 2476 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2477 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2478 %}
duke@0 2479
duke@0 2480 enc_class Jcc(cmpOp cop, label labl)
duke@0 2481 %{
duke@0 2482 // JCC
duke@0 2483 Label* l = $labl$$label;
duke@0 2484 $$$emit8$primary;
duke@0 2485 emit_cc(cbuf, $secondary, $cop$$cmpcode);
twisti@1668 2486 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
duke@0 2487 %}
duke@0 2488
duke@0 2489 enc_class JccShort (cmpOp cop, label labl)
duke@0 2490 %{
duke@0 2491 // JCC
duke@0 2492 Label *l = $labl$$label;
duke@0 2493 emit_cc(cbuf, $primary, $cop$$cmpcode);
twisti@1668 2494 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
duke@0 2495 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2496 emit_d8(cbuf, disp);
duke@0 2497 %}
duke@0 2498
duke@0 2499 enc_class enc_cmov(cmpOp cop)
duke@0 2500 %{
duke@0 2501 // CMOV
duke@0 2502 $$$emit8$primary;
duke@0 2503 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2504 %}
duke@0 2505
duke@0 2506 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
duke@0 2507 %{
duke@0 2508 // Invert sense of branch from sense of cmov
duke@0 2509 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2510 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
duke@0 2511 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 2512 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
duke@0 2513 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
duke@0 2514 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
duke@0 2515 if ($dst$$reg < 8) {
duke@0 2516 if ($src$$reg >= 8) {
duke@0 2517 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2518 }
duke@0 2519 } else {
duke@0 2520 if ($src$$reg < 8) {
duke@0 2521 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2522 } else {
duke@0 2523 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2524 }
duke@0 2525 }
duke@0 2526 emit_opcode(cbuf, 0x0F);
duke@0 2527 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2528 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2529 %}
duke@0 2530
duke@0 2531 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
duke@0 2532 %{
duke@0 2533 // Invert sense of branch from sense of cmov
duke@0 2534 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2535 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
duke@0 2536
duke@0 2537 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
duke@0 2538 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 2539 if ($dst$$reg < 8) {
duke@0 2540 if ($src$$reg >= 8) {
duke@0 2541 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2542 }
duke@0 2543 } else {
duke@0 2544 if ($src$$reg < 8) {
duke@0 2545 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2546 } else {
duke@0 2547 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2548 }
duke@0 2549 }
duke@0 2550 emit_opcode(cbuf, 0x0F);
duke@0 2551 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2552 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2553 %}
duke@0 2554
duke@0 2555 enc_class enc_PartialSubtypeCheck()
duke@0 2556 %{
duke@0 2557 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2558 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2559 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2560 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2561 Label miss;
jrose@644 2562 const bool set_cond_codes = true;
duke@0 2563
duke@0 2564 MacroAssembler _masm(&cbuf);
jrose@644 2565 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2566 NULL, &miss,
jrose@644 2567 /*set_cond_codes:*/ true);
duke@0 2568 if ($primary) {
never@304 2569 __ xorptr(Rrdi, Rrdi);
duke@0 2570 }
duke@0 2571 __ bind(miss);
duke@0 2572 %}
duke@0 2573
duke@0 2574 enc_class Java_To_Interpreter(method meth)
duke@0 2575 %{
duke@0 2576 // CALL Java_To_Interpreter
duke@0 2577 // This is the instruction starting address for relocation info.
twisti@1668 2578 cbuf.set_insts_mark();
duke@0 2579 $$$emit8$primary;
duke@0 2580 // CALL directly to the runtime
duke@0 2581 emit_d32_reloc(cbuf,
twisti@1668 2582 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2583 runtime_call_Relocation::spec(),
duke@0 2584 RELOC_DISP32);
duke@0 2585 %}
duke@0 2586
twisti@1137 2587 enc_class preserve_SP %{
twisti@1668 2588 debug_only(int off0 = cbuf.insts_size());
twisti@1137 2589 MacroAssembler _masm(&cbuf);
twisti@1137 2590 // RBP is preserved across all calls, even compiled calls.
twisti@1137 2591 // Use it to preserve RSP in places where the callee might change the SP.
twisti@1487 2592 __ movptr(rbp_mh_SP_save, rsp);
twisti@1668 2593 debug_only(int off1 = cbuf.insts_size());
twisti@1137 2594 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
twisti@1137 2595 %}
twisti@1137 2596
twisti@1137 2597 enc_class restore_SP %{
twisti@1137 2598 MacroAssembler _masm(&cbuf);
twisti@1487 2599 __ movptr(rsp, rbp_mh_SP_save);
twisti@1137 2600 %}
twisti@1137 2601
duke@0 2602 enc_class Java_Static_Call(method meth)
duke@0 2603 %{
duke@0 2604 // JAVA STATIC CALL
duke@0 2605 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2606 // determine who we intended to call.
twisti@1668 2607 cbuf.set_insts_mark();
duke@0 2608 $$$emit8$primary;
duke@0 2609
duke@0 2610 if (!_method) {
duke@0 2611 emit_d32_reloc(cbuf,
twisti@1668 2612 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2613 runtime_call_Relocation::spec(),
duke@0 2614 RELOC_DISP32);
duke@0 2615 } else if (_optimized_virtual) {
duke@0 2616 emit_d32_reloc(cbuf,
twisti@1668 2617 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2618 opt_virtual_call_Relocation::spec(),
duke@0 2619 RELOC_DISP32);
duke@0 2620 } else {
duke@0 2621 emit_d32_reloc(cbuf,
twisti@1668 2622 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2623 static_call_Relocation::spec(),
duke@0 2624 RELOC_DISP32);
duke@0 2625 }
duke@0 2626 if (_method) {
duke@0 2627 // Emit stub for static call
duke@0 2628 emit_java_to_interp(cbuf);
duke@0 2629 }
duke@0 2630 %}
duke@0 2631
duke@0 2632 enc_class Java_Dynamic_Call(method meth)
duke@0 2633 %{
duke@0 2634 // JAVA DYNAMIC CALL
duke@0 2635 // !!!!!
duke@0 2636 // Generate "movq rax, -1", placeholder instruction to load oop-info
duke@0 2637 // emit_call_dynamic_prologue( cbuf );
twisti@1668 2638 cbuf.set_insts_mark();
duke@0 2639
duke@0 2640 // movq rax, -1
duke@0 2641 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2642 emit_opcode(cbuf, 0xB8 | RAX_enc);
duke@0 2643 emit_d64_reloc(cbuf,
duke@0 2644 (int64_t) Universe::non_oop_word(),
duke@0 2645 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
twisti@1668 2646 address virtual_call_oop_addr = cbuf.insts_mark();
duke@0 2647 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2648 // who we intended to call.
twisti@1668 2649 cbuf.set_insts_mark();
duke@0 2650 $$$emit8$primary;
duke@0 2651 emit_d32_reloc(cbuf,
twisti@1668 2652 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2653 virtual_call_Relocation::spec(virtual_call_oop_addr),
duke@0 2654 RELOC_DISP32);
duke@0 2655 %}
duke@0 2656
duke@0 2657 enc_class Java_Compiled_Call(method meth)
duke@0 2658 %{
duke@0 2659 // JAVA COMPILED CALL
duke@0 2660 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
duke@0 2661
duke@0 2662 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2663 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2664
duke@0 2665 // callq *disp(%rax)
twisti@1668 2666 cbuf.set_insts_mark();
duke@0 2667 $$$emit8$primary;
duke@0 2668 if (disp < 0x80) {
duke@0 2669 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2670 emit_d8(cbuf, disp); // Displacement
duke@0 2671 } else {
duke@0 2672 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2673 emit_d32(cbuf, disp); // Displacement
duke@0 2674 }
duke@0 2675 %}
duke@0 2676
duke@0 2677 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2678 %{
duke@0 2679 // SAL, SAR, SHR
duke@0 2680 int dstenc = $dst$$reg;
duke@0 2681 if (dstenc >= 8) {
duke@0 2682 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2683 dstenc -= 8;
duke@0 2684 }
duke@0 2685 $$$emit8$primary;
duke@0 2686 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2687 $$$emit8$shift$$constant;
duke@0 2688 %}
duke@0 2689
duke@0 2690 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2691 %{
duke@0 2692 // SAL, SAR, SHR
duke@0 2693 int dstenc = $dst$$reg;
duke@0 2694 if (dstenc < 8) {
duke@0 2695 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2696 } else {
duke@0 2697 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2698 dstenc -= 8;
duke@0 2699 }
duke@0 2700 $$$emit8$primary;
duke@0 2701 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2702 $$$emit8$shift$$constant;
duke@0 2703 %}
duke@0 2704
duke@0 2705 enc_class load_immI(rRegI dst, immI src)
duke@0 2706 %{
duke@0 2707 int dstenc = $dst$$reg;
duke@0 2708 if (dstenc >= 8) {
duke@0 2709 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2710 dstenc -= 8;
duke@0 2711 }
duke@0 2712 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2713 $$$emit32$src$$constant;
duke@0 2714 %}
duke@0 2715
duke@0 2716 enc_class load_immL(rRegL dst, immL src)
duke@0 2717 %{
duke@0 2718 int dstenc = $dst$$reg;
duke@0 2719 if (dstenc < 8) {
duke@0 2720 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2721 } else {
duke@0 2722 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2723 dstenc -= 8;
duke@0 2724 }
duke@0 2725 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2726 emit_d64(cbuf, $src$$constant);
duke@0 2727 %}
duke@0 2728
duke@0 2729 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2730 %{
duke@0 2731 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2732 int dstenc = $dst$$reg;
duke@0 2733 if (dstenc >= 8) {
duke@0 2734 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2735 dstenc -= 8;
duke@0 2736 }
duke@0 2737 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2738 $$$emit32$src$$constant;
duke@0 2739 %}
duke@0 2740
duke@0 2741 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2742 %{
duke@0 2743 int dstenc = $dst$$reg;
duke@0 2744 if (dstenc < 8) {
duke@0 2745 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2746 } else {
duke@0 2747 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2748 dstenc -= 8;
duke@0 2749 }
duke@0 2750 emit_opcode(cbuf, 0xC7);
duke@0 2751 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2752 $$$emit32$src$$constant;
duke@0 2753 %}
duke@0 2754
duke@0 2755 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2756 %{
duke@0 2757 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2758 int dstenc = $dst$$reg;
duke@0 2759 if (dstenc >= 8) {
duke@0 2760 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2761 dstenc -= 8;
duke@0 2762 }
duke@0 2763 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2764 $$$emit32$src$$constant;
duke@0 2765 %}
duke@0 2766
duke@0 2767 enc_class load_immP(rRegP dst, immP src)
duke@0 2768 %{
duke@0 2769 int dstenc = $dst$$reg;
duke@0 2770 if (dstenc < 8) {
duke@0 2771 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2772 } else {
duke@0 2773 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2774 dstenc -= 8;
duke@0 2775 }
duke@0 2776 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2777 // This next line should be generated from ADLC
duke@0 2778 if ($src->constant_is_oop()) {
duke@0 2779 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
duke@0 2780 } else {
duke@0 2781 emit_d64(cbuf, $src$$constant);
duke@0 2782 }
duke@0 2783 %}
duke@0 2784
duke@0 2785 enc_class load_immF(regF dst, immF con)
duke@0 2786 %{
duke@0 2787 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 2788 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2789 emit_float_constant(cbuf, $con$$constant);
duke@0 2790 %}
duke@0 2791
duke@0 2792 enc_class load_immD(regD dst, immD con)
duke@0 2793 %{
duke@0 2794 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 2795 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2796 emit_double_constant(cbuf, $con$$constant);
duke@0 2797 %}
duke@0 2798
duke@0 2799 enc_class load_conF (regF dst, immF con) %{ // Load float constant
duke@0 2800 emit_opcode(cbuf, 0xF3);
duke@0 2801 if ($dst$$reg >= 8) {
duke@0 2802 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2803 }
duke@0 2804 emit_opcode(cbuf, 0x0F);
duke@0 2805 emit_opcode(cbuf, 0x10);
duke@0 2806 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2807 emit_float_constant(cbuf, $con$$constant);
duke@0 2808 %}
duke@0 2809
duke@0 2810 enc_class load_conD (regD dst, immD con) %{ // Load double constant
duke@0 2811 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
duke@0 2812 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 2813 if ($dst$$reg >= 8) {
duke@0 2814 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2815 }
duke@0 2816 emit_opcode(cbuf, 0x0F);
duke@0 2817 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 2818 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2819 emit_double_constant(cbuf, $con$$constant);
duke@0 2820 %}
duke@0 2821
duke@0 2822 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2823 enc_class enc_copy(rRegI dst, rRegI src)
duke@0 2824 %{
duke@0 2825 encode_copy(cbuf, $dst$$reg, $src$$reg);
duke@0 2826 %}
duke@0 2827
duke@0 2828 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
duke@0 2829 enc_class enc_CopyXD( RegD dst, RegD src ) %{
duke@0 2830 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
duke@0 2831 %}
duke@0 2832
duke@0 2833 enc_class enc_copy_always(rRegI dst, rRegI src)
duke@0 2834 %{
duke@0 2835 int srcenc = $src$$reg;
duke@0 2836 int dstenc = $dst$$reg;
duke@0 2837
duke@0 2838 if (dstenc < 8) {
duke@0 2839 if (srcenc >= 8) {
duke@0 2840 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2841 srcenc -= 8;
duke@0 2842 }
duke@0 2843 } else {
duke@0 2844 if (srcenc < 8) {
duke@0 2845 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2846 } else {
duke@0 2847 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2848 srcenc -= 8;
duke@0 2849 }
duke@0 2850 dstenc -= 8;
duke@0 2851 }
duke@0 2852
duke@0 2853 emit_opcode(cbuf, 0x8B);
duke@0 2854 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2855 %}
duke@0 2856
duke@0 2857 enc_class enc_copy_wide(rRegL dst, rRegL src)
duke@0 2858 %{
duke@0 2859 int srcenc = $src$$reg;
duke@0 2860 int dstenc = $dst$$reg;
duke@0 2861
duke@0 2862 if (dstenc != srcenc) {
duke@0 2863 if (dstenc < 8) {
duke@0 2864 if (srcenc < 8) {
duke@0 2865 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2866 } else {
duke@0 2867 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2868 srcenc -= 8;
duke@0 2869 }
duke@0 2870 } else {
duke@0 2871 if (srcenc < 8) {
duke@0 2872 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2873 } else {
duke@0 2874 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2875 srcenc -= 8;
duke@0 2876 }
duke@0 2877 dstenc -= 8;
duke@0 2878 }
duke@0 2879 emit_opcode(cbuf, 0x8B);
duke@0 2880 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2881 }
duke@0 2882 %}
duke@0 2883
duke@0 2884 enc_class Con32(immI src)
duke@0 2885 %{
duke@0 2886 // Output immediate
duke@0 2887 $$$emit32$src$$constant;
duke@0 2888 %}
duke@0 2889
duke@0 2890 enc_class Con64(immL src)
duke@0 2891 %{
duke@0 2892 // Output immediate
duke@0 2893 emit_d64($src$$constant);
duke@0 2894 %}
duke@0 2895
duke@0 2896 enc_class Con32F_as_bits(immF src)
duke@0 2897 %{
duke@0 2898 // Output Float immediate bits
duke@0 2899 jfloat jf = $src$$constant;
duke@0 2900 jint jf_as_bits = jint_cast(jf);
duke@0 2901 emit_d32(cbuf, jf_as_bits);
duke@0 2902 %}
duke@0 2903
duke@0 2904 enc_class Con16(immI src)
duke@0 2905 %{
duke@0 2906 // Output immediate
duke@0 2907 $$$emit16$src$$constant;
duke@0 2908 %}
duke@0 2909
duke@0 2910 // How is this different from Con32??? XXX
duke@0 2911 enc_class Con_d32(immI src)
duke@0 2912 %{
duke@0 2913 emit_d32(cbuf,$src$$constant);
duke@0 2914 %}
duke@0 2915
duke@0 2916 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2917 // Output immediate memory reference
duke@0 2918 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2919 emit_d32(cbuf, 0x00);
duke@0 2920 %}
duke@0 2921
duke@0 2922 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
duke@0 2923 MacroAssembler masm(&cbuf);
duke@0 2924
duke@0 2925 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2926 Register dest_reg = as_Register($dest$$reg);
duke@0 2927 address table_base = masm.address_table_constant(_index2label);
duke@0 2928
duke@0 2929 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 2930 // to do that and the compiler is using that register as one it can allocate.
duke@0 2931 // So we build it all by hand.
duke@0 2932 // Address index(noreg, switch_reg, Address::times_1);
duke@0 2933 // ArrayAddress dispatch(table, index);
duke@0 2934
duke@0 2935 Address dispatch(dest_reg, switch_reg, Address::times_1);
duke@0 2936
duke@0 2937 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 2938 masm.jmp(dispatch);
duke@0 2939 %}
duke@0 2940
duke@0 2941 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
duke@0 2942 MacroAssembler masm(&cbuf);
duke@0 2943
duke@0 2944 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2945 Register dest_reg = as_Register($dest$$reg);
duke@0 2946 address table_base = masm.address_table_constant(_index2label);
duke@0 2947
duke@0 2948 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 2949 // to do that and the compiler is using that register as one it can allocate.
duke@0 2950 // So we build it all by hand.
duke@0 2951 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
duke@0 2952 // ArrayAddress dispatch(table, index);
duke@0 2953
duke@0 2954 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
duke@0 2955
duke@0 2956 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 2957 masm.jmp(dispatch);
duke@0 2958 %}
duke@0 2959
duke@0 2960 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
duke@0 2961 MacroAssembler masm(&cbuf);
duke@0 2962
duke@0 2963 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2964 Register dest_reg = as_Register($dest$$reg);
duke@0 2965 address table_base = masm.address_table_constant(_index2label);
duke@0 2966
duke@0 2967 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 2968 // to do that and the compiler is using that register as one it can allocate.
duke@0 2969 // So we build it all by hand.
duke@0 2970 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
duke@0 2971 // ArrayAddress dispatch(table, index);
duke@0 2972
duke@0 2973 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
duke@0 2974 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 2975 masm.jmp(dispatch);
duke@0 2976
duke@0 2977 %}
duke@0 2978
duke@0 2979 enc_class lock_prefix()
duke@0 2980 %{
duke@0 2981 if (os::is_MP()) {
duke@0 2982 emit_opcode(cbuf, 0xF0); // lock
duke@0 2983 }
duke@0 2984 %}
duke@0 2985
duke@0 2986 enc_class REX_mem(memory mem)
duke@0 2987 %{
duke@0 2988 if ($mem$$base >= 8) {
duke@0 2989 if ($mem$$index < 8) {
duke@0 2990 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2991 } else {
duke@0 2992 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2993 }
duke@0 2994 } else {
duke@0 2995 if ($mem$$index >= 8) {
duke@0 2996 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2997 }
duke@0 2998 }
duke@0 2999 %}
duke@0 3000
duke@0 3001 enc_class REX_mem_wide(memory mem)
duke@0 3002 %{
duke@0 3003 if ($mem$$base >= 8) {
duke@0 3004 if ($mem$$index < 8) {
duke@0 3005 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3006 } else {
duke@0 3007 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3008 }
duke@0 3009 } else {
duke@0 3010 if ($mem$$index < 8) {
duke@0 3011 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3012 } else {
duke@0 3013 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3014 }
duke@0 3015 }
duke@0 3016 %}
duke@0 3017
duke@0 3018 // for byte regs
duke@0 3019 enc_class REX_breg(rRegI reg)
duke@0 3020 %{
duke@0 3021 if ($reg$$reg >= 4) {
duke@0 3022 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3023 }
duke@0 3024 %}
duke@0 3025
duke@0 3026 // for byte regs
duke@0 3027 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 3028 %{
duke@0 3029 if ($dst$$reg < 8) {
duke@0 3030 if ($src$$reg >= 4) {
duke@0 3031 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3032 }
duke@0 3033 } else {
duke@0 3034 if ($src$$reg < 8) {
duke@0 3035 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3036 } else {
duke@0 3037 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3038 }
duke@0 3039 }
duke@0 3040 %}
duke@0 3041
duke@0 3042 // for byte regs
duke@0 3043 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 3044 %{
duke@0 3045 if ($reg$$reg < 8) {
duke@0 3046 if ($mem$$base < 8) {
duke@0 3047 if ($mem$$index >= 8) {
duke@0 3048 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3049 } else if ($reg$$reg >= 4) {
duke@0 3050 emit_opcode(cbuf, Assembler::REX);
duke@0 3051 }
duke@0 3052 } else {
duke@0 3053 if ($mem$$index < 8) {
duke@0 3054 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3055 } else {
duke@0 3056 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3057 }
duke@0 3058 }
duke@0 3059 } else {
duke@0 3060 if ($mem$$base < 8) {
duke@0 3061 if ($mem$$index < 8) {
duke@0 3062 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3063 } else {
duke@0 3064 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3065 }
duke@0 3066 } else {
duke@0 3067 if ($mem$$index < 8) {
duke@0 3068 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3069 } else {
duke@0 3070 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3071 }
duke@0 3072 }
duke@0 3073 }
duke@0 3074 %}
duke@0 3075
duke@0 3076 enc_class REX_reg(rRegI reg)
duke@0 3077 %{
duke@0 3078 if ($reg$$reg >= 8) {
duke@0 3079 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3080 }
duke@0 3081 %}
duke@0 3082
duke@0 3083 enc_class REX_reg_wide(rRegI reg)
duke@0 3084 %{
duke@0 3085 if ($reg$$reg < 8) {
duke@0 3086 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3087 } else {
duke@0 3088 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3089 }
duke@0 3090 %}
duke@0 3091
duke@0 3092 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 3093 %{
duke@0 3094 if ($dst$$reg < 8) {
duke@0 3095 if ($src$$reg >= 8) {
duke@0 3096 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3097 }
duke@0 3098 } else {
duke@0 3099 if ($src$$reg < 8) {
duke@0 3100 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3101 } else {
duke@0 3102 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3103 }
duke@0 3104 }
duke@0 3105 %}
duke@0 3106
duke@0 3107 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 3108 %{
duke@0 3109 if ($dst$$reg < 8) {
duke@0 3110 if ($src$$reg < 8) {
duke@0 3111 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3112 } else {
duke@0 3113 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3114 }
duke@0 3115 } else {
duke@0 3116 if ($src$$reg < 8) {
duke@0 3117 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3118 } else {
duke@0 3119 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3120 }
duke@0 3121 }
duke@0 3122 %}
duke@0 3123
duke@0 3124 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 3125 %{
duke@0 3126 if ($reg$$reg < 8) {
duke@0 3127 if ($mem$$base < 8) {
duke@0 3128 if ($mem$$index >= 8) {
duke@0 3129 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3130 }
duke@0 3131 } else {
duke@0 3132 if ($mem$$index < 8) {
duke@0 3133 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3134 } else {
duke@0 3135 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3136 }
duke@0 3137 }
duke@0 3138 } else {
duke@0 3139 if ($mem$$base < 8) {
duke@0 3140 if ($mem$$index < 8) {
duke@0 3141 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3142 } else {
duke@0 3143 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3144 }
duke@0 3145 } else {
duke@0 3146 if ($mem$$index < 8) {
duke@0 3147 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3148 } else {
duke@0 3149 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3150 }
duke@0 3151 }
duke@0 3152 }
duke@0 3153 %}
duke@0 3154
duke@0 3155 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 3156 %{
duke@0 3157 if ($reg$$reg < 8) {
duke@0 3158 if ($mem$$base < 8) {
duke@0 3159 if ($mem$$index < 8) {
duke@0 3160 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3161 } else {
duke@0 3162 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3163 }
duke@0 3164 } else {
duke@0 3165 if ($mem$$index < 8) {
duke@0 3166 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3167 } else {
duke@0 3168 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3169 }
duke@0 3170 }
duke@0 3171 } else {
duke@0 3172 if ($mem$$base < 8) {
duke@0 3173 if ($mem$$index < 8) {
duke@0 3174 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3175 } else {
duke@0 3176 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 3177 }
duke@0 3178 } else {
duke@0 3179 if ($mem$$index < 8) {
duke@0 3180 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3181 } else {
duke@0 3182 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 3183 }
duke@0 3184 }
duke@0 3185 }
duke@0 3186 %}
duke@0 3187
duke@0 3188 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 3189 %{
duke@0 3190 // High registers handle in encode_RegMem
duke@0 3191 int reg = $ereg$$reg;
duke@0 3192 int base = $mem$$base;
duke@0 3193 int index = $mem$$index;
duke@0 3194 int scale = $mem$$scale;
duke@0 3195 int disp = $mem$$disp;
duke@0 3196 bool disp_is_oop = $mem->disp_is_oop();
duke@0 3197
duke@0 3198 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
duke@0 3199 %}
duke@0 3200
duke@0 3201 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 3202 %{
duke@0 3203 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 3204
duke@0 3205 // High registers handle in encode_RegMem
duke@0 3206 int base = $mem$$base;
duke@0 3207 int index = $mem$$index;
duke@0 3208 int scale = $mem$$scale;
duke@0 3209 int displace = $mem$$disp;
duke@0 3210
duke@0 3211 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
duke@0 3212 // working with static
duke@0 3213 // globals
duke@0 3214 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
duke@0 3215 disp_is_oop);
duke@0 3216 %}
duke@0 3217
duke@0 3218 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 3219 %{
duke@0 3220 int reg_encoding = $dst$$reg;
duke@0 3221 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 3222 int index = 0x04; // 0x04 indicates no index
duke@0 3223 int scale = 0x00; // 0x00 indicates no scale
duke@0 3224 int displace = $src1$$constant; // 0x00 indicates no displacement
duke@0 3225 bool disp_is_oop = false;
duke@0 3226 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
duke@0 3227 disp_is_oop);
duke@0 3228 %}
duke@0 3229
duke@0 3230 enc_class neg_reg(rRegI dst)
duke@0 3231 %{
duke@0 3232 int dstenc = $dst$$reg;
duke@0 3233 if (dstenc >= 8) {
duke@0 3234 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3235 dstenc -= 8;
duke@0 3236 }
duke@0 3237 // NEG $dst
duke@0 3238 emit_opcode(cbuf, 0xF7);
duke@0 3239 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3240 %}
duke@0 3241
duke@0 3242 enc_class neg_reg_wide(rRegI dst)
duke@0 3243 %{
duke@0 3244 int dstenc = $dst$$reg;
duke@0 3245 if (dstenc < 8) {
duke@0 3246 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3247 } else {
duke@0 3248 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3249 dstenc -= 8;
duke@0 3250 }
duke@0 3251 // NEG $dst
duke@0 3252 emit_opcode(cbuf, 0xF7);
duke@0 3253 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3254 %}
duke@0 3255
duke@0 3256 enc_class setLT_reg(rRegI dst)
duke@0 3257 %{
duke@0 3258 int dstenc = $dst$$reg;
duke@0 3259 if (dstenc >= 8) {
duke@0 3260 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3261 dstenc -= 8;
duke@0 3262 } else if (dstenc >= 4) {
duke@0 3263 emit_opcode(cbuf, Assembler::REX);
duke@0 3264 }
duke@0 3265 // SETLT $dst
duke@0 3266 emit_opcode(cbuf, 0x0F);
duke@0 3267 emit_opcode(cbuf, 0x9C);
duke@0 3268 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3269 %}
duke@0 3270
duke@0 3271 enc_class setNZ_reg(rRegI dst)
duke@0 3272 %{
duke@0 3273 int dstenc = $dst$$reg;
duke@0 3274 if (dstenc >= 8) {
duke@0 3275 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3276 dstenc -= 8;
duke@0 3277 } else if (dstenc >= 4) {
duke@0 3278 emit_opcode(cbuf, Assembler::REX);
duke@0 3279 }
duke@0 3280 // SETNZ $dst
duke@0 3281 emit_opcode(cbuf, 0x0F);
duke@0 3282 emit_opcode(cbuf, 0x95);
duke@0 3283 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3284 %}
duke@0 3285
duke@0 3286 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
duke@0 3287 rcx_RegI tmp)
duke@0 3288 %{
duke@0 3289 // cadd_cmpLT
duke@0 3290
duke@0 3291 int tmpReg = $tmp$$reg;
duke@0 3292
duke@0 3293 int penc = $p$$reg;
duke@0 3294 int qenc = $q$$reg;
duke@0 3295 int yenc = $y$$reg;
duke@0 3296
duke@0 3297 // subl $p,$q
duke@0 3298 if (penc < 8) {
duke@0 3299 if (qenc >= 8) {
duke@0 3300 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3301 }
duke@0 3302 } else {
duke@0 3303 if (qenc < 8) {
duke@0 3304 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3305 } else {
duke@0 3306 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3307 }
duke@0 3308 }
duke@0 3309 emit_opcode(cbuf, 0x2B);
duke@0 3310 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
duke@0 3311
duke@0 3312 // sbbl $tmp, $tmp
duke@0 3313 emit_opcode(cbuf, 0x1B);
duke@0 3314 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
duke@0 3315
duke@0 3316 // andl $tmp, $y
duke@0 3317 if (yenc >= 8) {
duke@0 3318 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3319 }
duke@0 3320 emit_opcode(cbuf, 0x23);
duke@0 3321 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
duke@0 3322
duke@0 3323 // addl $p,$tmp
duke@0 3324 if (penc >= 8) {
duke@0 3325 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3326 }
duke@0 3327 emit_opcode(cbuf, 0x03);
duke@0 3328 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
duke@0 3329 %}
duke@0 3330
duke@0 3331 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 3332 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 3333 %{
duke@0 3334 int src1enc = $src1$$reg;
duke@0 3335 int src2enc = $src2$$reg;
duke@0 3336 int dstenc = $dst$$reg;
duke@0 3337
duke@0 3338 // cmpq $src1, $src2
duke@0 3339 if (src1enc < 8) {
duke@0 3340 if (src2enc < 8) {
duke@0 3341 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3342 } else {
duke@0 3343 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3344 }
duke@0 3345 } else {
duke@0 3346 if (src2enc < 8) {
duke@0 3347 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3348 } else {
duke@0 3349 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3350 }
duke@0 3351 }
duke@0 3352 emit_opcode(cbuf, 0x3B);
duke@0 3353 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 3354
duke@0 3355 // movl $dst, -1
duke@0 3356 if (dstenc >= 8) {
duke@0 3357 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3358 }
duke@0 3359 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 3360 emit_d32(cbuf, -1);
duke@0 3361
duke@0 3362 // jl,s done
duke@0 3363 emit_opcode(cbuf, 0x7C);
duke@0 3364 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 3365
duke@0 3366 // setne $dst
duke@0 3367 if (dstenc >= 4) {
duke@0 3368 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3369 }
duke@0 3370 emit_opcode(cbuf, 0x0F);
duke@0 3371 emit_opcode(cbuf, 0x95);
duke@0 3372 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 3373
duke@0 3374 // movzbl $dst, $dst
duke@0 3375 if (dstenc >= 4) {
duke@0 3376 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 3377 }
duke@0 3378 emit_opcode(cbuf, 0x0F);
duke@0 3379 emit_opcode(cbuf, 0xB6);
duke@0 3380 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 3381 %}
duke@0 3382
duke@0 3383 enc_class Push_ResultXD(regD dst) %{
duke@0 3384 int dstenc = $dst$$reg;
duke@0 3385
duke@0 3386 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
duke@0 3387
duke@0 3388 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
duke@0 3389 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 3390 if (dstenc >= 8) {
duke@0 3391 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3392 }
duke@0 3393 emit_opcode (cbuf, 0x0F );
duke@0 3394 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
duke@0 3395 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3396
duke@0 3397 // add rsp,8
duke@0 3398 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3399 emit_opcode(cbuf,0x83);
duke@0 3400 emit_rm(cbuf,0x3, 0x0, RSP_enc);
duke@0 3401 emit_d8(cbuf,0x08);
duke@0 3402 %}
duke@0 3403
duke@0 3404 enc_class Push_SrcXD(regD src) %{
duke@0 3405 int srcenc = $src$$reg;
duke@0 3406
duke@0 3407 // subq rsp,#8
duke@0 3408 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3409 emit_opcode(cbuf, 0x83);
duke@0 3410 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3411 emit_d8(cbuf, 0x8);
duke@0 3412
duke@0 3413 // movsd [rsp],src
duke@0 3414 emit_opcode(cbuf, 0xF2);
duke@0 3415 if (srcenc >= 8) {
duke@0 3416 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3417 }
duke@0 3418 emit_opcode(cbuf, 0x0F);
duke@0 3419 emit_opcode(cbuf, 0x11);
duke@0 3420 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3421
duke@0 3422 // fldd [rsp]
duke@0 3423 emit_opcode(cbuf, 0x66);
duke@0 3424 emit_opcode(cbuf, 0xDD);
duke@0 3425 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
duke@0 3426 %}
duke@0 3427
duke@0 3428
duke@0 3429 enc_class movq_ld(regD dst, memory mem) %{
duke@0 3430 MacroAssembler _masm(&cbuf);
twisti@624 3431 __ movq($dst$$XMMRegister, $mem$$Address);
duke@0 3432 %}
duke@0 3433
duke@0 3434 enc_class movq_st(memory mem, regD src) %{
duke@0 3435 MacroAssembler _masm(&cbuf);
twisti@624 3436 __ movq($mem$$Address, $src$$XMMRegister);
duke@0 3437 %}
duke@0 3438
duke@0 3439 enc_class pshufd_8x8(regF dst, regF src) %{
duke@0 3440 MacroAssembler _masm(&cbuf);
duke@0 3441
duke@0 3442 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
duke@0 3443 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
duke@0 3444 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
duke@0 3445 %}
duke@0 3446
duke@0 3447 enc_class pshufd_4x16(regF dst, regF src) %{
duke@0 3448 MacroAssembler _masm(&cbuf);
duke@0 3449
duke@0 3450 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
duke@0 3451 %}
duke@0 3452
duke@0 3453 enc_class pshufd(regD dst, regD src, int mode) %{
duke@0 3454 MacroAssembler _masm(&cbuf);
duke@0 3455
duke@0 3456 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
duke@0 3457 %}
duke@0 3458
duke@0 3459 enc_class pxor(regD dst, regD src) %{
duke@0 3460 MacroAssembler _masm(&cbuf);
duke@0 3461
duke@0 3462 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
duke@0 3463 %}
duke@0 3464
duke@0 3465 enc_class mov_i2x(regD dst, rRegI src) %{
duke@0 3466 MacroAssembler _masm(&cbuf);
duke@0 3467
duke@0 3468 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
duke@0 3469 %}
duke@0 3470
duke@0 3471 // obj: object to lock
duke@0 3472 // box: box address (header location) -- killed
duke@0 3473 // tmp: rax -- killed
duke@0 3474 // scr: rbx -- killed
duke@0 3475 //
duke@0 3476 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 3477 // from i486.ad. See that file for comments.
duke@0 3478 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 3479 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 3480
duke@0 3481
duke@0 3482 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 3483 %{
duke@0 3484 Register objReg = as_Register((int)$obj$$reg);
duke@0 3485 Register boxReg = as_Register((int)$box$$reg);
duke@0 3486 Register tmpReg = as_Register($tmp$$reg);
duke@0 3487 Register scrReg = as_Register($scr$$reg);
duke@0 3488 MacroAssembler masm(&cbuf);
duke@0 3489
duke@0 3490 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 3491 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 3492 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 3493
duke@0 3494 if (_counters != NULL) {
duke@0 3495 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 3496 }
duke@0 3497 if (EmitSync & 1) {
never@304 3498 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3499 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3500 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 3501 } else
duke@0 3502 if (EmitSync & 2) {
duke@0 3503 Label DONE_LABEL;
duke@0 3504 if (UseBiasedLocking) {
duke@0 3505 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 3506 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 3507 }
never@304 3508 // QQQ was movl...
never@304 3509 masm.movptr(tmpReg, 0x1);
never@304 3510 masm.orptr(tmpReg, Address(objReg, 0));
never@304 3511 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3512 if (os::is_MP()) {
duke@0 3513 masm.lock();
duke@0 3514 }
never@304 3515 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3516 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 3517
duke@0 3518 // Recursive locking
never@304 3519 masm.subptr(tmpReg, rsp);
never@304 3520 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3521 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3522
duke@0 3523 masm.bind(DONE_LABEL);
duke@0 3524 masm.nop(); // avoid branch to branch
duke@0 3525 } else {
duke@0 3526 Label DONE_LABEL, IsInflated, Egress;
duke@0 3527
never@304 3528 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3529 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
never@304 3530 masm.jcc (Assembler::notZero, IsInflated) ;
never@304 3531
duke@0 3532 // it's stack-locked, biased or neutral
duke@0 3533 // TODO: optimize markword triage order to reduce the number of
duke@0 3534 // conditional branches in the most common cases.
duke@0 3535 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 3536 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 3537 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 3538
kvn@420 3539 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3540 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 3541 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 3542 }
duke@0 3543
never@304 3544 // was q will it destroy high?
never@304 3545 masm.orl (tmpReg, 1) ;
never@304 3546 masm.movptr(Address(boxReg, 0), tmpReg) ;
never@304 3547 if (os::is_MP()) { masm.lock(); }
never@304 3548 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3549 if (_counters != NULL) {
duke@0 3550 masm.cond_inc32(Assembler::equal,
duke@0 3551 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3552 }
duke@0 3553 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 3554
duke@0 3555 // Recursive locking
never@304 3556 masm.subptr(tmpReg, rsp);
never@304 3557 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3558 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3559 if (_counters != NULL) {
duke@0 3560 masm.cond_inc32(Assembler::equal,
duke@0 3561 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3562 }
duke@0 3563 masm.jmp (DONE_LABEL) ;
duke@0 3564
duke@0 3565 masm.bind (IsInflated) ;
duke@0 3566 // It's inflated
duke@0 3567
duke@0 3568 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 3569 // relocating (deferring) the following ST.
duke@0 3570 // We should also think about trying a CAS without having
duke@0 3571 // fetched _owner. If the CAS is successful we may
duke@0 3572 // avoid an RTO->RTS upgrade on the $line.
never@304 3573 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3574 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3575
never@304 3576 masm.mov (boxReg, tmpReg) ;
never@304 3577 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3578 masm.testptr(tmpReg, tmpReg) ;
never@304 3579 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 3580
duke@0 3581 // It's inflated and appears unlocked
never@304 3582 if (os::is_MP()) { masm.lock(); }
never@304 3583 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 3584 // Intentional fall-through into DONE_LABEL ...
duke@0 3585
duke@0 3586 masm.bind (DONE_LABEL) ;
duke@0 3587 masm.nop () ; // avoid jmp to jmp
duke@0 3588 }
duke@0 3589 %}
duke@0 3590
duke@0 3591 // obj: object to unlock
duke@0 3592 // box: box address (displaced header location), killed
duke@0 3593 // RBX: killed tmp; cannot be obj nor box
duke@0 3594 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 3595 %{
duke@0 3596
duke@0 3597 Register objReg = as_Register($obj$$reg);
duke@0 3598 Register boxReg = as_Register($box$$reg);
duke@0 3599 Register tmpReg = as_Register($tmp$$reg);
duke@0 3600 MacroAssembler masm(&cbuf);
duke@0 3601
never@304 3602 if (EmitSync & 4) {
never@304 3603 masm.cmpptr(rsp, 0) ;
duke@0 3604 } else
duke@0 3605 if (EmitSync & 8) {
duke@0 3606 Label DONE_LABEL;
duke@0 3607 if (UseBiasedLocking) {
duke@0 3608 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3609 }
duke@0 3610
duke@0 3611 // Check whether the displaced header is 0
duke@0 3612 //(=> recursive unlock)
never@304 3613 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 3614 masm.testptr(tmpReg, tmpReg);
duke@0 3615 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 3616
duke@0 3617 // If not recursive lock, reset the header to displaced header
duke@0 3618 if (os::is_MP()) {
duke@0 3619 masm.lock();
duke@0 3620 }
never@304 3621 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3622 masm.bind(DONE_LABEL);
duke@0 3623 masm.nop(); // avoid branch to branch
duke@0 3624 } else {
duke@0 3625 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 3626
kvn@420 3627 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3628 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3629 }
never@304 3630
never@304 3631 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3632 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
never@304 3633 masm.jcc (Assembler::zero, DONE_LABEL) ;
never@304 3634 masm.testl (tmpReg, 0x02) ;
never@304 3635 masm.jcc (Assembler::zero, Stacked) ;
never@304 3636
duke@0 3637 // It's inflated
never@304 3638 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3639 masm.xorptr(boxReg, r15_thread) ;
never@304 3640 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
never@304 3641 masm.jcc (Assembler::notZero, DONE_LABEL) ;
never@304 3642 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
never@304 3643 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
never@304 3644 masm.jcc (Assembler::notZero, CheckSucc) ;
never@304 3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
never@304 3646 masm.jmp (DONE_LABEL) ;
never@304 3647
never@304 3648 if ((EmitSync & 65536) == 0) {
duke@0 3649 Label LSuccess, LGoSlowPath ;
duke@0 3650 masm.bind (CheckSucc) ;
never@304 3651 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3652 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 3653
duke@0 3654 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 3655 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 3656 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 3657 // are all faster when the write buffer is populated.
never@304 3658 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3659 if (os::is_MP()) {
never@304 3660 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 3661 }
never@304 3662 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3663 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 3664
never@304 3665 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 3666 if (os::is_MP()) { masm.lock(); }
never@304 3667 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 3668 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 3669 // Intentional fall-through into slow-path
duke@0 3670
duke@0 3671 masm.bind (LGoSlowPath) ;
duke@0 3672 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 3673 masm.jmp (DONE_LABEL) ;
duke@0 3674
duke@0 3675 masm.bind (LSuccess) ;
duke@0 3676 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 3677 masm.jmp (DONE_LABEL) ;
duke@0 3678 }
duke@0 3679
never@304 3680 masm.bind (Stacked) ;
never@304 3681 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
never@304 3682 if (os::is_MP()) { masm.lock(); }
never@304 3683 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3684
duke@0 3685 if (EmitSync & 65536) {
duke@0 3686 masm.bind (CheckSucc) ;
duke@0 3687 }
duke@0 3688 masm.bind(DONE_LABEL);
duke@0 3689 if (EmitSync & 32768) {
duke@0 3690 masm.nop(); // avoid branch to branch
duke@0 3691 }
duke@0 3692 }
duke@0 3693 %}
duke@0 3694
rasbold@169 3695
duke@0 3696 enc_class enc_rethrow()
duke@0 3697 %{
twisti@1668 3698 cbuf.set_insts_mark();
duke@0 3699 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 3700 emit_d32_reloc(cbuf,
twisti@1668 3701 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 3702 runtime_call_Relocation::spec(),
duke@0 3703 RELOC_DISP32);
duke@0 3704 %}
duke@0 3705
duke@0 3706 enc_class absF_encoding(regF dst)
duke@0 3707 %{
duke@0 3708 int dstenc = $dst$$reg;
never@304 3709 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
duke@0 3710
twisti@1668 3711 cbuf.set_insts_mark();
duke@0 3712 if (dstenc >= 8) {
duke@0 3713 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3714 dstenc -= 8;
duke@0 3715 }
duke@0 3716 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3717 emit_opcode(cbuf, 0x0F);
duke@0 3718 emit_opcode(cbuf, 0x54);
duke@0 3719 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3720 emit_d32_reloc(cbuf, signmask_address);
duke@0 3721 %}
duke@0 3722
duke@0 3723 enc_class absD_encoding(regD dst)
duke@0 3724 %{
duke@0 3725 int dstenc = $dst$$reg;
never@304 3726 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
duke@0 3727
twisti@1668 3728 cbuf.set_insts_mark();
duke@0 3729 emit_opcode(cbuf, 0x66);
duke@0 3730 if (dstenc >= 8) {
duke@0 3731 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3732 dstenc -= 8;
duke@0 3733 }
duke@0 3734 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3735 emit_opcode(cbuf, 0x0F);
duke@0 3736 emit_opcode(cbuf, 0x54);
duke@0 3737 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3738 emit_d32_reloc(cbuf, signmask_address);
duke@0 3739 %}
duke@0 3740
duke@0 3741 enc_class negF_encoding(regF dst)
duke@0 3742 %{
duke@0 3743 int dstenc = $dst$$reg;
never@304 3744 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
duke@0 3745
twisti@1668 3746 cbuf.set_insts_mark();
duke@0 3747 if (dstenc >= 8) {
duke@0 3748 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3749 dstenc -= 8;
duke@0 3750 }
duke@0 3751 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3752 emit_opcode(cbuf, 0x0F);
duke@0 3753 emit_opcode(cbuf, 0x57);
duke@0 3754 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3755 emit_d32_reloc(cbuf, signflip_address);
duke@0 3756 %}
duke@0 3757
duke@0 3758 enc_class negD_encoding(regD dst)
duke@0 3759 %{
duke@0 3760 int dstenc = $dst$$reg;
never@304 3761 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3762
twisti@1668 3763 cbuf.set_insts_mark();
duke@0 3764 emit_opcode(cbuf, 0x66);
duke@0 3765 if (dstenc >= 8) {
duke@0 3766 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3767 dstenc -= 8;
duke@0 3768 }
duke@0 3769 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3770 emit_opcode(cbuf, 0x0F);
duke@0 3771 emit_opcode(cbuf, 0x57);
duke@0 3772 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3773 emit_d32_reloc(cbuf, signflip_address);
duke@0 3774 %}
duke@0 3775
duke@0 3776 enc_class f2i_fixup(rRegI dst, regF src)
duke@0 3777 %{
duke@0 3778 int dstenc = $dst$$reg;
duke@0 3779 int srcenc = $src$$reg;
duke@0 3780
duke@0 3781 // cmpl $dst, #0x80000000
duke@0 3782 if (dstenc >= 8) {
duke@0 3783 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3784 }
duke@0 3785 emit_opcode(cbuf, 0x81);
duke@0 3786 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3787 emit_d32(cbuf, 0x80000000);
duke@0 3788
duke@0 3789 // jne,s done
duke@0 3790 emit_opcode(cbuf, 0x75);
duke@0 3791 if (srcenc < 8 && dstenc < 8) {
duke@0 3792 emit_d8(cbuf, 0xF);
duke@0 3793 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3794 emit_d8(cbuf, 0x11);
duke@0 3795 } else {
duke@0 3796 emit_d8(cbuf, 0x10);
duke@0 3797 }
duke@0 3798
duke@0 3799 // subq rsp, #8
duke@0 3800 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3801 emit_opcode(cbuf, 0x83);
duke@0 3802 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3803 emit_d8(cbuf, 8);
duke@0 3804
duke@0 3805 // movss [rsp], $src
duke@0 3806 emit_opcode(cbuf, 0xF3);
duke@0 3807 if (srcenc >= 8) {
duke@0 3808 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3809 }
duke@0 3810 emit_opcode(cbuf, 0x0F);
duke@0 3811 emit_opcode(cbuf, 0x11);
duke@0 3812 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3813
duke@0 3814 // call f2i_fixup
twisti@1668 3815 cbuf.set_insts_mark();
duke@0 3816 emit_opcode(cbuf, 0xE8);
duke@0 3817 emit_d32_reloc(cbuf,
duke@0 3818 (int)
twisti@1668 3819 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4),
duke@0 3820 runtime_call_Relocation::spec(),
duke@0 3821 RELOC_DISP32);
duke@0 3822
duke@0 3823 // popq $dst
duke@0 3824 if (dstenc >= 8) {
duke@0 3825 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3826 }
duke@0 3827 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3828
duke@0 3829 // done:
duke@0 3830 %}
duke@0 3831
duke@0 3832 enc_class f2l_fixup(rRegL dst, regF src)
duke@0 3833 %{
duke@0 3834 int dstenc = $dst$$reg;
duke@0 3835 int srcenc = $src$$reg;
never@304 3836 address const_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3837
duke@0 3838 // cmpq $dst, [0x8000000000000000]
twisti@1668 3839 cbuf.set_insts_mark();
duke@0 3840 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 3841 emit_opcode(cbuf, 0x39);
duke@0 3842 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3843 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
duke@0 3844 emit_d32_reloc(cbuf, const_address);
duke@0 3845
duke@0 3846
duke@0 3847 // jne,s done
duke@0 3848 emit_opcode(cbuf, 0x75);
duke@0 3849 if (srcenc < 8 && dstenc < 8) {
duke@0 3850 emit_d8(cbuf, 0xF);
duke@0 3851 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3852 emit_d8(cbuf, 0x11);
duke@0 3853 } else {
duke@0 3854 emit_d8(cbuf, 0x10);
duke@0 3855 }
duke@0 3856
duke@0 3857 // subq rsp, #8
duke@0 3858 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3859 emit_opcode(cbuf, 0x83);
duke@0 3860 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3861 emit_d8(cbuf, 8);
duke@0 3862
duke@0 3863 // movss [rsp], $src
duke@0 3864 emit_opcode(cbuf, 0xF3);
duke@0 3865 if (srcenc >= 8) {
duke@0 3866 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3867 }
duke@0 3868 emit_opcode(cbuf, 0x0F);
duke@0 3869 emit_opcode(cbuf, 0x11);
duke@0 3870 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3871
duke@0 3872 // call f2l_fixup
twisti@1668 3873 cbuf.set_insts_mark();
duke@0 3874 emit_opcode(cbuf, 0xE8);
duke@0 3875 emit_d32_reloc(cbuf,
duke@0 3876 (int)
twisti@1668 3877 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4),
duke@0 3878 runtime_call_Relocation::spec(),
duke@0 3879 RELOC_DISP32);
duke@0 3880
duke@0 3881 // popq $dst
duke@0 3882 if (dstenc >= 8) {
duke@0 3883 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3884 }
duke@0 3885 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3886
duke@0 3887 // done:
duke@0 3888 %}
duke@0 3889
duke@0 3890 enc_class d2i_fixup(rRegI dst, regD src)
duke@0 3891 %{
duke@0 3892 int dstenc = $dst$$reg;
duke@0 3893 int srcenc = $src$$reg;
duke@0 3894
duke@0 3895 // cmpl $dst, #0x80000000
duke@0 3896 if (dstenc >= 8) {
duke@0 3897 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3898 }
duke@0 3899 emit_opcode(cbuf, 0x81);
duke@0 3900 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3901 emit_d32(cbuf, 0x80000000);