annotate src/cpu/x86/vm/x86_64.ad @ 415:4d9884b01ba6

6754519: don't emit flag fixup for NaN when condition being tested doesn't need it Reviewed-by: kvn, rasbold
author never
date Tue, 28 Oct 2008 09:31:30 -0700
parents b744678d4d71
children a1980da045cc
rev   line source
duke@0 1 //
xdono@196 2 // Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
duke@0 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 // CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 // have any questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
duke@0 135 // Word a in each register holds a Float, words ab hold a Double. We
duke@0 136 // currently do not use the SIMD capabilities, so registers cd are
duke@0 137 // unused at the moment.
duke@0 138 // XMM8-XMM15 must be encoded with REX.
duke@0 139 // Linux ABI: No register preserved across function calls
duke@0 140 // XMM0-XMM7 might hold parameters
duke@0 141 // Windows ABI: XMM6-XMM15 preserved across function calls
duke@0 142 // XMM0-XMM3 might hold parameters
duke@0 143
duke@0 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
duke@0 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
duke@0 146
duke@0 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
duke@0 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
duke@0 149
duke@0 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
duke@0 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
duke@0 152
duke@0 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
duke@0 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
duke@0 155
duke@0 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
duke@0 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
duke@0 158
duke@0 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
duke@0 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
duke@0 161
duke@0 162 #ifdef _WIN64
duke@0 163
duke@0 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
duke@0 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 166
duke@0 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
duke@0 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 169
duke@0 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
duke@0 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 172
duke@0 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
duke@0 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 175
duke@0 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
duke@0 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 178
duke@0 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
duke@0 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 181
duke@0 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
duke@0 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 184
duke@0 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
duke@0 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 187
duke@0 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
duke@0 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 190
duke@0 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
duke@0 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 193
duke@0 194 #else
duke@0 195
duke@0 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
duke@0 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 198
duke@0 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
duke@0 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 201
duke@0 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
duke@0 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 204
duke@0 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
duke@0 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 207
duke@0 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
duke@0 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 210
duke@0 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
duke@0 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 213
duke@0 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
duke@0 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 216
duke@0 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
duke@0 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 219
duke@0 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
duke@0 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 222
duke@0 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
duke@0 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 225
duke@0 226 #endif // _WIN64
duke@0 227
duke@0 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
duke@0 229
duke@0 230 // Specify priority of register selection within phases of register
duke@0 231 // allocation. Highest priority is first. A useful heuristic is to
duke@0 232 // give registers a low priority when they are required by machine
duke@0 233 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 234 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 235 // which participate in fixed calling sequences should come last.
duke@0 236 // Registers which are used as pairs must fall on an even boundary.
duke@0 237
duke@0 238 alloc_class chunk0(R10, R10_H,
duke@0 239 R11, R11_H,
duke@0 240 R8, R8_H,
duke@0 241 R9, R9_H,
duke@0 242 R12, R12_H,
duke@0 243 RCX, RCX_H,
duke@0 244 RBX, RBX_H,
duke@0 245 RDI, RDI_H,
duke@0 246 RDX, RDX_H,
duke@0 247 RSI, RSI_H,
duke@0 248 RAX, RAX_H,
duke@0 249 RBP, RBP_H,
duke@0 250 R13, R13_H,
duke@0 251 R14, R14_H,
duke@0 252 R15, R15_H,
duke@0 253 RSP, RSP_H);
duke@0 254
duke@0 255 // XXX probably use 8-15 first on Linux
duke@0 256 alloc_class chunk1(XMM0, XMM0_H,
duke@0 257 XMM1, XMM1_H,
duke@0 258 XMM2, XMM2_H,
duke@0 259 XMM3, XMM3_H,
duke@0 260 XMM4, XMM4_H,
duke@0 261 XMM5, XMM5_H,
duke@0 262 XMM6, XMM6_H,
duke@0 263 XMM7, XMM7_H,
duke@0 264 XMM8, XMM8_H,
duke@0 265 XMM9, XMM9_H,
duke@0 266 XMM10, XMM10_H,
duke@0 267 XMM11, XMM11_H,
duke@0 268 XMM12, XMM12_H,
duke@0 269 XMM13, XMM13_H,
duke@0 270 XMM14, XMM14_H,
duke@0 271 XMM15, XMM15_H);
duke@0 272
duke@0 273 alloc_class chunk2(RFLAGS);
duke@0 274
duke@0 275
duke@0 276 //----------Architecture Description Register Classes--------------------------
duke@0 277 // Several register classes are automatically defined based upon information in
duke@0 278 // this architecture description.
duke@0 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 283 //
duke@0 284
duke@0 285 // Class for all pointer registers (including RSP)
duke@0 286 reg_class any_reg(RAX, RAX_H,
duke@0 287 RDX, RDX_H,
duke@0 288 RBP, RBP_H,
duke@0 289 RDI, RDI_H,
duke@0 290 RSI, RSI_H,
duke@0 291 RCX, RCX_H,
duke@0 292 RBX, RBX_H,
duke@0 293 RSP, RSP_H,
duke@0 294 R8, R8_H,
duke@0 295 R9, R9_H,
duke@0 296 R10, R10_H,
duke@0 297 R11, R11_H,
duke@0 298 R12, R12_H,
duke@0 299 R13, R13_H,
duke@0 300 R14, R14_H,
duke@0 301 R15, R15_H);
duke@0 302
duke@0 303 // Class for all pointer registers except RSP
duke@0 304 reg_class ptr_reg(RAX, RAX_H,
duke@0 305 RDX, RDX_H,
duke@0 306 RBP, RBP_H,
duke@0 307 RDI, RDI_H,
duke@0 308 RSI, RSI_H,
duke@0 309 RCX, RCX_H,
duke@0 310 RBX, RBX_H,
duke@0 311 R8, R8_H,
duke@0 312 R9, R9_H,
duke@0 313 R10, R10_H,
duke@0 314 R11, R11_H,
duke@0 315 R13, R13_H,
duke@0 316 R14, R14_H);
duke@0 317
duke@0 318 // Class for all pointer registers except RAX and RSP
duke@0 319 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 320 RBP, RBP_H,
duke@0 321 RDI, RDI_H,
duke@0 322 RSI, RSI_H,
duke@0 323 RCX, RCX_H,
duke@0 324 RBX, RBX_H,
duke@0 325 R8, R8_H,
duke@0 326 R9, R9_H,
duke@0 327 R10, R10_H,
duke@0 328 R11, R11_H,
duke@0 329 R12, R12_H,
duke@0 330 R13, R13_H,
duke@0 331 R14, R14_H);
duke@0 332
duke@0 333 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 334 RAX, RAX_H,
duke@0 335 RDI, RDI_H,
duke@0 336 RSI, RSI_H,
duke@0 337 RCX, RCX_H,
duke@0 338 RBX, RBX_H,
duke@0 339 R8, R8_H,
duke@0 340 R9, R9_H,
duke@0 341 R10, R10_H,
duke@0 342 R11, R11_H,
duke@0 343 R12, R12_H,
duke@0 344 R13, R13_H,
duke@0 345 R14, R14_H);
duke@0 346
duke@0 347 // Class for all pointer registers except RAX, RBX and RSP
duke@0 348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 349 RBP, RBP_H,
duke@0 350 RDI, RDI_H,
duke@0 351 RSI, RSI_H,
duke@0 352 RCX, RCX_H,
duke@0 353 R8, R8_H,
duke@0 354 R9, R9_H,
duke@0 355 R10, R10_H,
duke@0 356 R11, R11_H,
duke@0 357 R12, R12_H,
duke@0 358 R13, R13_H,
duke@0 359 R14, R14_H);
duke@0 360
duke@0 361 // Singleton class for RAX pointer register
duke@0 362 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 363
duke@0 364 // Singleton class for RBX pointer register
duke@0 365 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 366
duke@0 367 // Singleton class for RSI pointer register
duke@0 368 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 369
duke@0 370 // Singleton class for RDI pointer register
duke@0 371 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 372
duke@0 373 // Singleton class for RBP pointer register
duke@0 374 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 375
duke@0 376 // Singleton class for stack pointer
duke@0 377 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 378
duke@0 379 // Singleton class for TLS pointer
duke@0 380 reg_class ptr_r15_reg(R15, R15_H);
duke@0 381
duke@0 382 // Class for all long registers (except RSP)
duke@0 383 reg_class long_reg(RAX, RAX_H,
duke@0 384 RDX, RDX_H,
duke@0 385 RBP, RBP_H,
duke@0 386 RDI, RDI_H,
duke@0 387 RSI, RSI_H,
duke@0 388 RCX, RCX_H,
duke@0 389 RBX, RBX_H,
duke@0 390 R8, R8_H,
duke@0 391 R9, R9_H,
duke@0 392 R10, R10_H,
duke@0 393 R11, R11_H,
duke@0 394 R13, R13_H,
duke@0 395 R14, R14_H);
duke@0 396
duke@0 397 // Class for all long registers except RAX, RDX (and RSP)
duke@0 398 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 399 RDI, RDI_H,
duke@0 400 RSI, RSI_H,
duke@0 401 RCX, RCX_H,
duke@0 402 RBX, RBX_H,
duke@0 403 R8, R8_H,
duke@0 404 R9, R9_H,
duke@0 405 R10, R10_H,
duke@0 406 R11, R11_H,
duke@0 407 R13, R13_H,
duke@0 408 R14, R14_H);
duke@0 409
duke@0 410 // Class for all long registers except RCX (and RSP)
duke@0 411 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 412 RDI, RDI_H,
duke@0 413 RSI, RSI_H,
duke@0 414 RAX, RAX_H,
duke@0 415 RDX, RDX_H,
duke@0 416 RBX, RBX_H,
duke@0 417 R8, R8_H,
duke@0 418 R9, R9_H,
duke@0 419 R10, R10_H,
duke@0 420 R11, R11_H,
duke@0 421 R13, R13_H,
duke@0 422 R14, R14_H);
duke@0 423
duke@0 424 // Class for all long registers except RAX (and RSP)
duke@0 425 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 426 RDX, RDX_H,
duke@0 427 RDI, RDI_H,
duke@0 428 RSI, RSI_H,
duke@0 429 RCX, RCX_H,
duke@0 430 RBX, RBX_H,
duke@0 431 R8, R8_H,
duke@0 432 R9, R9_H,
duke@0 433 R10, R10_H,
duke@0 434 R11, R11_H,
duke@0 435 R13, R13_H,
duke@0 436 R14, R14_H);
duke@0 437
duke@0 438 // Singleton class for RAX long register
duke@0 439 reg_class long_rax_reg(RAX, RAX_H);
duke@0 440
duke@0 441 // Singleton class for RCX long register
duke@0 442 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 443
duke@0 444 // Singleton class for RDX long register
duke@0 445 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 446
coleenp@113 447 // Singleton class for R12 long register
coleenp@113 448 reg_class long_r12_reg(R12, R12_H);
coleenp@113 449
duke@0 450 // Class for all int registers (except RSP)
duke@0 451 reg_class int_reg(RAX,
duke@0 452 RDX,
duke@0 453 RBP,
duke@0 454 RDI,
duke@0 455 RSI,
duke@0 456 RCX,
duke@0 457 RBX,
duke@0 458 R8,
duke@0 459 R9,
duke@0 460 R10,
duke@0 461 R11,
duke@0 462 R13,
duke@0 463 R14);
duke@0 464
duke@0 465 // Class for all int registers except RCX (and RSP)
duke@0 466 reg_class int_no_rcx_reg(RAX,
duke@0 467 RDX,
duke@0 468 RBP,
duke@0 469 RDI,
duke@0 470 RSI,
duke@0 471 RBX,
duke@0 472 R8,
duke@0 473 R9,
duke@0 474 R10,
duke@0 475 R11,
duke@0 476 R13,
duke@0 477 R14);
duke@0 478
duke@0 479 // Class for all int registers except RAX, RDX (and RSP)
duke@0 480 reg_class int_no_rax_rdx_reg(RBP,
never@304 481 RDI,
duke@0 482 RSI,
duke@0 483 RCX,
duke@0 484 RBX,
duke@0 485 R8,
duke@0 486 R9,
duke@0 487 R10,
duke@0 488 R11,
duke@0 489 R13,
duke@0 490 R14);
duke@0 491
duke@0 492 // Singleton class for RAX int register
duke@0 493 reg_class int_rax_reg(RAX);
duke@0 494
duke@0 495 // Singleton class for RBX int register
duke@0 496 reg_class int_rbx_reg(RBX);
duke@0 497
duke@0 498 // Singleton class for RCX int register
duke@0 499 reg_class int_rcx_reg(RCX);
duke@0 500
duke@0 501 // Singleton class for RCX int register
duke@0 502 reg_class int_rdx_reg(RDX);
duke@0 503
duke@0 504 // Singleton class for RCX int register
duke@0 505 reg_class int_rdi_reg(RDI);
duke@0 506
duke@0 507 // Singleton class for instruction pointer
duke@0 508 // reg_class ip_reg(RIP);
duke@0 509
duke@0 510 // Singleton class for condition codes
duke@0 511 reg_class int_flags(RFLAGS);
duke@0 512
duke@0 513 // Class for all float registers
duke@0 514 reg_class float_reg(XMM0,
duke@0 515 XMM1,
duke@0 516 XMM2,
duke@0 517 XMM3,
duke@0 518 XMM4,
duke@0 519 XMM5,
duke@0 520 XMM6,
duke@0 521 XMM7,
duke@0 522 XMM8,
duke@0 523 XMM9,
duke@0 524 XMM10,
duke@0 525 XMM11,
duke@0 526 XMM12,
duke@0 527 XMM13,
duke@0 528 XMM14,
duke@0 529 XMM15);
duke@0 530
duke@0 531 // Class for all double registers
duke@0 532 reg_class double_reg(XMM0, XMM0_H,
duke@0 533 XMM1, XMM1_H,
duke@0 534 XMM2, XMM2_H,
duke@0 535 XMM3, XMM3_H,
duke@0 536 XMM4, XMM4_H,
duke@0 537 XMM5, XMM5_H,
duke@0 538 XMM6, XMM6_H,
duke@0 539 XMM7, XMM7_H,
duke@0 540 XMM8, XMM8_H,
duke@0 541 XMM9, XMM9_H,
duke@0 542 XMM10, XMM10_H,
duke@0 543 XMM11, XMM11_H,
duke@0 544 XMM12, XMM12_H,
duke@0 545 XMM13, XMM13_H,
duke@0 546 XMM14, XMM14_H,
duke@0 547 XMM15, XMM15_H);
duke@0 548 %}
duke@0 549
duke@0 550
duke@0 551 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 552 // This is a block of C++ code which provides values, functions, and
duke@0 553 // definitions necessary in the rest of the architecture description
duke@0 554 source %{
never@304 555 #define RELOC_IMM64 Assembler::imm_operand
duke@0 556 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 557
duke@0 558 #define __ _masm.
duke@0 559
duke@0 560 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 561 // from the start of the call to the point where the return address
duke@0 562 // will point.
duke@0 563 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 564 {
duke@0 565 return 5; // 5 bytes from start of call to where return address points
duke@0 566 }
duke@0 567
duke@0 568 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 569 {
duke@0 570 return 15; // 15 bytes from start of call to where return address points
duke@0 571 }
duke@0 572
duke@0 573 // In os_cpu .ad file
duke@0 574 // int MachCallRuntimeNode::ret_addr_offset()
duke@0 575
duke@0 576 // Indicate if the safepoint node needs the polling page as an input.
duke@0 577 // Since amd64 does not have absolute addressing but RIP-relative
duke@0 578 // addressing and the polling page is within 2G, it doesn't.
duke@0 579 bool SafePointNode::needs_polling_address_input()
duke@0 580 {
duke@0 581 return false;
duke@0 582 }
duke@0 583
duke@0 584 //
duke@0 585 // Compute padding required for nodes which need alignment
duke@0 586 //
duke@0 587
duke@0 588 // The address of the call instruction needs to be 4-byte aligned to
duke@0 589 // ensure that it does not span a cache line so that it can be patched.
duke@0 590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 591 {
duke@0 592 current_offset += 1; // skip call opcode byte
duke@0 593 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 594 }
duke@0 595
duke@0 596 // The address of the call instruction needs to be 4-byte aligned to
duke@0 597 // ensure that it does not span a cache line so that it can be patched.
duke@0 598 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 599 {
duke@0 600 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 601 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 602 }
duke@0 603
duke@0 604 #ifndef PRODUCT
duke@0 605 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 606 {
duke@0 607 st->print("INT3");
duke@0 608 }
duke@0 609 #endif
duke@0 610
duke@0 611 // EMIT_RM()
duke@0 612 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
duke@0 613 {
duke@0 614 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
duke@0 615 *(cbuf.code_end()) = c;
duke@0 616 cbuf.set_code_end(cbuf.code_end() + 1);
duke@0 617 }
duke@0 618
duke@0 619 // EMIT_CC()
duke@0 620 void emit_cc(CodeBuffer &cbuf, int f1, int f2)
duke@0 621 {
duke@0 622 unsigned char c = (unsigned char) (f1 | f2);
duke@0 623 *(cbuf.code_end()) = c;
duke@0 624 cbuf.set_code_end(cbuf.code_end() + 1);
duke@0 625 }
duke@0 626
duke@0 627 // EMIT_OPCODE()
duke@0 628 void emit_opcode(CodeBuffer &cbuf, int code)
duke@0 629 {
duke@0 630 *(cbuf.code_end()) = (unsigned char) code;
duke@0 631 cbuf.set_code_end(cbuf.code_end() + 1);
duke@0 632 }
duke@0 633
duke@0 634 // EMIT_OPCODE() w/ relocation information
duke@0 635 void emit_opcode(CodeBuffer &cbuf,
duke@0 636 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 637 {
duke@0 638 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format);
duke@0 639 emit_opcode(cbuf, code);
duke@0 640 }
duke@0 641
duke@0 642 // EMIT_D8()
duke@0 643 void emit_d8(CodeBuffer &cbuf, int d8)
duke@0 644 {
duke@0 645 *(cbuf.code_end()) = (unsigned char) d8;
duke@0 646 cbuf.set_code_end(cbuf.code_end() + 1);
duke@0 647 }
duke@0 648
duke@0 649 // EMIT_D16()
duke@0 650 void emit_d16(CodeBuffer &cbuf, int d16)
duke@0 651 {
duke@0 652 *((short *)(cbuf.code_end())) = d16;
duke@0 653 cbuf.set_code_end(cbuf.code_end() + 2);
duke@0 654 }
duke@0 655
duke@0 656 // EMIT_D32()
duke@0 657 void emit_d32(CodeBuffer &cbuf, int d32)
duke@0 658 {
duke@0 659 *((int *)(cbuf.code_end())) = d32;
duke@0 660 cbuf.set_code_end(cbuf.code_end() + 4);
duke@0 661 }
duke@0 662
duke@0 663 // EMIT_D64()
duke@0 664 void emit_d64(CodeBuffer &cbuf, int64_t d64)
duke@0 665 {
duke@0 666 *((int64_t*) (cbuf.code_end())) = d64;
duke@0 667 cbuf.set_code_end(cbuf.code_end() + 8);
duke@0 668 }
duke@0 669
duke@0 670 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 671 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 672 int d32,
duke@0 673 relocInfo::relocType reloc,
duke@0 674 int format)
duke@0 675 {
duke@0 676 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
duke@0 677 cbuf.relocate(cbuf.inst_mark(), reloc, format);
duke@0 678
duke@0 679 *((int*) (cbuf.code_end())) = d32;
duke@0 680 cbuf.set_code_end(cbuf.code_end() + 4);
duke@0 681 }
duke@0 682
duke@0 683 // emit 32 bit value and construct relocation entry from RelocationHolder
duke@0 684 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 685 int d32,
duke@0 686 RelocationHolder const& rspec,
duke@0 687 int format)
duke@0 688 {
duke@0 689 #ifdef ASSERT
duke@0 690 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 691 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
duke@0 692 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code");
duke@0 693 }
duke@0 694 #endif
duke@0 695 cbuf.relocate(cbuf.inst_mark(), rspec, format);
duke@0 696
duke@0 697 *((int* )(cbuf.code_end())) = d32;
duke@0 698 cbuf.set_code_end(cbuf.code_end() + 4);
duke@0 699 }
duke@0 700
duke@0 701 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
duke@0 702 address next_ip = cbuf.code_end() + 4;
duke@0 703 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 704 external_word_Relocation::spec(addr),
duke@0 705 RELOC_DISP32);
duke@0 706 }
duke@0 707
duke@0 708
duke@0 709 // emit 64 bit value and construct relocation entry from relocInfo::relocType
duke@0 710 void emit_d64_reloc(CodeBuffer& cbuf,
duke@0 711 int64_t d64,
duke@0 712 relocInfo::relocType reloc,
duke@0 713 int format)
duke@0 714 {
duke@0 715 cbuf.relocate(cbuf.inst_mark(), reloc, format);
duke@0 716
duke@0 717 *((int64_t*) (cbuf.code_end())) = d64;
duke@0 718 cbuf.set_code_end(cbuf.code_end() + 8);
duke@0 719 }
duke@0 720
duke@0 721 // emit 64 bit value and construct relocation entry from RelocationHolder
duke@0 722 void emit_d64_reloc(CodeBuffer& cbuf,
duke@0 723 int64_t d64,
duke@0 724 RelocationHolder const& rspec,
duke@0 725 int format)
duke@0 726 {
duke@0 727 #ifdef ASSERT
duke@0 728 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 729 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
duke@0 730 assert(oop(d64)->is_oop() && oop(d64)->is_perm(),
duke@0 731 "cannot embed non-perm oops in code");
duke@0 732 }
duke@0 733 #endif
duke@0 734 cbuf.relocate(cbuf.inst_mark(), rspec, format);
duke@0 735
duke@0 736 *((int64_t*) (cbuf.code_end())) = d64;
duke@0 737 cbuf.set_code_end(cbuf.code_end() + 8);
duke@0 738 }
duke@0 739
duke@0 740 // Access stack slot for load or store
duke@0 741 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 742 {
duke@0 743 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 744 if (-0x80 <= disp && disp < 0x80) {
duke@0 745 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 746 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 747 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 748 } else {
duke@0 749 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 750 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 751 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 752 }
duke@0 753 }
duke@0 754
duke@0 755 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 756 void encode_RegMem(CodeBuffer &cbuf,
duke@0 757 int reg,
duke@0 758 int base, int index, int scale, int disp, bool disp_is_oop)
duke@0 759 {
duke@0 760 assert(!disp_is_oop, "cannot have disp");
duke@0 761 int regenc = reg & 7;
duke@0 762 int baseenc = base & 7;
duke@0 763 int indexenc = index & 7;
duke@0 764
duke@0 765 // There is no index & no scale, use form without SIB byte
duke@0 766 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 767 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 768 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 769 emit_rm(cbuf, 0x0, regenc, baseenc); // *
duke@0 770 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 771 // If 8-bit displacement, mode 0x1
duke@0 772 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 773 emit_d8(cbuf, disp);
duke@0 774 } else {
duke@0 775 // If 32-bit displacement
duke@0 776 if (base == -1) { // Special flag for absolute address
duke@0 777 emit_rm(cbuf, 0x0, regenc, 0x5); // *
duke@0 778 if (disp_is_oop) {
duke@0 779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 780 } else {
duke@0 781 emit_d32(cbuf, disp);
duke@0 782 }
duke@0 783 } else {
duke@0 784 // Normal base + offset
duke@0 785 emit_rm(cbuf, 0x2, regenc, baseenc); // *
duke@0 786 if (disp_is_oop) {
duke@0 787 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 788 } else {
duke@0 789 emit_d32(cbuf, disp);
duke@0 790 }
duke@0 791 }
duke@0 792 }
duke@0 793 } else {
duke@0 794 // Else, encode with the SIB byte
duke@0 795 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 796 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 797 // If no displacement
duke@0 798 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 799 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 800 } else {
duke@0 801 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 802 // If 8-bit displacement, mode 0x1
duke@0 803 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 804 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 805 emit_d8(cbuf, disp);
duke@0 806 } else {
duke@0 807 // If 32-bit displacement
duke@0 808 if (base == 0x04 ) {
duke@0 809 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 810 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 811 } else {
duke@0 812 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 813 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 814 }
duke@0 815 if (disp_is_oop) {
duke@0 816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 817 } else {
duke@0 818 emit_d32(cbuf, disp);
duke@0 819 }
duke@0 820 }
duke@0 821 }
duke@0 822 }
duke@0 823 }
duke@0 824
duke@0 825 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
duke@0 826 {
duke@0 827 if (dstenc != srcenc) {
duke@0 828 if (dstenc < 8) {
duke@0 829 if (srcenc >= 8) {
duke@0 830 emit_opcode(cbuf, Assembler::REX_B);
duke@0 831 srcenc -= 8;
duke@0 832 }
duke@0 833 } else {
duke@0 834 if (srcenc < 8) {
duke@0 835 emit_opcode(cbuf, Assembler::REX_R);
duke@0 836 } else {
duke@0 837 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 838 srcenc -= 8;
duke@0 839 }
duke@0 840 dstenc -= 8;
duke@0 841 }
duke@0 842
duke@0 843 emit_opcode(cbuf, 0x8B);
duke@0 844 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 845 }
duke@0 846 }
duke@0 847
duke@0 848 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
duke@0 849 if( dst_encoding == src_encoding ) {
duke@0 850 // reg-reg copy, use an empty encoding
duke@0 851 } else {
duke@0 852 MacroAssembler _masm(&cbuf);
duke@0 853
duke@0 854 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
duke@0 855 }
duke@0 856 }
duke@0 857
duke@0 858
duke@0 859 //=============================================================================
duke@0 860 #ifndef PRODUCT
duke@0 861 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 862 {
duke@0 863 Compile* C = ra_->C;
duke@0 864
duke@0 865 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 866 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 867 // Remove wordSize for return adr already pushed
duke@0 868 // and another for the RBP we are going to save
duke@0 869 framesize -= 2*wordSize;
duke@0 870 bool need_nop = true;
duke@0 871
duke@0 872 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 873 // We require that their callers must bang for them. But be
duke@0 874 // careful, because some VM calls (such as call site linkage) can
duke@0 875 // use several kilobytes of stack. But the stack safety zone should
duke@0 876 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 877 if (C->need_stack_bang(framesize)) {
duke@0 878 st->print_cr("# stack bang"); st->print("\t");
duke@0 879 need_nop = false;
duke@0 880 }
duke@0 881 st->print_cr("pushq rbp"); st->print("\t");
duke@0 882
duke@0 883 if (VerifyStackAtCalls) {
duke@0 884 // Majik cookie to verify stack depth
duke@0 885 st->print_cr("pushq 0xffffffffbadb100d"
duke@0 886 "\t# Majik cookie for stack depth check");
duke@0 887 st->print("\t");
duke@0 888 framesize -= wordSize; // Remove 2 for cookie
duke@0 889 need_nop = false;
duke@0 890 }
duke@0 891
duke@0 892 if (framesize) {
duke@0 893 st->print("subq rsp, #%d\t# Create frame", framesize);
duke@0 894 if (framesize < 0x80 && need_nop) {
duke@0 895 st->print("\n\tnop\t# nop for patch_verified_entry");
duke@0 896 }
duke@0 897 }
duke@0 898 }
duke@0 899 #endif
duke@0 900
duke@0 901 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 902 {
duke@0 903 Compile* C = ra_->C;
duke@0 904
duke@0 905 // WARNING: Initial instruction MUST be 5 bytes or longer so that
duke@0 906 // NativeJump::patch_verified_entry will be able to patch out the entry
duke@0 907 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
duke@0 908 // depth is ok at 5 bytes, the frame allocation can be either 3 or
duke@0 909 // 6 bytes. So if we don't do the fldcw or the push then we must
duke@0 910 // use the 6 byte frame allocation even if we have no frame. :-(
duke@0 911 // If method sets FPU control word do it now
duke@0 912
duke@0 913 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 914 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 915 // Remove wordSize for return adr already pushed
duke@0 916 // and another for the RBP we are going to save
duke@0 917 framesize -= 2*wordSize;
duke@0 918 bool need_nop = true;
duke@0 919
duke@0 920 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 921 // We require that their callers must bang for them. But be
duke@0 922 // careful, because some VM calls (such as call site linkage) can
duke@0 923 // use several kilobytes of stack. But the stack safety zone should
duke@0 924 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 925 if (C->need_stack_bang(framesize)) {
duke@0 926 MacroAssembler masm(&cbuf);
duke@0 927 masm.generate_stack_overflow_check(framesize);
duke@0 928 need_nop = false;
duke@0 929 }
duke@0 930
duke@0 931 // We always push rbp so that on return to interpreter rbp will be
duke@0 932 // restored correctly and we can correct the stack.
duke@0 933 emit_opcode(cbuf, 0x50 | RBP_enc);
duke@0 934
duke@0 935 if (VerifyStackAtCalls) {
duke@0 936 // Majik cookie to verify stack depth
duke@0 937 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
duke@0 938 emit_d32(cbuf, 0xbadb100d);
duke@0 939 framesize -= wordSize; // Remove 2 for cookie
duke@0 940 need_nop = false;
duke@0 941 }
duke@0 942
duke@0 943 if (framesize) {
duke@0 944 emit_opcode(cbuf, Assembler::REX_W);
duke@0 945 if (framesize < 0x80) {
duke@0 946 emit_opcode(cbuf, 0x83); // sub SP,#framesize
duke@0 947 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 948 emit_d8(cbuf, framesize);
duke@0 949 if (need_nop) {
duke@0 950 emit_opcode(cbuf, 0x90); // nop
duke@0 951 }
duke@0 952 } else {
duke@0 953 emit_opcode(cbuf, 0x81); // sub SP,#framesize
duke@0 954 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 955 emit_d32(cbuf, framesize);
duke@0 956 }
duke@0 957 }
duke@0 958
duke@0 959 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
duke@0 960
duke@0 961 #ifdef ASSERT
duke@0 962 if (VerifyStackAtCalls) {
duke@0 963 Label L;
duke@0 964 MacroAssembler masm(&cbuf);
never@304 965 masm.push(rax);
never@304 966 masm.mov(rax, rsp);
never@304 967 masm.andptr(rax, StackAlignmentInBytes-1);
never@304 968 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
never@304 969 masm.pop(rax);
duke@0 970 masm.jcc(Assembler::equal, L);
duke@0 971 masm.stop("Stack is not properly aligned!");
duke@0 972 masm.bind(L);
duke@0 973 }
duke@0 974 #endif
duke@0 975 }
duke@0 976
duke@0 977 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 978 {
duke@0 979 return MachNode::size(ra_); // too many variables; just compute it
duke@0 980 // the hard way
duke@0 981 }
duke@0 982
duke@0 983 int MachPrologNode::reloc() const
duke@0 984 {
duke@0 985 return 0; // a large enough number
duke@0 986 }
duke@0 987
duke@0 988 //=============================================================================
duke@0 989 #ifndef PRODUCT
duke@0 990 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 991 {
duke@0 992 Compile* C = ra_->C;
duke@0 993 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 994 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 995 // Remove word for return adr already pushed
duke@0 996 // and RBP
duke@0 997 framesize -= 2*wordSize;
duke@0 998
duke@0 999 if (framesize) {
duke@0 1000 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
duke@0 1001 st->print("\t");
duke@0 1002 }
duke@0 1003
duke@0 1004 st->print_cr("popq\trbp");
duke@0 1005 if (do_polling() && C->is_method_compilation()) {
duke@0 1006 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
duke@0 1007 "# Safepoint: poll for GC");
duke@0 1008 st->print("\t");
duke@0 1009 }
duke@0 1010 }
duke@0 1011 #endif
duke@0 1012
duke@0 1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1014 {
duke@0 1015 Compile* C = ra_->C;
duke@0 1016 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1018 // Remove word for return adr already pushed
duke@0 1019 // and RBP
duke@0 1020 framesize -= 2*wordSize;
duke@0 1021
duke@0 1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 1023
duke@0 1024 if (framesize) {
duke@0 1025 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1026 if (framesize < 0x80) {
duke@0 1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1029 emit_d8(cbuf, framesize);
duke@0 1030 } else {
duke@0 1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1033 emit_d32(cbuf, framesize);
duke@0 1034 }
duke@0 1035 }
duke@0 1036
duke@0 1037 // popq rbp
duke@0 1038 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 1039
duke@0 1040 if (do_polling() && C->is_method_compilation()) {
duke@0 1041 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
duke@0 1042 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 1043 cbuf.set_inst_mark();
duke@0 1044 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX
duke@0 1045 emit_opcode(cbuf, 0x85); // testl
duke@0 1046 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
duke@0 1047 // cbuf.inst_mark() is beginning of instruction
duke@0 1048 emit_d32_reloc(cbuf, os::get_polling_page());
duke@0 1049 // relocInfo::poll_return_type,
duke@0 1050 }
duke@0 1051 }
duke@0 1052
duke@0 1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 1054 {
duke@0 1055 Compile* C = ra_->C;
duke@0 1056 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1058 // Remove word for return adr already pushed
duke@0 1059 // and RBP
duke@0 1060 framesize -= 2*wordSize;
duke@0 1061
duke@0 1062 uint size = 0;
duke@0 1063
duke@0 1064 if (do_polling() && C->is_method_compilation()) {
duke@0 1065 size += 6;
duke@0 1066 }
duke@0 1067
duke@0 1068 // count popq rbp
duke@0 1069 size++;
duke@0 1070
duke@0 1071 if (framesize) {
duke@0 1072 if (framesize < 0x80) {
duke@0 1073 size += 4;
duke@0 1074 } else if (framesize) {
duke@0 1075 size += 7;
duke@0 1076 }
duke@0 1077 }
duke@0 1078
duke@0 1079 return size;
duke@0 1080 }
duke@0 1081
duke@0 1082 int MachEpilogNode::reloc() const
duke@0 1083 {
duke@0 1084 return 2; // a large enough number
duke@0 1085 }
duke@0 1086
duke@0 1087 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1088 {
duke@0 1089 return MachNode::pipeline_class();
duke@0 1090 }
duke@0 1091
duke@0 1092 int MachEpilogNode::safepoint_offset() const
duke@0 1093 {
duke@0 1094 return 0;
duke@0 1095 }
duke@0 1096
duke@0 1097 //=============================================================================
duke@0 1098
duke@0 1099 enum RC {
duke@0 1100 rc_bad,
duke@0 1101 rc_int,
duke@0 1102 rc_float,
duke@0 1103 rc_stack
duke@0 1104 };
duke@0 1105
duke@0 1106 static enum RC rc_class(OptoReg::Name reg)
duke@0 1107 {
duke@0 1108 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1109
duke@0 1110 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1111
duke@0 1112 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1113
duke@0 1114 if (r->is_Register()) return rc_int;
duke@0 1115
duke@0 1116 assert(r->is_XMMRegister(), "must be");
duke@0 1117 return rc_float;
duke@0 1118 }
duke@0 1119
duke@0 1120 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1121 PhaseRegAlloc* ra_,
duke@0 1122 bool do_size,
duke@0 1123 outputStream* st) const
duke@0 1124 {
duke@0 1125
duke@0 1126 // Get registers to move
duke@0 1127 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1128 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1129 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1130 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1131
duke@0 1132 enum RC src_second_rc = rc_class(src_second);
duke@0 1133 enum RC src_first_rc = rc_class(src_first);
duke@0 1134 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1135 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1136
duke@0 1137 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1138 "must move at least 1 register" );
duke@0 1139
duke@0 1140 if (src_first == dst_first && src_second == dst_second) {
duke@0 1141 // Self copy, no move
duke@0 1142 return 0;
duke@0 1143 } else if (src_first_rc == rc_stack) {
duke@0 1144 // mem ->
duke@0 1145 if (dst_first_rc == rc_stack) {
duke@0 1146 // mem -> mem
duke@0 1147 assert(src_second != dst_first, "overlap");
duke@0 1148 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1149 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1150 // 64-bit
duke@0 1151 int src_offset = ra_->reg2offset(src_first);
duke@0 1152 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1153 if (cbuf) {
duke@0 1154 emit_opcode(*cbuf, 0xFF);
duke@0 1155 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
duke@0 1156
duke@0 1157 emit_opcode(*cbuf, 0x8F);
duke@0 1158 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
duke@0 1159
duke@0 1160 #ifndef PRODUCT
duke@0 1161 } else if (!do_size) {
duke@0 1162 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
duke@0 1163 "popq [rsp + #%d]",
duke@0 1164 src_offset,
duke@0 1165 dst_offset);
duke@0 1166 #endif
duke@0 1167 }
duke@0 1168 return
duke@0 1169 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
duke@0 1170 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
duke@0 1171 } else {
duke@0 1172 // 32-bit
duke@0 1173 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1174 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1175 // No pushl/popl, so:
duke@0 1176 int src_offset = ra_->reg2offset(src_first);
duke@0 1177 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1178 if (cbuf) {
duke@0 1179 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1180 emit_opcode(*cbuf, 0x89);
duke@0 1181 emit_opcode(*cbuf, 0x44);
duke@0 1182 emit_opcode(*cbuf, 0x24);
duke@0 1183 emit_opcode(*cbuf, 0xF8);
duke@0 1184
duke@0 1185 emit_opcode(*cbuf, 0x8B);
duke@0 1186 encode_RegMem(*cbuf,
duke@0 1187 RAX_enc,
duke@0 1188 RSP_enc, 0x4, 0, src_offset,
duke@0 1189 false);
duke@0 1190
duke@0 1191 emit_opcode(*cbuf, 0x89);
duke@0 1192 encode_RegMem(*cbuf,
duke@0 1193 RAX_enc,
duke@0 1194 RSP_enc, 0x4, 0, dst_offset,
duke@0 1195 false);
duke@0 1196
duke@0 1197 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1198 emit_opcode(*cbuf, 0x8B);
duke@0 1199 emit_opcode(*cbuf, 0x44);
duke@0 1200 emit_opcode(*cbuf, 0x24);
duke@0 1201 emit_opcode(*cbuf, 0xF8);
duke@0 1202
duke@0 1203 #ifndef PRODUCT
duke@0 1204 } else if (!do_size) {
duke@0 1205 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
duke@0 1206 "movl rax, [rsp + #%d]\n\t"
duke@0 1207 "movl [rsp + #%d], rax\n\t"
duke@0 1208 "movq rax, [rsp - #8]",
duke@0 1209 src_offset,
duke@0 1210 dst_offset);
duke@0 1211 #endif
duke@0 1212 }
duke@0 1213 return
duke@0 1214 5 + // movq
duke@0 1215 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1216 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1217 5; // movq
duke@0 1218 }
duke@0 1219 } else if (dst_first_rc == rc_int) {
duke@0 1220 // mem -> gpr
duke@0 1221 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1223 // 64-bit
duke@0 1224 int offset = ra_->reg2offset(src_first);
duke@0 1225 if (cbuf) {
duke@0 1226 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1227 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1228 } else {
duke@0 1229 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1230 }
duke@0 1231 emit_opcode(*cbuf, 0x8B);
duke@0 1232 encode_RegMem(*cbuf,
duke@0 1233 Matcher::_regEncode[dst_first],
duke@0 1234 RSP_enc, 0x4, 0, offset,
duke@0 1235 false);
duke@0 1236 #ifndef PRODUCT
duke@0 1237 } else if (!do_size) {
duke@0 1238 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1239 Matcher::regName[dst_first],
duke@0 1240 offset);
duke@0 1241 #endif
duke@0 1242 }
duke@0 1243 return
duke@0 1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1245 } else {
duke@0 1246 // 32-bit
duke@0 1247 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1248 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1249 int offset = ra_->reg2offset(src_first);
duke@0 1250 if (cbuf) {
duke@0 1251 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1252 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1253 }
duke@0 1254 emit_opcode(*cbuf, 0x8B);
duke@0 1255 encode_RegMem(*cbuf,
duke@0 1256 Matcher::_regEncode[dst_first],
duke@0 1257 RSP_enc, 0x4, 0, offset,
duke@0 1258 false);
duke@0 1259 #ifndef PRODUCT
duke@0 1260 } else if (!do_size) {
duke@0 1261 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1262 Matcher::regName[dst_first],
duke@0 1263 offset);
duke@0 1264 #endif
duke@0 1265 }
duke@0 1266 return
duke@0 1267 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1268 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1269 ? 3
duke@0 1270 : 4); // REX
duke@0 1271 }
duke@0 1272 } else if (dst_first_rc == rc_float) {
duke@0 1273 // mem-> xmm
duke@0 1274 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1275 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1276 // 64-bit
duke@0 1277 int offset = ra_->reg2offset(src_first);
duke@0 1278 if (cbuf) {
duke@0 1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 1280 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1281 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1282 }
duke@0 1283 emit_opcode(*cbuf, 0x0F);
duke@0 1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 1285 encode_RegMem(*cbuf,
duke@0 1286 Matcher::_regEncode[dst_first],
duke@0 1287 RSP_enc, 0x4, 0, offset,
duke@0 1288 false);
duke@0 1289 #ifndef PRODUCT
duke@0 1290 } else if (!do_size) {
duke@0 1291 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1292 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1293 Matcher::regName[dst_first],
duke@0 1294 offset);
duke@0 1295 #endif
duke@0 1296 }
duke@0 1297 return
duke@0 1298 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1299 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1300 ? 5
duke@0 1301 : 6); // REX
duke@0 1302 } else {
duke@0 1303 // 32-bit
duke@0 1304 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1305 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1306 int offset = ra_->reg2offset(src_first);
duke@0 1307 if (cbuf) {
duke@0 1308 emit_opcode(*cbuf, 0xF3);
duke@0 1309 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1310 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1311 }
duke@0 1312 emit_opcode(*cbuf, 0x0F);
duke@0 1313 emit_opcode(*cbuf, 0x10);
duke@0 1314 encode_RegMem(*cbuf,
duke@0 1315 Matcher::_regEncode[dst_first],
duke@0 1316 RSP_enc, 0x4, 0, offset,
duke@0 1317 false);
duke@0 1318 #ifndef PRODUCT
duke@0 1319 } else if (!do_size) {
duke@0 1320 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1321 Matcher::regName[dst_first],
duke@0 1322 offset);
duke@0 1323 #endif
duke@0 1324 }
duke@0 1325 return
duke@0 1326 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1327 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1328 ? 5
duke@0 1329 : 6); // REX
duke@0 1330 }
duke@0 1331 }
duke@0 1332 } else if (src_first_rc == rc_int) {
duke@0 1333 // gpr ->
duke@0 1334 if (dst_first_rc == rc_stack) {
duke@0 1335 // gpr -> mem
duke@0 1336 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1337 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1338 // 64-bit
duke@0 1339 int offset = ra_->reg2offset(dst_first);
duke@0 1340 if (cbuf) {
duke@0 1341 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1342 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1343 } else {
duke@0 1344 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1345 }
duke@0 1346 emit_opcode(*cbuf, 0x89);
duke@0 1347 encode_RegMem(*cbuf,
duke@0 1348 Matcher::_regEncode[src_first],
duke@0 1349 RSP_enc, 0x4, 0, offset,
duke@0 1350 false);
duke@0 1351 #ifndef PRODUCT
duke@0 1352 } else if (!do_size) {
duke@0 1353 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1354 offset,
duke@0 1355 Matcher::regName[src_first]);
duke@0 1356 #endif
duke@0 1357 }
duke@0 1358 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1359 } else {
duke@0 1360 // 32-bit
duke@0 1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1363 int offset = ra_->reg2offset(dst_first);
duke@0 1364 if (cbuf) {
duke@0 1365 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1366 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1367 }
duke@0 1368 emit_opcode(*cbuf, 0x89);
duke@0 1369 encode_RegMem(*cbuf,
duke@0 1370 Matcher::_regEncode[src_first],
duke@0 1371 RSP_enc, 0x4, 0, offset,
duke@0 1372 false);
duke@0 1373 #ifndef PRODUCT
duke@0 1374 } else if (!do_size) {
duke@0 1375 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1376 offset,
duke@0 1377 Matcher::regName[src_first]);
duke@0 1378 #endif
duke@0 1379 }
duke@0 1380 return
duke@0 1381 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1382 ((Matcher::_regEncode[src_first] < 8)
duke@0 1383 ? 3
duke@0 1384 : 4); // REX
duke@0 1385 }
duke@0 1386 } else if (dst_first_rc == rc_int) {
duke@0 1387 // gpr -> gpr
duke@0 1388 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1389 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1390 // 64-bit
duke@0 1391 if (cbuf) {
duke@0 1392 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1393 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1394 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1395 } else {
duke@0 1396 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1397 }
duke@0 1398 } else {
duke@0 1399 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1400 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1401 } else {
duke@0 1402 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1403 }
duke@0 1404 }
duke@0 1405 emit_opcode(*cbuf, 0x8B);
duke@0 1406 emit_rm(*cbuf, 0x3,
duke@0 1407 Matcher::_regEncode[dst_first] & 7,
duke@0 1408 Matcher::_regEncode[src_first] & 7);
duke@0 1409 #ifndef PRODUCT
duke@0 1410 } else if (!do_size) {
duke@0 1411 st->print("movq %s, %s\t# spill",
duke@0 1412 Matcher::regName[dst_first],
duke@0 1413 Matcher::regName[src_first]);
duke@0 1414 #endif
duke@0 1415 }
duke@0 1416 return 3; // REX
duke@0 1417 } else {
duke@0 1418 // 32-bit
duke@0 1419 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1420 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1421 if (cbuf) {
duke@0 1422 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1423 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1424 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1425 }
duke@0 1426 } else {
duke@0 1427 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1428 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1429 } else {
duke@0 1430 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1431 }
duke@0 1432 }
duke@0 1433 emit_opcode(*cbuf, 0x8B);
duke@0 1434 emit_rm(*cbuf, 0x3,
duke@0 1435 Matcher::_regEncode[dst_first] & 7,
duke@0 1436 Matcher::_regEncode[src_first] & 7);
duke@0 1437 #ifndef PRODUCT
duke@0 1438 } else if (!do_size) {
duke@0 1439 st->print("movl %s, %s\t# spill",
duke@0 1440 Matcher::regName[dst_first],
duke@0 1441 Matcher::regName[src_first]);
duke@0 1442 #endif
duke@0 1443 }
duke@0 1444 return
duke@0 1445 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1446 ? 2
duke@0 1447 : 3; // REX
duke@0 1448 }
duke@0 1449 } else if (dst_first_rc == rc_float) {
duke@0 1450 // gpr -> xmm
duke@0 1451 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1453 // 64-bit
duke@0 1454 if (cbuf) {
duke@0 1455 emit_opcode(*cbuf, 0x66);
duke@0 1456 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1457 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1458 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1459 } else {
duke@0 1460 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1461 }
duke@0 1462 } else {
duke@0 1463 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1464 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1465 } else {
duke@0 1466 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1467 }
duke@0 1468 }
duke@0 1469 emit_opcode(*cbuf, 0x0F);
duke@0 1470 emit_opcode(*cbuf, 0x6E);
duke@0 1471 emit_rm(*cbuf, 0x3,
duke@0 1472 Matcher::_regEncode[dst_first] & 7,
duke@0 1473 Matcher::_regEncode[src_first] & 7);
duke@0 1474 #ifndef PRODUCT
duke@0 1475 } else if (!do_size) {
duke@0 1476 st->print("movdq %s, %s\t# spill",
duke@0 1477 Matcher::regName[dst_first],
duke@0 1478 Matcher::regName[src_first]);
duke@0 1479 #endif
duke@0 1480 }
duke@0 1481 return 5; // REX
duke@0 1482 } else {
duke@0 1483 // 32-bit
duke@0 1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1486 if (cbuf) {
duke@0 1487 emit_opcode(*cbuf, 0x66);
duke@0 1488 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1489 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1490 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1491 }
duke@0 1492 } else {
duke@0 1493 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1494 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1495 } else {
duke@0 1496 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1497 }
duke@0 1498 }
duke@0 1499 emit_opcode(*cbuf, 0x0F);
duke@0 1500 emit_opcode(*cbuf, 0x6E);
duke@0 1501 emit_rm(*cbuf, 0x3,
duke@0 1502 Matcher::_regEncode[dst_first] & 7,
duke@0 1503 Matcher::_regEncode[src_first] & 7);
duke@0 1504 #ifndef PRODUCT
duke@0 1505 } else if (!do_size) {
duke@0 1506 st->print("movdl %s, %s\t# spill",
duke@0 1507 Matcher::regName[dst_first],
duke@0 1508 Matcher::regName[src_first]);
duke@0 1509 #endif
duke@0 1510 }
duke@0 1511 return
duke@0 1512 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1513 ? 4
duke@0 1514 : 5; // REX
duke@0 1515 }
duke@0 1516 }
duke@0 1517 } else if (src_first_rc == rc_float) {
duke@0 1518 // xmm ->
duke@0 1519 if (dst_first_rc == rc_stack) {
duke@0 1520 // xmm -> mem
duke@0 1521 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1522 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1523 // 64-bit
duke@0 1524 int offset = ra_->reg2offset(dst_first);
duke@0 1525 if (cbuf) {
duke@0 1526 emit_opcode(*cbuf, 0xF2);
duke@0 1527 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1528 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1529 }
duke@0 1530 emit_opcode(*cbuf, 0x0F);
duke@0 1531 emit_opcode(*cbuf, 0x11);
duke@0 1532 encode_RegMem(*cbuf,
duke@0 1533 Matcher::_regEncode[src_first],
duke@0 1534 RSP_enc, 0x4, 0, offset,
duke@0 1535 false);
duke@0 1536 #ifndef PRODUCT
duke@0 1537 } else if (!do_size) {
duke@0 1538 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1539 offset,
duke@0 1540 Matcher::regName[src_first]);
duke@0 1541 #endif
duke@0 1542 }
duke@0 1543 return
duke@0 1544 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1545 ((Matcher::_regEncode[src_first] < 8)
duke@0 1546 ? 5
duke@0 1547 : 6); // REX
duke@0 1548 } else {
duke@0 1549 // 32-bit
duke@0 1550 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1551 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1552 int offset = ra_->reg2offset(dst_first);
duke@0 1553 if (cbuf) {
duke@0 1554 emit_opcode(*cbuf, 0xF3);
duke@0 1555 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1556 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1557 }
duke@0 1558 emit_opcode(*cbuf, 0x0F);
duke@0 1559 emit_opcode(*cbuf, 0x11);
duke@0 1560 encode_RegMem(*cbuf,
duke@0 1561 Matcher::_regEncode[src_first],
duke@0 1562 RSP_enc, 0x4, 0, offset,
duke@0 1563 false);
duke@0 1564 #ifndef PRODUCT
duke@0 1565 } else if (!do_size) {
duke@0 1566 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1567 offset,
duke@0 1568 Matcher::regName[src_first]);
duke@0 1569 #endif
duke@0 1570 }
duke@0 1571 return
duke@0 1572 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1573 ((Matcher::_regEncode[src_first] < 8)
duke@0 1574 ? 5
duke@0 1575 : 6); // REX
duke@0 1576 }
duke@0 1577 } else if (dst_first_rc == rc_int) {
duke@0 1578 // xmm -> gpr
duke@0 1579 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1580 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1581 // 64-bit
duke@0 1582 if (cbuf) {
duke@0 1583 emit_opcode(*cbuf, 0x66);
duke@0 1584 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1585 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1586 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1587 } else {
duke@0 1588 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
duke@0 1589 }
duke@0 1590 } else {
duke@0 1591 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1592 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
duke@0 1593 } else {
duke@0 1594 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1595 }
duke@0 1596 }
duke@0 1597 emit_opcode(*cbuf, 0x0F);
duke@0 1598 emit_opcode(*cbuf, 0x7E);
duke@0 1599 emit_rm(*cbuf, 0x3,
duke@0 1600 Matcher::_regEncode[dst_first] & 7,
duke@0 1601 Matcher::_regEncode[src_first] & 7);
duke@0 1602 #ifndef PRODUCT
duke@0 1603 } else if (!do_size) {
duke@0 1604 st->print("movdq %s, %s\t# spill",
duke@0 1605 Matcher::regName[dst_first],
duke@0 1606 Matcher::regName[src_first]);
duke@0 1607 #endif
duke@0 1608 }
duke@0 1609 return 5; // REX
duke@0 1610 } else {
duke@0 1611 // 32-bit
duke@0 1612 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1613 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1614 if (cbuf) {
duke@0 1615 emit_opcode(*cbuf, 0x66);
duke@0 1616 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1617 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1618 emit_opcode(*cbuf, Assembler::REX_R); // attention!
duke@0 1619 }
duke@0 1620 } else {
duke@0 1621 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1622 emit_opcode(*cbuf, Assembler::REX_B); // attention!
duke@0 1623 } else {
duke@0 1624 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1625 }
duke@0 1626 }
duke@0 1627 emit_opcode(*cbuf, 0x0F);
duke@0 1628 emit_opcode(*cbuf, 0x7E);
duke@0 1629 emit_rm(*cbuf, 0x3,
duke@0 1630 Matcher::_regEncode[dst_first] & 7,
duke@0 1631 Matcher::_regEncode[src_first] & 7);
duke@0 1632 #ifndef PRODUCT
duke@0 1633 } else if (!do_size) {
duke@0 1634 st->print("movdl %s, %s\t# spill",
duke@0 1635 Matcher::regName[dst_first],
duke@0 1636 Matcher::regName[src_first]);
duke@0 1637 #endif
duke@0 1638 }
duke@0 1639 return
duke@0 1640 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1641 ? 4
duke@0 1642 : 5; // REX
duke@0 1643 }
duke@0 1644 } else if (dst_first_rc == rc_float) {
duke@0 1645 // xmm -> xmm
duke@0 1646 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1647 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1648 // 64-bit
duke@0 1649 if (cbuf) {
duke@0 1650 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 1651 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1652 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1653 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1654 }
duke@0 1655 } else {
duke@0 1656 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1657 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1658 } else {
duke@0 1659 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1660 }
duke@0 1661 }
duke@0 1662 emit_opcode(*cbuf, 0x0F);
duke@0 1663 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1664 emit_rm(*cbuf, 0x3,
duke@0 1665 Matcher::_regEncode[dst_first] & 7,
duke@0 1666 Matcher::_regEncode[src_first] & 7);
duke@0 1667 #ifndef PRODUCT
duke@0 1668 } else if (!do_size) {
duke@0 1669 st->print("%s %s, %s\t# spill",
duke@0 1670 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1671 Matcher::regName[dst_first],
duke@0 1672 Matcher::regName[src_first]);
duke@0 1673 #endif
duke@0 1674 }
duke@0 1675 return
duke@0 1676 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1677 ? 4
duke@0 1678 : 5; // REX
duke@0 1679 } else {
duke@0 1680 // 32-bit
duke@0 1681 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1682 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1683 if (cbuf) {
duke@0 1684 if (!UseXmmRegToRegMoveAll)
duke@0 1685 emit_opcode(*cbuf, 0xF3);
duke@0 1686 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1687 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1688 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1689 }
duke@0 1690 } else {
duke@0 1691 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1692 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1693 } else {
duke@0 1694 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1695 }
duke@0 1696 }
duke@0 1697 emit_opcode(*cbuf, 0x0F);
duke@0 1698 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1699 emit_rm(*cbuf, 0x3,
duke@0 1700 Matcher::_regEncode[dst_first] & 7,
duke@0 1701 Matcher::_regEncode[src_first] & 7);
duke@0 1702 #ifndef PRODUCT
duke@0 1703 } else if (!do_size) {
duke@0 1704 st->print("%s %s, %s\t# spill",
duke@0 1705 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1706 Matcher::regName[dst_first],
duke@0 1707 Matcher::regName[src_first]);
duke@0 1708 #endif
duke@0 1709 }
duke@0 1710 return
duke@0 1711 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1712 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 1713 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
duke@0 1714 }
duke@0 1715 }
duke@0 1716 }
duke@0 1717
duke@0 1718 assert(0," foo ");
duke@0 1719 Unimplemented();
duke@0 1720
duke@0 1721 return 0;
duke@0 1722 }
duke@0 1723
duke@0 1724 #ifndef PRODUCT
duke@0 1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
duke@0 1726 {
duke@0 1727 implementation(NULL, ra_, false, st);
duke@0 1728 }
duke@0 1729 #endif
duke@0 1730
duke@0 1731 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 1732 {
duke@0 1733 implementation(&cbuf, ra_, false, NULL);
duke@0 1734 }
duke@0 1735
duke@0 1736 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
duke@0 1737 {
duke@0 1738 return implementation(NULL, ra_, true, NULL);
duke@0 1739 }
duke@0 1740
duke@0 1741 //=============================================================================
duke@0 1742 #ifndef PRODUCT
duke@0 1743 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 1744 {
duke@0 1745 st->print("nop \t# %d bytes pad for loops and calls", _count);
duke@0 1746 }
duke@0 1747 #endif
duke@0 1748
duke@0 1749 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
duke@0 1750 {
duke@0 1751 MacroAssembler _masm(&cbuf);
duke@0 1752 __ nop(_count);
duke@0 1753 }
duke@0 1754
duke@0 1755 uint MachNopNode::size(PhaseRegAlloc*) const
duke@0 1756 {
duke@0 1757 return _count;
duke@0 1758 }
duke@0 1759
duke@0 1760
duke@0 1761 //=============================================================================
duke@0 1762 #ifndef PRODUCT
duke@0 1763 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1764 {
duke@0 1765 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1766 int reg = ra_->get_reg_first(this);
duke@0 1767 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1768 Matcher::regName[reg], offset);
duke@0 1769 }
duke@0 1770 #endif
duke@0 1771
duke@0 1772 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1773 {
duke@0 1774 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1775 int reg = ra_->get_encode(this);
duke@0 1776 if (offset >= 0x80) {
duke@0 1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1779 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1781 emit_d32(cbuf, offset);
duke@0 1782 } else {
duke@0 1783 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1784 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1785 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1786 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1787 emit_d8(cbuf, offset);
duke@0 1788 }
duke@0 1789 }
duke@0 1790
duke@0 1791 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1792 {
duke@0 1793 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1794 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1795 }
duke@0 1796
duke@0 1797 //=============================================================================
duke@0 1798
duke@0 1799 // emit call stub, compiled java to interpreter
duke@0 1800 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1801 {
duke@0 1802 // Stub is fixed up when the corresponding call is converted from
duke@0 1803 // calling compiled code to calling interpreted code.
duke@0 1804 // movq rbx, 0
duke@0 1805 // jmp -5 # to self
duke@0 1806
duke@0 1807 address mark = cbuf.inst_mark(); // get mark within main instrs section
duke@0 1808
duke@0 1809 // Note that the code buffer's inst_mark is always relative to insts.
duke@0 1810 // That's why we must use the macroassembler to generate a stub.
duke@0 1811 MacroAssembler _masm(&cbuf);
duke@0 1812
duke@0 1813 address base =
duke@0 1814 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1815 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1816 // static stub relocation stores the instruction address of the call
duke@0 1817 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
duke@0 1818 // static stub relocation also tags the methodOop in the code-stream.
duke@0 1819 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
never@304 1820 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1821 __ jump(RuntimeAddress(__ pc()));
duke@0 1822
duke@0 1823 // Update current stubs pointer and restore code_end.
duke@0 1824 __ end_a_stub();
duke@0 1825 }
duke@0 1826
duke@0 1827 // size of call stub, compiled java to interpretor
duke@0 1828 uint size_java_to_interp()
duke@0 1829 {
duke@0 1830 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1831 }
duke@0 1832
duke@0 1833 // relocation entries for call stub, compiled java to interpretor
duke@0 1834 uint reloc_java_to_interp()
duke@0 1835 {
duke@0 1836 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1837 }
duke@0 1838
duke@0 1839 //=============================================================================
duke@0 1840 #ifndef PRODUCT
duke@0 1841 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1842 {
coleenp@113 1843 if (UseCompressedOops) {
coleenp@113 1844 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
coleenp@113 1845 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
coleenp@113 1846 st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1847 } else {
coleenp@113 1848 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
coleenp@113 1849 "# Inline cache check", oopDesc::klass_offset_in_bytes());
coleenp@113 1850 }
duke@0 1851 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
duke@0 1852 st->print_cr("\tnop");
duke@0 1853 if (!OptoBreakpoint) {
duke@0 1854 st->print_cr("\tnop");
duke@0 1855 }
duke@0 1856 }
duke@0 1857 #endif
duke@0 1858
duke@0 1859 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1860 {
duke@0 1861 MacroAssembler masm(&cbuf);
duke@0 1862 #ifdef ASSERT
duke@0 1863 uint code_size = cbuf.code_size();
duke@0 1864 #endif
coleenp@113 1865 if (UseCompressedOops) {
coleenp@113 1866 masm.load_klass(rscratch1, j_rarg0);
never@304 1867 masm.cmpptr(rax, rscratch1);
coleenp@113 1868 } else {
never@304 1869 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1870 }
duke@0 1871
duke@0 1872 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1873
duke@0 1874 /* WARNING these NOPs are critical so that verified entry point is properly
duke@0 1875 aligned for patching by NativeJump::patch_verified_entry() */
duke@0 1876 int nops_cnt = 1;
duke@0 1877 if (!OptoBreakpoint) {
duke@0 1878 // Leave space for int3
duke@0 1879 nops_cnt += 1;
duke@0 1880 }
coleenp@113 1881 if (UseCompressedOops) {
coleenp@113 1882 // ??? divisible by 4 is aligned?
coleenp@113 1883 nops_cnt += 1;
coleenp@113 1884 }
duke@0 1885 masm.nop(nops_cnt);
duke@0 1886
duke@0 1887 assert(cbuf.code_size() - code_size == size(ra_),
duke@0 1888 "checking code size of inline cache node");
duke@0 1889 }
duke@0 1890
duke@0 1891 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1892 {
coleenp@113 1893 if (UseCompressedOops) {
coleenp@113 1894 return OptoBreakpoint ? 19 : 20;
coleenp@113 1895 } else {
coleenp@113 1896 return OptoBreakpoint ? 11 : 12;
coleenp@113 1897 }
duke@0 1898 }
duke@0 1899
duke@0 1900
duke@0 1901 //=============================================================================
duke@0 1902 uint size_exception_handler()
duke@0 1903 {
duke@0 1904 // NativeCall instruction size is the same as NativeJump.
duke@0 1905 // Note that this value is also credited (in output.cpp) to
duke@0 1906 // the size of the code section.
duke@0 1907 return NativeJump::instruction_size;
duke@0 1908 }
duke@0 1909
duke@0 1910 // Emit exception handler code.
duke@0 1911 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1912 {
duke@0 1913
duke@0 1914 // Note that the code buffer's inst_mark is always relative to insts.
duke@0 1915 // That's why we must use the macroassembler to generate a handler.
duke@0 1916 MacroAssembler _masm(&cbuf);
duke@0 1917 address base =
duke@0 1918 __ start_a_stub(size_exception_handler());
duke@0 1919 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1920 int offset = __ offset();
duke@0 1921 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
duke@0 1922 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1923 __ end_a_stub();
duke@0 1924 return offset;
duke@0 1925 }
duke@0 1926
duke@0 1927 uint size_deopt_handler()
duke@0 1928 {
duke@0 1929 // three 5 byte instructions
duke@0 1930 return 15;
duke@0 1931 }
duke@0 1932
duke@0 1933 // Emit deopt handler code.
duke@0 1934 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1935 {
duke@0 1936
duke@0 1937 // Note that the code buffer's inst_mark is always relative to insts.
duke@0 1938 // That's why we must use the macroassembler to generate a handler.
duke@0 1939 MacroAssembler _masm(&cbuf);
duke@0 1940 address base =
duke@0 1941 __ start_a_stub(size_deopt_handler());
duke@0 1942 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1943 int offset = __ offset();
duke@0 1944 address the_pc = (address) __ pc();
duke@0 1945 Label next;
duke@0 1946 // push a "the_pc" on the stack without destroying any registers
duke@0 1947 // as they all may be live.
duke@0 1948
duke@0 1949 // push address of "next"
duke@0 1950 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1951 __ bind(next);
duke@0 1952 // adjust it so it matches "the_pc"
never@304 1953 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1954 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1955 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1956 __ end_a_stub();
duke@0 1957 return offset;
duke@0 1958 }
duke@0 1959
duke@0 1960 static void emit_double_constant(CodeBuffer& cbuf, double x) {
duke@0 1961 int mark = cbuf.insts()->mark_off();
duke@0 1962 MacroAssembler _masm(&cbuf);
duke@0 1963 address double_address = __ double_constant(x);
duke@0 1964 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
duke@0 1965 emit_d32_reloc(cbuf,
duke@0 1966 (int) (double_address - cbuf.code_end() - 4),
duke@0 1967 internal_word_Relocation::spec(double_address),
duke@0 1968 RELOC_DISP32);
duke@0 1969 }
duke@0 1970
duke@0 1971 static void emit_float_constant(CodeBuffer& cbuf, float x) {
duke@0 1972 int mark = cbuf.insts()->mark_off();
duke@0 1973 MacroAssembler _masm(&cbuf);
duke@0 1974 address float_address = __ float_constant(x);
duke@0 1975 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
duke@0 1976 emit_d32_reloc(cbuf,
duke@0 1977 (int) (float_address - cbuf.code_end() - 4),
duke@0 1978 internal_word_Relocation::spec(float_address),
duke@0 1979 RELOC_DISP32);
duke@0 1980 }
duke@0 1981
duke@0 1982
duke@0 1983 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1984 {
duke@0 1985 return regnum - 32; // The FP registers are in the second chunk
duke@0 1986 }
duke@0 1987
duke@0 1988 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1989 const bool Matcher::convL2FSupported(void) {
duke@0 1990 return true;
duke@0 1991 }
duke@0 1992
duke@0 1993 // Vector width in bytes
duke@0 1994 const uint Matcher::vector_width_in_bytes(void) {
duke@0 1995 return 8;
duke@0 1996 }
duke@0 1997
duke@0 1998 // Vector ideal reg
duke@0 1999 const uint Matcher::vector_ideal_reg(void) {
duke@0 2000 return Op_RegD;
duke@0 2001 }
duke@0 2002
duke@0 2003 // Is this branch offset short enough that a short branch can be used?
duke@0 2004 //
duke@0 2005 // NOTE: If the platform does not provide any short branch variants, then
duke@0 2006 // this method should return false for offset 0.
never@415 2007 bool Matcher::is_short_branch_offset(int rule, int offset) {
never@415 2008 // the short version of jmpConUCF2 contains multiple branches,
never@415 2009 // making the reach slightly less
never@415 2010 if (rule == jmpConUCF2_rule)
never@415 2011 return (-126 <= offset && offset <= 125);
never@415 2012 return (-128 <= offset && offset <= 127);
duke@0 2013 }
duke@0 2014
duke@0 2015 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 2016 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 2017 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 2018
duke@0 2019 // Probably always true, even if a temp register is required.
duke@0 2020 return true;
duke@0 2021 }
duke@0 2022
duke@0 2023 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 2024 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 2025
duke@0 2026 // Threshold size for cleararray.
duke@0 2027 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 2028
duke@0 2029 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 2030 // to be subsumed into complex addressing expressions or compute them
duke@0 2031 // into registers? True for Intel but false for most RISCs
duke@0 2032 const bool Matcher::clone_shift_expressions = true;
duke@0 2033
duke@0 2034 // Is it better to copy float constants, or load them directly from
duke@0 2035 // memory? Intel can load a float constant from a direct address,
duke@0 2036 // requiring no extra registers. Most RISCs will have to materialize
duke@0 2037 // an address into a register first, so they would do better to copy
duke@0 2038 // the constant from stack.
duke@0 2039 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 2040
duke@0 2041 // If CPU can load and store mis-aligned doubles directly then no
duke@0 2042 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 2043 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 2044 // C code as the Java calling convention forces doubles to be aligned.
duke@0 2045 const bool Matcher::misaligned_doubles_ok = true;
duke@0 2046
duke@0 2047 // No-op on amd64
duke@0 2048 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 2049
duke@0 2050 // Advertise here if the CPU requires explicit rounding operations to
duke@0 2051 // implement the UseStrictFP mode.
duke@0 2052 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 2053
duke@0 2054 // Do floats take an entire double register or just half?
duke@0 2055 const bool Matcher::float_in_double = true;
duke@0 2056 // Do ints take an entire long register or just half?
duke@0 2057 const bool Matcher::int_in_long = true;
duke@0 2058
duke@0 2059 // Return whether or not this register is ever used as an argument.
duke@0 2060 // This function is used on startup to build the trampoline stubs in
duke@0 2061 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 2062 // call in the trampoline, and arguments in those registers not be
duke@0 2063 // available to the callee.
duke@0 2064 bool Matcher::can_be_java_arg(int reg)
duke@0 2065 {
duke@0 2066 return
duke@0 2067 reg == RDI_num || reg == RDI_H_num ||
duke@0 2068 reg == RSI_num || reg == RSI_H_num ||
duke@0 2069 reg == RDX_num || reg == RDX_H_num ||
duke@0 2070 reg == RCX_num || reg == RCX_H_num ||
duke@0 2071 reg == R8_num || reg == R8_H_num ||
duke@0 2072 reg == R9_num || reg == R9_H_num ||
coleenp@113 2073 reg == R12_num || reg == R12_H_num ||
duke@0 2074 reg == XMM0_num || reg == XMM0_H_num ||
duke@0 2075 reg == XMM1_num || reg == XMM1_H_num ||
duke@0 2076 reg == XMM2_num || reg == XMM2_H_num ||
duke@0 2077 reg == XMM3_num || reg == XMM3_H_num ||
duke@0 2078 reg == XMM4_num || reg == XMM4_H_num ||
duke@0 2079 reg == XMM5_num || reg == XMM5_H_num ||
duke@0 2080 reg == XMM6_num || reg == XMM6_H_num ||
duke@0 2081 reg == XMM7_num || reg == XMM7_H_num;
duke@0 2082 }
duke@0 2083
duke@0 2084 bool Matcher::is_spillable_arg(int reg)
duke@0 2085 {
duke@0 2086 return can_be_java_arg(reg);
duke@0 2087 }
duke@0 2088
duke@0 2089 // Register for DIVI projection of divmodI
duke@0 2090 RegMask Matcher::divI_proj_mask() {
duke@0 2091 return INT_RAX_REG_mask;
duke@0 2092 }
duke@0 2093
duke@0 2094 // Register for MODI projection of divmodI
duke@0 2095 RegMask Matcher::modI_proj_mask() {
duke@0 2096 return INT_RDX_REG_mask;
duke@0 2097 }
duke@0 2098
duke@0 2099 // Register for DIVL projection of divmodL
duke@0 2100 RegMask Matcher::divL_proj_mask() {
duke@0 2101 return LONG_RAX_REG_mask;
duke@0 2102 }
duke@0 2103
duke@0 2104 // Register for MODL projection of divmodL
duke@0 2105 RegMask Matcher::modL_proj_mask() {
duke@0 2106 return LONG_RDX_REG_mask;
duke@0 2107 }
duke@0 2108
coleenp@113 2109 static Address build_address(int b, int i, int s, int d) {
coleenp@113 2110 Register index = as_Register(i);
coleenp@113 2111 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 2112 if (index == rsp) {
coleenp@113 2113 index = noreg;
coleenp@113 2114 scale = Address::no_scale;
coleenp@113 2115 }
coleenp@113 2116 Address addr(as_Register(b), index, scale, d);
coleenp@113 2117 return addr;
coleenp@113 2118 }
coleenp@113 2119
duke@0 2120 %}
duke@0 2121
duke@0 2122 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 2123 // This block specifies the encoding classes used by the compiler to
duke@0 2124 // output byte streams. Encoding classes are parameterized macros
duke@0 2125 // used by Machine Instruction Nodes in order to generate the bit
duke@0 2126 // encoding of the instruction. Operands specify their base encoding
duke@0 2127 // interface with the interface keyword. There are currently
duke@0 2128 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 2129 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 2130 // which returns its register number when queried. CONST_INTER causes
duke@0 2131 // an operand to generate a function which returns the value of the
duke@0 2132 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 2133 // four functions which return the Base Register, the Index Register,
duke@0 2134 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 2135 // COND_INTER causes an operand to generate six functions which return
duke@0 2136 // the encoding code (ie - encoding bits for the instruction)
duke@0 2137 // associated with each basic boolean condition for a conditional
duke@0 2138 // instruction.
duke@0 2139 //
duke@0 2140 // Instructions specify two basic values for encoding. Again, a
duke@0 2141 // function is available to check if the constant displacement is an
duke@0 2142 // oop. They use the ins_encode keyword to specify their encoding
duke@0 2143 // classes (which must be a sequence of enc_class names, and their
duke@0 2144 // parameters, specified in the encoding block), and they use the
duke@0 2145 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 2146 // tertiary opcode. Only the opcode sections which a particular
duke@0 2147 // instruction needs for encoding need to be specified.
duke@0 2148 encode %{
duke@0 2149 // Build emit functions for each basic byte or larger field in the
duke@0 2150 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 2151 // from C++ code in the enc_class source block. Emit functions will
duke@0 2152 // live in the main source block for now. In future, we can
duke@0 2153 // generalize this by adding a syntax that specifies the sizes of
duke@0 2154 // fields in an order, so that the adlc can build the emit functions
duke@0 2155 // automagically
duke@0 2156
duke@0 2157 // Emit primary opcode
duke@0 2158 enc_class OpcP
duke@0 2159 %{
duke@0 2160 emit_opcode(cbuf, $primary);
duke@0 2161 %}
duke@0 2162
duke@0 2163 // Emit secondary opcode
duke@0 2164 enc_class OpcS
duke@0 2165 %{
duke@0 2166 emit_opcode(cbuf, $secondary);
duke@0 2167 %}
duke@0 2168
duke@0 2169 // Emit tertiary opcode
duke@0 2170 enc_class OpcT
duke@0 2171 %{
duke@0 2172 emit_opcode(cbuf, $tertiary);
duke@0 2173 %}
duke@0 2174
duke@0 2175 // Emit opcode directly
duke@0 2176 enc_class Opcode(immI d8)
duke@0 2177 %{
duke@0 2178 emit_opcode(cbuf, $d8$$constant);
duke@0 2179 %}
duke@0 2180
duke@0 2181 // Emit size prefix
duke@0 2182 enc_class SizePrefix
duke@0 2183 %{
duke@0 2184 emit_opcode(cbuf, 0x66);
duke@0 2185 %}
duke@0 2186
duke@0 2187 enc_class reg(rRegI reg)
duke@0 2188 %{
duke@0 2189 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 2190 %}
duke@0 2191
duke@0 2192 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 2193 %{
duke@0 2194 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2195 %}
duke@0 2196
duke@0 2197 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 2198 %{
duke@0 2199 emit_opcode(cbuf, $opcode$$constant);
duke@0 2200 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2201 %}
duke@0 2202
duke@0 2203 enc_class cmpfp_fixup()
duke@0 2204 %{
duke@0 2205 // jnp,s exit
duke@0 2206 emit_opcode(cbuf, 0x7B);
duke@0 2207 emit_d8(cbuf, 0x0A);
duke@0 2208
duke@0 2209 // pushfq
duke@0 2210 emit_opcode(cbuf, 0x9C);
duke@0 2211
duke@0 2212 // andq $0xffffff2b, (%rsp)
duke@0 2213 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2214 emit_opcode(cbuf, 0x81);
duke@0 2215 emit_opcode(cbuf, 0x24);
duke@0 2216 emit_opcode(cbuf, 0x24);
duke@0 2217 emit_d32(cbuf, 0xffffff2b);
duke@0 2218
duke@0 2219 // popfq
duke@0 2220 emit_opcode(cbuf, 0x9D);
duke@0 2221
duke@0 2222 // nop (target for branch to avoid branch to branch)
duke@0 2223 emit_opcode(cbuf, 0x90);
duke@0 2224 %}
duke@0 2225
duke@0 2226 enc_class cmpfp3(rRegI dst)
duke@0 2227 %{
duke@0 2228 int dstenc = $dst$$reg;
duke@0 2229
duke@0 2230 // movl $dst, -1
duke@0 2231 if (dstenc >= 8) {
duke@0 2232 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2233 }
duke@0 2234 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2235 emit_d32(cbuf, -1);
duke@0 2236
duke@0 2237 // jp,s done
duke@0 2238 emit_opcode(cbuf, 0x7A);
duke@0 2239 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
duke@0 2240
duke@0 2241 // jb,s done
duke@0 2242 emit_opcode(cbuf, 0x72);
duke@0 2243 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2244
duke@0 2245 // setne $dst
duke@0 2246 if (dstenc >= 4) {
duke@0 2247 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2248 }
duke@0 2249 emit_opcode(cbuf, 0x0F);
duke@0 2250 emit_opcode(cbuf, 0x95);
duke@0 2251 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2252
duke@0 2253 // movzbl $dst, $dst
duke@0 2254 if (dstenc >= 4) {
duke@0 2255 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2256 }
duke@0 2257 emit_opcode(cbuf, 0x0F);
duke@0 2258 emit_opcode(cbuf, 0xB6);
duke@0 2259 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2260 %}
duke@0 2261
duke@0 2262 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 2263 %{
duke@0 2264 // Full implementation of Java idiv and irem; checks for
duke@0 2265 // special case as described in JVM spec., p.243 & p.271.
duke@0 2266 //
duke@0 2267 // normal case special case
duke@0 2268 //
duke@0 2269 // input : rax: dividend min_int
duke@0 2270 // reg: divisor -1
duke@0 2271 //
duke@0 2272 // output: rax: quotient (= rax idiv reg) min_int
duke@0 2273 // rdx: remainder (= rax irem reg) 0
duke@0 2274 //
duke@0 2275 // Code sequnce:
duke@0 2276 //
duke@0 2277 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 2278 // 5: 75 07/08 jne e <normal>
duke@0 2279 // 7: 33 d2 xor %edx,%edx
duke@0 2280 // [div >= 8 -> offset + 1]
duke@0 2281 // [REX_B]
duke@0 2282 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2283 // c: 74 03/04 je 11 <done>
duke@0 2284 // 000000000000000e <normal>:
duke@0 2285 // e: 99 cltd
duke@0 2286 // [div >= 8 -> offset + 1]
duke@0 2287 // [REX_B]
duke@0 2288 // f: f7 f9 idiv $div
duke@0 2289 // 0000000000000011 <done>:
duke@0 2290
duke@0 2291 // cmp $0x80000000,%eax
duke@0 2292 emit_opcode(cbuf, 0x3d);
duke@0 2293 emit_d8(cbuf, 0x00);
duke@0 2294 emit_d8(cbuf, 0x00);
duke@0 2295 emit_d8(cbuf, 0x00);
duke@0 2296 emit_d8(cbuf, 0x80);
duke@0 2297
duke@0 2298 // jne e <normal>
duke@0 2299 emit_opcode(cbuf, 0x75);
duke@0 2300 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 2301
duke@0 2302 // xor %edx,%edx
duke@0 2303 emit_opcode(cbuf, 0x33);
duke@0 2304 emit_d8(cbuf, 0xD2);
duke@0 2305
duke@0 2306 // cmp $0xffffffffffffffff,%ecx
duke@0 2307 if ($div$$reg >= 8) {
duke@0 2308 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2309 }
duke@0 2310 emit_opcode(cbuf, 0x83);
duke@0 2311 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2312 emit_d8(cbuf, 0xFF);
duke@0 2313
duke@0 2314 // je 11 <done>
duke@0 2315 emit_opcode(cbuf, 0x74);
duke@0 2316 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 2317
duke@0 2318 // <normal>
duke@0 2319 // cltd
duke@0 2320 emit_opcode(cbuf, 0x99);
duke@0 2321
duke@0 2322 // idivl (note: must be emitted by the user of this rule)
duke@0 2323 // <done>
duke@0 2324 %}
duke@0 2325
duke@0 2326 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 2327 %{
duke@0 2328 // Full implementation of Java ldiv and lrem; checks for
duke@0 2329 // special case as described in JVM spec., p.243 & p.271.
duke@0 2330 //
duke@0 2331 // normal case special case
duke@0 2332 //
duke@0 2333 // input : rax: dividend min_long
duke@0 2334 // reg: divisor -1
duke@0 2335 //
duke@0 2336 // output: rax: quotient (= rax idiv reg) min_long
duke@0 2337 // rdx: remainder (= rax irem reg) 0
duke@0 2338 //
duke@0 2339 // Code sequnce:
duke@0 2340 //
duke@0 2341 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 2342 // 7: 00 00 80
duke@0 2343 // a: 48 39 d0 cmp %rdx,%rax
duke@0 2344 // d: 75 08 jne 17 <normal>
duke@0 2345 // f: 33 d2 xor %edx,%edx
duke@0 2346 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2347 // 15: 74 05 je 1c <done>
duke@0 2348 // 0000000000000017 <normal>:
duke@0 2349 // 17: 48 99 cqto
duke@0 2350 // 19: 48 f7 f9 idiv $div
duke@0 2351 // 000000000000001c <done>:
duke@0 2352
duke@0 2353 // mov $0x8000000000000000,%rdx
duke@0 2354 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2355 emit_opcode(cbuf, 0xBA);
duke@0 2356 emit_d8(cbuf, 0x00);
duke@0 2357 emit_d8(cbuf, 0x00);
duke@0 2358 emit_d8(cbuf, 0x00);
duke@0 2359 emit_d8(cbuf, 0x00);
duke@0 2360 emit_d8(cbuf, 0x00);
duke@0 2361 emit_d8(cbuf, 0x00);
duke@0 2362 emit_d8(cbuf, 0x00);
duke@0 2363 emit_d8(cbuf, 0x80);
duke@0 2364
duke@0 2365 // cmp %rdx,%rax
duke@0 2366 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2367 emit_opcode(cbuf, 0x39);
duke@0 2368 emit_d8(cbuf, 0xD0);
duke@0 2369
duke@0 2370 // jne 17 <normal>
duke@0 2371 emit_opcode(cbuf, 0x75);
duke@0 2372 emit_d8(cbuf, 0x08);
duke@0 2373
duke@0 2374 // xor %edx,%edx
duke@0 2375 emit_opcode(cbuf, 0x33);
duke@0 2376 emit_d8(cbuf, 0xD2);
duke@0 2377
duke@0 2378 // cmp $0xffffffffffffffff,$div
duke@0 2379 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 2380 emit_opcode(cbuf, 0x83);
duke@0 2381 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2382 emit_d8(cbuf, 0xFF);
duke@0 2383
duke@0 2384 // je 1e <done>
duke@0 2385 emit_opcode(cbuf, 0x74);
duke@0 2386 emit_d8(cbuf, 0x05);
duke@0 2387
duke@0 2388 // <normal>
duke@0 2389 // cqto
duke@0 2390 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2391 emit_opcode(cbuf, 0x99);
duke@0 2392
duke@0 2393 // idivq (note: must be emitted by the user of this rule)
duke@0 2394 // <done>
duke@0 2395 %}
duke@0 2396
duke@0 2397 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 2398 enc_class OpcSE(immI imm)
duke@0 2399 %{
duke@0 2400 // Emit primary opcode and set sign-extend bit
duke@0 2401 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2402 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2403 emit_opcode(cbuf, $primary | 0x02);
duke@0 2404 } else {
duke@0 2405 // 32-bit immediate
duke@0 2406 emit_opcode(cbuf, $primary);
duke@0 2407 }
duke@0 2408 %}
duke@0 2409
duke@0 2410 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 2411 %{
duke@0 2412 // OpcSEr/m
duke@0 2413 int dstenc = $dst$$reg;
duke@0 2414 if (dstenc >= 8) {
duke@0 2415 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2416 dstenc -= 8;
duke@0 2417 }
duke@0 2418 // Emit primary opcode and set sign-extend bit
duke@0 2419 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2420 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2421 emit_opcode(cbuf, $primary | 0x02);
duke@0 2422 } else {
duke@0 2423 // 32-bit immediate
duke@0 2424 emit_opcode(cbuf, $primary);
duke@0 2425 }
duke@0 2426 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2427 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2428 %}
duke@0 2429
duke@0 2430 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 2431 %{
duke@0 2432 // OpcSEr/m
duke@0 2433 int dstenc = $dst$$reg;
duke@0 2434 if (dstenc < 8) {
duke@0 2435 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2436 } else {
duke@0 2437 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2438 dstenc -= 8;
duke@0 2439 }
duke@0 2440 // Emit primary opcode and set sign-extend bit
duke@0 2441 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2442 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2443 emit_opcode(cbuf, $primary | 0x02);
duke@0 2444 } else {
duke@0 2445 // 32-bit immediate
duke@0 2446 emit_opcode(cbuf, $primary);
duke@0 2447 }
duke@0 2448 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2449 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2450 %}
duke@0 2451
duke@0 2452 enc_class Con8or32(immI imm)
duke@0 2453 %{
duke@0 2454 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2455 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2456 $$$emit8$imm$$constant;
duke@0 2457 } else {
duke@0 2458 // 32-bit immediate
duke@0 2459 $$$emit32$imm$$constant;
duke@0 2460 }
duke@0 2461 %}
duke@0 2462
duke@0 2463 enc_class Lbl(label labl)
duke@0 2464 %{
duke@0 2465 // JMP, CALL
duke@0 2466 Label* l = $labl$$label;
duke@0 2467 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
duke@0 2468 %}
duke@0 2469
duke@0 2470 enc_class LblShort(label labl)
duke@0 2471 %{
duke@0 2472 // JMP, CALL
duke@0 2473 Label* l = $labl$$label;
duke@0 2474 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
duke@0 2475 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2476 emit_d8(cbuf, disp);
duke@0 2477 %}
duke@0 2478
duke@0 2479 enc_class opc2_reg(rRegI dst)
duke@0 2480 %{
duke@0 2481 // BSWAP
duke@0 2482 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2483 %}
duke@0 2484
duke@0 2485 enc_class opc3_reg(rRegI dst)
duke@0 2486 %{
duke@0 2487 // BSWAP
duke@0 2488 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2489 %}
duke@0 2490
duke@0 2491 enc_class reg_opc(rRegI div)
duke@0 2492 %{
duke@0 2493 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2494 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2495 %}
duke@0 2496
duke@0 2497 enc_class Jcc(cmpOp cop, label labl)
duke@0 2498 %{
duke@0 2499 // JCC
duke@0 2500 Label* l = $labl$$label;
duke@0 2501 $$$emit8$primary;
duke@0 2502 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2503 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
duke@0 2504 %}
duke@0 2505
duke@0 2506 enc_class JccShort (cmpOp cop, label labl)
duke@0 2507 %{
duke@0 2508 // JCC
duke@0 2509 Label *l = $labl$$label;
duke@0 2510 emit_cc(cbuf, $primary, $cop$$cmpcode);
duke@0 2511 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
duke@0 2512 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2513 emit_d8(cbuf, disp);
duke@0 2514 %}
duke@0 2515
duke@0 2516 enc_class enc_cmov(cmpOp cop)
duke@0 2517 %{
duke@0 2518 // CMOV
duke@0 2519 $$$emit8$primary;
duke@0 2520 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2521 %}
duke@0 2522
duke@0 2523 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
duke@0 2524 %{
duke@0 2525 // Invert sense of branch from sense of cmov
duke@0 2526 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2527 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
duke@0 2528 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 2529 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
duke@0 2530 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
duke@0 2531 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
duke@0 2532 if ($dst$$reg < 8) {
duke@0 2533 if ($src$$reg >= 8) {
duke@0 2534 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2535 }
duke@0 2536 } else {
duke@0 2537 if ($src$$reg < 8) {
duke@0 2538 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2539 } else {
duke@0 2540 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2541 }
duke@0 2542 }
duke@0 2543 emit_opcode(cbuf, 0x0F);
duke@0 2544 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2545 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2546 %}
duke@0 2547
duke@0 2548 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
duke@0 2549 %{
duke@0 2550 // Invert sense of branch from sense of cmov
duke@0 2551 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2552 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
duke@0 2553
duke@0 2554 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
duke@0 2555 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 2556 if ($dst$$reg < 8) {
duke@0 2557 if ($src$$reg >= 8) {
duke@0 2558 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2559 }
duke@0 2560 } else {
duke@0 2561 if ($src$$reg < 8) {
duke@0 2562 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2563 } else {
duke@0 2564 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2565 }
duke@0 2566 }
duke@0 2567 emit_opcode(cbuf, 0x0F);
duke@0 2568 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2569 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2570 %}
duke@0 2571
duke@0 2572 enc_class enc_PartialSubtypeCheck()
duke@0 2573 %{
duke@0 2574 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2575 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2576 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2577 Register Rrsi = as_Register(RSI_enc); // sub class
coleenp@113 2578 Label hit, miss, cmiss;
duke@0 2579
duke@0 2580 MacroAssembler _masm(&cbuf);
duke@0 2581 // Compare super with sub directly, since super is not in its own SSA.
duke@0 2582 // The compiler used to emit this test, but we fold it in here,
duke@0 2583 // to allow platform-specific tweaking on sparc.
never@304 2584 __ cmpptr(Rrax, Rrsi);
duke@0 2585 __ jcc(Assembler::equal, hit);
duke@0 2586 #ifndef PRODUCT
duke@0 2587 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
duke@0 2588 __ incrementl(Address(Rrcx, 0));
duke@0 2589 #endif //PRODUCT
never@304 2590 __ movptr(Rrdi, Address(Rrsi,
never@304 2591 sizeof(oopDesc) +
duke@0 2592 Klass::secondary_supers_offset_in_bytes()));
duke@0 2593 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
never@304 2594 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
coleenp@113 2595 if (UseCompressedOops) {
coleenp@113 2596 __ encode_heap_oop(Rrax);
coleenp@113 2597 __ repne_scanl();
coleenp@113 2598 __ jcc(Assembler::notEqual, cmiss);
coleenp@113 2599 __ decode_heap_oop(Rrax);
never@304 2600 __ movptr(Address(Rrsi,
coleenp@113 2601 sizeof(oopDesc) +
coleenp@113 2602 Klass::secondary_super_cache_offset_in_bytes()),
coleenp@113 2603 Rrax);
coleenp@113 2604 __ jmp(hit);
coleenp@113 2605 __ bind(cmiss);
coleenp@113 2606 __ decode_heap_oop(Rrax);
coleenp@113 2607 __ jmp(miss);
coleenp@113 2608 } else {
never@304 2609 __ repne_scan();
coleenp@113 2610 __ jcc(Assembler::notEqual, miss);
never@304 2611 __ movptr(Address(Rrsi,
coleenp@113 2612 sizeof(oopDesc) +
coleenp@113 2613 Klass::secondary_super_cache_offset_in_bytes()),
coleenp@113 2614 Rrax);
coleenp@113 2615 }
duke@0 2616 __ bind(hit);
duke@0 2617 if ($primary) {
never@304 2618 __ xorptr(Rrdi, Rrdi);
duke@0 2619 }
duke@0 2620 __ bind(miss);
duke@0 2621 %}
duke@0 2622
duke@0 2623 enc_class Java_To_Interpreter(method meth)
duke@0 2624 %{
duke@0 2625 // CALL Java_To_Interpreter
duke@0 2626 // This is the instruction starting address for relocation info.
duke@0 2627 cbuf.set_inst_mark();
duke@0 2628 $$$emit8$primary;
duke@0 2629 // CALL directly to the runtime
duke@0 2630 emit_d32_reloc(cbuf,
duke@0 2631 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
duke@0 2632 runtime_call_Relocation::spec(),
duke@0 2633 RELOC_DISP32);
duke@0 2634 %}
duke@0 2635
duke@0 2636 enc_class Java_Static_Call(method meth)
duke@0 2637 %{
duke@0 2638 // JAVA STATIC CALL
duke@0 2639 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2640 // determine who we intended to call.
duke@0 2641 cbuf.set_inst_mark();
duke@0 2642 $$$emit8$primary;
duke@0 2643
duke@0 2644 if (!_method) {
duke@0 2645 emit_d32_reloc(cbuf,
duke@0 2646 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
duke@0 2647 runtime_call_Relocation::spec(),
duke@0 2648 RELOC_DISP32);
duke@0 2649 } else if (_optimized_virtual) {
duke@0 2650 emit_d32_reloc(cbuf,
duke@0 2651 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
duke@0 2652 opt_virtual_call_Relocation::spec(),
duke@0 2653 RELOC_DISP32);
duke@0 2654 } else {
duke@0 2655 emit_d32_reloc(cbuf,
duke@0 2656 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
duke@0 2657 static_call_Relocation::spec(),
duke@0 2658 RELOC_DISP32);
duke@0 2659 }
duke@0 2660 if (_method) {
duke@0 2661 // Emit stub for static call
duke@0 2662 emit_java_to_interp(cbuf);
duke@0 2663 }
duke@0 2664 %}
duke@0 2665
duke@0 2666 enc_class Java_Dynamic_Call(method meth)
duke@0 2667 %{
duke@0 2668 // JAVA DYNAMIC CALL
duke@0 2669 // !!!!!
duke@0 2670 // Generate "movq rax, -1", placeholder instruction to load oop-info
duke@0 2671 // emit_call_dynamic_prologue( cbuf );
duke@0 2672 cbuf.set_inst_mark();
duke@0 2673
duke@0 2674 // movq rax, -1
duke@0 2675 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2676 emit_opcode(cbuf, 0xB8 | RAX_enc);
duke@0 2677 emit_d64_reloc(cbuf,
duke@0 2678 (int64_t) Universe::non_oop_word(),
duke@0 2679 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
duke@0 2680 address virtual_call_oop_addr = cbuf.inst_mark();
duke@0 2681 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2682 // who we intended to call.
duke@0 2683 cbuf.set_inst_mark();
duke@0 2684 $$$emit8$primary;
duke@0 2685 emit_d32_reloc(cbuf,
duke@0 2686 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
duke@0 2687 virtual_call_Relocation::spec(virtual_call_oop_addr),
duke@0 2688 RELOC_DISP32);
duke@0 2689 %}
duke@0 2690
duke@0 2691 enc_class Java_Compiled_Call(method meth)
duke@0 2692 %{
duke@0 2693 // JAVA COMPILED CALL
duke@0 2694 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
duke@0 2695
duke@0 2696 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2697 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2698
duke@0 2699 // callq *disp(%rax)
duke@0 2700 cbuf.set_inst_mark();
duke@0 2701 $$$emit8$primary;
duke@0 2702 if (disp < 0x80) {
duke@0 2703 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2704 emit_d8(cbuf, disp); // Displacement
duke@0 2705 } else {
duke@0 2706 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2707 emit_d32(cbuf, disp); // Displacement
duke@0 2708 }
duke@0 2709 %}
duke@0 2710
duke@0 2711 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2712 %{
duke@0 2713 // SAL, SAR, SHR
duke@0 2714 int dstenc = $dst$$reg;
duke@0 2715 if (dstenc >= 8) {
duke@0 2716 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2717 dstenc -= 8;
duke@0 2718 }
duke@0 2719 $$$emit8$primary;
duke@0 2720 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2721 $$$emit8$shift$$constant;
duke@0 2722 %}
duke@0 2723
duke@0 2724 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2725 %{
duke@0 2726 // SAL, SAR, SHR
duke@0 2727 int dstenc = $dst$$reg;
duke@0 2728 if (dstenc < 8) {
duke@0 2729 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2730 } else {
duke@0 2731 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2732 dstenc -= 8;
duke@0 2733 }
duke@0 2734 $$$emit8$primary;
duke@0 2735 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2736 $$$emit8$shift$$constant;
duke@0 2737 %}
duke@0 2738
duke@0 2739 enc_class load_immI(rRegI dst, immI src)
duke@0 2740 %{
duke@0 2741 int dstenc = $dst$$reg;
duke@0 2742 if (dstenc >= 8) {
duke@0 2743 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2744 dstenc -= 8;
duke@0 2745 }
duke@0 2746 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2747 $$$emit32$src$$constant;
duke@0 2748 %}
duke@0 2749
duke@0 2750 enc_class load_immL(rRegL dst, immL src)
duke@0 2751 %{
duke@0 2752 int dstenc = $dst$$reg;
duke@0 2753 if (dstenc < 8) {
duke@0 2754 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2755 } else {
duke@0 2756 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2757 dstenc -= 8;
duke@0 2758 }
duke@0 2759 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2760 emit_d64(cbuf, $src$$constant);
duke@0 2761 %}
duke@0 2762
duke@0 2763 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2764 %{
duke@0 2765 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2766 int dstenc = $dst$$reg;
duke@0 2767 if (dstenc >= 8) {
duke@0 2768 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2769 dstenc -= 8;
duke@0 2770 }
duke@0 2771 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2772 $$$emit32$src$$constant;
duke@0 2773 %}
duke@0 2774
duke@0 2775 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2776 %{
duke@0 2777 int dstenc = $dst$$reg;
duke@0 2778 if (dstenc < 8) {
duke@0 2779 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2780 } else {
duke@0 2781 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2782 dstenc -= 8;
duke@0 2783 }
duke@0 2784 emit_opcode(cbuf, 0xC7);
duke@0 2785 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2786 $$$emit32$src$$constant;
duke@0 2787 %}
duke@0 2788
duke@0 2789 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2790 %{
duke@0 2791 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2792 int dstenc = $dst$$reg;
duke@0 2793 if (dstenc >= 8) {
duke@0 2794 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2795 dstenc -= 8;
duke@0 2796 }
duke@0 2797 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2798 $$$emit32$src$$constant;
duke@0 2799 %}
duke@0 2800
duke@0 2801 enc_class load_immP(rRegP dst, immP src)
duke@0 2802 %{
duke@0 2803 int dstenc = $dst$$reg;
duke@0 2804 if (dstenc < 8) {
duke@0 2805 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2806 } else {
duke@0 2807 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2808 dstenc -= 8;
duke@0 2809 }
duke@0 2810 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2811 // This next line should be generated from ADLC
duke@0 2812 if ($src->constant_is_oop()) {
duke@0 2813 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
duke@0 2814 } else {
duke@0 2815 emit_d64(cbuf, $src$$constant);
duke@0 2816 }
duke@0 2817 %}
duke@0 2818
duke@0 2819 enc_class load_immF(regF dst, immF con)
duke@0 2820 %{
duke@0 2821 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 2822 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2823 emit_float_constant(cbuf, $con$$constant);
duke@0 2824 %}
duke@0 2825
duke@0 2826 enc_class load_immD(regD dst, immD con)
duke@0 2827 %{
duke@0 2828 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 2829 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2830 emit_double_constant(cbuf, $con$$constant);
duke@0 2831 %}
duke@0 2832
duke@0 2833 enc_class load_conF (regF dst, immF con) %{ // Load float constant
duke@0 2834 emit_opcode(cbuf, 0xF3);
duke@0 2835 if ($dst$$reg >= 8) {
duke@0 2836 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2837 }
duke@0 2838 emit_opcode(cbuf, 0x0F);
duke@0 2839 emit_opcode(cbuf, 0x10);
duke@0 2840 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2841 emit_float_constant(cbuf, $con$$constant);
duke@0 2842 %}
duke@0 2843
duke@0 2844 enc_class load_conD (regD dst, immD con) %{ // Load double constant
duke@0 2845 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
duke@0 2846 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 2847 if ($dst$$reg >= 8) {
duke@0 2848 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2849 }
duke@0 2850 emit_opcode(cbuf, 0x0F);
duke@0 2851 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 2852 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
duke@0 2853 emit_double_constant(cbuf, $con$$constant);
duke@0 2854 %}
duke@0 2855
duke@0 2856 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2857 enc_class enc_copy(rRegI dst, rRegI src)
duke@0 2858 %{
duke@0 2859 encode_copy(cbuf, $dst$$reg, $src$$reg);
duke@0 2860 %}
duke@0 2861
duke@0 2862 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
duke@0 2863 enc_class enc_CopyXD( RegD dst, RegD src ) %{
duke@0 2864 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
duke@0 2865 %}
duke@0 2866
duke@0 2867 enc_class enc_copy_always(rRegI dst, rRegI src)
duke@0 2868 %{
duke@0 2869 int srcenc = $src$$reg;
duke@0 2870 int dstenc = $dst$$reg;
duke@0 2871
duke@0 2872 if (dstenc < 8) {
duke@0 2873 if (srcenc >= 8) {
duke@0 2874 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2875 srcenc -= 8;
duke@0 2876 }
duke@0 2877 } else {
duke@0 2878 if (srcenc < 8) {
duke@0 2879 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2880 } else {
duke@0 2881 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2882 srcenc -= 8;
duke@0 2883 }
duke@0 2884 dstenc -= 8;
duke@0 2885 }
duke@0 2886
duke@0 2887 emit_opcode(cbuf, 0x8B);
duke@0 2888 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2889 %}
duke@0 2890
duke@0 2891 enc_class enc_copy_wide(rRegL dst, rRegL src)
duke@0 2892 %{
duke@0 2893 int srcenc = $src$$reg;
duke@0 2894 int dstenc = $dst$$reg;
duke@0 2895
duke@0 2896 if (dstenc != srcenc) {
duke@0 2897 if (dstenc < 8) {
duke@0 2898 if (srcenc < 8) {
duke@0 2899 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2900 } else {
duke@0 2901 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2902 srcenc -= 8;
duke@0 2903 }
duke@0 2904 } else {
duke@0 2905 if (srcenc < 8) {
duke@0 2906 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2907 } else {
duke@0 2908 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2909 srcenc -= 8;
duke@0 2910 }
duke@0 2911 dstenc -= 8;
duke@0 2912 }
duke@0 2913 emit_opcode(cbuf, 0x8B);
duke@0 2914 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2915 }
duke@0 2916 %}
duke@0 2917
duke@0 2918 enc_class Con32(immI src)
duke@0 2919 %{
duke@0 2920 // Output immediate
duke@0 2921 $$$emit32$src$$constant;
duke@0 2922 %}
duke@0 2923
duke@0 2924 enc_class Con64(immL src)
duke@0 2925 %{
duke@0 2926 // Output immediate
duke@0 2927 emit_d64($src$$constant);
duke@0 2928 %}
duke@0 2929
duke@0 2930 enc_class Con32F_as_bits(immF src)
duke@0 2931 %{
duke@0 2932 // Output Float immediate bits
duke@0 2933 jfloat jf = $src$$constant;
duke@0 2934 jint jf_as_bits = jint_cast(jf);
duke@0 2935 emit_d32(cbuf, jf_as_bits);
duke@0 2936 %}
duke@0 2937
duke@0 2938 enc_class Con16(immI src)
duke@0 2939 %{
duke@0 2940 // Output immediate
duke@0 2941 $$$emit16$src$$constant;
duke@0 2942 %}
duke@0 2943
duke@0 2944 // How is this different from Con32??? XXX
duke@0 2945 enc_class Con_d32(immI src)
duke@0 2946 %{
duke@0 2947 emit_d32(cbuf,$src$$constant);
duke@0 2948 %}
duke@0 2949
duke@0 2950 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2951 // Output immediate memory reference
duke@0 2952 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2953 emit_d32(cbuf, 0x00);
duke@0 2954 %}
duke@0 2955
duke@0 2956 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
duke@0 2957 MacroAssembler masm(&cbuf);
duke@0 2958
duke@0 2959 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2960 Register dest_reg = as_Register($dest$$reg);
duke@0 2961 address table_base = masm.address_table_constant(_index2label);
duke@0 2962
duke@0 2963 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 2964 // to do that and the compiler is using that register as one it can allocate.
duke@0 2965 // So we build it all by hand.
duke@0 2966 // Address index(noreg, switch_reg, Address::times_1);
duke@0 2967 // ArrayAddress dispatch(table, index);
duke@0 2968
duke@0 2969 Address dispatch(dest_reg, switch_reg, Address::times_1);
duke@0 2970
duke@0 2971 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 2972 masm.jmp(dispatch);
duke@0 2973 %}
duke@0 2974
duke@0 2975 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
duke@0 2976 MacroAssembler masm(&cbuf);
duke@0 2977
duke@0 2978 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2979 Register dest_reg = as_Register($dest$$reg);
duke@0 2980 address table_base = masm.address_table_constant(_index2label);
duke@0 2981
duke@0 2982 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 2983 // to do that and the compiler is using that register as one it can allocate.
duke@0 2984 // So we build it all by hand.
duke@0 2985 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
duke@0 2986 // ArrayAddress dispatch(table, index);
duke@0 2987
duke@0 2988 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
duke@0 2989
duke@0 2990 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 2991 masm.jmp(dispatch);
duke@0 2992 %}
duke@0 2993
duke@0 2994 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
duke@0 2995 MacroAssembler masm(&cbuf);
duke@0 2996
duke@0 2997 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2998 Register dest_reg = as_Register($dest$$reg);
duke@0 2999 address table_base = masm.address_table_constant(_index2label);
duke@0 3000
duke@0 3001 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
duke@0 3002 // to do that and the compiler is using that register as one it can allocate.
duke@0 3003 // So we build it all by hand.
duke@0 3004 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
duke@0 3005 // ArrayAddress dispatch(table, index);
duke@0 3006
duke@0 3007 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
duke@0 3008 masm.lea(dest_reg, InternalAddress(table_base));
duke@0 3009 masm.jmp(dispatch);
duke@0 3010
duke@0 3011 %}
duke@0 3012
duke@0 3013 enc_class lock_prefix()
duke@0 3014 %{
duke@0 3015 if (os::is_MP()) {
duke@0 3016 emit_opcode(cbuf, 0xF0); // lock
duke@0 3017 }
duke@0 3018 %}
duke@0 3019
duke@0 3020 enc_class REX_mem(memory mem)
duke@0 3021 %{
duke@0 3022 if ($mem$$base >= 8) {
duke@0 3023 if ($mem$$index < 8) {
duke@0 3024 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3025 } else {
duke@0 3026 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3027 }
duke@0 3028 } else {
duke@0 3029 if ($mem$$index >= 8) {
duke@0 3030 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3031 }
duke@0 3032 }
duke@0 3033 %}
duke@0 3034
duke@0 3035 enc_class REX_mem_wide(memory mem)
duke@0 3036 %{
duke@0 3037 if ($mem$$base >= 8) {
duke@0 3038 if ($mem$$index < 8) {
duke@0 3039 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3040 } else {
duke@0 3041 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3042 }
duke@0 3043 } else {
duke@0 3044 if ($mem$$index < 8) {
duke@0 3045 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3046 } else {
duke@0 3047 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3048 }
duke@0 3049 }
duke@0 3050 %}
duke@0 3051
duke@0 3052 // for byte regs
duke@0 3053 enc_class REX_breg(rRegI reg)
duke@0 3054 %{
duke@0 3055 if ($reg$$reg >= 4) {
duke@0 3056 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3057 }
duke@0 3058 %}
duke@0 3059
duke@0 3060 // for byte regs
duke@0 3061 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 3062 %{
duke@0 3063 if ($dst$$reg < 8) {
duke@0 3064 if ($src$$reg >= 4) {
duke@0 3065 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3066 }
duke@0 3067 } else {
duke@0 3068 if ($src$$reg < 8) {
duke@0 3069 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3070 } else {
duke@0 3071 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3072 }
duke@0 3073 }
duke@0 3074 %}
duke@0 3075
duke@0 3076 // for byte regs
duke@0 3077 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 3078 %{
duke@0 3079 if ($reg$$reg < 8) {
duke@0 3080 if ($mem$$base < 8) {
duke@0 3081 if ($mem$$index >= 8) {
duke@0 3082 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3083 } else if ($reg$$reg >= 4) {
duke@0 3084 emit_opcode(cbuf, Assembler::REX);
duke@0 3085 }
duke@0 3086 } else {
duke@0 3087 if ($mem$$index < 8) {
duke@0 3088 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3089 } else {
duke@0 3090 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3091 }
duke@0 3092 }
duke@0 3093 } else {
duke@0 3094 if ($mem$$base < 8) {
duke@0 3095 if ($mem$$index < 8) {
duke@0 3096 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3097 } else {
duke@0 3098 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3099 }
duke@0 3100 } else {
duke@0 3101 if ($mem$$index < 8) {
duke@0 3102 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3103 } else {
duke@0 3104 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3105 }
duke@0 3106 }
duke@0 3107 }
duke@0 3108 %}
duke@0 3109
duke@0 3110 enc_class REX_reg(rRegI reg)
duke@0 3111 %{
duke@0 3112 if ($reg$$reg >= 8) {
duke@0 3113 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3114 }
duke@0 3115 %}
duke@0 3116
duke@0 3117 enc_class REX_reg_wide(rRegI reg)
duke@0 3118 %{
duke@0 3119 if ($reg$$reg < 8) {
duke@0 3120 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3121 } else {
duke@0 3122 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3123 }
duke@0 3124 %}
duke@0 3125
duke@0 3126 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 3127 %{
duke@0 3128 if ($dst$$reg < 8) {
duke@0 3129 if ($src$$reg >= 8) {
duke@0 3130 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3131 }
duke@0 3132 } else {
duke@0 3133 if ($src$$reg < 8) {
duke@0 3134 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3135 } else {
duke@0 3136 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3137 }
duke@0 3138 }
duke@0 3139 %}
duke@0 3140
duke@0 3141 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 3142 %{
duke@0 3143 if ($dst$$reg < 8) {
duke@0 3144 if ($src$$reg < 8) {
duke@0 3145 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3146 } else {
duke@0 3147 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3148 }
duke@0 3149 } else {
duke@0 3150 if ($src$$reg < 8) {
duke@0 3151 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3152 } else {
duke@0 3153 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3154 }
duke@0 3155 }
duke@0 3156 %}
duke@0 3157
duke@0 3158 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 3159 %{
duke@0 3160 if ($reg$$reg < 8) {
duke@0 3161 if ($mem$$base < 8) {
duke@0 3162 if ($mem$$index >= 8) {
duke@0 3163 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3164 }
duke@0 3165 } else {
duke@0 3166 if ($mem$$index < 8) {
duke@0 3167 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3168 } else {
duke@0 3169 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3170 }
duke@0 3171 }
duke@0 3172 } else {
duke@0 3173 if ($mem$$base < 8) {
duke@0 3174 if ($mem$$index < 8) {
duke@0 3175 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3176 } else {
duke@0 3177 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3178 }
duke@0 3179 } else {
duke@0 3180 if ($mem$$index < 8) {
duke@0 3181 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3182 } else {
duke@0 3183 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3184 }
duke@0 3185 }
duke@0 3186 }
duke@0 3187 %}
duke@0 3188
duke@0 3189 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 3190 %{
duke@0 3191 if ($reg$$reg < 8) {
duke@0 3192 if ($mem$$base < 8) {
duke@0 3193 if ($mem$$index < 8) {
duke@0 3194 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3195 } else {
duke@0 3196 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3197 }
duke@0 3198 } else {
duke@0 3199 if ($mem$$index < 8) {
duke@0 3200 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3201 } else {
duke@0 3202 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3203 }
duke@0 3204 }
duke@0 3205 } else {
duke@0 3206 if ($mem$$base < 8) {
duke@0 3207 if ($mem$$index < 8) {
duke@0 3208 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3209 } else {
duke@0 3210 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 3211 }
duke@0 3212 } else {
duke@0 3213 if ($mem$$index < 8) {
duke@0 3214 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3215 } else {
duke@0 3216 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 3217 }
duke@0 3218 }
duke@0 3219 }
duke@0 3220 %}
duke@0 3221
duke@0 3222 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 3223 %{
duke@0 3224 // High registers handle in encode_RegMem
duke@0 3225 int reg = $ereg$$reg;
duke@0 3226 int base = $mem$$base;
duke@0 3227 int index = $mem$$index;
duke@0 3228 int scale = $mem$$scale;
duke@0 3229 int disp = $mem$$disp;
duke@0 3230 bool disp_is_oop = $mem->disp_is_oop();
duke@0 3231
duke@0 3232 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
duke@0 3233 %}
duke@0 3234
duke@0 3235 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 3236 %{
duke@0 3237 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 3238
duke@0 3239 // High registers handle in encode_RegMem
duke@0 3240 int base = $mem$$base;
duke@0 3241 int index = $mem$$index;
duke@0 3242 int scale = $mem$$scale;
duke@0 3243 int displace = $mem$$disp;
duke@0 3244
duke@0 3245 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
duke@0 3246 // working with static
duke@0 3247 // globals
duke@0 3248 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
duke@0 3249 disp_is_oop);
duke@0 3250 %}
duke@0 3251
duke@0 3252 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 3253 %{
duke@0 3254 int reg_encoding = $dst$$reg;
duke@0 3255 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 3256 int index = 0x04; // 0x04 indicates no index
duke@0 3257 int scale = 0x00; // 0x00 indicates no scale
duke@0 3258 int displace = $src1$$constant; // 0x00 indicates no displacement
duke@0 3259 bool disp_is_oop = false;
duke@0 3260 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
duke@0 3261 disp_is_oop);
duke@0 3262 %}
duke@0 3263
duke@0 3264 enc_class neg_reg(rRegI dst)
duke@0 3265 %{
duke@0 3266 int dstenc = $dst$$reg;
duke@0 3267 if (dstenc >= 8) {
duke@0 3268 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3269 dstenc -= 8;
duke@0 3270 }
duke@0 3271 // NEG $dst
duke@0 3272 emit_opcode(cbuf, 0xF7);
duke@0 3273 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3274 %}
duke@0 3275
duke@0 3276 enc_class neg_reg_wide(rRegI dst)
duke@0 3277 %{
duke@0 3278 int dstenc = $dst$$reg;
duke@0 3279 if (dstenc < 8) {
duke@0 3280 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3281 } else {
duke@0 3282 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3283 dstenc -= 8;
duke@0 3284 }
duke@0 3285 // NEG $dst
duke@0 3286 emit_opcode(cbuf, 0xF7);
duke@0 3287 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3288 %}
duke@0 3289
duke@0 3290 enc_class setLT_reg(rRegI dst)
duke@0 3291 %{
duke@0 3292 int dstenc = $dst$$reg;
duke@0 3293 if (dstenc >= 8) {
duke@0 3294 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3295 dstenc -= 8;
duke@0 3296 } else if (dstenc >= 4) {
duke@0 3297 emit_opcode(cbuf, Assembler::REX);
duke@0 3298 }
duke@0 3299 // SETLT $dst
duke@0 3300 emit_opcode(cbuf, 0x0F);
duke@0 3301 emit_opcode(cbuf, 0x9C);
duke@0 3302 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3303 %}
duke@0 3304
duke@0 3305 enc_class setNZ_reg(rRegI dst)
duke@0 3306 %{
duke@0 3307 int dstenc = $dst$$reg;
duke@0 3308 if (dstenc >= 8) {
duke@0 3309 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3310 dstenc -= 8;
duke@0 3311 } else if (dstenc >= 4) {
duke@0 3312 emit_opcode(cbuf, Assembler::REX);
duke@0 3313 }
duke@0 3314 // SETNZ $dst
duke@0 3315 emit_opcode(cbuf, 0x0F);
duke@0 3316 emit_opcode(cbuf, 0x95);
duke@0 3317 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3318 %}
duke@0 3319
duke@0 3320 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
duke@0 3321 rcx_RegI tmp)
duke@0 3322 %{
duke@0 3323 // cadd_cmpLT
duke@0 3324
duke@0 3325 int tmpReg = $tmp$$reg;
duke@0 3326
duke@0 3327 int penc = $p$$reg;
duke@0 3328 int qenc = $q$$reg;
duke@0 3329 int yenc = $y$$reg;
duke@0 3330
duke@0 3331 // subl $p,$q
duke@0 3332 if (penc < 8) {
duke@0 3333 if (qenc >= 8) {
duke@0 3334 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3335 }
duke@0 3336 } else {
duke@0 3337 if (qenc < 8) {
duke@0 3338 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3339 } else {
duke@0 3340 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3341 }
duke@0 3342 }
duke@0 3343 emit_opcode(cbuf, 0x2B);
duke@0 3344 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
duke@0 3345
duke@0 3346 // sbbl $tmp, $tmp
duke@0 3347 emit_opcode(cbuf, 0x1B);
duke@0 3348 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
duke@0 3349
duke@0 3350 // andl $tmp, $y
duke@0 3351 if (yenc >= 8) {
duke@0 3352 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3353 }
duke@0 3354 emit_opcode(cbuf, 0x23);
duke@0 3355 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
duke@0 3356
duke@0 3357 // addl $p,$tmp
duke@0 3358 if (penc >= 8) {
duke@0 3359 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3360 }
duke@0 3361 emit_opcode(cbuf, 0x03);
duke@0 3362 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
duke@0 3363 %}
duke@0 3364
duke@0 3365 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 3366 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 3367 %{
duke@0 3368 int src1enc = $src1$$reg;
duke@0 3369 int src2enc = $src2$$reg;
duke@0 3370 int dstenc = $dst$$reg;
duke@0 3371
duke@0 3372 // cmpq $src1, $src2
duke@0 3373 if (src1enc < 8) {
duke@0 3374 if (src2enc < 8) {
duke@0 3375 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3376 } else {
duke@0 3377 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3378 }
duke@0 3379 } else {
duke@0 3380 if (src2enc < 8) {
duke@0 3381 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3382 } else {
duke@0 3383 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3384 }
duke@0 3385 }
duke@0 3386 emit_opcode(cbuf, 0x3B);
duke@0 3387 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 3388
duke@0 3389 // movl $dst, -1
duke@0 3390 if (dstenc >= 8) {
duke@0 3391 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3392 }
duke@0 3393 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 3394 emit_d32(cbuf, -1);
duke@0 3395
duke@0 3396 // jl,s done
duke@0 3397 emit_opcode(cbuf, 0x7C);
duke@0 3398 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 3399
duke@0 3400 // setne $dst
duke@0 3401 if (dstenc >= 4) {
duke@0 3402 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3403 }
duke@0 3404 emit_opcode(cbuf, 0x0F);
duke@0 3405 emit_opcode(cbuf, 0x95);
duke@0 3406 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 3407
duke@0 3408 // movzbl $dst, $dst
duke@0 3409 if (dstenc >= 4) {
duke@0 3410 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 3411 }
duke@0 3412 emit_opcode(cbuf, 0x0F);
duke@0 3413 emit_opcode(cbuf, 0xB6);
duke@0 3414 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 3415 %}
duke@0 3416
duke@0 3417 enc_class Push_ResultXD(regD dst) %{
duke@0 3418 int dstenc = $dst$$reg;
duke@0 3419
duke@0 3420 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
duke@0 3421
duke@0 3422 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
duke@0 3423 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 3424 if (dstenc >= 8) {
duke@0 3425 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3426 }
duke@0 3427 emit_opcode (cbuf, 0x0F );
duke@0 3428 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
duke@0 3429 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3430
duke@0 3431 // add rsp,8
duke@0 3432 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3433 emit_opcode(cbuf,0x83);
duke@0 3434 emit_rm(cbuf,0x3, 0x0, RSP_enc);
duke@0 3435 emit_d8(cbuf,0x08);
duke@0 3436 %}
duke@0 3437
duke@0 3438 enc_class Push_SrcXD(regD src) %{
duke@0 3439 int srcenc = $src$$reg;
duke@0 3440
duke@0 3441 // subq rsp,#8
duke@0 3442 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3443 emit_opcode(cbuf, 0x83);
duke@0 3444 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3445 emit_d8(cbuf, 0x8);
duke@0 3446
duke@0 3447 // movsd [rsp],src
duke@0 3448 emit_opcode(cbuf, 0xF2);
duke@0 3449 if (srcenc >= 8) {
duke@0 3450 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3451 }
duke@0 3452 emit_opcode(cbuf, 0x0F);
duke@0 3453 emit_opcode(cbuf, 0x11);
duke@0 3454 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3455
duke@0 3456 // fldd [rsp]
duke@0 3457 emit_opcode(cbuf, 0x66);
duke@0 3458 emit_opcode(cbuf, 0xDD);
duke@0 3459 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
duke@0 3460 %}
duke@0 3461
duke@0 3462
duke@0 3463 enc_class movq_ld(regD dst, memory mem) %{
duke@0 3464 MacroAssembler _masm(&cbuf);
duke@0 3465 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
duke@0 3466 __ movq(as_XMMRegister($dst$$reg), madr);
duke@0 3467 %}
duke@0 3468
duke@0 3469 enc_class movq_st(memory mem, regD src) %{
duke@0 3470 MacroAssembler _masm(&cbuf);
duke@0 3471 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
duke@0 3472 __ movq(madr, as_XMMRegister($src$$reg));
duke@0 3473 %}
duke@0 3474
duke@0 3475 enc_class pshufd_8x8(regF dst, regF src) %{
duke@0 3476 MacroAssembler _masm(&cbuf);
duke@0 3477
duke@0 3478 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
duke@0 3479 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
duke@0 3480 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
duke@0 3481 %}
duke@0 3482
duke@0 3483 enc_class pshufd_4x16(regF dst, regF src) %{
duke@0 3484 MacroAssembler _masm(&cbuf);
duke@0 3485
duke@0 3486 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
duke@0 3487 %}
duke@0 3488
duke@0 3489 enc_class pshufd(regD dst, regD src, int mode) %{
duke@0 3490 MacroAssembler _masm(&cbuf);
duke@0 3491
duke@0 3492 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
duke@0 3493 %}
duke@0 3494
duke@0 3495 enc_class pxor(regD dst, regD src) %{
duke@0 3496 MacroAssembler _masm(&cbuf);
duke@0 3497
duke@0 3498 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
duke@0 3499 %}
duke@0 3500
duke@0 3501 enc_class mov_i2x(regD dst, rRegI src) %{
duke@0 3502 MacroAssembler _masm(&cbuf);
duke@0 3503
duke@0 3504 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
duke@0 3505 %}
duke@0 3506
duke@0 3507 // obj: object to lock
duke@0 3508 // box: box address (header location) -- killed
duke@0 3509 // tmp: rax -- killed
duke@0 3510 // scr: rbx -- killed
duke@0 3511 //
duke@0 3512 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 3513 // from i486.ad. See that file for comments.
duke@0 3514 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 3515 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 3516
duke@0 3517
duke@0 3518 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 3519 %{
duke@0 3520 Register objReg = as_Register((int)$obj$$reg);
duke@0 3521 Register boxReg = as_Register((int)$box$$reg);
duke@0 3522 Register tmpReg = as_Register($tmp$$reg);
duke@0 3523 Register scrReg = as_Register($scr$$reg);
duke@0 3524 MacroAssembler masm(&cbuf);
duke@0 3525
duke@0 3526 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 3527 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 3528 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 3529
duke@0 3530 if (_counters != NULL) {
duke@0 3531 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 3532 }
duke@0 3533 if (EmitSync & 1) {
never@304 3534 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3535 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3536 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 3537 } else
duke@0 3538 if (EmitSync & 2) {
duke@0 3539 Label DONE_LABEL;
duke@0 3540 if (UseBiasedLocking) {
duke@0 3541 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 3542 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 3543 }
never@304 3544 // QQQ was movl...
never@304 3545 masm.movptr(tmpReg, 0x1);
never@304 3546 masm.orptr(tmpReg, Address(objReg, 0));
never@304 3547 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3548 if (os::is_MP()) {
duke@0 3549 masm.lock();
duke@0 3550 }
never@304 3551 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3552 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 3553
duke@0 3554 // Recursive locking
never@304 3555 masm.subptr(tmpReg, rsp);
never@304 3556 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3557 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3558
duke@0 3559 masm.bind(DONE_LABEL);
duke@0 3560 masm.nop(); // avoid branch to branch
duke@0 3561 } else {
duke@0 3562 Label DONE_LABEL, IsInflated, Egress;
duke@0 3563
never@304 3564 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3565 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
never@304 3566 masm.jcc (Assembler::notZero, IsInflated) ;
never@304 3567
duke@0 3568 // it's stack-locked, biased or neutral
duke@0 3569 // TODO: optimize markword triage order to reduce the number of
duke@0 3570 // conditional branches in the most common cases.
duke@0 3571 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 3572 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 3573 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 3574
duke@0 3575 if (UseBiasedLocking) {
duke@0 3576 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 3577 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 3578 }
duke@0 3579
never@304 3580 // was q will it destroy high?
never@304 3581 masm.orl (tmpReg, 1) ;
never@304 3582 masm.movptr(Address(boxReg, 0), tmpReg) ;
never@304 3583 if (os::is_MP()) { masm.lock(); }
never@304 3584 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3585 if (_counters != NULL) {
duke@0 3586 masm.cond_inc32(Assembler::equal,
duke@0 3587 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3588 }
duke@0 3589 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 3590
duke@0 3591 // Recursive locking
never@304 3592 masm.subptr(tmpReg, rsp);
never@304 3593 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3594 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3595 if (_counters != NULL) {
duke@0 3596 masm.cond_inc32(Assembler::equal,
duke@0 3597 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3598 }
duke@0 3599 masm.jmp (DONE_LABEL) ;
duke@0 3600
duke@0 3601 masm.bind (IsInflated) ;
duke@0 3602 // It's inflated
duke@0 3603
duke@0 3604 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 3605 // relocating (deferring) the following ST.
duke@0 3606 // We should also think about trying a CAS without having
duke@0 3607 // fetched _owner. If the CAS is successful we may
duke@0 3608 // avoid an RTO->RTS upgrade on the $line.
never@304 3609 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3610 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3611
never@304 3612 masm.mov (boxReg, tmpReg) ;
never@304 3613 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3614 masm.testptr(tmpReg, tmpReg) ;
never@304 3615 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 3616
duke@0 3617 // It's inflated and appears unlocked
never@304 3618 if (os::is_MP()) { masm.lock(); }
never@304 3619 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 3620 // Intentional fall-through into DONE_LABEL ...
duke@0 3621
duke@0 3622 masm.bind (DONE_LABEL) ;
duke@0 3623 masm.nop () ; // avoid jmp to jmp
duke@0 3624 }
duke@0 3625 %}
duke@0 3626
duke@0 3627 // obj: object to unlock
duke@0 3628 // box: box address (displaced header location), killed
duke@0 3629 // RBX: killed tmp; cannot be obj nor box
duke@0 3630 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 3631 %{
duke@0 3632
duke@0 3633 Register objReg = as_Register($obj$$reg);
duke@0 3634 Register boxReg = as_Register($box$$reg);
duke@0 3635 Register tmpReg = as_Register($tmp$$reg);
duke@0 3636 MacroAssembler masm(&cbuf);
duke@0 3637
never@304 3638 if (EmitSync & 4) {
never@304 3639 masm.cmpptr(rsp, 0) ;
duke@0 3640 } else
duke@0 3641 if (EmitSync & 8) {
duke@0 3642 Label DONE_LABEL;
duke@0 3643 if (UseBiasedLocking) {
duke@0 3644 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3645 }
duke@0 3646
duke@0 3647 // Check whether the displaced header is 0
duke@0 3648 //(=> recursive unlock)
never@304 3649 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 3650 masm.testptr(tmpReg, tmpReg);
duke@0 3651 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 3652
duke@0 3653 // If not recursive lock, reset the header to displaced header
duke@0 3654 if (os::is_MP()) {
duke@0 3655 masm.lock();
duke@0 3656 }
never@304 3657 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3658 masm.bind(DONE_LABEL);
duke@0 3659 masm.nop(); // avoid branch to branch
duke@0 3660 } else {
duke@0 3661 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 3662
duke@0 3663 if (UseBiasedLocking) {
duke@0 3664 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3665 }
never@304 3666
never@304 3667 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3668 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
never@304 3669 masm.jcc (Assembler::zero, DONE_LABEL) ;
never@304 3670 masm.testl (tmpReg, 0x02) ;
never@304 3671 masm.jcc (Assembler::zero, Stacked) ;
never@304 3672
duke@0 3673 // It's inflated
never@304 3674 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3675 masm.xorptr(boxReg, r15_thread) ;
never@304 3676 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
never@304 3677 masm.jcc (Assembler::notZero, DONE_LABEL) ;
never@304 3678 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
never@304 3679 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
never@304 3680 masm.jcc (Assembler::notZero, CheckSucc) ;
never@304 3681 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
never@304 3682 masm.jmp (DONE_LABEL) ;
never@304 3683
never@304 3684 if ((EmitSync & 65536) == 0) {
duke@0 3685 Label LSuccess, LGoSlowPath ;
duke@0 3686 masm.bind (CheckSucc) ;
never@304 3687 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3688 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 3689
duke@0 3690 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 3691 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 3692 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 3693 // are all faster when the write buffer is populated.
never@304 3694 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3695 if (os::is_MP()) {
never@304 3696 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 3697 }
never@304 3698 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3699 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 3700
never@304 3701 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 3702 if (os::is_MP()) { masm.lock(); }
never@304 3703 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 3704 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 3705 // Intentional fall-through into slow-path
duke@0 3706
duke@0 3707 masm.bind (LGoSlowPath) ;
duke@0 3708 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 3709 masm.jmp (DONE_LABEL) ;
duke@0 3710
duke@0 3711 masm.bind (LSuccess) ;
duke@0 3712 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 3713 masm.jmp (DONE_LABEL) ;
duke@0 3714 }
duke@0 3715
never@304 3716 masm.bind (Stacked) ;
never@304 3717 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
never@304 3718 if (os::is_MP()) { masm.lock(); }
never@304 3719 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3720
duke@0 3721 if (EmitSync & 65536) {
duke@0 3722 masm.bind (CheckSucc) ;
duke@0 3723 }
duke@0 3724 masm.bind(DONE_LABEL);
duke@0 3725 if (EmitSync & 32768) {
duke@0 3726 masm.nop(); // avoid branch to branch
duke@0 3727 }
duke@0 3728 }
duke@0 3729 %}
duke@0 3730
duke@0 3731 enc_class enc_String_Compare()
duke@0 3732 %{
duke@0 3733 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL,
duke@0 3734 POP_LABEL, DONE_LABEL, CONT_LABEL,
duke@0 3735 WHILE_HEAD_LABEL;
duke@0 3736 MacroAssembler masm(&cbuf);
duke@0 3737
duke@0 3738 // Get the first character position in both strings
duke@0 3739 // [8] char array, [12] offset, [16] count
duke@0 3740 int value_offset = java_lang_String::value_offset_in_bytes();
duke@0 3741 int offset_offset = java_lang_String::offset_offset_in_bytes();
duke@0 3742 int count_offset = java_lang_String::count_offset_in_bytes();
duke@0 3743 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
duke@0 3744
coleenp@113 3745 masm.load_heap_oop(rax, Address(rsi, value_offset));
duke@0 3746 masm.movl(rcx, Address(rsi, offset_offset));
never@304 3747 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
coleenp@113 3748 masm.load_heap_oop(rbx, Address(rdi, value_offset));
duke@0 3749 masm.movl(rcx, Address(rdi, offset_offset));
never@304 3750 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
duke@0 3751
duke@0 3752 // Compute the minimum of the string lengths(rsi) and the
duke@0 3753 // difference of the string lengths (stack)
duke@0 3754
duke@0 3755 masm.movl(rdi, Address(rdi, count_offset));
duke@0 3756 masm.movl(rsi, Address(rsi, count_offset));
duke@0 3757 masm.movl(rcx, rdi);
duke@0 3758 masm.subl(rdi, rsi);
never@304 3759 masm.push(rdi);
never@304 3760 masm.cmov(Assembler::lessEqual, rsi, rcx);
duke@0 3761
duke@0 3762 // Is the minimum length zero?
duke@0 3763 masm.bind(RCX_GOOD_LABEL);
duke@0 3764 masm.testl(rsi, rsi);
duke@0 3765 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
duke@0 3766
duke@0 3767 // Load first characters
duke@0 3768 masm.load_unsigned_word(rcx, Address(rbx, 0));
duke@0 3769 masm.load_unsigned_word(rdi, Address(rax, 0));
duke@0 3770
duke@0 3771 // Compare first characters
duke@0 3772 masm.subl(rcx, rdi);
duke@0 3773 masm.jcc(Assembler::notZero, POP_LABEL);
duke@0 3774 masm.decrementl(rsi);
duke@0 3775 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
duke@0 3776
duke@0 3777 {
duke@0 3778 // Check after comparing first character to see if strings are equivalent
duke@0 3779 Label LSkip2;
duke@0 3780 // Check if the strings start at same location
never@304 3781 masm.cmpptr(rbx, rax);
duke@0 3782 masm.jcc(Assembler::notEqual, LSkip2);
duke@0 3783
duke@0 3784 // Check if the length difference is zero (from stack)
duke@0 3785 masm.cmpl(Address(rsp, 0), 0x0);
duke@0 3786 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
duke@0 3787
duke@0 3788 // Strings might not be equivalent
duke@0 3789 masm.bind(LSkip2);
duke@0 3790 }
duke@0 3791
duke@0 3792 // Shift RAX and RBX to the end of the arrays, negate min
never@304 3793 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
never@304 3794 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
never@304 3795 masm.negptr(rsi);
duke@0 3796
duke@0 3797 // Compare the rest of the characters
duke@0 3798 masm.bind(WHILE_HEAD_LABEL);
duke@0 3799 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
duke@0 3800 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
duke@0 3801 masm.subl(rcx, rdi);
duke@0 3802 masm.jcc(Assembler::notZero, POP_LABEL);
never@304 3803 masm.increment(rsi);
duke@0 3804 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
duke@0 3805
duke@0 3806 // Strings are equal up to min length. Return the length difference.
duke@0 3807 masm.bind(LENGTH_DIFF_LABEL);
never@304 3808 masm.pop(rcx);
duke@0 3809 masm.jmp(DONE_LABEL);
duke@0 3810
duke@0 3811 // Discard the stored length difference
duke@0 3812 masm.bind(POP_LABEL);
never@304 3813 masm.addptr(rsp, 8);
never@304 3814
duke@0 3815 // That's it
duke@0 3816 masm.bind(DONE_LABEL);
duke@0 3817 %}
duke@0 3818
rasbold@169 3819 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, rcx_RegI result) %{
rasbold@169 3820 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
rasbold@169 3821 MacroAssembler masm(&cbuf);
rasbold@169 3822
rasbold@169 3823 Register ary1Reg = as_Register($ary1$$reg);
rasbold@169 3824 Register ary2Reg = as_Register($ary2$$reg);
rasbold@169 3825 Register tmp1Reg = as_Register($tmp1$$reg);
rasbold@169 3826 Register tmp2Reg = as_Register($tmp2$$reg);
rasbold@169 3827 Register resultReg = as_Register($result$$reg);
rasbold@169 3828
rasbold@169 3829 int length_offset = arrayOopDesc::length_offset_in_bytes();
rasbold@169 3830 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
rasbold@169 3831
rasbold@169 3832 // Check the input args
rasbold@169 3833 masm.cmpq(ary1Reg, ary2Reg);
rasbold@169 3834 masm.jcc(Assembler::equal, TRUE_LABEL);
rasbold@169 3835 masm.testq(ary1Reg, ary1Reg);
rasbold@169 3836 masm.jcc(Assembler::zero, FALSE_LABEL);
rasbold@169 3837 masm.testq(ary2Reg, ary2Reg);
rasbold@169 3838 masm.jcc(Assembler::zero, FALSE_LABEL);
rasbold@169 3839
rasbold@169 3840 // Check the lengths
rasbold@169 3841 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
rasbold@169 3842 masm.movl(resultReg, Address(ary2Reg, length_offset));
rasbold@169 3843 masm.cmpl(tmp2Reg, resultReg);
rasbold@169 3844 masm.jcc(Assembler::notEqual, FALSE_LABEL);
rasbold@169 3845 masm.testl(resultReg, resultReg);
rasbold@169 3846 masm.jcc(Assembler::zero, TRUE_LABEL);
rasbold@169 3847
rasbold@169 3848 // Get the number of 4 byte vectors to compare
rasbold@169 3849 masm.shrl(resultReg, 1);
rasbold@169 3850
rasbold@169 3851 // Check for odd-length arrays
rasbold@169 3852 masm.andl(tmp2Reg, 1);
rasbold@169 3853 masm.testl(tmp2Reg, tmp2Reg);
rasbold@169 3854 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
rasbold@169 3855
rasbold@169 3856 // Compare 2-byte "tail" at end of arrays
rasbold@169 3857 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
rasbold@169 3858 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
rasbold@169 3859 masm.cmpl(tmp1Reg, tmp2Reg);
rasbold@169 3860 masm.jcc(Assembler::notEqual, FALSE_LABEL);
rasbold@169 3861 masm.testl(resultReg, resultReg);
rasbold@169 3862 masm.jcc(Assembler::zero, TRUE_LABEL);
rasbold@169 3863
rasbold@169 3864 // Setup compare loop
rasbold@169 3865 masm.bind(COMPARE_LOOP_HDR);
rasbold@169 3866 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
rasbold@169 3867 masm.leaq(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
rasbold@169 3868 masm.leaq(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
rasbold@169 3869 masm.negq(resultReg);
rasbold@169 3870
rasbold@169 3871 // 4-byte-wide compare loop
rasbold@169 3872 masm.bind(COMPARE_LOOP);
rasbold@169 3873 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
rasbold@169 3874 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
rasbold@169 3875 masm.cmpl(ary1Reg, ary2Reg);
rasbold@169 3876 masm.jcc(Assembler::notEqual, FALSE_LABEL);
rasbold@169 3877 masm.incrementq(resultReg);
rasbold@169 3878 masm.jcc(Assembler::notZero, COMPARE_LOOP);
rasbold@169 3879
rasbold@169 3880 masm.bind(TRUE_LABEL);
rasbold@169 3881 masm.movl(resultReg, 1); // return true
rasbold@169 3882 masm.jmp(DONE_LABEL);
rasbold@169 3883
rasbold@169 3884 masm.bind(FALSE_LABEL);
rasbold@169 3885 masm.xorl(resultReg, resultReg); // return false
rasbold@169 3886
rasbold@169 3887 // That's it
rasbold@169 3888 masm.bind(DONE_LABEL);
rasbold@169 3889 %}
rasbold@169 3890
duke@0 3891 enc_class enc_rethrow()
duke@0 3892 %{
duke@0 3893 cbuf.set_inst_mark();
duke@0 3894 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 3895 emit_d32_reloc(cbuf,
duke@0 3896 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4),
duke@0 3897 runtime_call_Relocat