annotate src/cpu/x86/vm/x86_64.ad @ 2248:7e88bdae86ec

7029017: Additional architecture support for c2 compiler Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it. Reviewed-by: kvn, never
author roland
date Fri, 25 Mar 2011 09:35:39 +0100
parents 41d4973cf100
children b40d4fa697bf
rev   line source
duke@0 1 //
kvn@2167 2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
duke@0 135 // Word a in each register holds a Float, words ab hold a Double. We
duke@0 136 // currently do not use the SIMD capabilities, so registers cd are
duke@0 137 // unused at the moment.
duke@0 138 // XMM8-XMM15 must be encoded with REX.
duke@0 139 // Linux ABI: No register preserved across function calls
duke@0 140 // XMM0-XMM7 might hold parameters
duke@0 141 // Windows ABI: XMM6-XMM15 preserved across function calls
duke@0 142 // XMM0-XMM3 might hold parameters
duke@0 143
duke@0 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
duke@0 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
duke@0 146
duke@0 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
duke@0 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
duke@0 149
duke@0 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
duke@0 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
duke@0 152
duke@0 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
duke@0 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
duke@0 155
duke@0 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
duke@0 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
duke@0 158
duke@0 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
duke@0 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
duke@0 161
duke@0 162 #ifdef _WIN64
duke@0 163
duke@0 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
duke@0 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 166
duke@0 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
duke@0 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 169
duke@0 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
duke@0 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 172
duke@0 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
duke@0 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 175
duke@0 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
duke@0 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 178
duke@0 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
duke@0 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 181
duke@0 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
duke@0 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 184
duke@0 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
duke@0 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 187
duke@0 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
duke@0 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 190
duke@0 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
duke@0 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 193
duke@0 194 #else
duke@0 195
duke@0 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
duke@0 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 198
duke@0 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
duke@0 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 201
duke@0 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
duke@0 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 204
duke@0 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
duke@0 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 207
duke@0 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
duke@0 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 210
duke@0 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
duke@0 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 213
duke@0 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
duke@0 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 216
duke@0 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
duke@0 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 219
duke@0 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
duke@0 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 222
duke@0 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
duke@0 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 225
duke@0 226 #endif // _WIN64
duke@0 227
duke@0 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
duke@0 229
duke@0 230 // Specify priority of register selection within phases of register
duke@0 231 // allocation. Highest priority is first. A useful heuristic is to
duke@0 232 // give registers a low priority when they are required by machine
duke@0 233 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 234 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 235 // which participate in fixed calling sequences should come last.
duke@0 236 // Registers which are used as pairs must fall on an even boundary.
duke@0 237
duke@0 238 alloc_class chunk0(R10, R10_H,
duke@0 239 R11, R11_H,
duke@0 240 R8, R8_H,
duke@0 241 R9, R9_H,
duke@0 242 R12, R12_H,
duke@0 243 RCX, RCX_H,
duke@0 244 RBX, RBX_H,
duke@0 245 RDI, RDI_H,
duke@0 246 RDX, RDX_H,
duke@0 247 RSI, RSI_H,
duke@0 248 RAX, RAX_H,
duke@0 249 RBP, RBP_H,
duke@0 250 R13, R13_H,
duke@0 251 R14, R14_H,
duke@0 252 R15, R15_H,
duke@0 253 RSP, RSP_H);
duke@0 254
duke@0 255 // XXX probably use 8-15 first on Linux
duke@0 256 alloc_class chunk1(XMM0, XMM0_H,
duke@0 257 XMM1, XMM1_H,
duke@0 258 XMM2, XMM2_H,
duke@0 259 XMM3, XMM3_H,
duke@0 260 XMM4, XMM4_H,
duke@0 261 XMM5, XMM5_H,
duke@0 262 XMM6, XMM6_H,
duke@0 263 XMM7, XMM7_H,
duke@0 264 XMM8, XMM8_H,
duke@0 265 XMM9, XMM9_H,
duke@0 266 XMM10, XMM10_H,
duke@0 267 XMM11, XMM11_H,
duke@0 268 XMM12, XMM12_H,
duke@0 269 XMM13, XMM13_H,
duke@0 270 XMM14, XMM14_H,
duke@0 271 XMM15, XMM15_H);
duke@0 272
duke@0 273 alloc_class chunk2(RFLAGS);
duke@0 274
duke@0 275
duke@0 276 //----------Architecture Description Register Classes--------------------------
duke@0 277 // Several register classes are automatically defined based upon information in
duke@0 278 // this architecture description.
duke@0 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 283 //
duke@0 284
duke@0 285 // Class for all pointer registers (including RSP)
duke@0 286 reg_class any_reg(RAX, RAX_H,
duke@0 287 RDX, RDX_H,
duke@0 288 RBP, RBP_H,
duke@0 289 RDI, RDI_H,
duke@0 290 RSI, RSI_H,
duke@0 291 RCX, RCX_H,
duke@0 292 RBX, RBX_H,
duke@0 293 RSP, RSP_H,
duke@0 294 R8, R8_H,
duke@0 295 R9, R9_H,
duke@0 296 R10, R10_H,
duke@0 297 R11, R11_H,
duke@0 298 R12, R12_H,
duke@0 299 R13, R13_H,
duke@0 300 R14, R14_H,
duke@0 301 R15, R15_H);
duke@0 302
duke@0 303 // Class for all pointer registers except RSP
duke@0 304 reg_class ptr_reg(RAX, RAX_H,
duke@0 305 RDX, RDX_H,
duke@0 306 RBP, RBP_H,
duke@0 307 RDI, RDI_H,
duke@0 308 RSI, RSI_H,
duke@0 309 RCX, RCX_H,
duke@0 310 RBX, RBX_H,
duke@0 311 R8, R8_H,
duke@0 312 R9, R9_H,
duke@0 313 R10, R10_H,
duke@0 314 R11, R11_H,
duke@0 315 R13, R13_H,
duke@0 316 R14, R14_H);
duke@0 317
duke@0 318 // Class for all pointer registers except RAX and RSP
duke@0 319 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 320 RBP, RBP_H,
duke@0 321 RDI, RDI_H,
duke@0 322 RSI, RSI_H,
duke@0 323 RCX, RCX_H,
duke@0 324 RBX, RBX_H,
duke@0 325 R8, R8_H,
duke@0 326 R9, R9_H,
duke@0 327 R10, R10_H,
duke@0 328 R11, R11_H,
duke@0 329 R13, R13_H,
duke@0 330 R14, R14_H);
duke@0 331
duke@0 332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 333 RAX, RAX_H,
duke@0 334 RDI, RDI_H,
duke@0 335 RSI, RSI_H,
duke@0 336 RCX, RCX_H,
duke@0 337 RBX, RBX_H,
duke@0 338 R8, R8_H,
duke@0 339 R9, R9_H,
duke@0 340 R10, R10_H,
duke@0 341 R11, R11_H,
duke@0 342 R13, R13_H,
duke@0 343 R14, R14_H);
duke@0 344
duke@0 345 // Class for all pointer registers except RAX, RBX and RSP
duke@0 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 347 RBP, RBP_H,
duke@0 348 RDI, RDI_H,
duke@0 349 RSI, RSI_H,
duke@0 350 RCX, RCX_H,
duke@0 351 R8, R8_H,
duke@0 352 R9, R9_H,
duke@0 353 R10, R10_H,
duke@0 354 R11, R11_H,
duke@0 355 R13, R13_H,
duke@0 356 R14, R14_H);
duke@0 357
duke@0 358 // Singleton class for RAX pointer register
duke@0 359 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 360
duke@0 361 // Singleton class for RBX pointer register
duke@0 362 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 363
duke@0 364 // Singleton class for RSI pointer register
duke@0 365 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 366
duke@0 367 // Singleton class for RDI pointer register
duke@0 368 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 369
duke@0 370 // Singleton class for RBP pointer register
duke@0 371 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 372
duke@0 373 // Singleton class for stack pointer
duke@0 374 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 375
duke@0 376 // Singleton class for TLS pointer
duke@0 377 reg_class ptr_r15_reg(R15, R15_H);
duke@0 378
duke@0 379 // Class for all long registers (except RSP)
duke@0 380 reg_class long_reg(RAX, RAX_H,
duke@0 381 RDX, RDX_H,
duke@0 382 RBP, RBP_H,
duke@0 383 RDI, RDI_H,
duke@0 384 RSI, RSI_H,
duke@0 385 RCX, RCX_H,
duke@0 386 RBX, RBX_H,
duke@0 387 R8, R8_H,
duke@0 388 R9, R9_H,
duke@0 389 R10, R10_H,
duke@0 390 R11, R11_H,
duke@0 391 R13, R13_H,
duke@0 392 R14, R14_H);
duke@0 393
duke@0 394 // Class for all long registers except RAX, RDX (and RSP)
duke@0 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 396 RDI, RDI_H,
duke@0 397 RSI, RSI_H,
duke@0 398 RCX, RCX_H,
duke@0 399 RBX, RBX_H,
duke@0 400 R8, R8_H,
duke@0 401 R9, R9_H,
duke@0 402 R10, R10_H,
duke@0 403 R11, R11_H,
duke@0 404 R13, R13_H,
duke@0 405 R14, R14_H);
duke@0 406
duke@0 407 // Class for all long registers except RCX (and RSP)
duke@0 408 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 409 RDI, RDI_H,
duke@0 410 RSI, RSI_H,
duke@0 411 RAX, RAX_H,
duke@0 412 RDX, RDX_H,
duke@0 413 RBX, RBX_H,
duke@0 414 R8, R8_H,
duke@0 415 R9, R9_H,
duke@0 416 R10, R10_H,
duke@0 417 R11, R11_H,
duke@0 418 R13, R13_H,
duke@0 419 R14, R14_H);
duke@0 420
duke@0 421 // Class for all long registers except RAX (and RSP)
duke@0 422 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 423 RDX, RDX_H,
duke@0 424 RDI, RDI_H,
duke@0 425 RSI, RSI_H,
duke@0 426 RCX, RCX_H,
duke@0 427 RBX, RBX_H,
duke@0 428 R8, R8_H,
duke@0 429 R9, R9_H,
duke@0 430 R10, R10_H,
duke@0 431 R11, R11_H,
duke@0 432 R13, R13_H,
duke@0 433 R14, R14_H);
duke@0 434
duke@0 435 // Singleton class for RAX long register
duke@0 436 reg_class long_rax_reg(RAX, RAX_H);
duke@0 437
duke@0 438 // Singleton class for RCX long register
duke@0 439 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 440
duke@0 441 // Singleton class for RDX long register
duke@0 442 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 443
duke@0 444 // Class for all int registers (except RSP)
duke@0 445 reg_class int_reg(RAX,
duke@0 446 RDX,
duke@0 447 RBP,
duke@0 448 RDI,
duke@0 449 RSI,
duke@0 450 RCX,
duke@0 451 RBX,
duke@0 452 R8,
duke@0 453 R9,
duke@0 454 R10,
duke@0 455 R11,
duke@0 456 R13,
duke@0 457 R14);
duke@0 458
duke@0 459 // Class for all int registers except RCX (and RSP)
duke@0 460 reg_class int_no_rcx_reg(RAX,
duke@0 461 RDX,
duke@0 462 RBP,
duke@0 463 RDI,
duke@0 464 RSI,
duke@0 465 RBX,
duke@0 466 R8,
duke@0 467 R9,
duke@0 468 R10,
duke@0 469 R11,
duke@0 470 R13,
duke@0 471 R14);
duke@0 472
duke@0 473 // Class for all int registers except RAX, RDX (and RSP)
duke@0 474 reg_class int_no_rax_rdx_reg(RBP,
never@304 475 RDI,
duke@0 476 RSI,
duke@0 477 RCX,
duke@0 478 RBX,
duke@0 479 R8,
duke@0 480 R9,
duke@0 481 R10,
duke@0 482 R11,
duke@0 483 R13,
duke@0 484 R14);
duke@0 485
duke@0 486 // Singleton class for RAX int register
duke@0 487 reg_class int_rax_reg(RAX);
duke@0 488
duke@0 489 // Singleton class for RBX int register
duke@0 490 reg_class int_rbx_reg(RBX);
duke@0 491
duke@0 492 // Singleton class for RCX int register
duke@0 493 reg_class int_rcx_reg(RCX);
duke@0 494
duke@0 495 // Singleton class for RCX int register
duke@0 496 reg_class int_rdx_reg(RDX);
duke@0 497
duke@0 498 // Singleton class for RCX int register
duke@0 499 reg_class int_rdi_reg(RDI);
duke@0 500
duke@0 501 // Singleton class for instruction pointer
duke@0 502 // reg_class ip_reg(RIP);
duke@0 503
duke@0 504 // Singleton class for condition codes
duke@0 505 reg_class int_flags(RFLAGS);
duke@0 506
duke@0 507 // Class for all float registers
duke@0 508 reg_class float_reg(XMM0,
duke@0 509 XMM1,
duke@0 510 XMM2,
duke@0 511 XMM3,
duke@0 512 XMM4,
duke@0 513 XMM5,
duke@0 514 XMM6,
duke@0 515 XMM7,
duke@0 516 XMM8,
duke@0 517 XMM9,
duke@0 518 XMM10,
duke@0 519 XMM11,
duke@0 520 XMM12,
duke@0 521 XMM13,
duke@0 522 XMM14,
duke@0 523 XMM15);
duke@0 524
duke@0 525 // Class for all double registers
duke@0 526 reg_class double_reg(XMM0, XMM0_H,
duke@0 527 XMM1, XMM1_H,
duke@0 528 XMM2, XMM2_H,
duke@0 529 XMM3, XMM3_H,
duke@0 530 XMM4, XMM4_H,
duke@0 531 XMM5, XMM5_H,
duke@0 532 XMM6, XMM6_H,
duke@0 533 XMM7, XMM7_H,
duke@0 534 XMM8, XMM8_H,
duke@0 535 XMM9, XMM9_H,
duke@0 536 XMM10, XMM10_H,
duke@0 537 XMM11, XMM11_H,
duke@0 538 XMM12, XMM12_H,
duke@0 539 XMM13, XMM13_H,
duke@0 540 XMM14, XMM14_H,
duke@0 541 XMM15, XMM15_H);
duke@0 542 %}
duke@0 543
duke@0 544
duke@0 545 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 546 // This is a block of C++ code which provides values, functions, and
duke@0 547 // definitions necessary in the rest of the architecture description
duke@0 548 source %{
never@304 549 #define RELOC_IMM64 Assembler::imm_operand
duke@0 550 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 551
duke@0 552 #define __ _masm.
duke@0 553
twisti@1137 554 static int preserve_SP_size() {
twisti@1137 555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
twisti@1137 556 }
twisti@1137 557
duke@0 558 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 559 // from the start of the call to the point where the return address
duke@0 560 // will point.
duke@0 561 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 562 {
twisti@1137 563 int offset = 5; // 5 bytes from start of call to where return address points
twisti@1137 564 if (_method_handle_invoke)
twisti@1137 565 offset += preserve_SP_size();
twisti@1137 566 return offset;
duke@0 567 }
duke@0 568
duke@0 569 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 570 {
duke@0 571 return 15; // 15 bytes from start of call to where return address points
duke@0 572 }
duke@0 573
duke@0 574 // In os_cpu .ad file
duke@0 575 // int MachCallRuntimeNode::ret_addr_offset()
duke@0 576
duke@0 577 // Indicate if the safepoint node needs the polling page as an input.
duke@0 578 // Since amd64 does not have absolute addressing but RIP-relative
duke@0 579 // addressing and the polling page is within 2G, it doesn't.
duke@0 580 bool SafePointNode::needs_polling_address_input()
duke@0 581 {
duke@0 582 return false;
duke@0 583 }
duke@0 584
duke@0 585 //
duke@0 586 // Compute padding required for nodes which need alignment
duke@0 587 //
duke@0 588
duke@0 589 // The address of the call instruction needs to be 4-byte aligned to
duke@0 590 // ensure that it does not span a cache line so that it can be patched.
duke@0 591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 592 {
duke@0 593 current_offset += 1; // skip call opcode byte
duke@0 594 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 595 }
duke@0 596
duke@0 597 // The address of the call instruction needs to be 4-byte aligned to
duke@0 598 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 599 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 600 {
twisti@1137 601 current_offset += preserve_SP_size(); // skip mov rbp, rsp
twisti@1137 602 current_offset += 1; // skip call opcode byte
twisti@1137 603 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 604 }
twisti@1137 605
twisti@1137 606 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 607 // ensure that it does not span a cache line so that it can be patched.
duke@0 608 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 609 {
duke@0 610 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 611 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 612 }
duke@0 613
duke@0 614 #ifndef PRODUCT
duke@0 615 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 616 {
duke@0 617 st->print("INT3");
duke@0 618 }
duke@0 619 #endif
duke@0 620
duke@0 621 // EMIT_RM()
twisti@1668 622 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 623 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 624 cbuf.insts()->emit_int8(c);
duke@0 625 }
duke@0 626
duke@0 627 // EMIT_CC()
twisti@1668 628 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 629 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 630 cbuf.insts()->emit_int8(c);
duke@0 631 }
duke@0 632
duke@0 633 // EMIT_OPCODE()
twisti@1668 634 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 635 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 636 }
duke@0 637
duke@0 638 // EMIT_OPCODE() w/ relocation information
duke@0 639 void emit_opcode(CodeBuffer &cbuf,
duke@0 640 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 641 {
twisti@1668 642 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 643 emit_opcode(cbuf, code);
duke@0 644 }
duke@0 645
duke@0 646 // EMIT_D8()
twisti@1668 647 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 648 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 649 }
duke@0 650
duke@0 651 // EMIT_D16()
twisti@1668 652 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 653 cbuf.insts()->emit_int16(d16);
duke@0 654 }
duke@0 655
duke@0 656 // EMIT_D32()
twisti@1668 657 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 658 cbuf.insts()->emit_int32(d32);
duke@0 659 }
duke@0 660
duke@0 661 // EMIT_D64()
twisti@1668 662 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 663 cbuf.insts()->emit_int64(d64);
duke@0 664 }
duke@0 665
duke@0 666 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 667 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 668 int d32,
duke@0 669 relocInfo::relocType reloc,
duke@0 670 int format)
duke@0 671 {
duke@0 672 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 674 cbuf.insts()->emit_int32(d32);
duke@0 675 }
duke@0 676
duke@0 677 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 678 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 679 #ifdef ASSERT
duke@0 680 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 681 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
jrose@989 682 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 683 }
duke@0 684 #endif
twisti@1668 685 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 686 cbuf.insts()->emit_int32(d32);
duke@0 687 }
duke@0 688
duke@0 689 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 690 address next_ip = cbuf.insts_end() + 4;
duke@0 691 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 692 external_word_Relocation::spec(addr),
duke@0 693 RELOC_DISP32);
duke@0 694 }
duke@0 695
duke@0 696
duke@0 697 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 698 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 699 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 700 cbuf.insts()->emit_int64(d64);
duke@0 701 }
duke@0 702
duke@0 703 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 704 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 705 #ifdef ASSERT
duke@0 706 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 707 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
jrose@989 708 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
jrose@989 709 "cannot embed scavengable oops in code");
duke@0 710 }
duke@0 711 #endif
twisti@1668 712 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 713 cbuf.insts()->emit_int64(d64);
duke@0 714 }
duke@0 715
duke@0 716 // Access stack slot for load or store
duke@0 717 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 718 {
duke@0 719 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 720 if (-0x80 <= disp && disp < 0x80) {
duke@0 721 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 722 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 723 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 724 } else {
duke@0 725 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 726 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 727 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 728 }
duke@0 729 }
duke@0 730
duke@0 731 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 732 void encode_RegMem(CodeBuffer &cbuf,
duke@0 733 int reg,
duke@0 734 int base, int index, int scale, int disp, bool disp_is_oop)
duke@0 735 {
duke@0 736 assert(!disp_is_oop, "cannot have disp");
duke@0 737 int regenc = reg & 7;
duke@0 738 int baseenc = base & 7;
duke@0 739 int indexenc = index & 7;
duke@0 740
duke@0 741 // There is no index & no scale, use form without SIB byte
duke@0 742 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 743 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 744 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 745 emit_rm(cbuf, 0x0, regenc, baseenc); // *
duke@0 746 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 747 // If 8-bit displacement, mode 0x1
duke@0 748 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 749 emit_d8(cbuf, disp);
duke@0 750 } else {
duke@0 751 // If 32-bit displacement
duke@0 752 if (base == -1) { // Special flag for absolute address
duke@0 753 emit_rm(cbuf, 0x0, regenc, 0x5); // *
duke@0 754 if (disp_is_oop) {
duke@0 755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 756 } else {
duke@0 757 emit_d32(cbuf, disp);
duke@0 758 }
duke@0 759 } else {
duke@0 760 // Normal base + offset
duke@0 761 emit_rm(cbuf, 0x2, regenc, baseenc); // *
duke@0 762 if (disp_is_oop) {
duke@0 763 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 764 } else {
duke@0 765 emit_d32(cbuf, disp);
duke@0 766 }
duke@0 767 }
duke@0 768 }
duke@0 769 } else {
duke@0 770 // Else, encode with the SIB byte
duke@0 771 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 772 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 773 // If no displacement
duke@0 774 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 775 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 776 } else {
duke@0 777 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 778 // If 8-bit displacement, mode 0x1
duke@0 779 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 780 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 781 emit_d8(cbuf, disp);
duke@0 782 } else {
duke@0 783 // If 32-bit displacement
duke@0 784 if (base == 0x04 ) {
duke@0 785 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 786 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 787 } else {
duke@0 788 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 789 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 790 }
duke@0 791 if (disp_is_oop) {
duke@0 792 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 793 } else {
duke@0 794 emit_d32(cbuf, disp);
duke@0 795 }
duke@0 796 }
duke@0 797 }
duke@0 798 }
duke@0 799 }
duke@0 800
duke@0 801 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
duke@0 802 {
duke@0 803 if (dstenc != srcenc) {
duke@0 804 if (dstenc < 8) {
duke@0 805 if (srcenc >= 8) {
duke@0 806 emit_opcode(cbuf, Assembler::REX_B);
duke@0 807 srcenc -= 8;
duke@0 808 }
duke@0 809 } else {
duke@0 810 if (srcenc < 8) {
duke@0 811 emit_opcode(cbuf, Assembler::REX_R);
duke@0 812 } else {
duke@0 813 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 814 srcenc -= 8;
duke@0 815 }
duke@0 816 dstenc -= 8;
duke@0 817 }
duke@0 818
duke@0 819 emit_opcode(cbuf, 0x8B);
duke@0 820 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 821 }
duke@0 822 }
duke@0 823
duke@0 824 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
duke@0 825 if( dst_encoding == src_encoding ) {
duke@0 826 // reg-reg copy, use an empty encoding
duke@0 827 } else {
duke@0 828 MacroAssembler _masm(&cbuf);
duke@0 829
duke@0 830 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
duke@0 831 }
duke@0 832 }
duke@0 833
duke@0 834
duke@0 835 //=============================================================================
twisti@1915 836 const bool Matcher::constant_table_absolute_addressing = true;
twisti@1915 837 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 838
twisti@1915 839 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 840 // Empty encoding
twisti@1915 841 }
twisti@1915 842
twisti@1915 843 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 844 return 0;
twisti@1915 845 }
twisti@1915 846
twisti@1915 847 #ifndef PRODUCT
twisti@1915 848 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 849 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 850 }
twisti@1915 851 #endif
twisti@1915 852
twisti@1915 853
twisti@1915 854 //=============================================================================
duke@0 855 #ifndef PRODUCT
duke@0 856 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 857 {
duke@0 858 Compile* C = ra_->C;
duke@0 859
duke@0 860 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 861 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 862 // Remove wordSize for return adr already pushed
duke@0 863 // and another for the RBP we are going to save
duke@0 864 framesize -= 2*wordSize;
duke@0 865 bool need_nop = true;
duke@0 866
duke@0 867 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 868 // We require that their callers must bang for them. But be
duke@0 869 // careful, because some VM calls (such as call site linkage) can
duke@0 870 // use several kilobytes of stack. But the stack safety zone should
duke@0 871 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 872 if (C->need_stack_bang(framesize)) {
duke@0 873 st->print_cr("# stack bang"); st->print("\t");
duke@0 874 need_nop = false;
duke@0 875 }
duke@0 876 st->print_cr("pushq rbp"); st->print("\t");
duke@0 877
duke@0 878 if (VerifyStackAtCalls) {
duke@0 879 // Majik cookie to verify stack depth
duke@0 880 st->print_cr("pushq 0xffffffffbadb100d"
duke@0 881 "\t# Majik cookie for stack depth check");
duke@0 882 st->print("\t");
duke@0 883 framesize -= wordSize; // Remove 2 for cookie
duke@0 884 need_nop = false;
duke@0 885 }
duke@0 886
duke@0 887 if (framesize) {
duke@0 888 st->print("subq rsp, #%d\t# Create frame", framesize);
duke@0 889 if (framesize < 0x80 && need_nop) {
duke@0 890 st->print("\n\tnop\t# nop for patch_verified_entry");
duke@0 891 }
duke@0 892 }
duke@0 893 }
duke@0 894 #endif
duke@0 895
duke@0 896 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 897 {
duke@0 898 Compile* C = ra_->C;
duke@0 899
duke@0 900 // WARNING: Initial instruction MUST be 5 bytes or longer so that
duke@0 901 // NativeJump::patch_verified_entry will be able to patch out the entry
duke@0 902 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
duke@0 903 // depth is ok at 5 bytes, the frame allocation can be either 3 or
duke@0 904 // 6 bytes. So if we don't do the fldcw or the push then we must
duke@0 905 // use the 6 byte frame allocation even if we have no frame. :-(
duke@0 906 // If method sets FPU control word do it now
duke@0 907
duke@0 908 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 909 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 910 // Remove wordSize for return adr already pushed
duke@0 911 // and another for the RBP we are going to save
duke@0 912 framesize -= 2*wordSize;
duke@0 913 bool need_nop = true;
duke@0 914
duke@0 915 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 916 // We require that their callers must bang for them. But be
duke@0 917 // careful, because some VM calls (such as call site linkage) can
duke@0 918 // use several kilobytes of stack. But the stack safety zone should
duke@0 919 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 920 if (C->need_stack_bang(framesize)) {
duke@0 921 MacroAssembler masm(&cbuf);
duke@0 922 masm.generate_stack_overflow_check(framesize);
duke@0 923 need_nop = false;
duke@0 924 }
duke@0 925
duke@0 926 // We always push rbp so that on return to interpreter rbp will be
duke@0 927 // restored correctly and we can correct the stack.
duke@0 928 emit_opcode(cbuf, 0x50 | RBP_enc);
duke@0 929
duke@0 930 if (VerifyStackAtCalls) {
duke@0 931 // Majik cookie to verify stack depth
duke@0 932 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
duke@0 933 emit_d32(cbuf, 0xbadb100d);
duke@0 934 framesize -= wordSize; // Remove 2 for cookie
duke@0 935 need_nop = false;
duke@0 936 }
duke@0 937
duke@0 938 if (framesize) {
duke@0 939 emit_opcode(cbuf, Assembler::REX_W);
duke@0 940 if (framesize < 0x80) {
duke@0 941 emit_opcode(cbuf, 0x83); // sub SP,#framesize
duke@0 942 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 943 emit_d8(cbuf, framesize);
duke@0 944 if (need_nop) {
duke@0 945 emit_opcode(cbuf, 0x90); // nop
duke@0 946 }
duke@0 947 } else {
duke@0 948 emit_opcode(cbuf, 0x81); // sub SP,#framesize
duke@0 949 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 950 emit_d32(cbuf, framesize);
duke@0 951 }
duke@0 952 }
duke@0 953
twisti@1668 954 C->set_frame_complete(cbuf.insts_size());
duke@0 955
duke@0 956 #ifdef ASSERT
duke@0 957 if (VerifyStackAtCalls) {
duke@0 958 Label L;
duke@0 959 MacroAssembler masm(&cbuf);
never@304 960 masm.push(rax);
never@304 961 masm.mov(rax, rsp);
never@304 962 masm.andptr(rax, StackAlignmentInBytes-1);
never@304 963 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
never@304 964 masm.pop(rax);
duke@0 965 masm.jcc(Assembler::equal, L);
duke@0 966 masm.stop("Stack is not properly aligned!");
duke@0 967 masm.bind(L);
duke@0 968 }
duke@0 969 #endif
duke@0 970 }
duke@0 971
duke@0 972 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 973 {
duke@0 974 return MachNode::size(ra_); // too many variables; just compute it
duke@0 975 // the hard way
duke@0 976 }
duke@0 977
duke@0 978 int MachPrologNode::reloc() const
duke@0 979 {
duke@0 980 return 0; // a large enough number
duke@0 981 }
duke@0 982
duke@0 983 //=============================================================================
duke@0 984 #ifndef PRODUCT
duke@0 985 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 986 {
duke@0 987 Compile* C = ra_->C;
duke@0 988 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 989 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 990 // Remove word for return adr already pushed
duke@0 991 // and RBP
duke@0 992 framesize -= 2*wordSize;
duke@0 993
duke@0 994 if (framesize) {
duke@0 995 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
duke@0 996 st->print("\t");
duke@0 997 }
duke@0 998
duke@0 999 st->print_cr("popq\trbp");
duke@0 1000 if (do_polling() && C->is_method_compilation()) {
duke@0 1001 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
duke@0 1002 "# Safepoint: poll for GC");
duke@0 1003 st->print("\t");
duke@0 1004 }
duke@0 1005 }
duke@0 1006 #endif
duke@0 1007
duke@0 1008 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1009 {
duke@0 1010 Compile* C = ra_->C;
duke@0 1011 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1012 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1013 // Remove word for return adr already pushed
duke@0 1014 // and RBP
duke@0 1015 framesize -= 2*wordSize;
duke@0 1016
duke@0 1017 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 1018
duke@0 1019 if (framesize) {
duke@0 1020 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1021 if (framesize < 0x80) {
duke@0 1022 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 1023 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1024 emit_d8(cbuf, framesize);
duke@0 1025 } else {
duke@0 1026 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 1027 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1028 emit_d32(cbuf, framesize);
duke@0 1029 }
duke@0 1030 }
duke@0 1031
duke@0 1032 // popq rbp
duke@0 1033 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 1034
duke@0 1035 if (do_polling() && C->is_method_compilation()) {
duke@0 1036 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
duke@0 1037 // XXX reg_mem doesn't support RIP-relative addressing yet
twisti@1668 1038 cbuf.set_insts_mark();
twisti@1668 1039 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_return_type, 0); // XXX
duke@0 1040 emit_opcode(cbuf, 0x85); // testl
duke@0 1041 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
twisti@1668 1042 // cbuf.insts_mark() is beginning of instruction
duke@0 1043 emit_d32_reloc(cbuf, os::get_polling_page());
duke@0 1044 // relocInfo::poll_return_type,
duke@0 1045 }
duke@0 1046 }
duke@0 1047
duke@0 1048 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 1049 {
duke@0 1050 Compile* C = ra_->C;
duke@0 1051 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1052 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1053 // Remove word for return adr already pushed
duke@0 1054 // and RBP
duke@0 1055 framesize -= 2*wordSize;
duke@0 1056
duke@0 1057 uint size = 0;
duke@0 1058
duke@0 1059 if (do_polling() && C->is_method_compilation()) {
duke@0 1060 size += 6;
duke@0 1061 }
duke@0 1062
duke@0 1063 // count popq rbp
duke@0 1064 size++;
duke@0 1065
duke@0 1066 if (framesize) {
duke@0 1067 if (framesize < 0x80) {
duke@0 1068 size += 4;
duke@0 1069 } else if (framesize) {
duke@0 1070 size += 7;
duke@0 1071 }
duke@0 1072 }
duke@0 1073
duke@0 1074 return size;
duke@0 1075 }
duke@0 1076
duke@0 1077 int MachEpilogNode::reloc() const
duke@0 1078 {
duke@0 1079 return 2; // a large enough number
duke@0 1080 }
duke@0 1081
duke@0 1082 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1083 {
duke@0 1084 return MachNode::pipeline_class();
duke@0 1085 }
duke@0 1086
duke@0 1087 int MachEpilogNode::safepoint_offset() const
duke@0 1088 {
duke@0 1089 return 0;
duke@0 1090 }
duke@0 1091
duke@0 1092 //=============================================================================
duke@0 1093
duke@0 1094 enum RC {
duke@0 1095 rc_bad,
duke@0 1096 rc_int,
duke@0 1097 rc_float,
duke@0 1098 rc_stack
duke@0 1099 };
duke@0 1100
duke@0 1101 static enum RC rc_class(OptoReg::Name reg)
duke@0 1102 {
duke@0 1103 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1104
duke@0 1105 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1106
duke@0 1107 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1108
duke@0 1109 if (r->is_Register()) return rc_int;
duke@0 1110
duke@0 1111 assert(r->is_XMMRegister(), "must be");
duke@0 1112 return rc_float;
duke@0 1113 }
duke@0 1114
duke@0 1115 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1116 PhaseRegAlloc* ra_,
duke@0 1117 bool do_size,
duke@0 1118 outputStream* st) const
duke@0 1119 {
duke@0 1120
duke@0 1121 // Get registers to move
duke@0 1122 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1123 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1124 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1125 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1126
duke@0 1127 enum RC src_second_rc = rc_class(src_second);
duke@0 1128 enum RC src_first_rc = rc_class(src_first);
duke@0 1129 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1130 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1131
duke@0 1132 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1133 "must move at least 1 register" );
duke@0 1134
duke@0 1135 if (src_first == dst_first && src_second == dst_second) {
duke@0 1136 // Self copy, no move
duke@0 1137 return 0;
duke@0 1138 } else if (src_first_rc == rc_stack) {
duke@0 1139 // mem ->
duke@0 1140 if (dst_first_rc == rc_stack) {
duke@0 1141 // mem -> mem
duke@0 1142 assert(src_second != dst_first, "overlap");
duke@0 1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1145 // 64-bit
duke@0 1146 int src_offset = ra_->reg2offset(src_first);
duke@0 1147 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1148 if (cbuf) {
duke@0 1149 emit_opcode(*cbuf, 0xFF);
duke@0 1150 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
duke@0 1151
duke@0 1152 emit_opcode(*cbuf, 0x8F);
duke@0 1153 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
duke@0 1154
duke@0 1155 #ifndef PRODUCT
duke@0 1156 } else if (!do_size) {
duke@0 1157 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
duke@0 1158 "popq [rsp + #%d]",
duke@0 1159 src_offset,
duke@0 1160 dst_offset);
duke@0 1161 #endif
duke@0 1162 }
duke@0 1163 return
duke@0 1164 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
duke@0 1165 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
duke@0 1166 } else {
duke@0 1167 // 32-bit
duke@0 1168 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1169 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1170 // No pushl/popl, so:
duke@0 1171 int src_offset = ra_->reg2offset(src_first);
duke@0 1172 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1173 if (cbuf) {
duke@0 1174 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1175 emit_opcode(*cbuf, 0x89);
duke@0 1176 emit_opcode(*cbuf, 0x44);
duke@0 1177 emit_opcode(*cbuf, 0x24);
duke@0 1178 emit_opcode(*cbuf, 0xF8);
duke@0 1179
duke@0 1180 emit_opcode(*cbuf, 0x8B);
duke@0 1181 encode_RegMem(*cbuf,
duke@0 1182 RAX_enc,
duke@0 1183 RSP_enc, 0x4, 0, src_offset,
duke@0 1184 false);
duke@0 1185
duke@0 1186 emit_opcode(*cbuf, 0x89);
duke@0 1187 encode_RegMem(*cbuf,
duke@0 1188 RAX_enc,
duke@0 1189 RSP_enc, 0x4, 0, dst_offset,
duke@0 1190 false);
duke@0 1191
duke@0 1192 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1193 emit_opcode(*cbuf, 0x8B);
duke@0 1194 emit_opcode(*cbuf, 0x44);
duke@0 1195 emit_opcode(*cbuf, 0x24);
duke@0 1196 emit_opcode(*cbuf, 0xF8);
duke@0 1197
duke@0 1198 #ifndef PRODUCT
duke@0 1199 } else if (!do_size) {
duke@0 1200 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
duke@0 1201 "movl rax, [rsp + #%d]\n\t"
duke@0 1202 "movl [rsp + #%d], rax\n\t"
duke@0 1203 "movq rax, [rsp - #8]",
duke@0 1204 src_offset,
duke@0 1205 dst_offset);
duke@0 1206 #endif
duke@0 1207 }
duke@0 1208 return
duke@0 1209 5 + // movq
duke@0 1210 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1211 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1212 5; // movq
duke@0 1213 }
duke@0 1214 } else if (dst_first_rc == rc_int) {
duke@0 1215 // mem -> gpr
duke@0 1216 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1217 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1218 // 64-bit
duke@0 1219 int offset = ra_->reg2offset(src_first);
duke@0 1220 if (cbuf) {
duke@0 1221 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1222 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1223 } else {
duke@0 1224 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1225 }
duke@0 1226 emit_opcode(*cbuf, 0x8B);
duke@0 1227 encode_RegMem(*cbuf,
duke@0 1228 Matcher::_regEncode[dst_first],
duke@0 1229 RSP_enc, 0x4, 0, offset,
duke@0 1230 false);
duke@0 1231 #ifndef PRODUCT
duke@0 1232 } else if (!do_size) {
duke@0 1233 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1234 Matcher::regName[dst_first],
duke@0 1235 offset);
duke@0 1236 #endif
duke@0 1237 }
duke@0 1238 return
duke@0 1239 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1240 } else {
duke@0 1241 // 32-bit
duke@0 1242 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1243 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1244 int offset = ra_->reg2offset(src_first);
duke@0 1245 if (cbuf) {
duke@0 1246 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1247 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1248 }
duke@0 1249 emit_opcode(*cbuf, 0x8B);
duke@0 1250 encode_RegMem(*cbuf,
duke@0 1251 Matcher::_regEncode[dst_first],
duke@0 1252 RSP_enc, 0x4, 0, offset,
duke@0 1253 false);
duke@0 1254 #ifndef PRODUCT
duke@0 1255 } else if (!do_size) {
duke@0 1256 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1257 Matcher::regName[dst_first],
duke@0 1258 offset);
duke@0 1259 #endif
duke@0 1260 }
duke@0 1261 return
duke@0 1262 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1263 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1264 ? 3
duke@0 1265 : 4); // REX
duke@0 1266 }
duke@0 1267 } else if (dst_first_rc == rc_float) {
duke@0 1268 // mem-> xmm
duke@0 1269 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1270 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1271 // 64-bit
duke@0 1272 int offset = ra_->reg2offset(src_first);
duke@0 1273 if (cbuf) {
duke@0 1274 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 1275 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1276 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1277 }
duke@0 1278 emit_opcode(*cbuf, 0x0F);
duke@0 1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 1280 encode_RegMem(*cbuf,
duke@0 1281 Matcher::_regEncode[dst_first],
duke@0 1282 RSP_enc, 0x4, 0, offset,
duke@0 1283 false);
duke@0 1284 #ifndef PRODUCT
duke@0 1285 } else if (!do_size) {
duke@0 1286 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1287 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1288 Matcher::regName[dst_first],
duke@0 1289 offset);
duke@0 1290 #endif
duke@0 1291 }
duke@0 1292 return
duke@0 1293 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1294 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1295 ? 5
duke@0 1296 : 6); // REX
duke@0 1297 } else {
duke@0 1298 // 32-bit
duke@0 1299 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1300 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1301 int offset = ra_->reg2offset(src_first);
duke@0 1302 if (cbuf) {
duke@0 1303 emit_opcode(*cbuf, 0xF3);
duke@0 1304 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1305 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1306 }
duke@0 1307 emit_opcode(*cbuf, 0x0F);
duke@0 1308 emit_opcode(*cbuf, 0x10);
duke@0 1309 encode_RegMem(*cbuf,
duke@0 1310 Matcher::_regEncode[dst_first],
duke@0 1311 RSP_enc, 0x4, 0, offset,
duke@0 1312 false);
duke@0 1313 #ifndef PRODUCT
duke@0 1314 } else if (!do_size) {
duke@0 1315 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1316 Matcher::regName[dst_first],
duke@0 1317 offset);
duke@0 1318 #endif
duke@0 1319 }
duke@0 1320 return
duke@0 1321 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1322 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1323 ? 5
duke@0 1324 : 6); // REX
duke@0 1325 }
duke@0 1326 }
duke@0 1327 } else if (src_first_rc == rc_int) {
duke@0 1328 // gpr ->
duke@0 1329 if (dst_first_rc == rc_stack) {
duke@0 1330 // gpr -> mem
duke@0 1331 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1332 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1333 // 64-bit
duke@0 1334 int offset = ra_->reg2offset(dst_first);
duke@0 1335 if (cbuf) {
duke@0 1336 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1337 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1338 } else {
duke@0 1339 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1340 }
duke@0 1341 emit_opcode(*cbuf, 0x89);
duke@0 1342 encode_RegMem(*cbuf,
duke@0 1343 Matcher::_regEncode[src_first],
duke@0 1344 RSP_enc, 0x4, 0, offset,
duke@0 1345 false);
duke@0 1346 #ifndef PRODUCT
duke@0 1347 } else if (!do_size) {
duke@0 1348 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1349 offset,
duke@0 1350 Matcher::regName[src_first]);
duke@0 1351 #endif
duke@0 1352 }
duke@0 1353 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1354 } else {
duke@0 1355 // 32-bit
duke@0 1356 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1357 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1358 int offset = ra_->reg2offset(dst_first);
duke@0 1359 if (cbuf) {
duke@0 1360 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1361 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1362 }
duke@0 1363 emit_opcode(*cbuf, 0x89);
duke@0 1364 encode_RegMem(*cbuf,
duke@0 1365 Matcher::_regEncode[src_first],
duke@0 1366 RSP_enc, 0x4, 0, offset,
duke@0 1367 false);
duke@0 1368 #ifndef PRODUCT
duke@0 1369 } else if (!do_size) {
duke@0 1370 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1371 offset,
duke@0 1372 Matcher::regName[src_first]);
duke@0 1373 #endif
duke@0 1374 }
duke@0 1375 return
duke@0 1376 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1377 ((Matcher::_regEncode[src_first] < 8)
duke@0 1378 ? 3
duke@0 1379 : 4); // REX
duke@0 1380 }
duke@0 1381 } else if (dst_first_rc == rc_int) {
duke@0 1382 // gpr -> gpr
duke@0 1383 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1384 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1385 // 64-bit
duke@0 1386 if (cbuf) {
duke@0 1387 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1388 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1389 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1390 } else {
duke@0 1391 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1392 }
duke@0 1393 } else {
duke@0 1394 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1395 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1396 } else {
duke@0 1397 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1398 }
duke@0 1399 }
duke@0 1400 emit_opcode(*cbuf, 0x8B);
duke@0 1401 emit_rm(*cbuf, 0x3,
duke@0 1402 Matcher::_regEncode[dst_first] & 7,
duke@0 1403 Matcher::_regEncode[src_first] & 7);
duke@0 1404 #ifndef PRODUCT
duke@0 1405 } else if (!do_size) {
duke@0 1406 st->print("movq %s, %s\t# spill",
duke@0 1407 Matcher::regName[dst_first],
duke@0 1408 Matcher::regName[src_first]);
duke@0 1409 #endif
duke@0 1410 }
duke@0 1411 return 3; // REX
duke@0 1412 } else {
duke@0 1413 // 32-bit
duke@0 1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1416 if (cbuf) {
duke@0 1417 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1418 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1419 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1420 }
duke@0 1421 } else {
duke@0 1422 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1423 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1424 } else {
duke@0 1425 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1426 }
duke@0 1427 }
duke@0 1428 emit_opcode(*cbuf, 0x8B);
duke@0 1429 emit_rm(*cbuf, 0x3,
duke@0 1430 Matcher::_regEncode[dst_first] & 7,
duke@0 1431 Matcher::_regEncode[src_first] & 7);
duke@0 1432 #ifndef PRODUCT
duke@0 1433 } else if (!do_size) {
duke@0 1434 st->print("movl %s, %s\t# spill",
duke@0 1435 Matcher::regName[dst_first],
duke@0 1436 Matcher::regName[src_first]);
duke@0 1437 #endif
duke@0 1438 }
duke@0 1439 return
duke@0 1440 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1441 ? 2
duke@0 1442 : 3; // REX
duke@0 1443 }
duke@0 1444 } else if (dst_first_rc == rc_float) {
duke@0 1445 // gpr -> xmm
duke@0 1446 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1447 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1448 // 64-bit
duke@0 1449 if (cbuf) {
duke@0 1450 emit_opcode(*cbuf, 0x66);
duke@0 1451 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1452 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1453 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1454 } else {
duke@0 1455 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1456 }
duke@0 1457 } else {
duke@0 1458 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1459 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1460 } else {
duke@0 1461 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1462 }
duke@0 1463 }
duke@0 1464 emit_opcode(*cbuf, 0x0F);
duke@0 1465 emit_opcode(*cbuf, 0x6E);
duke@0 1466 emit_rm(*cbuf, 0x3,
duke@0 1467 Matcher::_regEncode[dst_first] & 7,
duke@0 1468 Matcher::_regEncode[src_first] & 7);
duke@0 1469 #ifndef PRODUCT
duke@0 1470 } else if (!do_size) {
duke@0 1471 st->print("movdq %s, %s\t# spill",
duke@0 1472 Matcher::regName[dst_first],
duke@0 1473 Matcher::regName[src_first]);
duke@0 1474 #endif
duke@0 1475 }
duke@0 1476 return 5; // REX
duke@0 1477 } else {
duke@0 1478 // 32-bit
duke@0 1479 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1480 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1481 if (cbuf) {
duke@0 1482 emit_opcode(*cbuf, 0x66);
duke@0 1483 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1484 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1485 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1486 }
duke@0 1487 } else {
duke@0 1488 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1489 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1490 } else {
duke@0 1491 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1492 }
duke@0 1493 }
duke@0 1494 emit_opcode(*cbuf, 0x0F);
duke@0 1495 emit_opcode(*cbuf, 0x6E);
duke@0 1496 emit_rm(*cbuf, 0x3,
duke@0 1497 Matcher::_regEncode[dst_first] & 7,
duke@0 1498 Matcher::_regEncode[src_first] & 7);
duke@0 1499 #ifndef PRODUCT
duke@0 1500 } else if (!do_size) {
duke@0 1501 st->print("movdl %s, %s\t# spill",
duke@0 1502 Matcher::regName[dst_first],
duke@0 1503 Matcher::regName[src_first]);
duke@0 1504 #endif
duke@0 1505 }
duke@0 1506 return
duke@0 1507 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1508 ? 4
duke@0 1509 : 5; // REX
duke@0 1510 }
duke@0 1511 }
duke@0 1512 } else if (src_first_rc == rc_float) {
duke@0 1513 // xmm ->
duke@0 1514 if (dst_first_rc == rc_stack) {
duke@0 1515 // xmm -> mem
duke@0 1516 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1517 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1518 // 64-bit
duke@0 1519 int offset = ra_->reg2offset(dst_first);
duke@0 1520 if (cbuf) {
duke@0 1521 emit_opcode(*cbuf, 0xF2);
duke@0 1522 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1523 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1524 }
duke@0 1525 emit_opcode(*cbuf, 0x0F);
duke@0 1526 emit_opcode(*cbuf, 0x11);
duke@0 1527 encode_RegMem(*cbuf,
duke@0 1528 Matcher::_regEncode[src_first],
duke@0 1529 RSP_enc, 0x4, 0, offset,
duke@0 1530 false);
duke@0 1531 #ifndef PRODUCT
duke@0 1532 } else if (!do_size) {
duke@0 1533 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1534 offset,
duke@0 1535 Matcher::regName[src_first]);
duke@0 1536 #endif
duke@0 1537 }
duke@0 1538 return
duke@0 1539 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1540 ((Matcher::_regEncode[src_first] < 8)
duke@0 1541 ? 5
duke@0 1542 : 6); // REX
duke@0 1543 } else {
duke@0 1544 // 32-bit
duke@0 1545 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1546 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1547 int offset = ra_->reg2offset(dst_first);
duke@0 1548 if (cbuf) {
duke@0 1549 emit_opcode(*cbuf, 0xF3);
duke@0 1550 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1551 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1552 }
duke@0 1553 emit_opcode(*cbuf, 0x0F);
duke@0 1554 emit_opcode(*cbuf, 0x11);
duke@0 1555 encode_RegMem(*cbuf,
duke@0 1556 Matcher::_regEncode[src_first],
duke@0 1557 RSP_enc, 0x4, 0, offset,
duke@0 1558 false);
duke@0 1559 #ifndef PRODUCT
duke@0 1560 } else if (!do_size) {
duke@0 1561 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1562 offset,
duke@0 1563 Matcher::regName[src_first]);
duke@0 1564 #endif
duke@0 1565 }
duke@0 1566 return
duke@0 1567 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1568 ((Matcher::_regEncode[src_first] < 8)
duke@0 1569 ? 5
duke@0 1570 : 6); // REX
duke@0 1571 }
duke@0 1572 } else if (dst_first_rc == rc_int) {
duke@0 1573 // xmm -> gpr
duke@0 1574 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1575 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1576 // 64-bit
duke@0 1577 if (cbuf) {
duke@0 1578 emit_opcode(*cbuf, 0x66);
duke@0 1579 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1580 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1581 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1582 } else {
duke@0 1583 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
duke@0 1584 }
duke@0 1585 } else {
duke@0 1586 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1587 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
duke@0 1588 } else {
duke@0 1589 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1590 }
duke@0 1591 }
duke@0 1592 emit_opcode(*cbuf, 0x0F);
duke@0 1593 emit_opcode(*cbuf, 0x7E);
duke@0 1594 emit_rm(*cbuf, 0x3,
never@1650 1595 Matcher::_regEncode[src_first] & 7,
never@1650 1596 Matcher::_regEncode[dst_first] & 7);
duke@0 1597 #ifndef PRODUCT
duke@0 1598 } else if (!do_size) {
duke@0 1599 st->print("movdq %s, %s\t# spill",
duke@0 1600 Matcher::regName[dst_first],
duke@0 1601 Matcher::regName[src_first]);
duke@0 1602 #endif
duke@0 1603 }
duke@0 1604 return 5; // REX
duke@0 1605 } else {
duke@0 1606 // 32-bit
duke@0 1607 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1608 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1609 if (cbuf) {
duke@0 1610 emit_opcode(*cbuf, 0x66);
duke@0 1611 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1612 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1613 emit_opcode(*cbuf, Assembler::REX_R); // attention!
duke@0 1614 }
duke@0 1615 } else {
duke@0 1616 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1617 emit_opcode(*cbuf, Assembler::REX_B); // attention!
duke@0 1618 } else {
duke@0 1619 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1620 }
duke@0 1621 }
duke@0 1622 emit_opcode(*cbuf, 0x0F);
duke@0 1623 emit_opcode(*cbuf, 0x7E);
duke@0 1624 emit_rm(*cbuf, 0x3,
never@1650 1625 Matcher::_regEncode[src_first] & 7,
never@1650 1626 Matcher::_regEncode[dst_first] & 7);
duke@0 1627 #ifndef PRODUCT
duke@0 1628 } else if (!do_size) {
duke@0 1629 st->print("movdl %s, %s\t# spill",
duke@0 1630 Matcher::regName[dst_first],
duke@0 1631 Matcher::regName[src_first]);
duke@0 1632 #endif
duke@0 1633 }
duke@0 1634 return
duke@0 1635 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1636 ? 4
duke@0 1637 : 5; // REX
duke@0 1638 }
duke@0 1639 } else if (dst_first_rc == rc_float) {
duke@0 1640 // xmm -> xmm
duke@0 1641 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1642 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1643 // 64-bit
duke@0 1644 if (cbuf) {
duke@0 1645 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 1646 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1647 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1648 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1649 }
duke@0 1650 } else {
duke@0 1651 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1652 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1653 } else {
duke@0 1654 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1655 }
duke@0 1656 }
duke@0 1657 emit_opcode(*cbuf, 0x0F);
duke@0 1658 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1659 emit_rm(*cbuf, 0x3,
duke@0 1660 Matcher::_regEncode[dst_first] & 7,
duke@0 1661 Matcher::_regEncode[src_first] & 7);
duke@0 1662 #ifndef PRODUCT
duke@0 1663 } else if (!do_size) {
duke@0 1664 st->print("%s %s, %s\t# spill",
duke@0 1665 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1666 Matcher::regName[dst_first],
duke@0 1667 Matcher::regName[src_first]);
duke@0 1668 #endif
duke@0 1669 }
duke@0 1670 return
duke@0 1671 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1672 ? 4
duke@0 1673 : 5; // REX
duke@0 1674 } else {
duke@0 1675 // 32-bit
duke@0 1676 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1677 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1678 if (cbuf) {
duke@0 1679 if (!UseXmmRegToRegMoveAll)
duke@0 1680 emit_opcode(*cbuf, 0xF3);
duke@0 1681 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1682 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1683 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1684 }
duke@0 1685 } else {
duke@0 1686 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1687 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1688 } else {
duke@0 1689 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1690 }
duke@0 1691 }
duke@0 1692 emit_opcode(*cbuf, 0x0F);
duke@0 1693 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1694 emit_rm(*cbuf, 0x3,
duke@0 1695 Matcher::_regEncode[dst_first] & 7,
duke@0 1696 Matcher::_regEncode[src_first] & 7);
duke@0 1697 #ifndef PRODUCT
duke@0 1698 } else if (!do_size) {
duke@0 1699 st->print("%s %s, %s\t# spill",
duke@0 1700 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1701 Matcher::regName[dst_first],
duke@0 1702 Matcher::regName[src_first]);
duke@0 1703 #endif
duke@0 1704 }
duke@0 1705 return
duke@0 1706 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1707 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 1708 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
duke@0 1709 }
duke@0 1710 }
duke@0 1711 }
duke@0 1712
duke@0 1713 assert(0," foo ");
duke@0 1714 Unimplemented();
duke@0 1715
duke@0 1716 return 0;
duke@0 1717 }
duke@0 1718
duke@0 1719 #ifndef PRODUCT
duke@0 1720 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
duke@0 1721 {
duke@0 1722 implementation(NULL, ra_, false, st);
duke@0 1723 }
duke@0 1724 #endif
duke@0 1725
duke@0 1726 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 1727 {
duke@0 1728 implementation(&cbuf, ra_, false, NULL);
duke@0 1729 }
duke@0 1730
duke@0 1731 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
duke@0 1732 {
duke@0 1733 return implementation(NULL, ra_, true, NULL);
duke@0 1734 }
duke@0 1735
duke@0 1736 //=============================================================================
duke@0 1737 #ifndef PRODUCT
duke@0 1738 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 1739 {
duke@0 1740 st->print("nop \t# %d bytes pad for loops and calls", _count);
duke@0 1741 }
duke@0 1742 #endif
duke@0 1743
duke@0 1744 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
duke@0 1745 {
duke@0 1746 MacroAssembler _masm(&cbuf);
duke@0 1747 __ nop(_count);
duke@0 1748 }
duke@0 1749
duke@0 1750 uint MachNopNode::size(PhaseRegAlloc*) const
duke@0 1751 {
duke@0 1752 return _count;
duke@0 1753 }
duke@0 1754
duke@0 1755
duke@0 1756 //=============================================================================
duke@0 1757 #ifndef PRODUCT
duke@0 1758 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1759 {
duke@0 1760 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1761 int reg = ra_->get_reg_first(this);
duke@0 1762 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1763 Matcher::regName[reg], offset);
duke@0 1764 }
duke@0 1765 #endif
duke@0 1766
duke@0 1767 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1768 {
duke@0 1769 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1770 int reg = ra_->get_encode(this);
duke@0 1771 if (offset >= 0x80) {
duke@0 1772 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1773 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1774 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1775 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1776 emit_d32(cbuf, offset);
duke@0 1777 } else {
duke@0 1778 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1779 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1780 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1781 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1782 emit_d8(cbuf, offset);
duke@0 1783 }
duke@0 1784 }
duke@0 1785
duke@0 1786 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1787 {
duke@0 1788 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1789 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1790 }
duke@0 1791
duke@0 1792 //=============================================================================
duke@0 1793
duke@0 1794 // emit call stub, compiled java to interpreter
duke@0 1795 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1796 {
duke@0 1797 // Stub is fixed up when the corresponding call is converted from
duke@0 1798 // calling compiled code to calling interpreted code.
duke@0 1799 // movq rbx, 0
duke@0 1800 // jmp -5 # to self
duke@0 1801
twisti@1668 1802 address mark = cbuf.insts_mark(); // get mark within main instrs section
twisti@1668 1803
twisti@1668 1804 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1805 // That's why we must use the macroassembler to generate a stub.
duke@0 1806 MacroAssembler _masm(&cbuf);
duke@0 1807
duke@0 1808 address base =
duke@0 1809 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1810 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1811 // static stub relocation stores the instruction address of the call
duke@0 1812 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
duke@0 1813 // static stub relocation also tags the methodOop in the code-stream.
duke@0 1814 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
never@304 1815 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1816 __ jump(RuntimeAddress(__ pc()));
duke@0 1817
twisti@1668 1818 // Update current stubs pointer and restore insts_end.
duke@0 1819 __ end_a_stub();
duke@0 1820 }
duke@0 1821
duke@0 1822 // size of call stub, compiled java to interpretor
duke@0 1823 uint size_java_to_interp()
duke@0 1824 {
duke@0 1825 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1826 }
duke@0 1827
duke@0 1828 // relocation entries for call stub, compiled java to interpretor
duke@0 1829 uint reloc_java_to_interp()
duke@0 1830 {
duke@0 1831 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1832 }
duke@0 1833
duke@0 1834 //=============================================================================
duke@0 1835 #ifndef PRODUCT
duke@0 1836 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1837 {
coleenp@113 1838 if (UseCompressedOops) {
kvn@1491 1839 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
kvn@642 1840 if (Universe::narrow_oop_shift() != 0) {
kvn@1491 1841 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
kvn@1491 1842 }
kvn@1491 1843 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1844 } else {
kvn@1491 1845 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1846 "# Inline cache check");
coleenp@113 1847 }
duke@0 1848 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1849 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1850 }
duke@0 1851 #endif
duke@0 1852
duke@0 1853 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1854 {
duke@0 1855 MacroAssembler masm(&cbuf);
twisti@1668 1856 uint insts_size = cbuf.insts_size();
coleenp@113 1857 if (UseCompressedOops) {
coleenp@113 1858 masm.load_klass(rscratch1, j_rarg0);
never@304 1859 masm.cmpptr(rax, rscratch1);
coleenp@113 1860 } else {
never@304 1861 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1862 }
duke@0 1863
duke@0 1864 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1865
duke@0 1866 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1867 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1868 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1869 if (OptoBreakpoint) {
duke@0 1870 // Leave space for int3
kvn@1491 1871 nops_cnt -= 1;
duke@0 1872 }
kvn@1491 1873 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1874 if (nops_cnt > 0)
kvn@1491 1875 masm.nop(nops_cnt);
duke@0 1876 }
duke@0 1877
duke@0 1878 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1879 {
kvn@1491 1880 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1881 // the hard way
duke@0 1882 }
duke@0 1883
duke@0 1884
duke@0 1885 //=============================================================================
duke@0 1886 uint size_exception_handler()
duke@0 1887 {
duke@0 1888 // NativeCall instruction size is the same as NativeJump.
duke@0 1889 // Note that this value is also credited (in output.cpp) to
duke@0 1890 // the size of the code section.
duke@0 1891 return NativeJump::instruction_size;
duke@0 1892 }
duke@0 1893
duke@0 1894 // Emit exception handler code.
duke@0 1895 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1896 {
duke@0 1897
twisti@1668 1898 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1899 // That's why we must use the macroassembler to generate a handler.
duke@0 1900 MacroAssembler _masm(&cbuf);
duke@0 1901 address base =
duke@0 1902 __ start_a_stub(size_exception_handler());
duke@0 1903 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1904 int offset = __ offset();
twisti@1668 1905 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
duke@0 1906 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1907 __ end_a_stub();
duke@0 1908 return offset;
duke@0 1909 }
duke@0 1910
duke@0 1911 uint size_deopt_handler()
duke@0 1912 {
duke@0 1913 // three 5 byte instructions
duke@0 1914 return 15;
duke@0 1915 }
duke@0 1916
duke@0 1917 // Emit deopt handler code.
duke@0 1918 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1919 {
duke@0 1920
twisti@1668 1921 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1922 // That's why we must use the macroassembler to generate a handler.
duke@0 1923 MacroAssembler _masm(&cbuf);
duke@0 1924 address base =
duke@0 1925 __ start_a_stub(size_deopt_handler());
duke@0 1926 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1927 int offset = __ offset();
duke@0 1928 address the_pc = (address) __ pc();
duke@0 1929 Label next;
duke@0 1930 // push a "the_pc" on the stack without destroying any registers
duke@0 1931 // as they all may be live.
duke@0 1932
duke@0 1933 // push address of "next"
duke@0 1934 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1935 __ bind(next);
duke@0 1936 // adjust it so it matches "the_pc"
never@304 1937 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1938 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1939 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1940 __ end_a_stub();
duke@0 1941 return offset;
duke@0 1942 }
duke@0 1943
duke@0 1944
twisti@775 1945 const bool Matcher::match_rule_supported(int opcode) {
twisti@775 1946 if (!has_match_rule(opcode))
twisti@775 1947 return false;
twisti@775 1948
twisti@775 1949 return true; // Per default match rules are supported.
twisti@775 1950 }
twisti@775 1951
duke@0 1952 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1953 {
duke@0 1954 return regnum - 32; // The FP registers are in the second chunk
duke@0 1955 }
duke@0 1956
duke@0 1957 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1958 const bool Matcher::convL2FSupported(void) {
duke@0 1959 return true;
duke@0 1960 }
duke@0 1961
duke@0 1962 // Vector width in bytes
duke@0 1963 const uint Matcher::vector_width_in_bytes(void) {
duke@0 1964 return 8;
duke@0 1965 }
duke@0 1966
duke@0 1967 // Vector ideal reg
duke@0 1968 const uint Matcher::vector_ideal_reg(void) {
duke@0 1969 return Op_RegD;
duke@0 1970 }
duke@0 1971
duke@0 1972 // Is this branch offset short enough that a short branch can be used?
duke@0 1973 //
duke@0 1974 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1975 // this method should return false for offset 0.
never@415 1976 bool Matcher::is_short_branch_offset(int rule, int offset) {
never@415 1977 // the short version of jmpConUCF2 contains multiple branches,
never@415 1978 // making the reach slightly less
never@415 1979 if (rule == jmpConUCF2_rule)
never@415 1980 return (-126 <= offset && offset <= 125);
never@415 1981 return (-128 <= offset && offset <= 127);
duke@0 1982 }
duke@0 1983
duke@0 1984 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1985 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1986 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1987
duke@0 1988 // Probably always true, even if a temp register is required.
duke@0 1989 return true;
duke@0 1990 }
duke@0 1991
duke@0 1992 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1993 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1994
duke@0 1995 // Threshold size for cleararray.
duke@0 1996 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1997
duke@0 1998 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1999 // to be subsumed into complex addressing expressions or compute them
duke@0 2000 // into registers? True for Intel but false for most RISCs
duke@0 2001 const bool Matcher::clone_shift_expressions = true;
duke@0 2002
roland@2248 2003 // Do we need to mask the count passed to shift instructions or does
roland@2248 2004 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 2005 const bool Matcher::need_masked_shift_count = false;
roland@2248 2006
kvn@1495 2007 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 2008 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 2009 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 2010 }
kvn@1495 2011
duke@0 2012 // Is it better to copy float constants, or load them directly from
duke@0 2013 // memory? Intel can load a float constant from a direct address,
duke@0 2014 // requiring no extra registers. Most RISCs will have to materialize
duke@0 2015 // an address into a register first, so they would do better to copy
duke@0 2016 // the constant from stack.
duke@0 2017 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 2018
duke@0 2019 // If CPU can load and store mis-aligned doubles directly then no
duke@0 2020 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 2021 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 2022 // C code as the Java calling convention forces doubles to be aligned.
duke@0 2023 const bool Matcher::misaligned_doubles_ok = true;
duke@0 2024
duke@0 2025 // No-op on amd64
duke@0 2026 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 2027
duke@0 2028 // Advertise here if the CPU requires explicit rounding operations to
duke@0 2029 // implement the UseStrictFP mode.
duke@0 2030 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 2031
kvn@1274 2032 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 2033 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 2034 bool Matcher::float_in_double() { return false; }
kvn@1274 2035
duke@0 2036 // Do ints take an entire long register or just half?
duke@0 2037 const bool Matcher::int_in_long = true;
duke@0 2038
duke@0 2039 // Return whether or not this register is ever used as an argument.
duke@0 2040 // This function is used on startup to build the trampoline stubs in
duke@0 2041 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 2042 // call in the trampoline, and arguments in those registers not be
duke@0 2043 // available to the callee.
duke@0 2044 bool Matcher::can_be_java_arg(int reg)
duke@0 2045 {
duke@0 2046 return
duke@0 2047 reg == RDI_num || reg == RDI_H_num ||
duke@0 2048 reg == RSI_num || reg == RSI_H_num ||
duke@0 2049 reg == RDX_num || reg == RDX_H_num ||
duke@0 2050 reg == RCX_num || reg == RCX_H_num ||
duke@0 2051 reg == R8_num || reg == R8_H_num ||
duke@0 2052 reg == R9_num || reg == R9_H_num ||
coleenp@113 2053 reg == R12_num || reg == R12_H_num ||
duke@0 2054 reg == XMM0_num || reg == XMM0_H_num ||
duke@0 2055 reg == XMM1_num || reg == XMM1_H_num ||
duke@0 2056 reg == XMM2_num || reg == XMM2_H_num ||
duke@0 2057 reg == XMM3_num || reg == XMM3_H_num ||
duke@0 2058 reg == XMM4_num || reg == XMM4_H_num ||
duke@0 2059 reg == XMM5_num || reg == XMM5_H_num ||
duke@0 2060 reg == XMM6_num || reg == XMM6_H_num ||
duke@0 2061 reg == XMM7_num || reg == XMM7_H_num;
duke@0 2062 }
duke@0 2063
duke@0 2064 bool Matcher::is_spillable_arg(int reg)
duke@0 2065 {
duke@0 2066 return can_be_java_arg(reg);
duke@0 2067 }
duke@0 2068
kvn@1834 2069 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 2070 // In 64 bit mode a code which use multiply when
kvn@1834 2071 // devisor is constant is faster than hardware
kvn@1834 2072 // DIV instruction (it uses MulHiL).
kvn@1834 2073 return false;
kvn@1834 2074 }
kvn@1834 2075
duke@0 2076 // Register for DIVI projection of divmodI
duke@0 2077 RegMask Matcher::divI_proj_mask() {
duke@0 2078 return INT_RAX_REG_mask;
duke@0 2079 }
duke@0 2080
duke@0 2081 // Register for MODI projection of divmodI
duke@0 2082 RegMask Matcher::modI_proj_mask() {
duke@0 2083 return INT_RDX_REG_mask;
duke@0 2084 }
duke@0 2085
duke@0 2086 // Register for DIVL projection of divmodL
duke@0 2087 RegMask Matcher::divL_proj_mask() {
duke@0 2088 return LONG_RAX_REG_mask;
duke@0 2089 }
duke@0 2090
duke@0 2091 // Register for MODL projection of divmodL
duke@0 2092 RegMask Matcher::modL_proj_mask() {
duke@0 2093 return LONG_RDX_REG_mask;
duke@0 2094 }
duke@0 2095
twisti@1137 2096 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
twisti@1137 2097 return PTR_RBP_REG_mask;
twisti@1137 2098 }
twisti@1137 2099
coleenp@113 2100 static Address build_address(int b, int i, int s, int d) {
coleenp@113 2101 Register index = as_Register(i);
coleenp@113 2102 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 2103 if (index == rsp) {
coleenp@113 2104 index = noreg;
coleenp@113 2105 scale = Address::no_scale;
coleenp@113 2106 }
coleenp@113 2107 Address addr(as_Register(b), index, scale, d);
coleenp@113 2108 return addr;
coleenp@113 2109 }
coleenp@113 2110
duke@0 2111 %}
duke@0 2112
duke@0 2113 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 2114 // This block specifies the encoding classes used by the compiler to
duke@0 2115 // output byte streams. Encoding classes are parameterized macros
duke@0 2116 // used by Machine Instruction Nodes in order to generate the bit
duke@0 2117 // encoding of the instruction. Operands specify their base encoding
duke@0 2118 // interface with the interface keyword. There are currently
duke@0 2119 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 2120 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 2121 // which returns its register number when queried. CONST_INTER causes
duke@0 2122 // an operand to generate a function which returns the value of the
duke@0 2123 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 2124 // four functions which return the Base Register, the Index Register,
duke@0 2125 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 2126 // COND_INTER causes an operand to generate six functions which return
duke@0 2127 // the encoding code (ie - encoding bits for the instruction)
duke@0 2128 // associated with each basic boolean condition for a conditional
duke@0 2129 // instruction.
duke@0 2130 //
duke@0 2131 // Instructions specify two basic values for encoding. Again, a
duke@0 2132 // function is available to check if the constant displacement is an
duke@0 2133 // oop. They use the ins_encode keyword to specify their encoding
duke@0 2134 // classes (which must be a sequence of enc_class names, and their
duke@0 2135 // parameters, specified in the encoding block), and they use the
duke@0 2136 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 2137 // tertiary opcode. Only the opcode sections which a particular
duke@0 2138 // instruction needs for encoding need to be specified.
duke@0 2139 encode %{
duke@0 2140 // Build emit functions for each basic byte or larger field in the
duke@0 2141 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 2142 // from C++ code in the enc_class source block. Emit functions will
duke@0 2143 // live in the main source block for now. In future, we can
duke@0 2144 // generalize this by adding a syntax that specifies the sizes of
duke@0 2145 // fields in an order, so that the adlc can build the emit functions
duke@0 2146 // automagically
duke@0 2147
duke@0 2148 // Emit primary opcode
duke@0 2149 enc_class OpcP
duke@0 2150 %{
duke@0 2151 emit_opcode(cbuf, $primary);
duke@0 2152 %}
duke@0 2153
duke@0 2154 // Emit secondary opcode
duke@0 2155 enc_class OpcS
duke@0 2156 %{
duke@0 2157 emit_opcode(cbuf, $secondary);
duke@0 2158 %}
duke@0 2159
duke@0 2160 // Emit tertiary opcode
duke@0 2161 enc_class OpcT
duke@0 2162 %{
duke@0 2163 emit_opcode(cbuf, $tertiary);
duke@0 2164 %}
duke@0 2165
duke@0 2166 // Emit opcode directly
duke@0 2167 enc_class Opcode(immI d8)
duke@0 2168 %{
duke@0 2169 emit_opcode(cbuf, $d8$$constant);
duke@0 2170 %}
duke@0 2171
duke@0 2172 // Emit size prefix
duke@0 2173 enc_class SizePrefix
duke@0 2174 %{
duke@0 2175 emit_opcode(cbuf, 0x66);
duke@0 2176 %}
duke@0 2177
duke@0 2178 enc_class reg(rRegI reg)
duke@0 2179 %{
duke@0 2180 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 2181 %}
duke@0 2182
duke@0 2183 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 2184 %{
duke@0 2185 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2186 %}
duke@0 2187
duke@0 2188 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 2189 %{
duke@0 2190 emit_opcode(cbuf, $opcode$$constant);
duke@0 2191 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2192 %}
duke@0 2193
duke@0 2194 enc_class cmpfp_fixup()
duke@0 2195 %{
duke@0 2196 // jnp,s exit
duke@0 2197 emit_opcode(cbuf, 0x7B);
duke@0 2198 emit_d8(cbuf, 0x0A);
duke@0 2199
duke@0 2200 // pushfq
duke@0 2201 emit_opcode(cbuf, 0x9C);
duke@0 2202
duke@0 2203 // andq $0xffffff2b, (%rsp)
duke@0 2204 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2205 emit_opcode(cbuf, 0x81);
duke@0 2206 emit_opcode(cbuf, 0x24);
duke@0 2207 emit_opcode(cbuf, 0x24);
duke@0 2208 emit_d32(cbuf, 0xffffff2b);
duke@0 2209
duke@0 2210 // popfq
duke@0 2211 emit_opcode(cbuf, 0x9D);
duke@0 2212
duke@0 2213 // nop (target for branch to avoid branch to branch)
duke@0 2214 emit_opcode(cbuf, 0x90);
duke@0 2215 %}
duke@0 2216
duke@0 2217 enc_class cmpfp3(rRegI dst)
duke@0 2218 %{
duke@0 2219 int dstenc = $dst$$reg;
duke@0 2220
duke@0 2221 // movl $dst, -1
duke@0 2222 if (dstenc >= 8) {
duke@0 2223 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2224 }
duke@0 2225 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2226 emit_d32(cbuf, -1);
duke@0 2227
duke@0 2228 // jp,s done
duke@0 2229 emit_opcode(cbuf, 0x7A);
duke@0 2230 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
duke@0 2231
duke@0 2232 // jb,s done
duke@0 2233 emit_opcode(cbuf, 0x72);
duke@0 2234 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2235
duke@0 2236 // setne $dst
duke@0 2237 if (dstenc >= 4) {
duke@0 2238 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2239 }
duke@0 2240 emit_opcode(cbuf, 0x0F);
duke@0 2241 emit_opcode(cbuf, 0x95);
duke@0 2242 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2243
duke@0 2244 // movzbl $dst, $dst
duke@0 2245 if (dstenc >= 4) {
duke@0 2246 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2247 }
duke@0 2248 emit_opcode(cbuf, 0x0F);
duke@0 2249 emit_opcode(cbuf, 0xB6);
duke@0 2250 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2251 %}
duke@0 2252
duke@0 2253 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 2254 %{
duke@0 2255 // Full implementation of Java idiv and irem; checks for
duke@0 2256 // special case as described in JVM spec., p.243 & p.271.
duke@0 2257 //
duke@0 2258 // normal case special case
duke@0 2259 //
duke@0 2260 // input : rax: dividend min_int
duke@0 2261 // reg: divisor -1
duke@0 2262 //
duke@0 2263 // output: rax: quotient (= rax idiv reg) min_int
duke@0 2264 // rdx: remainder (= rax irem reg) 0
duke@0 2265 //
duke@0 2266 // Code sequnce:
duke@0 2267 //
duke@0 2268 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 2269 // 5: 75 07/08 jne e <normal>
duke@0 2270 // 7: 33 d2 xor %edx,%edx
duke@0 2271 // [div >= 8 -> offset + 1]
duke@0 2272 // [REX_B]
duke@0 2273 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2274 // c: 74 03/04 je 11 <done>
duke@0 2275 // 000000000000000e <normal>:
duke@0 2276 // e: 99 cltd
duke@0 2277 // [div >= 8 -> offset + 1]
duke@0 2278 // [REX_B]
duke@0 2279 // f: f7 f9 idiv $div
duke@0 2280 // 0000000000000011 <done>:
duke@0 2281
duke@0 2282 // cmp $0x80000000,%eax
duke@0 2283 emit_opcode(cbuf, 0x3d);
duke@0 2284 emit_d8(cbuf, 0x00);
duke@0 2285 emit_d8(cbuf, 0x00);
duke@0 2286 emit_d8(cbuf, 0x00);
duke@0 2287 emit_d8(cbuf, 0x80);
duke@0 2288
duke@0 2289 // jne e <normal>
duke@0 2290 emit_opcode(cbuf, 0x75);
duke@0 2291 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 2292
duke@0 2293 // xor %edx,%edx
duke@0 2294 emit_opcode(cbuf, 0x33);
duke@0 2295 emit_d8(cbuf, 0xD2);
duke@0 2296
duke@0 2297 // cmp $0xffffffffffffffff,%ecx
duke@0 2298 if ($div$$reg >= 8) {
duke@0 2299 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2300 }
duke@0 2301 emit_opcode(cbuf, 0x83);
duke@0 2302 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2303 emit_d8(cbuf, 0xFF);
duke@0 2304
duke@0 2305 // je 11 <done>
duke@0 2306 emit_opcode(cbuf, 0x74);
duke@0 2307 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 2308
duke@0 2309 // <normal>
duke@0 2310 // cltd
duke@0 2311 emit_opcode(cbuf, 0x99);
duke@0 2312
duke@0 2313 // idivl (note: must be emitted by the user of this rule)
duke@0 2314 // <done>
duke@0 2315 %}
duke@0 2316
duke@0 2317 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 2318 %{
duke@0 2319 // Full implementation of Java ldiv and lrem; checks for
duke@0 2320 // special case as described in JVM spec., p.243 & p.271.
duke@0 2321 //
duke@0 2322 // normal case special case
duke@0 2323 //
duke@0 2324 // input : rax: dividend min_long
duke@0 2325 // reg: divisor -1
duke@0 2326 //
duke@0 2327 // output: rax: quotient (= rax idiv reg) min_long
duke@0 2328 // rdx: remainder (= rax irem reg) 0
duke@0 2329 //
duke@0 2330 // Code sequnce:
duke@0 2331 //
duke@0 2332 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 2333 // 7: 00 00 80
duke@0 2334 // a: 48 39 d0 cmp %rdx,%rax
duke@0 2335 // d: 75 08 jne 17 <normal>
duke@0 2336 // f: 33 d2 xor %edx,%edx
duke@0 2337 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2338 // 15: 74 05 je 1c <done>
duke@0 2339 // 0000000000000017 <normal>:
duke@0 2340 // 17: 48 99 cqto
duke@0 2341 // 19: 48 f7 f9 idiv $div
duke@0 2342 // 000000000000001c <done>:
duke@0 2343
duke@0 2344 // mov $0x8000000000000000,%rdx
duke@0 2345 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2346 emit_opcode(cbuf, 0xBA);
duke@0 2347 emit_d8(cbuf, 0x00);
duke@0 2348 emit_d8(cbuf, 0x00);
duke@0 2349 emit_d8(cbuf, 0x00);
duke@0 2350 emit_d8(cbuf, 0x00);
duke@0 2351 emit_d8(cbuf, 0x00);
duke@0 2352 emit_d8(cbuf, 0x00);
duke@0 2353 emit_d8(cbuf, 0x00);
duke@0 2354 emit_d8(cbuf, 0x80);
duke@0 2355
duke@0 2356 // cmp %rdx,%rax
duke@0 2357 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2358 emit_opcode(cbuf, 0x39);
duke@0 2359 emit_d8(cbuf, 0xD0);
duke@0 2360
duke@0 2361 // jne 17 <normal>
duke@0 2362 emit_opcode(cbuf, 0x75);
duke@0 2363 emit_d8(cbuf, 0x08);
duke@0 2364
duke@0 2365 // xor %edx,%edx
duke@0 2366 emit_opcode(cbuf, 0x33);
duke@0 2367 emit_d8(cbuf, 0xD2);
duke@0 2368
duke@0 2369 // cmp $0xffffffffffffffff,$div
duke@0 2370 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 2371 emit_opcode(cbuf, 0x83);
duke@0 2372 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2373 emit_d8(cbuf, 0xFF);
duke@0 2374
duke@0 2375 // je 1e <done>
duke@0 2376 emit_opcode(cbuf, 0x74);
duke@0 2377 emit_d8(cbuf, 0x05);
duke@0 2378
duke@0 2379 // <normal>
duke@0 2380 // cqto
duke@0 2381 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2382 emit_opcode(cbuf, 0x99);
duke@0 2383
duke@0 2384 // idivq (note: must be emitted by the user of this rule)
duke@0 2385 // <done>
duke@0 2386 %}
duke@0 2387
duke@0 2388 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 2389 enc_class OpcSE(immI imm)
duke@0 2390 %{
duke@0 2391 // Emit primary opcode and set sign-extend bit
duke@0 2392 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2393 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2394 emit_opcode(cbuf, $primary | 0x02);
duke@0 2395 } else {
duke@0 2396 // 32-bit immediate
duke@0 2397 emit_opcode(cbuf, $primary);
duke@0 2398 }
duke@0 2399 %}
duke@0 2400
duke@0 2401 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 2402 %{
duke@0 2403 // OpcSEr/m
duke@0 2404 int dstenc = $dst$$reg;
duke@0 2405 if (dstenc >= 8) {
duke@0 2406 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2407 dstenc -= 8;
duke@0 2408 }
duke@0 2409 // Emit primary opcode and set sign-extend bit
duke@0 2410 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2411 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2412 emit_opcode(cbuf, $primary | 0x02);
duke@0 2413 } else {
duke@0 2414 // 32-bit immediate
duke@0 2415 emit_opcode(cbuf, $primary);
duke@0 2416 }
duke@0 2417 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2418 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2419 %}
duke@0 2420
duke@0 2421 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 2422 %{
duke@0 2423 // OpcSEr/m
duke@0 2424 int dstenc = $dst$$reg;
duke@0 2425 if (dstenc < 8) {
duke@0 2426 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2427 } else {
duke@0 2428 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2429 dstenc -= 8;
duke@0 2430 }
duke@0 2431 // Emit primary opcode and set sign-extend bit
duke@0 2432 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2433 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2434 emit_opcode(cbuf, $primary | 0x02);
duke@0 2435 } else {
duke@0 2436 // 32-bit immediate
duke@0 2437 emit_opcode(cbuf, $primary);
duke@0 2438 }
duke@0 2439 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2440 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2441 %}
duke@0 2442
duke@0 2443 enc_class Con8or32(immI imm)
duke@0 2444 %{
duke@0 2445 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2446 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2447 $$$emit8$imm$$constant;
duke@0 2448 } else {
duke@0 2449 // 32-bit immediate
duke@0 2450 $$$emit32$imm$$constant;
duke@0 2451 }
duke@0 2452 %}
duke@0 2453
duke@0 2454 enc_class Lbl(label labl)
duke@0 2455 %{
duke@0 2456 // JMP, CALL
duke@0 2457 Label* l = $labl$$label;
twisti@1668 2458 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
duke@0 2459 %}
duke@0 2460
duke@0 2461 enc_class LblShort(label labl)
duke@0 2462 %{
duke@0 2463 // JMP, CALL
duke@0 2464 Label* l = $labl$$label;
twisti@1668 2465 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
duke@0 2466 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2467 emit_d8(cbuf, disp);
duke@0 2468 %}
duke@0 2469
duke@0 2470 enc_class opc2_reg(rRegI dst)
duke@0 2471 %{
duke@0 2472 // BSWAP
duke@0 2473 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2474 %}
duke@0 2475
duke@0 2476 enc_class opc3_reg(rRegI dst)
duke@0 2477 %{
duke@0 2478 // BSWAP
duke@0 2479 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2480 %}
duke@0 2481
duke@0 2482 enc_class reg_opc(rRegI div)
duke@0 2483 %{
duke@0 2484 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2485 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2486 %}
duke@0 2487
duke@0 2488 enc_class Jcc(cmpOp cop, label labl)
duke@0 2489 %{
duke@0 2490 // JCC
duke@0 2491 Label* l = $labl$$label;
duke@0 2492 $$$emit8$primary;
duke@0 2493 emit_cc(cbuf, $secondary, $cop$$cmpcode);
twisti@1668 2494 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0);
duke@0 2495 %}
duke@0 2496
duke@0 2497 enc_class JccShort (cmpOp cop, label labl)
duke@0 2498 %{
duke@0 2499 // JCC
duke@0 2500 Label *l = $labl$$label;
duke@0 2501 emit_cc(cbuf, $primary, $cop$$cmpcode);
twisti@1668 2502 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0;
duke@0 2503 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
duke@0 2504 emit_d8(cbuf, disp);
duke@0 2505 %}
duke@0 2506
duke@0 2507 enc_class enc_cmov(cmpOp cop)
duke@0 2508 %{
duke@0 2509 // CMOV
duke@0 2510 $$$emit8$primary;
duke@0 2511 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2512 %}
duke@0 2513
duke@0 2514 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
duke@0 2515 %{
duke@0 2516 // Invert sense of branch from sense of cmov
duke@0 2517 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2518 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
duke@0 2519 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 2520 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
duke@0 2521 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
duke@0 2522 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
duke@0 2523 if ($dst$$reg < 8) {
duke@0 2524 if ($src$$reg >= 8) {
duke@0 2525 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2526 }
duke@0 2527 } else {
duke@0 2528 if ($src$$reg < 8) {
duke@0 2529 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2530 } else {
duke@0 2531 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2532 }
duke@0 2533 }
duke@0 2534 emit_opcode(cbuf, 0x0F);
duke@0 2535 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2536 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2537 %}
duke@0 2538
duke@0 2539 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
duke@0 2540 %{
duke@0 2541 // Invert sense of branch from sense of cmov
duke@0 2542 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2543 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
duke@0 2544
duke@0 2545 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
duke@0 2546 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 2547 if ($dst$$reg < 8) {
duke@0 2548 if ($src$$reg >= 8) {
duke@0 2549 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2550 }
duke@0 2551 } else {
duke@0 2552 if ($src$$reg < 8) {
duke@0 2553 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2554 } else {
duke@0 2555 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2556 }
duke@0 2557 }
duke@0 2558 emit_opcode(cbuf, 0x0F);
duke@0 2559 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2560 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2561 %}
duke@0 2562
duke@0 2563 enc_class enc_PartialSubtypeCheck()
duke@0 2564 %{
duke@0 2565 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2566 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2567 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2568 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2569 Label miss;
jrose@644 2570 const bool set_cond_codes = true;
duke@0 2571
duke@0 2572 MacroAssembler _masm(&cbuf);
jrose@644 2573 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2574 NULL, &miss,
jrose@644 2575 /*set_cond_codes:*/ true);
duke@0 2576 if ($primary) {
never@304 2577 __ xorptr(Rrdi, Rrdi);
duke@0 2578 }
duke@0 2579 __ bind(miss);
duke@0 2580 %}
duke@0 2581
duke@0 2582 enc_class Java_To_Interpreter(method meth)
duke@0 2583 %{
duke@0 2584 // CALL Java_To_Interpreter
duke@0 2585 // This is the instruction starting address for relocation info.
twisti@1668 2586 cbuf.set_insts_mark();
duke@0 2587 $$$emit8$primary;
duke@0 2588 // CALL directly to the runtime
duke@0 2589 emit_d32_reloc(cbuf,
twisti@1668 2590 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2591 runtime_call_Relocation::spec(),
duke@0 2592 RELOC_DISP32);
duke@0 2593 %}
duke@0 2594
twisti@1137 2595 enc_class preserve_SP %{
twisti@1668 2596 debug_only(int off0 = cbuf.insts_size());
twisti@1137 2597 MacroAssembler _masm(&cbuf);
twisti@1137 2598 // RBP is preserved across all calls, even compiled calls.
twisti@1137 2599 // Use it to preserve RSP in places where the callee might change the SP.
twisti@1487 2600 __ movptr(rbp_mh_SP_save, rsp);
twisti@1668 2601 debug_only(int off1 = cbuf.insts_size());
twisti@1137 2602 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
twisti@1137 2603 %}
twisti@1137 2604
twisti@1137 2605 enc_class restore_SP %{
twisti@1137 2606 MacroAssembler _masm(&cbuf);
twisti@1487 2607 __ movptr(rsp, rbp_mh_SP_save);
twisti@1137 2608 %}
twisti@1137 2609
duke@0 2610 enc_class Java_Static_Call(method meth)
duke@0 2611 %{
duke@0 2612 // JAVA STATIC CALL
duke@0 2613 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2614 // determine who we intended to call.
twisti@1668 2615 cbuf.set_insts_mark();
duke@0 2616 $$$emit8$primary;
duke@0 2617
duke@0 2618 if (!_method) {
duke@0 2619 emit_d32_reloc(cbuf,
twisti@1668 2620 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2621 runtime_call_Relocation::spec(),
duke@0 2622 RELOC_DISP32);
duke@0 2623 } else if (_optimized_virtual) {
duke@0 2624 emit_d32_reloc(cbuf,
twisti@1668 2625 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2626 opt_virtual_call_Relocation::spec(),
duke@0 2627 RELOC_DISP32);
duke@0 2628 } else {
duke@0 2629 emit_d32_reloc(cbuf,
twisti@1668 2630 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2631 static_call_Relocation::spec(),
duke@0 2632 RELOC_DISP32);
duke@0 2633 }
duke@0 2634 if (_method) {
duke@0 2635 // Emit stub for static call
duke@0 2636 emit_java_to_interp(cbuf);
duke@0 2637 }
duke@0 2638 %}
duke@0 2639
duke@0 2640 enc_class Java_Dynamic_Call(method meth)
duke@0 2641 %{
duke@0 2642 // JAVA DYNAMIC CALL
duke@0 2643 // !!!!!
duke@0 2644 // Generate "movq rax, -1", placeholder instruction to load oop-info
duke@0 2645 // emit_call_dynamic_prologue( cbuf );
twisti@1668 2646 cbuf.set_insts_mark();
duke@0 2647
duke@0 2648 // movq rax, -1
duke@0 2649 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2650 emit_opcode(cbuf, 0xB8 | RAX_enc);
duke@0 2651 emit_d64_reloc(cbuf,
duke@0 2652 (int64_t) Universe::non_oop_word(),
duke@0 2653 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
twisti@1668 2654 address virtual_call_oop_addr = cbuf.insts_mark();
duke@0 2655 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2656 // who we intended to call.
twisti@1668 2657 cbuf.set_insts_mark();
duke@0 2658 $$$emit8$primary;
duke@0 2659 emit_d32_reloc(cbuf,
twisti@1668 2660 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2661 virtual_call_Relocation::spec(virtual_call_oop_addr),
duke@0 2662 RELOC_DISP32);
duke@0 2663 %}
duke@0 2664
duke@0 2665 enc_class Java_Compiled_Call(method meth)
duke@0 2666 %{
duke@0 2667 // JAVA COMPILED CALL
duke@0 2668 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
duke@0 2669
duke@0 2670 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2671 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2672
duke@0 2673 // callq *disp(%rax)
twisti@1668 2674 cbuf.set_insts_mark();
duke@0 2675 $$$emit8$primary;
duke@0 2676 if (disp < 0x80) {
duke@0 2677 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2678 emit_d8(cbuf, disp); // Displacement
duke@0 2679 } else {
duke@0 2680 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2681 emit_d32(cbuf, disp); // Displacement
duke@0 2682 }
duke@0 2683 %}
duke@0 2684
duke@0 2685 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2686 %{
duke@0 2687 // SAL, SAR, SHR
duke@0 2688 int dstenc = $dst$$reg;
duke@0 2689 if (dstenc >= 8) {
duke@0 2690 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2691 dstenc -= 8;
duke@0 2692 }
duke@0 2693 $$$emit8$primary;
duke@0 2694 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2695 $$$emit8$shift$$constant;
duke@0 2696 %}
duke@0 2697
duke@0 2698 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2699 %{
duke@0 2700 // SAL, SAR, SHR
duke@0 2701 int dstenc = $dst$$reg;
duke@0 2702 if (dstenc < 8) {
duke@0 2703 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2704 } else {
duke@0 2705 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2706 dstenc -= 8;
duke@0 2707 }
duke@0 2708 $$$emit8$primary;
duke@0 2709 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2710 $$$emit8$shift$$constant;
duke@0 2711 %}
duke@0 2712
duke@0 2713 enc_class load_immI(rRegI dst, immI src)
duke@0 2714 %{
duke@0 2715 int dstenc = $dst$$reg;
duke@0 2716 if (dstenc >= 8) {
duke@0 2717 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2718 dstenc -= 8;
duke@0 2719 }
duke@0 2720 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2721 $$$emit32$src$$constant;
duke@0 2722 %}
duke@0 2723
duke@0 2724 enc_class load_immL(rRegL dst, immL src)
duke@0 2725 %{
duke@0 2726 int dstenc = $dst$$reg;
duke@0 2727 if (dstenc < 8) {
duke@0 2728 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2729 } else {
duke@0 2730 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2731 dstenc -= 8;
duke@0 2732 }
duke@0 2733 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2734 emit_d64(cbuf, $src$$constant);
duke@0 2735 %}
duke@0 2736
duke@0 2737 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2738 %{
duke@0 2739 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2740 int dstenc = $dst$$reg;
duke@0 2741 if (dstenc >= 8) {
duke@0 2742 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2743 dstenc -= 8;
duke@0 2744 }
duke@0 2745 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2746 $$$emit32$src$$constant;
duke@0 2747 %}
duke@0 2748
duke@0 2749 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2750 %{
duke@0 2751 int dstenc = $dst$$reg;
duke@0 2752 if (dstenc < 8) {
duke@0 2753 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2754 } else {
duke@0 2755 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2756 dstenc -= 8;
duke@0 2757 }
duke@0 2758 emit_opcode(cbuf, 0xC7);
duke@0 2759 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2760 $$$emit32$src$$constant;
duke@0 2761 %}
duke@0 2762
duke@0 2763 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2764 %{
duke@0 2765 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2766 int dstenc = $dst$$reg;
duke@0 2767 if (dstenc >= 8) {
duke@0 2768 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2769 dstenc -= 8;
duke@0 2770 }
duke@0 2771 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2772 $$$emit32$src$$constant;
duke@0 2773 %}
duke@0 2774
duke@0 2775 enc_class load_immP(rRegP dst, immP src)
duke@0 2776 %{
duke@0 2777 int dstenc = $dst$$reg;
duke@0 2778 if (dstenc < 8) {
duke@0 2779 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2780 } else {
duke@0 2781 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2782 dstenc -= 8;
duke@0 2783 }
duke@0 2784 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2785 // This next line should be generated from ADLC
duke@0 2786 if ($src->constant_is_oop()) {
duke@0 2787 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
duke@0 2788 } else {
duke@0 2789 emit_d64(cbuf, $src$$constant);
duke@0 2790 }
duke@0 2791 %}
duke@0 2792
duke@0 2793 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2794 enc_class enc_copy(rRegI dst, rRegI src)
duke@0 2795 %{
duke@0 2796 encode_copy(cbuf, $dst$$reg, $src$$reg);
duke@0 2797 %}
duke@0 2798
duke@0 2799 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
duke@0 2800 enc_class enc_CopyXD( RegD dst, RegD src ) %{
duke@0 2801 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
duke@0 2802 %}
duke@0 2803
duke@0 2804 enc_class enc_copy_always(rRegI dst, rRegI src)
duke@0 2805 %{
duke@0 2806 int srcenc = $src$$reg;
duke@0 2807 int dstenc = $dst$$reg;
duke@0 2808
duke@0 2809 if (dstenc < 8) {
duke@0 2810 if (srcenc >= 8) {
duke@0 2811 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2812 srcenc -= 8;
duke@0 2813 }
duke@0 2814 } else {
duke@0 2815 if (srcenc < 8) {
duke@0 2816 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2817 } else {
duke@0 2818 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2819 srcenc -= 8;
duke@0 2820 }
duke@0 2821 dstenc -= 8;
duke@0 2822 }
duke@0 2823
duke@0 2824 emit_opcode(cbuf, 0x8B);
duke@0 2825 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2826 %}
duke@0 2827
duke@0 2828 enc_class enc_copy_wide(rRegL dst, rRegL src)
duke@0 2829 %{
duke@0 2830 int srcenc = $src$$reg;
duke@0 2831 int dstenc = $dst$$reg;
duke@0 2832
duke@0 2833 if (dstenc != srcenc) {
duke@0 2834 if (dstenc < 8) {
duke@0 2835 if (srcenc < 8) {
duke@0 2836 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2837 } else {
duke@0 2838 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2839 srcenc -= 8;
duke@0 2840 }
duke@0 2841 } else {
duke@0 2842 if (srcenc < 8) {
duke@0 2843 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2844 } else {
duke@0 2845 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2846 srcenc -= 8;
duke@0 2847 }
duke@0 2848 dstenc -= 8;
duke@0 2849 }
duke@0 2850 emit_opcode(cbuf, 0x8B);
duke@0 2851 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2852 }
duke@0 2853 %}
duke@0 2854
duke@0 2855 enc_class Con32(immI src)
duke@0 2856 %{
duke@0 2857 // Output immediate
duke@0 2858 $$$emit32$src$$constant;
duke@0 2859 %}
duke@0 2860
duke@0 2861 enc_class Con64(immL src)
duke@0 2862 %{
duke@0 2863 // Output immediate
duke@0 2864 emit_d64($src$$constant);
duke@0 2865 %}
duke@0 2866
duke@0 2867 enc_class Con32F_as_bits(immF src)
duke@0 2868 %{
duke@0 2869 // Output Float immediate bits
duke@0 2870 jfloat jf = $src$$constant;
duke@0 2871 jint jf_as_bits = jint_cast(jf);
duke@0 2872 emit_d32(cbuf, jf_as_bits);
duke@0 2873 %}
duke@0 2874
duke@0 2875 enc_class Con16(immI src)
duke@0 2876 %{
duke@0 2877 // Output immediate
duke@0 2878 $$$emit16$src$$constant;
duke@0 2879 %}
duke@0 2880
duke@0 2881 // How is this different from Con32??? XXX
duke@0 2882 enc_class Con_d32(immI src)
duke@0 2883 %{
duke@0 2884 emit_d32(cbuf,$src$$constant);
duke@0 2885 %}
duke@0 2886
duke@0 2887 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2888 // Output immediate memory reference
duke@0 2889 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2890 emit_d32(cbuf, 0x00);
duke@0 2891 %}
duke@0 2892
duke@0 2893 enc_class lock_prefix()
duke@0 2894 %{
duke@0 2895 if (os::is_MP()) {
duke@0 2896 emit_opcode(cbuf, 0xF0); // lock
duke@0 2897 }
duke@0 2898 %}
duke@0 2899
duke@0 2900 enc_class REX_mem(memory mem)
duke@0 2901 %{
duke@0 2902 if ($mem$$base >= 8) {
duke@0 2903 if ($mem$$index < 8) {
duke@0 2904 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2905 } else {
duke@0 2906 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2907 }
duke@0 2908 } else {
duke@0 2909 if ($mem$$index >= 8) {
duke@0 2910 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2911 }
duke@0 2912 }
duke@0 2913 %}
duke@0 2914
duke@0 2915 enc_class REX_mem_wide(memory mem)
duke@0 2916 %{
duke@0 2917 if ($mem$$base >= 8) {
duke@0 2918 if ($mem$$index < 8) {
duke@0 2919 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2920 } else {
duke@0 2921 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2922 }
duke@0 2923 } else {
duke@0 2924 if ($mem$$index < 8) {
duke@0 2925 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2926 } else {
duke@0 2927 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2928 }
duke@0 2929 }
duke@0 2930 %}
duke@0 2931
duke@0 2932 // for byte regs
duke@0 2933 enc_class REX_breg(rRegI reg)
duke@0 2934 %{
duke@0 2935 if ($reg$$reg >= 4) {
duke@0 2936 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2937 }
duke@0 2938 %}
duke@0 2939
duke@0 2940 // for byte regs
duke@0 2941 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2942 %{
duke@0 2943 if ($dst$$reg < 8) {
duke@0 2944 if ($src$$reg >= 4) {
duke@0 2945 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2946 }
duke@0 2947 } else {
duke@0 2948 if ($src$$reg < 8) {
duke@0 2949 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2950 } else {
duke@0 2951 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2952 }
duke@0 2953 }
duke@0 2954 %}
duke@0 2955
duke@0 2956 // for byte regs
duke@0 2957 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2958 %{
duke@0 2959 if ($reg$$reg < 8) {
duke@0 2960 if ($mem$$base < 8) {
duke@0 2961 if ($mem$$index >= 8) {
duke@0 2962 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2963 } else if ($reg$$reg >= 4) {
duke@0 2964 emit_opcode(cbuf, Assembler::REX);
duke@0 2965 }
duke@0 2966 } else {
duke@0 2967 if ($mem$$index < 8) {
duke@0 2968 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2969 } else {
duke@0 2970 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2971 }
duke@0 2972 }
duke@0 2973 } else {
duke@0 2974 if ($mem$$base < 8) {
duke@0 2975 if ($mem$$index < 8) {
duke@0 2976 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2977 } else {
duke@0 2978 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2979 }
duke@0 2980 } else {
duke@0 2981 if ($mem$$index < 8) {
duke@0 2982 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2983 } else {
duke@0 2984 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2985 }
duke@0 2986 }
duke@0 2987 }
duke@0 2988 %}
duke@0 2989
duke@0 2990 enc_class REX_reg(rRegI reg)
duke@0 2991 %{
duke@0 2992 if ($reg$$reg >= 8) {
duke@0 2993 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2994 }
duke@0 2995 %}
duke@0 2996
duke@0 2997 enc_class REX_reg_wide(rRegI reg)
duke@0 2998 %{
duke@0 2999 if ($reg$$reg < 8) {
duke@0 3000 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3001 } else {
duke@0 3002 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3003 }
duke@0 3004 %}
duke@0 3005
duke@0 3006 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 3007 %{
duke@0 3008 if ($dst$$reg < 8) {
duke@0 3009 if ($src$$reg >= 8) {
duke@0 3010 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3011 }
duke@0 3012 } else {
duke@0 3013 if ($src$$reg < 8) {
duke@0 3014 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3015 } else {
duke@0 3016 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3017 }
duke@0 3018 }
duke@0 3019 %}
duke@0 3020
duke@0 3021 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 3022 %{
duke@0 3023 if ($dst$$reg < 8) {
duke@0 3024 if ($src$$reg < 8) {
duke@0 3025 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3026 } else {
duke@0 3027 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3028 }
duke@0 3029 } else {
duke@0 3030 if ($src$$reg < 8) {
duke@0 3031 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3032 } else {
duke@0 3033 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3034 }
duke@0 3035 }
duke@0 3036 %}
duke@0 3037
duke@0 3038 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 3039 %{
duke@0 3040 if ($reg$$reg < 8) {
duke@0 3041 if ($mem$$base < 8) {
duke@0 3042 if ($mem$$index >= 8) {
duke@0 3043 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3044 }
duke@0 3045 } else {
duke@0 3046 if ($mem$$index < 8) {
duke@0 3047 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3048 } else {
duke@0 3049 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3050 }
duke@0 3051 }
duke@0 3052 } else {
duke@0 3053 if ($mem$$base < 8) {
duke@0 3054 if ($mem$$index < 8) {
duke@0 3055 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3056 } else {
duke@0 3057 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3058 }
duke@0 3059 } else {
duke@0 3060 if ($mem$$index < 8) {
duke@0 3061 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3062 } else {
duke@0 3063 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3064 }
duke@0 3065 }
duke@0 3066 }
duke@0 3067 %}
duke@0 3068
duke@0 3069 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 3070 %{
duke@0 3071 if ($reg$$reg < 8) {
duke@0 3072 if ($mem$$base < 8) {
duke@0 3073 if ($mem$$index < 8) {
duke@0 3074 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3075 } else {
duke@0 3076 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3077 }
duke@0 3078 } else {
duke@0 3079 if ($mem$$index < 8) {
duke@0 3080 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3081 } else {
duke@0 3082 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3083 }
duke@0 3084 }
duke@0 3085 } else {
duke@0 3086 if ($mem$$base < 8) {
duke@0 3087 if ($mem$$index < 8) {
duke@0 3088 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3089 } else {
duke@0 3090 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 3091 }
duke@0 3092 } else {
duke@0 3093 if ($mem$$index < 8) {
duke@0 3094 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3095 } else {
duke@0 3096 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 3097 }
duke@0 3098 }
duke@0 3099 }
duke@0 3100 %}
duke@0 3101
duke@0 3102 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 3103 %{
duke@0 3104 // High registers handle in encode_RegMem
duke@0 3105 int reg = $ereg$$reg;
duke@0 3106 int base = $mem$$base;
duke@0 3107 int index = $mem$$index;
duke@0 3108 int scale = $mem$$scale;
duke@0 3109 int disp = $mem$$disp;
duke@0 3110 bool disp_is_oop = $mem->disp_is_oop();
duke@0 3111
duke@0 3112 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
duke@0 3113 %}
duke@0 3114
duke@0 3115 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 3116 %{
duke@0 3117 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 3118
duke@0 3119 // High registers handle in encode_RegMem
duke@0 3120 int base = $mem$$base;
duke@0 3121 int index = $mem$$index;
duke@0 3122 int scale = $mem$$scale;
duke@0 3123 int displace = $mem$$disp;
duke@0 3124
duke@0 3125 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
duke@0 3126 // working with static
duke@0 3127 // globals
duke@0 3128 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
duke@0 3129 disp_is_oop);
duke@0 3130 %}
duke@0 3131
duke@0 3132 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 3133 %{
duke@0 3134 int reg_encoding = $dst$$reg;
duke@0 3135 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 3136 int index = 0x04; // 0x04 indicates no index
duke@0 3137 int scale = 0x00; // 0x00 indicates no scale
duke@0 3138 int displace = $src1$$constant; // 0x00 indicates no displacement
duke@0 3139 bool disp_is_oop = false;
duke@0 3140 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
duke@0 3141 disp_is_oop);
duke@0 3142 %}
duke@0 3143
duke@0 3144 enc_class neg_reg(rRegI dst)
duke@0 3145 %{
duke@0 3146 int dstenc = $dst$$reg;
duke@0 3147 if (dstenc >= 8) {
duke@0 3148 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3149 dstenc -= 8;
duke@0 3150 }
duke@0 3151 // NEG $dst
duke@0 3152 emit_opcode(cbuf, 0xF7);
duke@0 3153 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3154 %}
duke@0 3155
duke@0 3156 enc_class neg_reg_wide(rRegI dst)
duke@0 3157 %{
duke@0 3158 int dstenc = $dst$$reg;
duke@0 3159 if (dstenc < 8) {
duke@0 3160 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3161 } else {
duke@0 3162 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3163 dstenc -= 8;
duke@0 3164 }
duke@0 3165 // NEG $dst
duke@0 3166 emit_opcode(cbuf, 0xF7);
duke@0 3167 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3168 %}
duke@0 3169
duke@0 3170 enc_class setLT_reg(rRegI dst)
duke@0 3171 %{
duke@0 3172 int dstenc = $dst$$reg;
duke@0 3173 if (dstenc >= 8) {
duke@0 3174 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3175 dstenc -= 8;
duke@0 3176 } else if (dstenc >= 4) {
duke@0 3177 emit_opcode(cbuf, Assembler::REX);
duke@0 3178 }
duke@0 3179 // SETLT $dst
duke@0 3180 emit_opcode(cbuf, 0x0F);
duke@0 3181 emit_opcode(cbuf, 0x9C);
duke@0 3182 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3183 %}
duke@0 3184
duke@0 3185 enc_class setNZ_reg(rRegI dst)
duke@0 3186 %{
duke@0 3187 int dstenc = $dst$$reg;
duke@0 3188 if (dstenc >= 8) {
duke@0 3189 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3190 dstenc -= 8;
duke@0 3191 } else if (dstenc >= 4) {
duke@0 3192 emit_opcode(cbuf, Assembler::REX);
duke@0 3193 }
duke@0 3194 // SETNZ $dst
duke@0 3195 emit_opcode(cbuf, 0x0F);
duke@0 3196 emit_opcode(cbuf, 0x95);
duke@0 3197 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3198 %}
duke@0 3199
duke@0 3200 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
duke@0 3201 rcx_RegI tmp)
duke@0 3202 %{
duke@0 3203 // cadd_cmpLT
duke@0 3204
duke@0 3205 int tmpReg = $tmp$$reg;
duke@0 3206
duke@0 3207 int penc = $p$$reg;
duke@0 3208 int qenc = $q$$reg;
duke@0 3209 int yenc = $y$$reg;
duke@0 3210
duke@0 3211 // subl $p,$q
duke@0 3212 if (penc < 8) {
duke@0 3213 if (qenc >= 8) {
duke@0 3214 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3215 }
duke@0 3216 } else {
duke@0 3217 if (qenc < 8) {
duke@0 3218 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3219 } else {
duke@0 3220 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3221 }
duke@0 3222 }
duke@0 3223 emit_opcode(cbuf, 0x2B);
duke@0 3224 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
duke@0 3225
duke@0 3226 // sbbl $tmp, $tmp
duke@0 3227 emit_opcode(cbuf, 0x1B);
duke@0 3228 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
duke@0 3229
duke@0 3230 // andl $tmp, $y
duke@0 3231 if (yenc >= 8) {
duke@0 3232 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3233 }
duke@0 3234 emit_opcode(cbuf, 0x23);
duke@0 3235 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
duke@0 3236
duke@0 3237 // addl $p,$tmp
duke@0 3238 if (penc >= 8) {
duke@0 3239 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3240 }
duke@0 3241 emit_opcode(cbuf, 0x03);
duke@0 3242 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
duke@0 3243 %}
duke@0 3244
duke@0 3245 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 3246 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 3247 %{
duke@0 3248 int src1enc = $src1$$reg;
duke@0 3249 int src2enc = $src2$$reg;
duke@0 3250 int dstenc = $dst$$reg;
duke@0 3251
duke@0 3252 // cmpq $src1, $src2
duke@0 3253 if (src1enc < 8) {
duke@0 3254 if (src2enc < 8) {
duke@0 3255 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3256 } else {
duke@0 3257 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3258 }
duke@0 3259 } else {
duke@0 3260 if (src2enc < 8) {
duke@0 3261 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3262 } else {
duke@0 3263 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3264 }
duke@0 3265 }
duke@0 3266 emit_opcode(cbuf, 0x3B);
duke@0 3267 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 3268
duke@0 3269 // movl $dst, -1
duke@0 3270 if (dstenc >= 8) {
duke@0 3271 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3272 }
duke@0 3273 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 3274 emit_d32(cbuf, -1);
duke@0 3275
duke@0 3276 // jl,s done
duke@0 3277 emit_opcode(cbuf, 0x7C);
duke@0 3278 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 3279
duke@0 3280 // setne $dst
duke@0 3281 if (dstenc >= 4) {
duke@0 3282 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3283 }
duke@0 3284 emit_opcode(cbuf, 0x0F);
duke@0 3285 emit_opcode(cbuf, 0x95);
duke@0 3286 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 3287
duke@0 3288 // movzbl $dst, $dst
duke@0 3289 if (dstenc >= 4) {
duke@0 3290 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 3291 }
duke@0 3292 emit_opcode(cbuf, 0x0F);
duke@0 3293 emit_opcode(cbuf, 0xB6);
duke@0 3294 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 3295 %}
duke@0 3296
duke@0 3297 enc_class Push_ResultXD(regD dst) %{
duke@0 3298 int dstenc = $dst$$reg;
duke@0 3299
duke@0 3300 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
duke@0 3301
duke@0 3302 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
duke@0 3303 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 3304 if (dstenc >= 8) {
duke@0 3305 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3306 }
duke@0 3307 emit_opcode (cbuf, 0x0F );
duke@0 3308 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
duke@0 3309 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3310
duke@0 3311 // add rsp,8
duke@0 3312 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3313 emit_opcode(cbuf,0x83);
duke@0 3314 emit_rm(cbuf,0x3, 0x0, RSP_enc);
duke@0 3315 emit_d8(cbuf,0x08);
duke@0 3316 %}
duke@0 3317
duke@0 3318 enc_class Push_SrcXD(regD src) %{
duke@0 3319 int srcenc = $src$$reg;
duke@0 3320
duke@0 3321 // subq rsp,#8
duke@0 3322 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3323 emit_opcode(cbuf, 0x83);
duke@0 3324 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3325 emit_d8(cbuf, 0x8);
duke@0 3326
duke@0 3327 // movsd [rsp],src
duke@0 3328 emit_opcode(cbuf, 0xF2);
duke@0 3329 if (srcenc >= 8) {
duke@0 3330 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3331 }
duke@0 3332 emit_opcode(cbuf, 0x0F);
duke@0 3333 emit_opcode(cbuf, 0x11);
duke@0 3334 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3335
duke@0 3336 // fldd [rsp]
duke@0 3337 emit_opcode(cbuf, 0x66);
duke@0 3338 emit_opcode(cbuf, 0xDD);
duke@0 3339 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
duke@0 3340 %}
duke@0 3341
duke@0 3342
duke@0 3343 enc_class movq_ld(regD dst, memory mem) %{
duke@0 3344 MacroAssembler _masm(&cbuf);
twisti@624 3345 __ movq($dst$$XMMRegister, $mem$$Address);
duke@0 3346 %}
duke@0 3347
duke@0 3348 enc_class movq_st(memory mem, regD src) %{
duke@0 3349 MacroAssembler _masm(&cbuf);
twisti@624 3350 __ movq($mem$$Address, $src$$XMMRegister);
duke@0 3351 %}
duke@0 3352
duke@0 3353 enc_class pshufd_8x8(regF dst, regF src) %{
duke@0 3354 MacroAssembler _masm(&cbuf);
duke@0 3355
duke@0 3356 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
duke@0 3357 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
duke@0 3358 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
duke@0 3359 %}
duke@0 3360
duke@0 3361 enc_class pshufd_4x16(regF dst, regF src) %{
duke@0 3362 MacroAssembler _masm(&cbuf);
duke@0 3363
duke@0 3364 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
duke@0 3365 %}
duke@0 3366
duke@0 3367 enc_class pshufd(regD dst, regD src, int mode) %{
duke@0 3368 MacroAssembler _masm(&cbuf);
duke@0 3369
duke@0 3370 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
duke@0 3371 %}
duke@0 3372
duke@0 3373 enc_class pxor(regD dst, regD src) %{
duke@0 3374 MacroAssembler _masm(&cbuf);
duke@0 3375
duke@0 3376 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
duke@0 3377 %}
duke@0 3378
duke@0 3379 enc_class mov_i2x(regD dst, rRegI src) %{
duke@0 3380 MacroAssembler _masm(&cbuf);
duke@0 3381
duke@0 3382 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
duke@0 3383 %}
duke@0 3384
duke@0 3385 // obj: object to lock
duke@0 3386 // box: box address (header location) -- killed
duke@0 3387 // tmp: rax -- killed
duke@0 3388 // scr: rbx -- killed
duke@0 3389 //
duke@0 3390 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 3391 // from i486.ad. See that file for comments.
duke@0 3392 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 3393 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 3394
duke@0 3395
duke@0 3396 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 3397 %{
duke@0 3398 Register objReg = as_Register((int)$obj$$reg);
duke@0 3399 Register boxReg = as_Register((int)$box$$reg);
duke@0 3400 Register tmpReg = as_Register($tmp$$reg);
duke@0 3401 Register scrReg = as_Register($scr$$reg);
duke@0 3402 MacroAssembler masm(&cbuf);
duke@0 3403
duke@0 3404 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 3405 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 3406 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 3407
duke@0 3408 if (_counters != NULL) {
duke@0 3409 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 3410 }
duke@0 3411 if (EmitSync & 1) {
never@304 3412 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3413 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3414 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 3415 } else
duke@0 3416 if (EmitSync & 2) {
duke@0 3417 Label DONE_LABEL;
duke@0 3418 if (UseBiasedLocking) {
duke@0 3419 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 3420 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 3421 }
never@304 3422 // QQQ was movl...
never@304 3423 masm.movptr(tmpReg, 0x1);
never@304 3424 masm.orptr(tmpReg, Address(objReg, 0));
never@304 3425 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3426 if (os::is_MP()) {
duke@0 3427 masm.lock();
duke@0 3428 }
never@304 3429 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3430 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 3431
duke@0 3432 // Recursive locking
never@304 3433 masm.subptr(tmpReg, rsp);
never@304 3434 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3435 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3436
duke@0 3437 masm.bind(DONE_LABEL);
duke@0 3438 masm.nop(); // avoid branch to branch
duke@0 3439 } else {
duke@0 3440 Label DONE_LABEL, IsInflated, Egress;
duke@0 3441
never@304 3442 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3443 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
never@304 3444 masm.jcc (Assembler::notZero, IsInflated) ;
never@304 3445
duke@0 3446 // it's stack-locked, biased or neutral
duke@0 3447 // TODO: optimize markword triage order to reduce the number of
duke@0 3448 // conditional branches in the most common cases.
duke@0 3449 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 3450 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 3451 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 3452
kvn@420 3453 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3454 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 3455 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 3456 }
duke@0 3457
never@304 3458 // was q will it destroy high?
never@304 3459 masm.orl (tmpReg, 1) ;
never@304 3460 masm.movptr(Address(boxReg, 0), tmpReg) ;
never@304 3461 if (os::is_MP()) { masm.lock(); }
never@304 3462 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3463 if (_counters != NULL) {
duke@0 3464 masm.cond_inc32(Assembler::equal,
duke@0 3465 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3466 }
duke@0 3467 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 3468
duke@0 3469 // Recursive locking
never@304 3470 masm.subptr(tmpReg, rsp);
never@304 3471 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3472 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3473 if (_counters != NULL) {
duke@0 3474 masm.cond_inc32(Assembler::equal,
duke@0 3475 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3476 }
duke@0 3477 masm.jmp (DONE_LABEL) ;
duke@0 3478
duke@0 3479 masm.bind (IsInflated) ;
duke@0 3480 // It's inflated
duke@0 3481
duke@0 3482 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 3483 // relocating (deferring) the following ST.
duke@0 3484 // We should also think about trying a CAS without having
duke@0 3485 // fetched _owner. If the CAS is successful we may
duke@0 3486 // avoid an RTO->RTS upgrade on the $line.
never@304 3487 // Without cast to int32_t a movptr will destroy r10 which is typically obj
never@304 3488 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
never@304 3489
never@304 3490 masm.mov (boxReg, tmpReg) ;
never@304 3491 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3492 masm.testptr(tmpReg, tmpReg) ;
never@304 3493 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 3494
duke@0 3495 // It's inflated and appears unlocked
never@304 3496 if (os::is_MP()) { masm.lock(); }
never@304 3497 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 3498 // Intentional fall-through into DONE_LABEL ...
duke@0 3499
duke@0 3500 masm.bind (DONE_LABEL) ;
duke@0 3501 masm.nop () ; // avoid jmp to jmp
duke@0 3502 }
duke@0 3503 %}
duke@0 3504
duke@0 3505 // obj: object to unlock
duke@0 3506 // box: box address (displaced header location), killed
duke@0 3507 // RBX: killed tmp; cannot be obj nor box
duke@0 3508 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 3509 %{
duke@0 3510
duke@0 3511 Register objReg = as_Register($obj$$reg);
duke@0 3512 Register boxReg = as_Register($box$$reg);
duke@0 3513 Register tmpReg = as_Register($tmp$$reg);
duke@0 3514 MacroAssembler masm(&cbuf);
duke@0 3515
never@304 3516 if (EmitSync & 4) {
never@304 3517 masm.cmpptr(rsp, 0) ;
duke@0 3518 } else
duke@0 3519 if (EmitSync & 8) {
duke@0 3520 Label DONE_LABEL;
duke@0 3521 if (UseBiasedLocking) {
duke@0 3522 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3523 }
duke@0 3524
duke@0 3525 // Check whether the displaced header is 0
duke@0 3526 //(=> recursive unlock)
never@304 3527 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 3528 masm.testptr(tmpReg, tmpReg);
duke@0 3529 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 3530
duke@0 3531 // If not recursive lock, reset the header to displaced header
duke@0 3532 if (os::is_MP()) {
duke@0 3533 masm.lock();
duke@0 3534 }
never@304 3535 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3536 masm.bind(DONE_LABEL);
duke@0 3537 masm.nop(); // avoid branch to branch
duke@0 3538 } else {
duke@0 3539 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 3540
kvn@420 3541 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3542 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3543 }
never@304 3544
never@304 3545 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3546 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
never@304 3547 masm.jcc (Assembler::zero, DONE_LABEL) ;
never@304 3548 masm.testl (tmpReg, 0x02) ;
never@304 3549 masm.jcc (Assembler::zero, Stacked) ;
never@304 3550
duke@0 3551 // It's inflated
never@304 3552 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
never@304 3553 masm.xorptr(boxReg, r15_thread) ;
never@304 3554 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
never@304 3555 masm.jcc (Assembler::notZero, DONE_LABEL) ;
never@304 3556 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
never@304 3557 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
never@304 3558 masm.jcc (Assembler::notZero, CheckSucc) ;
never@304 3559 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
never@304 3560 masm.jmp (DONE_LABEL) ;
never@304 3561
never@304 3562 if ((EmitSync & 65536) == 0) {
duke@0 3563 Label LSuccess, LGoSlowPath ;
duke@0 3564 masm.bind (CheckSucc) ;
never@304 3565 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3566 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 3567
duke@0 3568 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 3569 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 3570 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 3571 // are all faster when the write buffer is populated.
never@304 3572 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3573 if (os::is_MP()) {
never@304 3574 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 3575 }
never@304 3576 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3577 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 3578
never@304 3579 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 3580 if (os::is_MP()) { masm.lock(); }
never@304 3581 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 3582 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 3583 // Intentional fall-through into slow-path
duke@0 3584
duke@0 3585 masm.bind (LGoSlowPath) ;
duke@0 3586 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 3587 masm.jmp (DONE_LABEL) ;
duke@0 3588
duke@0 3589 masm.bind (LSuccess) ;
duke@0 3590 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 3591 masm.jmp (DONE_LABEL) ;
duke@0 3592 }
duke@0 3593
never@304 3594 masm.bind (Stacked) ;
never@304 3595 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
never@304 3596 if (os::is_MP()) { masm.lock(); }
never@304 3597 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3598
duke@0 3599 if (EmitSync & 65536) {
duke@0 3600 masm.bind (CheckSucc) ;
duke@0 3601 }
duke@0 3602 masm.bind(DONE_LABEL);
duke@0 3603 if (EmitSync & 32768) {
duke@0 3604 masm.nop(); // avoid branch to branch
duke@0 3605 }
duke@0 3606 }
duke@0 3607 %}
duke@0 3608
rasbold@169 3609
duke@0 3610 enc_class enc_rethrow()
duke@0 3611 %{
twisti@1668 3612 cbuf.set_insts_mark();
duke@0 3613 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 3614 emit_d32_reloc(cbuf,
twisti@1668 3615 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 3616 runtime_call_Relocation::spec(),
duke@0 3617 RELOC_DISP32);
duke@0 3618 %}
duke@0 3619
duke@0 3620 enc_class absF_encoding(regF dst)
duke@0 3621 %{
duke@0 3622 int dstenc = $dst$$reg;
never@304 3623 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
duke@0 3624
twisti@1668 3625 cbuf.set_insts_mark();
duke@0 3626 if (dstenc >= 8) {
duke@0 3627 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3628 dstenc -= 8;
duke@0 3629 }
duke@0 3630 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3631 emit_opcode(cbuf, 0x0F);
duke@0 3632 emit_opcode(cbuf, 0x54);
duke@0 3633 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3634 emit_d32_reloc(cbuf, signmask_address);
duke@0 3635 %}
duke@0 3636
duke@0 3637 enc_class absD_encoding(regD dst)
duke@0 3638 %{
duke@0 3639 int dstenc = $dst$$reg;
never@304 3640 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
duke@0 3641
twisti@1668 3642 cbuf.set_insts_mark();
duke@0 3643 emit_opcode(cbuf, 0x66);
duke@0 3644 if (dstenc >= 8) {
duke@0 3645 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3646 dstenc -= 8;
duke@0 3647 }
duke@0 3648 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3649 emit_opcode(cbuf, 0x0F);
duke@0 3650 emit_opcode(cbuf, 0x54);
duke@0 3651 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3652 emit_d32_reloc(cbuf, signmask_address);
duke@0 3653 %}
duke@0 3654
duke@0 3655 enc_class negF_encoding(regF dst)
duke@0 3656 %{
duke@0 3657 int dstenc = $dst$$reg;
never@304 3658 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
duke@0 3659
twisti@1668 3660 cbuf.set_insts_mark();
duke@0 3661 if (dstenc >= 8) {
duke@0 3662 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3663 dstenc -= 8;
duke@0 3664 }
duke@0 3665 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3666 emit_opcode(cbuf, 0x0F);
duke@0 3667 emit_opcode(cbuf, 0x57);
duke@0 3668 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3669 emit_d32_reloc(cbuf, signflip_address);
duke@0 3670 %}
duke@0 3671
duke@0 3672 enc_class negD_encoding(regD dst)
duke@0 3673 %{
duke@0 3674 int dstenc = $dst$$reg;
never@304 3675 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3676
twisti@1668 3677 cbuf.set_insts_mark();
duke@0 3678 emit_opcode(cbuf, 0x66);
duke@0 3679 if (dstenc >= 8) {
duke@0 3680 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3681 dstenc -= 8;
duke@0 3682 }
duke@0 3683 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3684 emit_opcode(cbuf, 0x0F);
duke@0 3685 emit_opcode(cbuf, 0x57);
duke@0 3686 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3687 emit_d32_reloc(cbuf, signflip_address);
duke@0 3688 %}
duke@0 3689
duke@0 3690 enc_class f2i_fixup(rRegI dst, regF src)
duke@0 3691 %{
duke@0 3692 int dstenc = $dst$$reg;
duke@0 3693 int srcenc = $src$$reg;
duke@0 3694
duke@0 3695 // cmpl $dst, #0x80000000
duke@0 3696 if (dstenc >= 8) {
duke@0 3697 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3698 }
duke@0 3699 emit_opcode(cbuf, 0x81);
duke@0 3700 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3701 emit_d32(cbuf, 0x80000000);
duke@0 3702
duke@0 3703 // jne,s done
duke@0 3704 emit_opcode(cbuf, 0x75);
duke@0 3705 if (srcenc < 8 && dstenc < 8) {
duke@0 3706 emit_d8(cbuf, 0xF);
duke@0 3707 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3708 emit_d8(cbuf, 0x11);
duke@0 3709 } else {
duke@0 3710 emit_d8(cbuf, 0x10);
duke@0 3711 }
duke@0 3712
duke@0 3713 // subq rsp, #8
duke@0 3714 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3715 emit_opcode(cbuf, 0x83);
duke@0 3716 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3717 emit_d8(cbuf, 8);
duke@0 3718
duke@0 3719 // movss [rsp], $src
duke@0 3720 emit_opcode(cbuf, 0xF3);
duke@0 3721 if (srcenc >= 8) {
duke@0 3722 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3723 }
duke@0 3724 emit_opcode(cbuf, 0x0F);
duke@0 3725 emit_opcode(cbuf, 0x11);
duke@0 3726 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3727
duke@0 3728 // call f2i_fixup
twisti@1668 3729 cbuf.set_insts_mark();
duke@0 3730 emit_opcode(cbuf, 0xE8);
duke@0 3731 emit_d32_reloc(cbuf,
duke@0 3732 (int)
twisti@1668 3733 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4),
duke@0 3734 runtime_call_Relocation::spec(),
duke@0 3735 RELOC_DISP32);
duke@0 3736
duke@0 3737 // popq $dst
duke@0 3738 if (dstenc >= 8) {
duke@0 3739 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3740 }
duke@0 3741 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3742
duke@0 3743 // done:
duke@0 3744 %}
duke@0 3745
duke@0 3746 enc_class f2l_fixup(rRegL dst, regF src)
duke@0 3747 %{
duke@0 3748 int dstenc = $dst$$reg;
duke@0 3749 int srcenc = $src$$reg;
never@304 3750 address const_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3751
duke@0 3752 // cmpq $dst, [0x8000000000000000]
twisti@1668 3753 cbuf.set_insts_mark();
duke@0 3754 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 3755 emit_opcode(cbuf, 0x39);
duke@0 3756 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3757 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
duke@0 3758 emit_d32_reloc(cbuf, const_address);
duke@0 3759
duke@0 3760
duke@0 3761 // jne,s done
duke@0 3762 emit_opcode(cbuf, 0x75);
duke@0 3763 if (srcenc < 8 && dstenc < 8) {
duke@0 3764 emit_d8(cbuf, 0xF);
duke@0 3765 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3766 emit_d8(cbuf, 0x11);
duke@0 3767 } else {
duke@0 3768 emit_d8(cbuf, 0x10);
duke@0 3769 }
duke@0 3770
duke@0 3771 // subq rsp, #8
duke@0 3772 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3773 emit_opcode(cbuf, 0x83);
duke@0 3774 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3775 emit_d8(cbuf, 8);
duke@0 3776
duke@0 3777 // movss [rsp], $src
duke@0 3778 emit_opcode(cbuf, 0xF3);
duke@0 3779 if (srcenc >= 8) {
duke@0 3780 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3781 }
duke@0 3782 emit_opcode(cbuf, 0x0F);
duke@0 3783 emit_opcode(cbuf, 0x11);
duke@0 3784 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3785
duke@0 3786 // call f2l_fixup
twisti@1668 3787 cbuf.set_insts_mark();
duke@0 3788 emit_opcode(cbuf, 0xE8);
duke@0 3789 emit_d32_reloc(cbuf,
duke@0 3790 (int)
twisti@1668 3791 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4),
duke@0 3792 runtime_call_Relocation::spec(),
duke@0 3793 RELOC_DISP32);
duke@0 3794
duke@0 3795 // popq $dst
duke@0 3796 if (dstenc >= 8) {
duke@0 3797 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3798 }
duke@0 3799 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3800
duke@0 3801 // done:
duke@0 3802 %}
duke@0 3803
duke@0 3804 enc_class d2i_fixup(rRegI dst, regD src)
duke@0 3805 %{
duke@0 3806 int dstenc = $dst$$reg;
duke@0 3807 int srcenc = $src$$reg;
duke@0 3808
duke@0 3809 // cmpl $dst, #0x80000000
duke@0 3810 if (dstenc >= 8) {
duke@0 3811 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3812 }
duke@0 3813 emit_opcode(cbuf, 0x81);
duke@0 3814 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3815 emit_d32(cbuf, 0x80000000);
duke@0 3816
duke@0 3817 // jne,s done
duke@0 3818 emit_opcode(cbuf, 0x75);
duke@0 3819 if (srcenc < 8 && dstenc < 8) {
duke@0 3820 emit_d8(cbuf, 0xF);
duke@0 3821 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3822 emit_d8(cbuf, 0x11);
duke@0 3823 } else {
duke@0 3824 emit_d8(cbuf, 0x10);
duke@0 3825 }
duke@0 3826
duke@0 3827 // subq rsp, #8
duke@0 3828 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3829 emit_opcode(cbuf, 0x83);
duke@0 3830 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3831 emit_d8(cbuf, 8);
duke@0 3832
duke@0 3833 // movsd [rsp], $src
duke@0 3834 emit_opcode(cbuf, 0xF2);
duke@0 3835 if (srcenc >= 8) {
duke@0 3836 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3837 }
duke@0 3838 emit_opcode(cbuf, 0x0F);
duke@0 3839 emit_opcode(cbuf, 0x11);
duke@0 3840 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3841
duke@0 3842 // call d2i_fixup
twisti@1668 3843 cbuf.set_insts_mark();
duke@0 3844 emit_opcode(cbuf, 0xE8);
duke@0 3845 emit_d32_reloc(cbuf,
duke@0 3846 (int)
twisti@1668 3847 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4),
duke@0 3848 runtime_call_Relocation::spec(),
duke@0 3849 RELOC_DISP32);
duke@0 3850
duke@0 3851 // popq $dst
duke@0 3852 if (dstenc >= 8) {
duke@0 3853 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3854 }
duke@0 3855 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3856
duke@0 3857 // done:
duke@0 3858 %}
duke@0 3859
duke@0 3860 enc_class d2l_fixup(rRegL dst, regD src)
duke@0 3861 %{
duke@0 3862 int dstenc = $dst$$reg;
duke@0 3863 int srcenc = $src$$reg;
never@304 3864 address const_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3865
duke@0 3866 // cmpq $dst, [0x8000000000000000]
twisti@1668 3867 cbuf.set_insts_mark();
duke@0 3868 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 3869 emit_opcode(cbuf, 0x39);
duke@0 3870 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3871 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
duke@0 3872 emit_d32_reloc(cbuf, const_address);
duke@0 3873
duke@0 3874
duke@0 3875 // jne,s done
duke@0 3876 emit_opcode(cbuf, 0x75);
duke@0 3877 if (srcenc < 8 && dstenc < 8) {
duke@0 3878 emit_d8(cbuf, 0xF);
duke@0 3879 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3880 emit_d8(cbuf, 0x11);
duke@0 3881 } else {
duke@0 3882 emit_d8(cbuf, 0x10);
duke@0 3883 }
duke@0 3884
duke@0 3885 // subq rsp, #8
duke@0 3886 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3887 emit_opcode(cbuf, 0x83);
duke@0 3888 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3889 emit_d8(cbuf, 8);
duke@0 3890
duke@0 3891 // movsd [rsp], $src
duke@0 3892 emit_opcode(cbuf, 0xF2);
duke@0 3893 if (srcenc >= 8) {
duke@0 3894 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3895 }
duke@0 3896 emit_opcode(cbuf, 0x0F);
duke@0 3897 emit_opcode(cbuf, 0x11);
duke@0 3898 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3899
duke@0