annotate src/cpu/x86/vm/x86_64.ad @ 3447:8c92982cbbc4

7119644: Increase superword's vector size up to 256 bits Summary: Increase vector size up to 256-bits for YMM AVX registers on x86. Reviewed-by: never, twisti, roland
author kvn
date Fri, 15 Jun 2012 01:25:19 -0700
parents 8b0a4867acf0
children 006050192a5a
rev   line source
duke@0 1 //
kvn@3142 2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // Specify priority of register selection within phases of register
duke@0 135 // allocation. Highest priority is first. A useful heuristic is to
duke@0 136 // give registers a low priority when they are required by machine
duke@0 137 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 138 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 139 // which participate in fixed calling sequences should come last.
duke@0 140 // Registers which are used as pairs must fall on an even boundary.
duke@0 141
duke@0 142 alloc_class chunk0(R10, R10_H,
duke@0 143 R11, R11_H,
duke@0 144 R8, R8_H,
duke@0 145 R9, R9_H,
duke@0 146 R12, R12_H,
duke@0 147 RCX, RCX_H,
duke@0 148 RBX, RBX_H,
duke@0 149 RDI, RDI_H,
duke@0 150 RDX, RDX_H,
duke@0 151 RSI, RSI_H,
duke@0 152 RAX, RAX_H,
duke@0 153 RBP, RBP_H,
duke@0 154 R13, R13_H,
duke@0 155 R14, R14_H,
duke@0 156 R15, R15_H,
duke@0 157 RSP, RSP_H);
duke@0 158
duke@0 159
duke@0 160 //----------Architecture Description Register Classes--------------------------
duke@0 161 // Several register classes are automatically defined based upon information in
duke@0 162 // this architecture description.
duke@0 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 167 //
duke@0 168
duke@0 169 // Class for all pointer registers (including RSP)
duke@0 170 reg_class any_reg(RAX, RAX_H,
duke@0 171 RDX, RDX_H,
duke@0 172 RBP, RBP_H,
duke@0 173 RDI, RDI_H,
duke@0 174 RSI, RSI_H,
duke@0 175 RCX, RCX_H,
duke@0 176 RBX, RBX_H,
duke@0 177 RSP, RSP_H,
duke@0 178 R8, R8_H,
duke@0 179 R9, R9_H,
duke@0 180 R10, R10_H,
duke@0 181 R11, R11_H,
duke@0 182 R12, R12_H,
duke@0 183 R13, R13_H,
duke@0 184 R14, R14_H,
duke@0 185 R15, R15_H);
duke@0 186
duke@0 187 // Class for all pointer registers except RSP
duke@0 188 reg_class ptr_reg(RAX, RAX_H,
duke@0 189 RDX, RDX_H,
duke@0 190 RBP, RBP_H,
duke@0 191 RDI, RDI_H,
duke@0 192 RSI, RSI_H,
duke@0 193 RCX, RCX_H,
duke@0 194 RBX, RBX_H,
duke@0 195 R8, R8_H,
duke@0 196 R9, R9_H,
duke@0 197 R10, R10_H,
duke@0 198 R11, R11_H,
duke@0 199 R13, R13_H,
duke@0 200 R14, R14_H);
duke@0 201
duke@0 202 // Class for all pointer registers except RAX and RSP
duke@0 203 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 204 RBP, RBP_H,
duke@0 205 RDI, RDI_H,
duke@0 206 RSI, RSI_H,
duke@0 207 RCX, RCX_H,
duke@0 208 RBX, RBX_H,
duke@0 209 R8, R8_H,
duke@0 210 R9, R9_H,
duke@0 211 R10, R10_H,
duke@0 212 R11, R11_H,
duke@0 213 R13, R13_H,
duke@0 214 R14, R14_H);
duke@0 215
duke@0 216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 217 RAX, RAX_H,
duke@0 218 RDI, RDI_H,
duke@0 219 RSI, RSI_H,
duke@0 220 RCX, RCX_H,
duke@0 221 RBX, RBX_H,
duke@0 222 R8, R8_H,
duke@0 223 R9, R9_H,
duke@0 224 R10, R10_H,
duke@0 225 R11, R11_H,
duke@0 226 R13, R13_H,
duke@0 227 R14, R14_H);
duke@0 228
duke@0 229 // Class for all pointer registers except RAX, RBX and RSP
duke@0 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 231 RBP, RBP_H,
duke@0 232 RDI, RDI_H,
duke@0 233 RSI, RSI_H,
duke@0 234 RCX, RCX_H,
duke@0 235 R8, R8_H,
duke@0 236 R9, R9_H,
duke@0 237 R10, R10_H,
duke@0 238 R11, R11_H,
duke@0 239 R13, R13_H,
duke@0 240 R14, R14_H);
duke@0 241
duke@0 242 // Singleton class for RAX pointer register
duke@0 243 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 244
duke@0 245 // Singleton class for RBX pointer register
duke@0 246 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 247
duke@0 248 // Singleton class for RSI pointer register
duke@0 249 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 250
duke@0 251 // Singleton class for RDI pointer register
duke@0 252 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 253
duke@0 254 // Singleton class for RBP pointer register
duke@0 255 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 256
duke@0 257 // Singleton class for stack pointer
duke@0 258 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 259
duke@0 260 // Singleton class for TLS pointer
duke@0 261 reg_class ptr_r15_reg(R15, R15_H);
duke@0 262
duke@0 263 // Class for all long registers (except RSP)
duke@0 264 reg_class long_reg(RAX, RAX_H,
duke@0 265 RDX, RDX_H,
duke@0 266 RBP, RBP_H,
duke@0 267 RDI, RDI_H,
duke@0 268 RSI, RSI_H,
duke@0 269 RCX, RCX_H,
duke@0 270 RBX, RBX_H,
duke@0 271 R8, R8_H,
duke@0 272 R9, R9_H,
duke@0 273 R10, R10_H,
duke@0 274 R11, R11_H,
duke@0 275 R13, R13_H,
duke@0 276 R14, R14_H);
duke@0 277
duke@0 278 // Class for all long registers except RAX, RDX (and RSP)
duke@0 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 280 RDI, RDI_H,
duke@0 281 RSI, RSI_H,
duke@0 282 RCX, RCX_H,
duke@0 283 RBX, RBX_H,
duke@0 284 R8, R8_H,
duke@0 285 R9, R9_H,
duke@0 286 R10, R10_H,
duke@0 287 R11, R11_H,
duke@0 288 R13, R13_H,
duke@0 289 R14, R14_H);
duke@0 290
duke@0 291 // Class for all long registers except RCX (and RSP)
duke@0 292 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 293 RDI, RDI_H,
duke@0 294 RSI, RSI_H,
duke@0 295 RAX, RAX_H,
duke@0 296 RDX, RDX_H,
duke@0 297 RBX, RBX_H,
duke@0 298 R8, R8_H,
duke@0 299 R9, R9_H,
duke@0 300 R10, R10_H,
duke@0 301 R11, R11_H,
duke@0 302 R13, R13_H,
duke@0 303 R14, R14_H);
duke@0 304
duke@0 305 // Class for all long registers except RAX (and RSP)
duke@0 306 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 307 RDX, RDX_H,
duke@0 308 RDI, RDI_H,
duke@0 309 RSI, RSI_H,
duke@0 310 RCX, RCX_H,
duke@0 311 RBX, RBX_H,
duke@0 312 R8, R8_H,
duke@0 313 R9, R9_H,
duke@0 314 R10, R10_H,
duke@0 315 R11, R11_H,
duke@0 316 R13, R13_H,
duke@0 317 R14, R14_H);
duke@0 318
duke@0 319 // Singleton class for RAX long register
duke@0 320 reg_class long_rax_reg(RAX, RAX_H);
duke@0 321
duke@0 322 // Singleton class for RCX long register
duke@0 323 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 324
duke@0 325 // Singleton class for RDX long register
duke@0 326 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 327
duke@0 328 // Class for all int registers (except RSP)
duke@0 329 reg_class int_reg(RAX,
duke@0 330 RDX,
duke@0 331 RBP,
duke@0 332 RDI,
duke@0 333 RSI,
duke@0 334 RCX,
duke@0 335 RBX,
duke@0 336 R8,
duke@0 337 R9,
duke@0 338 R10,
duke@0 339 R11,
duke@0 340 R13,
duke@0 341 R14);
duke@0 342
duke@0 343 // Class for all int registers except RCX (and RSP)
duke@0 344 reg_class int_no_rcx_reg(RAX,
duke@0 345 RDX,
duke@0 346 RBP,
duke@0 347 RDI,
duke@0 348 RSI,
duke@0 349 RBX,
duke@0 350 R8,
duke@0 351 R9,
duke@0 352 R10,
duke@0 353 R11,
duke@0 354 R13,
duke@0 355 R14);
duke@0 356
duke@0 357 // Class for all int registers except RAX, RDX (and RSP)
duke@0 358 reg_class int_no_rax_rdx_reg(RBP,
never@304 359 RDI,
duke@0 360 RSI,
duke@0 361 RCX,
duke@0 362 RBX,
duke@0 363 R8,
duke@0 364 R9,
duke@0 365 R10,
duke@0 366 R11,
duke@0 367 R13,
duke@0 368 R14);
duke@0 369
duke@0 370 // Singleton class for RAX int register
duke@0 371 reg_class int_rax_reg(RAX);
duke@0 372
duke@0 373 // Singleton class for RBX int register
duke@0 374 reg_class int_rbx_reg(RBX);
duke@0 375
duke@0 376 // Singleton class for RCX int register
duke@0 377 reg_class int_rcx_reg(RCX);
duke@0 378
duke@0 379 // Singleton class for RCX int register
duke@0 380 reg_class int_rdx_reg(RDX);
duke@0 381
duke@0 382 // Singleton class for RCX int register
duke@0 383 reg_class int_rdi_reg(RDI);
duke@0 384
duke@0 385 // Singleton class for instruction pointer
duke@0 386 // reg_class ip_reg(RIP);
duke@0 387
kvn@3447 388 %}
duke@0 389
duke@0 390 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 391 // This is a block of C++ code which provides values, functions, and
duke@0 392 // definitions necessary in the rest of the architecture description
duke@0 393 source %{
never@304 394 #define RELOC_IMM64 Assembler::imm_operand
duke@0 395 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 396
duke@0 397 #define __ _masm.
duke@0 398
twisti@1137 399 static int preserve_SP_size() {
kvn@2953 400 return 3; // rex.w, op, rm(reg/reg)
twisti@1137 401 }
twisti@1137 402
duke@0 403 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 404 // from the start of the call to the point where the return address
duke@0 405 // will point.
duke@0 406 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 407 {
twisti@1137 408 int offset = 5; // 5 bytes from start of call to where return address points
twisti@1137 409 if (_method_handle_invoke)
twisti@1137 410 offset += preserve_SP_size();
twisti@1137 411 return offset;
duke@0 412 }
duke@0 413
duke@0 414 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 415 {
duke@0 416 return 15; // 15 bytes from start of call to where return address points
duke@0 417 }
duke@0 418
duke@0 419 // In os_cpu .ad file
duke@0 420 // int MachCallRuntimeNode::ret_addr_offset()
duke@0 421
iveresov@2251 422 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 423 // it does if the polling page is more than disp32 away.
duke@0 424 bool SafePointNode::needs_polling_address_input()
duke@0 425 {
iveresov@2251 426 return Assembler::is_polling_page_far();
duke@0 427 }
duke@0 428
duke@0 429 //
duke@0 430 // Compute padding required for nodes which need alignment
duke@0 431 //
duke@0 432
duke@0 433 // The address of the call instruction needs to be 4-byte aligned to
duke@0 434 // ensure that it does not span a cache line so that it can be patched.
duke@0 435 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 436 {
duke@0 437 current_offset += 1; // skip call opcode byte
duke@0 438 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 439 }
duke@0 440
duke@0 441 // The address of the call instruction needs to be 4-byte aligned to
duke@0 442 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 443 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 444 {
twisti@1137 445 current_offset += preserve_SP_size(); // skip mov rbp, rsp
twisti@1137 446 current_offset += 1; // skip call opcode byte
twisti@1137 447 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 448 }
twisti@1137 449
twisti@1137 450 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 451 // ensure that it does not span a cache line so that it can be patched.
duke@0 452 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 453 {
duke@0 454 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 455 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 456 }
duke@0 457
duke@0 458 // EMIT_RM()
twisti@1668 459 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 460 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 461 cbuf.insts()->emit_int8(c);
duke@0 462 }
duke@0 463
duke@0 464 // EMIT_CC()
twisti@1668 465 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 466 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 467 cbuf.insts()->emit_int8(c);
duke@0 468 }
duke@0 469
duke@0 470 // EMIT_OPCODE()
twisti@1668 471 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 472 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 473 }
duke@0 474
duke@0 475 // EMIT_OPCODE() w/ relocation information
duke@0 476 void emit_opcode(CodeBuffer &cbuf,
duke@0 477 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 478 {
twisti@1668 479 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 480 emit_opcode(cbuf, code);
duke@0 481 }
duke@0 482
duke@0 483 // EMIT_D8()
twisti@1668 484 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 485 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 486 }
duke@0 487
duke@0 488 // EMIT_D16()
twisti@1668 489 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 490 cbuf.insts()->emit_int16(d16);
duke@0 491 }
duke@0 492
duke@0 493 // EMIT_D32()
twisti@1668 494 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 495 cbuf.insts()->emit_int32(d32);
duke@0 496 }
duke@0 497
duke@0 498 // EMIT_D64()
twisti@1668 499 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 500 cbuf.insts()->emit_int64(d64);
duke@0 501 }
duke@0 502
duke@0 503 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 504 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 505 int d32,
duke@0 506 relocInfo::relocType reloc,
duke@0 507 int format)
duke@0 508 {
duke@0 509 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 510 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 511 cbuf.insts()->emit_int32(d32);
duke@0 512 }
duke@0 513
duke@0 514 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 515 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 516 #ifdef ASSERT
duke@0 517 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 518 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
jrose@989 519 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 520 }
duke@0 521 #endif
twisti@1668 522 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 523 cbuf.insts()->emit_int32(d32);
duke@0 524 }
duke@0 525
duke@0 526 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 527 address next_ip = cbuf.insts_end() + 4;
duke@0 528 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 529 external_word_Relocation::spec(addr),
duke@0 530 RELOC_DISP32);
duke@0 531 }
duke@0 532
duke@0 533
duke@0 534 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 535 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 536 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 537 cbuf.insts()->emit_int64(d64);
duke@0 538 }
duke@0 539
duke@0 540 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 541 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 542 #ifdef ASSERT
duke@0 543 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 544 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
jrose@989 545 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
jrose@989 546 "cannot embed scavengable oops in code");
duke@0 547 }
duke@0 548 #endif
twisti@1668 549 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 550 cbuf.insts()->emit_int64(d64);
duke@0 551 }
duke@0 552
duke@0 553 // Access stack slot for load or store
duke@0 554 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 555 {
duke@0 556 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 557 if (-0x80 <= disp && disp < 0x80) {
duke@0 558 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 559 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 560 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 561 } else {
duke@0 562 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 563 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 564 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 565 }
duke@0 566 }
duke@0 567
duke@0 568 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 569 void encode_RegMem(CodeBuffer &cbuf,
duke@0 570 int reg,
duke@0 571 int base, int index, int scale, int disp, bool disp_is_oop)
duke@0 572 {
duke@0 573 assert(!disp_is_oop, "cannot have disp");
duke@0 574 int regenc = reg & 7;
duke@0 575 int baseenc = base & 7;
duke@0 576 int indexenc = index & 7;
duke@0 577
duke@0 578 // There is no index & no scale, use form without SIB byte
duke@0 579 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 580 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 581 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 582 emit_rm(cbuf, 0x0, regenc, baseenc); // *
duke@0 583 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 584 // If 8-bit displacement, mode 0x1
duke@0 585 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 586 emit_d8(cbuf, disp);
duke@0 587 } else {
duke@0 588 // If 32-bit displacement
duke@0 589 if (base == -1) { // Special flag for absolute address
duke@0 590 emit_rm(cbuf, 0x0, regenc, 0x5); // *
duke@0 591 if (disp_is_oop) {
duke@0 592 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 593 } else {
duke@0 594 emit_d32(cbuf, disp);
duke@0 595 }
duke@0 596 } else {
duke@0 597 // Normal base + offset
duke@0 598 emit_rm(cbuf, 0x2, regenc, baseenc); // *
duke@0 599 if (disp_is_oop) {
duke@0 600 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 601 } else {
duke@0 602 emit_d32(cbuf, disp);
duke@0 603 }
duke@0 604 }
duke@0 605 }
duke@0 606 } else {
duke@0 607 // Else, encode with the SIB byte
duke@0 608 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 609 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 610 // If no displacement
duke@0 611 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 612 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 613 } else {
duke@0 614 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 615 // If 8-bit displacement, mode 0x1
duke@0 616 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 617 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 618 emit_d8(cbuf, disp);
duke@0 619 } else {
duke@0 620 // If 32-bit displacement
duke@0 621 if (base == 0x04 ) {
duke@0 622 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 623 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 624 } else {
duke@0 625 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 626 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 627 }
duke@0 628 if (disp_is_oop) {
duke@0 629 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 630 } else {
duke@0 631 emit_d32(cbuf, disp);
duke@0 632 }
duke@0 633 }
duke@0 634 }
duke@0 635 }
duke@0 636 }
duke@0 637
never@2545 638 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 639 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 640 Label exit;
never@2545 641 __ jccb(Assembler::noParity, exit);
never@2545 642 __ pushf();
kvn@2953 643 //
kvn@2953 644 // comiss/ucomiss instructions set ZF,PF,CF flags and
kvn@2953 645 // zero OF,AF,SF for NaN values.
kvn@2953 646 // Fixup flags by zeroing ZF,PF so that compare of NaN
kvn@2953 647 // values returns 'less than' result (CF is set).
kvn@2953 648 // Leave the rest of flags unchanged.
kvn@2953 649 //
kvn@2953 650 // 7 6 5 4 3 2 1 0
kvn@2953 651 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
kvn@2953 652 // 0 0 1 0 1 0 1 1 (0x2B)
kvn@2953 653 //
never@2545 654 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 655 __ popf();
never@2545 656 __ bind(exit);
kvn@2953 657 }
kvn@2953 658
kvn@2953 659 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
kvn@2953 660 Label done;
kvn@2953 661 __ movl(dst, -1);
kvn@2953 662 __ jcc(Assembler::parity, done);
kvn@2953 663 __ jcc(Assembler::below, done);
kvn@2953 664 __ setb(Assembler::notEqual, dst);
kvn@2953 665 __ movzbl(dst, dst);
kvn@2953 666 __ bind(done);
never@2545 667 }
never@2545 668
duke@0 669
duke@0 670 //=============================================================================
twisti@1915 671 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 672
twisti@2875 673 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 674 return 0; // absolute addressing, no offset
twisti@2875 675 }
twisti@2875 676
twisti@1915 677 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 678 // Empty encoding
twisti@1915 679 }
twisti@1915 680
twisti@1915 681 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 682 return 0;
twisti@1915 683 }
twisti@1915 684
twisti@1915 685 #ifndef PRODUCT
twisti@1915 686 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 687 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 688 }
twisti@1915 689 #endif
twisti@1915 690
twisti@1915 691
twisti@1915 692 //=============================================================================
duke@0 693 #ifndef PRODUCT
kvn@3139 694 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
duke@0 695 Compile* C = ra_->C;
duke@0 696
duke@0 697 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 698 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
kvn@3139 699 // Remove wordSize for return addr which is already pushed.
kvn@3139 700 framesize -= wordSize;
kvn@3139 701
duke@0 702 if (C->need_stack_bang(framesize)) {
kvn@3139 703 framesize -= wordSize;
kvn@3139 704 st->print("# stack bang");
kvn@3139 705 st->print("\n\t");
kvn@3139 706 st->print("pushq rbp\t# Save rbp");
kvn@3139 707 if (framesize) {
kvn@3139 708 st->print("\n\t");
kvn@3139 709 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 710 }
kvn@3139 711 } else {
kvn@3139 712 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 713 st->print("\n\t");
kvn@3139 714 framesize -= wordSize;
kvn@3139 715 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
duke@0 716 }
duke@0 717
duke@0 718 if (VerifyStackAtCalls) {
kvn@3139 719 st->print("\n\t");
kvn@3139 720 framesize -= wordSize;
kvn@3139 721 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
kvn@3139 722 #ifdef ASSERT
kvn@3139 723 st->print("\n\t");
kvn@3139 724 st->print("# stack alignment check");
kvn@3139 725 #endif
duke@0 726 }
kvn@3139 727 st->cr();
duke@0 728 }
duke@0 729 #endif
duke@0 730
kvn@3139 731 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 732 Compile* C = ra_->C;
kvn@3139 733 MacroAssembler _masm(&cbuf);
duke@0 734
duke@0 735 int framesize = C->frame_slots() << LogBytesPerInt;
kvn@3139 736
kvn@3139 737 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
duke@0 738
twisti@1668 739 C->set_frame_complete(cbuf.insts_size());
duke@0 740
twisti@2875 741 if (C->has_mach_constant_base_node()) {
twisti@2875 742 // NOTE: We set the table base offset here because users might be
twisti@2875 743 // emitted before MachConstantBaseNode.
twisti@2875 744 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 745 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 746 }
duke@0 747 }
duke@0 748
duke@0 749 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 750 {
duke@0 751 return MachNode::size(ra_); // too many variables; just compute it
duke@0 752 // the hard way
duke@0 753 }
duke@0 754
duke@0 755 int MachPrologNode::reloc() const
duke@0 756 {
duke@0 757 return 0; // a large enough number
duke@0 758 }
duke@0 759
duke@0 760 //=============================================================================
duke@0 761 #ifndef PRODUCT
duke@0 762 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 763 {
duke@0 764 Compile* C = ra_->C;
duke@0 765 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 766 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 767 // Remove word for return adr already pushed
duke@0 768 // and RBP
duke@0 769 framesize -= 2*wordSize;
duke@0 770
duke@0 771 if (framesize) {
iveresov@2251 772 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 773 st->print("\t");
duke@0 774 }
duke@0 775
iveresov@2251 776 st->print_cr("popq rbp");
duke@0 777 if (do_polling() && C->is_method_compilation()) {
duke@0 778 st->print("\t");
iveresov@2251 779 if (Assembler::is_polling_page_far()) {
iveresov@2251 780 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 781 "testl rax, [rscratch1]\t"
iveresov@2251 782 "# Safepoint: poll for GC");
iveresov@2251 783 } else {
iveresov@2251 784 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 785 "# Safepoint: poll for GC");
iveresov@2251 786 }
duke@0 787 }
duke@0 788 }
duke@0 789 #endif
duke@0 790
duke@0 791 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 792 {
duke@0 793 Compile* C = ra_->C;
duke@0 794 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 795 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 796 // Remove word for return adr already pushed
duke@0 797 // and RBP
duke@0 798 framesize -= 2*wordSize;
duke@0 799
duke@0 800 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 801
duke@0 802 if (framesize) {
duke@0 803 emit_opcode(cbuf, Assembler::REX_W);
duke@0 804 if (framesize < 0x80) {
duke@0 805 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 806 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 807 emit_d8(cbuf, framesize);
duke@0 808 } else {
duke@0 809 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 810 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 811 emit_d32(cbuf, framesize);
duke@0 812 }
duke@0 813 }
duke@0 814
duke@0 815 // popq rbp
duke@0 816 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 817
duke@0 818 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 819 MacroAssembler _masm(&cbuf);
iveresov@2251 820 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 821 if (Assembler::is_polling_page_far()) {
iveresov@2251 822 __ lea(rscratch1, polling_page);
iveresov@2251 823 __ relocate(relocInfo::poll_return_type);
iveresov@2251 824 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 825 } else {
iveresov@2251 826 __ testl(rax, polling_page);
iveresov@2251 827 }
duke@0 828 }
duke@0 829 }
duke@0 830
duke@0 831 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 832 {
iveresov@2251 833 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 834 // the hard way
duke@0 835 }
duke@0 836
duke@0 837 int MachEpilogNode::reloc() const
duke@0 838 {
duke@0 839 return 2; // a large enough number
duke@0 840 }
duke@0 841
duke@0 842 const Pipeline* MachEpilogNode::pipeline() const
duke@0 843 {
duke@0 844 return MachNode::pipeline_class();
duke@0 845 }
duke@0 846
duke@0 847 int MachEpilogNode::safepoint_offset() const
duke@0 848 {
duke@0 849 return 0;
duke@0 850 }
duke@0 851
duke@0 852 //=============================================================================
duke@0 853
duke@0 854 enum RC {
duke@0 855 rc_bad,
duke@0 856 rc_int,
duke@0 857 rc_float,
duke@0 858 rc_stack
duke@0 859 };
duke@0 860
duke@0 861 static enum RC rc_class(OptoReg::Name reg)
duke@0 862 {
duke@0 863 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 864
duke@0 865 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 866
duke@0 867 VMReg r = OptoReg::as_VMReg(reg);
duke@0 868
duke@0 869 if (r->is_Register()) return rc_int;
duke@0 870
duke@0 871 assert(r->is_XMMRegister(), "must be");
duke@0 872 return rc_float;
duke@0 873 }
duke@0 874
kvn@3447 875 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
kvn@3447 876 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
kvn@3447 877 int src_hi, int dst_hi, uint ireg, outputStream* st);
kvn@3447 878
kvn@3447 879 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
kvn@3447 880 int stack_offset, int reg, uint ireg, outputStream* st);
kvn@3447 881
kvn@3447 882 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
kvn@3447 883 int dst_offset, uint ireg, outputStream* st) {
kvn@3447 884 if (cbuf) {
kvn@3447 885 MacroAssembler _masm(cbuf);
kvn@3447 886 switch (ireg) {
kvn@3447 887 case Op_VecS:
kvn@3447 888 __ movq(Address(rsp, -8), rax);
kvn@3447 889 __ movl(rax, Address(rsp, src_offset));
kvn@3447 890 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 891 __ movq(rax, Address(rsp, -8));
kvn@3447 892 break;
kvn@3447 893 case Op_VecD:
kvn@3447 894 __ pushq(Address(rsp, src_offset));
kvn@3447 895 __ popq (Address(rsp, dst_offset));
kvn@3447 896 break;
kvn@3447 897 case Op_VecX:
kvn@3447 898 __ pushq(Address(rsp, src_offset));
kvn@3447 899 __ popq (Address(rsp, dst_offset));
kvn@3447 900 __ pushq(Address(rsp, src_offset+8));
kvn@3447 901 __ popq (Address(rsp, dst_offset+8));
kvn@3447 902 break;
kvn@3447 903 case Op_VecY:
kvn@3447 904 __ vmovdqu(Address(rsp, -32), xmm0);
kvn@3447 905 __ vmovdqu(xmm0, Address(rsp, src_offset));
kvn@3447 906 __ vmovdqu(Address(rsp, dst_offset), xmm0);
kvn@3447 907 __ vmovdqu(xmm0, Address(rsp, -32));
kvn@3447 908 break;
kvn@3447 909 default:
kvn@3447 910 ShouldNotReachHere();
kvn@3447 911 }
kvn@3447 912 #ifndef PRODUCT
kvn@3447 913 } else {
kvn@3447 914 switch (ireg) {
kvn@3447 915 case Op_VecS:
kvn@3447 916 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 917 "movl rax, [rsp + #%d]\n\t"
kvn@3447 918 "movl [rsp + #%d], rax\n\t"
kvn@3447 919 "movq rax, [rsp - #8]",
kvn@3447 920 src_offset, dst_offset);
kvn@3447 921 break;
kvn@3447 922 case Op_VecD:
kvn@3447 923 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 924 "popq [rsp + #%d]",
kvn@3447 925 src_offset, dst_offset);
kvn@3447 926 break;
kvn@3447 927 case Op_VecX:
kvn@3447 928 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
kvn@3447 929 "popq [rsp + #%d]\n\t"
kvn@3447 930 "pushq [rsp + #%d]\n\t"
kvn@3447 931 "popq [rsp + #%d]",
kvn@3447 932 src_offset, dst_offset, src_offset+8, dst_offset+8);
kvn@3447 933 break;
kvn@3447 934 case Op_VecY:
kvn@3447 935 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
kvn@3447 936 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@3447 937 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@3447 938 "vmovdqu xmm0, [rsp - #32]",
kvn@3447 939 src_offset, dst_offset);
kvn@3447 940 break;
kvn@3447 941 default:
kvn@3447 942 ShouldNotReachHere();
kvn@3447 943 }
kvn@3447 944 #endif
kvn@3447 945 }
kvn@3447 946 }
kvn@3447 947
duke@0 948 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 949 PhaseRegAlloc* ra_,
duke@0 950 bool do_size,
kvn@3447 951 outputStream* st) const {
kvn@3447 952 assert(cbuf != NULL || st != NULL, "sanity");
duke@0 953 // Get registers to move
duke@0 954 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 955 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 956 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 957 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 958
duke@0 959 enum RC src_second_rc = rc_class(src_second);
duke@0 960 enum RC src_first_rc = rc_class(src_first);
duke@0 961 enum RC dst_second_rc = rc_class(dst_second);
duke@0 962 enum RC dst_first_rc = rc_class(dst_first);
duke@0 963
duke@0 964 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 965 "must move at least 1 register" );
duke@0 966
duke@0 967 if (src_first == dst_first && src_second == dst_second) {
duke@0 968 // Self copy, no move
duke@0 969 return 0;
kvn@3447 970 }
kvn@3447 971 if (bottom_type()->isa_vect() != NULL) {
kvn@3447 972 uint ireg = ideal_reg();
kvn@3447 973 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
kvn@3447 974 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
kvn@3447 975 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
kvn@3447 976 // mem -> mem
kvn@3447 977 int src_offset = ra_->reg2offset(src_first);
kvn@3447 978 int dst_offset = ra_->reg2offset(dst_first);
kvn@3447 979 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
kvn@3447 980 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
kvn@3447 981 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
kvn@3447 982 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
kvn@3447 983 int stack_offset = ra_->reg2offset(dst_first);
kvn@3447 984 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
kvn@3447 985 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
kvn@3447 986 int stack_offset = ra_->reg2offset(src_first);
kvn@3447 987 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
kvn@3447 988 } else {
kvn@3447 989 ShouldNotReachHere();
kvn@3447 990 }
kvn@3447 991 return 0;
kvn@3447 992 }
kvn@3447 993 if (src_first_rc == rc_stack) {
duke@0 994 // mem ->
duke@0 995 if (dst_first_rc == rc_stack) {
duke@0 996 // mem -> mem
duke@0 997 assert(src_second != dst_first, "overlap");
duke@0 998 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 999 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1000 // 64-bit
duke@0 1001 int src_offset = ra_->reg2offset(src_first);
duke@0 1002 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1003 if (cbuf) {
kvn@3447 1004 MacroAssembler _masm(cbuf);
kvn@3447 1005 __ pushq(Address(rsp, src_offset));
kvn@3447 1006 __ popq (Address(rsp, dst_offset));
duke@0 1007 #ifndef PRODUCT
kvn@3447 1008 } else {
duke@0 1009 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1010 "popq [rsp + #%d]",
kvn@3447 1011 src_offset, dst_offset);
duke@0 1012 #endif
duke@0 1013 }
duke@0 1014 } else {
duke@0 1015 // 32-bit
duke@0 1016 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1017 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1018 // No pushl/popl, so:
duke@0 1019 int src_offset = ra_->reg2offset(src_first);
duke@0 1020 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1021 if (cbuf) {
kvn@3447 1022 MacroAssembler _masm(cbuf);
kvn@3447 1023 __ movq(Address(rsp, -8), rax);
kvn@3447 1024 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1025 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1026 __ movq(rax, Address(rsp, -8));
duke@0 1027 #ifndef PRODUCT
kvn@3447 1028 } else {
duke@0 1029 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1030 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1031 "movl [rsp + #%d], rax\n\t"
kvn@3447 1032 "movq rax, [rsp - #8]",
kvn@3447 1033 src_offset, dst_offset);
duke@0 1034 #endif
duke@0 1035 }
duke@0 1036 }
kvn@3447 1037 return 0;
duke@0 1038 } else if (dst_first_rc == rc_int) {
duke@0 1039 // mem -> gpr
duke@0 1040 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1041 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1042 // 64-bit
duke@0 1043 int offset = ra_->reg2offset(src_first);
duke@0 1044 if (cbuf) {
kvn@3447 1045 MacroAssembler _masm(cbuf);
kvn@3447 1046 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1047 #ifndef PRODUCT
kvn@3447 1048 } else {
duke@0 1049 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1050 Matcher::regName[dst_first],
duke@0 1051 offset);
duke@0 1052 #endif
duke@0 1053 }
duke@0 1054 } else {
duke@0 1055 // 32-bit
duke@0 1056 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1057 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1058 int offset = ra_->reg2offset(src_first);
duke@0 1059 if (cbuf) {
kvn@3447 1060 MacroAssembler _masm(cbuf);
kvn@3447 1061 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1062 #ifndef PRODUCT
kvn@3447 1063 } else {
duke@0 1064 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1065 Matcher::regName[dst_first],
duke@0 1066 offset);
duke@0 1067 #endif
duke@0 1068 }
duke@0 1069 }
kvn@3447 1070 return 0;
duke@0 1071 } else if (dst_first_rc == rc_float) {
duke@0 1072 // mem-> xmm
duke@0 1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1075 // 64-bit
duke@0 1076 int offset = ra_->reg2offset(src_first);
duke@0 1077 if (cbuf) {
kvn@2953 1078 MacroAssembler _masm(cbuf);
kvn@2953 1079 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1080 #ifndef PRODUCT
kvn@3447 1081 } else {
duke@0 1082 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1083 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1084 Matcher::regName[dst_first],
duke@0 1085 offset);
duke@0 1086 #endif
duke@0 1087 }
duke@0 1088 } else {
duke@0 1089 // 32-bit
duke@0 1090 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1091 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1092 int offset = ra_->reg2offset(src_first);
duke@0 1093 if (cbuf) {
kvn@2953 1094 MacroAssembler _masm(cbuf);
kvn@2953 1095 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1096 #ifndef PRODUCT
kvn@3447 1097 } else {
duke@0 1098 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1099 Matcher::regName[dst_first],
duke@0 1100 offset);
duke@0 1101 #endif
duke@0 1102 }
duke@0 1103 }
kvn@3447 1104 return 0;
duke@0 1105 }
duke@0 1106 } else if (src_first_rc == rc_int) {
duke@0 1107 // gpr ->
duke@0 1108 if (dst_first_rc == rc_stack) {
duke@0 1109 // gpr -> mem
duke@0 1110 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1111 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1112 // 64-bit
duke@0 1113 int offset = ra_->reg2offset(dst_first);
duke@0 1114 if (cbuf) {
kvn@3447 1115 MacroAssembler _masm(cbuf);
kvn@3447 1116 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1117 #ifndef PRODUCT
kvn@3447 1118 } else {
duke@0 1119 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1120 offset,
duke@0 1121 Matcher::regName[src_first]);
duke@0 1122 #endif
duke@0 1123 }
duke@0 1124 } else {
duke@0 1125 // 32-bit
duke@0 1126 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1127 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1128 int offset = ra_->reg2offset(dst_first);
duke@0 1129 if (cbuf) {
kvn@3447 1130 MacroAssembler _masm(cbuf);
kvn@3447 1131 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1132 #ifndef PRODUCT
kvn@3447 1133 } else {
duke@0 1134 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1135 offset,
duke@0 1136 Matcher::regName[src_first]);
duke@0 1137 #endif
duke@0 1138 }
duke@0 1139 }
kvn@3447 1140 return 0;
duke@0 1141 } else if (dst_first_rc == rc_int) {
duke@0 1142 // gpr -> gpr
duke@0 1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1145 // 64-bit
duke@0 1146 if (cbuf) {
kvn@3447 1147 MacroAssembler _masm(cbuf);
kvn@3447 1148 __ movq(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1149 as_Register(Matcher::_regEncode[src_first]));
duke@0 1150 #ifndef PRODUCT
kvn@3447 1151 } else {
duke@0 1152 st->print("movq %s, %s\t# spill",
duke@0 1153 Matcher::regName[dst_first],
duke@0 1154 Matcher::regName[src_first]);
duke@0 1155 #endif
duke@0 1156 }
kvn@3447 1157 return 0;
duke@0 1158 } else {
duke@0 1159 // 32-bit
duke@0 1160 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1161 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1162 if (cbuf) {
kvn@3447 1163 MacroAssembler _masm(cbuf);
kvn@3447 1164 __ movl(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1165 as_Register(Matcher::_regEncode[src_first]));
duke@0 1166 #ifndef PRODUCT
kvn@3447 1167 } else {
duke@0 1168 st->print("movl %s, %s\t# spill",
duke@0 1169 Matcher::regName[dst_first],
duke@0 1170 Matcher::regName[src_first]);
duke@0 1171 #endif
duke@0 1172 }
kvn@3447 1173 return 0;
duke@0 1174 }
duke@0 1175 } else if (dst_first_rc == rc_float) {
duke@0 1176 // gpr -> xmm
duke@0 1177 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1178 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1179 // 64-bit
duke@0 1180 if (cbuf) {
kvn@2953 1181 MacroAssembler _masm(cbuf);
kvn@2953 1182 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1183 #ifndef PRODUCT
kvn@3447 1184 } else {
duke@0 1185 st->print("movdq %s, %s\t# spill",
duke@0 1186 Matcher::regName[dst_first],
duke@0 1187 Matcher::regName[src_first]);
duke@0 1188 #endif
duke@0 1189 }
duke@0 1190 } else {
duke@0 1191 // 32-bit
duke@0 1192 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1193 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1194 if (cbuf) {
kvn@2953 1195 MacroAssembler _masm(cbuf);
kvn@2953 1196 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1197 #ifndef PRODUCT
kvn@3447 1198 } else {
duke@0 1199 st->print("movdl %s, %s\t# spill",
duke@0 1200 Matcher::regName[dst_first],
duke@0 1201 Matcher::regName[src_first]);
duke@0 1202 #endif
duke@0 1203 }
duke@0 1204 }
kvn@3447 1205 return 0;
duke@0 1206 }
duke@0 1207 } else if (src_first_rc == rc_float) {
duke@0 1208 // xmm ->
duke@0 1209 if (dst_first_rc == rc_stack) {
duke@0 1210 // xmm -> mem
duke@0 1211 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1212 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1213 // 64-bit
duke@0 1214 int offset = ra_->reg2offset(dst_first);
duke@0 1215 if (cbuf) {
kvn@2953 1216 MacroAssembler _masm(cbuf);
kvn@2953 1217 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1218 #ifndef PRODUCT
kvn@3447 1219 } else {
duke@0 1220 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1221 offset,
duke@0 1222 Matcher::regName[src_first]);
duke@0 1223 #endif
duke@0 1224 }
duke@0 1225 } else {
duke@0 1226 // 32-bit
duke@0 1227 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1228 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1229 int offset = ra_->reg2offset(dst_first);
duke@0 1230 if (cbuf) {
kvn@2953 1231 MacroAssembler _masm(cbuf);
kvn@2953 1232 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1233 #ifndef PRODUCT
kvn@3447 1234 } else {
duke@0 1235 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1236 offset,
duke@0 1237 Matcher::regName[src_first]);
duke@0 1238 #endif
duke@0 1239 }
duke@0 1240 }
kvn@3447 1241 return 0;
duke@0 1242 } else if (dst_first_rc == rc_int) {
duke@0 1243 // xmm -> gpr
duke@0 1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1246 // 64-bit
duke@0 1247 if (cbuf) {
kvn@2953 1248 MacroAssembler _masm(cbuf);
kvn@2953 1249 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1250 #ifndef PRODUCT
kvn@3447 1251 } else {
duke@0 1252 st->print("movdq %s, %s\t# spill",
duke@0 1253 Matcher::regName[dst_first],
duke@0 1254 Matcher::regName[src_first]);
duke@0 1255 #endif
duke@0 1256 }
duke@0 1257 } else {
duke@0 1258 // 32-bit
duke@0 1259 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1260 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1261 if (cbuf) {
kvn@2953 1262 MacroAssembler _masm(cbuf);
kvn@2953 1263 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1264 #ifndef PRODUCT
kvn@3447 1265 } else {
duke@0 1266 st->print("movdl %s, %s\t# spill",
duke@0 1267 Matcher::regName[dst_first],
duke@0 1268 Matcher::regName[src_first]);
duke@0 1269 #endif
duke@0 1270 }
duke@0 1271 }
kvn@3447 1272 return 0;
duke@0 1273 } else if (dst_first_rc == rc_float) {
duke@0 1274 // xmm -> xmm
duke@0 1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1277 // 64-bit
duke@0 1278 if (cbuf) {
kvn@2953 1279 MacroAssembler _masm(cbuf);
kvn@2953 1280 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1281 #ifndef PRODUCT
kvn@3447 1282 } else {
duke@0 1283 st->print("%s %s, %s\t# spill",
duke@0 1284 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1285 Matcher::regName[dst_first],
duke@0 1286 Matcher::regName[src_first]);
duke@0 1287 #endif
duke@0 1288 }
duke@0 1289 } else {
duke@0 1290 // 32-bit
duke@0 1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1293 if (cbuf) {
kvn@2953 1294 MacroAssembler _masm(cbuf);
kvn@2953 1295 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1296 #ifndef PRODUCT
kvn@3447 1297 } else {
duke@0 1298 st->print("%s %s, %s\t# spill",
duke@0 1299 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1300 Matcher::regName[dst_first],
duke@0 1301 Matcher::regName[src_first]);
duke@0 1302 #endif
duke@0 1303 }
duke@0 1304 }
kvn@3447 1305 return 0;
duke@0 1306 }
duke@0 1307 }
duke@0 1308
duke@0 1309 assert(0," foo ");
duke@0 1310 Unimplemented();
duke@0 1311 return 0;
duke@0 1312 }
duke@0 1313
duke@0 1314 #ifndef PRODUCT
kvn@3447 1315 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
duke@0 1316 implementation(NULL, ra_, false, st);
duke@0 1317 }
duke@0 1318 #endif
duke@0 1319
kvn@3447 1320 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1321 implementation(&cbuf, ra_, false, NULL);
duke@0 1322 }
duke@0 1323
kvn@3447 1324 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
kvn@3447 1325 return MachNode::size(ra_);
duke@0 1326 }
duke@0 1327
duke@0 1328 //=============================================================================
duke@0 1329 #ifndef PRODUCT
duke@0 1330 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1331 {
duke@0 1332 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1333 int reg = ra_->get_reg_first(this);
duke@0 1334 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1335 Matcher::regName[reg], offset);
duke@0 1336 }
duke@0 1337 #endif
duke@0 1338
duke@0 1339 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1340 {
duke@0 1341 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1342 int reg = ra_->get_encode(this);
duke@0 1343 if (offset >= 0x80) {
duke@0 1344 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1345 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1346 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1347 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1348 emit_d32(cbuf, offset);
duke@0 1349 } else {
duke@0 1350 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1351 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1352 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1353 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1354 emit_d8(cbuf, offset);
duke@0 1355 }
duke@0 1356 }
duke@0 1357
duke@0 1358 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1359 {
duke@0 1360 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1361 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1362 }
duke@0 1363
duke@0 1364 //=============================================================================
duke@0 1365
duke@0 1366 // emit call stub, compiled java to interpreter
duke@0 1367 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1368 {
duke@0 1369 // Stub is fixed up when the corresponding call is converted from
duke@0 1370 // calling compiled code to calling interpreted code.
duke@0 1371 // movq rbx, 0
duke@0 1372 // jmp -5 # to self
duke@0 1373
twisti@1668 1374 address mark = cbuf.insts_mark(); // get mark within main instrs section
twisti@1668 1375
twisti@1668 1376 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1377 // That's why we must use the macroassembler to generate a stub.
duke@0 1378 MacroAssembler _masm(&cbuf);
duke@0 1379
duke@0 1380 address base =
duke@0 1381 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1382 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1383 // static stub relocation stores the instruction address of the call
duke@0 1384 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
duke@0 1385 // static stub relocation also tags the methodOop in the code-stream.
duke@0 1386 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
never@304 1387 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1388 __ jump(RuntimeAddress(__ pc()));
duke@0 1389
twisti@1668 1390 // Update current stubs pointer and restore insts_end.
duke@0 1391 __ end_a_stub();
duke@0 1392 }
duke@0 1393
duke@0 1394 // size of call stub, compiled java to interpretor
duke@0 1395 uint size_java_to_interp()
duke@0 1396 {
duke@0 1397 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1398 }
duke@0 1399
duke@0 1400 // relocation entries for call stub, compiled java to interpretor
duke@0 1401 uint reloc_java_to_interp()
duke@0 1402 {
duke@0 1403 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1404 }
duke@0 1405
duke@0 1406 //=============================================================================
duke@0 1407 #ifndef PRODUCT
duke@0 1408 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1409 {
coleenp@113 1410 if (UseCompressedOops) {
kvn@1491 1411 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
kvn@642 1412 if (Universe::narrow_oop_shift() != 0) {
kvn@1491 1413 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
kvn@1491 1414 }
kvn@1491 1415 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1416 } else {
kvn@1491 1417 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1418 "# Inline cache check");
coleenp@113 1419 }
duke@0 1420 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1421 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1422 }
duke@0 1423 #endif
duke@0 1424
duke@0 1425 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1426 {
duke@0 1427 MacroAssembler masm(&cbuf);
twisti@1668 1428 uint insts_size = cbuf.insts_size();
coleenp@113 1429 if (UseCompressedOops) {
coleenp@113 1430 masm.load_klass(rscratch1, j_rarg0);
never@304 1431 masm.cmpptr(rax, rscratch1);
coleenp@113 1432 } else {
never@304 1433 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1434 }
duke@0 1435
duke@0 1436 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1437
duke@0 1438 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1439 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1440 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1441 if (OptoBreakpoint) {
duke@0 1442 // Leave space for int3
kvn@1491 1443 nops_cnt -= 1;
duke@0 1444 }
kvn@1491 1445 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1446 if (nops_cnt > 0)
kvn@1491 1447 masm.nop(nops_cnt);
duke@0 1448 }
duke@0 1449
duke@0 1450 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1451 {
kvn@1491 1452 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1453 // the hard way
duke@0 1454 }
duke@0 1455
duke@0 1456
duke@0 1457 //=============================================================================
duke@0 1458 uint size_exception_handler()
duke@0 1459 {
duke@0 1460 // NativeCall instruction size is the same as NativeJump.
duke@0 1461 // Note that this value is also credited (in output.cpp) to
duke@0 1462 // the size of the code section.
duke@0 1463 return NativeJump::instruction_size;
duke@0 1464 }
duke@0 1465
duke@0 1466 // Emit exception handler code.
duke@0 1467 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1468 {
duke@0 1469
twisti@1668 1470 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1471 // That's why we must use the macroassembler to generate a handler.
duke@0 1472 MacroAssembler _masm(&cbuf);
duke@0 1473 address base =
duke@0 1474 __ start_a_stub(size_exception_handler());
duke@0 1475 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1476 int offset = __ offset();
twisti@1668 1477 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
duke@0 1478 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1479 __ end_a_stub();
duke@0 1480 return offset;
duke@0 1481 }
duke@0 1482
duke@0 1483 uint size_deopt_handler()
duke@0 1484 {
duke@0 1485 // three 5 byte instructions
duke@0 1486 return 15;
duke@0 1487 }
duke@0 1488
duke@0 1489 // Emit deopt handler code.
duke@0 1490 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1491 {
duke@0 1492
twisti@1668 1493 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1494 // That's why we must use the macroassembler to generate a handler.
duke@0 1495 MacroAssembler _masm(&cbuf);
duke@0 1496 address base =
duke@0 1497 __ start_a_stub(size_deopt_handler());
duke@0 1498 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1499 int offset = __ offset();
duke@0 1500 address the_pc = (address) __ pc();
duke@0 1501 Label next;
duke@0 1502 // push a "the_pc" on the stack without destroying any registers
duke@0 1503 // as they all may be live.
duke@0 1504
duke@0 1505 // push address of "next"
duke@0 1506 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1507 __ bind(next);
duke@0 1508 // adjust it so it matches "the_pc"
never@304 1509 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1510 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1511 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1512 __ end_a_stub();
duke@0 1513 return offset;
duke@0 1514 }
duke@0 1515
duke@0 1516
twisti@775 1517 const bool Matcher::match_rule_supported(int opcode) {
twisti@775 1518 if (!has_match_rule(opcode))
twisti@775 1519 return false;
twisti@775 1520
never@3202 1521 switch (opcode) {
never@3202 1522 case Op_PopCountI:
never@3202 1523 case Op_PopCountL:
never@3202 1524 if (!UsePopCountInstruction)
never@3202 1525 return false;
never@3202 1526 break;
never@3202 1527 }
never@3202 1528
twisti@775 1529 return true; // Per default match rules are supported.
twisti@775 1530 }
twisti@775 1531
duke@0 1532 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1533 {
duke@0 1534 return regnum - 32; // The FP registers are in the second chunk
duke@0 1535 }
duke@0 1536
duke@0 1537 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1538 const bool Matcher::convL2FSupported(void) {
duke@0 1539 return true;
duke@0 1540 }
duke@0 1541
duke@0 1542 // Is this branch offset short enough that a short branch can be used?
duke@0 1543 //
duke@0 1544 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1545 // this method should return false for offset 0.
kvn@2614 1546 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1547 // The passed offset is relative to address of the branch.
kvn@2614 1548 // On 86 a branch displacement is calculated relative to address
kvn@2614 1549 // of a next instruction.
kvn@2614 1550 offset -= br_size;
kvn@2614 1551
never@415 1552 // the short version of jmpConUCF2 contains multiple branches,
never@415 1553 // making the reach slightly less
never@415 1554 if (rule == jmpConUCF2_rule)
never@415 1555 return (-126 <= offset && offset <= 125);
never@415 1556 return (-128 <= offset && offset <= 127);
duke@0 1557 }
duke@0 1558
duke@0 1559 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1560 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1561 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1562
duke@0 1563 // Probably always true, even if a temp register is required.
duke@0 1564 return true;
duke@0 1565 }
duke@0 1566
duke@0 1567 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1568 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1569
duke@0 1570 // Threshold size for cleararray.
duke@0 1571 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1572
kvn@2808 1573 // No additional cost for CMOVL.
kvn@2808 1574 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 1575
kvn@2808 1576 // No CMOVF/CMOVD with SSE2
kvn@2808 1577 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 1578
duke@0 1579 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1580 // to be subsumed into complex addressing expressions or compute them
duke@0 1581 // into registers? True for Intel but false for most RISCs
duke@0 1582 const bool Matcher::clone_shift_expressions = true;
duke@0 1583
roland@2248 1584 // Do we need to mask the count passed to shift instructions or does
roland@2248 1585 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 1586 const bool Matcher::need_masked_shift_count = false;
roland@2248 1587
kvn@1495 1588 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 1589 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 1590 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 1591 }
kvn@1495 1592
duke@0 1593 // Is it better to copy float constants, or load them directly from
duke@0 1594 // memory? Intel can load a float constant from a direct address,
duke@0 1595 // requiring no extra registers. Most RISCs will have to materialize
duke@0 1596 // an address into a register first, so they would do better to copy
duke@0 1597 // the constant from stack.
duke@0 1598 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 1599
duke@0 1600 // If CPU can load and store mis-aligned doubles directly then no
duke@0 1601 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 1602 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 1603 // C code as the Java calling convention forces doubles to be aligned.
duke@0 1604 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1605
duke@0 1606 // No-op on amd64
duke@0 1607 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 1608
duke@0 1609 // Advertise here if the CPU requires explicit rounding operations to
duke@0 1610 // implement the UseStrictFP mode.
duke@0 1611 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 1612
kvn@1274 1613 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 1614 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 1615 bool Matcher::float_in_double() { return false; }
kvn@1274 1616
duke@0 1617 // Do ints take an entire long register or just half?
duke@0 1618 const bool Matcher::int_in_long = true;
duke@0 1619
duke@0 1620 // Return whether or not this register is ever used as an argument.
duke@0 1621 // This function is used on startup to build the trampoline stubs in
duke@0 1622 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 1623 // call in the trampoline, and arguments in those registers not be
duke@0 1624 // available to the callee.
duke@0 1625 bool Matcher::can_be_java_arg(int reg)
duke@0 1626 {
duke@0 1627 return
kvn@3447 1628 reg == RDI_num || reg == RDI_H_num ||
kvn@3447 1629 reg == RSI_num || reg == RSI_H_num ||
kvn@3447 1630 reg == RDX_num || reg == RDX_H_num ||
kvn@3447 1631 reg == RCX_num || reg == RCX_H_num ||
kvn@3447 1632 reg == R8_num || reg == R8_H_num ||
kvn@3447 1633 reg == R9_num || reg == R9_H_num ||
kvn@3447 1634 reg == R12_num || reg == R12_H_num ||
kvn@3447 1635 reg == XMM0_num || reg == XMM0b_num ||
kvn@3447 1636 reg == XMM1_num || reg == XMM1b_num ||
kvn@3447 1637 reg == XMM2_num || reg == XMM2b_num ||
kvn@3447 1638 reg == XMM3_num || reg == XMM3b_num ||
kvn@3447 1639 reg == XMM4_num || reg == XMM4b_num ||
kvn@3447 1640 reg == XMM5_num || reg == XMM5b_num ||
kvn@3447 1641 reg == XMM6_num || reg == XMM6b_num ||
kvn@3447 1642 reg == XMM7_num || reg == XMM7b_num;
duke@0 1643 }
duke@0 1644
duke@0 1645 bool Matcher::is_spillable_arg(int reg)
duke@0 1646 {
duke@0 1647 return can_be_java_arg(reg);
duke@0 1648 }
duke@0 1649
kvn@1834 1650 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 1651 // In 64 bit mode a code which use multiply when
kvn@1834 1652 // devisor is constant is faster than hardware
kvn@1834 1653 // DIV instruction (it uses MulHiL).
kvn@1834 1654 return false;
kvn@1834 1655 }
kvn@1834 1656
duke@0 1657 // Register for DIVI projection of divmodI
duke@0 1658 RegMask Matcher::divI_proj_mask() {
roland@2882 1659 return INT_RAX_REG_mask();
duke@0 1660 }
duke@0 1661
duke@0 1662 // Register for MODI projection of divmodI
duke@0 1663 RegMask Matcher::modI_proj_mask() {
roland@2882 1664 return INT_RDX_REG_mask();
duke@0 1665 }
duke@0 1666
duke@0 1667 // Register for DIVL projection of divmodL
duke@0 1668 RegMask Matcher::divL_proj_mask() {
roland@2882 1669 return LONG_RAX_REG_mask();
duke@0 1670 }
duke@0 1671
duke@0 1672 // Register for MODL projection of divmodL
duke@0 1673 RegMask Matcher::modL_proj_mask() {
roland@2882 1674 return LONG_RDX_REG_mask();
duke@0 1675 }
duke@0 1676
twisti@1137 1677 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
roland@2882 1678 return PTR_RBP_REG_mask();
twisti@1137 1679 }
twisti@1137 1680
coleenp@113 1681 static Address build_address(int b, int i, int s, int d) {
coleenp@113 1682 Register index = as_Register(i);
coleenp@113 1683 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 1684 if (index == rsp) {
coleenp@113 1685 index = noreg;
coleenp@113 1686 scale = Address::no_scale;
coleenp@113 1687 }
coleenp@113 1688 Address addr(as_Register(b), index, scale, d);
coleenp@113 1689 return addr;
coleenp@113 1690 }
coleenp@113 1691
duke@0 1692 %}
duke@0 1693
duke@0 1694 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1695 // This block specifies the encoding classes used by the compiler to
duke@0 1696 // output byte streams. Encoding classes are parameterized macros
duke@0 1697 // used by Machine Instruction Nodes in order to generate the bit
duke@0 1698 // encoding of the instruction. Operands specify their base encoding
duke@0 1699 // interface with the interface keyword. There are currently
duke@0 1700 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 1701 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 1702 // which returns its register number when queried. CONST_INTER causes
duke@0 1703 // an operand to generate a function which returns the value of the
duke@0 1704 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 1705 // four functions which return the Base Register, the Index Register,
duke@0 1706 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 1707 // COND_INTER causes an operand to generate six functions which return
duke@0 1708 // the encoding code (ie - encoding bits for the instruction)
duke@0 1709 // associated with each basic boolean condition for a conditional
duke@0 1710 // instruction.
duke@0 1711 //
duke@0 1712 // Instructions specify two basic values for encoding. Again, a
duke@0 1713 // function is available to check if the constant displacement is an
duke@0 1714 // oop. They use the ins_encode keyword to specify their encoding
duke@0 1715 // classes (which must be a sequence of enc_class names, and their
duke@0 1716 // parameters, specified in the encoding block), and they use the
duke@0 1717 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1718 // tertiary opcode. Only the opcode sections which a particular
duke@0 1719 // instruction needs for encoding need to be specified.
duke@0 1720 encode %{
duke@0 1721 // Build emit functions for each basic byte or larger field in the
duke@0 1722 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 1723 // from C++ code in the enc_class source block. Emit functions will
duke@0 1724 // live in the main source block for now. In future, we can
duke@0 1725 // generalize this by adding a syntax that specifies the sizes of
duke@0 1726 // fields in an order, so that the adlc can build the emit functions
duke@0 1727 // automagically
duke@0 1728
duke@0 1729 // Emit primary opcode
duke@0 1730 enc_class OpcP
duke@0 1731 %{
duke@0 1732 emit_opcode(cbuf, $primary);
duke@0 1733 %}
duke@0 1734
duke@0 1735 // Emit secondary opcode
duke@0 1736 enc_class OpcS
duke@0 1737 %{
duke@0 1738 emit_opcode(cbuf, $secondary);
duke@0 1739 %}
duke@0 1740
duke@0 1741 // Emit tertiary opcode
duke@0 1742 enc_class OpcT
duke@0 1743 %{
duke@0 1744 emit_opcode(cbuf, $tertiary);
duke@0 1745 %}
duke@0 1746
duke@0 1747 // Emit opcode directly
duke@0 1748 enc_class Opcode(immI d8)
duke@0 1749 %{
duke@0 1750 emit_opcode(cbuf, $d8$$constant);
duke@0 1751 %}
duke@0 1752
duke@0 1753 // Emit size prefix
duke@0 1754 enc_class SizePrefix
duke@0 1755 %{
duke@0 1756 emit_opcode(cbuf, 0x66);
duke@0 1757 %}
duke@0 1758
duke@0 1759 enc_class reg(rRegI reg)
duke@0 1760 %{
duke@0 1761 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 1762 %}
duke@0 1763
duke@0 1764 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 1765 %{
duke@0 1766 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1767 %}
duke@0 1768
duke@0 1769 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 1770 %{
duke@0 1771 emit_opcode(cbuf, $opcode$$constant);
duke@0 1772 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1773 %}
duke@0 1774
duke@0 1775 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 1776 %{
duke@0 1777 // Full implementation of Java idiv and irem; checks for
duke@0 1778 // special case as described in JVM spec., p.243 & p.271.
duke@0 1779 //
duke@0 1780 // normal case special case
duke@0 1781 //
duke@0 1782 // input : rax: dividend min_int
duke@0 1783 // reg: divisor -1
duke@0 1784 //
duke@0 1785 // output: rax: quotient (= rax idiv reg) min_int
duke@0 1786 // rdx: remainder (= rax irem reg) 0
duke@0 1787 //
duke@0 1788 // Code sequnce:
duke@0 1789 //
duke@0 1790 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 1791 // 5: 75 07/08 jne e <normal>
duke@0 1792 // 7: 33 d2 xor %edx,%edx
duke@0 1793 // [div >= 8 -> offset + 1]
duke@0 1794 // [REX_B]
duke@0 1795 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1796 // c: 74 03/04 je 11 <done>
duke@0 1797 // 000000000000000e <normal>:
duke@0 1798 // e: 99 cltd
duke@0 1799 // [div >= 8 -> offset + 1]
duke@0 1800 // [REX_B]
duke@0 1801 // f: f7 f9 idiv $div
duke@0 1802 // 0000000000000011 <done>:
duke@0 1803
duke@0 1804 // cmp $0x80000000,%eax
duke@0 1805 emit_opcode(cbuf, 0x3d);
duke@0 1806 emit_d8(cbuf, 0x00);
duke@0 1807 emit_d8(cbuf, 0x00);
duke@0 1808 emit_d8(cbuf, 0x00);
duke@0 1809 emit_d8(cbuf, 0x80);
duke@0 1810
duke@0 1811 // jne e <normal>
duke@0 1812 emit_opcode(cbuf, 0x75);
duke@0 1813 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 1814
duke@0 1815 // xor %edx,%edx
duke@0 1816 emit_opcode(cbuf, 0x33);
duke@0 1817 emit_d8(cbuf, 0xD2);
duke@0 1818
duke@0 1819 // cmp $0xffffffffffffffff,%ecx
duke@0 1820 if ($div$$reg >= 8) {
duke@0 1821 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1822 }
duke@0 1823 emit_opcode(cbuf, 0x83);
duke@0 1824 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1825 emit_d8(cbuf, 0xFF);
duke@0 1826
duke@0 1827 // je 11 <done>
duke@0 1828 emit_opcode(cbuf, 0x74);
duke@0 1829 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 1830
duke@0 1831 // <normal>
duke@0 1832 // cltd
duke@0 1833 emit_opcode(cbuf, 0x99);
duke@0 1834
duke@0 1835 // idivl (note: must be emitted by the user of this rule)
duke@0 1836 // <done>
duke@0 1837 %}
duke@0 1838
duke@0 1839 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 1840 %{
duke@0 1841 // Full implementation of Java ldiv and lrem; checks for
duke@0 1842 // special case as described in JVM spec., p.243 & p.271.
duke@0 1843 //
duke@0 1844 // normal case special case
duke@0 1845 //
duke@0 1846 // input : rax: dividend min_long
duke@0 1847 // reg: divisor -1
duke@0 1848 //
duke@0 1849 // output: rax: quotient (= rax idiv reg) min_long
duke@0 1850 // rdx: remainder (= rax irem reg) 0
duke@0 1851 //
duke@0 1852 // Code sequnce:
duke@0 1853 //
duke@0 1854 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 1855 // 7: 00 00 80
duke@0 1856 // a: 48 39 d0 cmp %rdx,%rax
duke@0 1857 // d: 75 08 jne 17 <normal>
duke@0 1858 // f: 33 d2 xor %edx,%edx
duke@0 1859 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1860 // 15: 74 05 je 1c <done>
duke@0 1861 // 0000000000000017 <normal>:
duke@0 1862 // 17: 48 99 cqto
duke@0 1863 // 19: 48 f7 f9 idiv $div
duke@0 1864 // 000000000000001c <done>:
duke@0 1865
duke@0 1866 // mov $0x8000000000000000,%rdx
duke@0 1867 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1868 emit_opcode(cbuf, 0xBA);
duke@0 1869 emit_d8(cbuf, 0x00);
duke@0 1870 emit_d8(cbuf, 0x00);
duke@0 1871 emit_d8(cbuf, 0x00);
duke@0 1872 emit_d8(cbuf, 0x00);
duke@0 1873 emit_d8(cbuf, 0x00);
duke@0 1874 emit_d8(cbuf, 0x00);
duke@0 1875 emit_d8(cbuf, 0x00);
duke@0 1876 emit_d8(cbuf, 0x80);
duke@0 1877
duke@0 1878 // cmp %rdx,%rax
duke@0 1879 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1880 emit_opcode(cbuf, 0x39);
duke@0 1881 emit_d8(cbuf, 0xD0);
duke@0 1882
duke@0 1883 // jne 17 <normal>
duke@0 1884 emit_opcode(cbuf, 0x75);
duke@0 1885 emit_d8(cbuf, 0x08);
duke@0 1886
duke@0 1887 // xor %edx,%edx
duke@0 1888 emit_opcode(cbuf, 0x33);
duke@0 1889 emit_d8(cbuf, 0xD2);
duke@0 1890
duke@0 1891 // cmp $0xffffffffffffffff,$div
duke@0 1892 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 1893 emit_opcode(cbuf, 0x83);
duke@0 1894 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1895 emit_d8(cbuf, 0xFF);
duke@0 1896
duke@0 1897 // je 1e <done>
duke@0 1898 emit_opcode(cbuf, 0x74);
duke@0 1899 emit_d8(cbuf, 0x05);
duke@0 1900
duke@0 1901 // <normal>
duke@0 1902 // cqto
duke@0 1903 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1904 emit_opcode(cbuf, 0x99);
duke@0 1905
duke@0 1906 // idivq (note: must be emitted by the user of this rule)
duke@0 1907 // <done>
duke@0 1908 %}
duke@0 1909
duke@0 1910 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 1911 enc_class OpcSE(immI imm)
duke@0 1912 %{
duke@0 1913 // Emit primary opcode and set sign-extend bit
duke@0 1914 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1915 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1916 emit_opcode(cbuf, $primary | 0x02);
duke@0 1917 } else {
duke@0 1918 // 32-bit immediate
duke@0 1919 emit_opcode(cbuf, $primary);
duke@0 1920 }
duke@0 1921 %}
duke@0 1922
duke@0 1923 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 1924 %{
duke@0 1925 // OpcSEr/m
duke@0 1926 int dstenc = $dst$$reg;
duke@0 1927 if (dstenc >= 8) {
duke@0 1928 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1929 dstenc -= 8;
duke@0 1930 }
duke@0 1931 // Emit primary opcode and set sign-extend bit
duke@0 1932 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1933 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1934 emit_opcode(cbuf, $primary | 0x02);
duke@0 1935 } else {
duke@0 1936 // 32-bit immediate
duke@0 1937 emit_opcode(cbuf, $primary);
duke@0 1938 }
duke@0 1939 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1940 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1941 %}
duke@0 1942
duke@0 1943 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 1944 %{
duke@0 1945 // OpcSEr/m
duke@0 1946 int dstenc = $dst$$reg;
duke@0 1947 if (dstenc < 8) {
duke@0 1948 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1949 } else {
duke@0 1950 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 1951 dstenc -= 8;
duke@0 1952 }
duke@0 1953 // Emit primary opcode and set sign-extend bit
duke@0 1954 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1955 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1956 emit_opcode(cbuf, $primary | 0x02);
duke@0 1957 } else {
duke@0 1958 // 32-bit immediate
duke@0 1959 emit_opcode(cbuf, $primary);
duke@0 1960 }
duke@0 1961 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1962 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1963 %}
duke@0 1964
duke@0 1965 enc_class Con8or32(immI imm)
duke@0 1966 %{
duke@0 1967 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1968 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1969 $$$emit8$imm$$constant;
duke@0 1970 } else {
duke@0 1971 // 32-bit immediate
duke@0 1972 $$$emit32$imm$$constant;
duke@0 1973 }
duke@0 1974 %}
duke@0 1975
duke@0 1976 enc_class opc2_reg(rRegI dst)
duke@0 1977 %{
duke@0 1978 // BSWAP
duke@0 1979 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 1980 %}
duke@0 1981
duke@0 1982 enc_class opc3_reg(rRegI dst)
duke@0 1983 %{
duke@0 1984 // BSWAP
duke@0 1985 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 1986 %}
duke@0 1987
duke@0 1988 enc_class reg_opc(rRegI div)
duke@0 1989 %{
duke@0 1990 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 1991 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 1992 %}
duke@0 1993
duke@0 1994 enc_class enc_cmov(cmpOp cop)
duke@0 1995 %{
duke@0 1996 // CMOV
duke@0 1997 $$$emit8$primary;
duke@0 1998 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 1999 %}
duke@0 2000
duke@0 2001 enc_class enc_PartialSubtypeCheck()
duke@0 2002 %{
duke@0 2003 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2004 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2005 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2006 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2007 Label miss;
jrose@644 2008 const bool set_cond_codes = true;
duke@0 2009
duke@0 2010 MacroAssembler _masm(&cbuf);
jrose@644 2011 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2012 NULL, &miss,
jrose@644 2013 /*set_cond_codes:*/ true);
duke@0 2014 if ($primary) {
never@304 2015 __ xorptr(Rrdi, Rrdi);
duke@0 2016 }
duke@0 2017 __ bind(miss);
duke@0 2018 %}
duke@0 2019
duke@0 2020 enc_class Java_To_Interpreter(method meth)
duke@0 2021 %{
duke@0 2022 // CALL Java_To_Interpreter
duke@0 2023 // This is the instruction starting address for relocation info.
twisti@1668 2024 cbuf.set_insts_mark();
duke@0 2025 $$$emit8$primary;
duke@0 2026 // CALL directly to the runtime
duke@0 2027 emit_d32_reloc(cbuf,
twisti@1668 2028 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2029 runtime_call_Relocation::spec(),
duke@0 2030 RELOC_DISP32);
duke@0 2031 %}
duke@0 2032
duke@0 2033 enc_class Java_Static_Call(method meth)
duke@0 2034 %{
duke@0 2035 // JAVA STATIC CALL
duke@0 2036 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2037 // determine who we intended to call.
twisti@1668 2038 cbuf.set_insts_mark();
duke@0 2039 $$$emit8$primary;
duke@0 2040
duke@0 2041 if (!_method) {
duke@0 2042 emit_d32_reloc(cbuf,
twisti@1668 2043 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2044 runtime_call_Relocation::spec(),
duke@0 2045 RELOC_DISP32);
duke@0 2046 } else if (_optimized_virtual) {
duke@0 2047 emit_d32_reloc(cbuf,
twisti@1668 2048 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2049 opt_virtual_call_Relocation::spec(),
duke@0 2050 RELOC_DISP32);
duke@0 2051 } else {
duke@0 2052 emit_d32_reloc(cbuf,
twisti@1668 2053 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2054 static_call_Relocation::spec(),
duke@0 2055 RELOC_DISP32);
duke@0 2056 }
duke@0 2057 if (_method) {
duke@0 2058 // Emit stub for static call
duke@0 2059 emit_java_to_interp(cbuf);
duke@0 2060 }
duke@0 2061 %}
duke@0 2062
duke@0 2063 enc_class Java_Dynamic_Call(method meth)
duke@0 2064 %{
duke@0 2065 // JAVA DYNAMIC CALL
duke@0 2066 // !!!!!
duke@0 2067 // Generate "movq rax, -1", placeholder instruction to load oop-info
duke@0 2068 // emit_call_dynamic_prologue( cbuf );
twisti@1668 2069 cbuf.set_insts_mark();
duke@0 2070
duke@0 2071 // movq rax, -1
duke@0 2072 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2073 emit_opcode(cbuf, 0xB8 | RAX_enc);
duke@0 2074 emit_d64_reloc(cbuf,
duke@0 2075 (int64_t) Universe::non_oop_word(),
duke@0 2076 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
twisti@1668 2077 address virtual_call_oop_addr = cbuf.insts_mark();
duke@0 2078 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2079 // who we intended to call.
twisti@1668 2080 cbuf.set_insts_mark();
duke@0 2081 $$$emit8$primary;
duke@0 2082 emit_d32_reloc(cbuf,
twisti@1668 2083 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2084 virtual_call_Relocation::spec(virtual_call_oop_addr),
duke@0 2085 RELOC_DISP32);
duke@0 2086 %}
duke@0 2087
duke@0 2088 enc_class Java_Compiled_Call(method meth)
duke@0 2089 %{
duke@0 2090 // JAVA COMPILED CALL
duke@0 2091 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
duke@0 2092
duke@0 2093 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2094 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2095
duke@0 2096 // callq *disp(%rax)
twisti@1668 2097 cbuf.set_insts_mark();
duke@0 2098 $$$emit8$primary;
duke@0 2099 if (disp < 0x80) {
duke@0 2100 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2101 emit_d8(cbuf, disp); // Displacement
duke@0 2102 } else {
duke@0 2103 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2104 emit_d32(cbuf, disp); // Displacement
duke@0 2105 }
duke@0 2106 %}
duke@0 2107
duke@0 2108 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2109 %{
duke@0 2110 // SAL, SAR, SHR
duke@0 2111 int dstenc = $dst$$reg;
duke@0 2112 if (dstenc >= 8) {
duke@0 2113 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2114 dstenc -= 8;
duke@0 2115 }
duke@0 2116 $$$emit8$primary;
duke@0 2117 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2118 $$$emit8$shift$$constant;
duke@0 2119 %}
duke@0 2120
duke@0 2121 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2122 %{
duke@0 2123 // SAL, SAR, SHR
duke@0 2124 int dstenc = $dst$$reg;
duke@0 2125 if (dstenc < 8) {
duke@0 2126 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2127 } else {
duke@0 2128 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2129 dstenc -= 8;
duke@0 2130 }
duke@0 2131 $$$emit8$primary;
duke@0 2132 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2133 $$$emit8$shift$$constant;
duke@0 2134 %}
duke@0 2135
duke@0 2136 enc_class load_immI(rRegI dst, immI src)
duke@0 2137 %{
duke@0 2138 int dstenc = $dst$$reg;
duke@0 2139 if (dstenc >= 8) {
duke@0 2140 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2141 dstenc -= 8;
duke@0 2142 }
duke@0 2143 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2144 $$$emit32$src$$constant;
duke@0 2145 %}
duke@0 2146
duke@0 2147 enc_class load_immL(rRegL dst, immL src)
duke@0 2148 %{
duke@0 2149 int dstenc = $dst$$reg;
duke@0 2150 if (dstenc < 8) {
duke@0 2151 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2152 } else {
duke@0 2153 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2154 dstenc -= 8;
duke@0 2155 }
duke@0 2156 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2157 emit_d64(cbuf, $src$$constant);
duke@0 2158 %}
duke@0 2159
duke@0 2160 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2161 %{
duke@0 2162 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2163 int dstenc = $dst$$reg;
duke@0 2164 if (dstenc >= 8) {
duke@0 2165 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2166 dstenc -= 8;
duke@0 2167 }
duke@0 2168 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2169 $$$emit32$src$$constant;
duke@0 2170 %}
duke@0 2171
duke@0 2172 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2173 %{
duke@0 2174 int dstenc = $dst$$reg;
duke@0 2175 if (dstenc < 8) {
duke@0 2176 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2177 } else {
duke@0 2178 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2179 dstenc -= 8;
duke@0 2180 }
duke@0 2181 emit_opcode(cbuf, 0xC7);
duke@0 2182 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2183 $$$emit32$src$$constant;
duke@0 2184 %}
duke@0 2185
duke@0 2186 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2187 %{
duke@0 2188 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2189 int dstenc = $dst$$reg;
duke@0 2190 if (dstenc >= 8) {
duke@0 2191 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2192 dstenc -= 8;
duke@0 2193 }
duke@0 2194 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2195 $$$emit32$src$$constant;
duke@0 2196 %}
duke@0 2197
duke@0 2198 enc_class load_immP(rRegP dst, immP src)
duke@0 2199 %{
duke@0 2200 int dstenc = $dst$$reg;
duke@0 2201 if (dstenc < 8) {
duke@0 2202 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2203 } else {
duke@0 2204 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2205 dstenc -= 8;
duke@0 2206 }
duke@0 2207 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2208 // This next line should be generated from ADLC
duke@0 2209 if ($src->constant_is_oop()) {
duke@0 2210 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
duke@0 2211 } else {
duke@0 2212 emit_d64(cbuf, $src$$constant);
duke@0 2213 }
duke@0 2214 %}
duke@0 2215
duke@0 2216 enc_class Con32(immI src)
duke@0 2217 %{
duke@0 2218 // Output immediate
duke@0 2219 $$$emit32$src$$constant;
duke@0 2220 %}
duke@0 2221
duke@0 2222 enc_class Con64(immL src)
duke@0 2223 %{
duke@0 2224 // Output immediate
duke@0 2225 emit_d64($src$$constant);
duke@0 2226 %}
duke@0 2227
duke@0 2228 enc_class Con32F_as_bits(immF src)
duke@0 2229 %{
duke@0 2230 // Output Float immediate bits
duke@0 2231 jfloat jf = $src$$constant;
duke@0 2232 jint jf_as_bits = jint_cast(jf);
duke@0 2233 emit_d32(cbuf, jf_as_bits);
duke@0 2234 %}
duke@0 2235
duke@0 2236 enc_class Con16(immI src)
duke@0 2237 %{
duke@0 2238 // Output immediate
duke@0 2239 $$$emit16$src$$constant;
duke@0 2240 %}
duke@0 2241
duke@0 2242 // How is this different from Con32??? XXX
duke@0 2243 enc_class Con_d32(immI src)
duke@0 2244 %{
duke@0 2245 emit_d32(cbuf,$src$$constant);
duke@0 2246 %}
duke@0 2247
duke@0 2248 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2249 // Output immediate memory reference
duke@0 2250 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2251 emit_d32(cbuf, 0x00);
duke@0 2252 %}
duke@0 2253
duke@0 2254 enc_class lock_prefix()
duke@0 2255 %{
duke@0 2256 if (os::is_MP()) {
duke@0 2257 emit_opcode(cbuf, 0xF0); // lock
duke@0 2258 }
duke@0 2259 %}
duke@0 2260
duke@0 2261 enc_class REX_mem(memory mem)
duke@0 2262 %{
duke@0 2263 if ($mem$$base >= 8) {
duke@0 2264 if ($mem$$index < 8) {
duke@0 2265 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2266 } else {
duke@0 2267 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2268 }
duke@0 2269 } else {
duke@0 2270 if ($mem$$index >= 8) {
duke@0 2271 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2272 }
duke@0 2273 }
duke@0 2274 %}
duke@0 2275
duke@0 2276 enc_class REX_mem_wide(memory mem)
duke@0 2277 %{
duke@0 2278 if ($mem$$base >= 8) {
duke@0 2279 if ($mem$$index < 8) {
duke@0 2280 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2281 } else {
duke@0 2282 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2283 }
duke@0 2284 } else {
duke@0 2285 if ($mem$$index < 8) {
duke@0 2286 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2287 } else {
duke@0 2288 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2289 }
duke@0 2290 }
duke@0 2291 %}
duke@0 2292
duke@0 2293 // for byte regs
duke@0 2294 enc_class REX_breg(rRegI reg)
duke@0 2295 %{
duke@0 2296 if ($reg$$reg >= 4) {
duke@0 2297 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2298 }
duke@0 2299 %}
duke@0 2300
duke@0 2301 // for byte regs
duke@0 2302 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2303 %{
duke@0 2304 if ($dst$$reg < 8) {
duke@0 2305 if ($src$$reg >= 4) {
duke@0 2306 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2307 }
duke@0 2308 } else {
duke@0 2309 if ($src$$reg < 8) {
duke@0 2310 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2311 } else {
duke@0 2312 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2313 }
duke@0 2314 }
duke@0 2315 %}
duke@0 2316
duke@0 2317 // for byte regs
duke@0 2318 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2319 %{
duke@0 2320 if ($reg$$reg < 8) {
duke@0 2321 if ($mem$$base < 8) {
duke@0 2322 if ($mem$$index >= 8) {
duke@0 2323 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2324 } else if ($reg$$reg >= 4) {
duke@0 2325 emit_opcode(cbuf, Assembler::REX);
duke@0 2326 }
duke@0 2327 } else {
duke@0 2328 if ($mem$$index < 8) {
duke@0 2329 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2330 } else {
duke@0 2331 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2332 }
duke@0 2333 }
duke@0 2334 } else {
duke@0 2335 if ($mem$$base < 8) {
duke@0 2336 if ($mem$$index < 8) {
duke@0 2337 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2338 } else {
duke@0 2339 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2340 }
duke@0 2341 } else {
duke@0 2342 if ($mem$$index < 8) {
duke@0 2343 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2344 } else {
duke@0 2345 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2346 }
duke@0 2347 }
duke@0 2348 }
duke@0 2349 %}
duke@0 2350
duke@0 2351 enc_class REX_reg(rRegI reg)
duke@0 2352 %{
duke@0 2353 if ($reg$$reg >= 8) {
duke@0 2354 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2355 }
duke@0 2356 %}
duke@0 2357
duke@0 2358 enc_class REX_reg_wide(rRegI reg)
duke@0 2359 %{
duke@0 2360 if ($reg$$reg < 8) {
duke@0 2361 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2362 } else {
duke@0 2363 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2364 }
duke@0 2365 %}
duke@0 2366
duke@0 2367 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2368 %{
duke@0 2369 if ($dst$$reg < 8) {
duke@0 2370 if ($src$$reg >= 8) {
duke@0 2371 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2372 }
duke@0 2373 } else {
duke@0 2374 if ($src$$reg < 8) {
duke@0 2375 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2376 } else {
duke@0 2377 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2378 }
duke@0 2379 }
duke@0 2380 %}
duke@0 2381
duke@0 2382 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2383 %{
duke@0 2384 if ($dst$$reg < 8) {
duke@0 2385 if ($src$$reg < 8) {
duke@0 2386 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2387 } else {
duke@0 2388 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2389 }
duke@0 2390 } else {
duke@0 2391 if ($src$$reg < 8) {
duke@0 2392 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2393 } else {
duke@0 2394 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2395 }
duke@0 2396 }
duke@0 2397 %}
duke@0 2398
duke@0 2399 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 2400 %{
duke@0 2401 if ($reg$$reg < 8) {
duke@0 2402 if ($mem$$base < 8) {
duke@0 2403 if ($mem$$index >= 8) {
duke@0 2404 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2405 }
duke@0 2406 } else {
duke@0 2407 if ($mem$$index < 8) {
duke@0 2408 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2409 } else {
duke@0 2410 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2411 }
duke@0 2412 }
duke@0 2413 } else {
duke@0 2414 if ($mem$$base < 8) {
duke@0 2415 if ($mem$$index < 8) {
duke@0 2416 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2417 } else {
duke@0 2418 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2419 }
duke@0 2420 } else {
duke@0 2421 if ($mem$$index < 8) {
duke@0 2422 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2423 } else {
duke@0 2424 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2425 }
duke@0 2426 }
duke@0 2427 }
duke@0 2428 %}
duke@0 2429
duke@0 2430 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 2431 %{
duke@0 2432 if ($reg$$reg < 8) {
duke@0 2433 if ($mem$$base < 8) {
duke@0 2434 if ($mem$$index < 8) {
duke@0 2435 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2436 } else {
duke@0 2437 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2438 }
duke@0 2439 } else {
duke@0 2440 if ($mem$$index < 8) {
duke@0 2441 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2442 } else {
duke@0 2443 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2444 }
duke@0 2445 }
duke@0 2446 } else {
duke@0 2447 if ($mem$$base < 8) {
duke@0 2448 if ($mem$$index < 8) {
duke@0 2449 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2450 } else {
duke@0 2451 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 2452 }
duke@0 2453 } else {
duke@0 2454 if ($mem$$index < 8) {
duke@0 2455 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2456 } else {
duke@0 2457 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 2458 }
duke@0 2459 }
duke@0 2460 }
duke@0 2461 %}
duke@0 2462
duke@0 2463 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 2464 %{
duke@0 2465 // High registers handle in encode_RegMem
duke@0 2466 int reg = $ereg$$reg;
duke@0 2467 int base = $mem$$base;
duke@0 2468 int index = $mem$$index;
duke@0 2469 int scale = $mem$$scale;
duke@0 2470 int disp = $mem$$disp;
duke@0 2471 bool disp_is_oop = $mem->disp_is_oop();
duke@0 2472
duke@0 2473 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
duke@0 2474 %}
duke@0 2475
duke@0 2476 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 2477 %{
duke@0 2478 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 2479
duke@0 2480 // High registers handle in encode_RegMem
duke@0 2481 int base = $mem$$base;
duke@0 2482 int index = $mem$$index;
duke@0 2483 int scale = $mem$$scale;
duke@0 2484 int displace = $mem$$disp;
duke@0 2485
duke@0 2486 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
duke@0 2487 // working with static
duke@0 2488 // globals
duke@0 2489 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
duke@0 2490 disp_is_oop);
duke@0 2491 %}
duke@0 2492
duke@0 2493 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 2494 %{
duke@0 2495 int reg_encoding = $dst$$reg;
duke@0 2496 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 2497 int index = 0x04; // 0x04 indicates no index
duke@0 2498 int scale = 0x00; // 0x00 indicates no scale
duke@0 2499 int displace = $src1$$constant; // 0x00 indicates no displacement
duke@0 2500 bool disp_is_oop = false;
duke@0 2501 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
duke@0 2502 disp_is_oop);
duke@0 2503 %}
duke@0 2504
duke@0 2505 enc_class neg_reg(rRegI dst)
duke@0 2506 %{
duke@0 2507 int dstenc = $dst$$reg;
duke@0 2508 if (dstenc >= 8) {
duke@0 2509 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2510 dstenc -= 8;
duke@0 2511 }
duke@0 2512 // NEG $dst
duke@0 2513 emit_opcode(cbuf, 0xF7);
duke@0 2514 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2515 %}
duke@0 2516
duke@0 2517 enc_class neg_reg_wide(rRegI dst)
duke@0 2518 %{
duke@0 2519 int dstenc = $dst$$reg;
duke@0 2520 if (dstenc < 8) {
duke@0 2521 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2522 } else {
duke@0 2523 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2524 dstenc -= 8;
duke@0 2525 }
duke@0 2526 // NEG $dst
duke@0 2527 emit_opcode(cbuf, 0xF7);
duke@0 2528 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2529 %}
duke@0 2530
duke@0 2531 enc_class setLT_reg(rRegI dst)
duke@0 2532 %{
duke@0 2533 int dstenc = $dst$$reg;
duke@0 2534 if (dstenc >= 8) {
duke@0 2535 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2536 dstenc -= 8;
duke@0 2537 } else if (dstenc >= 4) {
duke@0 2538 emit_opcode(cbuf, Assembler::REX);
duke@0 2539 }
duke@0 2540 // SETLT $dst
duke@0 2541 emit_opcode(cbuf, 0x0F);
duke@0 2542 emit_opcode(cbuf, 0x9C);
duke@0 2543 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2544 %}
duke@0 2545
duke@0 2546 enc_class setNZ_reg(rRegI dst)
duke@0 2547 %{
duke@0 2548 int dstenc = $dst$$reg;
duke@0 2549 if (dstenc >= 8) {
duke@0 2550 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2551 dstenc -= 8;
duke@0 2552 } else if (dstenc >= 4) {
duke@0 2553 emit_opcode(cbuf, Assembler::REX);
duke@0 2554 }
duke@0 2555 // SETNZ $dst
duke@0 2556 emit_opcode(cbuf, 0x0F);
duke@0 2557 emit_opcode(cbuf, 0x95);
duke@0 2558 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2559 %}
duke@0 2560
duke@0 2561
duke@0 2562 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 2563 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 2564 %{
duke@0 2565 int src1enc = $src1$$reg;
duke@0 2566 int src2enc = $src2$$reg;
duke@0 2567 int dstenc = $dst$$reg;
duke@0 2568
duke@0 2569 // cmpq $src1, $src2
duke@0 2570 if (src1enc < 8) {
duke@0 2571 if (src2enc < 8) {
duke@0 2572 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2573 } else {
duke@0 2574 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2575 }
duke@0 2576 } else {
duke@0 2577 if (src2enc < 8) {
duke@0 2578 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2579 } else {
duke@0 2580 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2581 }
duke@0 2582 }
duke@0 2583 emit_opcode(cbuf, 0x3B);
duke@0 2584 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 2585
duke@0 2586 // movl $dst, -1
duke@0 2587 if (dstenc >= 8) {
duke@0 2588 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2589 }
duke@0 2590 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2591 emit_d32(cbuf, -1);
duke@0 2592
duke@0 2593 // jl,s done
duke@0 2594 emit_opcode(cbuf, 0x7C);
duke@0 2595 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2596
duke@0 2597 // setne $dst
duke@0 2598 if (dstenc >= 4) {
duke@0 2599 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2600 }
duke@0 2601 emit_opcode(cbuf, 0x0F);
duke@0 2602 emit_opcode(cbuf, 0x95);
duke@0 2603 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2604
duke@0 2605 // movzbl $dst, $dst
duke@0 2606 if (dstenc >= 4) {
duke@0 2607 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2608 }
duke@0 2609 emit_opcode(cbuf, 0x0F);
duke@0 2610 emit_opcode(cbuf, 0xB6);
duke@0 2611 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2612 %}
duke@0 2613
duke@0 2614 enc_class Push_ResultXD(regD dst) %{
kvn@2953 2615 MacroAssembler _masm(&cbuf);
kvn@2953 2616 __ fstp_d(Address(rsp, 0));
kvn@2953 2617 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
kvn@2953 2618 __ addptr(rsp, 8);
duke@0 2619 %}
duke@0 2620
duke@0 2621 enc_class Push_SrcXD(regD src) %{
duke@0 2622 MacroAssembler _masm(&cbuf);
kvn@2953 2623 __ subptr(rsp, 8);
kvn@2953 2624 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
kvn@2953 2625 __ fld_d(Address(rsp, 0));
kvn@2953 2626 %}
kvn@2953 2627
duke@0 2628
duke@0 2629 // obj: object to lock
duke@0 2630 // box: box address (header location) -- killed
duke@0 2631 // tmp: rax -- killed
duke@0 2632 // scr: rbx -- killed
duke@0 2633 //
duke@0 2634 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 2635 // from i486.ad. See that file for comments.
duke@0 2636 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 2637 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 2638
duke@0 2639
duke@0 2640 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 2641 %{
duke@0 2642 Register objReg = as_Register((int)$obj$$reg);
duke@0 2643 Register boxReg = as_Register((int)$box$$reg);
duke@0 2644 Register tmpReg = as_Register($tmp$$reg);
duke@0 2645 Register scrReg = as_Register($scr$$reg);
duke@0 2646 MacroAssembler masm(&cbuf);
duke@0 2647
duke@0 2648 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 2649 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 2650 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 2651
duke@0 2652 if (_counters != NULL) {
duke@0 2653 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 2654 }
duke@0 2655 if (EmitSync & 1) {
never@304 2656 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 2657 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 2658 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 2659 } else
duke@0 2660 if (EmitSync & 2) {
duke@0 2661 Label DONE_LABEL;
duke@0 2662 if (UseBiasedLocking) {
duke@0 2663 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 2664 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 2665 }
never@304 2666 // QQQ was movl...
never@304 2667 masm.movptr(tmpReg, 0x1);
never@304 2668 masm.orptr(tmpReg, Address(objReg, 0));
never@304 2669 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2670 if (os::is_MP()) {
duke@0 2671 masm.lock();
duke@0 2672 }
never@304 2673 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 2674 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 2675
duke@0 2676 // Recursive locking
never@304 2677 masm.subptr(tmpReg, rsp);
never@304 2678 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 2679 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2680
duke@0 2681 masm.bind(DONE_LABEL);
duke@0 2682 masm.nop(); // avoid branch to branch
duke@0 2683 } else {
duke@0 2684 Label DONE_LABEL, IsInflated, Egress;
duke@0 2685
iveresov@2251 2686 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 2687 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
iveresov@2251 2688 masm.jcc (Assembler::notZero, IsInflated) ;
iveresov@2251 2689
duke@0 2690 // it's stack-locked, biased or neutral
duke@0 2691 // TODO: optimize markword triage order to reduce the number of
duke@0 2692 // conditional branches in the most common cases.
duke@0 2693 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 2694 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 2695 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 2696
kvn@420 2697 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 2698 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 2699 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 2700 }
duke@0 2701
never@304 2702 // was q will it destroy high?
iveresov@2251 2703 masm.orl (tmpReg, 1) ;
iveresov@2251 2704 masm.movptr(Address(boxReg, 0), tmpReg) ;
iveresov@2251 2705 if (os::is_MP()) { masm.lock(); }
never@304 2706 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 2707 if (_counters != NULL) {
duke@0 2708 masm.cond_inc32(Assembler::equal,
duke@0 2709 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 2710 }
duke@0 2711 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 2712
duke@0 2713 // Recursive locking
never@304 2714 masm.subptr(tmpReg, rsp);
never@304 2715 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 2716 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2717 if (_counters != NULL) {
duke@0 2718 masm.cond_inc32(Assembler::equal,
duke@0 2719 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 2720 }
duke@0 2721 masm.jmp (DONE_LABEL) ;
duke@0 2722
duke@0 2723 masm.bind (IsInflated) ;
duke@0 2724 // It's inflated
duke@0 2725
duke@0 2726 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 2727 // relocating (deferring) the following ST.
duke@0 2728 // We should also think about trying a CAS without having
duke@0 2729 // fetched _owner. If the CAS is successful we may
duke@0 2730 // avoid an RTO->RTS upgrade on the $line.
never@304 2731 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 2732 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 2733
iveresov@2251 2734 masm.mov (boxReg, tmpReg) ;
iveresov@2251 2735 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 2736 masm.testptr(tmpReg, tmpReg) ;
iveresov@2251 2737 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 2738
duke@0 2739 // It's inflated and appears unlocked
iveresov@2251 2740 if (os::is_MP()) { masm.lock(); }
iveresov@2251 2741 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 2742 // Intentional fall-through into DONE_LABEL ...
duke@0 2743
duke@0 2744 masm.bind (DONE_LABEL) ;
duke@0 2745 masm.nop () ; // avoid jmp to jmp
duke@0 2746 }
duke@0 2747 %}
duke@0 2748
duke@0 2749 // obj: object to unlock
duke@0 2750 // box: box address (displaced header location), killed
duke@0 2751 // RBX: killed tmp; cannot be obj nor box
duke@0 2752 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 2753 %{
duke@0 2754
duke@0 2755 Register objReg = as_Register($obj$$reg);
duke@0 2756 Register boxReg = as_Register($box$$reg);
duke@0 2757 Register tmpReg = as_Register($tmp$$reg);
duke@0 2758 MacroAssembler masm(&cbuf);
duke@0 2759
iveresov@2251 2760 if (EmitSync & 4) {
iveresov@2251 2761 masm.cmpptr(rsp, 0) ;
duke@0 2762 } else
duke@0 2763 if (EmitSync & 8) {
duke@0 2764 Label DONE_LABEL;
duke@0 2765 if (UseBiasedLocking) {
duke@0 2766 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 2767 }
duke@0 2768
duke@0 2769 // Check whether the displaced header is 0
duke@0 2770 //(=> recursive unlock)
never@304 2771 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 2772 masm.testptr(tmpReg, tmpReg);
duke@0 2773 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 2774
duke@0 2775 // If not recursive lock, reset the header to displaced header
duke@0 2776 if (os::is_MP()) {
duke@0 2777 masm.lock();
duke@0 2778 }
never@304 2779 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 2780 masm.bind(DONE_LABEL);
duke@0 2781 masm.nop(); // avoid branch to branch
duke@0 2782 } else {
duke@0 2783 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 2784
kvn@420 2785 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 2786 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 2787 }
iveresov@2251 2788
iveresov@2251 2789 masm.movptr(tmpReg, Address(objReg, 0)) ;
iveresov@2251 2790 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
iveresov@2251 2791 masm.jcc (Assembler::zero, DONE_LABEL) ;
iveresov@2251 2792 masm.testl (tmpReg, 0x02) ;
iveresov@2251 2793 masm.jcc (Assembler::zero, Stacked) ;
iveresov@2251 2794
duke@0 2795 // It's inflated
iveresov@2251 2796 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 2797 masm.xorptr(boxReg, r15_thread) ;
iveresov@2251 2798 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
iveresov@2251 2799 masm.jcc (Assembler::notZero, DONE_LABEL) ;
iveresov@2251 2800 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
iveresov@2251 2801 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
iveresov@2251 2802 masm.jcc (Assembler::notZero, CheckSucc) ;
iveresov@2251 2803 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
iveresov@2251 2804 masm.jmp (DONE_LABEL) ;
iveresov@2251 2805
iveresov@2251 2806 if ((EmitSync & 65536) == 0) {
duke@0 2807 Label LSuccess, LGoSlowPath ;
duke@0 2808 masm.bind (CheckSucc) ;
never@304 2809 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2810 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 2811
duke@0 2812 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 2813 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 2814 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 2815 // are all faster when the write buffer is populated.
never@304 2816 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2817 if (os::is_MP()) {
never@304 2818 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 2819 }
never@304 2820 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2821 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 2822
never@304 2823 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 2824 if (os::is_MP()) { masm.lock(); }
never@304 2825 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 2826 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 2827 // Intentional fall-through into slow-path
duke@0 2828
duke@0 2829 masm.bind (LGoSlowPath) ;
duke@0 2830 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 2831 masm.jmp (DONE_LABEL) ;
duke@0 2832
duke@0 2833 masm.bind (LSuccess) ;
duke@0 2834 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 2835 masm.jmp (DONE_LABEL) ;
duke@0 2836 }
duke@0 2837
iveresov@2251 2838 masm.bind (Stacked) ;
never@304 2839 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
iveresov@2251 2840 if (os::is_MP()) { masm.lock(); }
never@304 2841 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 2842
duke@0 2843 if (EmitSync & 65536) {
duke@0 2844 masm.bind (CheckSucc) ;
duke@0 2845 }
duke@0 2846 masm.bind(DONE_LABEL);
duke@0 2847 if (EmitSync & 32768) {
duke@0 2848 masm.nop(); // avoid branch to branch
duke@0 2849 }
duke@0 2850 }
duke@0 2851 %}
duke@0 2852
rasbold@169 2853
duke@0 2854 enc_class enc_rethrow()
duke@0 2855 %{
twisti@1668 2856 cbuf.set_insts_mark();
duke@0 2857 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 2858 emit_d32_reloc(cbuf,
twisti@1668 2859 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 2860 runtime_call_Relocation::spec(),
duke@0 2861 RELOC_DISP32);
duke@0 2862 %}
duke@0 2863
duke@0 2864 %}
duke@0 2865
duke@0 2866
coleenp@113 2867
duke@0 2868 //----------FRAME--------------------------------------------------------------
duke@0 2869 // Definition of frame structure and management information.
duke@0 2870 //
duke@0 2871 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 2872 // | (to get allocators register number
duke@0 2873 // G Owned by | | v add OptoReg::stack0())
duke@0 2874 // r CALLER | |
duke@0 2875 // o | +--------+ pad to even-align allocators stack-slot
duke@0 2876 // w V | pad0 | numbers; owned by CALLER
duke@0 2877 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 2878 // h ^ | in | 5
duke@0 2879 // | | args | 4 Holes in incoming args owned by SELF
duke@0 2880 // | | | | 3
duke@0 2881 // | | +--------+
duke@0 2882 // V | | old out| Empty on Intel, window on Sparc
duke@0 2883 // | old |preserve| Must be even aligned.
duke@0 2884 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 2885 // | | in | 3 area for Intel ret address
duke@0 2886 // Owned by |preserve| Empty on Sparc.
duke@0 2887 // SELF +--------+
duke@0 2888 // | | pad2 | 2 pad to align old SP
duke@0 2889 // | +--------+ 1
duke@0 2890 // | | locks | 0
duke@0 2891 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 2892 // | | pad1 | 11 pad to align new SP
duke@0 2893 // | +--------+
duke@0 2894 // | | | 10
duke@0 2895 // | | spills | 9 spills
duke@0 2896 // V | | 8 (pad0 slot for callee)
duke@0 2897 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 2898 // ^ | out | 7
duke@0 2899 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 2900 // Owned by +--------+
duke@0 2901 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 2902 // | new |preserve| Must be even-aligned.
duke@0 2903 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 2904 // | | |
duke@0 2905 //
duke@0 2906 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 2907 // known from SELF's arguments and the Java calling convention.
duke@0 2908 // Region 6-7 is determined per call site.
duke@0 2909 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 2910 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 2911 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 2912 // incoming area, as the Java calling convention is completely under
duke@0 2913 // the control of the AD file. Doubles can be sorted and packed to
duke@0 2914 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 2915 // varargs C calling conventions.
duke@0 2916 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 2917 // even aligned with pad0 as needed.
duke@0 2918 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 2919 // region 6-11 is even aligned; it may be padded out more so that
duke@0 2920 // the region from SP to FP meets the minimum stack alignment.
duke@0 2921 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
duke@0 2922 // alignment. Region 11, pad1, may be dynamically extended so that
duke@0 2923 // SP meets the minimum alignment.
duke@0 2924
duke@0 2925 frame
duke@0 2926 %{
duke@0 2927 // What direction does stack grow in (assumed to be same for C & Java)
duke@0 2928 stack_direction(TOWARDS_LOW);
duke@0 2929
duke@0 2930 // These three registers define part of the calling convention
duke@0 2931 // between compiled code and the interpreter.
duke@0 2932 inline_cache_reg(RAX); // Inline Cache Register
duke@0 2933 interpreter_method_oop_reg(RBX); // Method Oop Register when
duke@0 2934 // calling interpreter
duke@0 2935
duke@0 2936 // Optional: name the operand used by cisc-spilling to access
duke@0 2937 // [stack_pointer + offset]
duke@0 2938 cisc_spilling_operand_name(indOffset32);
duke@0 2939
duke@0 2940 // Number of stack slots consumed by locking an object
duke@0 2941 sync_stack_slots(2);
duke@0 2942
duke@0 2943 // Compiled code's Frame Pointer
duke@0 2944 frame_pointer(RSP);
duke@0 2945
duke@0 2946 // Interpreter stores its frame pointer in a register which is
duke@0 2947 // stored to the stack by I2CAdaptors.
duke@0 2948 // I2CAdaptors convert from interpreted java to compiled java.
duke@0 2949 interpreter_frame_pointer(RBP);
duke@0 2950
duke@0 2951 // Stack alignment requirement
duke@0 2952 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
duke@0 2953
duke@0 2954 // Number of stack slots between incoming argument block and the start of
duke@0 2955 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 2956 // EPILOG must remove this many slots. amd64 needs two slots for
duke@0 2957 // return address.
duke@0 2958 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
duke@0 2959
duke@0 2960 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 2961 // for calls to C. Supports the var-args backing area for register parms.
duke@0 2962 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
duke@0 2963
duke@0 2964 // The after-PROLOG location of the return address. Location of
duke@0 2965 // return address specifies a type (REG or STACK) and a number
duke@0 2966 // representing the register number (i.e. - use a register name) or
duke@0 2967 // stack slot.
duke@0 2968 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
duke@0 2969 // Otherwise, it is above the locks and verification slot and alignment word
duke@0 2970 return_addr(STACK - 2 +
kvn@3142 2971 round_to((Compile::current()->in_preserve_stack_slots() +
kvn@3142 2972 Compile::current()->fixed_slots()),
kvn@3142 2973 stack_alignment_in_slots()));
duke@0 2974
duke@0 2975 // Body of function which returns an integer array locating
duke@0 2976 // arguments either in registers or in stack slots. Passed an array
duke@0 2977 // of ideal registers called "sig" and a "length" count. Stack-slot
duke@0 2978 // offsets are based on outgoing arguments, i.e. a CALLER setting up
duke@0 2979 // arguments for a CALLEE. Incoming stack arguments are
duke@0 2980 // automatically biased by the preserve_stack_slots field above.
duke@0 2981
duke@0 2982 calling_convention
duke@0 2983 %{
duke@0 2984 // No difference between ingoing/outgoing just pass false
duke@0 2985 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
duke@0 2986 %}
duke@0 2987
duke@0 2988 c_calling_convention
duke@0 2989 %{
duke@0 2990 // This is obviously always outgoing
duke@0 2991 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
duke@0 2992 %}
duke@0 2993
duke@0 2994 // Location of compiled Java return values. Same as C for now.
duke@0 2995 return_value
duke@0 2996 %{
duke@0 2997 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
duke@0 2998 "only return normal values");
duke@0 2999
duke@0 3000 static const int lo[Op_RegL + 1] = {
duke@0 3001 0,
duke@0 3002 0,
coleenp@113 3003 RAX_num, // Op_RegN
duke@0 3004 RAX_num, // Op_RegI
duke@0 3005 RAX_num, // Op_RegP
duke@0 3006 XMM0_num, // Op_RegF
duke@0 3007 XMM0_num, // Op_RegD
duke@0 3008 RAX_num // Op_RegL
duke@0 3009 };
duke@0 3010 static const int hi[Op_RegL + 1] = {
duke@0 3011 0,
duke@0 3012 0,
coleenp@113 3013 OptoReg::Bad, // Op_RegN
duke@0 3014 OptoReg::Bad, // Op_RegI
duke@0 3015 RAX_H_num, // Op_RegP
duke@0 3016 OptoReg::Bad, // Op_RegF
kvn@3447 3017 XMM0b_num, // Op_RegD
duke@0 3018 RAX_H_num // Op_RegL
duke@0 3019 };
kvn@3447 3020 // Excluded flags and vector registers.
kvn@3447 3021 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
duke@0 3022 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
duke@0 3023 %}
duke@0 3024 %}
duke@0 3025
duke@0 3026 //----------ATTRIBUTES---------------------------------------------------------
duke@0 3027 //----------Operand Attributes-------------------------------------------------
duke@0 3028 op_attrib op_cost(0); // Required cost attribute
duke@0 3029
duke@0 3030 //----------Instruction Attributes---------------------------------------------
duke@0 3031 ins_attrib ins_cost(100); // Required cost attribute
duke@0 3032 ins_attrib ins_size(8); // Required size attribute (in bits)
duke@0 3033 ins_attrib ins_short_branch(0); // Required flag: is this instruction
duke@0 3034 // a non-matching short branch variant
duke@0 3035 // of some long branch?
duke@0 3036 ins_attrib ins_alignment(1); // Required alignment attribute (must
duke@0 3037 // be a power of 2) specifies the
duke@0 3038 // alignment that some part of the
duke@0 3039 // instruction (not necessarily the
duke@0 3040 // start) requires. If > 1, a
duke@0 3041 // compute_padding() function must be
duke@0 3042 // provided for the instruction
duke@0 3043
duke@0 3044 //----------OPERANDS-----------------------------------------------------------
duke@0 3045 // Operand definitions must precede instruction definitions for correct parsing
duke@0 3046 // in the ADLC because operands constitute user defined types which are used in
duke@0 3047 // instruction definitions.
duke@0 3048
duke@0 3049 //----------Simple Operands----------------------------------------------------
duke@0 3050 // Immediate Operands
duke@0 3051 // Integer Immediate
duke@0 3052 operand immI()
duke@0 3053 %{
duke@0 3054 match(ConI);
duke@0 3055
duke@0 3056 op_cost(10);
duke@0 3057 format %{ %}
duke@0 3058 interface(CONST_INTER);
duke@0 3059 %}
duke@0 3060
duke@0 3061 // Constant for test vs zero
duke@0 3062 operand immI0()
duke@0 3063 %{
duke@0 3064 predicate(n->get_int() == 0);
duke@0 3065 match(ConI);
duke@0 3066
duke@0 3067 op_cost(0);
duke@0 3068 format %{ %}
duke@0 3069 interface(CONST_INTER);
duke@0 3070 %}
duke@0 3071
duke@0 3072 // Constant for increment
duke@0 3073 operand immI1()
duke@0 3074 %{
duke@0 3075 predicate(n->get_int() == 1);
duke@0 3076 match(ConI);
duke@0 3077
duke@0 3078 op_cost(0);
duke@0 3079 format %{ %}
duke@0 3080 interface(CONST_INTER);
duke@0 3081 %}
duke@0 3082
duke@0 3083 // Constant for decrement
duke@0 3084 operand immI_M1()
duke@0 3085 %{
duke@0 3086 predicate(n->get_int() == -1);
duke@0 3087 match(ConI);
duke@0 3088
duke@0 3089 op_cost(0);
duke@0 3090 format %{ %}
duke@0 3091 interface(CONST_INTER);
duke@0 3092 %}
duke@0 3093
duke@0 3094 // Valid scale values for addressing modes
duke@0 3095 operand immI2()
duke@0 3096 %{
duke@0 3097 predicate(0 <= n->get_int() && (n->get_int() <= 3));
duke@0 3098 match(ConI);
duke@0 3099
duke@0 3100 format %{ %}
duke@0 3101 interface(CONST_INTER);
duke@0 3102 %}
duke@0 3103
duke@0 3104 operand immI8()
duke@0 3105 %{
duke@0 3106 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
duke@0 3107 match(ConI);
duke@0 3108
duke@0 3109 op_cost(5);
duke@0 3110 format %{ %}
duke@0 3111 interface(CONST_INTER);
duke@0 3112 %}
duke@0 3113
duke@0 3114 operand immI16()
duke@0 3115 %{
duke@0 3116 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
duke@0 3117 match(ConI);
duke@0 3118
duke@0 3119 op_cost(10);
duke@0 3120 format %{ %}
duke@0 3121 interface(CONST_INTER);
duke@0 3122 %}
duke@0 3123
duke@0 3124 // Constant for long shifts
duke@0 3125 operand immI_32()
duke@0 3126 %{
duke@0 3127 predicate( n->get_int() == 32 );
duke@0 3128 match(ConI);
duke@0 3129
duke@0 3130 op_cost(0);
duke@0 3131 format %{ %}
duke@0 3132 interface(CONST_INTER);
duke@0 3133 %}
duke@0 3134
duke@0 3135 // Constant for long shifts
duke@0 3136 operand immI_64()
duke@0 3137 %{
duke@0 3138 predicate( n->get_int() == 64 );
duke@0 3139 match(ConI);
duke@0 3140
duke@0 3141 op_cost(0);
duke@0 3142 format %{ %}
duke@0 3143 interface(CONST_INTER);
duke@0 3144 %}
duke@0 3145
duke@0 3146 // Pointer Immediate
duke@0 3147 operand immP()
duke@0 3148 %{
duke@0 3149 match(ConP);
duke@0 3150
duke@0 3151 op_cost(10);
duke@0 3152 format %{ %}
duke@0 3153 interface(CONST_INTER);
duke@0 3154 %}
duke@0 3155
duke@0 3156 // NULL Pointer Immediate
duke@0 3157 operand immP0()
duke@0 3158 %{
duke@0 3159 predicate(n->get_ptr() == 0);
duke@0 3160 match(ConP);
duke@0 3161
duke@0 3162 op_cost(5);
duke@0 3163 format %{ %}
duke@0 3164 interface(CONST_INTER);
duke@0 3165 %}
duke@0 3166
coleenp@113 3167 // Pointer Immediate
coleenp@113 3168 operand immN() %{
coleenp@113 3169 match(ConN);
coleenp@113 3170
coleenp@113 3171 op_cost(10);
coleenp@113 3172 format %{ %}
coleenp@113 3173 interface(CONST_INTER);
coleenp@113 3174 %}
coleenp@113 3175
coleenp@113 3176 // NULL Pointer Immediate
coleenp@113 3177 operand immN0() %{
coleenp@113 3178 predicate(n->get_narrowcon() == 0);
coleenp@113 3179 match(ConN);
coleenp@113 3180
coleenp@113 3181 op_cost(5);
coleenp@113 3182 format %{ %}
coleenp@113 3183 interface(CONST_INTER);
coleenp@113 3184 %}
coleenp@113 3185
duke@0 3186 operand immP31()
duke@0 3187 %{
duke@0 3188 predicate(!n->as_Type()->type()->isa_oopptr()
duke@0 3189 && (n->get_ptr() >> 31) == 0);
duke@0 3190 match(ConP);
duke@0 3191
duke@0 3192 op_cost(5);
duke@0 3193 format %{ %}
duke@0 3194 interface(CONST_INTER);
duke@0 3195 %}
duke@0 3196
coleenp@113 3197
duke@0 3198 // Long Immediate
duke@0 3199 operand immL()
duke@0 3200 %{
duke@0 3201 match(ConL);
duke@0 3202
duke@0 3203 op_cost(20);
duke@0 3204 format %{ %}
duke@0 3205 interface(CONST_INTER);
duke@0 3206 %}
duke@0 3207
duke@0 3208 // Long Immediate 8-bit
duke@0 3209 operand immL8()
duke@0 3210 %{
duke@0 3211 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
duke@0 3212 match(ConL);
duke@0 3213
duke@0 3214 op_cost(5);
duke@0 3215 format %{ %}
duke@0 3216 interface(CONST_INTER);
duke@0 3217 %}
duke@0 3218
duke@0 3219 // Long Immediate 32-bit unsigned
duke@0 3220 operand immUL32()
duke@0 3221 %{
duke@0 3222 predicate(n->get_long() == (unsigned int) (n->get_long()));
duke@0 3223 match(ConL);
duke@0 3224
duke@0 3225 op_cost(10);
duke@0 3226 format %{ %}
duke@0 3227 interface(CONST_INTER);
duke@0 3228 %}
duke@0 3229
duke@0 3230 // Long Immediate 32-bit signed
duke@0 3231 operand immL32()
duke@0 3232 %{
duke@0 3233 predicate(n->get_long() == (int) (n->get_long()));
duke@0 3234 match(ConL);
duke@0 3235
duke@0 3236 op_cost(15);
duke@0 3237 format %{ %}
duke@0 3238 interface(CONST_INTER);
duke@0 3239 %}
duke@0 3240
duke@0 3241 // Long Immediate zero
duke@0 3242 operand immL0()
duke@0 3243 %{
duke@0 3244 predicate(n->get_long() == 0L);
duke@0 3245 match(ConL);
duke@0 3246
duke@0 3247 op_cost(10);
duke@0 3248 format %{ %}
duke@0 3249 interface(CONST_INTER);
duke@0 3250 %}
duke@0 3251
duke@0 3252 // Constant for increment
duke@0 3253 operand immL1()
duke@0 3254 %{
duke@0 3255 predicate(n->get_long() == 1);
duke@0 3256 match(ConL);
duke@0 3257
duke@0 3258 format %{ %}
duke@0 3259 interface(CONST_INTER);
duke@0 3260 %}
duke@0 3261
duke@0 3262 // Constant for decrement
duke@0 3263 operand immL_M1()
duke@0 3264 %{
duke@0 3265 predicate(n->get_long() == -1);
duke@0 3266 match(ConL);
duke@0 3267
duke@0 3268 format %{ %}
duke@0 3269 interface(CONST_INTER);
duke@0 3270 %}
duke@0 3271
duke@0 3272 // Long Immediate: the value 10
duke@0 3273 operand immL10()
duke@0 3274 %{
duke@0 3275 predicate(n->get_long() == 10);
duke@0 3276 match(ConL);
duke@0 3277
duke@0 3278 format %{ %}
duke@0 3279 interface(CONST_INTER);
duke@0 3280 %}
duke@0 3281
duke@0 3282 // Long immediate from 0 to 127.
duke@0 3283 // Used for a shorter form of long mul by 10.
duke@0 3284 operand immL_127()
duke@0 3285 %{
duke@0 3286 predicate(0 <= n->get_long() && n->get_long() < 0x80);
duke@0 3287 match(ConL);
duke@0 3288
duke@0 3289 op_cost(10);
duke@0 3290 format %{ %}
duke@0 3291 interface(CONST_INTER);
duke@0 3292 %}
duke@0 3293
duke@0 3294 // Long Immediate: low 32-bit mask
duke@0 3295 operand immL_32bits()
duke@0 3296 %{
duke@0 3297 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 3298 match(ConL);
duke@0 3299 op_cost(20);
duke@0 3300
duke@0 3301 format %{ %}
duke@0 3302 interface(CONST_INTER);
duke@0 3303 %}
duke@0 3304
duke@0 3305 // Float Immediate zero
duke@0 3306 operand immF0()
duke@0 3307 %{
duke@0 3308 predicate(jint_cast(n->getf()) == 0);
duke@0 3309 match(ConF);
duke@0 3310
duke@0 3311 op_cost(5);
duke@0 3312 format %{ %}
duke@0 3313 interface(CONST_INTER);
duke@0 3314 %}
duke@0 3315
duke@0 3316 // Float Immediate
duke@0 3317 operand immF()
duke@0 3318 %{
duke@0 3319 match(ConF);
duke@0 3320
duke@0 3321 op_cost(15);
duke@0 3322 format %{ %}
duke@0 3323 interface(CONST_INTER);
duke@0 3324 %}
duke@0 3325
duke@0 3326 // Double Immediate zero
duke@0 3327 operand immD0()
duke@0 3328 %{
duke@0 3329 predicate(jlong_cast(n->getd()) == 0);
duke@0 3330 match(ConD);
duke@0 3331
duke@0 3332 op_cost(5);
duke@0 3333 format %{ %}
duke@0 3334 interface(CONST_INTER);
duke@0 3335 %}
duke@0 3336
duke@0 3337 // Double Immediate
duke@0 3338 operand immD()
duke@0 3339 %{
duke@0 3340 match(ConD);
duke@0 3341
duke@0 3342 op_cost(15);
duke@0 3343 format %{ %}
duke@0 3344 interface(CONST_INTER);
duke@0 3345 %}
duke@0 3346
duke@0 3347 // Immediates for special shifts (sign extend)
duke@0 3348
duke@0 3349 // Constants for increment
duke@0 3350 operand immI_16()
duke@0 3351 %{
duke@0 3352 predicate(n->get_int() == 16);
duke@0 3353 match(ConI);
duke@0 3354
duke@0 3355 format %{ %}
duke@0 3356 interface(CONST_INTER);
duke@0 3357 %}
duke@0 3358
duke@0 3359 operand immI_24()
duke@0 3360 %{
duke@0 3361 predicate(n->get_int() == 24);
duke@0 3362 match(ConI);
duke@0 3363
duke@0 3364 format %{ %}
duke@0 3365 interface(CONST_INTER);
duke@0 3366 %}
duke@0 3367
duke@0 3368 // Constant for byte-wide masking
duke@0 3369 operand immI_255()
duke@0 3370 %{
duke@0 3371 predicate(n->get_int() == 255);
duke@0 3372 match(ConI);
duke@0 3373
duke@0 3374 format %{ %}
duke@0 3375 interface(CONST_INTER);
duke@0 3376 %}
duke@0 3377
duke@0 3378 // Constant for short-wide masking
duke@0 3379 operand immI_65535()
duke@0 3380 %{
duke@0 3381 predicate(n->get_int() == 65535);
duke@0 3382 match(ConI);
duke@0 3383
duke@0 3384 format %{ %}
duke@0 3385 interface(CONST_INTER);
duke@0 3386 %}
duke@0 3387
duke@0 3388 // Constant for byte-wide masking
duke@0 3389 operand immL_255()
duke@0 3390 %{
duke@0 3391 predicate(n->get_long() == 255);
duke@0 3392 match(ConL);
duke@0 3393
duke@0 3394 format %{ %}
duke@0 3395 interface(CONST_INTER);
duke@0 3396 %}
duke@0 3397
duke@0 3398 // Constant for short-wide masking
duke@0 3399 operand immL_65535()
duke@0 3400 %{
duke@0 3401 predicate(n->get_long() == 65535);
duke@0 3402 match(ConL);
duke@0 3403
duke@0 3404 format %{ %}
duke@0 3405 interface(CONST_INTER);
duke@0 3406 %}
duke@0 3407
duke@0 3408 // Register Operands
duke@0 3409 // Integer Register
duke@0 3410 operand rRegI()
duke@0 3411 %{
duke@0 3412 constraint(ALLOC_IN_RC(int_reg));
duke@0 3413 match(RegI);
duke@0 3414
duke@0 3415 match(rax_RegI);
duke@0 3416 match(rbx_RegI);
duke@0 3417 match(rcx_RegI);
duke@0 3418 match(rdx_RegI);
duke@0 3419 match(rdi_RegI);
duke@0 3420
duke@0 3421 format %{ %}
duke@0 3422 interface(REG_INTER);
duke@0 3423 %}
duke@0 3424
duke@0 3425 // Special Registers
duke@0 3426 operand rax_RegI()
duke@0 3427 %{
duke@0 3428 constraint(ALLOC_IN_RC(int_rax_reg));
duke@0 3429 match(RegI);
duke@0 3430 match(rRegI);
duke@0 3431
duke@0 3432 format %{ "RAX" %}
duke@0 3433 interface(REG_INTER);
duke@0 3434 %}
duke@0 3435
duke@0 3436 // Special Registers
duke@0 3437 operand rbx_RegI()
duke@0 3438 %{
duke@0 3439 constraint(ALLOC_IN_RC(int_rbx_reg));
duke@0 3440 match(RegI);
duke@0 3441 match(rRegI);
duke@0 3442
duke@0 3443 format %{ "RBX" %}
duke@0 3444 interface(REG_INTER);
duke@0 3445 %}
duke@0 3446
duke@0 3447 operand rcx_RegI()
duke@0 3448 %{
duke@0 3449 constraint(ALLOC_IN_RC(int_rcx_reg));
duke@0 3450 match(RegI);
duke@0 3451 match(rRegI);
duke@0 3452
duke@0 3453 format %{ "RCX" %}
duke@0 3454 interface(REG_INTER);
duke@0 3455 %}
duke@0 3456
duke@0 3457 operand rdx_RegI()
duke@0 3458 %{
duke@0 3459 constraint(ALLOC_IN_RC(int_rdx_reg));
duke@0 3460 match(RegI);
duke@0 3461 match(rRegI);
duke@0 3462
duke@0 3463 format %{ "RDX" %}
duke@0 3464 interface(REG_INTER);
duke@0 3465 %}
duke@0 3466
duke@0 3467 operand rdi_RegI()
duke@0 3468 %{
duke@0 3469 constraint(ALLOC_IN_RC(int_rdi_reg));
duke@0 3470 match(RegI);
duke@0 3471 match(rRegI);
duke@0 3472
duke@0 3473 format %{ "RDI" %}
duke@0 3474 interface(REG_INTER);
duke@0 3475 %}
duke@0 3476
duke@0 3477 operand no_rcx_RegI()
duke@0 3478 %{
duke@0 3479 constraint(ALLOC_IN_RC(int_no_rcx_reg));
duke@0 3480 match(RegI);
duke@0 3481 match(rax_RegI);
duke@0 3482 match(rbx_RegI);
duke@0 3483 match(rdx_RegI);
duke@0 3484 match(rdi_RegI);
duke@0 3485
duke@0 3486 format %{ %}
duke@0 3487 interface(REG_INTER);
duke@0 3488 %}
duke@0 3489
duke@0 3490 operand no_rax_rdx_RegI()
duke@0 3491 %{
duke@0 3492 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
duke@0 3493 match(RegI);
duke@0 3494 match(rbx_RegI);
duke@0 3495 match(rcx_RegI);
duke@0 3496 match(rdi_RegI);
duke@0 3497
duke@0 3498 format %{ %}
duke@0 3499 interface(REG_INTER);
duke@0 3500 %}
duke@0 3501
duke@0 3502 // Pointer Register
duke@0 3503 operand any_RegP()
duke@0 3504 %{
duke@0 3505 constraint(ALLOC_IN_RC(any_reg));
duke@0 3506 match(RegP);
duke@0 3507 match(rax_RegP);
duke@0 3508 match(rbx_RegP);
duke@0 3509 match(rdi_RegP);
duke@0 3510 match(rsi_RegP);
duke@0 3511 match(rbp_RegP);
duke@0 3512 match(r15_RegP);
duke@0 3513 match(rRegP);
duke@0 3514
duke@0 3515 format %{ %}
duke@0 3516 interface(REG_INTER);
duke@0 3517 %}
duke@0 3518
duke@0 3519 operand rRegP()
duke@0 3520 %{
duke@0 3521 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3522 match(RegP);
duke@0 3523 match(rax_RegP);
duke@0 3524 match(rbx_RegP);
duke@0 3525 match(rdi_RegP);
duke@0 3526 match(rsi_RegP);
duke@0 3527 match(rbp_RegP);
duke@0 3528 match(r15_RegP); // See Q&A below about r15_RegP.
duke@0 3529
duke@0 3530 format %{ %}
duke@0 3531 interface(REG_INTER);
duke@0 3532 %}
duke@0 3533
coleenp@113 3534 operand rRegN() %{
coleenp@113 3535 constraint(ALLOC_IN_RC(int_reg));
coleenp@113 3536 match(RegN);
coleenp@113 3537
coleenp@113 3538 format %{ %}
coleenp@113 3539 interface(REG_INTER);
coleenp@113 3540 %}
coleenp@113 3541
duke@0 3542 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
duke@0 3543 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
duke@0 3544 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
duke@0 3545 // The output of an instruction is controlled by the allocator, which respects
duke@0 3546 // register class masks, not match rules. Unless an instruction mentions
duke@0 3547 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
duke@0 3548 // by the allocator as an input.
duke@0 3549
duke@0 3550 operand no_rax_RegP()
duke@0 3551 %{
duke@0 3552 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
duke@0 3553 match(RegP);
duke@0 3554 match(rbx_RegP);
duke@0 3555 match(rsi_RegP);
duke@0 3556 match(rdi_RegP);
duke@0 3557
duke@0 3558 format %{ %}
duke@0 3559 interface(REG_INTER);
duke@0 3560 %}
duke@0 3561
duke@0 3562 operand no_rbp_RegP()
duke@0 3563 %{
duke@0 3564 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
duke@0 3565 match(RegP);
duke@0 3566 match(rbx_RegP);
duke@0 3567 match(rsi_RegP);
duke@0 3568 match(rdi_RegP);
duke@0 3569
duke@0 3570 format %{ %}
duke@0 3571 interface(REG_INTER);
duke@0 3572 %}
duke@0 3573
duke@0 3574 operand no_rax_rbx_RegP()
duke@0 3575 %{
duke@0 3576 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
duke@0 3577 match(RegP);
duke@0 3578 match(rsi_RegP);
duke@0 3579 match(rdi_RegP);
duke@0 3580
duke@0 3581 format %{ %}
duke@0 3582 interface(REG_INTER);
duke@0 3583 %}
duke@0 3584
duke@0 3585 // Special Registers
duke@0 3586 // Return a pointer value
duke@0 3587 operand rax_RegP()
duke@0 3588 %{
duke@0 3589 constraint(ALLOC_IN_RC(ptr_rax_reg));
duke@0 3590 match(RegP);
duke@0 3591 match(rRegP);
duke@0 3592
duke@0 3593 format %{ %}
duke@0 3594 interface(REG_INTER);
duke@0 3595 %}
duke@0 3596
coleenp@113 3597 // Special Registers
coleenp@113 3598 // Return a compressed pointer value
coleenp@113 3599 operand rax_RegN()
coleenp@113 3600 %{
coleenp@113 3601 constraint(ALLOC_IN_RC(int_rax_reg));
coleenp@113 3602 match(RegN);
coleenp@113 3603 match(rRegN);
coleenp@113 3604
coleenp@113 3605 format %{ %}
coleenp@113 3606 interface(REG_INTER);
coleenp@113 3607 %}
coleenp@113 3608
duke@0 3609 // Used in AtomicAdd
duke@0 3610 operand rbx_RegP()
duke@0 3611 %{
duke@0 3612 constraint(ALLOC_IN_RC(ptr_rbx_reg));
duke@0 3613 match(RegP);
duke@0 3614 match(rRegP);
duke@0 3615
duke@0 3616 format %{ %}
duke@0 3617 interface(REG_INTER);
duke@0 3618 %}
duke@0 3619
duke@0 3620 operand rsi_RegP()
duke@0 3621 %{
duke@0 3622 constraint(ALLOC_IN_RC(ptr_rsi_reg));
duke@0 3623 match(RegP);
duke@0 3624 match(rRegP);
duke@0 3625
duke@0 3626 format %{ %}
duke@0 3627 interface(REG_INTER);
duke@0 3628 %}
duke@0 3629
duke@0 3630 // Used in rep stosq
duke@0 3631 operand rdi_RegP()
duke@0 3632 %{
duke@0 3633 constraint(ALLOC_IN_RC(ptr_rdi_reg));
duke@0 3634 match(RegP);
duke@0 3635 match(rRegP);
duke@0 3636
duke@0 3637 format %{ %}
duke@0 3638 interface(REG_INTER);
duke@0 3639 %}
duke@0 3640
duke@0 3641 operand rbp_RegP()
duke@0 3642 %{
duke@0 3643 constraint(ALLOC_IN_RC(ptr_rbp_reg));
duke@0 3644 match(RegP);
duke@0 3645 match(rRegP);
duke@0 3646
duke@0 3647 format %{ %}
duke@0 3648 interface(REG_INTER);
duke@0 3649 %}
duke@0 3650
duke@0 3651 operand r15_RegP()
duke@0 3652 %{
duke@0 3653 constraint(ALLOC_IN_RC(ptr_r15_reg));
duke@0 3654 match(RegP);
duke@0 3655 match(rRegP);
duke@0 3656
duke@0 3657 format %{ %}
duke@0 3658 interface(REG_INTER);
duke@0 3659 %}
duke@0 3660
duke@0 3661 operand rRegL()
duke@0 3662 %{
duke@0 3663 constraint(ALLOC_IN_RC(long_reg));
duke@0 3664 match(RegL);
duke@0 3665 match(rax_RegL);
duke@0 3666 match(rdx_RegL);
duke@0 3667
duke@0 3668 format %{ %}
duke@0 3669 interface(REG_INTER);
duke@0 3670 %}
duke@0 3671
duke@0 3672 // Special Registers
duke@0 3673 operand no_rax_rdx_RegL()
duke@0 3674 %{
duke@0 3675 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3676 match(RegL);
duke@0 3677 match(rRegL);
duke@0 3678
duke@0 3679 format %{ %}
duke@0 3680 interface(REG_INTER);
duke@0 3681 %}
duke@0 3682
duke@0 3683 operand no_rax_RegL()
duke@0 3684 %{
duke@0 3685 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3686 match(RegL);
duke@0 3687 match(rRegL);
duke@0 3688 match(rdx_RegL);
duke@0 3689
duke@0 3690 format %{ %}
duke@0 3691 interface(REG_INTER);
duke@0 3692 %}
duke@0 3693
duke@0 3694 operand no_rcx_RegL()
duke@0 3695 %{
duke@0 3696 constraint(ALLOC_IN_RC(long_no_rcx_reg));
duke@0 3697 match(RegL);
duke@0 3698 match(rRegL);
duke@0 3699
duke@0 3700 format %{ %}
duke@0 3701 interface(REG_INTER);
duke@0 3702 %}
duke@0 3703
duke@0 3704 operand rax_RegL()
duke@0 3705 %{
duke@0 3706 constraint(ALLOC_IN_RC(long_rax_reg));
duke@0 3707 match(RegL);
duke@0 3708 match(rRegL);
duke@0 3709
duke@0 3710 format %{ "RAX" %}
duke@0 3711 interface(REG_INTER);
duke@0 3712 %}
duke@0 3713
duke@0 3714 operand rcx_RegL()
duke@0 3715 %{
duke@0 3716 constraint(ALLOC_IN_RC(long_rcx_reg));
duke@0 3717 match(RegL);
duke@0 3718 match(rRegL);
duke@0 3719
duke@0 3720 format %{ %}
duke@0 3721 interface(REG_INTER);
duke@0 3722 %}
duke@0 3723
duke@0 3724 operand rdx_RegL()
duke@0 3725 %{
duke@0 3726 constraint(ALLOC_IN_RC(long_rdx_reg));
duke@0 3727 match(RegL);
duke@0 3728 match(rRegL);
duke@0 3729
duke@0 3730 format %{ %}
duke@0 3731 interface(REG_INTER);
duke@0 3732 %}
duke@0 3733
duke@0 3734 // Flags register, used as output of compare instructions
duke@0 3735 operand rFlagsReg()
duke@0 3736 %{
duke@0 3737 constraint(ALLOC_IN_RC(int_flags));
duke@0 3738 match(RegFlags);
duke@0 3739
duke@0 3740 format %{ "RFLAGS" %}
duke@0 3741 interface(REG_INTER);
duke@0 3742 %}
duke@0 3743
duke@0 3744 // Flags register, used as output of FLOATING POINT compare instructions
duke@0 3745 operand rFlagsRegU()
duke@0 3746 %{
duke@0 3747 constraint(ALLOC_IN_RC(int_flags));
duke@0 3748 match(RegFlags);
duke@0 3749
duke@0 3750 format %{ "RFLAGS_U" %}
duke@0 3751 interface(REG_INTER);
duke@0 3752 %}
duke@0 3753
never@415 3754 operand rFlagsRegUCF() %{
never@415 3755 constraint(ALLOC_IN_RC(int_flags));
never@415 3756 match(RegFlags);
never@415 3757 predicate(false);
never@415 3758
never@415 3759 format %{ "RFLAGS_U_CF" %}
never@415 3760 interface(REG_INTER);
never@415 3761 %}
never@415 3762
duke@0 3763 // Float register operands
duke@0 3764 operand regF()
duke@0 3765 %{
duke@0 3766 constraint(ALLOC_IN_RC(float_reg));
duke@0 3767 match(RegF);
duke@0 3768
duke@0 3769 format %{ %}
duke@0 3770 interface(REG_INTER);
duke@0 3771 %}
duke@0 3772
duke@0 3773 // Double register operands
iveresov@2251 3774 operand regD()
duke@0 3775 %{
duke@0 3776 constraint(ALLOC_IN_RC(double_reg));
duke@0 3777 match(RegD);
duke@0 3778
duke@0 3779 format %{ %}
duke@0 3780 interface(REG_INTER);
duke@0 3781 %}
duke@0 3782
duke@0 3783 //----------Memory Operands----------------------------------------------------
duke@0 3784 // Direct Memory Operand
duke@0 3785 // operand direct(immP addr)
duke@0 3786 // %{
duke@0 3787 // match(addr);
duke@0 3788
duke@0 3789 // format %{ "[$addr]" %}
duke@0 3790 // interface(MEMORY_INTER) %{
duke@0 3791 // base(0xFFFFFFFF);
duke@0 3792 // index(0x4);
duke@0 3793 // scale(0x0);
duke@0 3794 // disp($addr);
duke@0 3795 // %}
duke@0 3796 // %}
duke@0 3797
duke@0 3798 // Indirect Memory Operand
duke@0 3799 operand indirect(any_RegP reg)
duke@0 3800 %{
duke@0 3801 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3802 match(reg);
duke@0 3803
duke@0 3804 format %{ "[$reg]" %}
duke@0 3805 interface(MEMORY_INTER) %{
duke@0 3806 base($reg);
duke@0 3807 index(0x4);
duke@0 3808 scale(0x0);
duke@0 3809 disp(0x0);
duke@0 3810 %}
duke@0 3811 %}
duke@0 3812
duke@0 3813 // Indirect Memory Plus Short Offset Operand
duke@0 3814 operand indOffset8(any_RegP reg, immL8 off)
duke@0 3815 %{
duke@0 3816 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3817 match(AddP reg off);
duke@0 3818
duke@0 3819 format %{ "[$reg + $off (8-bit)]" %}
duke@0 3820 interface(MEMORY_INTER) %{
duke@0 3821 base($reg);
duke@0 3822 index(0x4);
duke@0 3823 scale(0x0);
duke@0 3824 disp($off);
duke@0 3825 %}
duke@0 3826 %}
duke@0 3827
duke@0 3828 // Indirect Memory Plus Long Offset Operand
duke@0 3829 operand indOffset32(any_RegP reg, immL32 off)
duke@0 3830 %{
duke@0 3831 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3832 match(AddP reg off);
duke@0 3833
duke@0 3834 format %{ "[$reg + $off (32-bit)]" %}
duke@0 3835 interface(MEMORY_INTER) %{
duke@0 3836 base($reg);
duke@0 3837 index(0x4);
duke@0 3838 scale(0x0);
duke@0 3839 disp($off);
duke@0 3840 %}
duke@0 3841 %}
duke@0 3842
duke@0 3843 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3844 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
duke@0 3845 %{
duke@0 3846 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3847 match(AddP (AddP reg lreg) off);
duke@0 3848
duke@0 3849 op_cost(10);
duke@0 3850 format %{"[$reg + $off + $lreg]" %}
duke@0 3851 interface(MEMORY_INTER) %{
duke@0 3852 base($reg);
duke@0 3853 index($lreg);
duke@0 3854 scale(0x0);
duke@0 3855 disp($off);
duke@0 3856 %}
duke@0 3857 %}
duke@0 3858
duke@0 3859 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3860 operand indIndex(any_RegP reg, rRegL lreg)
duke@0 3861 %{
duke@0 3862 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3863 match(AddP reg lreg);
duke@0 3864
duke@0 3865 op_cost(10);
duke@0 3866 format %{"[$reg + $lreg]" %}