annotate src/cpu/x86/vm/x86_64.ad @ 10004:c8b709902e0e

8145322: Code generated from unsafe loops can be slightly improved Summary: improve code generated from checkIndex and unsafe loops Reviewed-by: kvn, thartmann
author roland
date Mon, 11 Jan 2016 16:33:27 +0100
parents 13b04370e8e9
children 8b9fdaeb8c57
rev   line source
duke@0 1 //
psandoz@7844 2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // Specify priority of register selection within phases of register
duke@0 135 // allocation. Highest priority is first. A useful heuristic is to
duke@0 136 // give registers a low priority when they are required by machine
duke@0 137 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 138 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 139 // which participate in fixed calling sequences should come last.
duke@0 140 // Registers which are used as pairs must fall on an even boundary.
duke@0 141
duke@0 142 alloc_class chunk0(R10, R10_H,
duke@0 143 R11, R11_H,
duke@0 144 R8, R8_H,
duke@0 145 R9, R9_H,
duke@0 146 R12, R12_H,
duke@0 147 RCX, RCX_H,
duke@0 148 RBX, RBX_H,
duke@0 149 RDI, RDI_H,
duke@0 150 RDX, RDX_H,
duke@0 151 RSI, RSI_H,
duke@0 152 RAX, RAX_H,
duke@0 153 RBP, RBP_H,
duke@0 154 R13, R13_H,
duke@0 155 R14, R14_H,
duke@0 156 R15, R15_H,
duke@0 157 RSP, RSP_H);
duke@0 158
duke@0 159
duke@0 160 //----------Architecture Description Register Classes--------------------------
duke@0 161 // Several register classes are automatically defined based upon information in
duke@0 162 // this architecture description.
duke@0 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 167 //
duke@0 168
zmajo@8290 169 // Empty register class.
zmajo@8290 170 reg_class no_reg();
zmajo@8290 171
zmajo@8290 172 // Class for all pointer registers (including RSP and RBP)
zmajo@8290 173 reg_class any_reg_with_rbp(RAX, RAX_H,
zmajo@8290 174 RDX, RDX_H,
kvn@8379 175 RBP, RBP_H,
zmajo@8290 176 RDI, RDI_H,
zmajo@8290 177 RSI, RSI_H,
zmajo@8290 178 RCX, RCX_H,
zmajo@8290 179 RBX, RBX_H,
zmajo@8290 180 RSP, RSP_H,
zmajo@8290 181 R8, R8_H,
zmajo@8290 182 R9, R9_H,
zmajo@8290 183 R10, R10_H,
zmajo@8290 184 R11, R11_H,
zmajo@8290 185 R12, R12_H,
zmajo@8290 186 R13, R13_H,
zmajo@8290 187 R14, R14_H,
zmajo@8290 188 R15, R15_H);
zmajo@8290 189
zmajo@8290 190 // Class for all pointer registers (including RSP, but excluding RBP)
zmajo@8290 191 reg_class any_reg_no_rbp(RAX, RAX_H,
kvn@8379 192 RDX, RDX_H,
zmajo@8290 193 RDI, RDI_H,
zmajo@8290 194 RSI, RSI_H,
zmajo@8290 195 RCX, RCX_H,
zmajo@8290 196 RBX, RBX_H,
zmajo@8290 197 RSP, RSP_H,
zmajo@8290 198 R8, R8_H,
zmajo@8290 199 R9, R9_H,
zmajo@8290 200 R10, R10_H,
zmajo@8290 201 R11, R11_H,
zmajo@8290 202 R12, R12_H,
zmajo@8290 203 R13, R13_H,
zmajo@8290 204 R14, R14_H,
zmajo@8290 205 R15, R15_H);
zmajo@8290 206
zmajo@8290 207 // Dynamic register class that selects at runtime between register classes
kvn@8379 208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
zmajo@8290 209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
zmajo@8290 210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
kvn@8379 211
zmajo@8290 212 // Class for all pointer registers (excluding RSP)
zmajo@8290 213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
zmajo@8290 214 RDX, RDX_H,
zmajo@8290 215 RBP, RBP_H,
zmajo@8290 216 RDI, RDI_H,
zmajo@8290 217 RSI, RSI_H,
zmajo@8290 218 RCX, RCX_H,
zmajo@8290 219 RBX, RBX_H,
zmajo@8290 220 R8, R8_H,
zmajo@8290 221 R9, R9_H,
zmajo@8290 222 R10, R10_H,
zmajo@8290 223 R11, R11_H,
zmajo@8290 224 R13, R13_H,
zmajo@8290 225 R14, R14_H);
zmajo@8290 226
zmajo@8290 227 // Class for all pointer registers (excluding RSP and RBP)
zmajo@8290 228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
kvn@8379 229 RDX, RDX_H,
duke@0 230 RDI, RDI_H,
duke@0 231 RSI, RSI_H,
duke@0 232 RCX, RCX_H,
duke@0 233 RBX, RBX_H,
duke@0 234 R8, R8_H,
duke@0 235 R9, R9_H,
duke@0 236 R10, R10_H,
duke@0 237 R11, R11_H,
duke@0 238 R13, R13_H,
duke@0 239 R14, R14_H);
duke@0 240
zmajo@8290 241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
zmajo@8290 242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 243
zmajo@8290 244 // Class for all pointer registers (excluding RAX and RSP)
zmajo@8290 245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
zmajo@8290 246 RBP, RBP_H,
zmajo@8290 247 RDI, RDI_H,
zmajo@8290 248 RSI, RSI_H,
zmajo@8290 249 RCX, RCX_H,
zmajo@8290 250 RBX, RBX_H,
zmajo@8290 251 R8, R8_H,
zmajo@8290 252 R9, R9_H,
zmajo@8290 253 R10, R10_H,
zmajo@8290 254 R11, R11_H,
zmajo@8290 255 R13, R13_H,
zmajo@8290 256 R14, R14_H);
zmajo@8290 257
zmajo@8290 258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
zmajo@8290 259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
zmajo@8290 260 RDI, RDI_H,
zmajo@8290 261 RSI, RSI_H,
zmajo@8290 262 RCX, RCX_H,
zmajo@8290 263 RBX, RBX_H,
zmajo@8290 264 R8, R8_H,
zmajo@8290 265 R9, R9_H,
zmajo@8290 266 R10, R10_H,
zmajo@8290 267 R11, R11_H,
zmajo@8290 268 R13, R13_H,
zmajo@8290 269 R14, R14_H);
zmajo@8290 270
zmajo@8290 271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
zmajo@8290 272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 273
zmajo@8290 274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
zmajo@8290 275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
zmajo@8290 276 RBP, RBP_H,
zmajo@8290 277 RDI, RDI_H,
zmajo@8290 278 RSI, RSI_H,
zmajo@8290 279 RCX, RCX_H,
zmajo@8290 280 R8, R8_H,
zmajo@8290 281 R9, R9_H,
zmajo@8290 282 R10, R10_H,
zmajo@8290 283 R11, R11_H,
zmajo@8290 284 R13, R13_H,
zmajo@8290 285 R14, R14_H);
zmajo@8290 286
zmajo@8290 287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
zmajo@8290 288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
zmajo@8290 289 RDI, RDI_H,
zmajo@8290 290 RSI, RSI_H,
zmajo@8290 291 RCX, RCX_H,
zmajo@8290 292 R8, R8_H,
zmajo@8290 293 R9, R9_H,
zmajo@8290 294 R10, R10_H,
zmajo@8290 295 R11, R11_H,
zmajo@8290 296 R13, R13_H,
zmajo@8290 297 R14, R14_H);
zmajo@8290 298
zmajo@8290 299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
zmajo@8290 300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
duke@0 301
duke@0 302 // Singleton class for RAX pointer register
duke@0 303 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 304
duke@0 305 // Singleton class for RBX pointer register
duke@0 306 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 307
duke@0 308 // Singleton class for RSI pointer register
duke@0 309 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 310
duke@0 311 // Singleton class for RDI pointer register
duke@0 312 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 313
duke@0 314 // Singleton class for stack pointer
duke@0 315 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 316
duke@0 317 // Singleton class for TLS pointer
duke@0 318 reg_class ptr_r15_reg(R15, R15_H);
duke@0 319
zmajo@8290 320 // Class for all long registers (excluding RSP)
zmajo@8290 321 reg_class long_reg_with_rbp(RAX, RAX_H,
zmajo@8290 322 RDX, RDX_H,
zmajo@8290 323 RBP, RBP_H,
zmajo@8290 324 RDI, RDI_H,
zmajo@8290 325 RSI, RSI_H,
zmajo@8290 326 RCX, RCX_H,
zmajo@8290 327 RBX, RBX_H,
zmajo@8290 328 R8, R8_H,
zmajo@8290 329 R9, R9_H,
zmajo@8290 330 R10, R10_H,
zmajo@8290 331 R11, R11_H,
zmajo@8290 332 R13, R13_H,
zmajo@8290 333 R14, R14_H);
zmajo@8290 334
zmajo@8290 335 // Class for all long registers (excluding RSP and RBP)
zmajo@8290 336 reg_class long_reg_no_rbp(RAX, RAX_H,
duke@0 337 RDX, RDX_H,
duke@0 338 RDI, RDI_H,
duke@0 339 RSI, RSI_H,
duke@0 340 RCX, RCX_H,
duke@0 341 RBX, RBX_H,
duke@0 342 R8, R8_H,
duke@0 343 R9, R9_H,
duke@0 344 R10, R10_H,
duke@0 345 R11, R11_H,
duke@0 346 R13, R13_H,
duke@0 347 R14, R14_H);
duke@0 348
zmajo@8290 349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
zmajo@8290 350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 351
zmajo@8290 352 // Class for all long registers (excluding RAX, RDX and RSP)
zmajo@8290 353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
zmajo@8290 354 RDI, RDI_H,
zmajo@8290 355 RSI, RSI_H,
zmajo@8290 356 RCX, RCX_H,
zmajo@8290 357 RBX, RBX_H,
zmajo@8290 358 R8, R8_H,
zmajo@8290 359 R9, R9_H,
zmajo@8290 360 R10, R10_H,
zmajo@8290 361 R11, R11_H,
zmajo@8290 362 R13, R13_H,
zmajo@8290 363 R14, R14_H);
zmajo@8290 364
zmajo@8290 365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
zmajo@8290 366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
zmajo@8290 367 RSI, RSI_H,
zmajo@8290 368 RCX, RCX_H,
zmajo@8290 369 RBX, RBX_H,
zmajo@8290 370 R8, R8_H,
zmajo@8290 371 R9, R9_H,
zmajo@8290 372 R10, R10_H,
zmajo@8290 373 R11, R11_H,
zmajo@8290 374 R13, R13_H,
zmajo@8290 375 R14, R14_H);
zmajo@8290 376
zmajo@8290 377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
zmajo@8290 378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 379
zmajo@8290 380 // Class for all long registers (excluding RCX and RSP)
zmajo@8290 381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
zmajo@8290 382 RDI, RDI_H,
zmajo@8290 383 RSI, RSI_H,
zmajo@8290 384 RAX, RAX_H,
zmajo@8290 385 RDX, RDX_H,
zmajo@8290 386 RBX, RBX_H,
zmajo@8290 387 R8, R8_H,
zmajo@8290 388 R9, R9_H,
zmajo@8290 389 R10, R10_H,
zmajo@8290 390 R11, R11_H,
zmajo@8290 391 R13, R13_H,
zmajo@8290 392 R14, R14_H);
zmajo@8290 393
zmajo@8290 394 // Class for all long registers (excluding RCX, RSP, and RBP)
zmajo@8290 395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
zmajo@8290 396 RSI, RSI_H,
zmajo@8290 397 RAX, RAX_H,
zmajo@8290 398 RDX, RDX_H,
zmajo@8290 399 RBX, RBX_H,
zmajo@8290 400 R8, R8_H,
zmajo@8290 401 R9, R9_H,
zmajo@8290 402 R10, R10_H,
zmajo@8290 403 R11, R11_H,
zmajo@8290 404 R13, R13_H,
zmajo@8290 405 R14, R14_H);
zmajo@8290 406
zmajo@8290 407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
zmajo@8290 408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 409
duke@0 410 // Singleton class for RAX long register
duke@0 411 reg_class long_rax_reg(RAX, RAX_H);
duke@0 412
duke@0 413 // Singleton class for RCX long register
duke@0 414 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 415
duke@0 416 // Singleton class for RDX long register
duke@0 417 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 418
zmajo@8290 419 // Class for all int registers (excluding RSP)
zmajo@8290 420 reg_class int_reg_with_rbp(RAX,
zmajo@8290 421 RDX,
zmajo@8290 422 RBP,
zmajo@8290 423 RDI,
zmajo@8290 424 RSI,
zmajo@8290 425 RCX,
zmajo@8290 426 RBX,
zmajo@8290 427 R8,
zmajo@8290 428 R9,
zmajo@8290 429 R10,
zmajo@8290 430 R11,
zmajo@8290 431 R13,
zmajo@8290 432 R14);
zmajo@8290 433
zmajo@8290 434 // Class for all int registers (excluding RSP and RBP)
zmajo@8290 435 reg_class int_reg_no_rbp(RAX,
duke@0 436 RDX,
duke@0 437 RDI,
duke@0 438 RSI,
zmajo@8290 439 RCX,
duke@0 440 RBX,
duke@0 441 R8,
duke@0 442 R9,
duke@0 443 R10,
duke@0 444 R11,
duke@0 445 R13,
duke@0 446 R14);
duke@0 447
zmajo@8290 448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
zmajo@8290 449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 450
zmajo@8290 451 // Class for all int registers (excluding RCX and RSP)
zmajo@8290 452 reg_class int_no_rcx_reg_with_rbp(RAX,
zmajo@8290 453 RDX,
zmajo@8290 454 RBP,
zmajo@8290 455 RDI,
zmajo@8290 456 RSI,
zmajo@8290 457 RBX,
zmajo@8290 458 R8,
zmajo@8290 459 R9,
zmajo@8290 460 R10,
zmajo@8290 461 R11,
zmajo@8290 462 R13,
zmajo@8290 463 R14);
zmajo@8290 464
zmajo@8290 465 // Class for all int registers (excluding RCX, RSP, and RBP)
zmajo@8290 466 reg_class int_no_rcx_reg_no_rbp(RAX,
zmajo@8290 467 RDX,
zmajo@8290 468 RDI,
zmajo@8290 469 RSI,
zmajo@8290 470 RBX,
zmajo@8290 471 R8,
zmajo@8290 472 R9,
zmajo@8290 473 R10,
zmajo@8290 474 R11,
zmajo@8290 475 R13,
zmajo@8290 476 R14);
zmajo@8290 477
zmajo@8290 478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
zmajo@8290 479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
zmajo@8290 480
zmajo@8290 481 // Class for all int registers (excluding RAX, RDX, and RSP)
zmajo@8290 482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
zmajo@8290 483 RDI,
zmajo@8290 484 RSI,
zmajo@8290 485 RCX,
zmajo@8290 486 RBX,
zmajo@8290 487 R8,
zmajo@8290 488 R9,
zmajo@8290 489 R10,
zmajo@8290 490 R11,
zmajo@8290 491 R13,
zmajo@8290 492 R14);
zmajo@8290 493
zmajo@8290 494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
zmajo@8290 495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
zmajo@8290 496 RSI,
zmajo@8290 497 RCX,
zmajo@8290 498 RBX,
zmajo@8290 499 R8,
zmajo@8290 500 R9,
zmajo@8290 501 R10,
zmajo@8290 502 R11,
zmajo@8290 503 R13,
zmajo@8290 504 R14);
zmajo@8290 505
zmajo@8290 506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
zmajo@8290 507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
duke@0 508
duke@0 509 // Singleton class for RAX int register
duke@0 510 reg_class int_rax_reg(RAX);
duke@0 511
duke@0 512 // Singleton class for RBX int register
duke@0 513 reg_class int_rbx_reg(RBX);
duke@0 514
duke@0 515 // Singleton class for RCX int register
duke@0 516 reg_class int_rcx_reg(RCX);
duke@0 517
duke@0 518 // Singleton class for RCX int register
duke@0 519 reg_class int_rdx_reg(RDX);
duke@0 520
duke@0 521 // Singleton class for RCX int register
duke@0 522 reg_class int_rdi_reg(RDI);
duke@0 523
duke@0 524 // Singleton class for instruction pointer
duke@0 525 // reg_class ip_reg(RIP);
duke@0 526
kvn@3447 527 %}
duke@0 528
duke@0 529 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 530 // This is a block of C++ code which provides values, functions, and
duke@0 531 // definitions necessary in the rest of the architecture description
duke@0 532 source %{
never@304 533 #define RELOC_IMM64 Assembler::imm_operand
duke@0 534 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 535
duke@0 536 #define __ _masm.
duke@0 537
kvn@4438 538 static int clear_avx_size() {
iveresov@9450 539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
kvn@4438 540 }
twisti@1137 541
duke@0 542 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 543 // from the start of the call to the point where the return address
duke@0 544 // will point.
duke@0 545 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 546 {
twisti@1137 547 int offset = 5; // 5 bytes from start of call to where return address points
kvn@8379 548 offset += clear_avx_size();
twisti@1137 549 return offset;
duke@0 550 }
duke@0 551
duke@0 552 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 553 {
kvn@4438 554 int offset = 15; // 15 bytes from start of call to where return address points
kvn@4438 555 offset += clear_avx_size();
kvn@4438 556 return offset;
duke@0 557 }
duke@0 558
kvn@4438 559 int MachCallRuntimeNode::ret_addr_offset() {
kvn@4438 560 int offset = 13; // movq r10,#addr; callq (r10)
kvn@4438 561 offset += clear_avx_size();
kvn@4438 562 return offset;
kvn@4438 563 }
duke@0 564
iveresov@2251 565 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 566 // it does if the polling page is more than disp32 away.
duke@0 567 bool SafePointNode::needs_polling_address_input()
duke@0 568 {
iveresov@2251 569 return Assembler::is_polling_page_far();
duke@0 570 }
duke@0 571
duke@0 572 //
duke@0 573 // Compute padding required for nodes which need alignment
duke@0 574 //
duke@0 575
duke@0 576 // The address of the call instruction needs to be 4-byte aligned to
duke@0 577 // ensure that it does not span a cache line so that it can be patched.
duke@0 578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 579 {
kvn@4438 580 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 581 current_offset += 1; // skip call opcode byte
duke@0 582 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 583 }
duke@0 584
duke@0 585 // The address of the call instruction needs to be 4-byte aligned to
duke@0 586 // ensure that it does not span a cache line so that it can be patched.
duke@0 587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 588 {
kvn@4438 589 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 590 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 591 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 592 }
duke@0 593
duke@0 594 // EMIT_RM()
twisti@1668 595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 597 cbuf.insts()->emit_int8(c);
duke@0 598 }
duke@0 599
duke@0 600 // EMIT_CC()
twisti@1668 601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 602 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 603 cbuf.insts()->emit_int8(c);
duke@0 604 }
duke@0 605
duke@0 606 // EMIT_OPCODE()
twisti@1668 607 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 608 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 609 }
duke@0 610
duke@0 611 // EMIT_OPCODE() w/ relocation information
duke@0 612 void emit_opcode(CodeBuffer &cbuf,
duke@0 613 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 614 {
twisti@1668 615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 616 emit_opcode(cbuf, code);
duke@0 617 }
duke@0 618
duke@0 619 // EMIT_D8()
twisti@1668 620 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 621 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 622 }
duke@0 623
duke@0 624 // EMIT_D16()
twisti@1668 625 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 626 cbuf.insts()->emit_int16(d16);
duke@0 627 }
duke@0 628
duke@0 629 // EMIT_D32()
twisti@1668 630 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 631 cbuf.insts()->emit_int32(d32);
duke@0 632 }
duke@0 633
duke@0 634 // EMIT_D64()
twisti@1668 635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 636 cbuf.insts()->emit_int64(d64);
duke@0 637 }
duke@0 638
duke@0 639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 640 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 641 int d32,
duke@0 642 relocInfo::relocType reloc,
duke@0 643 int format)
duke@0 644 {
duke@0 645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 647 cbuf.insts()->emit_int32(d32);
duke@0 648 }
duke@0 649
duke@0 650 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 652 #ifdef ASSERT
duke@0 653 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
coleenp@3602 655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
hseigel@5349 656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 657 }
duke@0 658 #endif
twisti@1668 659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 660 cbuf.insts()->emit_int32(d32);
duke@0 661 }
duke@0 662
duke@0 663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 664 address next_ip = cbuf.insts_end() + 4;
duke@0 665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 666 external_word_Relocation::spec(addr),
duke@0 667 RELOC_DISP32);
duke@0 668 }
duke@0 669
duke@0 670
duke@0 671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 674 cbuf.insts()->emit_int64(d64);
duke@0 675 }
duke@0 676
duke@0 677 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 679 #ifdef ASSERT
duke@0 680 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
coleenp@3602 682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
hseigel@5349 683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
jrose@989 684 "cannot embed scavengable oops in code");
duke@0 685 }
duke@0 686 #endif
twisti@1668 687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 688 cbuf.insts()->emit_int64(d64);
duke@0 689 }
duke@0 690
duke@0 691 // Access stack slot for load or store
duke@0 692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 693 {
duke@0 694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 695 if (-0x80 <= disp && disp < 0x80) {
duke@0 696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 698 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 699 } else {
duke@0 700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 702 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 703 }
duke@0 704 }
duke@0 705
duke@0 706 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 707 void encode_RegMem(CodeBuffer &cbuf,
duke@0 708 int reg,
coleenp@3602 709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
duke@0 710 {
coleenp@3602 711 assert(disp_reloc == relocInfo::none, "cannot have disp");
duke@0 712 int regenc = reg & 7;
duke@0 713 int baseenc = base & 7;
duke@0 714 int indexenc = index & 7;
duke@0 715
duke@0 716 // There is no index & no scale, use form without SIB byte
duke@0 717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
coleenp@3602 721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 722 // If 8-bit displacement, mode 0x1
duke@0 723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 724 emit_d8(cbuf, disp);
duke@0 725 } else {
duke@0 726 // If 32-bit displacement
duke@0 727 if (base == -1) { // Special flag for absolute address
duke@0 728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
coleenp@3602 729 if (disp_reloc != relocInfo::none) {
duke@0 730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 731 } else {
duke@0 732 emit_d32(cbuf, disp);
duke@0 733 }
duke@0 734 } else {
duke@0 735 // Normal base + offset
duke@0 736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
coleenp@3602 737 if (disp_reloc != relocInfo::none) {
duke@0 738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 739 } else {
duke@0 740 emit_d32(cbuf, disp);
duke@0 741 }
duke@0 742 }
duke@0 743 }
duke@0 744 } else {
duke@0 745 // Else, encode with the SIB byte
duke@0 746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 748 // If no displacement
duke@0 749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 750 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 751 } else {
coleenp@3602 752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 753 // If 8-bit displacement, mode 0x1
duke@0 754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 755 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 756 emit_d8(cbuf, disp);
duke@0 757 } else {
duke@0 758 // If 32-bit displacement
duke@0 759 if (base == 0x04 ) {
duke@0 760 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 762 } else {
duke@0 763 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 764 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 765 }
coleenp@3602 766 if (disp_reloc != relocInfo::none) {
duke@0 767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 768 } else {
duke@0 769 emit_d32(cbuf, disp);
duke@0 770 }
duke@0 771 }
duke@0 772 }
duke@0 773 }
duke@0 774 }
duke@0 775
never@2545 776 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 778 Label exit;
never@2545 779 __ jccb(Assembler::noParity, exit);
never@2545 780 __ pushf();
kvn@2953 781 //
kvn@2953 782 // comiss/ucomiss instructions set ZF,PF,CF flags and
kvn@2953 783 // zero OF,AF,SF for NaN values.
kvn@2953 784 // Fixup flags by zeroing ZF,PF so that compare of NaN
kvn@2953 785 // values returns 'less than' result (CF is set).
kvn@2953 786 // Leave the rest of flags unchanged.
kvn@2953 787 //
kvn@2953 788 // 7 6 5 4 3 2 1 0
kvn@2953 789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
kvn@2953 790 // 0 0 1 0 1 0 1 1 (0x2B)
kvn@2953 791 //
never@2545 792 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 793 __ popf();
never@2545 794 __ bind(exit);
kvn@2953 795 }
kvn@2953 796
kvn@2953 797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
kvn@2953 798 Label done;
kvn@2953 799 __ movl(dst, -1);
kvn@2953 800 __ jcc(Assembler::parity, done);
kvn@2953 801 __ jcc(Assembler::below, done);
kvn@2953 802 __ setb(Assembler::notEqual, dst);
kvn@2953 803 __ movzbl(dst, dst);
kvn@2953 804 __ bind(done);
never@2545 805 }
never@2545 806
duke@0 807
duke@0 808 //=============================================================================
twisti@1915 809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 810
twisti@2875 811 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 812 return 0; // absolute addressing, no offset
twisti@2875 813 }
twisti@2875 814
goetz@5982 815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
goetz@5982 816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
goetz@5982 817 ShouldNotReachHere();
goetz@5982 818 }
goetz@5982 819
twisti@1915 820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 821 // Empty encoding
twisti@1915 822 }
twisti@1915 823
twisti@1915 824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 825 return 0;
twisti@1915 826 }
twisti@1915 827
twisti@1915 828 #ifndef PRODUCT
twisti@1915 829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 830 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 831 }
twisti@1915 832 #endif
twisti@1915 833
twisti@1915 834
twisti@1915 835 //=============================================================================
duke@0 836 #ifndef PRODUCT
kvn@3139 837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
duke@0 838 Compile* C = ra_->C;
duke@0 839
roland@6307 840 int framesize = C->frame_size_in_bytes();
roland@6307 841 int bangsize = C->bang_size_in_bytes();
duke@0 842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
kvn@3139 843 // Remove wordSize for return addr which is already pushed.
kvn@3139 844 framesize -= wordSize;
kvn@3139 845
roland@6307 846 if (C->need_stack_bang(bangsize)) {
kvn@3139 847 framesize -= wordSize;
roland@6307 848 st->print("# stack bang (%d bytes)", bangsize);
kvn@3139 849 st->print("\n\t");
kvn@3139 850 st->print("pushq rbp\t# Save rbp");
zmajo@8290 851 if (PreserveFramePointer) {
zmajo@8290 852 st->print("\n\t");
zmajo@8290 853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
zmajo@8290 854 }
kvn@3139 855 if (framesize) {
kvn@3139 856 st->print("\n\t");
kvn@3139 857 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 858 }
kvn@3139 859 } else {
kvn@3139 860 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 861 st->print("\n\t");
kvn@3139 862 framesize -= wordSize;
kvn@8379 863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
zmajo@8290 864 if (PreserveFramePointer) {
zmajo@8290 865 st->print("\n\t");
zmajo@9139 866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
zmajo@9139 867 if (framesize > 0) {
zmajo@9139 868 st->print("\n\t");
zmajo@9139 869 st->print("addq rbp, #%d", framesize);
iveresov@9450 870 }
zmajo@8290 871 }
duke@0 872 }
duke@0 873
duke@0 874 if (VerifyStackAtCalls) {
kvn@3139 875 st->print("\n\t");
kvn@3139 876 framesize -= wordSize;
kvn@3139 877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
kvn@3139 878 #ifdef ASSERT
kvn@3139 879 st->print("\n\t");
kvn@3139 880 st->print("# stack alignment check");
kvn@3139 881 #endif
duke@0 882 }
kvn@3139 883 st->cr();
duke@0 884 }
duke@0 885 #endif
duke@0 886
kvn@3139 887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 888 Compile* C = ra_->C;
kvn@3139 889 MacroAssembler _masm(&cbuf);
duke@0 890
roland@6307 891 int framesize = C->frame_size_in_bytes();
roland@6307 892 int bangsize = C->bang_size_in_bytes();
roland@6307 893
roland@6307 894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
duke@0 895
twisti@1668 896 C->set_frame_complete(cbuf.insts_size());
duke@0 897
twisti@2875 898 if (C->has_mach_constant_base_node()) {
twisti@2875 899 // NOTE: We set the table base offset here because users might be
twisti@2875 900 // emitted before MachConstantBaseNode.
twisti@2875 901 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 903 }
duke@0 904 }
duke@0 905
duke@0 906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 907 {
duke@0 908 return MachNode::size(ra_); // too many variables; just compute it
duke@0 909 // the hard way
duke@0 910 }
duke@0 911
duke@0 912 int MachPrologNode::reloc() const
duke@0 913 {
duke@0 914 return 0; // a large enough number
duke@0 915 }
duke@0 916
duke@0 917 //=============================================================================
duke@0 918 #ifndef PRODUCT
duke@0 919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 920 {
duke@0 921 Compile* C = ra_->C;
kvn@4438 922 if (C->max_vector_size() > 16) {
kvn@4438 923 st->print("vzeroupper");
kvn@4438 924 st->cr(); st->print("\t");
kvn@4438 925 }
kvn@4438 926
roland@6307 927 int framesize = C->frame_size_in_bytes();
duke@0 928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 929 // Remove word for return adr already pushed
duke@0 930 // and RBP
duke@0 931 framesize -= 2*wordSize;
duke@0 932
duke@0 933 if (framesize) {
iveresov@2251 934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 935 st->print("\t");
duke@0 936 }
duke@0 937
iveresov@2251 938 st->print_cr("popq rbp");
duke@0 939 if (do_polling() && C->is_method_compilation()) {
duke@0 940 st->print("\t");
iveresov@2251 941 if (Assembler::is_polling_page_far()) {
iveresov@2251 942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 943 "testl rax, [rscratch1]\t"
iveresov@2251 944 "# Safepoint: poll for GC");
iveresov@2251 945 } else {
iveresov@2251 946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 947 "# Safepoint: poll for GC");
iveresov@2251 948 }
duke@0 949 }
duke@0 950 }
duke@0 951 #endif
duke@0 952
duke@0 953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 954 {
duke@0 955 Compile* C = ra_->C;
fparain@9737 956 MacroAssembler _masm(&cbuf);
fparain@9737 957
kvn@4438 958 if (C->max_vector_size() > 16) {
kvn@4438 959 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 960 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 961 __ vzeroupper();
kvn@4438 962 }
kvn@4438 963
roland@6307 964 int framesize = C->frame_size_in_bytes();
duke@0 965 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 966 // Remove word for return adr already pushed
duke@0 967 // and RBP
duke@0 968 framesize -= 2*wordSize;
duke@0 969
duke@0 970 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 971
duke@0 972 if (framesize) {
duke@0 973 emit_opcode(cbuf, Assembler::REX_W);
duke@0 974 if (framesize < 0x80) {
duke@0 975 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 976 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 977 emit_d8(cbuf, framesize);
duke@0 978 } else {
duke@0 979 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 981 emit_d32(cbuf, framesize);
duke@0 982 }
duke@0 983 }
duke@0 984
duke@0 985 // popq rbp
duke@0 986 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 987
fparain@9737 988 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
fparain@9737 989 __ reserved_stack_check();
fparain@9737 990 }
fparain@9737 991
duke@0 992 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 993 MacroAssembler _masm(&cbuf);
iveresov@2251 994 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 995 if (Assembler::is_polling_page_far()) {
iveresov@2251 996 __ lea(rscratch1, polling_page);
iveresov@2251 997 __ relocate(relocInfo::poll_return_type);
iveresov@2251 998 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 999 } else {
iveresov@2251 1000 __ testl(rax, polling_page);
iveresov@2251 1001 }
duke@0 1002 }
duke@0 1003 }
duke@0 1004
duke@0 1005 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 1006 {
iveresov@2251 1007 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 1008 // the hard way
duke@0 1009 }
duke@0 1010
duke@0 1011 int MachEpilogNode::reloc() const
duke@0 1012 {
duke@0 1013 return 2; // a large enough number
duke@0 1014 }
duke@0 1015
duke@0 1016 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1017 {
duke@0 1018 return MachNode::pipeline_class();
duke@0 1019 }
duke@0 1020
duke@0 1021 int MachEpilogNode::safepoint_offset() const
duke@0 1022 {
duke@0 1023 return 0;
duke@0 1024 }
duke@0 1025
duke@0 1026 //=============================================================================
duke@0 1027
duke@0 1028 enum RC {
duke@0 1029 rc_bad,
duke@0 1030 rc_int,
duke@0 1031 rc_float,
duke@0 1032 rc_stack
duke@0 1033 };
duke@0 1034
duke@0 1035 static enum RC rc_class(OptoReg::Name reg)
duke@0 1036 {
duke@0 1037 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1038
duke@0 1039 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1040
duke@0 1041 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1042
duke@0 1043 if (r->is_Register()) return rc_int;
duke@0 1044
duke@0 1045 assert(r->is_XMMRegister(), "must be");
duke@0 1046 return rc_float;
duke@0 1047 }
duke@0 1048
kvn@3447 1049 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
kvn@3447 1050 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
kvn@3447 1051 int src_hi, int dst_hi, uint ireg, outputStream* st);
kvn@3447 1052
kvn@3447 1053 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
kvn@3447 1054 int stack_offset, int reg, uint ireg, outputStream* st);
kvn@3447 1055
kvn@3447 1056 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
kvn@3447 1057 int dst_offset, uint ireg, outputStream* st) {
kvn@3447 1058 if (cbuf) {
kvn@3447 1059 MacroAssembler _masm(cbuf);
kvn@3447 1060 switch (ireg) {
kvn@3447 1061 case Op_VecS:
kvn@3447 1062 __ movq(Address(rsp, -8), rax);
kvn@3447 1063 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1064 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1065 __ movq(rax, Address(rsp, -8));
kvn@3447 1066 break;
kvn@3447 1067 case Op_VecD:
kvn@3447 1068 __ pushq(Address(rsp, src_offset));
kvn@3447 1069 __ popq (Address(rsp, dst_offset));
kvn@3447 1070 break;
kvn@3447 1071 case Op_VecX:
kvn@3447 1072 __ pushq(Address(rsp, src_offset));
kvn@3447 1073 __ popq (Address(rsp, dst_offset));
kvn@3447 1074 __ pushq(Address(rsp, src_offset+8));
kvn@3447 1075 __ popq (Address(rsp, dst_offset+8));
kvn@3447 1076 break;
kvn@3447 1077 case Op_VecY:
kvn@3447 1078 __ vmovdqu(Address(rsp, -32), xmm0);
kvn@3447 1079 __ vmovdqu(xmm0, Address(rsp, src_offset));
kvn@3447 1080 __ vmovdqu(Address(rsp, dst_offset), xmm0);
kvn@3447 1081 __ vmovdqu(xmm0, Address(rsp, -32));
roland@10004 1082 break;
kvn@8379 1083 case Op_VecZ:
mcberg@8965 1084 __ evmovdqul(Address(rsp, -64), xmm0, 2);
mcberg@8965 1085 __ evmovdqul(xmm0, Address(rsp, src_offset), 2);
mcberg@8965 1086 __ evmovdqul(Address(rsp, dst_offset), xmm0, 2);
mcberg@8965 1087 __ evmovdqul(xmm0, Address(rsp, -64), 2);
kvn@3447 1088 break;
kvn@3447 1089 default:
kvn@3447 1090 ShouldNotReachHere();
kvn@3447 1091 }
kvn@3447 1092 #ifndef PRODUCT
kvn@3447 1093 } else {
kvn@3447 1094 switch (ireg) {
kvn@3447 1095 case Op_VecS:
kvn@3447 1096 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1097 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1098 "movl [rsp + #%d], rax\n\t"
kvn@3447 1099 "movq rax, [rsp - #8]",
kvn@3447 1100 src_offset, dst_offset);
kvn@3447 1101 break;
kvn@3447 1102 case Op_VecD:
kvn@3447 1103 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1104 "popq [rsp + #%d]",
kvn@3447 1105 src_offset, dst_offset);
kvn@3447 1106 break;
kvn@3447 1107 case Op_VecX:
kvn@3447 1108 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
kvn@3447 1109 "popq [rsp + #%d]\n\t"
kvn@3447 1110 "pushq [rsp + #%d]\n\t"
kvn@3447 1111 "popq [rsp + #%d]",
kvn@3447 1112 src_offset, dst_offset, src_offset+8, dst_offset+8);
kvn@3447 1113 break;
kvn@3447 1114 case Op_VecY:
kvn@3447 1115 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
kvn@3447 1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@3447 1117 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@3447 1118 "vmovdqu xmm0, [rsp - #32]",
kvn@3447 1119 src_offset, dst_offset);
kvn@3447 1120 break;
kvn@8379 1121 case Op_VecZ:
kvn@8379 1122 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
kvn@8379 1123 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@8379 1124 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@8379 1125 "vmovdqu xmm0, [rsp - #64]",
kvn@8379 1126 src_offset, dst_offset);
kvn@8379 1127 break;
kvn@3447 1128 default:
kvn@3447 1129 ShouldNotReachHere();
kvn@3447 1130 }
kvn@3447 1131 #endif
kvn@3447 1132 }
kvn@3447 1133 }
kvn@3447 1134
duke@0 1135 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1136 PhaseRegAlloc* ra_,
duke@0 1137 bool do_size,
kvn@3447 1138 outputStream* st) const {
kvn@3447 1139 assert(cbuf != NULL || st != NULL, "sanity");
duke@0 1140 // Get registers to move
duke@0 1141 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1142 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1143 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1144 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1145
duke@0 1146 enum RC src_second_rc = rc_class(src_second);
duke@0 1147 enum RC src_first_rc = rc_class(src_first);
duke@0 1148 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1149 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1150
duke@0 1151 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1152 "must move at least 1 register" );
duke@0 1153
duke@0 1154 if (src_first == dst_first && src_second == dst_second) {
duke@0 1155 // Self copy, no move
duke@0 1156 return 0;
kvn@3447 1157 }
kvn@3447 1158 if (bottom_type()->isa_vect() != NULL) {
kvn@3447 1159 uint ireg = ideal_reg();
kvn@3447 1160 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
kvn@8379 1161 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
kvn@3447 1162 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
kvn@3447 1163 // mem -> mem
kvn@3447 1164 int src_offset = ra_->reg2offset(src_first);
kvn@3447 1165 int dst_offset = ra_->reg2offset(dst_first);
kvn@3447 1166 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
kvn@3447 1167 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
kvn@3447 1168 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
kvn@3447 1169 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
kvn@3447 1170 int stack_offset = ra_->reg2offset(dst_first);
kvn@3447 1171 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
kvn@3447 1172 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
kvn@3447 1173 int stack_offset = ra_->reg2offset(src_first);
kvn@3447 1174 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
kvn@3447 1175 } else {
kvn@3447 1176 ShouldNotReachHere();
kvn@3447 1177 }
kvn@3447 1178 return 0;
kvn@3447 1179 }
kvn@3447 1180 if (src_first_rc == rc_stack) {
duke@0 1181 // mem ->
duke@0 1182 if (dst_first_rc == rc_stack) {
duke@0 1183 // mem -> mem
duke@0 1184 assert(src_second != dst_first, "overlap");
duke@0 1185 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1186 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1187 // 64-bit
duke@0 1188 int src_offset = ra_->reg2offset(src_first);
duke@0 1189 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1190 if (cbuf) {
kvn@3447 1191 MacroAssembler _masm(cbuf);
kvn@3447 1192 __ pushq(Address(rsp, src_offset));
kvn@3447 1193 __ popq (Address(rsp, dst_offset));
duke@0 1194 #ifndef PRODUCT
kvn@3447 1195 } else {
duke@0 1196 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1197 "popq [rsp + #%d]",
kvn@3447 1198 src_offset, dst_offset);
duke@0 1199 #endif
duke@0 1200 }
duke@0 1201 } else {
duke@0 1202 // 32-bit
duke@0 1203 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1204 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1205 // No pushl/popl, so:
duke@0 1206 int src_offset = ra_->reg2offset(src_first);
duke@0 1207 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1208 if (cbuf) {
kvn@3447 1209 MacroAssembler _masm(cbuf);
kvn@3447 1210 __ movq(Address(rsp, -8), rax);
kvn@3447 1211 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1212 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1213 __ movq(rax, Address(rsp, -8));
duke@0 1214 #ifndef PRODUCT
kvn@3447 1215 } else {
duke@0 1216 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1217 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1218 "movl [rsp + #%d], rax\n\t"
kvn@3447 1219 "movq rax, [rsp - #8]",
kvn@3447 1220 src_offset, dst_offset);
duke@0 1221 #endif
duke@0 1222 }
duke@0 1223 }
kvn@3447 1224 return 0;
duke@0 1225 } else if (dst_first_rc == rc_int) {
duke@0 1226 // mem -> gpr
duke@0 1227 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1228 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1229 // 64-bit
duke@0 1230 int offset = ra_->reg2offset(src_first);
duke@0 1231 if (cbuf) {
kvn@3447 1232 MacroAssembler _masm(cbuf);
kvn@3447 1233 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1234 #ifndef PRODUCT
kvn@3447 1235 } else {
duke@0 1236 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1237 Matcher::regName[dst_first],
duke@0 1238 offset);
duke@0 1239 #endif
duke@0 1240 }
duke@0 1241 } else {
duke@0 1242 // 32-bit
duke@0 1243 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1244 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1245 int offset = ra_->reg2offset(src_first);
duke@0 1246 if (cbuf) {
kvn@3447 1247 MacroAssembler _masm(cbuf);
kvn@3447 1248 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1249 #ifndef PRODUCT
kvn@3447 1250 } else {
duke@0 1251 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1252 Matcher::regName[dst_first],
duke@0 1253 offset);
duke@0 1254 #endif
duke@0 1255 }
duke@0 1256 }
kvn@3447 1257 return 0;
duke@0 1258 } else if (dst_first_rc == rc_float) {
duke@0 1259 // mem-> xmm
duke@0 1260 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1261 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1262 // 64-bit
duke@0 1263 int offset = ra_->reg2offset(src_first);
duke@0 1264 if (cbuf) {
kvn@2953 1265 MacroAssembler _masm(cbuf);
kvn@2953 1266 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1267 #ifndef PRODUCT
kvn@3447 1268 } else {
duke@0 1269 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1270 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1271 Matcher::regName[dst_first],
duke@0 1272 offset);
duke@0 1273 #endif
duke@0 1274 }
duke@0 1275 } else {
duke@0 1276 // 32-bit
duke@0 1277 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1278 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1279 int offset = ra_->reg2offset(src_first);
duke@0 1280 if (cbuf) {
kvn@2953 1281 MacroAssembler _masm(cbuf);
kvn@2953 1282 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1283 #ifndef PRODUCT
kvn@3447 1284 } else {
duke@0 1285 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1286 Matcher::regName[dst_first],
duke@0 1287 offset);
duke@0 1288 #endif
duke@0 1289 }
duke@0 1290 }
kvn@3447 1291 return 0;
duke@0 1292 }
duke@0 1293 } else if (src_first_rc == rc_int) {
duke@0 1294 // gpr ->
duke@0 1295 if (dst_first_rc == rc_stack) {
duke@0 1296 // gpr -> mem
duke@0 1297 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1298 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1299 // 64-bit
duke@0 1300 int offset = ra_->reg2offset(dst_first);
duke@0 1301 if (cbuf) {
kvn@3447 1302 MacroAssembler _masm(cbuf);
kvn@3447 1303 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1304 #ifndef PRODUCT
kvn@3447 1305 } else {
duke@0 1306 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1307 offset,
duke@0 1308 Matcher::regName[src_first]);
duke@0 1309 #endif
duke@0 1310 }
duke@0 1311 } else {
duke@0 1312 // 32-bit
duke@0 1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1315 int offset = ra_->reg2offset(dst_first);
duke@0 1316 if (cbuf) {
kvn@3447 1317 MacroAssembler _masm(cbuf);
kvn@3447 1318 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1319 #ifndef PRODUCT
kvn@3447 1320 } else {
duke@0 1321 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1322 offset,
duke@0 1323 Matcher::regName[src_first]);
duke@0 1324 #endif
duke@0 1325 }
duke@0 1326 }
kvn@3447 1327 return 0;
duke@0 1328 } else if (dst_first_rc == rc_int) {
duke@0 1329 // gpr -> gpr
duke@0 1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1332 // 64-bit
duke@0 1333 if (cbuf) {
kvn@3447 1334 MacroAssembler _masm(cbuf);
kvn@3447 1335 __ movq(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1336 as_Register(Matcher::_regEncode[src_first]));
duke@0 1337 #ifndef PRODUCT
kvn@3447 1338 } else {
duke@0 1339 st->print("movq %s, %s\t# spill",
duke@0 1340 Matcher::regName[dst_first],
duke@0 1341 Matcher::regName[src_first]);
duke@0 1342 #endif
duke@0 1343 }
kvn@3447 1344 return 0;
duke@0 1345 } else {
duke@0 1346 // 32-bit
duke@0 1347 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1348 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1349 if (cbuf) {
kvn@3447 1350 MacroAssembler _masm(cbuf);
kvn@3447 1351 __ movl(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1352 as_Register(Matcher::_regEncode[src_first]));
duke@0 1353 #ifndef PRODUCT
kvn@3447 1354 } else {
duke@0 1355 st->print("movl %s, %s\t# spill",
duke@0 1356 Matcher::regName[dst_first],
duke@0 1357 Matcher::regName[src_first]);
duke@0 1358 #endif
duke@0 1359 }
kvn@3447 1360 return 0;
duke@0 1361 }
duke@0 1362 } else if (dst_first_rc == rc_float) {
duke@0 1363 // gpr -> xmm
duke@0 1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1366 // 64-bit
duke@0 1367 if (cbuf) {
kvn@2953 1368 MacroAssembler _masm(cbuf);
kvn@2953 1369 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1370 #ifndef PRODUCT
kvn@3447 1371 } else {
duke@0 1372 st->print("movdq %s, %s\t# spill",
duke@0 1373 Matcher::regName[dst_first],
duke@0 1374 Matcher::regName[src_first]);
duke@0 1375 #endif
duke@0 1376 }
duke@0 1377 } else {
duke@0 1378 // 32-bit
duke@0 1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1381 if (cbuf) {
kvn@2953 1382 MacroAssembler _masm(cbuf);
kvn@2953 1383 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1384 #ifndef PRODUCT
kvn@3447 1385 } else {
duke@0 1386 st->print("movdl %s, %s\t# spill",
duke@0 1387 Matcher::regName[dst_first],
duke@0 1388 Matcher::regName[src_first]);
duke@0 1389 #endif
duke@0 1390 }
duke@0 1391 }
kvn@3447 1392 return 0;
duke@0 1393 }
duke@0 1394 } else if (src_first_rc == rc_float) {
duke@0 1395 // xmm ->
duke@0 1396 if (dst_first_rc == rc_stack) {
duke@0 1397 // xmm -> mem
duke@0 1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1400 // 64-bit
duke@0 1401 int offset = ra_->reg2offset(dst_first);
duke@0 1402 if (cbuf) {
kvn@2953 1403 MacroAssembler _masm(cbuf);
kvn@2953 1404 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1405 #ifndef PRODUCT
kvn@3447 1406 } else {
duke@0 1407 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1408 offset,
duke@0 1409 Matcher::regName[src_first]);
duke@0 1410 #endif
duke@0 1411 }
duke@0 1412 } else {
duke@0 1413 // 32-bit
duke@0 1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1416 int offset = ra_->reg2offset(dst_first);
duke@0 1417 if (cbuf) {
kvn@2953 1418 MacroAssembler _masm(cbuf);
kvn@2953 1419 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1420 #ifndef PRODUCT
kvn@3447 1421 } else {
duke@0 1422 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1423 offset,
duke@0 1424 Matcher::regName[src_first]);
duke@0 1425 #endif
duke@0 1426 }
duke@0 1427 }
kvn@3447 1428 return 0;
duke@0 1429 } else if (dst_first_rc == rc_int) {
duke@0 1430 // xmm -> gpr
duke@0 1431 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1432 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1433 // 64-bit
duke@0 1434 if (cbuf) {
kvn@2953 1435 MacroAssembler _masm(cbuf);
kvn@2953 1436 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1437 #ifndef PRODUCT
kvn@3447 1438 } else {
duke@0 1439 st->print("movdq %s, %s\t# spill",
duke@0 1440 Matcher::regName[dst_first],
duke@0 1441 Matcher::regName[src_first]);
duke@0 1442 #endif
duke@0 1443 }
duke@0 1444 } else {
duke@0 1445 // 32-bit
duke@0 1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1448 if (cbuf) {
kvn@2953 1449 MacroAssembler _masm(cbuf);
kvn@2953 1450 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1451 #ifndef PRODUCT
kvn@3447 1452 } else {
duke@0 1453 st->print("movdl %s, %s\t# spill",
duke@0 1454 Matcher::regName[dst_first],
duke@0 1455 Matcher::regName[src_first]);
duke@0 1456 #endif
duke@0 1457 }
duke@0 1458 }
kvn@3447 1459 return 0;
duke@0 1460 } else if (dst_first_rc == rc_float) {
duke@0 1461 // xmm -> xmm
duke@0 1462 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1463 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1464 // 64-bit
duke@0 1465 if (cbuf) {
kvn@2953 1466 MacroAssembler _masm(cbuf);
kvn@2953 1467 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1468 #ifndef PRODUCT
kvn@3447 1469 } else {
duke@0 1470 st->print("%s %s, %s\t# spill",
duke@0 1471 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1472 Matcher::regName[dst_first],
duke@0 1473 Matcher::regName[src_first]);
duke@0 1474 #endif
duke@0 1475 }
duke@0 1476 } else {
duke@0 1477 // 32-bit
duke@0 1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1480 if (cbuf) {
kvn@2953 1481 MacroAssembler _masm(cbuf);
kvn@2953 1482 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1483 #ifndef PRODUCT
kvn@3447 1484 } else {
duke@0 1485 st->print("%s %s, %s\t# spill",
duke@0 1486 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1487 Matcher::regName[dst_first],
duke@0 1488 Matcher::regName[src_first]);
duke@0 1489 #endif
duke@0 1490 }
duke@0 1491 }
kvn@3447 1492 return 0;
duke@0 1493 }
duke@0 1494 }
duke@0 1495
duke@0 1496 assert(0," foo ");
duke@0 1497 Unimplemented();
duke@0 1498 return 0;
duke@0 1499 }
duke@0 1500
duke@0 1501 #ifndef PRODUCT
kvn@3447 1502 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
duke@0 1503 implementation(NULL, ra_, false, st);
duke@0 1504 }
duke@0 1505 #endif
duke@0 1506
kvn@3447 1507 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1508 implementation(&cbuf, ra_, false, NULL);
duke@0 1509 }
duke@0 1510
kvn@3447 1511 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
kvn@3447 1512 return MachNode::size(ra_);
duke@0 1513 }
duke@0 1514
duke@0 1515 //=============================================================================
duke@0 1516 #ifndef PRODUCT
duke@0 1517 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1518 {
duke@0 1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1520 int reg = ra_->get_reg_first(this);
duke@0 1521 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1522 Matcher::regName[reg], offset);
duke@0 1523 }
duke@0 1524 #endif
duke@0 1525
duke@0 1526 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1527 {
duke@0 1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1529 int reg = ra_->get_encode(this);
duke@0 1530 if (offset >= 0x80) {
duke@0 1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1533 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1535 emit_d32(cbuf, offset);
duke@0 1536 } else {
duke@0 1537 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1538 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1539 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1540 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1541 emit_d8(cbuf, offset);
duke@0 1542 }
duke@0 1543 }
duke@0 1544
duke@0 1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1546 {
duke@0 1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1548 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1549 }
duke@0 1550
duke@0 1551 //=============================================================================
duke@0 1552 #ifndef PRODUCT
duke@0 1553 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1554 {
ehelin@5259 1555 if (UseCompressedClassPointers) {
kvn@1491 1556 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
hseigel@5093 1557 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
kvn@1491 1558 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1559 } else {
kvn@1491 1560 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1561 "# Inline cache check");
coleenp@113 1562 }
duke@0 1563 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1564 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1565 }
duke@0 1566 #endif
duke@0 1567
duke@0 1568 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1569 {
duke@0 1570 MacroAssembler masm(&cbuf);
twisti@1668 1571 uint insts_size = cbuf.insts_size();
ehelin@5259 1572 if (UseCompressedClassPointers) {
coleenp@113 1573 masm.load_klass(rscratch1, j_rarg0);
never@304 1574 masm.cmpptr(rax, rscratch1);
coleenp@113 1575 } else {
never@304 1576 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1577 }
duke@0 1578
duke@0 1579 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1580
duke@0 1581 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1582 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1583 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1584 if (OptoBreakpoint) {
duke@0 1585 // Leave space for int3
kvn@1491 1586 nops_cnt -= 1;
duke@0 1587 }
kvn@1491 1588 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1589 if (nops_cnt > 0)
kvn@1491 1590 masm.nop(nops_cnt);
duke@0 1591 }
duke@0 1592
duke@0 1593 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1594 {
kvn@1491 1595 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1596 // the hard way
duke@0 1597 }
kvn@8379 1598
duke@0 1599
duke@0 1600 //=============================================================================
duke@0 1601
duke@0 1602 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1603 {
duke@0 1604 return regnum - 32; // The FP registers are in the second chunk
duke@0 1605 }
duke@0 1606
duke@0 1607 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1608 const bool Matcher::convL2FSupported(void) {
duke@0 1609 return true;
duke@0 1610 }
duke@0 1611
duke@0 1612 // Is this branch offset short enough that a short branch can be used?
duke@0 1613 //
duke@0 1614 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1615 // this method should return false for offset 0.
kvn@2614 1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1617 // The passed offset is relative to address of the branch.
kvn@2614 1618 // On 86 a branch displacement is calculated relative to address
kvn@2614 1619 // of a next instruction.
kvn@2614 1620 offset -= br_size;
kvn@2614 1621
never@415 1622 // the short version of jmpConUCF2 contains multiple branches,
never@415 1623 // making the reach slightly less
never@415 1624 if (rule == jmpConUCF2_rule)
never@415 1625 return (-126 <= offset && offset <= 125);
never@415 1626 return (-128 <= offset && offset <= 127);
duke@0 1627 }
duke@0 1628
duke@0 1629 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1630 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1631 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1632
duke@0 1633 // Probably always true, even if a temp register is required.
duke@0 1634 return true;
duke@0 1635 }
duke@0 1636
duke@0 1637 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1638 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1639
duke@0 1640 // Threshold size for cleararray.
duke@0 1641 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1642
kvn@2808 1643 // No additional cost for CMOVL.
kvn@2808 1644 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 1645
kvn@2808 1646 // No CMOVF/CMOVD with SSE2
kvn@2808 1647 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 1648
goetz@5982 1649 // Does the CPU require late expand (see block.cpp for description of late expand)?
goetz@5982 1650 const bool Matcher::require_postalloc_expand = false;
goetz@5982 1651
duke@0 1652 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1653 // to be subsumed into complex addressing expressions or compute them
duke@0 1654 // into registers? True for Intel but false for most RISCs
duke@0 1655 const bool Matcher::clone_shift_expressions = true;
duke@0 1656
roland@2248 1657 // Do we need to mask the count passed to shift instructions or does
roland@2248 1658 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 1659 const bool Matcher::need_masked_shift_count = false;
roland@2248 1660
kvn@1495 1661 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 1662 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 1663 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 1664 }
kvn@1495 1665
roland@3724 1666 bool Matcher::narrow_klass_use_complex_address() {
ehelin@5259 1667 assert(UseCompressedClassPointers, "only for compressed klass code");
roland@3724 1668 return (LogKlassAlignmentInBytes <= 3);
roland@3724 1669 }
roland@3724 1670
duke@0 1671 // Is it better to copy float constants, or load them directly from
duke@0 1672 // memory? Intel can load a float constant from a direct address,
duke@0 1673 // requiring no extra registers. Most RISCs will have to materialize
duke@0 1674 // an address into a register first, so they would do better to copy
duke@0 1675 // the constant from stack.
duke@0 1676 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 1677
duke@0 1678 // If CPU can load and store mis-aligned doubles directly then no
duke@0 1679 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 1680 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 1681 // C code as the Java calling convention forces doubles to be aligned.
duke@0 1682 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1683
duke@0 1684 // No-op on amd64
duke@0 1685 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 1686
duke@0 1687 // Advertise here if the CPU requires explicit rounding operations to
duke@0 1688 // implement the UseStrictFP mode.
duke@0 1689 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 1690
kvn@1274 1691 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 1692 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 1693 bool Matcher::float_in_double() { return false; }
kvn@1274 1694
duke@0 1695 // Do ints take an entire long register or just half?
duke@0 1696 const bool Matcher::int_in_long = true;
duke@0 1697
duke@0 1698 // Return whether or not this register is ever used as an argument.
duke@0 1699 // This function is used on startup to build the trampoline stubs in
duke@0 1700 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 1701 // call in the trampoline, and arguments in those registers not be
duke@0 1702 // available to the callee.
duke@0 1703 bool Matcher::can_be_java_arg(int reg)
duke@0 1704 {
duke@0 1705 return
kvn@3447 1706 reg == RDI_num || reg == RDI_H_num ||
kvn@3447 1707 reg == RSI_num || reg == RSI_H_num ||
kvn@3447 1708 reg == RDX_num || reg == RDX_H_num ||
kvn@3447 1709 reg == RCX_num || reg == RCX_H_num ||
kvn@3447 1710 reg == R8_num || reg == R8_H_num ||
kvn@3447 1711 reg == R9_num || reg == R9_H_num ||
kvn@3447 1712 reg == R12_num || reg == R12_H_num ||
kvn@3447 1713 reg == XMM0_num || reg == XMM0b_num ||
kvn@3447 1714 reg == XMM1_num || reg == XMM1b_num ||
kvn@3447 1715 reg == XMM2_num || reg == XMM2b_num ||
kvn@3447 1716 reg == XMM3_num || reg == XMM3b_num ||
kvn@3447 1717 reg == XMM4_num || reg == XMM4b_num ||
kvn@3447 1718 reg == XMM5_num || reg == XMM5b_num ||
kvn@3447 1719 reg == XMM6_num || reg == XMM6b_num ||
kvn@3447 1720 reg == XMM7_num || reg == XMM7b_num;
duke@0 1721 }
duke@0 1722
duke@0 1723 bool Matcher::is_spillable_arg(int reg)
duke@0 1724 {
duke@0 1725 return can_be_java_arg(reg);
duke@0 1726 }
duke@0 1727
kvn@1834 1728 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 1729 // In 64 bit mode a code which use multiply when
kvn@1834 1730 // devisor is constant is faster than hardware
kvn@1834 1731 // DIV instruction (it uses MulHiL).
kvn@1834 1732 return false;
kvn@1834 1733 }
kvn@1834 1734
duke@0 1735 // Register for DIVI projection of divmodI
duke@0 1736 RegMask Matcher::divI_proj_mask() {
roland@2882 1737 return INT_RAX_REG_mask();
duke@0 1738 }
duke@0 1739
duke@0 1740 // Register for MODI projection of divmodI
duke@0 1741 RegMask Matcher::modI_proj_mask() {
roland@2882 1742 return INT_RDX_REG_mask();
duke@0 1743 }
duke@0 1744
duke@0 1745 // Register for DIVL projection of divmodL
duke@0 1746 RegMask Matcher::divL_proj_mask() {
roland@2882 1747 return LONG_RAX_REG_mask();
duke@0 1748 }
duke@0 1749
duke@0 1750 // Register for MODL projection of divmodL
duke@0 1751 RegMask Matcher::modL_proj_mask() {
roland@2882 1752 return LONG_RDX_REG_mask();
duke@0 1753 }
duke@0 1754
zmajo@8290 1755 // Register for saving SP into on method handle invokes. Not used on x86_64.
twisti@1137 1756 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
zmajo@8290 1757 return NO_REG_mask();
twisti@1137 1758 }
twisti@1137 1759
duke@0 1760 %}
duke@0 1761
duke@0 1762 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1763 // This block specifies the encoding classes used by the compiler to
duke@0 1764 // output byte streams. Encoding classes are parameterized macros
duke@0 1765 // used by Machine Instruction Nodes in order to generate the bit
duke@0 1766 // encoding of the instruction. Operands specify their base encoding
duke@0 1767 // interface with the interface keyword. There are currently
duke@0 1768 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 1769 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 1770 // which returns its register number when queried. CONST_INTER causes
duke@0 1771 // an operand to generate a function which returns the value of the
duke@0 1772 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 1773 // four functions which return the Base Register, the Index Register,
duke@0 1774 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 1775 // COND_INTER causes an operand to generate six functions which return
duke@0 1776 // the encoding code (ie - encoding bits for the instruction)
duke@0 1777 // associated with each basic boolean condition for a conditional
duke@0 1778 // instruction.
duke@0 1779 //
duke@0 1780 // Instructions specify two basic values for encoding. Again, a
duke@0 1781 // function is available to check if the constant displacement is an
duke@0 1782 // oop. They use the ins_encode keyword to specify their encoding
duke@0 1783 // classes (which must be a sequence of enc_class names, and their
duke@0 1784 // parameters, specified in the encoding block), and they use the
duke@0 1785 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1786 // tertiary opcode. Only the opcode sections which a particular
duke@0 1787 // instruction needs for encoding need to be specified.
duke@0 1788 encode %{
duke@0 1789 // Build emit functions for each basic byte or larger field in the
duke@0 1790 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 1791 // from C++ code in the enc_class source block. Emit functions will
duke@0 1792 // live in the main source block for now. In future, we can
duke@0 1793 // generalize this by adding a syntax that specifies the sizes of
duke@0 1794 // fields in an order, so that the adlc can build the emit functions
duke@0 1795 // automagically
duke@0 1796
duke@0 1797 // Emit primary opcode
duke@0 1798 enc_class OpcP
duke@0 1799 %{
duke@0 1800 emit_opcode(cbuf, $primary);
duke@0 1801 %}
duke@0 1802
duke@0 1803 // Emit secondary opcode
duke@0 1804 enc_class OpcS
duke@0 1805 %{
duke@0 1806 emit_opcode(cbuf, $secondary);
duke@0 1807 %}
duke@0 1808
duke@0 1809 // Emit tertiary opcode
duke@0 1810 enc_class OpcT
duke@0 1811 %{
duke@0 1812 emit_opcode(cbuf, $tertiary);
duke@0 1813 %}
duke@0 1814
duke@0 1815 // Emit opcode directly
duke@0 1816 enc_class Opcode(immI d8)
duke@0 1817 %{
duke@0 1818 emit_opcode(cbuf, $d8$$constant);
duke@0 1819 %}
duke@0 1820
duke@0 1821 // Emit size prefix
duke@0 1822 enc_class SizePrefix
duke@0 1823 %{
duke@0 1824 emit_opcode(cbuf, 0x66);
duke@0 1825 %}
duke@0 1826
duke@0 1827 enc_class reg(rRegI reg)
duke@0 1828 %{
duke@0 1829 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 1830 %}
duke@0 1831
duke@0 1832 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 1833 %{
duke@0 1834 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1835 %}
duke@0 1836
duke@0 1837 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 1838 %{
duke@0 1839 emit_opcode(cbuf, $opcode$$constant);
duke@0 1840 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1841 %}
duke@0 1842
duke@0 1843 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 1844 %{
duke@0 1845 // Full implementation of Java idiv and irem; checks for
duke@0 1846 // special case as described in JVM spec., p.243 & p.271.
duke@0 1847 //
duke@0 1848 // normal case special case
duke@0 1849 //
duke@0 1850 // input : rax: dividend min_int
duke@0 1851 // reg: divisor -1
duke@0 1852 //
duke@0 1853 // output: rax: quotient (= rax idiv reg) min_int
duke@0 1854 // rdx: remainder (= rax irem reg) 0
duke@0 1855 //
duke@0 1856 // Code sequnce:
duke@0 1857 //
duke@0 1858 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 1859 // 5: 75 07/08 jne e <normal>
duke@0 1860 // 7: 33 d2 xor %edx,%edx
duke@0 1861 // [div >= 8 -> offset + 1]
duke@0 1862 // [REX_B]
duke@0 1863 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1864 // c: 74 03/04 je 11 <done>
duke@0 1865 // 000000000000000e <normal>:
duke@0 1866 // e: 99 cltd
duke@0 1867 // [div >= 8 -> offset + 1]
duke@0 1868 // [REX_B]
duke@0 1869 // f: f7 f9 idiv $div
duke@0 1870 // 0000000000000011 <done>:
duke@0 1871
duke@0 1872 // cmp $0x80000000,%eax
duke@0 1873 emit_opcode(cbuf, 0x3d);
duke@0 1874 emit_d8(cbuf, 0x00);
duke@0 1875 emit_d8(cbuf, 0x00);
duke@0 1876 emit_d8(cbuf, 0x00);
duke@0 1877 emit_d8(cbuf, 0x80);
duke@0 1878
duke@0 1879 // jne e <normal>
duke@0 1880 emit_opcode(cbuf, 0x75);
duke@0 1881 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 1882
duke@0 1883 // xor %edx,%edx
duke@0 1884 emit_opcode(cbuf, 0x33);
duke@0 1885 emit_d8(cbuf, 0xD2);
duke@0 1886
duke@0 1887 // cmp $0xffffffffffffffff,%ecx
duke@0 1888 if ($div$$reg >= 8) {
duke@0 1889 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1890 }
duke@0 1891 emit_opcode(cbuf, 0x83);
duke@0 1892 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1893 emit_d8(cbuf, 0xFF);
duke@0 1894
duke@0 1895 // je 11 <done>
duke@0 1896 emit_opcode(cbuf, 0x74);
duke@0 1897 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 1898
duke@0 1899 // <normal>
duke@0 1900 // cltd
duke@0 1901 emit_opcode(cbuf, 0x99);
duke@0 1902
duke@0 1903 // idivl (note: must be emitted by the user of this rule)
duke@0 1904 // <done>
duke@0 1905 %}
duke@0 1906
duke@0 1907 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 1908 %{
duke@0 1909 // Full implementation of Java ldiv and lrem; checks for
duke@0 1910 // special case as described in JVM spec., p.243 & p.271.
duke@0 1911 //
duke@0 1912 // normal case special case
duke@0 1913 //
duke@0 1914 // input : rax: dividend min_long
duke@0 1915 // reg: divisor -1
duke@0 1916 //
duke@0 1917 // output: rax: quotient (= rax idiv reg) min_long
duke@0 1918 // rdx: remainder (= rax irem reg) 0
duke@0 1919 //
duke@0 1920 // Code sequnce:
duke@0 1921 //
duke@0 1922 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 1923 // 7: 00 00 80
duke@0 1924 // a: 48 39 d0 cmp %rdx,%rax
duke@0 1925 // d: 75 08 jne 17 <normal>
duke@0 1926 // f: 33 d2 xor %edx,%edx
duke@0 1927 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1928 // 15: 74 05 je 1c <done>
duke@0 1929 // 0000000000000017 <normal>:
duke@0 1930 // 17: 48 99 cqto
duke@0 1931 // 19: 48 f7 f9 idiv $div
duke@0 1932 // 000000000000001c <done>:
duke@0 1933
duke@0 1934 // mov $0x8000000000000000,%rdx
duke@0 1935 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1936 emit_opcode(cbuf, 0xBA);
duke@0 1937 emit_d8(cbuf, 0x00);
duke@0 1938 emit_d8(cbuf, 0x00);
duke@0 1939 emit_d8(cbuf, 0x00);
duke@0 1940 emit_d8(cbuf, 0x00);
duke@0 1941 emit_d8(cbuf, 0x00);
duke@0 1942 emit_d8(cbuf, 0x00);
duke@0 1943 emit_d8(cbuf, 0x00);
duke@0 1944 emit_d8(cbuf, 0x80);
duke@0 1945
duke@0 1946 // cmp %rdx,%rax
duke@0 1947 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1948 emit_opcode(cbuf, 0x39);
duke@0 1949 emit_d8(cbuf, 0xD0);
duke@0 1950
duke@0 1951 // jne 17 <normal>
duke@0 1952 emit_opcode(cbuf, 0x75);
duke@0 1953 emit_d8(cbuf, 0x08);
duke@0 1954
duke@0 1955 // xor %edx,%edx
duke@0 1956 emit_opcode(cbuf, 0x33);
duke@0 1957 emit_d8(cbuf, 0xD2);
duke@0 1958
duke@0 1959 // cmp $0xffffffffffffffff,$div
duke@0 1960 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 1961 emit_opcode(cbuf, 0x83);
duke@0 1962 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1963 emit_d8(cbuf, 0xFF);
duke@0 1964
duke@0 1965 // je 1e <done>
duke@0 1966 emit_opcode(cbuf, 0x74);
duke@0 1967 emit_d8(cbuf, 0x05);
duke@0 1968
duke@0 1969 // <normal>
duke@0 1970 // cqto
duke@0 1971 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1972 emit_opcode(cbuf, 0x99);
duke@0 1973
duke@0 1974 // idivq (note: must be emitted by the user of this rule)
duke@0 1975 // <done>
duke@0 1976 %}
duke@0 1977
duke@0 1978 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 1979 enc_class OpcSE(immI imm)
duke@0 1980 %{
duke@0 1981 // Emit primary opcode and set sign-extend bit
duke@0 1982 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1983 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1984 emit_opcode(cbuf, $primary | 0x02);
duke@0 1985 } else {
duke@0 1986 // 32-bit immediate
duke@0 1987 emit_opcode(cbuf, $primary);
duke@0 1988 }
duke@0 1989 %}
duke@0 1990
duke@0 1991 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 1992 %{
duke@0 1993 // OpcSEr/m
duke@0 1994 int dstenc = $dst$$reg;
duke@0 1995 if (dstenc >= 8) {
duke@0 1996 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1997 dstenc -= 8;
duke@0 1998 }
duke@0 1999 // Emit primary opcode and set sign-extend bit
duke@0 2000 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2001 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2002 emit_opcode(cbuf, $primary | 0x02);
duke@0 2003 } else {
duke@0 2004 // 32-bit immediate
duke@0 2005 emit_opcode(cbuf, $primary);
duke@0 2006 }
duke@0 2007 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2008 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2009 %}
duke@0 2010
duke@0 2011 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 2012 %{
duke@0 2013 // OpcSEr/m
duke@0 2014 int dstenc = $dst$$reg;
duke@0 2015 if (dstenc < 8) {
duke@0 2016 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2017 } else {
duke@0 2018 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2019 dstenc -= 8;
duke@0 2020 }
duke@0 2021 // Emit primary opcode and set sign-extend bit
duke@0 2022 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2023 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2024 emit_opcode(cbuf, $primary | 0x02);
duke@0 2025 } else {
duke@0 2026 // 32-bit immediate
duke@0 2027 emit_opcode(cbuf, $primary);
duke@0 2028 }
duke@0 2029 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2030 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2031 %}
duke@0 2032
duke@0 2033 enc_class Con8or32(immI imm)
duke@0 2034 %{
duke@0 2035 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2036 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2037 $$$emit8$imm$$constant;
duke@0 2038 } else {
duke@0 2039 // 32-bit immediate
duke@0 2040 $$$emit32$imm$$constant;
duke@0 2041 }
duke@0 2042 %}
duke@0 2043
duke@0 2044 enc_class opc2_reg(rRegI dst)
duke@0 2045 %{
duke@0 2046 // BSWAP
duke@0 2047 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2048 %}
duke@0 2049
duke@0 2050 enc_class opc3_reg(rRegI dst)
duke@0 2051 %{
duke@0 2052 // BSWAP
duke@0 2053 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2054 %}
duke@0 2055
duke@0 2056 enc_class reg_opc(rRegI div)
duke@0 2057 %{
duke@0 2058 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2059 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2060 %}
duke@0 2061
duke@0 2062 enc_class enc_cmov(cmpOp cop)
duke@0 2063 %{
duke@0 2064 // CMOV
duke@0 2065 $$$emit8$primary;
duke@0 2066 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2067 %}
duke@0 2068
duke@0 2069 enc_class enc_PartialSubtypeCheck()
duke@0 2070 %{
duke@0 2071 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2072 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2073 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2074 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2075 Label miss;
jrose@644 2076 const bool set_cond_codes = true;
duke@0 2077
duke@0 2078 MacroAssembler _masm(&cbuf);
jrose@644 2079 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2080 NULL, &miss,
jrose@644 2081 /*set_cond_codes:*/ true);
duke@0 2082 if ($primary) {
never@304 2083 __ xorptr(Rrdi, Rrdi);
duke@0 2084 }
duke@0 2085 __ bind(miss);
duke@0 2086 %}
duke@0 2087
kvn@4438 2088 enc_class clear_avx %{
kvn@4438 2089 debug_only(int off0 = cbuf.insts_size());
kvn@4438 2090 if (ra_->C->max_vector_size() > 16) {
kvn@4438 2091 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 2092 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 2093 MacroAssembler _masm(&cbuf);
kvn@4438 2094 __ vzeroupper();
kvn@4438 2095 }
kvn@4438 2096 debug_only(int off1 = cbuf.insts_size());
kvn@4438 2097 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
kvn@4438 2098 %}
kvn@4438 2099
kvn@4438 2100 enc_class Java_To_Runtime(method meth) %{
kvn@4438 2101 // No relocation needed
kvn@4438 2102 MacroAssembler _masm(&cbuf);
kvn@4438 2103 __ mov64(r10, (int64_t) $meth$$method);
kvn@4438 2104 __ call(r10);
kvn@4438 2105 %}
kvn@4438 2106
duke@0 2107 enc_class Java_To_Interpreter(method meth)
duke@0 2108 %{
duke@0 2109 // CALL Java_To_Interpreter
duke@0 2110 // This is the instruction starting address for relocation info.
twisti@1668 2111 cbuf.set_insts_mark();
duke@0 2112 $$$emit8$primary;
duke@0 2113 // CALL directly to the runtime
duke@0 2114 emit_d32_reloc(cbuf,
twisti@1668 2115 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2116 runtime_call_Relocation::spec(),
duke@0 2117 RELOC_DISP32);
duke@0 2118 %}
duke@0 2119
duke@0 2120 enc_class Java_Static_Call(method meth)
duke@0 2121 %{
duke@0 2122 // JAVA STATIC CALL
duke@0 2123 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2124 // determine who we intended to call.
twisti@1668 2125 cbuf.set_insts_mark();
duke@0 2126 $$$emit8$primary;
duke@0 2127
duke@0 2128 if (!_method) {
vlivanov@9752 2129 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2130 runtime_call_Relocation::spec(),
duke@0 2131 RELOC_DISP32);
duke@0 2132 } else {
vlivanov@9752 2133 int method_index = resolved_method_index(cbuf);
vlivanov@9752 2134 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
vlivanov@9752 2135 : static_call_Relocation::spec(method_index);
vlivanov@9752 2136 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
vlivanov@9752 2137 rspec, RELOC_DISP32);
twisti@9111 2138 // Emit stubs for static call.
twisti@9111 2139 address mark = cbuf.insts_mark();
twisti@9111 2140 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
thartmann@8795 2141 if (stub == NULL) {
thartmann@8795 2142 ciEnv::current()->record_failure("CodeCache is full");
thartmann@8795 2143 return;
twisti@9111 2144 }
duke@0 2145 }
duke@0 2146 %}
duke@0 2147
coleenp@3602 2148 enc_class Java_Dynamic_Call(method meth) %{
coleenp@3602 2149 MacroAssembler _masm(&cbuf);
vlivanov@9752 2150 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
duke@0 2151 %}
duke@0 2152
duke@0 2153 enc_class Java_Compiled_Call(method meth)
duke@0 2154 %{
duke@0 2155 // JAVA COMPILED CALL
coleenp@3602 2156 int disp = in_bytes(Method:: from_compiled_offset());
duke@0 2157
duke@0 2158 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2159 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2160
duke@0 2161 // callq *disp(%rax)
twisti@1668 2162 cbuf.set_insts_mark();
duke@0 2163 $$$emit8$primary;
duke@0 2164 if (disp < 0x80) {
duke@0 2165 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2166 emit_d8(cbuf, disp); // Displacement
duke@0 2167 } else {
duke@0 2168 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2169 emit_d32(cbuf, disp); // Displacement
duke@0 2170 }
duke@0 2171 %}
duke@0 2172
duke@0 2173 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2174 %{
duke@0 2175 // SAL, SAR, SHR
duke@0 2176 int dstenc = $dst$$reg;
duke@0 2177 if (dstenc >= 8) {
duke@0 2178 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2179 dstenc -= 8;
duke@0 2180 }
duke@0 2181 $$$emit8$primary;
duke@0 2182 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2183 $$$emit8$shift$$constant;
duke@0 2184 %}
duke@0 2185
duke@0 2186 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2187 %{
duke@0 2188 // SAL, SAR, SHR
duke@0 2189 int dstenc = $dst$$reg;
duke@0 2190 if (dstenc < 8) {
duke@0 2191 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2192 } else {
duke@0 2193 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2194 dstenc -= 8;
duke@0 2195 }
duke@0 2196 $$$emit8$primary;
duke@0 2197 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2198 $$$emit8$shift$$constant;
duke@0 2199 %}
duke@0 2200
duke@0 2201 enc_class load_immI(rRegI dst, immI src)
duke@0 2202 %{
duke@0 2203 int dstenc = $dst$$reg;
duke@0 2204 if (dstenc >= 8) {
duke@0 2205 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2206 dstenc -= 8;
duke@0 2207 }
duke@0 2208 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2209 $$$emit32$src$$constant;
duke@0 2210 %}
duke@0 2211
duke@0 2212 enc_class load_immL(rRegL dst, immL src)
duke@0 2213 %{
duke@0 2214 int dstenc = $dst$$reg;
duke@0 2215 if (dstenc < 8) {
duke@0 2216 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2217 } else {
duke@0 2218 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2219 dstenc -= 8;
duke@0 2220 }
duke@0 2221 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2222 emit_d64(cbuf, $src$$constant);
duke@0 2223 %}
duke@0 2224
duke@0 2225 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2226 %{
duke@0 2227 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2228 int dstenc = $dst$$reg;
duke@0 2229 if (dstenc >= 8) {
duke@0 2230 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2231 dstenc -= 8;
duke@0 2232 }
duke@0 2233 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2234 $$$emit32$src$$constant;
duke@0 2235 %}
duke@0 2236
duke@0 2237 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2238 %{
duke@0 2239 int dstenc = $dst$$reg;
duke@0 2240 if (dstenc < 8) {
duke@0 2241 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2242 } else {
duke@0 2243 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2244 dstenc -= 8;
duke@0 2245 }
duke@0 2246 emit_opcode(cbuf, 0xC7);
duke@0 2247 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2248 $$$emit32$src$$constant;
duke@0 2249 %}
duke@0 2250
duke@0 2251 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2252 %{
duke@0 2253 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2254 int dstenc = $dst$$reg;
duke@0 2255 if (dstenc >= 8) {
duke@0 2256 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2257 dstenc -= 8;
duke@0 2258 }
duke@0 2259 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2260 $$$emit32$src$$constant;
duke@0 2261 %}
duke@0 2262
duke@0 2263 enc_class load_immP(rRegP dst, immP src)
duke@0 2264 %{
duke@0 2265 int dstenc = $dst$$reg;
duke@0 2266 if (dstenc < 8) {
duke@0 2267 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2268 } else {
duke@0 2269 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2270 dstenc -= 8;
duke@0 2271 }
duke@0 2272 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2273 // This next line should be generated from ADLC
coleenp@3602 2274 if ($src->constant_reloc() != relocInfo::none) {
coleenp@3602 2275 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
duke@0 2276 } else {
duke@0 2277 emit_d64(cbuf, $src$$constant);
duke@0 2278 }
duke@0 2279 %}
duke@0 2280
duke@0 2281 enc_class Con32(immI src)
duke@0 2282 %{
duke@0 2283 // Output immediate
duke@0 2284 $$$emit32$src$$constant;
duke@0 2285 %}
duke@0 2286
duke@0 2287 enc_class Con32F_as_bits(immF src)
duke@0 2288 %{
duke@0 2289 // Output Float immediate bits
duke@0 2290 jfloat jf = $src$$constant;
duke@0 2291 jint jf_as_bits = jint_cast(jf);
duke@0 2292 emit_d32(cbuf, jf_as_bits);
duke@0 2293 %}
duke@0 2294
duke@0 2295 enc_class Con16(immI src)
duke@0 2296 %{
duke@0 2297 // Output immediate
duke@0 2298 $$$emit16$src$$constant;
duke@0 2299 %}
duke@0 2300
duke@0 2301 // How is this different from Con32??? XXX
duke@0 2302 enc_class Con_d32(immI src)
duke@0 2303 %{
duke@0 2304 emit_d32(cbuf,$src$$constant);
duke@0 2305 %}
duke@0 2306
duke@0 2307 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2308 // Output immediate memory reference
duke@0 2309 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2310 emit_d32(cbuf, 0x00);
duke@0 2311 %}
duke@0 2312
duke@0 2313 enc_class lock_prefix()
duke@0 2314 %{
duke@0 2315 if (os::is_MP()) {
duke@0 2316 emit_opcode(cbuf, 0xF0); // lock
duke@0 2317 }
duke@0 2318 %}
duke@0 2319
duke@0 2320 enc_class REX_mem(memory mem)
duke@0 2321 %{
duke@0 2322 if ($mem$$base >= 8) {
duke@0 2323 if ($mem$$index < 8) {
duke@0 2324 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2325 } else {
duke@0 2326 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2327 }
duke@0 2328 } else {
duke@0 2329 if ($mem$$index >= 8) {
duke@0 2330 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2331 }
duke@0 2332 }
duke@0 2333 %}
duke@0 2334
duke@0 2335 enc_class REX_mem_wide(memory mem)
duke@0 2336 %{
duke@0 2337 if ($mem$$base >= 8) {
duke@0 2338 if ($mem$$index < 8) {
duke@0 2339 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2340 } else {
duke@0 2341 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2342 }
duke@0 2343 } else {
duke@0 2344 if ($mem$$index < 8) {
duke@0 2345 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2346 } else {
duke@0 2347 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2348 }
duke@0 2349 }
duke@0 2350 %}
duke@0 2351
duke@0 2352 // for byte regs
duke@0 2353 enc_class REX_breg(rRegI reg)
duke@0 2354 %{
duke@0 2355 if ($reg$$reg >= 4) {
duke@0 2356 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2357 }
duke@0 2358 %}
duke@0 2359
duke@0 2360 // for byte regs
duke@0 2361 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2362 %{
duke@0 2363 if ($dst$$reg < 8) {
duke@0 2364 if ($src$$reg >= 4) {
duke@0 2365 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2366 }
duke@0 2367 } else {
duke@0 2368 if ($src$$reg < 8) {
duke@0 2369 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2370 } else {
duke@0 2371 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2372 }
duke@0 2373 }
duke@0 2374 %}
duke@0 2375
duke@0 2376 // for byte regs
duke@0 2377 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2378 %{
duke@0 2379 if ($reg$$reg < 8) {
duke@0 2380 if ($mem$$base < 8) {
duke@0 2381 if ($mem$$index >= 8) {
duke@0 2382 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2383 } else if ($reg$$reg >= 4) {
duke@0 2384 emit_opcode(cbuf, Assembler::REX);
duke@0 2385 }
duke@0 2386 } else {
duke@0 2387 if ($mem$$index < 8) {
duke@0 2388 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2389 } else {
duke@0 2390 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2391 }
duke@0 2392 }
duke@0 2393 } else {
duke@0 2394 if ($mem$$base < 8) {
duke@0 2395 if ($mem$$index < 8) {
duke@0 2396 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2397 } else {
duke@0 2398 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2399 }
duke@0 2400 } else {
duke@0 2401 if ($mem$$index < 8) {
duke@0 2402 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2403 } else {
duke@0 2404 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2405 }
duke@0 2406 }
duke@0 2407 }
duke@0 2408 %}
duke@0 2409
duke@0 2410 enc_class REX_reg(rRegI reg)
duke@0 2411 %{
duke@0 2412 if ($reg$$reg >= 8) {
duke@0 2413 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2414 }
duke@0 2415 %}
duke@0 2416
duke@0 2417 enc_class REX_reg_wide(rRegI reg)
duke@0 2418 %{
duke@0 2419 if ($reg$$reg < 8) {
duke@0 2420 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2421 } else {
duke@0 2422 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2423 }
duke@0 2424 %}
duke@0 2425
duke@0 2426 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2427 %{
duke@0 2428 if ($dst$$reg < 8) {
duke@0 2429 if ($src$$reg >= 8) {
duke@0 2430 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2431 }
duke@0 2432 } else {
duke@0 2433 if ($src$$reg < 8) {
duke@0 2434 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2435 } else {
duke@0 2436 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2437 }
duke@0 2438 }
duke@0 2439 %}
duke@0 2440
duke@0 2441 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2442 %{
duke@0 2443 if ($dst$$reg < 8) {
duke@0 2444 if ($src$$reg < 8) {
duke@0 2445 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2446 } else {
duke@0 2447 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2448 }
duke@0 2449 } else {
duke@0 2450 if ($src$$reg < 8) {
duke@0 2451 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2452 } else {
duke@0 2453 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2454 }
duke@0 2455 }
duke@0 2456 %}
duke@0 2457
duke@0 2458 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 2459 %{
duke@0 2460 if ($reg$$reg < 8) {
duke@0 2461 if ($mem$$base < 8) {
duke@0 2462 if ($mem$$index >= 8) {
duke@0 2463 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2464 }
duke@0 2465 } else {
duke@0 2466 if ($mem$$index < 8) {
duke@0 2467 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2468 } else {
duke@0 2469 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2470 }
duke@0 2471 }
duke@0 2472 } else {
duke@0 2473 if ($mem$$base < 8) {
duke@0 2474 if ($mem$$index < 8) {
duke@0 2475 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2476 } else {
duke@0 2477 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2478 }
duke@0 2479 } else {
duke@0 2480 if ($mem$$index < 8) {
duke@0 2481 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2482 } else {
duke@0 2483 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2484 }
duke@0 2485 }
duke@0 2486 }
duke@0 2487 %}
duke@0 2488
duke@0 2489 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 2490 %{
duke@0 2491 if ($reg$$reg < 8) {
duke@0 2492 if ($mem$$base < 8) {
duke@0 2493 if ($mem$$index < 8) {
duke@0 2494 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2495 } else {
duke@0 2496 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2497 }
duke@0 2498 } else {
duke@0 2499 if ($mem$$index < 8) {
duke@0 2500 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2501 } else {
duke@0 2502 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2503 }
duke@0 2504 }
duke@0 2505 } else {
duke@0 2506 if ($mem$$base < 8) {
duke@0 2507 if ($mem$$index < 8) {
duke@0 2508 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2509 } else {
duke@0 2510 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 2511 }
duke@0 2512 } else {
duke@0 2513 if ($mem$$index < 8) {
duke@0 2514 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2515 } else {
duke@0 2516 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 2517 }
duke@0 2518 }
duke@0 2519 }
duke@0 2520 %}
duke@0 2521
duke@0 2522 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 2523 %{
duke@0 2524 // High registers handle in encode_RegMem
duke@0 2525 int reg = $ereg$$reg;
duke@0 2526 int base = $mem$$base;
duke@0 2527 int index = $mem$$index;
duke@0 2528 int scale = $mem$$scale;
duke@0 2529 int disp = $mem$$disp;
coleenp@3602 2530 relocInfo::relocType disp_reloc = $mem->disp_reloc();
coleenp@3602 2531
coleenp@3602 2532 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
duke@0 2533 %}
duke@0 2534
duke@0 2535 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 2536 %{
duke@0 2537 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 2538
duke@0 2539 // High registers handle in encode_RegMem
duke@0 2540 int base = $mem$$base;
duke@0 2541 int index = $mem$$index;
duke@0 2542 int scale = $mem$$scale;
duke@0 2543 int displace = $mem$$disp;
duke@0 2544
coleenp@3602 2545 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
duke@0 2546 // working with static
duke@0 2547 // globals
duke@0 2548 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
coleenp@3602 2549 disp_reloc);
duke@0 2550 %}
duke@0 2551
duke@0 2552 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 2553 %{
duke@0 2554 int reg_encoding = $dst$$reg;
duke@0 2555 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 2556 int index = 0x04; // 0x04 indicates no index
duke@0 2557 int scale = 0x00; // 0x00 indicates no scale
duke@0 2558 int displace = $src1$$constant; // 0x00 indicates no displacement
coleenp@3602 2559 relocInfo::relocType disp_reloc = relocInfo::none;
duke@0 2560 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
coleenp@3602 2561 disp_reloc);
duke@0 2562 %}
duke@0 2563
duke@0 2564 enc_class neg_reg(rRegI dst)
duke@0 2565 %{
duke@0 2566 int dstenc = $dst$$reg;
duke@0 2567 if (dstenc >= 8) {
duke@0 2568 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2569 dstenc -= 8;
duke@0 2570 }
duke@0 2571 // NEG $dst
duke@0 2572 emit_opcode(cbuf, 0xF7);
duke@0 2573 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2574 %}
duke@0 2575
duke@0 2576 enc_class neg_reg_wide(rRegI dst)
duke@0 2577 %{
duke@0 2578 int dstenc = $dst$$reg;
duke@0 2579 if (dstenc < 8) {
duke@0 2580 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2581 } else {
duke@0 2582 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2583 dstenc -= 8;
duke@0 2584 }
duke@0 2585 // NEG $dst
duke@0 2586 emit_opcode(cbuf, 0xF7);
duke@0 2587 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2588 %}
duke@0 2589
duke@0 2590 enc_class setLT_reg(rRegI dst)
duke@0 2591 %{
duke@0 2592 int dstenc = $dst$$reg;
duke@0 2593 if (dstenc >= 8) {
duke@0 2594 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2595 dstenc -= 8;
duke@0 2596 } else if (dstenc >= 4) {
duke@0 2597 emit_opcode(cbuf, Assembler::REX);
duke@0 2598 }
duke@0 2599 // SETLT $dst
duke@0 2600 emit_opcode(cbuf, 0x0F);
duke@0 2601 emit_opcode(cbuf, 0x9C);
duke@0 2602 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2603 %}
duke@0 2604
duke@0 2605 enc_class setNZ_reg(rRegI dst)
duke@0 2606 %{
duke@0 2607 int dstenc = $dst$$reg;
duke@0 2608 if (dstenc >= 8) {
duke@0 2609 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2610 dstenc -= 8;
duke@0 2611 } else if (dstenc >= 4) {
duke@0 2612 emit_opcode(cbuf, Assembler::REX);
duke@0 2613 }
duke@0 2614 // SETNZ $dst
duke@0 2615 emit_opcode(cbuf, 0x0F);
duke@0 2616 emit_opcode(cbuf, 0x95);
duke@0 2617 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2618 %}
duke@0 2619
duke@0 2620
duke@0 2621 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 2622 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 2623 %{
duke@0 2624 int src1enc = $src1$$reg;
duke@0 2625 int src2enc = $src2$$reg;
duke@0 2626 int dstenc = $dst$$reg;
duke@0 2627
duke@0 2628 // cmpq $src1, $src2
duke@0 2629 if (src1enc < 8) {
duke@0 2630 if (src2enc < 8) {
duke@0 2631 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2632 } else {
duke@0 2633 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2634 }
duke@0 2635 } else {
duke@0 2636 if (src2enc < 8) {
duke@0 2637 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2638 } else {
duke@0 2639 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2640 }
duke@0 2641 }
duke@0 2642 emit_opcode(cbuf, 0x3B);
duke@0 2643 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 2644
duke@0 2645 // movl $dst, -1
duke@0 2646 if (dstenc >= 8) {
duke@0 2647 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2648 }
duke@0 2649 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2650 emit_d32(cbuf, -1);
duke@0 2651
duke@0 2652 // jl,s done
duke@0 2653 emit_opcode(cbuf, 0x7C);
duke@0 2654 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2655
duke@0 2656 // setne $dst
duke@0 2657 if (dstenc >= 4) {
duke@0 2658 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2659 }
duke@0 2660 emit_opcode(cbuf, 0x0F);
duke@0 2661 emit_opcode(cbuf, 0x95);
duke@0 2662 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2663
duke@0 2664 // movzbl $dst, $dst
duke@0 2665 if (dstenc >= 4) {
duke@0 2666 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2667 }
duke@0 2668 emit_opcode(cbuf, 0x0F);
duke@0 2669 emit_opcode(cbuf, 0xB6);
duke@0 2670 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2671 %}
duke@0 2672
duke@0 2673 enc_class Push_ResultXD(regD dst) %{
kvn@2953 2674 MacroAssembler _masm(&cbuf);
kvn@2953 2675 __ fstp_d(Address(rsp, 0));
kvn@2953 2676 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
kvn@2953 2677 __ addptr(rsp, 8);
duke@0 2678 %}
duke@0 2679
duke@0 2680 enc_class Push_SrcXD(regD src) %{
duke@0 2681 MacroAssembler _masm(&cbuf);
kvn@2953 2682 __ subptr(rsp, 8);
kvn@2953 2683 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
kvn@2953 2684 __ fld_d(Address(rsp, 0));
kvn@2953 2685 %}
kvn@2953 2686
duke@0 2687
duke@0 2688 enc_class enc_rethrow()
duke@0 2689 %{
twisti@1668 2690 cbuf.set_insts_mark();
duke@0 2691 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 2692 emit_d32_reloc(cbuf,
twisti@1668 2693 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 2694 runtime_call_Relocation::spec(),
duke@0 2695 RELOC_DISP32);
duke@0 2696 %}
duke@0 2697
duke@0 2698 %}
duke@0 2699
duke@0 2700
coleenp@113 2701
duke@0 2702 //----------FRAME--------------------------------------------------------------
duke@0 2703 // Definition of frame structure and management information.
duke@0 2704 //
duke@0 2705 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 2706 // | (to get allocators register number
duke@0 2707 // G Owned by | | v add OptoReg::stack0())
duke@0 2708 // r CALLER | |
duke@0 2709 // o | +--------+ pad to even-align allocators stack-slot
duke@0 2710 // w V | pad0 | numbers; owned by CALLER
duke@0 2711 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 2712 // h ^ | in | 5
duke@0 2713 // | | args | 4 Holes in incoming args owned by SELF
duke@0 2714 // | | | | 3
duke@0 2715 // | | +--------+
duke@0 2716 // V | | old out| Empty on Intel, window on Sparc
duke@0 2717 // | old |preserve| Must be even aligned.
duke@0 2718 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 2719 // | | in | 3 area for Intel ret address
duke@0 2720 // Owned by |preserve| Empty on Sparc.
duke@0 2721 // SELF +--------+
duke@0 2722 // | | pad2 | 2 pad to align old SP
duke@0 2723 // | +--------+ 1
duke@0 2724 // | | locks | 0
duke@0 2725 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 2726 // | | pad1 | 11 pad to align new SP
duke@0 2727 // | +--------+
duke@0 2728 // | | | 10
duke@0 2729 // | | spills | 9 spills
duke@0 2730 // V | | 8 (pad0 slot for callee)
duke@0 2731 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 2732 // ^ | out | 7
duke@0 2733 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 2734 // Owned by +--------+
duke@0 2735 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 2736 // | new |preserve| Must be even-aligned.
duke@0 2737 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 2738 // | | |
duke@0 2739 //
duke@0 2740 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 2741 // known from SELF's arguments and the Java calling convention.
duke@0 2742 // Region 6-7 is determined per call site.
duke@0 2743 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 2744 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 2745 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 2746 // incoming area, as the Java calling convention is completely under
duke@0 2747 // the control of the AD file. Doubles can be sorted and packed to
duke@0 2748 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 2749 // varargs C calling conventions.
duke@0 2750 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 2751 // even aligned with pad0 as needed.
duke@0 2752 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 2753 // region 6-11 is even aligned; it may be padded out more so that
duke@0 2754 // the region from SP to FP meets the minimum stack alignment.
duke@0 2755 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
duke@0 2756 // alignment. Region 11, pad1, may be dynamically extended so that
duke@0 2757 // SP meets the minimum alignment.
duke@0 2758
duke@0 2759 frame
duke@0 2760 %{
duke@0 2761 // What direction does stack grow in (assumed to be same for C & Java)
duke@0 2762 stack_direction(TOWARDS_LOW);
duke@0 2763
duke@0 2764 // These three registers define part of the calling convention
duke@0 2765 // between compiled code and the interpreter.
duke@0 2766 inline_cache_reg(RAX); // Inline Cache Register
duke@0 2767 interpreter_method_oop_reg(RBX); // Method Oop Register when
duke@0 2768 // calling interpreter
duke@0 2769
duke@0 2770 // Optional: name the operand used by cisc-spilling to access
duke@0 2771 // [stack_pointer + offset]
duke@0 2772 cisc_spilling_operand_name(indOffset32);
duke@0 2773
duke@0 2774 // Number of stack slots consumed by locking an object
duke@0 2775 sync_stack_slots(2);
duke@0 2776
duke@0 2777 // Compiled code's Frame Pointer
duke@0 2778 frame_pointer(RSP);
duke@0 2779
duke@0 2780 // Interpreter stores its frame pointer in a register which is
duke@0 2781 // stored to the stack by I2CAdaptors.
duke@0 2782 // I2CAdaptors convert from interpreted java to compiled java.
duke@0 2783 interpreter_frame_pointer(RBP);
duke@0 2784
duke@0 2785 // Stack alignment requirement
duke@0 2786 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
duke@0 2787
duke@0 2788 // Number of stack slots between incoming argument block and the start of
duke@0 2789 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 2790 // EPILOG must remove this many slots. amd64 needs two slots for
duke@0 2791 // return address.
duke@0 2792 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
duke@0 2793
duke@0 2794 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 2795 // for calls to C. Supports the var-args backing area for register parms.
duke@0 2796 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
duke@0 2797
duke@0 2798 // The after-PROLOG location of the return address. Location of
duke@0 2799 // return address specifies a type (REG or STACK) and a number
duke@0 2800 // representing the register number (i.e. - use a register name) or
duke@0 2801 // stack slot.
duke@0 2802 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
duke@0 2803 // Otherwise, it is above the locks and verification slot and alignment word
duke@0 2804 return_addr(STACK - 2 +
kvn@3142 2805 round_to((Compile::current()->in_preserve_stack_slots() +
kvn@3142 2806 Compile::current()->fixed_slots()),
kvn@3142 2807 stack_alignment_in_slots()));
duke@0 2808
duke@0 2809 // Body of function which returns an integer array locating
duke@0 2810 // arguments either in registers or in stack slots. Passed an array
duke@0 2811 // of ideal registers called "sig" and a "length" count. Stack-slot
duke@0 2812 // offsets are based on outgoing arguments, i.e. a CALLER setting up
duke@0 2813 // arguments for a CALLEE. Incoming stack arguments are
duke@0 2814 // automatically biased by the preserve_stack_slots field above.
duke@0 2815
duke@0 2816 calling_convention
duke@0 2817 %{
duke@0 2818 // No difference between ingoing/outgoing just pass false
duke@0 2819 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
duke@0 2820 %}
duke@0 2821
duke@0 2822 c_calling_convention
duke@0 2823 %{
duke@0 2824 // This is obviously always outgoing
goetz@5970 2825 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
duke@0 2826 %}
duke@0 2827
duke@0 2828 // Location of compiled Java return values. Same as C for now.
duke@0 2829 return_value
duke@0 2830 %{
duke@0 2831 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
duke@0 2832 "only return normal values");
duke@0 2833
duke@0 2834 static const int lo[Op_RegL + 1] = {
duke@0 2835 0,
duke@0 2836 0,
coleenp@113 2837 RAX_num, // Op_RegN
duke@0 2838 RAX_num, // Op_RegI
duke@0 2839 RAX_num, // Op_RegP
duke@0 2840 XMM0_num, // Op_RegF
duke@0 2841 XMM0_num, // Op_RegD
duke@0 2842 RAX_num // Op_RegL
duke@0 2843 };
duke@0 2844 static const int hi[Op_RegL + 1] = {
duke@0 2845 0,
duke@0 2846 0,
coleenp@113 2847 OptoReg::Bad, // Op_RegN
duke@0 2848 OptoReg::Bad, // Op_RegI
duke@0 2849 RAX_H_num, // Op_RegP
duke@0 2850 OptoReg::Bad, // Op_RegF
kvn@3447 2851 XMM0b_num, // Op_RegD
duke@0 2852 RAX_H_num // Op_RegL
duke@0 2853 };
kvn@3447 2854 // Excluded flags and vector registers.
kvn@8379 2855 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
duke@0 2856 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
duke@0 2857 %}
duke@0 2858 %}
duke@0 2859
duke@0 2860 //----------ATTRIBUTES---------------------------------------------------------
duke@0 2861 //----------Operand Attributes-------------------------------------------------
duke@0 2862 op_attrib op_cost(0); // Required cost attribute
duke@0 2863
duke@0 2864 //----------Instruction Attributes---------------------------------------------
duke@0 2865 ins_attrib ins_cost(100); // Required cost attribute
duke@0 2866 ins_attrib ins_size(8); // Required size attribute (in bits)
duke@0 2867 ins_attrib ins_short_branch(0); // Required flag: is this instruction
duke@0 2868 // a non-matching short branch variant
duke@0 2869 // of some long branch?
duke@0 2870 ins_attrib ins_alignment(1); // Required alignment attribute (must
duke@0 2871 // be a power of 2) specifies the
duke@0 2872 // alignment that some part of the
duke@0 2873 // instruction (not necessarily the
duke@0 2874 // start) requires. If > 1, a
duke@0 2875 // compute_padding() function must be
duke@0 2876 // provided for the instruction
duke@0 2877
duke@0 2878 //----------OPERANDS-----------------------------------------------------------
duke@0 2879 // Operand definitions must precede instruction definitions for correct parsing
duke@0 2880 // in the ADLC because operands constitute user defined types which are used in
duke@0 2881 // instruction definitions.
duke@0 2882
duke@0 2883 //----------Simple Operands----------------------------------------------------
duke@0 2884 // Immediate Operands
duke@0 2885 // Integer Immediate
duke@0 2886 operand immI()
duke@0 2887 %{
duke@0 2888 match(ConI);
duke@0 2889
duke@0 2890 op_cost(10);
duke@0 2891 format %{ %}
duke@0 2892 interface(CONST_INTER);
duke@0 2893 %}
duke@0 2894
duke@0 2895 // Constant for test vs zero
duke@0 2896 operand immI0()
duke@0 2897 %{
duke@0 2898 predicate(n->get_int() == 0);
duke@0 2899 match(ConI);
duke@0 2900
duke@0 2901 op_cost(0);
duke@0 2902 format %{ %}
duke@0 2903 interface(CONST_INTER);
duke@0 2904 %}
duke@0 2905
duke@0 2906 // Constant for increment
duke@0 2907 operand immI1()
duke@0 2908 %{
duke@0 2909 predicate(n->get_int() == 1);
duke@0 2910 match(ConI);
duke@0 2911
duke@0 2912 op_cost(0);
duke@0 2913 format %{ %}
duke@0 2914 interface(CONST_INTER);
duke@0 2915 %}
duke@0 2916
duke@0 2917 // Constant for decrement
duke@0 2918 operand immI_M1()
duke@0 2919 %{
duke@0 2920 predicate(n->get_int() == -1);
duke@0 2921 match(ConI);
duke@0 2922
duke@0 2923 op_cost(0);
duke@0 2924 format %{ %}
duke@0 2925 interface(CONST_INTER);
duke@0 2926 %}
duke@0 2927
duke@0 2928 // Valid scale values for addressing modes
duke@0 2929 operand immI2()
duke@0 2930 %{
duke@0 2931 predicate(0 <= n->get_int() && (n->get_int() <= 3));
duke@0 2932 match(ConI);
duke@0 2933
duke@0 2934 format %{ %}
duke@0 2935 interface(CONST_INTER);
duke@0 2936 %}
duke@0 2937
duke@0 2938 operand immI8()
duke@0 2939 %{
duke@0 2940 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
duke@0 2941 match(ConI);
duke@0 2942
duke@0 2943 op_cost(5);
duke@0 2944 format %{ %}
duke@0 2945 interface(CONST_INTER);
duke@0 2946 %}
duke@0 2947
duke@0 2948 operand immI16()
duke@0 2949 %{
duke@0 2950 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
duke@0 2951 match(ConI);
duke@0 2952
duke@0 2953 op_cost(10);
duke@0 2954 format %{ %}
duke@0 2955 interface(CONST_INTER);
duke@0 2956 %}
duke@0 2957
iveresov@5824 2958 // Int Immediate non-negative
iveresov@5824 2959 operand immU31()
iveresov@5824 2960 %{
iveresov@5824 2961 predicate(n->get_int() >= 0);
iveresov@5824 2962 match(ConI);
iveresov@5824 2963
iveresov@5824 2964 op_cost(0);
iveresov@5824 2965 format %{ %}
iveresov@5824 2966 interface(CONST_INTER);
iveresov@5824 2967 %}
iveresov@5824 2968
duke@0 2969 // Constant for long shifts
duke@0 2970 operand immI_32()
duke@0 2971 %{
duke@0 2972 predicate( n->get_int() == 32 );
duke@0 2973 match(ConI);
duke@0 2974
duke@0 2975 op_cost(0);
duke@0 2976 format %{ %}
duke@0 2977 interface(CONST_INTER);
duke@0 2978 %}
duke@0 2979
duke@0 2980 // Constant for long shifts
duke@0 2981 operand immI_64()
duke@0 2982 %{
duke@0 2983 predicate( n->get_int() == 64 );
duke@0 2984 match(ConI);
duke@0 2985
duke@0 2986 op_cost(0);
duke@0 2987 format %{ %}
duke@0 2988 interface(CONST_INTER);
duke@0 2989 %}
duke@0 2990
duke@0 2991 // Pointer Immediate
duke@0 2992 operand immP()
duke@0 2993 %{
duke@0 2994 match(ConP);
duke@0 2995
duke@0 2996 op_cost(10);
duke@0 2997 format %{ %}
duke@0 2998 interface(CONST_INTER);
duke@0 2999 %}
duke@0 3000
duke@0 3001 // NULL Pointer Immediate
duke@0 3002 operand immP0()
duke@0 3003 %{
duke@0 3004 predicate(n->get_ptr() == 0);
duke@0 3005 match(ConP);
duke@0 3006
duke@0 3007 op_cost(5);
duke@0 3008 format %{ %}
duke@0 3009 interface(CONST_INTER);
duke@0 3010 %}
duke@0 3011
coleenp@113 3012 // Pointer Immediate
coleenp@113 3013 operand immN() %{
coleenp@113 3014 match(ConN);
coleenp@113 3015
coleenp@113 3016 op_cost(10);
coleenp@113 3017 format %{ %}
coleenp@113 3018 interface(CONST_INTER);
coleenp@113 3019 %}
coleenp@113 3020
roland@3724 3021 operand immNKlass() %{
roland@3724 3022 match(ConNKlass);
roland@3724 3023
roland@3724 3024 op_cost(10);
roland@3724 3025 format %{ %}
roland@3724 3026 interface(CONST_INTER);
roland@3724 3027 %}
roland@3724 3028
coleenp@113 3029 // NULL Pointer Immediate
coleenp@113 3030 operand immN0() %{
coleenp@113 3031 predicate(n->get_narrowcon() == 0);
coleenp@113 3032 match(ConN);
coleenp@113 3033
coleenp@113 3034 op_cost(5);
coleenp@113 3035 format %{ %}
coleenp@113 3036 interface(CONST_INTER);
coleenp@113 3037 %}
coleenp@113 3038
duke@0 3039 operand immP31()
duke@0 3040 %{
coleenp@3602 3041 predicate(n->as_Type()->type()->reloc() == relocInfo::none
duke@0 3042 && (n->get_ptr() >> 31) == 0);
duke@0 3043 match(ConP);
duke@0 3044
duke@0 3045 op_cost(5);
duke@0 3046 format %{ %}
duke@0 3047 interface(CONST_INTER);
duke@0 3048 %}
duke@0 3049
coleenp@113 3050
duke@0 3051 // Long Immediate
duke@0 3052 operand immL()
duke@0 3053 %{
duke@0 3054 match(ConL);
duke@0 3055
duke@0 3056 op_cost(20);
duke@0 3057 format %{ %}
duke@0 3058 interface(CONST_INTER);
duke@0 3059 %}
duke@0 3060
duke@0 3061 // Long Immediate 8-bit
duke@0 3062 operand immL8()
duke@0 3063 %{
duke@0 3064 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
duke@0 3065 match(ConL);
duke@0 3066
duke@0 3067 op_cost(5);
duke@0 3068 format %{ %}
duke@0 3069 interface(CONST_INTER);
duke@0 3070 %}
duke@0 3071
duke@0 3072 // Long Immediate 32-bit unsigned
duke@0 3073 operand immUL32()
duke@0 3074 %{
duke@0 3075 predicate(n->get_long() == (unsigned int) (n->get_long()));
duke@0 3076 match(ConL);
duke@0 3077
duke@0 3078 op_cost(10);
duke@0 3079 format %{ %}
duke@0 3080 interface(CONST_INTER);
duke@0 3081 %}
duke@0 3082
duke@0 3083 // Long Immediate 32-bit signed
duke@0 3084 operand immL32()
duke@0 3085 %{
duke@0 3086 predicate(n->get_long() == (int) (n->get_long()));
duke@0 3087 match(ConL);
duke@0 3088
duke@0 3089 op_cost(15);
duke@0 3090 format %{ %}
duke@0 3091 interface(CONST_INTER);
duke@0 3092 %}
duke@0 3093
duke@0 3094 // Long Immediate zero
duke@0 3095 operand immL0()
duke@0 3096 %{
duke@0 3097 predicate(n->get_long() == 0L);
duke@0 3098 match(ConL);
duke@0 3099
duke@0 3100 op_cost(10);
duke@0 3101 format %{ %}
duke@0 3102 interface(CONST_INTER);
duke@0 3103 %}
duke@0 3104
duke@0 3105 // Constant for increment
duke@0 3106 operand immL1()
duke@0 3107 %{
duke@0 3108 predicate(n->get_long() == 1);
duke@0 3109 match(ConL);
duke@0 3110
duke@0 3111 format %{ %}
duke@0 3112 interface(CONST_INTER);
duke@0 3113 %}
duke@0 3114
duke@0 3115 // Constant for decrement
duke@0 3116 operand immL_M1()
duke@0 3117 %{
duke@0 3118 predicate(n->get_long() == -1);
duke@0 3119 match(ConL);
duke@0 3120
duke@0 3121 format %{ %}
duke@0 3122 interface(CONST_INTER);
duke@0 3123 %}
duke@0 3124
duke@0 3125 // Long Immediate: the value 10
duke@0 3126 operand immL10()
duke@0 3127 %{
duke@0 3128 predicate(n->get_long() == 10);
duke@0 3129 match(ConL);
duke@0 3130
duke@0 3131 format %{ %}
duke@0 3132 interface(CONST_INTER);
duke@0 3133 %}
duke@0 3134
duke@0 3135 // Long immediate from 0 to 127.
duke@0 3136 // Used for a shorter form of long mul by 10.
duke@0 3137 operand immL_127()
duke@0 3138 %{
duke@0 3139 predicate(0 <= n->get_long() && n->get_long() < 0x80);
duke@0 3140 match(ConL);
duke@0 3141
duke@0 3142 op_cost(10);
duke@0 3143 format %{ %}
duke@0 3144 interface(CONST_INTER);
duke@0 3145 %}
duke@0 3146
duke@0 3147 // Long Immediate: low 32-bit mask
duke@0 3148 operand immL_32bits()
duke@0 3149 %{
duke@0 3150 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 3151 match(ConL);
duke@0 3152 op_cost(20);
duke@0 3153
duke@0 3154 format %{ %}
duke@0 3155 interface(CONST_INTER);
duke@0 3156 %}
duke@0 3157
duke@0 3158 // Float Immediate zero
duke@0 3159 operand immF0()
duke@0 3160 %{
duke@0 3161 predicate(jint_cast(n->getf()) == 0);
duke@0 3162 match(ConF);
duke@0 3163
duke@0 3164 op_cost(5);
duke@0 3165 format %{ %}
duke@0 3166 interface(CONST_INTER);
duke@0 3167 %}
duke@0 3168
duke@0 3169 // Float Immediate
duke@0 3170 operand immF()
duke@0 3171 %{
duke@0 3172 match(ConF);
duke@0 3173
duke@0 3174 op_cost(15);
duke@0 3175 format %{ %}
duke@0 3176 interface(CONST_INTER);
duke@0 3177 %}
duke@0 3178
duke@0 3179 // Double Immediate zero
duke@0 3180 operand immD0()
duke@0 3181 %{
duke@0 3182 predicate(jlong_cast(n->getd()) == 0);
duke@0 3183 match(ConD);
duke@0 3184
duke@0 3185 op_cost(5);
duke@0 3186 format %{ %}
duke@0 3187 interface(CONST_INTER);
duke@0 3188 %}
duke@0 3189
duke@0 3190 // Double Immediate
duke@0 3191 operand immD()
duke@0 3192 %{
duke@0 3193 match(ConD);
duke@0 3194
duke@0 3195 op_cost(15);
duke@0 3196 format %{ %}
duke@0 3197 interface(CONST_INTER);
duke@0 3198 %}
duke@0 3199
duke@0 3200 // Immediates for special shifts (sign extend)
duke@0 3201
duke@0 3202 // Constants for increment
duke@0 3203 operand immI_16()
duke@0 3204 %{
duke@0 3205 predicate(n->get_int() == 16);
duke@0 3206 match(ConI);
duke@0 3207
duke@0 3208 format %{ %}
duke@0 3209 interface(CONST_INTER);
duke@0 3210 %}
duke@0 3211
duke@0 3212 operand immI_24()
duke@0 3213 %{
duke@0 3214 predicate(n->get_int() == 24);
duke@0 3215 match(ConI);
duke@0 3216
duke@0 3217 format %{ %}
duke@0 3218 interface(CONST_INTER);
duke@0 3219 %}
duke@0 3220
duke@0 3221 // Constant for byte-wide masking
duke@0 3222 operand immI_255()
duke@0 3223 %{
duke@0 3224 predicate(n->get_int() == 255);
duke@0 3225 match(ConI);
duke@0 3226
duke@0 3227 format %{ %}
duke@0 3228 interface(CONST_INTER);
duke@0 3229 %}
duke@0 3230
duke@0 3231 // Constant for short-wide masking
duke@0 3232 operand immI_65535()
duke@0 3233 %{
duke@0 3234 predicate(n->get_int() == 65535);
duke@0 3235 match(ConI);
duke@0 3236
duke@0 3237 format %{ %}
duke@0 3238 interface(CONST_INTER);
duke@0 3239 %}
duke@0 3240
duke@0 3241 // Constant for byte-wide masking
duke@0 3242 operand immL_255()
duke@0 3243 %{
duke@0 3244 predicate(n->get_long() == 255);
duke@0 3245 match(ConL);
duke@0 3246
duke@0 3247 format %{ %}
duke@0 3248 interface(CONST_INTER);
duke@0 3249 %}
duke@0 3250
duke@0 3251 // Constant for short-wide masking
duke@0 3252 operand immL_65535()
duke@0 3253 %{
duke@0 3254 predicate(n->get_long() == 65535);
duke@0 3255 match(ConL);
duke@0 3256
duke@0 3257 format %{ %}
duke@0 3258 interface(CONST_INTER);
duke@0 3259 %}
duke@0 3260
duke@0 3261 // Register Operands
duke@0 3262 // Integer Register
duke@0 3263 operand rRegI()
duke@0 3264 %{
duke@0 3265 constraint(ALLOC_IN_RC(int_reg));
duke@0 3266 match(RegI);
duke@0 3267
duke@0 3268 match(rax_RegI);
duke@0 3269 match(rbx_RegI);
duke@0 3270 match(rcx_RegI);
duke@0 3271 match(rdx_RegI);
duke@0 3272 match(rdi_RegI);
duke@0 3273
duke@0 3274 format %{ %}
duke@0 3275 interface(REG_INTER);
duke@0 3276 %}
duke@0 3277
duke@0 3278 // Special Registers
duke@0 3279 operand rax_RegI()
duke@0 3280 %{
duke@0 3281 constraint(ALLOC_IN_RC(int_rax_reg));
duke@0 3282 match(RegI);
duke@0 3283 match(rRegI);
duke@0 3284
duke@0 3285 format %{ "RAX" %}
duke@0 3286 interface(REG_INTER);
duke@0 3287 %}
duke@0 3288
duke@0 3289 // Special Registers
duke@0 3290 operand rbx_RegI()
duke@0 3291 %{
duke@0 3292 constraint(ALLOC_IN_RC(int_rbx_reg));
duke@0 3293 match(RegI);
duke@0 3294 match(rRegI);
duke@0 3295
duke@0 3296 format %{ "RBX" %}
duke@0 3297 interface(REG_INTER);
duke@0 3298 %}
duke@0 3299
duke@0 3300 operand rcx_RegI()
duke@0 3301 %{
duke@0 3302 constraint(ALLOC_IN_RC(int_rcx_reg));
duke@0 3303 match(RegI);
duke@0 3304 match(rRegI);
duke@0 3305
duke@0 3306 format %{ "RCX" %}
duke@0 3307 interface(REG_INTER);
duke@0 3308 %}
duke@0 3309
duke@0 3310 operand rdx_RegI()
duke@0 3311 %{
duke@0 3312 constraint(ALLOC_IN_RC(int_rdx_reg));
duke@0 3313 match(RegI);
duke@0 3314 match(rRegI);
duke@0 3315
duke@0 3316 format %{ "RDX" %}
duke@0 3317 interface(REG_INTER);
duke@0 3318 %}
duke@0 3319
duke@0 3320 operand rdi_RegI()
duke@0 3321 %{
duke@0 3322 constraint(ALLOC_IN_RC(int_rdi_reg));
duke@0 3323 match(RegI);
duke@0 3324 match(rRegI);
duke@0 3325
duke@0 3326 format %{ "RDI" %}
duke@0 3327 interface(REG_INTER);
duke@0 3328 %}
duke@0 3329
duke@0 3330 operand no_rcx_RegI()
duke@0 3331 %{
duke@0 3332 constraint(ALLOC_IN_RC(int_no_rcx_reg));
duke@0 3333 match(RegI);
duke@0 3334 match(rax_RegI);
duke@0 3335 match(rbx_RegI);
duke@0 3336 match(rdx_RegI);
duke@0 3337 match(rdi_RegI);
duke@0 3338
duke@0 3339 format %{ %}
duke@0 3340 interface(REG_INTER);
duke@0 3341 %}
duke@0 3342
duke@0 3343 operand no_rax_rdx_RegI()
duke@0 3344 %{
duke@0 3345 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
duke@0 3346 match(RegI);
duke@0 3347 match(rbx_RegI);
duke@0 3348 match(rcx_RegI);
duke@0 3349 match(rdi_RegI);
duke@0 3350
duke@0 3351 format %{ %}
duke@0 3352 interface(REG_INTER);
duke@0 3353 %}
duke@0 3354
duke@0 3355 // Pointer Register
duke@0 3356 operand any_RegP()
duke@0 3357 %{
kvn@8379 3358 constraint(ALLOC_IN_RC(any_reg));
duke@0 3359 match(RegP);
duke@0 3360 match(rax_RegP);
duke@0 3361 match(rbx_RegP);
duke@0 3362 match(rdi_RegP);
duke@0 3363 match(rsi_RegP);
duke@0 3364 match(rbp_RegP);
duke@0 3365 match(r15_RegP);
duke@0 3366 match(rRegP);
duke@0 3367
duke@0 3368 format %{ %}
duke@0 3369 interface(REG_INTER);
duke@0 3370 %}
duke@0 3371
duke@0 3372 operand rRegP()
duke@0 3373 %{
duke@0 3374 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3375 match(RegP);
duke@0 3376 match(rax_RegP);
duke@0 3377 match(rbx_RegP);
duke@0 3378 match(rdi_RegP);
duke@0 3379 match(rsi_RegP);
zmajo@8290 3380 match(rbp_RegP); // See Q&A below about
zmajo@8290 3381 match(r15_RegP); // r15_RegP and rbp_RegP.
duke@0 3382
duke@0 3383 format %{ %}
duke@0 3384 interface(REG_INTER);
duke@0 3385 %}
duke@0 3386
coleenp@113 3387 operand rRegN() %{
coleenp@113 3388 constraint(ALLOC_IN_RC(int_reg));
coleenp@113 3389 match(RegN);
coleenp@113 3390
coleenp@113 3391 format %{ %}
coleenp@113 3392 interface(REG_INTER);
coleenp@113 3393 %}
coleenp@113 3394
duke@0 3395 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
duke@0 3396 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
zmajo@8290 3397 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
duke@0 3398 // The output of an instruction is controlled by the allocator, which respects
duke@0 3399 // register class masks, not match rules. Unless an instruction mentions
duke@0 3400 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
duke@0 3401 // by the allocator as an input.
zmajo@8290 3402 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
zmajo@8290 3403 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
zmajo@8290 3404 // result, RBP is not included in the output of the instruction either.
duke@0 3405
duke@0 3406 operand no_rax_RegP()
duke@0 3407 %{
duke@0 3408 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
duke@0 3409 match(RegP);
duke@0 3410 match(rbx_RegP);
duke@0 3411 match(rsi_RegP);
duke@0 3412 match(rdi_RegP);
duke@0 3413
duke@0 3414 format %{ %}
duke@0 3415 interface(REG_INTER);
duke@0 3416 %}
duke@0 3417
zmajo@8290 3418 // This operand is not allowed to use RBP even if
zmajo@8290 3419 // RBP is not used to hold the frame pointer.
duke@0 3420 operand no_rbp_RegP()
duke@0 3421 %{
zmajo@8290 3422 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
duke@0 3423 match(RegP);
duke@0 3424 match(rbx_RegP);
duke@0 3425 match(rsi_RegP);
duke@0 3426 match(rdi_RegP);
duke@0 3427
duke@0 3428 format %{ %}
duke@0 3429 interface(REG_INTER);
duke@0 3430 %}
duke@0 3431
duke@0 3432 operand no_rax_rbx_RegP()
duke@0 3433 %{
duke@0 3434 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
duke@0 3435 match(RegP);
duke@0 3436 match(rsi_RegP);
duke@0 3437 match(rdi_RegP);
duke@0 3438
duke@0 3439 format %{ %}
duke@0 3440 interface(REG_INTER);
duke@0 3441 %}
duke@0 3442
duke@0 3443 // Special Registers
duke@0 3444 // Return a pointer value
duke@0 3445 operand rax_RegP()
duke@0 3446 %{
duke@0 3447 constraint(ALLOC_IN_RC(ptr_rax_reg));
duke@0 3448 match(RegP);
duke@0 3449 match(rRegP);
duke@0 3450
duke@0 3451 format %{ %}
duke@0 3452 interface(REG_INTER);
duke@0 3453 %}
duke@0 3454
coleenp@113 3455 // Special Registers
coleenp@113 3456 // Return a compressed pointer value
coleenp@113 3457 operand rax_RegN()
coleenp@113 3458 %{
coleenp@113 3459 constraint(ALLOC_IN_RC(int_rax_reg));
coleenp@113 3460 match(RegN);
coleenp@113 3461 match(rRegN);
coleenp@113 3462
coleenp@113 3463 format %{ %}
coleenp@113 3464 interface(REG_INTER);
coleenp@113 3465 %}
coleenp@113 3466
duke@0 3467 // Used in AtomicAdd
duke@0 3468 operand rbx_RegP()
duke@0 3469 %{
duke@0 3470 constraint(ALLOC_IN_RC(ptr_rbx_reg));
duke@0 3471 match(RegP);
duke@0 3472 match(rRegP);
duke@0 3473
duke@0 3474 format %{ %}
duke@0 3475 interface(REG_INTER);
duke@0 3476 %}
duke@0 3477
duke@0 3478 operand rsi_RegP()
duke@0 3479 %{
duke@0 3480 constraint(ALLOC_IN_RC(ptr_rsi_reg));
duke@0 3481 match(RegP);
duke@0 3482 match(rRegP);
duke@0 3483
duke@0 3484 format %{ %}
duke@0 3485 interface(REG_INTER);
duke@0 3486 %}
duke@0 3487
duke@0 3488 // Used in rep stosq
duke@0 3489 operand rdi_RegP()
duke@0 3490 %{
duke@0 3491 constraint(ALLOC_IN_RC(ptr_rdi_reg));
duke@0 3492 match(RegP);
duke@0 3493 match(rRegP);
duke@0 3494
duke@0 3495 format %{ %}
duke@0 3496 interface(REG_INTER);
duke@0 3497 %}
duke@0 3498
duke@0 3499 operand r15_RegP()
duke@0 3500 %{
duke@0 3501 constraint(ALLOC_IN_RC(ptr_r15_reg));
duke@0 3502 match(RegP);
duke@0 3503 match(rRegP);
duke@0 3504
duke@0 3505 format %{ %}
duke@0 3506 interface(REG_INTER);
duke@0 3507 %}
duke@0 3508
duke@0 3509 operand rRegL()
duke@0 3510 %{
duke@0 3511 constraint(ALLOC_IN_RC(long_reg));
duke@0 3512 match(RegL);
duke@0 3513 match(rax_RegL);
duke@0 3514 match(rdx_RegL);
duke@0 3515
duke@0 3516 format %{ %}
duke@0 3517 interface(REG_INTER);
duke@0 3518 %}
duke@0 3519
duke@0 3520 // Special Registers
duke@0 3521 operand no_rax_rdx_RegL()
duke@0 3522 %{
duke@0 3523 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3524 match(RegL);
duke@0 3525 match(rRegL);
duke@0 3526
duke@0 3527 format %{ %}
duke@0 3528 interface(REG_INTER);
duke@0 3529 %}
duke@0 3530
duke@0 3531 operand no_rax_RegL()
duke@0 3532 %{
duke@0 3533 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3534 match(RegL);
duke@0 3535 match(rRegL);
duke@0 3536 match(rdx_RegL);
duke@0 3537
duke@0 3538 format %{ %}
duke@0 3539 interface(REG_INTER);
duke@0 3540 %}
duke@0 3541
duke@0 3542 operand no_rcx_RegL()
duke@0 3543 %{
duke@0 3544 constraint(ALLOC_IN_RC(long_no_rcx_reg));
duke@0 3545 match(RegL);
duke@0 3546 match(rRegL);
duke@0 3547
duke@0 3548 format %{ %}
duke@0 3549 interface(REG_INTER);
duke@0 3550 %}
duke@0 3551
duke@0 3552 operand rax_RegL()
duke@0 3553 %{
duke@0 3554 constraint(ALLOC_IN_RC(long_rax_reg));
duke@0 3555 match(RegL);
duke@0 3556 match(rRegL);
duke@0 3557
duke@0 3558 format %{ "RAX" %}
duke@0 3559 interface(REG_INTER);
duke@0 3560 %}
duke@0 3561
duke@0 3562 operand rcx_RegL()
duke@0 3563 %{
duke@0 3564 constraint(ALLOC_IN_RC(long_rcx_reg));
duke@0 3565 match(RegL);
duke@0 3566 match(rRegL);
duke@0 3567
duke@0 3568 format %{ %}
duke@0 3569 interface(REG_INTER);
duke@0 3570 %}
duke@0 3571
duke@0 3572 operand rdx_RegL()
duke@0 3573 %{
duke@0 3574 constraint(ALLOC_IN_RC(long_rdx_reg));
duke@0 3575 match(RegL);
duke@0 3576 match(rRegL);
duke@0 3577
duke@0 3578 format %{ %}
duke@0 3579 interface(REG_INTER);
duke@0 3580 %}
duke@0 3581
duke@0 3582 // Flags register, used as output of compare instructions
duke@0 3583 operand rFlagsReg()
duke@0 3584 %{
duke@0 3585 constraint(ALLOC_IN_RC(int_flags));
duke@0 3586 match(RegFlags);
duke@0 3587
duke@0 3588 format %{ "RFLAGS" %}
duke@0 3589 interface(REG_INTER);
duke@0 3590 %}
duke@0 3591
duke@0 3592 // Flags register, used as output of FLOATING POINT compare instructions
duke@0 3593 operand rFlagsRegU()
duke@0 3594 %{
duke@0 3595 constraint(ALLOC_IN_RC(int_flags));
duke@0 3596 match(RegFlags);
duke@0 3597
duke@0 3598 format %{ "RFLAGS_U" %}
duke@0 3599 interface(REG_INTER);
duke@0 3600 %}
duke@0 3601
never@415 3602 operand rFlagsRegUCF() %{
never@415 3603 constraint(ALLOC_IN_RC(int_flags));
never@415 3604 match(RegFlags);
never@415 3605 predicate(false);
never@415 3606
never@415 3607 format %{ "RFLAGS_U_CF" %}
never@415 3608 interface(REG_INTER);
never@415 3609 %}
never@415 3610
duke@0 3611 // Float register operands
kvn@8379 3612 operand regF() %{
kvn@8379 3613 constraint(ALLOC_IN_RC(float_reg));
kvn@8379 3614 match(RegF);
kvn@8379 3615
kvn@8379 3616 format %{ %}
kvn@8379 3617 interface(REG_INTER);
kvn@8379 3618 %}
kvn@8379 3619
kvn@8379 3620 // Double register operands
kvn@8379 3621 operand regD() %{
kvn@8379 3622 constraint(ALLOC_IN_RC(double_reg));
kvn@8379 3623 match(RegD);
kvn@8379 3624
kvn@8379 3625 format %{ %}
kvn@8379 3626 interface(REG_INTER);
kvn@8379 3627 %}
kvn@8379 3628
kvn@8379 3629 // Vectors
kvn@8379 3630 operand vecS() %{
kvn@8379 3631 constraint(ALLOC_IN_RC(vectors_reg));
kvn@8379 3632 match(VecS);
duke@0 3633
duke@0 3634 format %{ %}
duke@0 3635 interface(REG_INTER);
duke@0 3636 %}
duke@0 3637
kvn@8379 3638 operand vecD() %{
kvn@8379 3639 constraint(ALLOC_IN_RC(vectord_reg));
kvn@8379 3640 match(VecD);
kvn@8379 3641
kvn@8379 3642 format %{ %}
kvn@8379 3643 interface(REG_INTER);
kvn@8379 3644 %}
kvn@8379 3645
kvn@8379 3646 operand vecX() %{
kvn@8379 3647 constraint(ALLOC_IN_RC(vectorx_reg));
kvn@8379 3648 match(VecX);
kvn@8379 3649
kvn@8379 3650 format %{ %}
kvn@8379 3651 interface(REG_INTER);
kvn@8379 3652 %}
kvn@8379 3653
kvn@8379 3654 operand vecY() %{
kvn@8379 3655 constraint(ALLOC_IN_RC(vectory_reg));
kvn@8379 3656 match(VecY);
duke@0 3657
duke@0 3658 format %{ %}
duke@0 3659 interface(REG_INTER);
duke@0 3660 %}
duke@0 3661
duke@0 3662 //----------Memory Operands----------------------------------------------------
duke@0 3663 // Direct Memory Operand
duke@0 3664 // operand direct(immP addr)
duke@0 3665 // %{
duke@0 3666 // match(addr);
duke@0 3667
duke@0 3668 // format %{ "[$addr]" %}
duke@0 3669 // interface(MEMORY_INTER) %{
duke@0 3670 // base(0xFFFFFFFF);
duke@0 3671 // index(0x4);
duke@0 3672 // scale(0x0);
duke@0 3673 // disp($addr);
duke@0 3674 // %}
duke@0 3675 // %}
duke@0 3676
duke@0 3677 // Indirect Memory Operand
duke@0 3678 operand indirect(any_RegP reg)
duke@0 3679 %{
duke@0 3680 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3681 match(reg);
duke@0 3682
duke@0 3683 format %{ "[$reg]" %}
duke@0 3684 interface(MEMORY_INTER) %{
duke@0 3685 base($reg);
duke@0 3686 index(0x4);
duke@0 3687 scale(0x0);
duke@0 3688 disp(0x0);
duke@0 3689 %}
duke@0 3690 %}
duke@0 3691
duke@0 3692 // Indirect Memory Plus Short Offset Operand
duke@0 3693 operand indOffset8(any_RegP reg, immL8 off)
duke@0 3694 %{
duke@0 3695 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3696 match(AddP reg off);
duke@0 3697
duke@0 3698 format %{ "[$reg + $off (8-bit)]" %}
duke@0 3699 interface(MEMORY_INTER) %{
duke@0 3700 base($reg);
duke@0 3701 index(0x4);
duke@0 3702 scale(0x0);
duke@0 3703 disp($off);
duke@0 3704 %}
duke@0 3705 %}
duke@0 3706
duke@0 3707 // Indirect Memory Plus Long Offset Operand
duke@0 3708 operand indOffset32(any_RegP reg, immL32 off)
duke@0 3709 %{
duke@0 3710 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3711 match(AddP reg off);
duke@0 3712
duke@0 3713 format %{ "[$reg + $off (32-bit)]" %}
duke@0 3714 interface(MEMORY_INTER) %{
duke@0 3715 base($reg);
duke@0 3716 index(0x4);
duke@0 3717 scale(0x0);
duke@0 3718 disp($off);
duke@0 3719 %}
duke@0 3720 %}
duke@0 3721
duke@0 3722 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3723 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
duke@0 3724 %{
duke@0 3725 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3726 match(AddP (AddP reg lreg) off);
duke@0 3727
duke@0 3728 op_cost(10);
duke@0 3729 format %{"[$reg + $off + $lreg]" %}
duke@0 3730 interface(MEMORY_INTER) %{
duke@0 3731 base($reg);
duke@0 3732 index($lreg);
duke@0 3733 scale(0x0);
duke@0 3734 disp($off);
duke@0 3735 %}
duke@0 3736 %}
duke@0 3737
duke@0 3738 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3739 operand indIndex(any_RegP reg, rRegL lreg)
duke@0 3740 %{
duke@0 3741 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3742 match(AddP reg lreg);
duke@0 3743
duke@0 3744 op_cost(10);
duke@0 3745 format %{"[$reg + $lreg]" %}
duke@0 3746 interface(MEMORY_INTER) %{
duke@0 3747 base($reg);
duke@0 3748 index($lreg);
duke@0 3749 scale(0x0);
duke@0 3750 disp(0x0);
duke@0 3751 %}
duke@0 3752 %}
duke@0 3753
duke@0 3754 // Indirect Memory Times Scale Plus Index Register
duke@0 3755 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
duke@0 3756 %{
duke@0 3757 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3758 match(AddP reg (LShiftL lreg scale));
duke@0 3759
duke@0 3760 op_cost(10);
duke@0 3761 format %{"[$reg + $lreg << $scale]" %}
duke@0 3762 interface(MEMORY_INTER) %{
duke@0 3763 base($reg);
duke@0 3764 index($lreg);
duke@0 3765 scale($scale);
duke@0 3766 disp(0x0);
duke@0 3767 %}
duke@0 3768 %}
duke@0 3769
roland@9033 3770 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
roland@9033 3771 %{
roland@9033 3772 constraint(ALLOC_IN_RC(ptr_reg));
roland@9033 3773 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
roland@9033 3774 match(AddP reg (LShiftL (ConvI2L idx) scale));
roland@9033 3775
roland@9033 3776 op_cost(10);