annotate src/cpu/x86/vm/x86_64.ad @ 6307:cfa802bad1d8

8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9 Summary: make compiled code bang the stack by the worst case size of the interpreter frame at deoptimization points. Reviewed-by: twisti, kvn
author roland
date Tue, 01 Apr 2014 09:36:49 +0200
parents 34a8cb310db3
children ce2c731bb770
rev   line source
duke@0 1 //
drchase@4509 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // Specify priority of register selection within phases of register
duke@0 135 // allocation. Highest priority is first. A useful heuristic is to
duke@0 136 // give registers a low priority when they are required by machine
duke@0 137 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 138 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 139 // which participate in fixed calling sequences should come last.
duke@0 140 // Registers which are used as pairs must fall on an even boundary.
duke@0 141
duke@0 142 alloc_class chunk0(R10, R10_H,
duke@0 143 R11, R11_H,
duke@0 144 R8, R8_H,
duke@0 145 R9, R9_H,
duke@0 146 R12, R12_H,
duke@0 147 RCX, RCX_H,
duke@0 148 RBX, RBX_H,
duke@0 149 RDI, RDI_H,
duke@0 150 RDX, RDX_H,
duke@0 151 RSI, RSI_H,
duke@0 152 RAX, RAX_H,
duke@0 153 RBP, RBP_H,
duke@0 154 R13, R13_H,
duke@0 155 R14, R14_H,
duke@0 156 R15, R15_H,
duke@0 157 RSP, RSP_H);
duke@0 158
duke@0 159
duke@0 160 //----------Architecture Description Register Classes--------------------------
duke@0 161 // Several register classes are automatically defined based upon information in
duke@0 162 // this architecture description.
duke@0 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 167 //
duke@0 168
duke@0 169 // Class for all pointer registers (including RSP)
duke@0 170 reg_class any_reg(RAX, RAX_H,
duke@0 171 RDX, RDX_H,
duke@0 172 RBP, RBP_H,
duke@0 173 RDI, RDI_H,
duke@0 174 RSI, RSI_H,
duke@0 175 RCX, RCX_H,
duke@0 176 RBX, RBX_H,
duke@0 177 RSP, RSP_H,
duke@0 178 R8, R8_H,
duke@0 179 R9, R9_H,
duke@0 180 R10, R10_H,
duke@0 181 R11, R11_H,
duke@0 182 R12, R12_H,
duke@0 183 R13, R13_H,
duke@0 184 R14, R14_H,
duke@0 185 R15, R15_H);
duke@0 186
duke@0 187 // Class for all pointer registers except RSP
duke@0 188 reg_class ptr_reg(RAX, RAX_H,
duke@0 189 RDX, RDX_H,
duke@0 190 RBP, RBP_H,
duke@0 191 RDI, RDI_H,
duke@0 192 RSI, RSI_H,
duke@0 193 RCX, RCX_H,
duke@0 194 RBX, RBX_H,
duke@0 195 R8, R8_H,
duke@0 196 R9, R9_H,
duke@0 197 R10, R10_H,
duke@0 198 R11, R11_H,
duke@0 199 R13, R13_H,
duke@0 200 R14, R14_H);
duke@0 201
duke@0 202 // Class for all pointer registers except RAX and RSP
duke@0 203 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 204 RBP, RBP_H,
duke@0 205 RDI, RDI_H,
duke@0 206 RSI, RSI_H,
duke@0 207 RCX, RCX_H,
duke@0 208 RBX, RBX_H,
duke@0 209 R8, R8_H,
duke@0 210 R9, R9_H,
duke@0 211 R10, R10_H,
duke@0 212 R11, R11_H,
duke@0 213 R13, R13_H,
duke@0 214 R14, R14_H);
duke@0 215
duke@0 216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 217 RAX, RAX_H,
duke@0 218 RDI, RDI_H,
duke@0 219 RSI, RSI_H,
duke@0 220 RCX, RCX_H,
duke@0 221 RBX, RBX_H,
duke@0 222 R8, R8_H,
duke@0 223 R9, R9_H,
duke@0 224 R10, R10_H,
duke@0 225 R11, R11_H,
duke@0 226 R13, R13_H,
duke@0 227 R14, R14_H);
duke@0 228
duke@0 229 // Class for all pointer registers except RAX, RBX and RSP
duke@0 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 231 RBP, RBP_H,
duke@0 232 RDI, RDI_H,
duke@0 233 RSI, RSI_H,
duke@0 234 RCX, RCX_H,
duke@0 235 R8, R8_H,
duke@0 236 R9, R9_H,
duke@0 237 R10, R10_H,
duke@0 238 R11, R11_H,
duke@0 239 R13, R13_H,
duke@0 240 R14, R14_H);
duke@0 241
duke@0 242 // Singleton class for RAX pointer register
duke@0 243 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 244
duke@0 245 // Singleton class for RBX pointer register
duke@0 246 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 247
duke@0 248 // Singleton class for RSI pointer register
duke@0 249 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 250
duke@0 251 // Singleton class for RDI pointer register
duke@0 252 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 253
duke@0 254 // Singleton class for RBP pointer register
duke@0 255 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 256
duke@0 257 // Singleton class for stack pointer
duke@0 258 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 259
duke@0 260 // Singleton class for TLS pointer
duke@0 261 reg_class ptr_r15_reg(R15, R15_H);
duke@0 262
duke@0 263 // Class for all long registers (except RSP)
duke@0 264 reg_class long_reg(RAX, RAX_H,
duke@0 265 RDX, RDX_H,
duke@0 266 RBP, RBP_H,
duke@0 267 RDI, RDI_H,
duke@0 268 RSI, RSI_H,
duke@0 269 RCX, RCX_H,
duke@0 270 RBX, RBX_H,
duke@0 271 R8, R8_H,
duke@0 272 R9, R9_H,
duke@0 273 R10, R10_H,
duke@0 274 R11, R11_H,
duke@0 275 R13, R13_H,
duke@0 276 R14, R14_H);
duke@0 277
duke@0 278 // Class for all long registers except RAX, RDX (and RSP)
duke@0 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 280 RDI, RDI_H,
duke@0 281 RSI, RSI_H,
duke@0 282 RCX, RCX_H,
duke@0 283 RBX, RBX_H,
duke@0 284 R8, R8_H,
duke@0 285 R9, R9_H,
duke@0 286 R10, R10_H,
duke@0 287 R11, R11_H,
duke@0 288 R13, R13_H,
duke@0 289 R14, R14_H);
duke@0 290
duke@0 291 // Class for all long registers except RCX (and RSP)
duke@0 292 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 293 RDI, RDI_H,
duke@0 294 RSI, RSI_H,
duke@0 295 RAX, RAX_H,
duke@0 296 RDX, RDX_H,
duke@0 297 RBX, RBX_H,
duke@0 298 R8, R8_H,
duke@0 299 R9, R9_H,
duke@0 300 R10, R10_H,
duke@0 301 R11, R11_H,
duke@0 302 R13, R13_H,
duke@0 303 R14, R14_H);
duke@0 304
duke@0 305 // Class for all long registers except RAX (and RSP)
duke@0 306 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 307 RDX, RDX_H,
duke@0 308 RDI, RDI_H,
duke@0 309 RSI, RSI_H,
duke@0 310 RCX, RCX_H,
duke@0 311 RBX, RBX_H,
duke@0 312 R8, R8_H,
duke@0 313 R9, R9_H,
duke@0 314 R10, R10_H,
duke@0 315 R11, R11_H,
duke@0 316 R13, R13_H,
duke@0 317 R14, R14_H);
duke@0 318
duke@0 319 // Singleton class for RAX long register
duke@0 320 reg_class long_rax_reg(RAX, RAX_H);
duke@0 321
duke@0 322 // Singleton class for RCX long register
duke@0 323 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 324
duke@0 325 // Singleton class for RDX long register
duke@0 326 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 327
duke@0 328 // Class for all int registers (except RSP)
duke@0 329 reg_class int_reg(RAX,
duke@0 330 RDX,
duke@0 331 RBP,
duke@0 332 RDI,
duke@0 333 RSI,
duke@0 334 RCX,
duke@0 335 RBX,
duke@0 336 R8,
duke@0 337 R9,
duke@0 338 R10,
duke@0 339 R11,
duke@0 340 R13,
duke@0 341 R14);
duke@0 342
duke@0 343 // Class for all int registers except RCX (and RSP)
duke@0 344 reg_class int_no_rcx_reg(RAX,
duke@0 345 RDX,
duke@0 346 RBP,
duke@0 347 RDI,
duke@0 348 RSI,
duke@0 349 RBX,
duke@0 350 R8,
duke@0 351 R9,
duke@0 352 R10,
duke@0 353 R11,
duke@0 354 R13,
duke@0 355 R14);
duke@0 356
duke@0 357 // Class for all int registers except RAX, RDX (and RSP)
duke@0 358 reg_class int_no_rax_rdx_reg(RBP,
never@304 359 RDI,
duke@0 360 RSI,
duke@0 361 RCX,
duke@0 362 RBX,
duke@0 363 R8,
duke@0 364 R9,
duke@0 365 R10,
duke@0 366 R11,
duke@0 367 R13,
duke@0 368 R14);
duke@0 369
duke@0 370 // Singleton class for RAX int register
duke@0 371 reg_class int_rax_reg(RAX);
duke@0 372
duke@0 373 // Singleton class for RBX int register
duke@0 374 reg_class int_rbx_reg(RBX);
duke@0 375
duke@0 376 // Singleton class for RCX int register
duke@0 377 reg_class int_rcx_reg(RCX);
duke@0 378
duke@0 379 // Singleton class for RCX int register
duke@0 380 reg_class int_rdx_reg(RDX);
duke@0 381
duke@0 382 // Singleton class for RCX int register
duke@0 383 reg_class int_rdi_reg(RDI);
duke@0 384
duke@0 385 // Singleton class for instruction pointer
duke@0 386 // reg_class ip_reg(RIP);
duke@0 387
kvn@3447 388 %}
duke@0 389
duke@0 390 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 391 // This is a block of C++ code which provides values, functions, and
duke@0 392 // definitions necessary in the rest of the architecture description
duke@0 393 source %{
never@304 394 #define RELOC_IMM64 Assembler::imm_operand
duke@0 395 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 396
duke@0 397 #define __ _masm.
duke@0 398
twisti@1137 399 static int preserve_SP_size() {
kvn@2953 400 return 3; // rex.w, op, rm(reg/reg)
twisti@1137 401 }
kvn@4438 402 static int clear_avx_size() {
kvn@4438 403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
kvn@4438 404 }
twisti@1137 405
duke@0 406 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 407 // from the start of the call to the point where the return address
duke@0 408 // will point.
duke@0 409 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 410 {
twisti@1137 411 int offset = 5; // 5 bytes from start of call to where return address points
kvn@4438 412 offset += clear_avx_size();
twisti@1137 413 if (_method_handle_invoke)
twisti@1137 414 offset += preserve_SP_size();
twisti@1137 415 return offset;
duke@0 416 }
duke@0 417
duke@0 418 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 419 {
kvn@4438 420 int offset = 15; // 15 bytes from start of call to where return address points
kvn@4438 421 offset += clear_avx_size();
kvn@4438 422 return offset;
duke@0 423 }
duke@0 424
kvn@4438 425 int MachCallRuntimeNode::ret_addr_offset() {
kvn@4438 426 int offset = 13; // movq r10,#addr; callq (r10)
kvn@4438 427 offset += clear_avx_size();
kvn@4438 428 return offset;
kvn@4438 429 }
duke@0 430
iveresov@2251 431 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 432 // it does if the polling page is more than disp32 away.
duke@0 433 bool SafePointNode::needs_polling_address_input()
duke@0 434 {
iveresov@2251 435 return Assembler::is_polling_page_far();
duke@0 436 }
duke@0 437
duke@0 438 //
duke@0 439 // Compute padding required for nodes which need alignment
duke@0 440 //
duke@0 441
duke@0 442 // The address of the call instruction needs to be 4-byte aligned to
duke@0 443 // ensure that it does not span a cache line so that it can be patched.
duke@0 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 445 {
kvn@4438 446 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 447 current_offset += 1; // skip call opcode byte
duke@0 448 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 449 }
duke@0 450
duke@0 451 // The address of the call instruction needs to be 4-byte aligned to
duke@0 452 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 454 {
twisti@1137 455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
kvn@4438 456 current_offset += clear_avx_size(); // skip vzeroupper
twisti@1137 457 current_offset += 1; // skip call opcode byte
twisti@1137 458 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 459 }
twisti@1137 460
twisti@1137 461 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 462 // ensure that it does not span a cache line so that it can be patched.
duke@0 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 464 {
kvn@4438 465 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 466 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 467 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 468 }
duke@0 469
duke@0 470 // EMIT_RM()
twisti@1668 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 473 cbuf.insts()->emit_int8(c);
duke@0 474 }
duke@0 475
duke@0 476 // EMIT_CC()
twisti@1668 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 478 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 479 cbuf.insts()->emit_int8(c);
duke@0 480 }
duke@0 481
duke@0 482 // EMIT_OPCODE()
twisti@1668 483 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 484 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 485 }
duke@0 486
duke@0 487 // EMIT_OPCODE() w/ relocation information
duke@0 488 void emit_opcode(CodeBuffer &cbuf,
duke@0 489 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 490 {
twisti@1668 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 492 emit_opcode(cbuf, code);
duke@0 493 }
duke@0 494
duke@0 495 // EMIT_D8()
twisti@1668 496 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 497 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 498 }
duke@0 499
duke@0 500 // EMIT_D16()
twisti@1668 501 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 502 cbuf.insts()->emit_int16(d16);
duke@0 503 }
duke@0 504
duke@0 505 // EMIT_D32()
twisti@1668 506 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 507 cbuf.insts()->emit_int32(d32);
duke@0 508 }
duke@0 509
duke@0 510 // EMIT_D64()
twisti@1668 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 512 cbuf.insts()->emit_int64(d64);
duke@0 513 }
duke@0 514
duke@0 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 516 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 517 int d32,
duke@0 518 relocInfo::relocType reloc,
duke@0 519 int format)
duke@0 520 {
duke@0 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 523 cbuf.insts()->emit_int32(d32);
duke@0 524 }
duke@0 525
duke@0 526 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 528 #ifdef ASSERT
duke@0 529 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
coleenp@3602 531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
hseigel@5349 532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 533 }
duke@0 534 #endif
twisti@1668 535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 536 cbuf.insts()->emit_int32(d32);
duke@0 537 }
duke@0 538
duke@0 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 540 address next_ip = cbuf.insts_end() + 4;
duke@0 541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 542 external_word_Relocation::spec(addr),
duke@0 543 RELOC_DISP32);
duke@0 544 }
duke@0 545
duke@0 546
duke@0 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 550 cbuf.insts()->emit_int64(d64);
duke@0 551 }
duke@0 552
duke@0 553 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 555 #ifdef ASSERT
duke@0 556 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
coleenp@3602 558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
hseigel@5349 559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
jrose@989 560 "cannot embed scavengable oops in code");
duke@0 561 }
duke@0 562 #endif
twisti@1668 563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 564 cbuf.insts()->emit_int64(d64);
duke@0 565 }
duke@0 566
duke@0 567 // Access stack slot for load or store
duke@0 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 569 {
duke@0 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 571 if (-0x80 <= disp && disp < 0x80) {
duke@0 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 574 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 575 } else {
duke@0 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 578 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 579 }
duke@0 580 }
duke@0 581
duke@0 582 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 583 void encode_RegMem(CodeBuffer &cbuf,
duke@0 584 int reg,
coleenp@3602 585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
duke@0 586 {
coleenp@3602 587 assert(disp_reloc == relocInfo::none, "cannot have disp");
duke@0 588 int regenc = reg & 7;
duke@0 589 int baseenc = base & 7;
duke@0 590 int indexenc = index & 7;
duke@0 591
duke@0 592 // There is no index & no scale, use form without SIB byte
duke@0 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
coleenp@3602 597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 598 // If 8-bit displacement, mode 0x1
duke@0 599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 600 emit_d8(cbuf, disp);
duke@0 601 } else {
duke@0 602 // If 32-bit displacement
duke@0 603 if (base == -1) { // Special flag for absolute address
duke@0 604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
coleenp@3602 605 if (disp_reloc != relocInfo::none) {
duke@0 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 607 } else {
duke@0 608 emit_d32(cbuf, disp);
duke@0 609 }
duke@0 610 } else {
duke@0 611 // Normal base + offset
duke@0 612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
coleenp@3602 613 if (disp_reloc != relocInfo::none) {
duke@0 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 615 } else {
duke@0 616 emit_d32(cbuf, disp);
duke@0 617 }
duke@0 618 }
duke@0 619 }
duke@0 620 } else {
duke@0 621 // Else, encode with the SIB byte
duke@0 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 624 // If no displacement
duke@0 625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 626 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 627 } else {
coleenp@3602 628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 629 // If 8-bit displacement, mode 0x1
duke@0 630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 631 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 632 emit_d8(cbuf, disp);
duke@0 633 } else {
duke@0 634 // If 32-bit displacement
duke@0 635 if (base == 0x04 ) {
duke@0 636 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 638 } else {
duke@0 639 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 640 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 641 }
coleenp@3602 642 if (disp_reloc != relocInfo::none) {
duke@0 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 644 } else {
duke@0 645 emit_d32(cbuf, disp);
duke@0 646 }
duke@0 647 }
duke@0 648 }
duke@0 649 }
duke@0 650 }
duke@0 651
never@2545 652 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 654 Label exit;
never@2545 655 __ jccb(Assembler::noParity, exit);
never@2545 656 __ pushf();
kvn@2953 657 //
kvn@2953 658 // comiss/ucomiss instructions set ZF,PF,CF flags and
kvn@2953 659 // zero OF,AF,SF for NaN values.
kvn@2953 660 // Fixup flags by zeroing ZF,PF so that compare of NaN
kvn@2953 661 // values returns 'less than' result (CF is set).
kvn@2953 662 // Leave the rest of flags unchanged.
kvn@2953 663 //
kvn@2953 664 // 7 6 5 4 3 2 1 0
kvn@2953 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
kvn@2953 666 // 0 0 1 0 1 0 1 1 (0x2B)
kvn@2953 667 //
never@2545 668 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 669 __ popf();
never@2545 670 __ bind(exit);
kvn@2953 671 }
kvn@2953 672
kvn@2953 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
kvn@2953 674 Label done;
kvn@2953 675 __ movl(dst, -1);
kvn@2953 676 __ jcc(Assembler::parity, done);
kvn@2953 677 __ jcc(Assembler::below, done);
kvn@2953 678 __ setb(Assembler::notEqual, dst);
kvn@2953 679 __ movzbl(dst, dst);
kvn@2953 680 __ bind(done);
never@2545 681 }
never@2545 682
duke@0 683
duke@0 684 //=============================================================================
twisti@1915 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 686
twisti@2875 687 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 688 return 0; // absolute addressing, no offset
twisti@2875 689 }
twisti@2875 690
goetz@5982 691 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
goetz@5982 692 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
goetz@5982 693 ShouldNotReachHere();
goetz@5982 694 }
goetz@5982 695
twisti@1915 696 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 697 // Empty encoding
twisti@1915 698 }
twisti@1915 699
twisti@1915 700 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 701 return 0;
twisti@1915 702 }
twisti@1915 703
twisti@1915 704 #ifndef PRODUCT
twisti@1915 705 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 706 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 707 }
twisti@1915 708 #endif
twisti@1915 709
twisti@1915 710
twisti@1915 711 //=============================================================================
duke@0 712 #ifndef PRODUCT
kvn@3139 713 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
duke@0 714 Compile* C = ra_->C;
duke@0 715
roland@6307 716 int framesize = C->frame_size_in_bytes();
roland@6307 717 int bangsize = C->bang_size_in_bytes();
duke@0 718 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
kvn@3139 719 // Remove wordSize for return addr which is already pushed.
kvn@3139 720 framesize -= wordSize;
kvn@3139 721
roland@6307 722 if (C->need_stack_bang(bangsize)) {
kvn@3139 723 framesize -= wordSize;
roland@6307 724 st->print("# stack bang (%d bytes)", bangsize);
kvn@3139 725 st->print("\n\t");
kvn@3139 726 st->print("pushq rbp\t# Save rbp");
kvn@3139 727 if (framesize) {
kvn@3139 728 st->print("\n\t");
kvn@3139 729 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 730 }
kvn@3139 731 } else {
kvn@3139 732 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 733 st->print("\n\t");
kvn@3139 734 framesize -= wordSize;
kvn@3139 735 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
duke@0 736 }
duke@0 737
duke@0 738 if (VerifyStackAtCalls) {
kvn@3139 739 st->print("\n\t");
kvn@3139 740 framesize -= wordSize;
kvn@3139 741 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
kvn@3139 742 #ifdef ASSERT
kvn@3139 743 st->print("\n\t");
kvn@3139 744 st->print("# stack alignment check");
kvn@3139 745 #endif
duke@0 746 }
kvn@3139 747 st->cr();
duke@0 748 }
duke@0 749 #endif
duke@0 750
kvn@3139 751 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 752 Compile* C = ra_->C;
kvn@3139 753 MacroAssembler _masm(&cbuf);
duke@0 754
roland@6307 755 int framesize = C->frame_size_in_bytes();
roland@6307 756 int bangsize = C->bang_size_in_bytes();
roland@6307 757
roland@6307 758 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
duke@0 759
twisti@1668 760 C->set_frame_complete(cbuf.insts_size());
duke@0 761
twisti@2875 762 if (C->has_mach_constant_base_node()) {
twisti@2875 763 // NOTE: We set the table base offset here because users might be
twisti@2875 764 // emitted before MachConstantBaseNode.
twisti@2875 765 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 766 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 767 }
duke@0 768 }
duke@0 769
duke@0 770 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 771 {
duke@0 772 return MachNode::size(ra_); // too many variables; just compute it
duke@0 773 // the hard way
duke@0 774 }
duke@0 775
duke@0 776 int MachPrologNode::reloc() const
duke@0 777 {
duke@0 778 return 0; // a large enough number
duke@0 779 }
duke@0 780
duke@0 781 //=============================================================================
duke@0 782 #ifndef PRODUCT
duke@0 783 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 784 {
duke@0 785 Compile* C = ra_->C;
kvn@4438 786 if (C->max_vector_size() > 16) {
kvn@4438 787 st->print("vzeroupper");
kvn@4438 788 st->cr(); st->print("\t");
kvn@4438 789 }
kvn@4438 790
roland@6307 791 int framesize = C->frame_size_in_bytes();
duke@0 792 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 793 // Remove word for return adr already pushed
duke@0 794 // and RBP
duke@0 795 framesize -= 2*wordSize;
duke@0 796
duke@0 797 if (framesize) {
iveresov@2251 798 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 799 st->print("\t");
duke@0 800 }
duke@0 801
iveresov@2251 802 st->print_cr("popq rbp");
duke@0 803 if (do_polling() && C->is_method_compilation()) {
duke@0 804 st->print("\t");
iveresov@2251 805 if (Assembler::is_polling_page_far()) {
iveresov@2251 806 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 807 "testl rax, [rscratch1]\t"
iveresov@2251 808 "# Safepoint: poll for GC");
iveresov@2251 809 } else {
iveresov@2251 810 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 811 "# Safepoint: poll for GC");
iveresov@2251 812 }
duke@0 813 }
duke@0 814 }
duke@0 815 #endif
duke@0 816
duke@0 817 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 818 {
duke@0 819 Compile* C = ra_->C;
kvn@4438 820 if (C->max_vector_size() > 16) {
kvn@4438 821 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 822 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 823 MacroAssembler _masm(&cbuf);
kvn@4438 824 __ vzeroupper();
kvn@4438 825 }
kvn@4438 826
roland@6307 827 int framesize = C->frame_size_in_bytes();
duke@0 828 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 829 // Remove word for return adr already pushed
duke@0 830 // and RBP
duke@0 831 framesize -= 2*wordSize;
duke@0 832
duke@0 833 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 834
duke@0 835 if (framesize) {
duke@0 836 emit_opcode(cbuf, Assembler::REX_W);
duke@0 837 if (framesize < 0x80) {
duke@0 838 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 839 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 840 emit_d8(cbuf, framesize);
duke@0 841 } else {
duke@0 842 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 843 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 844 emit_d32(cbuf, framesize);
duke@0 845 }
duke@0 846 }
duke@0 847
duke@0 848 // popq rbp
duke@0 849 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 850
duke@0 851 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 852 MacroAssembler _masm(&cbuf);
iveresov@2251 853 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 854 if (Assembler::is_polling_page_far()) {
iveresov@2251 855 __ lea(rscratch1, polling_page);
iveresov@2251 856 __ relocate(relocInfo::poll_return_type);
iveresov@2251 857 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 858 } else {
iveresov@2251 859 __ testl(rax, polling_page);
iveresov@2251 860 }
duke@0 861 }
duke@0 862 }
duke@0 863
duke@0 864 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 865 {
iveresov@2251 866 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 867 // the hard way
duke@0 868 }
duke@0 869
duke@0 870 int MachEpilogNode::reloc() const
duke@0 871 {
duke@0 872 return 2; // a large enough number
duke@0 873 }
duke@0 874
duke@0 875 const Pipeline* MachEpilogNode::pipeline() const
duke@0 876 {
duke@0 877 return MachNode::pipeline_class();
duke@0 878 }
duke@0 879
duke@0 880 int MachEpilogNode::safepoint_offset() const
duke@0 881 {
duke@0 882 return 0;
duke@0 883 }
duke@0 884
duke@0 885 //=============================================================================
duke@0 886
duke@0 887 enum RC {
duke@0 888 rc_bad,
duke@0 889 rc_int,
duke@0 890 rc_float,
duke@0 891 rc_stack
duke@0 892 };
duke@0 893
duke@0 894 static enum RC rc_class(OptoReg::Name reg)
duke@0 895 {
duke@0 896 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 897
duke@0 898 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 899
duke@0 900 VMReg r = OptoReg::as_VMReg(reg);
duke@0 901
duke@0 902 if (r->is_Register()) return rc_int;
duke@0 903
duke@0 904 assert(r->is_XMMRegister(), "must be");
duke@0 905 return rc_float;
duke@0 906 }
duke@0 907
kvn@3447 908 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
kvn@3447 909 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
kvn@3447 910 int src_hi, int dst_hi, uint ireg, outputStream* st);
kvn@3447 911
kvn@3447 912 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
kvn@3447 913 int stack_offset, int reg, uint ireg, outputStream* st);
kvn@3447 914
kvn@3447 915 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
kvn@3447 916 int dst_offset, uint ireg, outputStream* st) {
kvn@3447 917 if (cbuf) {
kvn@3447 918 MacroAssembler _masm(cbuf);
kvn@3447 919 switch (ireg) {
kvn@3447 920 case Op_VecS:
kvn@3447 921 __ movq(Address(rsp, -8), rax);
kvn@3447 922 __ movl(rax, Address(rsp, src_offset));
kvn@3447 923 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 924 __ movq(rax, Address(rsp, -8));
kvn@3447 925 break;
kvn@3447 926 case Op_VecD:
kvn@3447 927 __ pushq(Address(rsp, src_offset));
kvn@3447 928 __ popq (Address(rsp, dst_offset));
kvn@3447 929 break;
kvn@3447 930 case Op_VecX:
kvn@3447 931 __ pushq(Address(rsp, src_offset));
kvn@3447 932 __ popq (Address(rsp, dst_offset));
kvn@3447 933 __ pushq(Address(rsp, src_offset+8));
kvn@3447 934 __ popq (Address(rsp, dst_offset+8));
kvn@3447 935 break;
kvn@3447 936 case Op_VecY:
kvn@3447 937 __ vmovdqu(Address(rsp, -32), xmm0);
kvn@3447 938 __ vmovdqu(xmm0, Address(rsp, src_offset));
kvn@3447 939 __ vmovdqu(Address(rsp, dst_offset), xmm0);
kvn@3447 940 __ vmovdqu(xmm0, Address(rsp, -32));
kvn@3447 941 break;
kvn@3447 942 default:
kvn@3447 943 ShouldNotReachHere();
kvn@3447 944 }
kvn@3447 945 #ifndef PRODUCT
kvn@3447 946 } else {
kvn@3447 947 switch (ireg) {
kvn@3447 948 case Op_VecS:
kvn@3447 949 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 950 "movl rax, [rsp + #%d]\n\t"
kvn@3447 951 "movl [rsp + #%d], rax\n\t"
kvn@3447 952 "movq rax, [rsp - #8]",
kvn@3447 953 src_offset, dst_offset);
kvn@3447 954 break;
kvn@3447 955 case Op_VecD:
kvn@3447 956 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 957 "popq [rsp + #%d]",
kvn@3447 958 src_offset, dst_offset);
kvn@3447 959 break;
kvn@3447 960 case Op_VecX:
kvn@3447 961 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
kvn@3447 962 "popq [rsp + #%d]\n\t"
kvn@3447 963 "pushq [rsp + #%d]\n\t"
kvn@3447 964 "popq [rsp + #%d]",
kvn@3447 965 src_offset, dst_offset, src_offset+8, dst_offset+8);
kvn@3447 966 break;
kvn@3447 967 case Op_VecY:
kvn@3447 968 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
kvn@3447 969 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@3447 970 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@3447 971 "vmovdqu xmm0, [rsp - #32]",
kvn@3447 972 src_offset, dst_offset);
kvn@3447 973 break;
kvn@3447 974 default:
kvn@3447 975 ShouldNotReachHere();
kvn@3447 976 }
kvn@3447 977 #endif
kvn@3447 978 }
kvn@3447 979 }
kvn@3447 980
duke@0 981 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 982 PhaseRegAlloc* ra_,
duke@0 983 bool do_size,
kvn@3447 984 outputStream* st) const {
kvn@3447 985 assert(cbuf != NULL || st != NULL, "sanity");
duke@0 986 // Get registers to move
duke@0 987 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 988 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 989 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 990 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 991
duke@0 992 enum RC src_second_rc = rc_class(src_second);
duke@0 993 enum RC src_first_rc = rc_class(src_first);
duke@0 994 enum RC dst_second_rc = rc_class(dst_second);
duke@0 995 enum RC dst_first_rc = rc_class(dst_first);
duke@0 996
duke@0 997 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 998 "must move at least 1 register" );
duke@0 999
duke@0 1000 if (src_first == dst_first && src_second == dst_second) {
duke@0 1001 // Self copy, no move
duke@0 1002 return 0;
kvn@3447 1003 }
kvn@3447 1004 if (bottom_type()->isa_vect() != NULL) {
kvn@3447 1005 uint ireg = ideal_reg();
kvn@3447 1006 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
kvn@3447 1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
kvn@3447 1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
kvn@3447 1009 // mem -> mem
kvn@3447 1010 int src_offset = ra_->reg2offset(src_first);
kvn@3447 1011 int dst_offset = ra_->reg2offset(dst_first);
kvn@3447 1012 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
kvn@3447 1013 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
kvn@3447 1014 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
kvn@3447 1015 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
kvn@3447 1016 int stack_offset = ra_->reg2offset(dst_first);
kvn@3447 1017 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
kvn@3447 1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
kvn@3447 1019 int stack_offset = ra_->reg2offset(src_first);
kvn@3447 1020 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
kvn@3447 1021 } else {
kvn@3447 1022 ShouldNotReachHere();
kvn@3447 1023 }
kvn@3447 1024 return 0;
kvn@3447 1025 }
kvn@3447 1026 if (src_first_rc == rc_stack) {
duke@0 1027 // mem ->
duke@0 1028 if (dst_first_rc == rc_stack) {
duke@0 1029 // mem -> mem
duke@0 1030 assert(src_second != dst_first, "overlap");
duke@0 1031 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1032 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1033 // 64-bit
duke@0 1034 int src_offset = ra_->reg2offset(src_first);
duke@0 1035 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1036 if (cbuf) {
kvn@3447 1037 MacroAssembler _masm(cbuf);
kvn@3447 1038 __ pushq(Address(rsp, src_offset));
kvn@3447 1039 __ popq (Address(rsp, dst_offset));
duke@0 1040 #ifndef PRODUCT
kvn@3447 1041 } else {
duke@0 1042 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1043 "popq [rsp + #%d]",
kvn@3447 1044 src_offset, dst_offset);
duke@0 1045 #endif
duke@0 1046 }
duke@0 1047 } else {
duke@0 1048 // 32-bit
duke@0 1049 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1050 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1051 // No pushl/popl, so:
duke@0 1052 int src_offset = ra_->reg2offset(src_first);
duke@0 1053 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1054 if (cbuf) {
kvn@3447 1055 MacroAssembler _masm(cbuf);
kvn@3447 1056 __ movq(Address(rsp, -8), rax);
kvn@3447 1057 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1058 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1059 __ movq(rax, Address(rsp, -8));
duke@0 1060 #ifndef PRODUCT
kvn@3447 1061 } else {
duke@0 1062 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1063 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1064 "movl [rsp + #%d], rax\n\t"
kvn@3447 1065 "movq rax, [rsp - #8]",
kvn@3447 1066 src_offset, dst_offset);
duke@0 1067 #endif
duke@0 1068 }
duke@0 1069 }
kvn@3447 1070 return 0;
duke@0 1071 } else if (dst_first_rc == rc_int) {
duke@0 1072 // mem -> gpr
duke@0 1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1075 // 64-bit
duke@0 1076 int offset = ra_->reg2offset(src_first);
duke@0 1077 if (cbuf) {
kvn@3447 1078 MacroAssembler _masm(cbuf);
kvn@3447 1079 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1080 #ifndef PRODUCT
kvn@3447 1081 } else {
duke@0 1082 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1083 Matcher::regName[dst_first],
duke@0 1084 offset);
duke@0 1085 #endif
duke@0 1086 }
duke@0 1087 } else {
duke@0 1088 // 32-bit
duke@0 1089 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1090 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1091 int offset = ra_->reg2offset(src_first);
duke@0 1092 if (cbuf) {
kvn@3447 1093 MacroAssembler _masm(cbuf);
kvn@3447 1094 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1095 #ifndef PRODUCT
kvn@3447 1096 } else {
duke@0 1097 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1098 Matcher::regName[dst_first],
duke@0 1099 offset);
duke@0 1100 #endif
duke@0 1101 }
duke@0 1102 }
kvn@3447 1103 return 0;
duke@0 1104 } else if (dst_first_rc == rc_float) {
duke@0 1105 // mem-> xmm
duke@0 1106 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1107 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1108 // 64-bit
duke@0 1109 int offset = ra_->reg2offset(src_first);
duke@0 1110 if (cbuf) {
kvn@2953 1111 MacroAssembler _masm(cbuf);
kvn@2953 1112 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1113 #ifndef PRODUCT
kvn@3447 1114 } else {
duke@0 1115 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1116 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1117 Matcher::regName[dst_first],
duke@0 1118 offset);
duke@0 1119 #endif
duke@0 1120 }
duke@0 1121 } else {
duke@0 1122 // 32-bit
duke@0 1123 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1124 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1125 int offset = ra_->reg2offset(src_first);
duke@0 1126 if (cbuf) {
kvn@2953 1127 MacroAssembler _masm(cbuf);
kvn@2953 1128 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1129 #ifndef PRODUCT
kvn@3447 1130 } else {
duke@0 1131 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1132 Matcher::regName[dst_first],
duke@0 1133 offset);
duke@0 1134 #endif
duke@0 1135 }
duke@0 1136 }
kvn@3447 1137 return 0;
duke@0 1138 }
duke@0 1139 } else if (src_first_rc == rc_int) {
duke@0 1140 // gpr ->
duke@0 1141 if (dst_first_rc == rc_stack) {
duke@0 1142 // gpr -> mem
duke@0 1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1145 // 64-bit
duke@0 1146 int offset = ra_->reg2offset(dst_first);
duke@0 1147 if (cbuf) {
kvn@3447 1148 MacroAssembler _masm(cbuf);
kvn@3447 1149 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1150 #ifndef PRODUCT
kvn@3447 1151 } else {
duke@0 1152 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1153 offset,
duke@0 1154 Matcher::regName[src_first]);
duke@0 1155 #endif
duke@0 1156 }
duke@0 1157 } else {
duke@0 1158 // 32-bit
duke@0 1159 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1160 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1161 int offset = ra_->reg2offset(dst_first);
duke@0 1162 if (cbuf) {
kvn@3447 1163 MacroAssembler _masm(cbuf);
kvn@3447 1164 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1165 #ifndef PRODUCT
kvn@3447 1166 } else {
duke@0 1167 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1168 offset,
duke@0 1169 Matcher::regName[src_first]);
duke@0 1170 #endif
duke@0 1171 }
duke@0 1172 }
kvn@3447 1173 return 0;
duke@0 1174 } else if (dst_first_rc == rc_int) {
duke@0 1175 // gpr -> gpr
duke@0 1176 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1177 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1178 // 64-bit
duke@0 1179 if (cbuf) {
kvn@3447 1180 MacroAssembler _masm(cbuf);
kvn@3447 1181 __ movq(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1182 as_Register(Matcher::_regEncode[src_first]));
duke@0 1183 #ifndef PRODUCT
kvn@3447 1184 } else {
duke@0 1185 st->print("movq %s, %s\t# spill",
duke@0 1186 Matcher::regName[dst_first],
duke@0 1187 Matcher::regName[src_first]);
duke@0 1188 #endif
duke@0 1189 }
kvn@3447 1190 return 0;
duke@0 1191 } else {
duke@0 1192 // 32-bit
duke@0 1193 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1194 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1195 if (cbuf) {
kvn@3447 1196 MacroAssembler _masm(cbuf);
kvn@3447 1197 __ movl(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1198 as_Register(Matcher::_regEncode[src_first]));
duke@0 1199 #ifndef PRODUCT
kvn@3447 1200 } else {
duke@0 1201 st->print("movl %s, %s\t# spill",
duke@0 1202 Matcher::regName[dst_first],
duke@0 1203 Matcher::regName[src_first]);
duke@0 1204 #endif
duke@0 1205 }
kvn@3447 1206 return 0;
duke@0 1207 }
duke@0 1208 } else if (dst_first_rc == rc_float) {
duke@0 1209 // gpr -> xmm
duke@0 1210 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1211 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1212 // 64-bit
duke@0 1213 if (cbuf) {
kvn@2953 1214 MacroAssembler _masm(cbuf);
kvn@2953 1215 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1216 #ifndef PRODUCT
kvn@3447 1217 } else {
duke@0 1218 st->print("movdq %s, %s\t# spill",
duke@0 1219 Matcher::regName[dst_first],
duke@0 1220 Matcher::regName[src_first]);
duke@0 1221 #endif
duke@0 1222 }
duke@0 1223 } else {
duke@0 1224 // 32-bit
duke@0 1225 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1226 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1227 if (cbuf) {
kvn@2953 1228 MacroAssembler _masm(cbuf);
kvn@2953 1229 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1230 #ifndef PRODUCT
kvn@3447 1231 } else {
duke@0 1232 st->print("movdl %s, %s\t# spill",
duke@0 1233 Matcher::regName[dst_first],
duke@0 1234 Matcher::regName[src_first]);
duke@0 1235 #endif
duke@0 1236 }
duke@0 1237 }
kvn@3447 1238 return 0;
duke@0 1239 }
duke@0 1240 } else if (src_first_rc == rc_float) {
duke@0 1241 // xmm ->
duke@0 1242 if (dst_first_rc == rc_stack) {
duke@0 1243 // xmm -> mem
duke@0 1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1246 // 64-bit
duke@0 1247 int offset = ra_->reg2offset(dst_first);
duke@0 1248 if (cbuf) {
kvn@2953 1249 MacroAssembler _masm(cbuf);
kvn@2953 1250 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1251 #ifndef PRODUCT
kvn@3447 1252 } else {
duke@0 1253 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1254 offset,
duke@0 1255 Matcher::regName[src_first]);
duke@0 1256 #endif
duke@0 1257 }
duke@0 1258 } else {
duke@0 1259 // 32-bit
duke@0 1260 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1261 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1262 int offset = ra_->reg2offset(dst_first);
duke@0 1263 if (cbuf) {
kvn@2953 1264 MacroAssembler _masm(cbuf);
kvn@2953 1265 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1266 #ifndef PRODUCT
kvn@3447 1267 } else {
duke@0 1268 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1269 offset,
duke@0 1270 Matcher::regName[src_first]);
duke@0 1271 #endif
duke@0 1272 }
duke@0 1273 }
kvn@3447 1274 return 0;
duke@0 1275 } else if (dst_first_rc == rc_int) {
duke@0 1276 // xmm -> gpr
duke@0 1277 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1278 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1279 // 64-bit
duke@0 1280 if (cbuf) {
kvn@2953 1281 MacroAssembler _masm(cbuf);
kvn@2953 1282 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1283 #ifndef PRODUCT
kvn@3447 1284 } else {
duke@0 1285 st->print("movdq %s, %s\t# spill",
duke@0 1286 Matcher::regName[dst_first],
duke@0 1287 Matcher::regName[src_first]);
duke@0 1288 #endif
duke@0 1289 }
duke@0 1290 } else {
duke@0 1291 // 32-bit
duke@0 1292 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1293 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1294 if (cbuf) {
kvn@2953 1295 MacroAssembler _masm(cbuf);
kvn@2953 1296 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1297 #ifndef PRODUCT
kvn@3447 1298 } else {
duke@0 1299 st->print("movdl %s, %s\t# spill",
duke@0 1300 Matcher::regName[dst_first],
duke@0 1301 Matcher::regName[src_first]);
duke@0 1302 #endif
duke@0 1303 }
duke@0 1304 }
kvn@3447 1305 return 0;
duke@0 1306 } else if (dst_first_rc == rc_float) {
duke@0 1307 // xmm -> xmm
duke@0 1308 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1309 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1310 // 64-bit
duke@0 1311 if (cbuf) {
kvn@2953 1312 MacroAssembler _masm(cbuf);
kvn@2953 1313 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1314 #ifndef PRODUCT
kvn@3447 1315 } else {
duke@0 1316 st->print("%s %s, %s\t# spill",
duke@0 1317 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1318 Matcher::regName[dst_first],
duke@0 1319 Matcher::regName[src_first]);
duke@0 1320 #endif
duke@0 1321 }
duke@0 1322 } else {
duke@0 1323 // 32-bit
duke@0 1324 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1325 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1326 if (cbuf) {
kvn@2953 1327 MacroAssembler _masm(cbuf);
kvn@2953 1328 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1329 #ifndef PRODUCT
kvn@3447 1330 } else {
duke@0 1331 st->print("%s %s, %s\t# spill",
duke@0 1332 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1333 Matcher::regName[dst_first],
duke@0 1334 Matcher::regName[src_first]);
duke@0 1335 #endif
duke@0 1336 }
duke@0 1337 }
kvn@3447 1338 return 0;
duke@0 1339 }
duke@0 1340 }
duke@0 1341
duke@0 1342 assert(0," foo ");
duke@0 1343 Unimplemented();
duke@0 1344 return 0;
duke@0 1345 }
duke@0 1346
duke@0 1347 #ifndef PRODUCT
kvn@3447 1348 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
duke@0 1349 implementation(NULL, ra_, false, st);
duke@0 1350 }
duke@0 1351 #endif
duke@0 1352
kvn@3447 1353 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1354 implementation(&cbuf, ra_, false, NULL);
duke@0 1355 }
duke@0 1356
kvn@3447 1357 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
kvn@3447 1358 return MachNode::size(ra_);
duke@0 1359 }
duke@0 1360
duke@0 1361 //=============================================================================
duke@0 1362 #ifndef PRODUCT
duke@0 1363 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1364 {
duke@0 1365 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1366 int reg = ra_->get_reg_first(this);
duke@0 1367 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1368 Matcher::regName[reg], offset);
duke@0 1369 }
duke@0 1370 #endif
duke@0 1371
duke@0 1372 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1373 {
duke@0 1374 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1375 int reg = ra_->get_encode(this);
duke@0 1376 if (offset >= 0x80) {
duke@0 1377 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1378 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1379 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1380 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1381 emit_d32(cbuf, offset);
duke@0 1382 } else {
duke@0 1383 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1384 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1385 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1386 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1387 emit_d8(cbuf, offset);
duke@0 1388 }
duke@0 1389 }
duke@0 1390
duke@0 1391 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1392 {
duke@0 1393 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1394 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1395 }
duke@0 1396
duke@0 1397 //=============================================================================
duke@0 1398 #ifndef PRODUCT
duke@0 1399 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1400 {
ehelin@5259 1401 if (UseCompressedClassPointers) {
kvn@1491 1402 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
hseigel@5093 1403 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
kvn@1491 1404 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1405 } else {
kvn@1491 1406 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1407 "# Inline cache check");
coleenp@113 1408 }
duke@0 1409 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1410 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1411 }
duke@0 1412 #endif
duke@0 1413
duke@0 1414 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1415 {
duke@0 1416 MacroAssembler masm(&cbuf);
twisti@1668 1417 uint insts_size = cbuf.insts_size();
ehelin@5259 1418 if (UseCompressedClassPointers) {
coleenp@113 1419 masm.load_klass(rscratch1, j_rarg0);
never@304 1420 masm.cmpptr(rax, rscratch1);
coleenp@113 1421 } else {
never@304 1422 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1423 }
duke@0 1424
duke@0 1425 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1426
duke@0 1427 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1428 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1429 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1430 if (OptoBreakpoint) {
duke@0 1431 // Leave space for int3
kvn@1491 1432 nops_cnt -= 1;
duke@0 1433 }
kvn@1491 1434 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1435 if (nops_cnt > 0)
kvn@1491 1436 masm.nop(nops_cnt);
duke@0 1437 }
duke@0 1438
duke@0 1439 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1440 {
kvn@1491 1441 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1442 // the hard way
duke@0 1443 }
goetz@6189 1444
duke@0 1445
duke@0 1446 //=============================================================================
duke@0 1447
duke@0 1448 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1449 {
duke@0 1450 return regnum - 32; // The FP registers are in the second chunk
duke@0 1451 }
duke@0 1452
duke@0 1453 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1454 const bool Matcher::convL2FSupported(void) {
duke@0 1455 return true;
duke@0 1456 }
duke@0 1457
duke@0 1458 // Is this branch offset short enough that a short branch can be used?
duke@0 1459 //
duke@0 1460 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1461 // this method should return false for offset 0.
kvn@2614 1462 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1463 // The passed offset is relative to address of the branch.
kvn@2614 1464 // On 86 a branch displacement is calculated relative to address
kvn@2614 1465 // of a next instruction.
kvn@2614 1466 offset -= br_size;
kvn@2614 1467
never@415 1468 // the short version of jmpConUCF2 contains multiple branches,
never@415 1469 // making the reach slightly less
never@415 1470 if (rule == jmpConUCF2_rule)
never@415 1471 return (-126 <= offset && offset <= 125);
never@415 1472 return (-128 <= offset && offset <= 127);
duke@0 1473 }
duke@0 1474
duke@0 1475 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1476 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1477 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1478
duke@0 1479 // Probably always true, even if a temp register is required.
duke@0 1480 return true;
duke@0 1481 }
duke@0 1482
duke@0 1483 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1484 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1485
duke@0 1486 // Threshold size for cleararray.
duke@0 1487 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1488
kvn@2808 1489 // No additional cost for CMOVL.
kvn@2808 1490 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 1491
kvn@2808 1492 // No CMOVF/CMOVD with SSE2
kvn@2808 1493 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 1494
goetz@5982 1495 // Does the CPU require late expand (see block.cpp for description of late expand)?
goetz@5982 1496 const bool Matcher::require_postalloc_expand = false;
goetz@5982 1497
duke@0 1498 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1499 // to be subsumed into complex addressing expressions or compute them
duke@0 1500 // into registers? True for Intel but false for most RISCs
duke@0 1501 const bool Matcher::clone_shift_expressions = true;
duke@0 1502
roland@2248 1503 // Do we need to mask the count passed to shift instructions or does
roland@2248 1504 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 1505 const bool Matcher::need_masked_shift_count = false;
roland@2248 1506
kvn@1495 1507 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 1508 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 1509 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 1510 }
kvn@1495 1511
roland@3724 1512 bool Matcher::narrow_klass_use_complex_address() {
ehelin@5259 1513 assert(UseCompressedClassPointers, "only for compressed klass code");
roland@3724 1514 return (LogKlassAlignmentInBytes <= 3);
roland@3724 1515 }
roland@3724 1516
duke@0 1517 // Is it better to copy float constants, or load them directly from
duke@0 1518 // memory? Intel can load a float constant from a direct address,
duke@0 1519 // requiring no extra registers. Most RISCs will have to materialize
duke@0 1520 // an address into a register first, so they would do better to copy
duke@0 1521 // the constant from stack.
duke@0 1522 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 1523
duke@0 1524 // If CPU can load and store mis-aligned doubles directly then no
duke@0 1525 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 1526 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 1527 // C code as the Java calling convention forces doubles to be aligned.
duke@0 1528 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1529
duke@0 1530 // No-op on amd64
duke@0 1531 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 1532
duke@0 1533 // Advertise here if the CPU requires explicit rounding operations to
duke@0 1534 // implement the UseStrictFP mode.
duke@0 1535 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 1536
kvn@1274 1537 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 1538 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 1539 bool Matcher::float_in_double() { return false; }
kvn@1274 1540
duke@0 1541 // Do ints take an entire long register or just half?
duke@0 1542 const bool Matcher::int_in_long = true;
duke@0 1543
duke@0 1544 // Return whether or not this register is ever used as an argument.
duke@0 1545 // This function is used on startup to build the trampoline stubs in
duke@0 1546 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 1547 // call in the trampoline, and arguments in those registers not be
duke@0 1548 // available to the callee.
duke@0 1549 bool Matcher::can_be_java_arg(int reg)
duke@0 1550 {
duke@0 1551 return
kvn@3447 1552 reg == RDI_num || reg == RDI_H_num ||
kvn@3447 1553 reg == RSI_num || reg == RSI_H_num ||
kvn@3447 1554 reg == RDX_num || reg == RDX_H_num ||
kvn@3447 1555 reg == RCX_num || reg == RCX_H_num ||
kvn@3447 1556 reg == R8_num || reg == R8_H_num ||
kvn@3447 1557 reg == R9_num || reg == R9_H_num ||
kvn@3447 1558 reg == R12_num || reg == R12_H_num ||
kvn@3447 1559 reg == XMM0_num || reg == XMM0b_num ||
kvn@3447 1560 reg == XMM1_num || reg == XMM1b_num ||
kvn@3447 1561 reg == XMM2_num || reg == XMM2b_num ||
kvn@3447 1562 reg == XMM3_num || reg == XMM3b_num ||
kvn@3447 1563 reg == XMM4_num || reg == XMM4b_num ||
kvn@3447 1564 reg == XMM5_num || reg == XMM5b_num ||
kvn@3447 1565 reg == XMM6_num || reg == XMM6b_num ||
kvn@3447 1566 reg == XMM7_num || reg == XMM7b_num;
duke@0 1567 }
duke@0 1568
duke@0 1569 bool Matcher::is_spillable_arg(int reg)
duke@0 1570 {
duke@0 1571 return can_be_java_arg(reg);
duke@0 1572 }
duke@0 1573
kvn@1834 1574 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 1575 // In 64 bit mode a code which use multiply when
kvn@1834 1576 // devisor is constant is faster than hardware
kvn@1834 1577 // DIV instruction (it uses MulHiL).
kvn@1834 1578 return false;
kvn@1834 1579 }
kvn@1834 1580
duke@0 1581 // Register for DIVI projection of divmodI
duke@0 1582 RegMask Matcher::divI_proj_mask() {
roland@2882 1583 return INT_RAX_REG_mask();
duke@0 1584 }
duke@0 1585
duke@0 1586 // Register for MODI projection of divmodI
duke@0 1587 RegMask Matcher::modI_proj_mask() {
roland@2882 1588 return INT_RDX_REG_mask();
duke@0 1589 }
duke@0 1590
duke@0 1591 // Register for DIVL projection of divmodL
duke@0 1592 RegMask Matcher::divL_proj_mask() {
roland@2882 1593 return LONG_RAX_REG_mask();
duke@0 1594 }
duke@0 1595
duke@0 1596 // Register for MODL projection of divmodL
duke@0 1597 RegMask Matcher::modL_proj_mask() {
roland@2882 1598 return LONG_RDX_REG_mask();
duke@0 1599 }
duke@0 1600
twisti@1137 1601 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
roland@2882 1602 return PTR_RBP_REG_mask();
twisti@1137 1603 }
twisti@1137 1604
duke@0 1605 %}
duke@0 1606
duke@0 1607 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1608 // This block specifies the encoding classes used by the compiler to
duke@0 1609 // output byte streams. Encoding classes are parameterized macros
duke@0 1610 // used by Machine Instruction Nodes in order to generate the bit
duke@0 1611 // encoding of the instruction. Operands specify their base encoding
duke@0 1612 // interface with the interface keyword. There are currently
duke@0 1613 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 1614 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 1615 // which returns its register number when queried. CONST_INTER causes
duke@0 1616 // an operand to generate a function which returns the value of the
duke@0 1617 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 1618 // four functions which return the Base Register, the Index Register,
duke@0 1619 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 1620 // COND_INTER causes an operand to generate six functions which return
duke@0 1621 // the encoding code (ie - encoding bits for the instruction)
duke@0 1622 // associated with each basic boolean condition for a conditional
duke@0 1623 // instruction.
duke@0 1624 //
duke@0 1625 // Instructions specify two basic values for encoding. Again, a
duke@0 1626 // function is available to check if the constant displacement is an
duke@0 1627 // oop. They use the ins_encode keyword to specify their encoding
duke@0 1628 // classes (which must be a sequence of enc_class names, and their
duke@0 1629 // parameters, specified in the encoding block), and they use the
duke@0 1630 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1631 // tertiary opcode. Only the opcode sections which a particular
duke@0 1632 // instruction needs for encoding need to be specified.
duke@0 1633 encode %{
duke@0 1634 // Build emit functions for each basic byte or larger field in the
duke@0 1635 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 1636 // from C++ code in the enc_class source block. Emit functions will
duke@0 1637 // live in the main source block for now. In future, we can
duke@0 1638 // generalize this by adding a syntax that specifies the sizes of
duke@0 1639 // fields in an order, so that the adlc can build the emit functions
duke@0 1640 // automagically
duke@0 1641
duke@0 1642 // Emit primary opcode
duke@0 1643 enc_class OpcP
duke@0 1644 %{
duke@0 1645 emit_opcode(cbuf, $primary);
duke@0 1646 %}
duke@0 1647
duke@0 1648 // Emit secondary opcode
duke@0 1649 enc_class OpcS
duke@0 1650 %{
duke@0 1651 emit_opcode(cbuf, $secondary);
duke@0 1652 %}
duke@0 1653
duke@0 1654 // Emit tertiary opcode
duke@0 1655 enc_class OpcT
duke@0 1656 %{
duke@0 1657 emit_opcode(cbuf, $tertiary);
duke@0 1658 %}
duke@0 1659
duke@0 1660 // Emit opcode directly
duke@0 1661 enc_class Opcode(immI d8)
duke@0 1662 %{
duke@0 1663 emit_opcode(cbuf, $d8$$constant);
duke@0 1664 %}
duke@0 1665
duke@0 1666 // Emit size prefix
duke@0 1667 enc_class SizePrefix
duke@0 1668 %{
duke@0 1669 emit_opcode(cbuf, 0x66);
duke@0 1670 %}
duke@0 1671
duke@0 1672 enc_class reg(rRegI reg)
duke@0 1673 %{
duke@0 1674 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 1675 %}
duke@0 1676
duke@0 1677 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 1678 %{
duke@0 1679 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1680 %}
duke@0 1681
duke@0 1682 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 1683 %{
duke@0 1684 emit_opcode(cbuf, $opcode$$constant);
duke@0 1685 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1686 %}
duke@0 1687
duke@0 1688 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 1689 %{
duke@0 1690 // Full implementation of Java idiv and irem; checks for
duke@0 1691 // special case as described in JVM spec., p.243 & p.271.
duke@0 1692 //
duke@0 1693 // normal case special case
duke@0 1694 //
duke@0 1695 // input : rax: dividend min_int
duke@0 1696 // reg: divisor -1
duke@0 1697 //
duke@0 1698 // output: rax: quotient (= rax idiv reg) min_int
duke@0 1699 // rdx: remainder (= rax irem reg) 0
duke@0 1700 //
duke@0 1701 // Code sequnce:
duke@0 1702 //
duke@0 1703 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 1704 // 5: 75 07/08 jne e <normal>
duke@0 1705 // 7: 33 d2 xor %edx,%edx
duke@0 1706 // [div >= 8 -> offset + 1]
duke@0 1707 // [REX_B]
duke@0 1708 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1709 // c: 74 03/04 je 11 <done>
duke@0 1710 // 000000000000000e <normal>:
duke@0 1711 // e: 99 cltd
duke@0 1712 // [div >= 8 -> offset + 1]
duke@0 1713 // [REX_B]
duke@0 1714 // f: f7 f9 idiv $div
duke@0 1715 // 0000000000000011 <done>:
duke@0 1716
duke@0 1717 // cmp $0x80000000,%eax
duke@0 1718 emit_opcode(cbuf, 0x3d);
duke@0 1719 emit_d8(cbuf, 0x00);
duke@0 1720 emit_d8(cbuf, 0x00);
duke@0 1721 emit_d8(cbuf, 0x00);
duke@0 1722 emit_d8(cbuf, 0x80);
duke@0 1723
duke@0 1724 // jne e <normal>
duke@0 1725 emit_opcode(cbuf, 0x75);
duke@0 1726 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 1727
duke@0 1728 // xor %edx,%edx
duke@0 1729 emit_opcode(cbuf, 0x33);
duke@0 1730 emit_d8(cbuf, 0xD2);
duke@0 1731
duke@0 1732 // cmp $0xffffffffffffffff,%ecx
duke@0 1733 if ($div$$reg >= 8) {
duke@0 1734 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1735 }
duke@0 1736 emit_opcode(cbuf, 0x83);
duke@0 1737 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1738 emit_d8(cbuf, 0xFF);
duke@0 1739
duke@0 1740 // je 11 <done>
duke@0 1741 emit_opcode(cbuf, 0x74);
duke@0 1742 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 1743
duke@0 1744 // <normal>
duke@0 1745 // cltd
duke@0 1746 emit_opcode(cbuf, 0x99);
duke@0 1747
duke@0 1748 // idivl (note: must be emitted by the user of this rule)
duke@0 1749 // <done>
duke@0 1750 %}
duke@0 1751
duke@0 1752 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 1753 %{
duke@0 1754 // Full implementation of Java ldiv and lrem; checks for
duke@0 1755 // special case as described in JVM spec., p.243 & p.271.
duke@0 1756 //
duke@0 1757 // normal case special case
duke@0 1758 //
duke@0 1759 // input : rax: dividend min_long
duke@0 1760 // reg: divisor -1
duke@0 1761 //
duke@0 1762 // output: rax: quotient (= rax idiv reg) min_long
duke@0 1763 // rdx: remainder (= rax irem reg) 0
duke@0 1764 //
duke@0 1765 // Code sequnce:
duke@0 1766 //
duke@0 1767 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 1768 // 7: 00 00 80
duke@0 1769 // a: 48 39 d0 cmp %rdx,%rax
duke@0 1770 // d: 75 08 jne 17 <normal>
duke@0 1771 // f: 33 d2 xor %edx,%edx
duke@0 1772 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1773 // 15: 74 05 je 1c <done>
duke@0 1774 // 0000000000000017 <normal>:
duke@0 1775 // 17: 48 99 cqto
duke@0 1776 // 19: 48 f7 f9 idiv $div
duke@0 1777 // 000000000000001c <done>:
duke@0 1778
duke@0 1779 // mov $0x8000000000000000,%rdx
duke@0 1780 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1781 emit_opcode(cbuf, 0xBA);
duke@0 1782 emit_d8(cbuf, 0x00);
duke@0 1783 emit_d8(cbuf, 0x00);
duke@0 1784 emit_d8(cbuf, 0x00);
duke@0 1785 emit_d8(cbuf, 0x00);
duke@0 1786 emit_d8(cbuf, 0x00);
duke@0 1787 emit_d8(cbuf, 0x00);
duke@0 1788 emit_d8(cbuf, 0x00);
duke@0 1789 emit_d8(cbuf, 0x80);
duke@0 1790
duke@0 1791 // cmp %rdx,%rax
duke@0 1792 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1793 emit_opcode(cbuf, 0x39);
duke@0 1794 emit_d8(cbuf, 0xD0);
duke@0 1795
duke@0 1796 // jne 17 <normal>
duke@0 1797 emit_opcode(cbuf, 0x75);
duke@0 1798 emit_d8(cbuf, 0x08);
duke@0 1799
duke@0 1800 // xor %edx,%edx
duke@0 1801 emit_opcode(cbuf, 0x33);
duke@0 1802 emit_d8(cbuf, 0xD2);
duke@0 1803
duke@0 1804 // cmp $0xffffffffffffffff,$div
duke@0 1805 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 1806 emit_opcode(cbuf, 0x83);
duke@0 1807 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1808 emit_d8(cbuf, 0xFF);
duke@0 1809
duke@0 1810 // je 1e <done>
duke@0 1811 emit_opcode(cbuf, 0x74);
duke@0 1812 emit_d8(cbuf, 0x05);
duke@0 1813
duke@0 1814 // <normal>
duke@0 1815 // cqto
duke@0 1816 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1817 emit_opcode(cbuf, 0x99);
duke@0 1818
duke@0 1819 // idivq (note: must be emitted by the user of this rule)
duke@0 1820 // <done>
duke@0 1821 %}
duke@0 1822
duke@0 1823 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 1824 enc_class OpcSE(immI imm)
duke@0 1825 %{
duke@0 1826 // Emit primary opcode and set sign-extend bit
duke@0 1827 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1828 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1829 emit_opcode(cbuf, $primary | 0x02);
duke@0 1830 } else {
duke@0 1831 // 32-bit immediate
duke@0 1832 emit_opcode(cbuf, $primary);
duke@0 1833 }
duke@0 1834 %}
duke@0 1835
duke@0 1836 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 1837 %{
duke@0 1838 // OpcSEr/m
duke@0 1839 int dstenc = $dst$$reg;
duke@0 1840 if (dstenc >= 8) {
duke@0 1841 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1842 dstenc -= 8;
duke@0 1843 }
duke@0 1844 // Emit primary opcode and set sign-extend bit
duke@0 1845 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1846 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1847 emit_opcode(cbuf, $primary | 0x02);
duke@0 1848 } else {
duke@0 1849 // 32-bit immediate
duke@0 1850 emit_opcode(cbuf, $primary);
duke@0 1851 }
duke@0 1852 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1853 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1854 %}
duke@0 1855
duke@0 1856 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 1857 %{
duke@0 1858 // OpcSEr/m
duke@0 1859 int dstenc = $dst$$reg;
duke@0 1860 if (dstenc < 8) {
duke@0 1861 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1862 } else {
duke@0 1863 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 1864 dstenc -= 8;
duke@0 1865 }
duke@0 1866 // Emit primary opcode and set sign-extend bit
duke@0 1867 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1868 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1869 emit_opcode(cbuf, $primary | 0x02);
duke@0 1870 } else {
duke@0 1871 // 32-bit immediate
duke@0 1872 emit_opcode(cbuf, $primary);
duke@0 1873 }
duke@0 1874 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1875 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1876 %}
duke@0 1877
duke@0 1878 enc_class Con8or32(immI imm)
duke@0 1879 %{
duke@0 1880 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1881 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1882 $$$emit8$imm$$constant;
duke@0 1883 } else {
duke@0 1884 // 32-bit immediate
duke@0 1885 $$$emit32$imm$$constant;
duke@0 1886 }
duke@0 1887 %}
duke@0 1888
duke@0 1889 enc_class opc2_reg(rRegI dst)
duke@0 1890 %{
duke@0 1891 // BSWAP
duke@0 1892 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 1893 %}
duke@0 1894
duke@0 1895 enc_class opc3_reg(rRegI dst)
duke@0 1896 %{
duke@0 1897 // BSWAP
duke@0 1898 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 1899 %}
duke@0 1900
duke@0 1901 enc_class reg_opc(rRegI div)
duke@0 1902 %{
duke@0 1903 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 1904 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 1905 %}
duke@0 1906
duke@0 1907 enc_class enc_cmov(cmpOp cop)
duke@0 1908 %{
duke@0 1909 // CMOV
duke@0 1910 $$$emit8$primary;
duke@0 1911 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 1912 %}
duke@0 1913
duke@0 1914 enc_class enc_PartialSubtypeCheck()
duke@0 1915 %{
duke@0 1916 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 1917 Register Rrax = as_Register(RAX_enc); // super class
duke@0 1918 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 1919 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 1920 Label miss;
jrose@644 1921 const bool set_cond_codes = true;
duke@0 1922
duke@0 1923 MacroAssembler _masm(&cbuf);
jrose@644 1924 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 1925 NULL, &miss,
jrose@644 1926 /*set_cond_codes:*/ true);
duke@0 1927 if ($primary) {
never@304 1928 __ xorptr(Rrdi, Rrdi);
duke@0 1929 }
duke@0 1930 __ bind(miss);
duke@0 1931 %}
duke@0 1932
kvn@4438 1933 enc_class clear_avx %{
kvn@4438 1934 debug_only(int off0 = cbuf.insts_size());
kvn@4438 1935 if (ra_->C->max_vector_size() > 16) {
kvn@4438 1936 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 1937 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 1938 MacroAssembler _masm(&cbuf);
kvn@4438 1939 __ vzeroupper();
kvn@4438 1940 }
kvn@4438 1941 debug_only(int off1 = cbuf.insts_size());
kvn@4438 1942 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
kvn@4438 1943 %}
kvn@4438 1944
kvn@4438 1945 enc_class Java_To_Runtime(method meth) %{
kvn@4438 1946 // No relocation needed
kvn@4438 1947 MacroAssembler _masm(&cbuf);
kvn@4438 1948 __ mov64(r10, (int64_t) $meth$$method);
kvn@4438 1949 __ call(r10);
kvn@4438 1950 %}
kvn@4438 1951
duke@0 1952 enc_class Java_To_Interpreter(method meth)
duke@0 1953 %{
duke@0 1954 // CALL Java_To_Interpreter
duke@0 1955 // This is the instruction starting address for relocation info.
twisti@1668 1956 cbuf.set_insts_mark();
duke@0 1957 $$$emit8$primary;
duke@0 1958 // CALL directly to the runtime
duke@0 1959 emit_d32_reloc(cbuf,
twisti@1668 1960 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 1961 runtime_call_Relocation::spec(),
duke@0 1962 RELOC_DISP32);
duke@0 1963 %}
duke@0 1964
duke@0 1965 enc_class Java_Static_Call(method meth)
duke@0 1966 %{
duke@0 1967 // JAVA STATIC CALL
duke@0 1968 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 1969 // determine who we intended to call.
twisti@1668 1970 cbuf.set_insts_mark();
duke@0 1971 $$$emit8$primary;
duke@0 1972
duke@0 1973 if (!_method) {
duke@0 1974 emit_d32_reloc(cbuf,
twisti@1668 1975 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 1976 runtime_call_Relocation::spec(),
duke@0 1977 RELOC_DISP32);
duke@0 1978 } else if (_optimized_virtual) {
duke@0 1979 emit_d32_reloc(cbuf,
twisti@1668 1980 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 1981 opt_virtual_call_Relocation::spec(),
duke@0 1982 RELOC_DISP32);
duke@0 1983 } else {
duke@0 1984 emit_d32_reloc(cbuf,
twisti@1668 1985 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 1986 static_call_Relocation::spec(),
duke@0 1987 RELOC_DISP32);
duke@0 1988 }
duke@0 1989 if (_method) {
dlong@4565 1990 // Emit stub for static call.
dlong@4565 1991 CompiledStaticCall::emit_to_interp_stub(cbuf);
duke@0 1992 }
duke@0 1993 %}
duke@0 1994
coleenp@3602 1995 enc_class Java_Dynamic_Call(method meth) %{
coleenp@3602 1996 MacroAssembler _masm(&cbuf);
coleenp@3602 1997 __ ic_call((address)$meth$$method);
duke@0 1998 %}
duke@0 1999
duke@0 2000 enc_class Java_Compiled_Call(method meth)
duke@0 2001 %{
duke@0 2002 // JAVA COMPILED CALL
coleenp@3602 2003 int disp = in_bytes(Method:: from_compiled_offset());
duke@0 2004
duke@0 2005 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2006 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2007
duke@0 2008 // callq *disp(%rax)
twisti@1668 2009 cbuf.set_insts_mark();
duke@0 2010 $$$emit8$primary;
duke@0 2011 if (disp < 0x80) {
duke@0 2012 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2013 emit_d8(cbuf, disp); // Displacement
duke@0 2014 } else {
duke@0 2015 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2016 emit_d32(cbuf, disp); // Displacement
duke@0 2017 }
duke@0 2018 %}
duke@0 2019
duke@0 2020 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2021 %{
duke@0 2022 // SAL, SAR, SHR
duke@0 2023 int dstenc = $dst$$reg;
duke@0 2024 if (dstenc >= 8) {
duke@0 2025 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2026 dstenc -= 8;
duke@0 2027 }
duke@0 2028 $$$emit8$primary;
duke@0 2029 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2030 $$$emit8$shift$$constant;
duke@0 2031 %}
duke@0 2032
duke@0 2033 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2034 %{
duke@0 2035 // SAL, SAR, SHR
duke@0 2036 int dstenc = $dst$$reg;
duke@0 2037 if (dstenc < 8) {
duke@0 2038 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2039 } else {
duke@0 2040 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2041 dstenc -= 8;
duke@0 2042 }
duke@0 2043 $$$emit8$primary;
duke@0 2044 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2045 $$$emit8$shift$$constant;
duke@0 2046 %}
duke@0 2047
duke@0 2048 enc_class load_immI(rRegI dst, immI src)
duke@0 2049 %{
duke@0 2050 int dstenc = $dst$$reg;
duke@0 2051 if (dstenc >= 8) {
duke@0 2052 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2053 dstenc -= 8;
duke@0 2054 }
duke@0 2055 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2056 $$$emit32$src$$constant;
duke@0 2057 %}
duke@0 2058
duke@0 2059 enc_class load_immL(rRegL dst, immL src)
duke@0 2060 %{
duke@0 2061 int dstenc = $dst$$reg;
duke@0 2062 if (dstenc < 8) {
duke@0 2063 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2064 } else {
duke@0 2065 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2066 dstenc -= 8;
duke@0 2067 }
duke@0 2068 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2069 emit_d64(cbuf, $src$$constant);
duke@0 2070 %}
duke@0 2071
duke@0 2072 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2073 %{
duke@0 2074 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2075 int dstenc = $dst$$reg;
duke@0 2076 if (dstenc >= 8) {
duke@0 2077 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2078 dstenc -= 8;
duke@0 2079 }
duke@0 2080 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2081 $$$emit32$src$$constant;
duke@0 2082 %}
duke@0 2083
duke@0 2084 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2085 %{
duke@0 2086 int dstenc = $dst$$reg;
duke@0 2087 if (dstenc < 8) {
duke@0 2088 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2089 } else {
duke@0 2090 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2091 dstenc -= 8;
duke@0 2092 }
duke@0 2093 emit_opcode(cbuf, 0xC7);
duke@0 2094 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2095 $$$emit32$src$$constant;
duke@0 2096 %}
duke@0 2097
duke@0 2098 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2099 %{
duke@0 2100 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2101 int dstenc = $dst$$reg;
duke@0 2102 if (dstenc >= 8) {
duke@0 2103 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2104 dstenc -= 8;
duke@0 2105 }
duke@0 2106 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2107 $$$emit32$src$$constant;
duke@0 2108 %}
duke@0 2109
duke@0 2110 enc_class load_immP(rRegP dst, immP src)
duke@0 2111 %{
duke@0 2112 int dstenc = $dst$$reg;
duke@0 2113 if (dstenc < 8) {
duke@0 2114 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2115 } else {
duke@0 2116 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2117 dstenc -= 8;
duke@0 2118 }
duke@0 2119 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2120 // This next line should be generated from ADLC
coleenp@3602 2121 if ($src->constant_reloc() != relocInfo::none) {
coleenp@3602 2122 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
duke@0 2123 } else {
duke@0 2124 emit_d64(cbuf, $src$$constant);
duke@0 2125 }
duke@0 2126 %}
duke@0 2127
duke@0 2128 enc_class Con32(immI src)
duke@0 2129 %{
duke@0 2130 // Output immediate
duke@0 2131 $$$emit32$src$$constant;
duke@0 2132 %}
duke@0 2133
duke@0 2134 enc_class Con32F_as_bits(immF src)
duke@0 2135 %{
duke@0 2136 // Output Float immediate bits
duke@0 2137 jfloat jf = $src$$constant;
duke@0 2138 jint jf_as_bits = jint_cast(jf);
duke@0 2139 emit_d32(cbuf, jf_as_bits);
duke@0 2140 %}
duke@0 2141
duke@0 2142 enc_class Con16(immI src)
duke@0 2143 %{
duke@0 2144 // Output immediate
duke@0 2145 $$$emit16$src$$constant;
duke@0 2146 %}
duke@0 2147
duke@0 2148 // How is this different from Con32??? XXX
duke@0 2149 enc_class Con_d32(immI src)
duke@0 2150 %{
duke@0 2151 emit_d32(cbuf,$src$$constant);
duke@0 2152 %}
duke@0 2153
duke@0 2154 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2155 // Output immediate memory reference
duke@0 2156 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2157 emit_d32(cbuf, 0x00);
duke@0 2158 %}
duke@0 2159
duke@0 2160 enc_class lock_prefix()
duke@0 2161 %{
duke@0 2162 if (os::is_MP()) {
duke@0 2163 emit_opcode(cbuf, 0xF0); // lock
duke@0 2164 }
duke@0 2165 %}
duke@0 2166
duke@0 2167 enc_class REX_mem(memory mem)
duke@0 2168 %{
duke@0 2169 if ($mem$$base >= 8) {
duke@0 2170 if ($mem$$index < 8) {
duke@0 2171 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2172 } else {
duke@0 2173 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2174 }
duke@0 2175 } else {
duke@0 2176 if ($mem$$index >= 8) {
duke@0 2177 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2178 }
duke@0 2179 }
duke@0 2180 %}
duke@0 2181
duke@0 2182 enc_class REX_mem_wide(memory mem)
duke@0 2183 %{
duke@0 2184 if ($mem$$base >= 8) {
duke@0 2185 if ($mem$$index < 8) {
duke@0 2186 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2187 } else {
duke@0 2188 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2189 }
duke@0 2190 } else {
duke@0 2191 if ($mem$$index < 8) {
duke@0 2192 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2193 } else {
duke@0 2194 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2195 }
duke@0 2196 }
duke@0 2197 %}
duke@0 2198
duke@0 2199 // for byte regs
duke@0 2200 enc_class REX_breg(rRegI reg)
duke@0 2201 %{
duke@0 2202 if ($reg$$reg >= 4) {
duke@0 2203 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2204 }
duke@0 2205 %}
duke@0 2206
duke@0 2207 // for byte regs
duke@0 2208 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2209 %{
duke@0 2210 if ($dst$$reg < 8) {
duke@0 2211 if ($src$$reg >= 4) {
duke@0 2212 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2213 }
duke@0 2214 } else {
duke@0 2215 if ($src$$reg < 8) {
duke@0 2216 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2217 } else {
duke@0 2218 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2219 }
duke@0 2220 }
duke@0 2221 %}
duke@0 2222
duke@0 2223 // for byte regs
duke@0 2224 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2225 %{
duke@0 2226 if ($reg$$reg < 8) {
duke@0 2227 if ($mem$$base < 8) {
duke@0 2228 if ($mem$$index >= 8) {
duke@0 2229 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2230 } else if ($reg$$reg >= 4) {
duke@0 2231 emit_opcode(cbuf, Assembler::REX);
duke@0 2232 }
duke@0 2233 } else {
duke@0 2234 if ($mem$$index < 8) {
duke@0 2235 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2236 } else {
duke@0 2237 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2238 }
duke@0 2239 }
duke@0 2240 } else {
duke@0 2241 if ($mem$$base < 8) {
duke@0 2242 if ($mem$$index < 8) {
duke@0 2243 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2244 } else {
duke@0 2245 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2246 }
duke@0 2247 } else {
duke@0 2248 if ($mem$$index < 8) {
duke@0 2249 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2250 } else {
duke@0 2251 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2252 }
duke@0 2253 }
duke@0 2254 }
duke@0 2255 %}
duke@0 2256
duke@0 2257 enc_class REX_reg(rRegI reg)
duke@0 2258 %{
duke@0 2259 if ($reg$$reg >= 8) {
duke@0 2260 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2261 }
duke@0 2262 %}
duke@0 2263
duke@0 2264 enc_class REX_reg_wide(rRegI reg)
duke@0 2265 %{
duke@0 2266 if ($reg$$reg < 8) {
duke@0 2267 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2268 } else {
duke@0 2269 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2270 }
duke@0 2271 %}
duke@0 2272
duke@0 2273 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2274 %{
duke@0 2275 if ($dst$$reg < 8) {
duke@0 2276 if ($src$$reg >= 8) {
duke@0 2277 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2278 }
duke@0 2279 } else {
duke@0 2280 if ($src$$reg < 8) {
duke@0 2281 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2282 } else {
duke@0 2283 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2284 }
duke@0 2285 }
duke@0 2286 %}
duke@0 2287
duke@0 2288 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2289 %{
duke@0 2290 if ($dst$$reg < 8) {
duke@0 2291 if ($src$$reg < 8) {
duke@0 2292 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2293 } else {
duke@0 2294 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2295 }
duke@0 2296 } else {
duke@0 2297 if ($src$$reg < 8) {
duke@0 2298 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2299 } else {
duke@0 2300 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2301 }
duke@0 2302 }
duke@0 2303 %}
duke@0 2304
duke@0 2305 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 2306 %{
duke@0 2307 if ($reg$$reg < 8) {
duke@0 2308 if ($mem$$base < 8) {
duke@0 2309 if ($mem$$index >= 8) {
duke@0 2310 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2311 }
duke@0 2312 } else {
duke@0 2313 if ($mem$$index < 8) {
duke@0 2314 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2315 } else {
duke@0 2316 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2317 }
duke@0 2318 }
duke@0 2319 } else {
duke@0 2320 if ($mem$$base < 8) {
duke@0 2321 if ($mem$$index < 8) {
duke@0 2322 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2323 } else {
duke@0 2324 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2325 }
duke@0 2326 } else {
duke@0 2327 if ($mem$$index < 8) {
duke@0 2328 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2329 } else {
duke@0 2330 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2331 }
duke@0 2332 }
duke@0 2333 }
duke@0 2334 %}
duke@0 2335
duke@0 2336 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 2337 %{
duke@0 2338 if ($reg$$reg < 8) {
duke@0 2339 if ($mem$$base < 8) {
duke@0 2340 if ($mem$$index < 8) {
duke@0 2341 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2342 } else {
duke@0 2343 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2344 }
duke@0 2345 } else {
duke@0 2346 if ($mem$$index < 8) {
duke@0 2347 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2348 } else {
duke@0 2349 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2350 }
duke@0 2351 }
duke@0 2352 } else {
duke@0 2353 if ($mem$$base < 8) {
duke@0 2354 if ($mem$$index < 8) {
duke@0 2355 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2356 } else {
duke@0 2357 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 2358 }
duke@0 2359 } else {
duke@0 2360 if ($mem$$index < 8) {
duke@0 2361 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2362 } else {
duke@0 2363 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 2364 }
duke@0 2365 }
duke@0 2366 }
duke@0 2367 %}
duke@0 2368
duke@0 2369 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 2370 %{
duke@0 2371 // High registers handle in encode_RegMem
duke@0 2372 int reg = $ereg$$reg;
duke@0 2373 int base = $mem$$base;
duke@0 2374 int index = $mem$$index;
duke@0 2375 int scale = $mem$$scale;
duke@0 2376 int disp = $mem$$disp;
coleenp@3602 2377 relocInfo::relocType disp_reloc = $mem->disp_reloc();
coleenp@3602 2378
coleenp@3602 2379 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
duke@0 2380 %}
duke@0 2381
duke@0 2382 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 2383 %{
duke@0 2384 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 2385
duke@0 2386 // High registers handle in encode_RegMem
duke@0 2387 int base = $mem$$base;
duke@0 2388 int index = $mem$$index;
duke@0 2389 int scale = $mem$$scale;
duke@0 2390 int displace = $mem$$disp;
duke@0 2391
coleenp@3602 2392 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
duke@0 2393 // working with static
duke@0 2394 // globals
duke@0 2395 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
coleenp@3602 2396 disp_reloc);
duke@0 2397 %}
duke@0 2398
duke@0 2399 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 2400 %{
duke@0 2401 int reg_encoding = $dst$$reg;
duke@0 2402 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 2403 int index = 0x04; // 0x04 indicates no index
duke@0 2404 int scale = 0x00; // 0x00 indicates no scale
duke@0 2405 int displace = $src1$$constant; // 0x00 indicates no displacement
coleenp@3602 2406 relocInfo::relocType disp_reloc = relocInfo::none;
duke@0 2407 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
coleenp@3602 2408 disp_reloc);
duke@0 2409 %}
duke@0 2410
duke@0 2411 enc_class neg_reg(rRegI dst)
duke@0 2412 %{
duke@0 2413 int dstenc = $dst$$reg;
duke@0 2414 if (dstenc >= 8) {
duke@0 2415 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2416 dstenc -= 8;
duke@0 2417 }
duke@0 2418 // NEG $dst
duke@0 2419 emit_opcode(cbuf, 0xF7);
duke@0 2420 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2421 %}
duke@0 2422
duke@0 2423 enc_class neg_reg_wide(rRegI dst)
duke@0 2424 %{
duke@0 2425 int dstenc = $dst$$reg;
duke@0 2426 if (dstenc < 8) {
duke@0 2427 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2428 } else {
duke@0 2429 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2430 dstenc -= 8;
duke@0 2431 }
duke@0 2432 // NEG $dst
duke@0 2433 emit_opcode(cbuf, 0xF7);
duke@0 2434 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2435 %}
duke@0 2436
duke@0 2437 enc_class setLT_reg(rRegI dst)
duke@0 2438 %{
duke@0 2439 int dstenc = $dst$$reg;
duke@0 2440 if (dstenc >= 8) {
duke@0 2441 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2442 dstenc -= 8;
duke@0 2443 } else if (dstenc >= 4) {
duke@0 2444 emit_opcode(cbuf, Assembler::REX);
duke@0 2445 }
duke@0 2446 // SETLT $dst
duke@0 2447 emit_opcode(cbuf, 0x0F);
duke@0 2448 emit_opcode(cbuf, 0x9C);
duke@0 2449 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2450 %}
duke@0 2451
duke@0 2452 enc_class setNZ_reg(rRegI dst)
duke@0 2453 %{
duke@0 2454 int dstenc = $dst$$reg;
duke@0 2455 if (dstenc >= 8) {
duke@0 2456 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2457 dstenc -= 8;
duke@0 2458 } else if (dstenc >= 4) {
duke@0 2459 emit_opcode(cbuf, Assembler::REX);
duke@0 2460 }
duke@0 2461 // SETNZ $dst
duke@0 2462 emit_opcode(cbuf, 0x0F);
duke@0 2463 emit_opcode(cbuf, 0x95);
duke@0 2464 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2465 %}
duke@0 2466
duke@0 2467
duke@0 2468 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 2469 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 2470 %{
duke@0 2471 int src1enc = $src1$$reg;
duke@0 2472 int src2enc = $src2$$reg;
duke@0 2473 int dstenc = $dst$$reg;
duke@0 2474
duke@0 2475 // cmpq $src1, $src2
duke@0 2476 if (src1enc < 8) {
duke@0 2477 if (src2enc < 8) {
duke@0 2478 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2479 } else {
duke@0 2480 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2481 }
duke@0 2482 } else {
duke@0 2483 if (src2enc < 8) {
duke@0 2484 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2485 } else {
duke@0 2486 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2487 }
duke@0 2488 }
duke@0 2489 emit_opcode(cbuf, 0x3B);
duke@0 2490 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 2491
duke@0 2492 // movl $dst, -1
duke@0 2493 if (dstenc >= 8) {
duke@0 2494 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2495 }
duke@0 2496 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2497 emit_d32(cbuf, -1);
duke@0 2498
duke@0 2499 // jl,s done
duke@0 2500 emit_opcode(cbuf, 0x7C);
duke@0 2501 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2502
duke@0 2503 // setne $dst
duke@0 2504 if (dstenc >= 4) {
duke@0 2505 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2506 }
duke@0 2507 emit_opcode(cbuf, 0x0F);
duke@0 2508 emit_opcode(cbuf, 0x95);
duke@0 2509 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2510
duke@0 2511 // movzbl $dst, $dst
duke@0 2512 if (dstenc >= 4) {
duke@0 2513 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2514 }
duke@0 2515 emit_opcode(cbuf, 0x0F);
duke@0 2516 emit_opcode(cbuf, 0xB6);
duke@0 2517 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2518 %}
duke@0 2519
duke@0 2520 enc_class Push_ResultXD(regD dst) %{
kvn@2953 2521 MacroAssembler _masm(&cbuf);
kvn@2953 2522 __ fstp_d(Address(rsp, 0));
kvn@2953 2523 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
kvn@2953 2524 __ addptr(rsp, 8);
duke@0 2525 %}
duke@0 2526
duke@0 2527 enc_class Push_SrcXD(regD src) %{
duke@0 2528 MacroAssembler _masm(&cbuf);
kvn@2953 2529 __ subptr(rsp, 8);
kvn@2953 2530 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
kvn@2953 2531 __ fld_d(Address(rsp, 0));
kvn@2953 2532 %}
kvn@2953 2533
duke@0 2534
duke@0 2535 enc_class enc_rethrow()
duke@0 2536 %{
twisti@1668 2537 cbuf.set_insts_mark();
duke@0 2538 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 2539 emit_d32_reloc(cbuf,
twisti@1668 2540 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 2541 runtime_call_Relocation::spec(),
duke@0 2542 RELOC_DISP32);
duke@0 2543 %}
duke@0 2544
duke@0 2545 %}
duke@0 2546
duke@0 2547
coleenp@113 2548
duke@0 2549 //----------FRAME--------------------------------------------------------------
duke@0 2550 // Definition of frame structure and management information.
duke@0 2551 //
duke@0 2552 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 2553 // | (to get allocators register number
duke@0 2554 // G Owned by | | v add OptoReg::stack0())
duke@0 2555 // r CALLER | |
duke@0 2556 // o | +--------+ pad to even-align allocators stack-slot
duke@0 2557 // w V | pad0 | numbers; owned by CALLER
duke@0 2558 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 2559 // h ^ | in | 5
duke@0 2560 // | | args | 4 Holes in incoming args owned by SELF
duke@0 2561 // | | | | 3
duke@0 2562 // | | +--------+
duke@0 2563 // V | | old out| Empty on Intel, window on Sparc
duke@0 2564 // | old |preserve| Must be even aligned.
duke@0 2565 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 2566 // | | in | 3 area for Intel ret address
duke@0 2567 // Owned by |preserve| Empty on Sparc.
duke@0 2568 // SELF +--------+
duke@0 2569 // | | pad2 | 2 pad to align old SP
duke@0 2570 // | +--------+ 1
duke@0 2571 // | | locks | 0
duke@0 2572 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 2573 // | | pad1 | 11 pad to align new SP
duke@0 2574 // | +--------+
duke@0 2575 // | | | 10
duke@0 2576 // | | spills | 9 spills
duke@0 2577 // V | | 8 (pad0 slot for callee)
duke@0 2578 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 2579 // ^ | out | 7
duke@0 2580 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 2581 // Owned by +--------+
duke@0 2582 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 2583 // | new |preserve| Must be even-aligned.
duke@0 2584 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 2585 // | | |
duke@0 2586 //
duke@0 2587 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 2588 // known from SELF's arguments and the Java calling convention.
duke@0 2589 // Region 6-7 is determined per call site.
duke@0 2590 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 2591 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 2592 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 2593 // incoming area, as the Java calling convention is completely under
duke@0 2594 // the control of the AD file. Doubles can be sorted and packed to
duke@0 2595 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 2596 // varargs C calling conventions.
duke@0 2597 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 2598 // even aligned with pad0 as needed.
duke@0 2599 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 2600 // region 6-11 is even aligned; it may be padded out more so that
duke@0 2601 // the region from SP to FP meets the minimum stack alignment.
duke@0 2602 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
duke@0 2603 // alignment. Region 11, pad1, may be dynamically extended so that
duke@0 2604 // SP meets the minimum alignment.
duke@0 2605
duke@0 2606 frame
duke@0 2607 %{
duke@0 2608 // What direction does stack grow in (assumed to be same for C & Java)
duke@0 2609 stack_direction(TOWARDS_LOW);
duke@0 2610
duke@0 2611 // These three registers define part of the calling convention
duke@0 2612 // between compiled code and the interpreter.
duke@0 2613 inline_cache_reg(RAX); // Inline Cache Register
duke@0 2614 interpreter_method_oop_reg(RBX); // Method Oop Register when
duke@0 2615 // calling interpreter
duke@0 2616
duke@0 2617 // Optional: name the operand used by cisc-spilling to access
duke@0 2618 // [stack_pointer + offset]
duke@0 2619 cisc_spilling_operand_name(indOffset32);
duke@0 2620
duke@0 2621 // Number of stack slots consumed by locking an object
duke@0 2622 sync_stack_slots(2);
duke@0 2623
duke@0 2624 // Compiled code's Frame Pointer
duke@0 2625 frame_pointer(RSP);
duke@0 2626
duke@0 2627 // Interpreter stores its frame pointer in a register which is
duke@0 2628 // stored to the stack by I2CAdaptors.
duke@0 2629 // I2CAdaptors convert from interpreted java to compiled java.
duke@0 2630 interpreter_frame_pointer(RBP);
duke@0 2631
duke@0 2632 // Stack alignment requirement
duke@0 2633 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
duke@0 2634
duke@0 2635 // Number of stack slots between incoming argument block and the start of
duke@0 2636 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 2637 // EPILOG must remove this many slots. amd64 needs two slots for
duke@0 2638 // return address.
duke@0 2639 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
duke@0 2640
duke@0 2641 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 2642 // for calls to C. Supports the var-args backing area for register parms.
duke@0 2643 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
duke@0 2644
duke@0 2645 // The after-PROLOG location of the return address. Location of
duke@0 2646 // return address specifies a type (REG or STACK) and a number
duke@0 2647 // representing the register number (i.e. - use a register name) or
duke@0 2648 // stack slot.
duke@0 2649 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
duke@0 2650 // Otherwise, it is above the locks and verification slot and alignment word
duke@0 2651 return_addr(STACK - 2 +
kvn@3142 2652 round_to((Compile::current()->in_preserve_stack_slots() +
kvn@3142 2653 Compile::current()->fixed_slots()),
kvn@3142 2654 stack_alignment_in_slots()));
duke@0 2655
duke@0 2656 // Body of function which returns an integer array locating
duke@0 2657 // arguments either in registers or in stack slots. Passed an array
duke@0 2658 // of ideal registers called "sig" and a "length" count. Stack-slot
duke@0 2659 // offsets are based on outgoing arguments, i.e. a CALLER setting up
duke@0 2660 // arguments for a CALLEE. Incoming stack arguments are
duke@0 2661 // automatically biased by the preserve_stack_slots field above.
duke@0 2662
duke@0 2663 calling_convention
duke@0 2664 %{
duke@0 2665 // No difference between ingoing/outgoing just pass false
duke@0 2666 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
duke@0 2667 %}
duke@0 2668
duke@0 2669 c_calling_convention
duke@0 2670 %{
duke@0 2671 // This is obviously always outgoing
goetz@5970 2672 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
duke@0 2673 %}
duke@0 2674
duke@0 2675 // Location of compiled Java return values. Same as C for now.
duke@0 2676 return_value
duke@0 2677 %{
duke@0 2678 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
duke@0 2679 "only return normal values");
duke@0 2680
duke@0 2681 static const int lo[Op_RegL + 1] = {
duke@0 2682 0,
duke@0 2683 0,
coleenp@113 2684 RAX_num, // Op_RegN
duke@0 2685 RAX_num, // Op_RegI
duke@0 2686 RAX_num, // Op_RegP
duke@0 2687 XMM0_num, // Op_RegF
duke@0 2688 XMM0_num, // Op_RegD
duke@0 2689 RAX_num // Op_RegL
duke@0 2690 };
duke@0 2691 static const int hi[Op_RegL + 1] = {
duke@0 2692 0,
duke@0 2693 0,
coleenp@113 2694 OptoReg::Bad, // Op_RegN
duke@0 2695 OptoReg::Bad, // Op_RegI
duke@0 2696 RAX_H_num, // Op_RegP
duke@0 2697 OptoReg::Bad, // Op_RegF
kvn@3447 2698 XMM0b_num, // Op_RegD
duke@0 2699 RAX_H_num // Op_RegL
duke@0 2700 };
kvn@3447 2701 // Excluded flags and vector registers.
kvn@3447 2702 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
duke@0 2703 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
duke@0 2704 %}
duke@0 2705 %}
duke@0 2706
duke@0 2707 //----------ATTRIBUTES---------------------------------------------------------
duke@0 2708 //----------Operand Attributes-------------------------------------------------
duke@0 2709 op_attrib op_cost(0); // Required cost attribute
duke@0 2710
duke@0 2711 //----------Instruction Attributes---------------------------------------------
duke@0 2712 ins_attrib ins_cost(100); // Required cost attribute
duke@0 2713 ins_attrib ins_size(8); // Required size attribute (in bits)
duke@0 2714 ins_attrib ins_short_branch(0); // Required flag: is this instruction
duke@0 2715 // a non-matching short branch variant
duke@0 2716 // of some long branch?
duke@0 2717 ins_attrib ins_alignment(1); // Required alignment attribute (must
duke@0 2718 // be a power of 2) specifies the
duke@0 2719 // alignment that some part of the
duke@0 2720 // instruction (not necessarily the
duke@0 2721 // start) requires. If > 1, a
duke@0 2722 // compute_padding() function must be
duke@0 2723 // provided for the instruction
duke@0 2724
duke@0 2725 //----------OPERANDS-----------------------------------------------------------
duke@0 2726 // Operand definitions must precede instruction definitions for correct parsing
duke@0 2727 // in the ADLC because operands constitute user defined types which are used in
duke@0 2728 // instruction definitions.
duke@0 2729
duke@0 2730 //----------Simple Operands----------------------------------------------------
duke@0 2731 // Immediate Operands
duke@0 2732 // Integer Immediate
duke@0 2733 operand immI()
duke@0 2734 %{
duke@0 2735 match(ConI);
duke@0 2736
duke@0 2737 op_cost(10);
duke@0 2738 format %{ %}
duke@0 2739 interface(CONST_INTER);
duke@0 2740 %}
duke@0 2741
duke@0 2742 // Constant for test vs zero
duke@0 2743 operand immI0()
duke@0 2744 %{
duke@0 2745 predicate(n->get_int() == 0);
duke@0 2746 match(ConI);
duke@0 2747
duke@0 2748 op_cost(0);
duke@0 2749 format %{ %}
duke@0 2750 interface(CONST_INTER);
duke@0 2751 %}
duke@0 2752
duke@0 2753 // Constant for increment
duke@0 2754 operand immI1()
duke@0 2755 %{
duke@0 2756 predicate(n->get_int() == 1);
duke@0 2757 match(ConI);
duke@0 2758
duke@0 2759 op_cost(0);
duke@0 2760 format %{ %}
duke@0 2761 interface(CONST_INTER);
duke@0 2762 %}
duke@0 2763
duke@0 2764 // Constant for decrement
duke@0 2765 operand immI_M1()
duke@0 2766 %{
duke@0 2767 predicate(n->get_int() == -1);
duke@0 2768 match(ConI);
duke@0 2769
duke@0 2770 op_cost(0);
duke@0 2771 format %{ %}
duke@0 2772 interface(CONST_INTER);
duke@0 2773 %}
duke@0 2774
duke@0 2775 // Valid scale values for addressing modes
duke@0 2776 operand immI2()
duke@0 2777 %{
duke@0 2778 predicate(0 <= n->get_int() && (n->get_int() <= 3));
duke@0 2779 match(ConI);
duke@0 2780
duke@0 2781 format %{ %}
duke@0 2782 interface(CONST_INTER);
duke@0 2783 %}
duke@0 2784
duke@0 2785 operand immI8()
duke@0 2786 %{
duke@0 2787 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
duke@0 2788 match(ConI);
duke@0 2789
duke@0 2790 op_cost(5);
duke@0 2791 format %{ %}
duke@0 2792 interface(CONST_INTER);
duke@0 2793 %}
duke@0 2794
duke@0 2795 operand immI16()
duke@0 2796 %{
duke@0 2797 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
duke@0 2798 match(ConI);
duke@0 2799
duke@0 2800 op_cost(10);
duke@0 2801 format %{ %}
duke@0 2802 interface(CONST_INTER);
duke@0 2803 %}
duke@0 2804
iveresov@5824 2805 // Int Immediate non-negative
iveresov@5824 2806 operand immU31()
iveresov@5824 2807 %{
iveresov@5824 2808 predicate(n->get_int() >= 0);
iveresov@5824 2809 match(ConI);
iveresov@5824 2810
iveresov@5824 2811 op_cost(0);
iveresov@5824 2812 format %{ %}
iveresov@5824 2813 interface(CONST_INTER);
iveresov@5824 2814 %}
iveresov@5824 2815
duke@0 2816 // Constant for long shifts
duke@0 2817 operand immI_32()
duke@0 2818 %{
duke@0 2819 predicate( n->get_int() == 32 );
duke@0 2820 match(ConI);
duke@0 2821
duke@0 2822 op_cost(0);
duke@0 2823 format %{ %}
duke@0 2824 interface(CONST_INTER);
duke@0 2825 %}
duke@0 2826
duke@0 2827 // Constant for long shifts
duke@0 2828 operand immI_64()
duke@0 2829 %{
duke@0 2830 predicate( n->get_int() == 64 );
duke@0 2831 match(ConI);
duke@0 2832
duke@0 2833 op_cost(0);
duke@0 2834 format %{ %}
duke@0 2835 interface(CONST_INTER);
duke@0 2836 %}
duke@0 2837
duke@0 2838 // Pointer Immediate
duke@0 2839 operand immP()
duke@0 2840 %{
duke@0 2841 match(ConP);
duke@0 2842
duke@0 2843 op_cost(10);
duke@0 2844 format %{ %}
duke@0 2845 interface(CONST_INTER);
duke@0 2846 %}
duke@0 2847
duke@0 2848 // NULL Pointer Immediate
duke@0 2849 operand immP0()
duke@0 2850 %{
duke@0 2851 predicate(n->get_ptr() == 0);
duke@0 2852 match(ConP);
duke@0 2853
duke@0 2854 op_cost(5);
duke@0 2855 format %{ %}
duke@0 2856 interface(CONST_INTER);
duke@0 2857 %}
duke@0 2858
coleenp@113 2859 // Pointer Immediate
coleenp@113 2860 operand immN() %{
coleenp@113 2861 match(ConN);
coleenp@113 2862
coleenp@113 2863 op_cost(10);
coleenp@113 2864 format %{ %}
coleenp@113 2865 interface(CONST_INTER);
coleenp@113 2866 %}
coleenp@113 2867
roland@3724 2868 operand immNKlass() %{
roland@3724 2869 match(ConNKlass);
roland@3724 2870
roland@3724 2871 op_cost(10);
roland@3724 2872 format %{ %}
roland@3724 2873 interface(CONST_INTER);
roland@3724 2874 %}
roland@3724 2875
coleenp@113 2876 // NULL Pointer Immediate
coleenp@113 2877 operand immN0() %{
coleenp@113 2878 predicate(n->get_narrowcon() == 0);
coleenp@113 2879 match(ConN);
coleenp@113 2880
coleenp@113 2881 op_cost(5);
coleenp@113 2882 format %{ %}
coleenp@113 2883 interface(CONST_INTER);
coleenp@113 2884 %}
coleenp@113 2885
duke@0 2886 operand immP31()
duke@0 2887 %{
coleenp@3602 2888 predicate(n->as_Type()->type()->reloc() == relocInfo::none
duke@0 2889 && (n->get_ptr() >> 31) == 0);
duke@0 2890 match(ConP);
duke@0 2891
duke@0 2892 op_cost(5);
duke@0 2893 format %{ %}
duke@0 2894 interface(CONST_INTER);
duke@0 2895 %}
duke@0 2896
coleenp@113 2897
duke@0 2898 // Long Immediate
duke@0 2899 operand immL()
duke@0 2900 %{
duke@0 2901 match(ConL);
duke@0 2902
duke@0 2903 op_cost(20);
duke@0 2904 format %{ %}
duke@0 2905 interface(CONST_INTER);
duke@0 2906 %}
duke@0 2907
duke@0 2908 // Long Immediate 8-bit
duke@0 2909 operand immL8()
duke@0 2910 %{
duke@0 2911 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
duke@0 2912 match(ConL);
duke@0 2913
duke@0 2914 op_cost(5);
duke@0 2915 format %{ %}
duke@0 2916 interface(CONST_INTER);
duke@0 2917 %}
duke@0 2918
duke@0 2919 // Long Immediate 32-bit unsigned
duke@0 2920 operand immUL32()
duke@0 2921 %{
duke@0 2922 predicate(n->get_long() == (unsigned int) (n->get_long()));
duke@0 2923 match(ConL);
duke@0 2924
duke@0 2925 op_cost(10);
duke@0 2926 format %{ %}
duke@0 2927 interface(CONST_INTER);
duke@0 2928 %}
duke@0 2929
duke@0 2930 // Long Immediate 32-bit signed
duke@0 2931 operand immL32()
duke@0 2932 %{
duke@0 2933 predicate(n->get_long() == (int) (n->get_long()));
duke@0 2934 match(ConL);
duke@0 2935
duke@0 2936 op_cost(15);
duke@0 2937 format %{ %}
duke@0 2938 interface(CONST_INTER);
duke@0 2939 %}
duke@0 2940
duke@0 2941 // Long Immediate zero
duke@0 2942 operand immL0()
duke@0 2943 %{
duke@0 2944 predicate(n->get_long() == 0L);
duke@0 2945 match(ConL);
duke@0 2946
duke@0 2947 op_cost(10);
duke@0 2948 format %{ %}
duke@0 2949 interface(CONST_INTER);
duke@0 2950 %}
duke@0 2951
duke@0 2952 // Constant for increment
duke@0 2953 operand immL1()
duke@0 2954 %{
duke@0 2955 predicate(n->get_long() == 1);
duke@0 2956 match(ConL);
duke@0 2957
duke@0 2958 format %{ %}
duke@0 2959 interface(CONST_INTER);
duke@0 2960 %}
duke@0 2961
duke@0 2962 // Constant for decrement
duke@0 2963 operand immL_M1()
duke@0 2964 %{
duke@0 2965 predicate(n->get_long() == -1);
duke@0 2966 match(ConL);
duke@0 2967
duke@0 2968 format %{ %}
duke@0 2969 interface(CONST_INTER);
duke@0 2970 %}
duke@0 2971
duke@0 2972 // Long Immediate: the value 10
duke@0 2973 operand immL10()
duke@0 2974 %{
duke@0 2975 predicate(n->get_long() == 10);
duke@0 2976 match(ConL);
duke@0 2977
duke@0 2978 format %{ %}
duke@0 2979 interface(CONST_INTER);
duke@0 2980 %}
duke@0 2981
duke@0 2982 // Long immediate from 0 to 127.
duke@0 2983 // Used for a shorter form of long mul by 10.
duke@0 2984 operand immL_127()
duke@0 2985 %{
duke@0 2986 predicate(0 <= n->get_long() && n->get_long() < 0x80);
duke@0 2987 match(ConL);
duke@0 2988
duke@0 2989 op_cost(10);
duke@0 2990 format %{ %}
duke@0 2991 interface(CONST_INTER);
duke@0 2992 %}
duke@0 2993
duke@0 2994 // Long Immediate: low 32-bit mask
duke@0 2995 operand immL_32bits()
duke@0 2996 %{
duke@0 2997 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 2998 match(ConL);
duke@0 2999 op_cost(20);
duke@0 3000
duke@0 3001 format %{ %}
duke@0 3002 interface(CONST_INTER);
duke@0 3003 %}
duke@0 3004
duke@0 3005 // Float Immediate zero
duke@0 3006 operand immF0()
duke@0 3007 %{
duke@0 3008 predicate(jint_cast(n->getf()) == 0);
duke@0 3009 match(ConF);
duke@0 3010
duke@0 3011 op_cost(5);
duke@0 3012 format %{ %}
duke@0 3013 interface(CONST_INTER);
duke@0 3014 %}
duke@0 3015
duke@0 3016 // Float Immediate
duke@0 3017 operand immF()
duke@0 3018 %{
duke@0 3019 match(ConF);
duke@0 3020
duke@0 3021 op_cost(15);
duke@0 3022 format %{ %}
duke@0 3023 interface(CONST_INTER);
duke@0 3024 %}
duke@0 3025
duke@0 3026 // Double Immediate zero
duke@0 3027 operand immD0()
duke@0 3028 %{
duke@0 3029 predicate(jlong_cast(n->getd()) == 0);
duke@0 3030 match(ConD);
duke@0 3031
duke@0 3032 op_cost(5);
duke@0 3033 format %{ %}
duke@0 3034 interface(CONST_INTER);
duke@0 3035 %}
duke@0 3036
duke@0 3037 // Double Immediate
duke@0 3038 operand immD()
duke@0 3039 %{
duke@0 3040 match(ConD);
duke@0 3041
duke@0 3042 op_cost(15);
duke@0 3043 format %{ %}
duke@0 3044 interface(CONST_INTER);
duke@0 3045 %}
duke@0 3046
duke@0 3047 // Immediates for special shifts (sign extend)
duke@0 3048
duke@0 3049 // Constants for increment
duke@0 3050 operand immI_16()
duke@0 3051 %{
duke@0 3052 predicate(n->get_int() == 16);
duke@0 3053 match(ConI);
duke@0 3054
duke@0 3055 format %{ %}
duke@0 3056 interface(CONST_INTER);
duke@0 3057 %}
duke@0 3058
duke@0 3059 operand immI_24()
duke@0 3060 %{
duke@0 3061 predicate(n->get_int() == 24);
duke@0 3062 match(ConI);
duke@0 3063
duke@0 3064 format %{ %}
duke@0 3065 interface(CONST_INTER);
duke@0 3066 %}
duke@0 3067
duke@0 3068 // Constant for byte-wide masking
duke@0 3069 operand immI_255()
duke@0 3070 %{
duke@0 3071 predicate(n->get_int() == 255);
duke@0 3072 match(ConI);
duke@0 3073
duke@0 3074 format %{ %}
duke@0 3075 interface(CONST_INTER);
duke@0 3076 %}
duke@0 3077
duke@0 3078 // Constant for short-wide masking
duke@0 3079 operand immI_65535()
duke@0 3080 %{
duke@0 3081 predicate(n->get_int() == 65535);
duke@0 3082 match(ConI);
duke@0 3083
duke@0 3084 format %{ %}
duke@0 3085 interface(CONST_INTER);
duke@0 3086 %}
duke@0 3087
duke@0 3088 // Constant for byte-wide masking
duke@0 3089 operand immL_255()
duke@0 3090 %{
duke@0 3091 predicate(n->get_long() == 255);
duke@0 3092 match(ConL);
duke@0 3093
duke@0 3094 format %{ %}
duke@0 3095 interface(CONST_INTER);
duke@0 3096 %}
duke@0 3097
duke@0 3098 // Constant for short-wide masking
duke@0 3099 operand immL_65535()
duke@0 3100 %{
duke@0 3101 predicate(n->get_long() == 65535);
duke@0 3102 match(ConL);
duke@0 3103
duke@0 3104 format %{ %}
duke@0 3105 interface(CONST_INTER);
duke@0 3106 %}
duke@0 3107
duke@0 3108 // Register Operands
duke@0 3109 // Integer Register
duke@0 3110 operand rRegI()
duke@0 3111 %{
duke@0 3112 constraint(ALLOC_IN_RC(int_reg));
duke@0 3113 match(RegI);
duke@0 3114
duke@0 3115 match(rax_RegI);
duke@0 3116 match(rbx_RegI);
duke@0 3117 match(rcx_RegI);
duke@0 3118 match(rdx_RegI);
duke@0 3119 match(rdi_RegI);
duke@0 3120
duke@0 3121 format %{ %}
duke@0 3122 interface(REG_INTER);
duke@0 3123 %}
duke@0 3124
duke@0 3125 // Special Registers
duke@0 3126 operand rax_RegI()
duke@0 3127 %{
duke@0 3128 constraint(ALLOC_IN_RC(int_rax_reg));
duke@0 3129 match(RegI);
duke@0 3130 match(rRegI);
duke@0 3131
duke@0 3132 format %{ "RAX" %}
duke@0 3133 interface(REG_INTER);
duke@0 3134 %}
duke@0 3135
duke@0 3136 // Special Registers
duke@0 3137 operand rbx_RegI()
duke@0 3138 %{
duke@0 3139 constraint(ALLOC_IN_RC(int_rbx_reg));
duke@0 3140 match(RegI);
duke@0 3141 match(rRegI);
duke@0 3142
duke@0 3143 format %{ "RBX" %}
duke@0 3144 interface(REG_INTER);
duke@0 3145 %}
duke@0 3146
duke@0 3147 operand rcx_RegI()
duke@0 3148 %{
duke@0 3149 constraint(ALLOC_IN_RC(int_rcx_reg));
duke@0 3150 match(RegI);
duke@0 3151 match(rRegI);
duke@0 3152
duke@0 3153 format %{ "RCX" %}
duke@0 3154 interface(REG_INTER);
duke@0 3155 %}
duke@0 3156
duke@0 3157 operand rdx_RegI()
duke@0 3158 %{
duke@0 3159 constraint(ALLOC_IN_RC(int_rdx_reg));
duke@0 3160 match(RegI);
duke@0 3161 match(rRegI);
duke@0 3162
duke@0 3163 format %{ "RDX" %}
duke@0 3164 interface(REG_INTER);
duke@0 3165 %}
duke@0 3166
duke@0 3167 operand rdi_RegI()
duke@0 3168 %{
duke@0 3169 constraint(ALLOC_IN_RC(int_rdi_reg));
duke@0 3170 match(RegI);
duke@0 3171 match(rRegI);
duke@0 3172
duke@0 3173 format %{ "RDI" %}
duke@0 3174 interface(REG_INTER);
duke@0 3175 %}
duke@0 3176
duke@0 3177 operand no_rcx_RegI()
duke@0 3178 %{
duke@0 3179 constraint(ALLOC_IN_RC(int_no_rcx_reg));
duke@0 3180 match(RegI);
duke@0 3181 match(rax_RegI);
duke@0 3182 match(rbx_RegI);
duke@0 3183 match(rdx_RegI);
duke@0 3184 match(rdi_RegI);
duke@0 3185
duke@0 3186 format %{ %}
duke@0 3187 interface(REG_INTER);
duke@0 3188 %}
duke@0 3189
duke@0 3190 operand no_rax_rdx_RegI()
duke@0 3191 %{
duke@0 3192 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
duke@0 3193 match(RegI);
duke@0 3194 match(rbx_RegI);
duke@0 3195 match(rcx_RegI);
duke@0 3196 match(rdi_RegI);
duke@0 3197
duke@0 3198 format %{ %}
duke@0 3199 interface(REG_INTER);
duke@0 3200 %}
duke@0 3201
duke@0 3202 // Pointer Register
duke@0 3203 operand any_RegP()
duke@0 3204 %{
duke@0 3205 constraint(ALLOC_IN_RC(any_reg));
duke@0 3206 match(RegP);
duke@0 3207 match(rax_RegP);
duke@0 3208 match(rbx_RegP);
duke@0 3209 match(rdi_RegP);
duke@0 3210 match(rsi_RegP);
duke@0 3211 match(rbp_RegP);
duke@0 3212 match(r15_RegP);
duke@0 3213 match(rRegP);
duke@0 3214
duke@0 3215 format %{ %}
duke@0 3216 interface(REG_INTER);
duke@0 3217 %}
duke@0 3218
duke@0 3219 operand rRegP()
duke@0 3220 %{
duke@0 3221 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3222 match(RegP);
duke@0 3223 match(rax_RegP);
duke@0 3224 match(rbx_RegP);
duke@0 3225 match(rdi_RegP);
duke@0 3226 match(rsi_RegP);
duke@0 3227 match(rbp_RegP);
duke@0 3228 match(r15_RegP); // See Q&A below about r15_RegP.
duke@0 3229
duke@0 3230 format %{ %}
duke@0 3231 interface(REG_INTER);
duke@0 3232 %}
duke@0 3233
coleenp@113 3234 operand rRegN() %{
coleenp@113 3235 constraint(ALLOC_IN_RC(int_reg));
coleenp@113 3236 match(RegN);
coleenp@113 3237
coleenp@113 3238 format %{ %}
coleenp@113 3239 interface(REG_INTER);
coleenp@113 3240 %}
coleenp@113 3241
duke@0 3242 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
duke@0 3243 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
duke@0 3244 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
duke@0 3245 // The output of an instruction is controlled by the allocator, which respects
duke@0 3246 // register class masks, not match rules. Unless an instruction mentions
duke@0 3247 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
duke@0 3248 // by the allocator as an input.
duke@0 3249
duke@0 3250 operand no_rax_RegP()
duke@0 3251 %{
duke@0 3252 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
duke@0 3253 match(RegP);
duke@0 3254 match(rbx_RegP);
duke@0 3255 match(rsi_RegP);
duke@0 3256 match(rdi_RegP);
duke@0 3257
duke@0 3258 format %{ %}
duke@0 3259 interface(REG_INTER);
duke@0 3260 %}
duke@0 3261
duke@0 3262 operand no_rbp_RegP()
duke@0 3263 %{
duke@0 3264 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
duke@0 3265 match(RegP);
duke@0 3266 match(rbx_RegP);
duke@0 3267 match(rsi_RegP);
duke@0 3268 match(rdi_RegP);
duke@0 3269
duke@0 3270 format %{ %}
duke@0 3271 interface(REG_INTER);
duke@0 3272 %}
duke@0 3273
duke@0 3274 operand no_rax_rbx_RegP()
duke@0 3275 %{
duke@0 3276 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
duke@0 3277 match(RegP);
duke@0 3278 match(rsi_RegP);
duke@0 3279 match(rdi_RegP);
duke@0 3280
duke@0 3281 format %{ %}
duke@0 3282 interface(REG_INTER);
duke@0 3283 %}
duke@0 3284
duke@0 3285 // Special Registers
duke@0 3286 // Return a pointer value
duke@0 3287 operand rax_RegP()
duke@0 3288 %{
duke@0 3289 constraint(ALLOC_IN_RC(ptr_rax_reg));
duke@0 3290 match(RegP);
duke@0 3291 match(rRegP);
duke@0 3292
duke@0 3293 format %{ %}
duke@0 3294 interface(REG_INTER);
duke@0 3295 %}
duke@0 3296
coleenp@113 3297 // Special Registers
coleenp@113 3298 // Return a compressed pointer value
coleenp@113 3299 operand rax_RegN()
coleenp@113 3300 %{
coleenp@113 3301 constraint(ALLOC_IN_RC(int_rax_reg));
coleenp@113 3302 match(RegN);
coleenp@113 3303 match(rRegN);
coleenp@113 3304
coleenp@113 3305 format %{ %}
coleenp@113 3306 interface(REG_INTER);
coleenp@113 3307 %}
coleenp@113 3308
duke@0 3309 // Used in AtomicAdd
duke@0 3310 operand rbx_RegP()
duke@0 3311 %{
duke@0 3312 constraint(ALLOC_IN_RC(ptr_rbx_reg));
duke@0 3313 match(RegP);
duke@0 3314 match(rRegP);
duke@0 3315
duke@0 3316 format %{ %}
duke@0 3317 interface(REG_INTER);
duke@0 3318 %}
duke@0 3319
duke@0 3320 operand rsi_RegP()
duke@0 3321 %{
duke@0 3322 constraint(ALLOC_IN_RC(ptr_rsi_reg));
duke@0 3323 match(RegP);
duke@0 3324 match(rRegP);
duke@0 3325
duke@0 3326 format %{ %}
duke@0 3327 interface(REG_INTER);
duke@0 3328 %}
duke@0 3329
duke@0 3330 // Used in rep stosq
duke@0 3331 operand rdi_RegP()
duke@0 3332 %{
duke@0 3333 constraint(ALLOC_IN_RC(ptr_rdi_reg));
duke@0 3334 match(RegP);
duke@0 3335 match(rRegP);
duke@0 3336
duke@0 3337 format %{ %}
duke@0 3338 interface(REG_INTER);
duke@0 3339 %}
duke@0 3340
duke@0 3341 operand rbp_RegP()
duke@0 3342 %{
duke@0 3343 constraint(ALLOC_IN_RC(ptr_rbp_reg));
duke@0 3344 match(RegP);
duke@0 3345 match(rRegP);
duke@0 3346
duke@0 3347 format %{ %}
duke@0 3348 interface(REG_INTER);
duke@0 3349 %}
duke@0 3350
duke@0 3351 operand r15_RegP()
duke@0 3352 %{
duke@0 3353 constraint(ALLOC_IN_RC(ptr_r15_reg));
duke@0 3354 match(RegP);
duke@0 3355 match(rRegP);
duke@0 3356
duke@0 3357 format %{ %}
duke@0 3358 interface(REG_INTER);
duke@0 3359 %}
duke@0 3360
duke@0 3361 operand rRegL()
duke@0 3362 %{
duke@0 3363 constraint(ALLOC_IN_RC(long_reg));
duke@0 3364 match(RegL);
duke@0 3365 match(rax_RegL);
duke@0 3366 match(rdx_RegL);
duke@0 3367
duke@0 3368 format %{ %}
duke@0 3369 interface(REG_INTER);
duke@0 3370 %}
duke@0 3371
duke@0 3372 // Special Registers
duke@0 3373 operand no_rax_rdx_RegL()
duke@0 3374 %{
duke@0 3375 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3376 match(RegL);
duke@0 3377 match(rRegL);
duke@0 3378
duke@0 3379 format %{ %}
duke@0 3380 interface(REG_INTER);
duke@0 3381 %}
duke@0 3382
duke@0 3383 operand no_rax_RegL()
duke@0 3384 %{
duke@0 3385 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3386 match(RegL);
duke@0 3387 match(rRegL);
duke@0 3388 match(rdx_RegL);
duke@0 3389
duke@0 3390 format %{ %}
duke@0 3391 interface(REG_INTER);
duke@0 3392 %}
duke@0 3393
duke@0 3394 operand no_rcx_RegL()
duke@0 3395 %{
duke@0 3396 constraint(ALLOC_IN_RC(long_no_rcx_reg));
duke@0 3397 match(RegL);
duke@0 3398 match(rRegL);
duke@0 3399
duke@0 3400 format %{ %}
duke@0 3401 interface(REG_INTER);
duke@0 3402 %}
duke@0 3403
duke@0 3404 operand rax_RegL()
duke@0 3405 %{
duke@0 3406 constraint(ALLOC_IN_RC(long_rax_reg));
duke@0 3407 match(RegL);
duke@0 3408 match(rRegL);
duke@0 3409
duke@0 3410 format %{ "RAX" %}
duke@0 3411 interface(REG_INTER);
duke@0 3412 %}
duke@0 3413
duke@0 3414 operand rcx_RegL()
duke@0 3415 %{
duke@0 3416 constraint(ALLOC_IN_RC(long_rcx_reg));
duke@0 3417 match(RegL);
duke@0 3418 match(rRegL);
duke@0 3419
duke@0 3420 format %{ %}
duke@0 3421 interface(REG_INTER);
duke@0 3422 %}
duke@0 3423
duke@0 3424 operand rdx_RegL()
duke@0 3425 %{
duke@0 3426 constraint(ALLOC_IN_RC(long_rdx_reg));
duke@0 3427 match(RegL);
duke@0 3428 match(rRegL);
duke@0 3429
duke@0 3430 format %{ %}
duke@0 3431 interface(REG_INTER);
duke@0 3432 %}
duke@0 3433
duke@0 3434 // Flags register, used as output of compare instructions
duke@0 3435 operand rFlagsReg()
duke@0 3436 %{
duke@0 3437 constraint(ALLOC_IN_RC(int_flags));
duke@0 3438 match(RegFlags);
duke@0 3439
duke@0 3440 format %{ "RFLAGS" %}
duke@0 3441 interface(REG_INTER);
duke@0 3442 %}
duke@0 3443
duke@0 3444 // Flags register, used as output of FLOATING POINT compare instructions
duke@0 3445 operand rFlagsRegU()
duke@0 3446 %{
duke@0 3447 constraint(ALLOC_IN_RC(int_flags));
duke@0 3448 match(RegFlags);
duke@0 3449
duke@0 3450 format %{ "RFLAGS_U" %}
duke@0 3451 interface(REG_INTER);
duke@0 3452 %}
duke@0 3453
never@415 3454 operand rFlagsRegUCF() %{
never@415 3455 constraint(ALLOC_IN_RC(int_flags));
never@415 3456 match(RegFlags);
never@415 3457 predicate(false);
never@415 3458
never@415 3459 format %{ "RFLAGS_U_CF" %}
never@415 3460 interface(REG_INTER);
never@415 3461 %}
never@415 3462
duke@0 3463 // Float register operands
duke@0 3464 operand regF()
duke@0 3465 %{
duke@0 3466 constraint(ALLOC_IN_RC(float_reg));
duke@0 3467 match(RegF);
duke@0 3468
duke@0 3469 format %{ %}
duke@0 3470 interface(REG_INTER);
duke@0 3471 %}
duke@0 3472
duke@0 3473 // Double register operands
iveresov@2251 3474 operand regD()
duke@0 3475 %{
duke@0 3476 constraint(ALLOC_IN_RC(double_reg));
duke@0 3477 match(RegD);
duke@0 3478
duke@0 3479 format %{ %}
duke@0 3480 interface(REG_INTER);
duke@0 3481 %}
duke@0 3482
duke@0 3483 //----------Memory Operands----------------------------------------------------
duke@0 3484 // Direct Memory Operand
duke@0 3485 // operand direct(immP addr)
duke@0 3486 // %{
duke@0 3487 // match(addr);
duke@0 3488
duke@0 3489 // format %{ "[$addr]" %}
duke@0 3490 // interface(MEMORY_INTER) %{
duke@0 3491 // base(0xFFFFFFFF);
duke@0 3492 // index(0x4);
duke@0 3493 // scale(0x0);
duke@0 3494 // disp($addr);
duke@0 3495 // %}
duke@0 3496 // %}
duke@0 3497
duke@0 3498 // Indirect Memory Operand
duke@0 3499 operand indirect(any_RegP reg)
duke@0 3500 %{
duke@0 3501 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3502 match(reg);
duke@0 3503
duke@0 3504 format %{ "[$reg]" %}
duke@0 3505 interface(MEMORY_INTER) %{
duke@0 3506 base($reg);
duke@0 3507 index(0x4);
duke@0 3508 scale(0x0);
duke@0 3509 disp(0x0);
duke@0 3510 %}
duke@0 3511 %}
duke@0 3512
duke@0 3513 // Indirect Memory Plus Short Offset Operand
duke@0 3514 operand indOffset8(any_RegP reg, immL8 off)
duke@0 3515 %{
duke@0 3516 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3517 match(AddP reg off);
duke@0 3518
duke@0 3519 format %{ "[$reg + $off (8-bit)]" %}
duke@0 3520 interface(MEMORY_INTER) %{
duke@0 3521 base($reg);
duke@0 3522 index(0x4);
duke@0 3523 scale(0x0);
duke@0 3524 disp($off);
duke@0 3525 %}
duke@0 3526 %}
duke@0 3527
duke@0 3528 // Indirect Memory Plus Long Offset Operand
duke@0 3529 operand indOffset32(any_RegP reg, immL32 off)
duke@0 3530 %{
duke@0 3531 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3532 match(AddP reg off);
duke@0 3533
duke@0 3534 format %{ "[$reg + $off (32-bit)]" %}
duke@0 3535 interface(MEMORY_INTER) %{
duke@0 3536 base($reg);
duke@0 3537 index(0x4);
duke@0 3538 scale(0x0);
duke@0 3539 disp($off);
duke@0 3540 %}
duke@0 3541 %}
duke@0 3542
duke@0 3543 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3544 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
duke@0 3545 %{
duke@0 3546 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3547 match(AddP (AddP reg lreg) off);
duke@0 3548
duke@0 3549 op_cost(10);
duke@0 3550 format %{"[$reg + $off + $lreg]" %}
duke@0 3551 interface(MEMORY_INTER) %{
duke@0 3552 base($reg);
duke@0 3553 index($lreg);
duke@0 3554 scale(0x0);
duke@0 3555 disp($off);
duke@0 3556 %}
duke@0 3557 %}
duke@0 3558
duke@0 3559 // Indirect Memory Plus Index Register Plus Offset Operand
duke@0 3560 operand indIndex(any_RegP reg, rRegL lreg)
duke@0 3561 %{
duke@0 3562 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3563 match(AddP reg lreg);
duke@0 3564
duke@0 3565 op_cost(10);
duke@0 3566 format %{"[$reg + $lreg]" %}
duke@0 3567 interface(MEMORY_INTER) %{
duke@0 3568 base($reg);
duke@0 3569 index($lreg);
duke@0 3570 scale(0x0);
duke@0 3571 disp(0x0);
duke@0 3572 %}
duke@0 3573 %}
duke@0 3574
duke@0 3575 // Indirect Memory Times Scale Plus Index Register
duke@0 3576 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
duke@0 3577 %{
duke@0 3578 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3579 match(AddP reg (LShiftL lreg scale));
duke@0 3580
duke@0 3581 op_cost(10);
duke@0 3582 format %{"[$reg + $lreg << $scale]" %}
duke@0 3583 interface(MEMORY_INTER) %{
duke@0 3584 base($reg);
duke@0 3585 index($lreg);
duke@0 3586 scale($scale);
duke@0 3587 disp(0x0);
duke@0 3588 %}
duke@0 3589 %}
duke@0 3590
duke@0 3591 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
duke@0 3592 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
duke@0 3593 %{
duke@0 3594 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3595 match(AddP (AddP reg (LShiftL lreg scale)) off);
duke@0 3596
duke@0 3597 op_cost(10);
duke@0 3598 format %{"[$reg + $off + $lreg << $scale]" %}
duke@0 3599 interface(MEMORY_INTER) %{
duke@0 3600 base($reg);
duke@0 3601 index($lreg);
duke@0 3602 scale($scale);
duke@0 3603 disp($off);
duke@0 3604 %}
duke@0 3605 %}
duke@0 3606
duke@0 3607 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
duke@0 3608 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
duke@0 3609 %{
duke@0 3610 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3611 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
duke@0 3612 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
duke@0 3613
duke@0 3614 op_cost(10);
duke@0 3615 format %{"[$reg + $off + $idx << $scale]" %}
duke@0 3616 interface(MEMORY_INTER) %{
duke@0 3617 base($reg);
duke@0 3618 index($idx);
duke@0 3619 scale($scale);
duke@0 3620 disp($off);
duke@0 3621 %}
duke@0 3622 %}
duke@0 3623
kvn@642 3624 // Indirect Narrow Oop Plus Offset Operand
kvn@642 3625 // Note: x86 architecture doesn't support "scale * index + offset" without a base
kvn@642 3626 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
kvn@642 3627 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
kvn@1491 3628 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
kvn@642 3629 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3630 match(AddP (DecodeN reg) off);
kvn@642 3631
kvn@642 3632 op_cost(10);
kvn@642 3633 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
kvn@642 3634 interface(MEMORY_INTER) %{
kvn@642 3635 base(0xc); // R12
kvn@642 3636 index($reg);
kvn@642 3637 scale(0x3);
kvn@642 3638 disp($off);
kvn@642 3639 %}
kvn@642 3640 %}
kvn@642 3641
kvn@642 3642 // Indirect Memory Operand
kvn@642 3643 operand indirectNarrow(rRegN reg)
kvn@642 3644 %{
kvn@642 3645 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3646 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3647 match(DecodeN reg);
kvn@642 3648
kvn@642 3649 format %{ "[$reg]" %}
kvn@642 3650 interface(MEMORY_INTER) %{
kvn@642 3651 base($reg);
kvn@642 3652 index(0x4);
kvn@642 3653 scale(0x0);
kvn@642 3654 disp(0x0);
kvn@642 3655 %}
kvn@642 3656 %}
kvn@642 3657
kvn@642 3658 // Indirect Memory Plus Short Offset Operand
kvn@642 3659 operand indOffset8Narrow(rRegN reg, immL8 off)
kvn@642 3660 %{
kvn@642 3661 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3662 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3663 match(AddP (DecodeN reg) off);
kvn@642 3664
kvn@642 3665 format %{ "[$reg + $off (8-bit)]" %}
kvn@642 3666 interface(MEMORY_INTER) %{
kvn@642 3667 base($reg);
kvn@642 3668 index(0x4);
kvn@642 3669 scale(0x0);
kvn@642 3670 disp($off);
kvn@642 3671 %}
kvn@642 3672 %}
kvn@642 3673
kvn@642 3674 // Indirect Memory Plus Long Offset Operand
kvn@642 3675 operand indOffset32Narrow(rRegN reg, immL32 off)
kvn@642 3676 %{
kvn@642 3677 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3678 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3679 match(AddP (DecodeN reg) off);
kvn@642 3680
kvn@642 3681 format %{ "[$reg + $off (32-bit)]" %}
kvn@642 3682 interface(MEMORY_INTER) %{
kvn@642 3683 base($reg);
kvn@642 3684 index(0x4);
kvn@642 3685 scale(0x0);
kvn@642 3686 disp($off);
kvn@642 3687 %}
kvn@642 3688 %}
kvn@642 3689
kvn@642 3690 // Indirect Memory Plus Index Register Plus Offset Operand
kvn@642 3691 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
kvn@642 3692 %{
kvn@642 3693 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3694 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3695 match(AddP (AddP (DecodeN reg) lreg) off);
kvn@642 3696
kvn@642 3697 op_cost(10);
kvn@642 3698 format %{"[$reg + $off + $lreg]" %}
kvn@642 3699 interface(MEMORY_INTER) %{
kvn@642 3700 base($reg);
kvn@642 3701 index($lreg);
kvn@642 3702 scale(0x0);
kvn@642 3703 disp($off);
kvn@642 3704 %}
kvn@642 3705 %}
kvn@642 3706
kvn@642 3707 // Indirect Memory Plus Index Register Plus Offset Operand
kvn@642 3708 operand indIndexNarrow(rRegN reg, rRegL lreg)
kvn@642 3709 %{
kvn@642 3710 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3711 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3712 match(AddP (DecodeN reg) lreg);
kvn@642 3713
kvn@642 3714 op_cost(10);
kvn@642 3715 format %{"[$reg + $lreg]" %}
kvn@642 3716 interface(MEMORY_INTER) %{
kvn@642 3717 base($reg);
kvn@642 3718 index($lreg);
kvn@642 3719 scale(0x0);
kvn@642 3720 disp(0x0);
kvn@642 3721 %}
kvn@642 3722 %}
kvn@642 3723
kvn@642 3724 // Indirect Memory Times Scale Plus Index Register
kvn@642 3725 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
kvn@642 3726 %{
kvn@642 3727 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3728 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3729 match(AddP (DecodeN reg) (LShiftL lreg scale));
kvn@642 3730
kvn@642 3731 op_cost(10);
kvn@642 3732 format %{"[$reg + $lreg << $scale]" %}
kvn@642 3733 interface(MEMORY_INTER) %{
kvn@642 3734 base($reg);
kvn@642 3735 index($lreg);
kvn@642 3736 scale($scale);
kvn@642 3737 disp(0x0);
kvn@642 3738 %}
kvn@642 3739 %}
kvn@642 3740
kvn@642 3741 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
kvn@642 3742 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
kvn@642 3743 %{
kvn@642 3744 predicate(Universe::narrow_oop_shift() == 0);
kvn@642 3745 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3746 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
kvn@642 3747
kvn@642 3748 op_cost(10);
kvn@642 3749 format %{"[$reg + $off + $lreg << $scale]" %}
kvn@642 3750 interface(MEMORY_INTER) %{
kvn@642 3751 base($reg);
kvn@642 3752 index($lreg);
kvn@642 3753 scale($scale);
kvn@642 3754 disp($off);
kvn@642 3755 %}
kvn@642 3756 %}
kvn@642 3757
kvn@642 3758 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
kvn@642 3759 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
kvn@642 3760 %{
kvn@642 3761 constraint(ALLOC_IN_RC(ptr_reg));
kvn@642 3762 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
kvn@642 3763 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
kvn@642 3764
kvn@642 3765 op_cost(10);
kvn@642 3766 format %{"[$reg + $off + $idx << $scale]" %}
kvn@642 3767 interface(MEMORY_INTER) %{
kvn@642 3768 base($reg);
kvn@642 3769 index($idx);
kvn@642 3770 scale($scale);
kvn@642 3771 disp($off);
kvn@642 3772 %}
kvn@642 3773 %}
kvn@642 3774
duke@0 3775 //----------Special Memory Operands--------------------------------------------
duke@0 3776 // Stack Slot Operand - This operand is used for loading and storing temporary
duke@0 3777 // values on the stack where a match requires a value to
duke@0 3778 // flow through memory.
duke@0 3779 operand stackSlotP(sRegP reg)
duke@0 3780 %{
duke@0 3781 constraint(ALLOC_IN_RC(stack_slots));
duke@0 3782 // No match rule because this operand is only generated in matching
duke@0 3783
duke@0 3784 format %{ "[$reg]" %}
duke@0 3785 interface(MEMORY_INTER) %{
duke@0 3786 base(0x4); // RSP
duke@0 3787 index(0x4); // No Index
duke@0 3788 scale(0x0); // No Scale
duke@0 3789 disp($reg); // Stack Offset
duke@0 3790 %}
duke@0 3791 %}
duke@0 3792
duke@0 3793 operand stackSlotI(sRegI reg)
duke@0 3794 %{
duke@0 3795 constraint(ALLOC_IN_RC(stack_slots));
duke@0 3796 // No match rule because this operand is only generated in matching
duke@0 3797
duke@0 3798 format %{ "[$reg]" %}
duke@0 3799 interface(MEMORY_INTER) %{
duke@0 3800 base(0x4); // RSP
duke@0 3801 index(0x4); // No Index
duke@0 3802 scale(0x0); // No Scale
duke@0 3803 disp($reg); // Stack Offset
duke@0 3804 %}
duke@0 3805 %}
duke@0 3806
duke@0 3807 operand stackSlotF(sRegF reg)
duke@0 3808 %{
duke@0 3809 constraint(ALLOC_IN_RC(stack_slots));
duke@0 3810 // No match rule because this operand is only generated in matching
duke@0 3811
duke@0 3812 format %{ "[$reg]" %}
duke@0 3813 interface(MEMORY_INTER) %{
duke@0 3814 base(0x4); // RSP
duke@0 3815 index(0x4); // No Index
duke@0 3816 scale(0x0); // No Scale
duke@0 3817 disp($reg); // Stack Offset
duke@0 3818 %}
duke@0 3819 %}
duke@0 3820
duke@0 3821 operand stackSlotD(sRegD reg)
duke@0 3822 %{
duke@0 3823 constraint(ALLOC_IN_RC(stack_slots));
duke@0 3824 // No match rule because this operand is only generated in matching
duke@0 3825
duke@0 3826 format %{ "[$reg]" %}
duke@0 3827 interface(MEMORY_INTER) %{
duke@0 3828 base(0x4); // RSP
duke@0 3829 index(0x4); // No Index
duke@0 3830 scale(0x0); // No Scale
duke@0 3831 disp($reg); // Stack Offset
duke@0 3832 %}
duke@0 3833 %}
duke@0 3834 operand stackSlotL(sRegL reg)
duke@0 3835 %{
duke@0 3836 constraint(ALLOC_IN_RC(stack_slots));
duke@0 3837 // No match rule because this operand is only generated in matching
duke@0 3838
duke@0 3839 format %{ "[$reg]" %}
duke@0 3840 interface(MEMORY_INTER) %{
duke@0 3841 base(0x4); // RSP
duke@0 3842 index(0x4); // No Index
duke@0 3843 scale(0x0); // No Scale
duke@0 3844 disp($reg); // Stack Offset
duke@0 3845 %}
duke@0 3846 %}
duke