annotate src/cpu/x86/vm/x86_64.ad @ 2882:db2e64ca2d5a

7090968: Allow adlc register class to depend on runtime conditions Summary: allow reg_class definition as a function. Reviewed-by: kvn, never
author roland
date Tue, 22 Nov 2011 09:45:57 +0100
parents 6729bbc1fcd6
children 127b3692c168
rev   line source
duke@0 1 //
kvn@2167 2 // Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
duke@0 135 // Word a in each register holds a Float, words ab hold a Double. We
duke@0 136 // currently do not use the SIMD capabilities, so registers cd are
duke@0 137 // unused at the moment.
duke@0 138 // XMM8-XMM15 must be encoded with REX.
duke@0 139 // Linux ABI: No register preserved across function calls
duke@0 140 // XMM0-XMM7 might hold parameters
duke@0 141 // Windows ABI: XMM6-XMM15 preserved across function calls
duke@0 142 // XMM0-XMM3 might hold parameters
duke@0 143
duke@0 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
duke@0 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
duke@0 146
duke@0 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
duke@0 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
duke@0 149
duke@0 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
duke@0 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
duke@0 152
duke@0 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
duke@0 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
duke@0 155
duke@0 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
duke@0 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
duke@0 158
duke@0 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
duke@0 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
duke@0 161
duke@0 162 #ifdef _WIN64
duke@0 163
duke@0 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
duke@0 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 166
duke@0 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
duke@0 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 169
duke@0 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
duke@0 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 172
duke@0 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
duke@0 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 175
duke@0 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
duke@0 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 178
duke@0 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
duke@0 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 181
duke@0 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
duke@0 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 184
duke@0 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
duke@0 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 187
duke@0 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
duke@0 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 190
duke@0 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
duke@0 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 193
duke@0 194 #else
duke@0 195
duke@0 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
duke@0 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
duke@0 198
duke@0 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
duke@0 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
duke@0 201
duke@0 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
duke@0 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
duke@0 204
duke@0 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
duke@0 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
duke@0 207
duke@0 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
duke@0 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
duke@0 210
duke@0 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
duke@0 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
duke@0 213
duke@0 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
duke@0 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
duke@0 216
duke@0 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
duke@0 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
duke@0 219
duke@0 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
duke@0 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
duke@0 222
duke@0 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
duke@0 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
duke@0 225
duke@0 226 #endif // _WIN64
duke@0 227
duke@0 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
duke@0 229
duke@0 230 // Specify priority of register selection within phases of register
duke@0 231 // allocation. Highest priority is first. A useful heuristic is to
duke@0 232 // give registers a low priority when they are required by machine
duke@0 233 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 234 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 235 // which participate in fixed calling sequences should come last.
duke@0 236 // Registers which are used as pairs must fall on an even boundary.
duke@0 237
duke@0 238 alloc_class chunk0(R10, R10_H,
duke@0 239 R11, R11_H,
duke@0 240 R8, R8_H,
duke@0 241 R9, R9_H,
duke@0 242 R12, R12_H,
duke@0 243 RCX, RCX_H,
duke@0 244 RBX, RBX_H,
duke@0 245 RDI, RDI_H,
duke@0 246 RDX, RDX_H,
duke@0 247 RSI, RSI_H,
duke@0 248 RAX, RAX_H,
duke@0 249 RBP, RBP_H,
duke@0 250 R13, R13_H,
duke@0 251 R14, R14_H,
duke@0 252 R15, R15_H,
duke@0 253 RSP, RSP_H);
duke@0 254
duke@0 255 // XXX probably use 8-15 first on Linux
duke@0 256 alloc_class chunk1(XMM0, XMM0_H,
duke@0 257 XMM1, XMM1_H,
duke@0 258 XMM2, XMM2_H,
duke@0 259 XMM3, XMM3_H,
duke@0 260 XMM4, XMM4_H,
duke@0 261 XMM5, XMM5_H,
duke@0 262 XMM6, XMM6_H,
duke@0 263 XMM7, XMM7_H,
duke@0 264 XMM8, XMM8_H,
duke@0 265 XMM9, XMM9_H,
duke@0 266 XMM10, XMM10_H,
duke@0 267 XMM11, XMM11_H,
duke@0 268 XMM12, XMM12_H,
duke@0 269 XMM13, XMM13_H,
duke@0 270 XMM14, XMM14_H,
duke@0 271 XMM15, XMM15_H);
duke@0 272
duke@0 273 alloc_class chunk2(RFLAGS);
duke@0 274
duke@0 275
duke@0 276 //----------Architecture Description Register Classes--------------------------
duke@0 277 // Several register classes are automatically defined based upon information in
duke@0 278 // this architecture description.
duke@0 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 283 //
duke@0 284
duke@0 285 // Class for all pointer registers (including RSP)
duke@0 286 reg_class any_reg(RAX, RAX_H,
duke@0 287 RDX, RDX_H,
duke@0 288 RBP, RBP_H,
duke@0 289 RDI, RDI_H,
duke@0 290 RSI, RSI_H,
duke@0 291 RCX, RCX_H,
duke@0 292 RBX, RBX_H,
duke@0 293 RSP, RSP_H,
duke@0 294 R8, R8_H,
duke@0 295 R9, R9_H,
duke@0 296 R10, R10_H,
duke@0 297 R11, R11_H,
duke@0 298 R12, R12_H,
duke@0 299 R13, R13_H,
duke@0 300 R14, R14_H,
duke@0 301 R15, R15_H);
duke@0 302
duke@0 303 // Class for all pointer registers except RSP
duke@0 304 reg_class ptr_reg(RAX, RAX_H,
duke@0 305 RDX, RDX_H,
duke@0 306 RBP, RBP_H,
duke@0 307 RDI, RDI_H,
duke@0 308 RSI, RSI_H,
duke@0 309 RCX, RCX_H,
duke@0 310 RBX, RBX_H,
duke@0 311 R8, R8_H,
duke@0 312 R9, R9_H,
duke@0 313 R10, R10_H,
duke@0 314 R11, R11_H,
duke@0 315 R13, R13_H,
duke@0 316 R14, R14_H);
duke@0 317
duke@0 318 // Class for all pointer registers except RAX and RSP
duke@0 319 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 320 RBP, RBP_H,
duke@0 321 RDI, RDI_H,
duke@0 322 RSI, RSI_H,
duke@0 323 RCX, RCX_H,
duke@0 324 RBX, RBX_H,
duke@0 325 R8, R8_H,
duke@0 326 R9, R9_H,
duke@0 327 R10, R10_H,
duke@0 328 R11, R11_H,
duke@0 329 R13, R13_H,
duke@0 330 R14, R14_H);
duke@0 331
duke@0 332 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 333 RAX, RAX_H,
duke@0 334 RDI, RDI_H,
duke@0 335 RSI, RSI_H,
duke@0 336 RCX, RCX_H,
duke@0 337 RBX, RBX_H,
duke@0 338 R8, R8_H,
duke@0 339 R9, R9_H,
duke@0 340 R10, R10_H,
duke@0 341 R11, R11_H,
duke@0 342 R13, R13_H,
duke@0 343 R14, R14_H);
duke@0 344
duke@0 345 // Class for all pointer registers except RAX, RBX and RSP
duke@0 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 347 RBP, RBP_H,
duke@0 348 RDI, RDI_H,
duke@0 349 RSI, RSI_H,
duke@0 350 RCX, RCX_H,
duke@0 351 R8, R8_H,
duke@0 352 R9, R9_H,
duke@0 353 R10, R10_H,
duke@0 354 R11, R11_H,
duke@0 355 R13, R13_H,
duke@0 356 R14, R14_H);
duke@0 357
duke@0 358 // Singleton class for RAX pointer register
duke@0 359 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 360
duke@0 361 // Singleton class for RBX pointer register
duke@0 362 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 363
duke@0 364 // Singleton class for RSI pointer register
duke@0 365 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 366
duke@0 367 // Singleton class for RDI pointer register
duke@0 368 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 369
duke@0 370 // Singleton class for RBP pointer register
duke@0 371 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 372
duke@0 373 // Singleton class for stack pointer
duke@0 374 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 375
duke@0 376 // Singleton class for TLS pointer
duke@0 377 reg_class ptr_r15_reg(R15, R15_H);
duke@0 378
duke@0 379 // Class for all long registers (except RSP)
duke@0 380 reg_class long_reg(RAX, RAX_H,
duke@0 381 RDX, RDX_H,
duke@0 382 RBP, RBP_H,
duke@0 383 RDI, RDI_H,
duke@0 384 RSI, RSI_H,
duke@0 385 RCX, RCX_H,
duke@0 386 RBX, RBX_H,
duke@0 387 R8, R8_H,
duke@0 388 R9, R9_H,
duke@0 389 R10, R10_H,
duke@0 390 R11, R11_H,
duke@0 391 R13, R13_H,
duke@0 392 R14, R14_H);
duke@0 393
duke@0 394 // Class for all long registers except RAX, RDX (and RSP)
duke@0 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 396 RDI, RDI_H,
duke@0 397 RSI, RSI_H,
duke@0 398 RCX, RCX_H,
duke@0 399 RBX, RBX_H,
duke@0 400 R8, R8_H,
duke@0 401 R9, R9_H,
duke@0 402 R10, R10_H,
duke@0 403 R11, R11_H,
duke@0 404 R13, R13_H,
duke@0 405 R14, R14_H);
duke@0 406
duke@0 407 // Class for all long registers except RCX (and RSP)
duke@0 408 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 409 RDI, RDI_H,
duke@0 410 RSI, RSI_H,
duke@0 411 RAX, RAX_H,
duke@0 412 RDX, RDX_H,
duke@0 413 RBX, RBX_H,
duke@0 414 R8, R8_H,
duke@0 415 R9, R9_H,
duke@0 416 R10, R10_H,
duke@0 417 R11, R11_H,
duke@0 418 R13, R13_H,
duke@0 419 R14, R14_H);
duke@0 420
duke@0 421 // Class for all long registers except RAX (and RSP)
duke@0 422 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 423 RDX, RDX_H,
duke@0 424 RDI, RDI_H,
duke@0 425 RSI, RSI_H,
duke@0 426 RCX, RCX_H,
duke@0 427 RBX, RBX_H,
duke@0 428 R8, R8_H,
duke@0 429 R9, R9_H,
duke@0 430 R10, R10_H,
duke@0 431 R11, R11_H,
duke@0 432 R13, R13_H,
duke@0 433 R14, R14_H);
duke@0 434
duke@0 435 // Singleton class for RAX long register
duke@0 436 reg_class long_rax_reg(RAX, RAX_H);
duke@0 437
duke@0 438 // Singleton class for RCX long register
duke@0 439 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 440
duke@0 441 // Singleton class for RDX long register
duke@0 442 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 443
duke@0 444 // Class for all int registers (except RSP)
duke@0 445 reg_class int_reg(RAX,
duke@0 446 RDX,
duke@0 447 RBP,
duke@0 448 RDI,
duke@0 449 RSI,
duke@0 450 RCX,
duke@0 451 RBX,
duke@0 452 R8,
duke@0 453 R9,
duke@0 454 R10,
duke@0 455 R11,
duke@0 456 R13,
duke@0 457 R14);
duke@0 458
duke@0 459 // Class for all int registers except RCX (and RSP)
duke@0 460 reg_class int_no_rcx_reg(RAX,
duke@0 461 RDX,
duke@0 462 RBP,
duke@0 463 RDI,
duke@0 464 RSI,
duke@0 465 RBX,
duke@0 466 R8,
duke@0 467 R9,
duke@0 468 R10,
duke@0 469 R11,
duke@0 470 R13,
duke@0 471 R14);
duke@0 472
duke@0 473 // Class for all int registers except RAX, RDX (and RSP)
duke@0 474 reg_class int_no_rax_rdx_reg(RBP,
never@304 475 RDI,
duke@0 476 RSI,
duke@0 477 RCX,
duke@0 478 RBX,
duke@0 479 R8,
duke@0 480 R9,
duke@0 481 R10,
duke@0 482 R11,
duke@0 483 R13,
duke@0 484 R14);
duke@0 485
duke@0 486 // Singleton class for RAX int register
duke@0 487 reg_class int_rax_reg(RAX);
duke@0 488
duke@0 489 // Singleton class for RBX int register
duke@0 490 reg_class int_rbx_reg(RBX);
duke@0 491
duke@0 492 // Singleton class for RCX int register
duke@0 493 reg_class int_rcx_reg(RCX);
duke@0 494
duke@0 495 // Singleton class for RCX int register
duke@0 496 reg_class int_rdx_reg(RDX);
duke@0 497
duke@0 498 // Singleton class for RCX int register
duke@0 499 reg_class int_rdi_reg(RDI);
duke@0 500
duke@0 501 // Singleton class for instruction pointer
duke@0 502 // reg_class ip_reg(RIP);
duke@0 503
duke@0 504 // Singleton class for condition codes
duke@0 505 reg_class int_flags(RFLAGS);
duke@0 506
duke@0 507 // Class for all float registers
duke@0 508 reg_class float_reg(XMM0,
duke@0 509 XMM1,
duke@0 510 XMM2,
duke@0 511 XMM3,
duke@0 512 XMM4,
duke@0 513 XMM5,
duke@0 514 XMM6,
duke@0 515 XMM7,
duke@0 516 XMM8,
duke@0 517 XMM9,
duke@0 518 XMM10,
duke@0 519 XMM11,
duke@0 520 XMM12,
duke@0 521 XMM13,
duke@0 522 XMM14,
duke@0 523 XMM15);
duke@0 524
duke@0 525 // Class for all double registers
duke@0 526 reg_class double_reg(XMM0, XMM0_H,
duke@0 527 XMM1, XMM1_H,
duke@0 528 XMM2, XMM2_H,
duke@0 529 XMM3, XMM3_H,
duke@0 530 XMM4, XMM4_H,
duke@0 531 XMM5, XMM5_H,
duke@0 532 XMM6, XMM6_H,
duke@0 533 XMM7, XMM7_H,
duke@0 534 XMM8, XMM8_H,
duke@0 535 XMM9, XMM9_H,
duke@0 536 XMM10, XMM10_H,
duke@0 537 XMM11, XMM11_H,
duke@0 538 XMM12, XMM12_H,
duke@0 539 XMM13, XMM13_H,
duke@0 540 XMM14, XMM14_H,
duke@0 541 XMM15, XMM15_H);
duke@0 542 %}
duke@0 543
duke@0 544
duke@0 545 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 546 // This is a block of C++ code which provides values, functions, and
duke@0 547 // definitions necessary in the rest of the architecture description
duke@0 548 source %{
never@304 549 #define RELOC_IMM64 Assembler::imm_operand
duke@0 550 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 551
duke@0 552 #define __ _masm.
duke@0 553
twisti@1137 554 static int preserve_SP_size() {
twisti@1137 555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
twisti@1137 556 }
twisti@1137 557
duke@0 558 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 559 // from the start of the call to the point where the return address
duke@0 560 // will point.
duke@0 561 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 562 {
twisti@1137 563 int offset = 5; // 5 bytes from start of call to where return address points
twisti@1137 564 if (_method_handle_invoke)
twisti@1137 565 offset += preserve_SP_size();
twisti@1137 566 return offset;
duke@0 567 }
duke@0 568
duke@0 569 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 570 {
duke@0 571 return 15; // 15 bytes from start of call to where return address points
duke@0 572 }
duke@0 573
duke@0 574 // In os_cpu .ad file
duke@0 575 // int MachCallRuntimeNode::ret_addr_offset()
duke@0 576
iveresov@2251 577 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 578 // it does if the polling page is more than disp32 away.
duke@0 579 bool SafePointNode::needs_polling_address_input()
duke@0 580 {
iveresov@2251 581 return Assembler::is_polling_page_far();
duke@0 582 }
duke@0 583
duke@0 584 //
duke@0 585 // Compute padding required for nodes which need alignment
duke@0 586 //
duke@0 587
duke@0 588 // The address of the call instruction needs to be 4-byte aligned to
duke@0 589 // ensure that it does not span a cache line so that it can be patched.
duke@0 590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 591 {
duke@0 592 current_offset += 1; // skip call opcode byte
duke@0 593 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 594 }
duke@0 595
duke@0 596 // The address of the call instruction needs to be 4-byte aligned to
duke@0 597 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 598 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 599 {
twisti@1137 600 current_offset += preserve_SP_size(); // skip mov rbp, rsp
twisti@1137 601 current_offset += 1; // skip call opcode byte
twisti@1137 602 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 603 }
twisti@1137 604
twisti@1137 605 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 606 // ensure that it does not span a cache line so that it can be patched.
duke@0 607 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 608 {
duke@0 609 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 610 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 611 }
duke@0 612
duke@0 613 #ifndef PRODUCT
duke@0 614 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 615 {
duke@0 616 st->print("INT3");
duke@0 617 }
duke@0 618 #endif
duke@0 619
duke@0 620 // EMIT_RM()
twisti@1668 621 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 622 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 623 cbuf.insts()->emit_int8(c);
duke@0 624 }
duke@0 625
duke@0 626 // EMIT_CC()
twisti@1668 627 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 628 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 629 cbuf.insts()->emit_int8(c);
duke@0 630 }
duke@0 631
duke@0 632 // EMIT_OPCODE()
twisti@1668 633 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 634 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 635 }
duke@0 636
duke@0 637 // EMIT_OPCODE() w/ relocation information
duke@0 638 void emit_opcode(CodeBuffer &cbuf,
duke@0 639 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 640 {
twisti@1668 641 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 642 emit_opcode(cbuf, code);
duke@0 643 }
duke@0 644
duke@0 645 // EMIT_D8()
twisti@1668 646 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 647 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 648 }
duke@0 649
duke@0 650 // EMIT_D16()
twisti@1668 651 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 652 cbuf.insts()->emit_int16(d16);
duke@0 653 }
duke@0 654
duke@0 655 // EMIT_D32()
twisti@1668 656 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 657 cbuf.insts()->emit_int32(d32);
duke@0 658 }
duke@0 659
duke@0 660 // EMIT_D64()
twisti@1668 661 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 662 cbuf.insts()->emit_int64(d64);
duke@0 663 }
duke@0 664
duke@0 665 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 666 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 667 int d32,
duke@0 668 relocInfo::relocType reloc,
duke@0 669 int format)
duke@0 670 {
duke@0 671 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 672 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 673 cbuf.insts()->emit_int32(d32);
duke@0 674 }
duke@0 675
duke@0 676 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 677 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 678 #ifdef ASSERT
duke@0 679 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 680 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
jrose@989 681 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 682 }
duke@0 683 #endif
twisti@1668 684 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 685 cbuf.insts()->emit_int32(d32);
duke@0 686 }
duke@0 687
duke@0 688 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 689 address next_ip = cbuf.insts_end() + 4;
duke@0 690 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 691 external_word_Relocation::spec(addr),
duke@0 692 RELOC_DISP32);
duke@0 693 }
duke@0 694
duke@0 695
duke@0 696 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 697 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 698 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 699 cbuf.insts()->emit_int64(d64);
duke@0 700 }
duke@0 701
duke@0 702 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 703 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 704 #ifdef ASSERT
duke@0 705 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 706 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
jrose@989 707 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
jrose@989 708 "cannot embed scavengable oops in code");
duke@0 709 }
duke@0 710 #endif
twisti@1668 711 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 712 cbuf.insts()->emit_int64(d64);
duke@0 713 }
duke@0 714
duke@0 715 // Access stack slot for load or store
duke@0 716 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 717 {
duke@0 718 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 719 if (-0x80 <= disp && disp < 0x80) {
duke@0 720 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 721 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 722 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 723 } else {
duke@0 724 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 725 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 726 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 727 }
duke@0 728 }
duke@0 729
duke@0 730 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 731 void encode_RegMem(CodeBuffer &cbuf,
duke@0 732 int reg,
duke@0 733 int base, int index, int scale, int disp, bool disp_is_oop)
duke@0 734 {
duke@0 735 assert(!disp_is_oop, "cannot have disp");
duke@0 736 int regenc = reg & 7;
duke@0 737 int baseenc = base & 7;
duke@0 738 int indexenc = index & 7;
duke@0 739
duke@0 740 // There is no index & no scale, use form without SIB byte
duke@0 741 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 742 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 743 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 744 emit_rm(cbuf, 0x0, regenc, baseenc); // *
duke@0 745 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 746 // If 8-bit displacement, mode 0x1
duke@0 747 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 748 emit_d8(cbuf, disp);
duke@0 749 } else {
duke@0 750 // If 32-bit displacement
duke@0 751 if (base == -1) { // Special flag for absolute address
duke@0 752 emit_rm(cbuf, 0x0, regenc, 0x5); // *
duke@0 753 if (disp_is_oop) {
duke@0 754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 755 } else {
duke@0 756 emit_d32(cbuf, disp);
duke@0 757 }
duke@0 758 } else {
duke@0 759 // Normal base + offset
duke@0 760 emit_rm(cbuf, 0x2, regenc, baseenc); // *
duke@0 761 if (disp_is_oop) {
duke@0 762 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 763 } else {
duke@0 764 emit_d32(cbuf, disp);
duke@0 765 }
duke@0 766 }
duke@0 767 }
duke@0 768 } else {
duke@0 769 // Else, encode with the SIB byte
duke@0 770 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 771 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 772 // If no displacement
duke@0 773 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 774 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 775 } else {
duke@0 776 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
duke@0 777 // If 8-bit displacement, mode 0x1
duke@0 778 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 779 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 780 emit_d8(cbuf, disp);
duke@0 781 } else {
duke@0 782 // If 32-bit displacement
duke@0 783 if (base == 0x04 ) {
duke@0 784 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 785 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 786 } else {
duke@0 787 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 788 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 789 }
duke@0 790 if (disp_is_oop) {
duke@0 791 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 792 } else {
duke@0 793 emit_d32(cbuf, disp);
duke@0 794 }
duke@0 795 }
duke@0 796 }
duke@0 797 }
duke@0 798 }
duke@0 799
duke@0 800 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
duke@0 801 {
duke@0 802 if (dstenc != srcenc) {
duke@0 803 if (dstenc < 8) {
duke@0 804 if (srcenc >= 8) {
duke@0 805 emit_opcode(cbuf, Assembler::REX_B);
duke@0 806 srcenc -= 8;
duke@0 807 }
duke@0 808 } else {
duke@0 809 if (srcenc < 8) {
duke@0 810 emit_opcode(cbuf, Assembler::REX_R);
duke@0 811 } else {
duke@0 812 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 813 srcenc -= 8;
duke@0 814 }
duke@0 815 dstenc -= 8;
duke@0 816 }
duke@0 817
duke@0 818 emit_opcode(cbuf, 0x8B);
duke@0 819 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 820 }
duke@0 821 }
duke@0 822
duke@0 823 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
duke@0 824 if( dst_encoding == src_encoding ) {
duke@0 825 // reg-reg copy, use an empty encoding
duke@0 826 } else {
duke@0 827 MacroAssembler _masm(&cbuf);
duke@0 828
duke@0 829 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
duke@0 830 }
duke@0 831 }
duke@0 832
never@2545 833 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 834 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 835 Label exit;
never@2545 836 __ jccb(Assembler::noParity, exit);
never@2545 837 __ pushf();
never@2545 838 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 839 __ popf();
never@2545 840 __ bind(exit);
never@2545 841 __ nop(); // (target for branch to avoid branch to branch)
never@2545 842 }
never@2545 843
duke@0 844
duke@0 845 //=============================================================================
twisti@1915 846 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 847
twisti@2875 848 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 849 return 0; // absolute addressing, no offset
twisti@2875 850 }
twisti@2875 851
twisti@1915 852 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 853 // Empty encoding
twisti@1915 854 }
twisti@1915 855
twisti@1915 856 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 857 return 0;
twisti@1915 858 }
twisti@1915 859
twisti@1915 860 #ifndef PRODUCT
twisti@1915 861 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 862 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 863 }
twisti@1915 864 #endif
twisti@1915 865
twisti@1915 866
twisti@1915 867 //=============================================================================
duke@0 868 #ifndef PRODUCT
duke@0 869 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 870 {
duke@0 871 Compile* C = ra_->C;
duke@0 872
duke@0 873 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 874 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 875 // Remove wordSize for return adr already pushed
duke@0 876 // and another for the RBP we are going to save
duke@0 877 framesize -= 2*wordSize;
duke@0 878 bool need_nop = true;
duke@0 879
duke@0 880 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 881 // We require that their callers must bang for them. But be
duke@0 882 // careful, because some VM calls (such as call site linkage) can
duke@0 883 // use several kilobytes of stack. But the stack safety zone should
duke@0 884 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 885 if (C->need_stack_bang(framesize)) {
duke@0 886 st->print_cr("# stack bang"); st->print("\t");
duke@0 887 need_nop = false;
duke@0 888 }
duke@0 889 st->print_cr("pushq rbp"); st->print("\t");
duke@0 890
duke@0 891 if (VerifyStackAtCalls) {
duke@0 892 // Majik cookie to verify stack depth
duke@0 893 st->print_cr("pushq 0xffffffffbadb100d"
duke@0 894 "\t# Majik cookie for stack depth check");
duke@0 895 st->print("\t");
duke@0 896 framesize -= wordSize; // Remove 2 for cookie
duke@0 897 need_nop = false;
duke@0 898 }
duke@0 899
duke@0 900 if (framesize) {
duke@0 901 st->print("subq rsp, #%d\t# Create frame", framesize);
duke@0 902 if (framesize < 0x80 && need_nop) {
duke@0 903 st->print("\n\tnop\t# nop for patch_verified_entry");
duke@0 904 }
duke@0 905 }
duke@0 906 }
duke@0 907 #endif
duke@0 908
duke@0 909 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 910 {
duke@0 911 Compile* C = ra_->C;
duke@0 912
duke@0 913 // WARNING: Initial instruction MUST be 5 bytes or longer so that
duke@0 914 // NativeJump::patch_verified_entry will be able to patch out the entry
duke@0 915 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
duke@0 916 // depth is ok at 5 bytes, the frame allocation can be either 3 or
duke@0 917 // 6 bytes. So if we don't do the fldcw or the push then we must
duke@0 918 // use the 6 byte frame allocation even if we have no frame. :-(
duke@0 919 // If method sets FPU control word do it now
duke@0 920
duke@0 921 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 922 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 923 // Remove wordSize for return adr already pushed
duke@0 924 // and another for the RBP we are going to save
duke@0 925 framesize -= 2*wordSize;
duke@0 926 bool need_nop = true;
duke@0 927
duke@0 928 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 929 // We require that their callers must bang for them. But be
duke@0 930 // careful, because some VM calls (such as call site linkage) can
duke@0 931 // use several kilobytes of stack. But the stack safety zone should
duke@0 932 // account for that. See bugs 4446381, 4468289, 4497237.
duke@0 933 if (C->need_stack_bang(framesize)) {
duke@0 934 MacroAssembler masm(&cbuf);
duke@0 935 masm.generate_stack_overflow_check(framesize);
duke@0 936 need_nop = false;
duke@0 937 }
duke@0 938
duke@0 939 // We always push rbp so that on return to interpreter rbp will be
duke@0 940 // restored correctly and we can correct the stack.
duke@0 941 emit_opcode(cbuf, 0x50 | RBP_enc);
duke@0 942
duke@0 943 if (VerifyStackAtCalls) {
duke@0 944 // Majik cookie to verify stack depth
duke@0 945 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
duke@0 946 emit_d32(cbuf, 0xbadb100d);
duke@0 947 framesize -= wordSize; // Remove 2 for cookie
duke@0 948 need_nop = false;
duke@0 949 }
duke@0 950
duke@0 951 if (framesize) {
duke@0 952 emit_opcode(cbuf, Assembler::REX_W);
duke@0 953 if (framesize < 0x80) {
duke@0 954 emit_opcode(cbuf, 0x83); // sub SP,#framesize
duke@0 955 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 956 emit_d8(cbuf, framesize);
duke@0 957 if (need_nop) {
duke@0 958 emit_opcode(cbuf, 0x90); // nop
duke@0 959 }
duke@0 960 } else {
duke@0 961 emit_opcode(cbuf, 0x81); // sub SP,#framesize
duke@0 962 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
duke@0 963 emit_d32(cbuf, framesize);
duke@0 964 }
duke@0 965 }
duke@0 966
twisti@1668 967 C->set_frame_complete(cbuf.insts_size());
duke@0 968
duke@0 969 #ifdef ASSERT
duke@0 970 if (VerifyStackAtCalls) {
duke@0 971 Label L;
duke@0 972 MacroAssembler masm(&cbuf);
never@304 973 masm.push(rax);
never@304 974 masm.mov(rax, rsp);
never@304 975 masm.andptr(rax, StackAlignmentInBytes-1);
never@304 976 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
never@304 977 masm.pop(rax);
duke@0 978 masm.jcc(Assembler::equal, L);
duke@0 979 masm.stop("Stack is not properly aligned!");
duke@0 980 masm.bind(L);
duke@0 981 }
duke@0 982 #endif
twisti@2875 983
twisti@2875 984 if (C->has_mach_constant_base_node()) {
twisti@2875 985 // NOTE: We set the table base offset here because users might be
twisti@2875 986 // emitted before MachConstantBaseNode.
twisti@2875 987 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 988 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 989 }
duke@0 990 }
duke@0 991
duke@0 992 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 993 {
duke@0 994 return MachNode::size(ra_); // too many variables; just compute it
duke@0 995 // the hard way
duke@0 996 }
duke@0 997
duke@0 998 int MachPrologNode::reloc() const
duke@0 999 {
duke@0 1000 return 0; // a large enough number
duke@0 1001 }
duke@0 1002
duke@0 1003 //=============================================================================
duke@0 1004 #ifndef PRODUCT
duke@0 1005 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1006 {
duke@0 1007 Compile* C = ra_->C;
duke@0 1008 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1009 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1010 // Remove word for return adr already pushed
duke@0 1011 // and RBP
duke@0 1012 framesize -= 2*wordSize;
duke@0 1013
duke@0 1014 if (framesize) {
iveresov@2251 1015 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 1016 st->print("\t");
duke@0 1017 }
duke@0 1018
iveresov@2251 1019 st->print_cr("popq rbp");
duke@0 1020 if (do_polling() && C->is_method_compilation()) {
duke@0 1021 st->print("\t");
iveresov@2251 1022 if (Assembler::is_polling_page_far()) {
iveresov@2251 1023 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 1024 "testl rax, [rscratch1]\t"
iveresov@2251 1025 "# Safepoint: poll for GC");
iveresov@2251 1026 } else {
iveresov@2251 1027 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 1028 "# Safepoint: poll for GC");
iveresov@2251 1029 }
duke@0 1030 }
duke@0 1031 }
duke@0 1032 #endif
duke@0 1033
duke@0 1034 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1035 {
duke@0 1036 Compile* C = ra_->C;
duke@0 1037 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1038 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 1039 // Remove word for return adr already pushed
duke@0 1040 // and RBP
duke@0 1041 framesize -= 2*wordSize;
duke@0 1042
duke@0 1043 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 1044
duke@0 1045 if (framesize) {
duke@0 1046 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1047 if (framesize < 0x80) {
duke@0 1048 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 1049 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1050 emit_d8(cbuf, framesize);
duke@0 1051 } else {
duke@0 1052 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 1053 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 1054 emit_d32(cbuf, framesize);
duke@0 1055 }
duke@0 1056 }
duke@0 1057
duke@0 1058 // popq rbp
duke@0 1059 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 1060
duke@0 1061 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 1062 MacroAssembler _masm(&cbuf);
iveresov@2251 1063 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 1064 if (Assembler::is_polling_page_far()) {
iveresov@2251 1065 __ lea(rscratch1, polling_page);
iveresov@2251 1066 __ relocate(relocInfo::poll_return_type);
iveresov@2251 1067 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 1068 } else {
iveresov@2251 1069 __ testl(rax, polling_page);
iveresov@2251 1070 }
duke@0 1071 }
duke@0 1072 }
duke@0 1073
duke@0 1074 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 1075 {
iveresov@2251 1076 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 1077 // the hard way
duke@0 1078 }
duke@0 1079
duke@0 1080 int MachEpilogNode::reloc() const
duke@0 1081 {
duke@0 1082 return 2; // a large enough number
duke@0 1083 }
duke@0 1084
duke@0 1085 const Pipeline* MachEpilogNode::pipeline() const
duke@0 1086 {
duke@0 1087 return MachNode::pipeline_class();
duke@0 1088 }
duke@0 1089
duke@0 1090 int MachEpilogNode::safepoint_offset() const
duke@0 1091 {
duke@0 1092 return 0;
duke@0 1093 }
duke@0 1094
duke@0 1095 //=============================================================================
duke@0 1096
duke@0 1097 enum RC {
duke@0 1098 rc_bad,
duke@0 1099 rc_int,
duke@0 1100 rc_float,
duke@0 1101 rc_stack
duke@0 1102 };
duke@0 1103
duke@0 1104 static enum RC rc_class(OptoReg::Name reg)
duke@0 1105 {
duke@0 1106 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1107
duke@0 1108 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1109
duke@0 1110 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1111
duke@0 1112 if (r->is_Register()) return rc_int;
duke@0 1113
duke@0 1114 assert(r->is_XMMRegister(), "must be");
duke@0 1115 return rc_float;
duke@0 1116 }
duke@0 1117
duke@0 1118 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 1119 PhaseRegAlloc* ra_,
duke@0 1120 bool do_size,
duke@0 1121 outputStream* st) const
duke@0 1122 {
duke@0 1123
duke@0 1124 // Get registers to move
duke@0 1125 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1126 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1127 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 1128 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 1129
duke@0 1130 enum RC src_second_rc = rc_class(src_second);
duke@0 1131 enum RC src_first_rc = rc_class(src_first);
duke@0 1132 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1133 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1134
duke@0 1135 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 1136 "must move at least 1 register" );
duke@0 1137
duke@0 1138 if (src_first == dst_first && src_second == dst_second) {
duke@0 1139 // Self copy, no move
duke@0 1140 return 0;
duke@0 1141 } else if (src_first_rc == rc_stack) {
duke@0 1142 // mem ->
duke@0 1143 if (dst_first_rc == rc_stack) {
duke@0 1144 // mem -> mem
duke@0 1145 assert(src_second != dst_first, "overlap");
duke@0 1146 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1147 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1148 // 64-bit
duke@0 1149 int src_offset = ra_->reg2offset(src_first);
duke@0 1150 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1151 if (cbuf) {
duke@0 1152 emit_opcode(*cbuf, 0xFF);
duke@0 1153 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
duke@0 1154
duke@0 1155 emit_opcode(*cbuf, 0x8F);
duke@0 1156 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
duke@0 1157
duke@0 1158 #ifndef PRODUCT
duke@0 1159 } else if (!do_size) {
duke@0 1160 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
duke@0 1161 "popq [rsp + #%d]",
duke@0 1162 src_offset,
duke@0 1163 dst_offset);
duke@0 1164 #endif
duke@0 1165 }
duke@0 1166 return
duke@0 1167 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
duke@0 1168 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
duke@0 1169 } else {
duke@0 1170 // 32-bit
duke@0 1171 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1172 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1173 // No pushl/popl, so:
duke@0 1174 int src_offset = ra_->reg2offset(src_first);
duke@0 1175 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1176 if (cbuf) {
duke@0 1177 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1178 emit_opcode(*cbuf, 0x89);
duke@0 1179 emit_opcode(*cbuf, 0x44);
duke@0 1180 emit_opcode(*cbuf, 0x24);
duke@0 1181 emit_opcode(*cbuf, 0xF8);
duke@0 1182
duke@0 1183 emit_opcode(*cbuf, 0x8B);
duke@0 1184 encode_RegMem(*cbuf,
duke@0 1185 RAX_enc,
duke@0 1186 RSP_enc, 0x4, 0, src_offset,
duke@0 1187 false);
duke@0 1188
duke@0 1189 emit_opcode(*cbuf, 0x89);
duke@0 1190 encode_RegMem(*cbuf,
duke@0 1191 RAX_enc,
duke@0 1192 RSP_enc, 0x4, 0, dst_offset,
duke@0 1193 false);
duke@0 1194
duke@0 1195 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1196 emit_opcode(*cbuf, 0x8B);
duke@0 1197 emit_opcode(*cbuf, 0x44);
duke@0 1198 emit_opcode(*cbuf, 0x24);
duke@0 1199 emit_opcode(*cbuf, 0xF8);
duke@0 1200
duke@0 1201 #ifndef PRODUCT
duke@0 1202 } else if (!do_size) {
duke@0 1203 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
duke@0 1204 "movl rax, [rsp + #%d]\n\t"
duke@0 1205 "movl [rsp + #%d], rax\n\t"
duke@0 1206 "movq rax, [rsp - #8]",
duke@0 1207 src_offset,
duke@0 1208 dst_offset);
duke@0 1209 #endif
duke@0 1210 }
duke@0 1211 return
duke@0 1212 5 + // movq
duke@0 1213 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1214 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
duke@0 1215 5; // movq
duke@0 1216 }
duke@0 1217 } else if (dst_first_rc == rc_int) {
duke@0 1218 // mem -> gpr
duke@0 1219 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1220 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1221 // 64-bit
duke@0 1222 int offset = ra_->reg2offset(src_first);
duke@0 1223 if (cbuf) {
duke@0 1224 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1225 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1226 } else {
duke@0 1227 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1228 }
duke@0 1229 emit_opcode(*cbuf, 0x8B);
duke@0 1230 encode_RegMem(*cbuf,
duke@0 1231 Matcher::_regEncode[dst_first],
duke@0 1232 RSP_enc, 0x4, 0, offset,
duke@0 1233 false);
duke@0 1234 #ifndef PRODUCT
duke@0 1235 } else if (!do_size) {
duke@0 1236 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1237 Matcher::regName[dst_first],
duke@0 1238 offset);
duke@0 1239 #endif
duke@0 1240 }
duke@0 1241 return
duke@0 1242 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1243 } else {
duke@0 1244 // 32-bit
duke@0 1245 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1246 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1247 int offset = ra_->reg2offset(src_first);
duke@0 1248 if (cbuf) {
duke@0 1249 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1250 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1251 }
duke@0 1252 emit_opcode(*cbuf, 0x8B);
duke@0 1253 encode_RegMem(*cbuf,
duke@0 1254 Matcher::_regEncode[dst_first],
duke@0 1255 RSP_enc, 0x4, 0, offset,
duke@0 1256 false);
duke@0 1257 #ifndef PRODUCT
duke@0 1258 } else if (!do_size) {
duke@0 1259 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1260 Matcher::regName[dst_first],
duke@0 1261 offset);
duke@0 1262 #endif
duke@0 1263 }
duke@0 1264 return
duke@0 1265 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1266 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1267 ? 3
duke@0 1268 : 4); // REX
duke@0 1269 }
duke@0 1270 } else if (dst_first_rc == rc_float) {
duke@0 1271 // mem-> xmm
duke@0 1272 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1273 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1274 // 64-bit
duke@0 1275 int offset = ra_->reg2offset(src_first);
duke@0 1276 if (cbuf) {
duke@0 1277 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 1278 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1279 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1280 }
duke@0 1281 emit_opcode(*cbuf, 0x0F);
duke@0 1282 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
duke@0 1283 encode_RegMem(*cbuf,
duke@0 1284 Matcher::_regEncode[dst_first],
duke@0 1285 RSP_enc, 0x4, 0, offset,
duke@0 1286 false);
duke@0 1287 #ifndef PRODUCT
duke@0 1288 } else if (!do_size) {
duke@0 1289 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1290 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1291 Matcher::regName[dst_first],
duke@0 1292 offset);
duke@0 1293 #endif
duke@0 1294 }
duke@0 1295 return
duke@0 1296 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1297 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1298 ? 5
duke@0 1299 : 6); // REX
duke@0 1300 } else {
duke@0 1301 // 32-bit
duke@0 1302 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1303 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1304 int offset = ra_->reg2offset(src_first);
duke@0 1305 if (cbuf) {
duke@0 1306 emit_opcode(*cbuf, 0xF3);
duke@0 1307 if (Matcher::_regEncode[dst_first] >= 8) {
duke@0 1308 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1309 }
duke@0 1310 emit_opcode(*cbuf, 0x0F);
duke@0 1311 emit_opcode(*cbuf, 0x10);
duke@0 1312 encode_RegMem(*cbuf,
duke@0 1313 Matcher::_regEncode[dst_first],
duke@0 1314 RSP_enc, 0x4, 0, offset,
duke@0 1315 false);
duke@0 1316 #ifndef PRODUCT
duke@0 1317 } else if (!do_size) {
duke@0 1318 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1319 Matcher::regName[dst_first],
duke@0 1320 offset);
duke@0 1321 #endif
duke@0 1322 }
duke@0 1323 return
duke@0 1324 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1325 ((Matcher::_regEncode[dst_first] < 8)
duke@0 1326 ? 5
duke@0 1327 : 6); // REX
duke@0 1328 }
duke@0 1329 }
duke@0 1330 } else if (src_first_rc == rc_int) {
duke@0 1331 // gpr ->
duke@0 1332 if (dst_first_rc == rc_stack) {
duke@0 1333 // gpr -> mem
duke@0 1334 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1335 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1336 // 64-bit
duke@0 1337 int offset = ra_->reg2offset(dst_first);
duke@0 1338 if (cbuf) {
duke@0 1339 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1340 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1341 } else {
duke@0 1342 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1343 }
duke@0 1344 emit_opcode(*cbuf, 0x89);
duke@0 1345 encode_RegMem(*cbuf,
duke@0 1346 Matcher::_regEncode[src_first],
duke@0 1347 RSP_enc, 0x4, 0, offset,
duke@0 1348 false);
duke@0 1349 #ifndef PRODUCT
duke@0 1350 } else if (!do_size) {
duke@0 1351 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1352 offset,
duke@0 1353 Matcher::regName[src_first]);
duke@0 1354 #endif
duke@0 1355 }
duke@0 1356 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
duke@0 1357 } else {
duke@0 1358 // 32-bit
duke@0 1359 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1360 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1361 int offset = ra_->reg2offset(dst_first);
duke@0 1362 if (cbuf) {
duke@0 1363 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1364 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1365 }
duke@0 1366 emit_opcode(*cbuf, 0x89);
duke@0 1367 encode_RegMem(*cbuf,
duke@0 1368 Matcher::_regEncode[src_first],
duke@0 1369 RSP_enc, 0x4, 0, offset,
duke@0 1370 false);
duke@0 1371 #ifndef PRODUCT
duke@0 1372 } else if (!do_size) {
duke@0 1373 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1374 offset,
duke@0 1375 Matcher::regName[src_first]);
duke@0 1376 #endif
duke@0 1377 }
duke@0 1378 return
duke@0 1379 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1380 ((Matcher::_regEncode[src_first] < 8)
duke@0 1381 ? 3
duke@0 1382 : 4); // REX
duke@0 1383 }
duke@0 1384 } else if (dst_first_rc == rc_int) {
duke@0 1385 // gpr -> gpr
duke@0 1386 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1387 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1388 // 64-bit
duke@0 1389 if (cbuf) {
duke@0 1390 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1391 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1392 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1393 } else {
duke@0 1394 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1395 }
duke@0 1396 } else {
duke@0 1397 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1398 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1399 } else {
duke@0 1400 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1401 }
duke@0 1402 }
duke@0 1403 emit_opcode(*cbuf, 0x8B);
duke@0 1404 emit_rm(*cbuf, 0x3,
duke@0 1405 Matcher::_regEncode[dst_first] & 7,
duke@0 1406 Matcher::_regEncode[src_first] & 7);
duke@0 1407 #ifndef PRODUCT
duke@0 1408 } else if (!do_size) {
duke@0 1409 st->print("movq %s, %s\t# spill",
duke@0 1410 Matcher::regName[dst_first],
duke@0 1411 Matcher::regName[src_first]);
duke@0 1412 #endif
duke@0 1413 }
duke@0 1414 return 3; // REX
duke@0 1415 } else {
duke@0 1416 // 32-bit
duke@0 1417 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1418 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1419 if (cbuf) {
duke@0 1420 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1421 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1422 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1423 }
duke@0 1424 } else {
duke@0 1425 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1426 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1427 } else {
duke@0 1428 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1429 }
duke@0 1430 }
duke@0 1431 emit_opcode(*cbuf, 0x8B);
duke@0 1432 emit_rm(*cbuf, 0x3,
duke@0 1433 Matcher::_regEncode[dst_first] & 7,
duke@0 1434 Matcher::_regEncode[src_first] & 7);
duke@0 1435 #ifndef PRODUCT
duke@0 1436 } else if (!do_size) {
duke@0 1437 st->print("movl %s, %s\t# spill",
duke@0 1438 Matcher::regName[dst_first],
duke@0 1439 Matcher::regName[src_first]);
duke@0 1440 #endif
duke@0 1441 }
duke@0 1442 return
duke@0 1443 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1444 ? 2
duke@0 1445 : 3; // REX
duke@0 1446 }
duke@0 1447 } else if (dst_first_rc == rc_float) {
duke@0 1448 // gpr -> xmm
duke@0 1449 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1450 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1451 // 64-bit
duke@0 1452 if (cbuf) {
duke@0 1453 emit_opcode(*cbuf, 0x66);
duke@0 1454 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1455 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1456 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1457 } else {
duke@0 1458 emit_opcode(*cbuf, Assembler::REX_WB);
duke@0 1459 }
duke@0 1460 } else {
duke@0 1461 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1462 emit_opcode(*cbuf, Assembler::REX_WR);
duke@0 1463 } else {
duke@0 1464 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1465 }
duke@0 1466 }
duke@0 1467 emit_opcode(*cbuf, 0x0F);
duke@0 1468 emit_opcode(*cbuf, 0x6E);
duke@0 1469 emit_rm(*cbuf, 0x3,
duke@0 1470 Matcher::_regEncode[dst_first] & 7,
duke@0 1471 Matcher::_regEncode[src_first] & 7);
duke@0 1472 #ifndef PRODUCT
duke@0 1473 } else if (!do_size) {
duke@0 1474 st->print("movdq %s, %s\t# spill",
duke@0 1475 Matcher::regName[dst_first],
duke@0 1476 Matcher::regName[src_first]);
duke@0 1477 #endif
duke@0 1478 }
duke@0 1479 return 5; // REX
duke@0 1480 } else {
duke@0 1481 // 32-bit
duke@0 1482 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1483 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1484 if (cbuf) {
duke@0 1485 emit_opcode(*cbuf, 0x66);
duke@0 1486 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1487 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1488 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1489 }
duke@0 1490 } else {
duke@0 1491 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1492 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1493 } else {
duke@0 1494 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1495 }
duke@0 1496 }
duke@0 1497 emit_opcode(*cbuf, 0x0F);
duke@0 1498 emit_opcode(*cbuf, 0x6E);
duke@0 1499 emit_rm(*cbuf, 0x3,
duke@0 1500 Matcher::_regEncode[dst_first] & 7,
duke@0 1501 Matcher::_regEncode[src_first] & 7);
duke@0 1502 #ifndef PRODUCT
duke@0 1503 } else if (!do_size) {
duke@0 1504 st->print("movdl %s, %s\t# spill",
duke@0 1505 Matcher::regName[dst_first],
duke@0 1506 Matcher::regName[src_first]);
duke@0 1507 #endif
duke@0 1508 }
duke@0 1509 return
duke@0 1510 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1511 ? 4
duke@0 1512 : 5; // REX
duke@0 1513 }
duke@0 1514 }
duke@0 1515 } else if (src_first_rc == rc_float) {
duke@0 1516 // xmm ->
duke@0 1517 if (dst_first_rc == rc_stack) {
duke@0 1518 // xmm -> mem
duke@0 1519 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1520 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1521 // 64-bit
duke@0 1522 int offset = ra_->reg2offset(dst_first);
duke@0 1523 if (cbuf) {
duke@0 1524 emit_opcode(*cbuf, 0xF2);
duke@0 1525 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1526 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1527 }
duke@0 1528 emit_opcode(*cbuf, 0x0F);
duke@0 1529 emit_opcode(*cbuf, 0x11);
duke@0 1530 encode_RegMem(*cbuf,
duke@0 1531 Matcher::_regEncode[src_first],
duke@0 1532 RSP_enc, 0x4, 0, offset,
duke@0 1533 false);
duke@0 1534 #ifndef PRODUCT
duke@0 1535 } else if (!do_size) {
duke@0 1536 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1537 offset,
duke@0 1538 Matcher::regName[src_first]);
duke@0 1539 #endif
duke@0 1540 }
duke@0 1541 return
duke@0 1542 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1543 ((Matcher::_regEncode[src_first] < 8)
duke@0 1544 ? 5
duke@0 1545 : 6); // REX
duke@0 1546 } else {
duke@0 1547 // 32-bit
duke@0 1548 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1549 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1550 int offset = ra_->reg2offset(dst_first);
duke@0 1551 if (cbuf) {
duke@0 1552 emit_opcode(*cbuf, 0xF3);
duke@0 1553 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1554 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1555 }
duke@0 1556 emit_opcode(*cbuf, 0x0F);
duke@0 1557 emit_opcode(*cbuf, 0x11);
duke@0 1558 encode_RegMem(*cbuf,
duke@0 1559 Matcher::_regEncode[src_first],
duke@0 1560 RSP_enc, 0x4, 0, offset,
duke@0 1561 false);
duke@0 1562 #ifndef PRODUCT
duke@0 1563 } else if (!do_size) {
duke@0 1564 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1565 offset,
duke@0 1566 Matcher::regName[src_first]);
duke@0 1567 #endif
duke@0 1568 }
duke@0 1569 return
duke@0 1570 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
duke@0 1571 ((Matcher::_regEncode[src_first] < 8)
duke@0 1572 ? 5
duke@0 1573 : 6); // REX
duke@0 1574 }
duke@0 1575 } else if (dst_first_rc == rc_int) {
duke@0 1576 // xmm -> gpr
duke@0 1577 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1578 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1579 // 64-bit
duke@0 1580 if (cbuf) {
duke@0 1581 emit_opcode(*cbuf, 0x66);
duke@0 1582 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1583 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1584 emit_opcode(*cbuf, Assembler::REX_W);
duke@0 1585 } else {
duke@0 1586 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
duke@0 1587 }
duke@0 1588 } else {
duke@0 1589 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1590 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
duke@0 1591 } else {
duke@0 1592 emit_opcode(*cbuf, Assembler::REX_WRB);
duke@0 1593 }
duke@0 1594 }
duke@0 1595 emit_opcode(*cbuf, 0x0F);
duke@0 1596 emit_opcode(*cbuf, 0x7E);
duke@0 1597 emit_rm(*cbuf, 0x3,
never@1650 1598 Matcher::_regEncode[src_first] & 7,
never@1650 1599 Matcher::_regEncode[dst_first] & 7);
duke@0 1600 #ifndef PRODUCT
duke@0 1601 } else if (!do_size) {
duke@0 1602 st->print("movdq %s, %s\t# spill",
duke@0 1603 Matcher::regName[dst_first],
duke@0 1604 Matcher::regName[src_first]);
duke@0 1605 #endif
duke@0 1606 }
duke@0 1607 return 5; // REX
duke@0 1608 } else {
duke@0 1609 // 32-bit
duke@0 1610 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1611 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1612 if (cbuf) {
duke@0 1613 emit_opcode(*cbuf, 0x66);
duke@0 1614 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1615 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1616 emit_opcode(*cbuf, Assembler::REX_R); // attention!
duke@0 1617 }
duke@0 1618 } else {
duke@0 1619 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1620 emit_opcode(*cbuf, Assembler::REX_B); // attention!
duke@0 1621 } else {
duke@0 1622 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1623 }
duke@0 1624 }
duke@0 1625 emit_opcode(*cbuf, 0x0F);
duke@0 1626 emit_opcode(*cbuf, 0x7E);
duke@0 1627 emit_rm(*cbuf, 0x3,
never@1650 1628 Matcher::_regEncode[src_first] & 7,
never@1650 1629 Matcher::_regEncode[dst_first] & 7);
duke@0 1630 #ifndef PRODUCT
duke@0 1631 } else if (!do_size) {
duke@0 1632 st->print("movdl %s, %s\t# spill",
duke@0 1633 Matcher::regName[dst_first],
duke@0 1634 Matcher::regName[src_first]);
duke@0 1635 #endif
duke@0 1636 }
duke@0 1637 return
duke@0 1638 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1639 ? 4
duke@0 1640 : 5; // REX
duke@0 1641 }
duke@0 1642 } else if (dst_first_rc == rc_float) {
duke@0 1643 // xmm -> xmm
duke@0 1644 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1645 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1646 // 64-bit
duke@0 1647 if (cbuf) {
duke@0 1648 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 1649 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1650 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1651 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1652 }
duke@0 1653 } else {
duke@0 1654 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1655 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1656 } else {
duke@0 1657 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1658 }
duke@0 1659 }
duke@0 1660 emit_opcode(*cbuf, 0x0F);
duke@0 1661 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1662 emit_rm(*cbuf, 0x3,
duke@0 1663 Matcher::_regEncode[dst_first] & 7,
duke@0 1664 Matcher::_regEncode[src_first] & 7);
duke@0 1665 #ifndef PRODUCT
duke@0 1666 } else if (!do_size) {
duke@0 1667 st->print("%s %s, %s\t# spill",
duke@0 1668 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1669 Matcher::regName[dst_first],
duke@0 1670 Matcher::regName[src_first]);
duke@0 1671 #endif
duke@0 1672 }
duke@0 1673 return
duke@0 1674 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1675 ? 4
duke@0 1676 : 5; // REX
duke@0 1677 } else {
duke@0 1678 // 32-bit
duke@0 1679 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1680 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1681 if (cbuf) {
duke@0 1682 if (!UseXmmRegToRegMoveAll)
duke@0 1683 emit_opcode(*cbuf, 0xF3);
duke@0 1684 if (Matcher::_regEncode[dst_first] < 8) {
duke@0 1685 if (Matcher::_regEncode[src_first] >= 8) {
duke@0 1686 emit_opcode(*cbuf, Assembler::REX_B);
duke@0 1687 }
duke@0 1688 } else {
duke@0 1689 if (Matcher::_regEncode[src_first] < 8) {
duke@0 1690 emit_opcode(*cbuf, Assembler::REX_R);
duke@0 1691 } else {
duke@0 1692 emit_opcode(*cbuf, Assembler::REX_RB);
duke@0 1693 }
duke@0 1694 }
duke@0 1695 emit_opcode(*cbuf, 0x0F);
duke@0 1696 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 1697 emit_rm(*cbuf, 0x3,
duke@0 1698 Matcher::_regEncode[dst_first] & 7,
duke@0 1699 Matcher::_regEncode[src_first] & 7);
duke@0 1700 #ifndef PRODUCT
duke@0 1701 } else if (!do_size) {
duke@0 1702 st->print("%s %s, %s\t# spill",
duke@0 1703 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1704 Matcher::regName[dst_first],
duke@0 1705 Matcher::regName[src_first]);
duke@0 1706 #endif
duke@0 1707 }
duke@0 1708 return
duke@0 1709 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
duke@0 1710 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 1711 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
duke@0 1712 }
duke@0 1713 }
duke@0 1714 }
duke@0 1715
duke@0 1716 assert(0," foo ");
duke@0 1717 Unimplemented();
duke@0 1718
duke@0 1719 return 0;
duke@0 1720 }
duke@0 1721
duke@0 1722 #ifndef PRODUCT
duke@0 1723 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
duke@0 1724 {
duke@0 1725 implementation(NULL, ra_, false, st);
duke@0 1726 }
duke@0 1727 #endif
duke@0 1728
duke@0 1729 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
duke@0 1730 {
duke@0 1731 implementation(&cbuf, ra_, false, NULL);
duke@0 1732 }
duke@0 1733
duke@0 1734 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
duke@0 1735 {
duke@0 1736 return implementation(NULL, ra_, true, NULL);
duke@0 1737 }
duke@0 1738
duke@0 1739 //=============================================================================
duke@0 1740 #ifndef PRODUCT
duke@0 1741 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
duke@0 1742 {
duke@0 1743 st->print("nop \t# %d bytes pad for loops and calls", _count);
duke@0 1744 }
duke@0 1745 #endif
duke@0 1746
duke@0 1747 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
duke@0 1748 {
duke@0 1749 MacroAssembler _masm(&cbuf);
duke@0 1750 __ nop(_count);
duke@0 1751 }
duke@0 1752
duke@0 1753 uint MachNopNode::size(PhaseRegAlloc*) const
duke@0 1754 {
duke@0 1755 return _count;
duke@0 1756 }
duke@0 1757
duke@0 1758
duke@0 1759 //=============================================================================
duke@0 1760 #ifndef PRODUCT
duke@0 1761 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1762 {
duke@0 1763 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1764 int reg = ra_->get_reg_first(this);
duke@0 1765 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1766 Matcher::regName[reg], offset);
duke@0 1767 }
duke@0 1768 #endif
duke@0 1769
duke@0 1770 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1771 {
duke@0 1772 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1773 int reg = ra_->get_encode(this);
duke@0 1774 if (offset >= 0x80) {
duke@0 1775 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1776 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1777 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1778 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1779 emit_d32(cbuf, offset);
duke@0 1780 } else {
duke@0 1781 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1782 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1783 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1784 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1785 emit_d8(cbuf, offset);
duke@0 1786 }
duke@0 1787 }
duke@0 1788
duke@0 1789 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1790 {
duke@0 1791 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1792 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1793 }
duke@0 1794
duke@0 1795 //=============================================================================
duke@0 1796
duke@0 1797 // emit call stub, compiled java to interpreter
duke@0 1798 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1799 {
duke@0 1800 // Stub is fixed up when the corresponding call is converted from
duke@0 1801 // calling compiled code to calling interpreted code.
duke@0 1802 // movq rbx, 0
duke@0 1803 // jmp -5 # to self
duke@0 1804
twisti@1668 1805 address mark = cbuf.insts_mark(); // get mark within main instrs section
twisti@1668 1806
twisti@1668 1807 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1808 // That's why we must use the macroassembler to generate a stub.
duke@0 1809 MacroAssembler _masm(&cbuf);
duke@0 1810
duke@0 1811 address base =
duke@0 1812 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1813 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1814 // static stub relocation stores the instruction address of the call
duke@0 1815 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
duke@0 1816 // static stub relocation also tags the methodOop in the code-stream.
duke@0 1817 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
never@304 1818 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1819 __ jump(RuntimeAddress(__ pc()));
duke@0 1820
twisti@1668 1821 // Update current stubs pointer and restore insts_end.
duke@0 1822 __ end_a_stub();
duke@0 1823 }
duke@0 1824
duke@0 1825 // size of call stub, compiled java to interpretor
duke@0 1826 uint size_java_to_interp()
duke@0 1827 {
duke@0 1828 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1829 }
duke@0 1830
duke@0 1831 // relocation entries for call stub, compiled java to interpretor
duke@0 1832 uint reloc_java_to_interp()
duke@0 1833 {
duke@0 1834 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1835 }
duke@0 1836
duke@0 1837 //=============================================================================
duke@0 1838 #ifndef PRODUCT
duke@0 1839 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1840 {
coleenp@113 1841 if (UseCompressedOops) {
kvn@1491 1842 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
kvn@642 1843 if (Universe::narrow_oop_shift() != 0) {
kvn@1491 1844 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1");
kvn@1491 1845 }
kvn@1491 1846 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1847 } else {
kvn@1491 1848 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1849 "# Inline cache check");
coleenp@113 1850 }
duke@0 1851 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1852 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1853 }
duke@0 1854 #endif
duke@0 1855
duke@0 1856 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1857 {
duke@0 1858 MacroAssembler masm(&cbuf);
twisti@1668 1859 uint insts_size = cbuf.insts_size();
coleenp@113 1860 if (UseCompressedOops) {
coleenp@113 1861 masm.load_klass(rscratch1, j_rarg0);
never@304 1862 masm.cmpptr(rax, rscratch1);
coleenp@113 1863 } else {
never@304 1864 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1865 }
duke@0 1866
duke@0 1867 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1868
duke@0 1869 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1870 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1871 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1872 if (OptoBreakpoint) {
duke@0 1873 // Leave space for int3
kvn@1491 1874 nops_cnt -= 1;
duke@0 1875 }
kvn@1491 1876 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1877 if (nops_cnt > 0)
kvn@1491 1878 masm.nop(nops_cnt);
duke@0 1879 }
duke@0 1880
duke@0 1881 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1882 {
kvn@1491 1883 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1884 // the hard way
duke@0 1885 }
duke@0 1886
duke@0 1887
duke@0 1888 //=============================================================================
duke@0 1889 uint size_exception_handler()
duke@0 1890 {
duke@0 1891 // NativeCall instruction size is the same as NativeJump.
duke@0 1892 // Note that this value is also credited (in output.cpp) to
duke@0 1893 // the size of the code section.
duke@0 1894 return NativeJump::instruction_size;
duke@0 1895 }
duke@0 1896
duke@0 1897 // Emit exception handler code.
duke@0 1898 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1899 {
duke@0 1900
twisti@1668 1901 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1902 // That's why we must use the macroassembler to generate a handler.
duke@0 1903 MacroAssembler _masm(&cbuf);
duke@0 1904 address base =
duke@0 1905 __ start_a_stub(size_exception_handler());
duke@0 1906 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1907 int offset = __ offset();
twisti@1668 1908 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
duke@0 1909 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1910 __ end_a_stub();
duke@0 1911 return offset;
duke@0 1912 }
duke@0 1913
duke@0 1914 uint size_deopt_handler()
duke@0 1915 {
duke@0 1916 // three 5 byte instructions
duke@0 1917 return 15;
duke@0 1918 }
duke@0 1919
duke@0 1920 // Emit deopt handler code.
duke@0 1921 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1922 {
duke@0 1923
twisti@1668 1924 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1925 // That's why we must use the macroassembler to generate a handler.
duke@0 1926 MacroAssembler _masm(&cbuf);
duke@0 1927 address base =
duke@0 1928 __ start_a_stub(size_deopt_handler());
duke@0 1929 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1930 int offset = __ offset();
duke@0 1931 address the_pc = (address) __ pc();
duke@0 1932 Label next;
duke@0 1933 // push a "the_pc" on the stack without destroying any registers
duke@0 1934 // as they all may be live.
duke@0 1935
duke@0 1936 // push address of "next"
duke@0 1937 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1938 __ bind(next);
duke@0 1939 // adjust it so it matches "the_pc"
never@304 1940 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1941 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1942 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1943 __ end_a_stub();
duke@0 1944 return offset;
duke@0 1945 }
duke@0 1946
duke@0 1947
twisti@775 1948 const bool Matcher::match_rule_supported(int opcode) {
twisti@775 1949 if (!has_match_rule(opcode))
twisti@775 1950 return false;
twisti@775 1951
twisti@775 1952 return true; // Per default match rules are supported.
twisti@775 1953 }
twisti@775 1954
duke@0 1955 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1956 {
duke@0 1957 return regnum - 32; // The FP registers are in the second chunk
duke@0 1958 }
duke@0 1959
duke@0 1960 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1961 const bool Matcher::convL2FSupported(void) {
duke@0 1962 return true;
duke@0 1963 }
duke@0 1964
duke@0 1965 // Vector width in bytes
duke@0 1966 const uint Matcher::vector_width_in_bytes(void) {
duke@0 1967 return 8;
duke@0 1968 }
duke@0 1969
duke@0 1970 // Vector ideal reg
duke@0 1971 const uint Matcher::vector_ideal_reg(void) {
duke@0 1972 return Op_RegD;
duke@0 1973 }
duke@0 1974
duke@0 1975 // Is this branch offset short enough that a short branch can be used?
duke@0 1976 //
duke@0 1977 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1978 // this method should return false for offset 0.
kvn@2614 1979 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1980 // The passed offset is relative to address of the branch.
kvn@2614 1981 // On 86 a branch displacement is calculated relative to address
kvn@2614 1982 // of a next instruction.
kvn@2614 1983 offset -= br_size;
kvn@2614 1984
never@415 1985 // the short version of jmpConUCF2 contains multiple branches,
never@415 1986 // making the reach slightly less
never@415 1987 if (rule == jmpConUCF2_rule)
never@415 1988 return (-126 <= offset && offset <= 125);
never@415 1989 return (-128 <= offset && offset <= 127);
duke@0 1990 }
duke@0 1991
duke@0 1992 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1993 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1994 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1995
duke@0 1996 // Probably always true, even if a temp register is required.
duke@0 1997 return true;
duke@0 1998 }
duke@0 1999
duke@0 2000 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 2001 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 2002
duke@0 2003 // Threshold size for cleararray.
duke@0 2004 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 2005
kvn@2808 2006 // No additional cost for CMOVL.
kvn@2808 2007 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 2008
kvn@2808 2009 // No CMOVF/CMOVD with SSE2
kvn@2808 2010 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 2011
duke@0 2012 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 2013 // to be subsumed into complex addressing expressions or compute them
duke@0 2014 // into registers? True for Intel but false for most RISCs
duke@0 2015 const bool Matcher::clone_shift_expressions = true;
duke@0 2016
roland@2248 2017 // Do we need to mask the count passed to shift instructions or does
roland@2248 2018 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 2019 const bool Matcher::need_masked_shift_count = false;
roland@2248 2020
kvn@1495 2021 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 2022 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 2023 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 2024 }
kvn@1495 2025
duke@0 2026 // Is it better to copy float constants, or load them directly from
duke@0 2027 // memory? Intel can load a float constant from a direct address,
duke@0 2028 // requiring no extra registers. Most RISCs will have to materialize
duke@0 2029 // an address into a register first, so they would do better to copy
duke@0 2030 // the constant from stack.
duke@0 2031 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 2032
duke@0 2033 // If CPU can load and store mis-aligned doubles directly then no
duke@0 2034 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 2035 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 2036 // C code as the Java calling convention forces doubles to be aligned.
duke@0 2037 const bool Matcher::misaligned_doubles_ok = true;
duke@0 2038
duke@0 2039 // No-op on amd64
duke@0 2040 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 2041
duke@0 2042 // Advertise here if the CPU requires explicit rounding operations to
duke@0 2043 // implement the UseStrictFP mode.
duke@0 2044 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 2045
kvn@1274 2046 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 2047 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 2048 bool Matcher::float_in_double() { return false; }
kvn@1274 2049
duke@0 2050 // Do ints take an entire long register or just half?
duke@0 2051 const bool Matcher::int_in_long = true;
duke@0 2052
duke@0 2053 // Return whether or not this register is ever used as an argument.
duke@0 2054 // This function is used on startup to build the trampoline stubs in
duke@0 2055 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 2056 // call in the trampoline, and arguments in those registers not be
duke@0 2057 // available to the callee.
duke@0 2058 bool Matcher::can_be_java_arg(int reg)
duke@0 2059 {
duke@0 2060 return
duke@0 2061 reg == RDI_num || reg == RDI_H_num ||
duke@0 2062 reg == RSI_num || reg == RSI_H_num ||
duke@0 2063 reg == RDX_num || reg == RDX_H_num ||
duke@0 2064 reg == RCX_num || reg == RCX_H_num ||
duke@0 2065 reg == R8_num || reg == R8_H_num ||
duke@0 2066 reg == R9_num || reg == R9_H_num ||
coleenp@113 2067 reg == R12_num || reg == R12_H_num ||
duke@0 2068 reg == XMM0_num || reg == XMM0_H_num ||
duke@0 2069 reg == XMM1_num || reg == XMM1_H_num ||
duke@0 2070 reg == XMM2_num || reg == XMM2_H_num ||
duke@0 2071 reg == XMM3_num || reg == XMM3_H_num ||
duke@0 2072 reg == XMM4_num || reg == XMM4_H_num ||
duke@0 2073 reg == XMM5_num || reg == XMM5_H_num ||
duke@0 2074 reg == XMM6_num || reg == XMM6_H_num ||
duke@0 2075 reg == XMM7_num || reg == XMM7_H_num;
duke@0 2076 }
duke@0 2077
duke@0 2078 bool Matcher::is_spillable_arg(int reg)
duke@0 2079 {
duke@0 2080 return can_be_java_arg(reg);
duke@0 2081 }
duke@0 2082
kvn@1834 2083 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 2084 // In 64 bit mode a code which use multiply when
kvn@1834 2085 // devisor is constant is faster than hardware
kvn@1834 2086 // DIV instruction (it uses MulHiL).
kvn@1834 2087 return false;
kvn@1834 2088 }
kvn@1834 2089
duke@0 2090 // Register for DIVI projection of divmodI
duke@0 2091 RegMask Matcher::divI_proj_mask() {
roland@2882 2092 return INT_RAX_REG_mask();
duke@0 2093 }
duke@0 2094
duke@0 2095 // Register for MODI projection of divmodI
duke@0 2096 RegMask Matcher::modI_proj_mask() {
roland@2882 2097 return INT_RDX_REG_mask();
duke@0 2098 }
duke@0 2099
duke@0 2100 // Register for DIVL projection of divmodL
duke@0 2101 RegMask Matcher::divL_proj_mask() {
roland@2882 2102 return LONG_RAX_REG_mask();
duke@0 2103 }
duke@0 2104
duke@0 2105 // Register for MODL projection of divmodL
duke@0 2106 RegMask Matcher::modL_proj_mask() {
roland@2882 2107 return LONG_RDX_REG_mask();
duke@0 2108 }
duke@0 2109
twisti@1137 2110 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
roland@2882 2111 return PTR_RBP_REG_mask();
twisti@1137 2112 }
twisti@1137 2113
coleenp@113 2114 static Address build_address(int b, int i, int s, int d) {
coleenp@113 2115 Register index = as_Register(i);
coleenp@113 2116 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 2117 if (index == rsp) {
coleenp@113 2118 index = noreg;
coleenp@113 2119 scale = Address::no_scale;
coleenp@113 2120 }
coleenp@113 2121 Address addr(as_Register(b), index, scale, d);
coleenp@113 2122 return addr;
coleenp@113 2123 }
coleenp@113 2124
duke@0 2125 %}
duke@0 2126
duke@0 2127 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 2128 // This block specifies the encoding classes used by the compiler to
duke@0 2129 // output byte streams. Encoding classes are parameterized macros
duke@0 2130 // used by Machine Instruction Nodes in order to generate the bit
duke@0 2131 // encoding of the instruction. Operands specify their base encoding
duke@0 2132 // interface with the interface keyword. There are currently
duke@0 2133 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 2134 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 2135 // which returns its register number when queried. CONST_INTER causes
duke@0 2136 // an operand to generate a function which returns the value of the
duke@0 2137 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 2138 // four functions which return the Base Register, the Index Register,
duke@0 2139 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 2140 // COND_INTER causes an operand to generate six functions which return
duke@0 2141 // the encoding code (ie - encoding bits for the instruction)
duke@0 2142 // associated with each basic boolean condition for a conditional
duke@0 2143 // instruction.
duke@0 2144 //
duke@0 2145 // Instructions specify two basic values for encoding. Again, a
duke@0 2146 // function is available to check if the constant displacement is an
duke@0 2147 // oop. They use the ins_encode keyword to specify their encoding
duke@0 2148 // classes (which must be a sequence of enc_class names, and their
duke@0 2149 // parameters, specified in the encoding block), and they use the
duke@0 2150 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 2151 // tertiary opcode. Only the opcode sections which a particular
duke@0 2152 // instruction needs for encoding need to be specified.
duke@0 2153 encode %{
duke@0 2154 // Build emit functions for each basic byte or larger field in the
duke@0 2155 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 2156 // from C++ code in the enc_class source block. Emit functions will
duke@0 2157 // live in the main source block for now. In future, we can
duke@0 2158 // generalize this by adding a syntax that specifies the sizes of
duke@0 2159 // fields in an order, so that the adlc can build the emit functions
duke@0 2160 // automagically
duke@0 2161
duke@0 2162 // Emit primary opcode
duke@0 2163 enc_class OpcP
duke@0 2164 %{
duke@0 2165 emit_opcode(cbuf, $primary);
duke@0 2166 %}
duke@0 2167
duke@0 2168 // Emit secondary opcode
duke@0 2169 enc_class OpcS
duke@0 2170 %{
duke@0 2171 emit_opcode(cbuf, $secondary);
duke@0 2172 %}
duke@0 2173
duke@0 2174 // Emit tertiary opcode
duke@0 2175 enc_class OpcT
duke@0 2176 %{
duke@0 2177 emit_opcode(cbuf, $tertiary);
duke@0 2178 %}
duke@0 2179
duke@0 2180 // Emit opcode directly
duke@0 2181 enc_class Opcode(immI d8)
duke@0 2182 %{
duke@0 2183 emit_opcode(cbuf, $d8$$constant);
duke@0 2184 %}
duke@0 2185
duke@0 2186 // Emit size prefix
duke@0 2187 enc_class SizePrefix
duke@0 2188 %{
duke@0 2189 emit_opcode(cbuf, 0x66);
duke@0 2190 %}
duke@0 2191
duke@0 2192 enc_class reg(rRegI reg)
duke@0 2193 %{
duke@0 2194 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 2195 %}
duke@0 2196
duke@0 2197 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 2198 %{
duke@0 2199 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2200 %}
duke@0 2201
duke@0 2202 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 2203 %{
duke@0 2204 emit_opcode(cbuf, $opcode$$constant);
duke@0 2205 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2206 %}
duke@0 2207
never@2545 2208 enc_class cmpfp_fixup() %{
never@2545 2209 MacroAssembler _masm(&cbuf);
never@2545 2210 emit_cmpfp_fixup(_masm);
duke@0 2211 %}
duke@0 2212
duke@0 2213 enc_class cmpfp3(rRegI dst)
duke@0 2214 %{
duke@0 2215 int dstenc = $dst$$reg;
duke@0 2216
duke@0 2217 // movl $dst, -1
duke@0 2218 if (dstenc >= 8) {
duke@0 2219 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2220 }
duke@0 2221 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2222 emit_d32(cbuf, -1);
duke@0 2223
duke@0 2224 // jp,s done
duke@0 2225 emit_opcode(cbuf, 0x7A);
duke@0 2226 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
duke@0 2227
duke@0 2228 // jb,s done
duke@0 2229 emit_opcode(cbuf, 0x72);
duke@0 2230 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2231
duke@0 2232 // setne $dst
duke@0 2233 if (dstenc >= 4) {
duke@0 2234 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2235 }
duke@0 2236 emit_opcode(cbuf, 0x0F);
duke@0 2237 emit_opcode(cbuf, 0x95);
duke@0 2238 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2239
duke@0 2240 // movzbl $dst, $dst
duke@0 2241 if (dstenc >= 4) {
duke@0 2242 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2243 }
duke@0 2244 emit_opcode(cbuf, 0x0F);
duke@0 2245 emit_opcode(cbuf, 0xB6);
duke@0 2246 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2247 %}
duke@0 2248
duke@0 2249 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 2250 %{
duke@0 2251 // Full implementation of Java idiv and irem; checks for
duke@0 2252 // special case as described in JVM spec., p.243 & p.271.
duke@0 2253 //
duke@0 2254 // normal case special case
duke@0 2255 //
duke@0 2256 // input : rax: dividend min_int
duke@0 2257 // reg: divisor -1
duke@0 2258 //
duke@0 2259 // output: rax: quotient (= rax idiv reg) min_int
duke@0 2260 // rdx: remainder (= rax irem reg) 0
duke@0 2261 //
duke@0 2262 // Code sequnce:
duke@0 2263 //
duke@0 2264 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 2265 // 5: 75 07/08 jne e <normal>
duke@0 2266 // 7: 33 d2 xor %edx,%edx
duke@0 2267 // [div >= 8 -> offset + 1]
duke@0 2268 // [REX_B]
duke@0 2269 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2270 // c: 74 03/04 je 11 <done>
duke@0 2271 // 000000000000000e <normal>:
duke@0 2272 // e: 99 cltd
duke@0 2273 // [div >= 8 -> offset + 1]
duke@0 2274 // [REX_B]
duke@0 2275 // f: f7 f9 idiv $div
duke@0 2276 // 0000000000000011 <done>:
duke@0 2277
duke@0 2278 // cmp $0x80000000,%eax
duke@0 2279 emit_opcode(cbuf, 0x3d);
duke@0 2280 emit_d8(cbuf, 0x00);
duke@0 2281 emit_d8(cbuf, 0x00);
duke@0 2282 emit_d8(cbuf, 0x00);
duke@0 2283 emit_d8(cbuf, 0x80);
duke@0 2284
duke@0 2285 // jne e <normal>
duke@0 2286 emit_opcode(cbuf, 0x75);
duke@0 2287 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 2288
duke@0 2289 // xor %edx,%edx
duke@0 2290 emit_opcode(cbuf, 0x33);
duke@0 2291 emit_d8(cbuf, 0xD2);
duke@0 2292
duke@0 2293 // cmp $0xffffffffffffffff,%ecx
duke@0 2294 if ($div$$reg >= 8) {
duke@0 2295 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2296 }
duke@0 2297 emit_opcode(cbuf, 0x83);
duke@0 2298 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2299 emit_d8(cbuf, 0xFF);
duke@0 2300
duke@0 2301 // je 11 <done>
duke@0 2302 emit_opcode(cbuf, 0x74);
duke@0 2303 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 2304
duke@0 2305 // <normal>
duke@0 2306 // cltd
duke@0 2307 emit_opcode(cbuf, 0x99);
duke@0 2308
duke@0 2309 // idivl (note: must be emitted by the user of this rule)
duke@0 2310 // <done>
duke@0 2311 %}
duke@0 2312
duke@0 2313 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 2314 %{
duke@0 2315 // Full implementation of Java ldiv and lrem; checks for
duke@0 2316 // special case as described in JVM spec., p.243 & p.271.
duke@0 2317 //
duke@0 2318 // normal case special case
duke@0 2319 //
duke@0 2320 // input : rax: dividend min_long
duke@0 2321 // reg: divisor -1
duke@0 2322 //
duke@0 2323 // output: rax: quotient (= rax idiv reg) min_long
duke@0 2324 // rdx: remainder (= rax irem reg) 0
duke@0 2325 //
duke@0 2326 // Code sequnce:
duke@0 2327 //
duke@0 2328 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 2329 // 7: 00 00 80
duke@0 2330 // a: 48 39 d0 cmp %rdx,%rax
duke@0 2331 // d: 75 08 jne 17 <normal>
duke@0 2332 // f: 33 d2 xor %edx,%edx
duke@0 2333 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 2334 // 15: 74 05 je 1c <done>
duke@0 2335 // 0000000000000017 <normal>:
duke@0 2336 // 17: 48 99 cqto
duke@0 2337 // 19: 48 f7 f9 idiv $div
duke@0 2338 // 000000000000001c <done>:
duke@0 2339
duke@0 2340 // mov $0x8000000000000000,%rdx
duke@0 2341 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2342 emit_opcode(cbuf, 0xBA);
duke@0 2343 emit_d8(cbuf, 0x00);
duke@0 2344 emit_d8(cbuf, 0x00);
duke@0 2345 emit_d8(cbuf, 0x00);
duke@0 2346 emit_d8(cbuf, 0x00);
duke@0 2347 emit_d8(cbuf, 0x00);
duke@0 2348 emit_d8(cbuf, 0x00);
duke@0 2349 emit_d8(cbuf, 0x00);
duke@0 2350 emit_d8(cbuf, 0x80);
duke@0 2351
duke@0 2352 // cmp %rdx,%rax
duke@0 2353 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2354 emit_opcode(cbuf, 0x39);
duke@0 2355 emit_d8(cbuf, 0xD0);
duke@0 2356
duke@0 2357 // jne 17 <normal>
duke@0 2358 emit_opcode(cbuf, 0x75);
duke@0 2359 emit_d8(cbuf, 0x08);
duke@0 2360
duke@0 2361 // xor %edx,%edx
duke@0 2362 emit_opcode(cbuf, 0x33);
duke@0 2363 emit_d8(cbuf, 0xD2);
duke@0 2364
duke@0 2365 // cmp $0xffffffffffffffff,$div
duke@0 2366 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 2367 emit_opcode(cbuf, 0x83);
duke@0 2368 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 2369 emit_d8(cbuf, 0xFF);
duke@0 2370
duke@0 2371 // je 1e <done>
duke@0 2372 emit_opcode(cbuf, 0x74);
duke@0 2373 emit_d8(cbuf, 0x05);
duke@0 2374
duke@0 2375 // <normal>
duke@0 2376 // cqto
duke@0 2377 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2378 emit_opcode(cbuf, 0x99);
duke@0 2379
duke@0 2380 // idivq (note: must be emitted by the user of this rule)
duke@0 2381 // <done>
duke@0 2382 %}
duke@0 2383
duke@0 2384 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 2385 enc_class OpcSE(immI imm)
duke@0 2386 %{
duke@0 2387 // Emit primary opcode and set sign-extend bit
duke@0 2388 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2389 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2390 emit_opcode(cbuf, $primary | 0x02);
duke@0 2391 } else {
duke@0 2392 // 32-bit immediate
duke@0 2393 emit_opcode(cbuf, $primary);
duke@0 2394 }
duke@0 2395 %}
duke@0 2396
duke@0 2397 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 2398 %{
duke@0 2399 // OpcSEr/m
duke@0 2400 int dstenc = $dst$$reg;
duke@0 2401 if (dstenc >= 8) {
duke@0 2402 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2403 dstenc -= 8;
duke@0 2404 }
duke@0 2405 // Emit primary opcode and set sign-extend bit
duke@0 2406 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2407 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2408 emit_opcode(cbuf, $primary | 0x02);
duke@0 2409 } else {
duke@0 2410 // 32-bit immediate
duke@0 2411 emit_opcode(cbuf, $primary);
duke@0 2412 }
duke@0 2413 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2414 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2415 %}
duke@0 2416
duke@0 2417 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 2418 %{
duke@0 2419 // OpcSEr/m
duke@0 2420 int dstenc = $dst$$reg;
duke@0 2421 if (dstenc < 8) {
duke@0 2422 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2423 } else {
duke@0 2424 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2425 dstenc -= 8;
duke@0 2426 }
duke@0 2427 // Emit primary opcode and set sign-extend bit
duke@0 2428 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2429 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2430 emit_opcode(cbuf, $primary | 0x02);
duke@0 2431 } else {
duke@0 2432 // 32-bit immediate
duke@0 2433 emit_opcode(cbuf, $primary);
duke@0 2434 }
duke@0 2435 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 2436 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2437 %}
duke@0 2438
duke@0 2439 enc_class Con8or32(immI imm)
duke@0 2440 %{
duke@0 2441 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 2442 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 2443 $$$emit8$imm$$constant;
duke@0 2444 } else {
duke@0 2445 // 32-bit immediate
duke@0 2446 $$$emit32$imm$$constant;
duke@0 2447 }
duke@0 2448 %}
duke@0 2449
duke@0 2450 enc_class opc2_reg(rRegI dst)
duke@0 2451 %{
duke@0 2452 // BSWAP
duke@0 2453 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 2454 %}
duke@0 2455
duke@0 2456 enc_class opc3_reg(rRegI dst)
duke@0 2457 %{
duke@0 2458 // BSWAP
duke@0 2459 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2460 %}
duke@0 2461
duke@0 2462 enc_class reg_opc(rRegI div)
duke@0 2463 %{
duke@0 2464 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2465 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2466 %}
duke@0 2467
duke@0 2468 enc_class enc_cmov(cmpOp cop)
duke@0 2469 %{
duke@0 2470 // CMOV
duke@0 2471 $$$emit8$primary;
duke@0 2472 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2473 %}
duke@0 2474
duke@0 2475 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
duke@0 2476 %{
duke@0 2477 // Invert sense of branch from sense of cmov
duke@0 2478 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2479 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
duke@0 2480 ? (UseXmmRegToRegMoveAll ? 3 : 4)
duke@0 2481 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
duke@0 2482 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
duke@0 2483 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
duke@0 2484 if ($dst$$reg < 8) {
duke@0 2485 if ($src$$reg >= 8) {
duke@0 2486 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2487 }
duke@0 2488 } else {
duke@0 2489 if ($src$$reg < 8) {
duke@0 2490 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2491 } else {
duke@0 2492 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2493 }
duke@0 2494 }
duke@0 2495 emit_opcode(cbuf, 0x0F);
duke@0 2496 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2497 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2498 %}
duke@0 2499
duke@0 2500 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
duke@0 2501 %{
duke@0 2502 // Invert sense of branch from sense of cmov
duke@0 2503 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
duke@0 2504 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
duke@0 2505
duke@0 2506 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
duke@0 2507 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
duke@0 2508 if ($dst$$reg < 8) {
duke@0 2509 if ($src$$reg >= 8) {
duke@0 2510 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2511 }
duke@0 2512 } else {
duke@0 2513 if ($src$$reg < 8) {
duke@0 2514 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2515 } else {
duke@0 2516 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2517 }
duke@0 2518 }
duke@0 2519 emit_opcode(cbuf, 0x0F);
duke@0 2520 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
duke@0 2521 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 2522 %}
duke@0 2523
duke@0 2524 enc_class enc_PartialSubtypeCheck()
duke@0 2525 %{
duke@0 2526 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2527 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2528 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2529 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2530 Label miss;
jrose@644 2531 const bool set_cond_codes = true;
duke@0 2532
duke@0 2533 MacroAssembler _masm(&cbuf);
jrose@644 2534 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2535 NULL, &miss,
jrose@644 2536 /*set_cond_codes:*/ true);
duke@0 2537 if ($primary) {
never@304 2538 __ xorptr(Rrdi, Rrdi);
duke@0 2539 }
duke@0 2540 __ bind(miss);
duke@0 2541 %}
duke@0 2542
duke@0 2543 enc_class Java_To_Interpreter(method meth)
duke@0 2544 %{
duke@0 2545 // CALL Java_To_Interpreter
duke@0 2546 // This is the instruction starting address for relocation info.
twisti@1668 2547 cbuf.set_insts_mark();
duke@0 2548 $$$emit8$primary;
duke@0 2549 // CALL directly to the runtime
duke@0 2550 emit_d32_reloc(cbuf,
twisti@1668 2551 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2552 runtime_call_Relocation::spec(),
duke@0 2553 RELOC_DISP32);
duke@0 2554 %}
duke@0 2555
twisti@1137 2556 enc_class preserve_SP %{
twisti@1668 2557 debug_only(int off0 = cbuf.insts_size());
twisti@1137 2558 MacroAssembler _masm(&cbuf);
twisti@1137 2559 // RBP is preserved across all calls, even compiled calls.
twisti@1137 2560 // Use it to preserve RSP in places where the callee might change the SP.
twisti@1487 2561 __ movptr(rbp_mh_SP_save, rsp);
twisti@1668 2562 debug_only(int off1 = cbuf.insts_size());
twisti@1137 2563 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
twisti@1137 2564 %}
twisti@1137 2565
twisti@1137 2566 enc_class restore_SP %{
twisti@1137 2567 MacroAssembler _masm(&cbuf);
twisti@1487 2568 __ movptr(rsp, rbp_mh_SP_save);
twisti@1137 2569 %}
twisti@1137 2570
duke@0 2571 enc_class Java_Static_Call(method meth)
duke@0 2572 %{
duke@0 2573 // JAVA STATIC CALL
duke@0 2574 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2575 // determine who we intended to call.
twisti@1668 2576 cbuf.set_insts_mark();
duke@0 2577 $$$emit8$primary;
duke@0 2578
duke@0 2579 if (!_method) {
duke@0 2580 emit_d32_reloc(cbuf,
twisti@1668 2581 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2582 runtime_call_Relocation::spec(),
duke@0 2583 RELOC_DISP32);
duke@0 2584 } else if (_optimized_virtual) {
duke@0 2585 emit_d32_reloc(cbuf,
twisti@1668 2586 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2587 opt_virtual_call_Relocation::spec(),
duke@0 2588 RELOC_DISP32);
duke@0 2589 } else {
duke@0 2590 emit_d32_reloc(cbuf,
twisti@1668 2591 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2592 static_call_Relocation::spec(),
duke@0 2593 RELOC_DISP32);
duke@0 2594 }
duke@0 2595 if (_method) {
duke@0 2596 // Emit stub for static call
duke@0 2597 emit_java_to_interp(cbuf);
duke@0 2598 }
duke@0 2599 %}
duke@0 2600
duke@0 2601 enc_class Java_Dynamic_Call(method meth)
duke@0 2602 %{
duke@0 2603 // JAVA DYNAMIC CALL
duke@0 2604 // !!!!!
duke@0 2605 // Generate "movq rax, -1", placeholder instruction to load oop-info
duke@0 2606 // emit_call_dynamic_prologue( cbuf );
twisti@1668 2607 cbuf.set_insts_mark();
duke@0 2608
duke@0 2609 // movq rax, -1
duke@0 2610 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2611 emit_opcode(cbuf, 0xB8 | RAX_enc);
duke@0 2612 emit_d64_reloc(cbuf,
duke@0 2613 (int64_t) Universe::non_oop_word(),
duke@0 2614 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
twisti@1668 2615 address virtual_call_oop_addr = cbuf.insts_mark();
duke@0 2616 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2617 // who we intended to call.
twisti@1668 2618 cbuf.set_insts_mark();
duke@0 2619 $$$emit8$primary;
duke@0 2620 emit_d32_reloc(cbuf,
twisti@1668 2621 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2622 virtual_call_Relocation::spec(virtual_call_oop_addr),
duke@0 2623 RELOC_DISP32);
duke@0 2624 %}
duke@0 2625
duke@0 2626 enc_class Java_Compiled_Call(method meth)
duke@0 2627 %{
duke@0 2628 // JAVA COMPILED CALL
duke@0 2629 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
duke@0 2630
duke@0 2631 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2632 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2633
duke@0 2634 // callq *disp(%rax)
twisti@1668 2635 cbuf.set_insts_mark();
duke@0 2636 $$$emit8$primary;
duke@0 2637 if (disp < 0x80) {
duke@0 2638 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2639 emit_d8(cbuf, disp); // Displacement
duke@0 2640 } else {
duke@0 2641 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2642 emit_d32(cbuf, disp); // Displacement
duke@0 2643 }
duke@0 2644 %}
duke@0 2645
duke@0 2646 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2647 %{
duke@0 2648 // SAL, SAR, SHR
duke@0 2649 int dstenc = $dst$$reg;
duke@0 2650 if (dstenc >= 8) {
duke@0 2651 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2652 dstenc -= 8;
duke@0 2653 }
duke@0 2654 $$$emit8$primary;
duke@0 2655 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2656 $$$emit8$shift$$constant;
duke@0 2657 %}
duke@0 2658
duke@0 2659 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2660 %{
duke@0 2661 // SAL, SAR, SHR
duke@0 2662 int dstenc = $dst$$reg;
duke@0 2663 if (dstenc < 8) {
duke@0 2664 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2665 } else {
duke@0 2666 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2667 dstenc -= 8;
duke@0 2668 }
duke@0 2669 $$$emit8$primary;
duke@0 2670 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2671 $$$emit8$shift$$constant;
duke@0 2672 %}
duke@0 2673
duke@0 2674 enc_class load_immI(rRegI dst, immI src)
duke@0 2675 %{
duke@0 2676 int dstenc = $dst$$reg;
duke@0 2677 if (dstenc >= 8) {
duke@0 2678 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2679 dstenc -= 8;
duke@0 2680 }
duke@0 2681 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2682 $$$emit32$src$$constant;
duke@0 2683 %}
duke@0 2684
duke@0 2685 enc_class load_immL(rRegL dst, immL src)
duke@0 2686 %{
duke@0 2687 int dstenc = $dst$$reg;
duke@0 2688 if (dstenc < 8) {
duke@0 2689 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2690 } else {
duke@0 2691 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2692 dstenc -= 8;
duke@0 2693 }
duke@0 2694 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2695 emit_d64(cbuf, $src$$constant);
duke@0 2696 %}
duke@0 2697
duke@0 2698 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2699 %{
duke@0 2700 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2701 int dstenc = $dst$$reg;
duke@0 2702 if (dstenc >= 8) {
duke@0 2703 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2704 dstenc -= 8;
duke@0 2705 }
duke@0 2706 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2707 $$$emit32$src$$constant;
duke@0 2708 %}
duke@0 2709
duke@0 2710 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2711 %{
duke@0 2712 int dstenc = $dst$$reg;
duke@0 2713 if (dstenc < 8) {
duke@0 2714 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2715 } else {
duke@0 2716 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2717 dstenc -= 8;
duke@0 2718 }
duke@0 2719 emit_opcode(cbuf, 0xC7);
duke@0 2720 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2721 $$$emit32$src$$constant;
duke@0 2722 %}
duke@0 2723
duke@0 2724 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2725 %{
duke@0 2726 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2727 int dstenc = $dst$$reg;
duke@0 2728 if (dstenc >= 8) {
duke@0 2729 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2730 dstenc -= 8;
duke@0 2731 }
duke@0 2732 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2733 $$$emit32$src$$constant;
duke@0 2734 %}
duke@0 2735
duke@0 2736 enc_class load_immP(rRegP dst, immP src)
duke@0 2737 %{
duke@0 2738 int dstenc = $dst$$reg;
duke@0 2739 if (dstenc < 8) {
duke@0 2740 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2741 } else {
duke@0 2742 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2743 dstenc -= 8;
duke@0 2744 }
duke@0 2745 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2746 // This next line should be generated from ADLC
duke@0 2747 if ($src->constant_is_oop()) {
duke@0 2748 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
duke@0 2749 } else {
duke@0 2750 emit_d64(cbuf, $src$$constant);
duke@0 2751 }
duke@0 2752 %}
duke@0 2753
duke@0 2754 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2755 enc_class enc_copy(rRegI dst, rRegI src)
duke@0 2756 %{
duke@0 2757 encode_copy(cbuf, $dst$$reg, $src$$reg);
duke@0 2758 %}
duke@0 2759
duke@0 2760 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
duke@0 2761 enc_class enc_CopyXD( RegD dst, RegD src ) %{
duke@0 2762 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
duke@0 2763 %}
duke@0 2764
duke@0 2765 enc_class enc_copy_always(rRegI dst, rRegI src)
duke@0 2766 %{
duke@0 2767 int srcenc = $src$$reg;
duke@0 2768 int dstenc = $dst$$reg;
duke@0 2769
duke@0 2770 if (dstenc < 8) {
duke@0 2771 if (srcenc >= 8) {
duke@0 2772 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2773 srcenc -= 8;
duke@0 2774 }
duke@0 2775 } else {
duke@0 2776 if (srcenc < 8) {
duke@0 2777 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2778 } else {
duke@0 2779 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2780 srcenc -= 8;
duke@0 2781 }
duke@0 2782 dstenc -= 8;
duke@0 2783 }
duke@0 2784
duke@0 2785 emit_opcode(cbuf, 0x8B);
duke@0 2786 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2787 %}
duke@0 2788
duke@0 2789 enc_class enc_copy_wide(rRegL dst, rRegL src)
duke@0 2790 %{
duke@0 2791 int srcenc = $src$$reg;
duke@0 2792 int dstenc = $dst$$reg;
duke@0 2793
duke@0 2794 if (dstenc != srcenc) {
duke@0 2795 if (dstenc < 8) {
duke@0 2796 if (srcenc < 8) {
duke@0 2797 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2798 } else {
duke@0 2799 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2800 srcenc -= 8;
duke@0 2801 }
duke@0 2802 } else {
duke@0 2803 if (srcenc < 8) {
duke@0 2804 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2805 } else {
duke@0 2806 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2807 srcenc -= 8;
duke@0 2808 }
duke@0 2809 dstenc -= 8;
duke@0 2810 }
duke@0 2811 emit_opcode(cbuf, 0x8B);
duke@0 2812 emit_rm(cbuf, 0x3, dstenc, srcenc);
duke@0 2813 }
duke@0 2814 %}
duke@0 2815
duke@0 2816 enc_class Con32(immI src)
duke@0 2817 %{
duke@0 2818 // Output immediate
duke@0 2819 $$$emit32$src$$constant;
duke@0 2820 %}
duke@0 2821
duke@0 2822 enc_class Con64(immL src)
duke@0 2823 %{
duke@0 2824 // Output immediate
duke@0 2825 emit_d64($src$$constant);
duke@0 2826 %}
duke@0 2827
duke@0 2828 enc_class Con32F_as_bits(immF src)
duke@0 2829 %{
duke@0 2830 // Output Float immediate bits
duke@0 2831 jfloat jf = $src$$constant;
duke@0 2832 jint jf_as_bits = jint_cast(jf);
duke@0 2833 emit_d32(cbuf, jf_as_bits);
duke@0 2834 %}
duke@0 2835
duke@0 2836 enc_class Con16(immI src)
duke@0 2837 %{
duke@0 2838 // Output immediate
duke@0 2839 $$$emit16$src$$constant;
duke@0 2840 %}
duke@0 2841
duke@0 2842 // How is this different from Con32??? XXX
duke@0 2843 enc_class Con_d32(immI src)
duke@0 2844 %{
duke@0 2845 emit_d32(cbuf,$src$$constant);
duke@0 2846 %}
duke@0 2847
duke@0 2848 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2849 // Output immediate memory reference
duke@0 2850 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2851 emit_d32(cbuf, 0x00);
duke@0 2852 %}
duke@0 2853
duke@0 2854 enc_class lock_prefix()
duke@0 2855 %{
duke@0 2856 if (os::is_MP()) {
duke@0 2857 emit_opcode(cbuf, 0xF0); // lock
duke@0 2858 }
duke@0 2859 %}
duke@0 2860
duke@0 2861 enc_class REX_mem(memory mem)
duke@0 2862 %{
duke@0 2863 if ($mem$$base >= 8) {
duke@0 2864 if ($mem$$index < 8) {
duke@0 2865 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2866 } else {
duke@0 2867 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2868 }
duke@0 2869 } else {
duke@0 2870 if ($mem$$index >= 8) {
duke@0 2871 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2872 }
duke@0 2873 }
duke@0 2874 %}
duke@0 2875
duke@0 2876 enc_class REX_mem_wide(memory mem)
duke@0 2877 %{
duke@0 2878 if ($mem$$base >= 8) {
duke@0 2879 if ($mem$$index < 8) {
duke@0 2880 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2881 } else {
duke@0 2882 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2883 }
duke@0 2884 } else {
duke@0 2885 if ($mem$$index < 8) {
duke@0 2886 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2887 } else {
duke@0 2888 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2889 }
duke@0 2890 }
duke@0 2891 %}
duke@0 2892
duke@0 2893 // for byte regs
duke@0 2894 enc_class REX_breg(rRegI reg)
duke@0 2895 %{
duke@0 2896 if ($reg$$reg >= 4) {
duke@0 2897 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2898 }
duke@0 2899 %}
duke@0 2900
duke@0 2901 // for byte regs
duke@0 2902 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2903 %{
duke@0 2904 if ($dst$$reg < 8) {
duke@0 2905 if ($src$$reg >= 4) {
duke@0 2906 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2907 }
duke@0 2908 } else {
duke@0 2909 if ($src$$reg < 8) {
duke@0 2910 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2911 } else {
duke@0 2912 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2913 }
duke@0 2914 }
duke@0 2915 %}
duke@0 2916
duke@0 2917 // for byte regs
duke@0 2918 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2919 %{
duke@0 2920 if ($reg$$reg < 8) {
duke@0 2921 if ($mem$$base < 8) {
duke@0 2922 if ($mem$$index >= 8) {
duke@0 2923 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2924 } else if ($reg$$reg >= 4) {
duke@0 2925 emit_opcode(cbuf, Assembler::REX);
duke@0 2926 }
duke@0 2927 } else {
duke@0 2928 if ($mem$$index < 8) {
duke@0 2929 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2930 } else {
duke@0 2931 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2932 }
duke@0 2933 }
duke@0 2934 } else {
duke@0 2935 if ($mem$$base < 8) {
duke@0 2936 if ($mem$$index < 8) {
duke@0 2937 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2938 } else {
duke@0 2939 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2940 }
duke@0 2941 } else {
duke@0 2942 if ($mem$$index < 8) {
duke@0 2943 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2944 } else {
duke@0 2945 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2946 }
duke@0 2947 }
duke@0 2948 }
duke@0 2949 %}
duke@0 2950
duke@0 2951 enc_class REX_reg(rRegI reg)
duke@0 2952 %{
duke@0 2953 if ($reg$$reg >= 8) {
duke@0 2954 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2955 }
duke@0 2956 %}
duke@0 2957
duke@0 2958 enc_class REX_reg_wide(rRegI reg)
duke@0 2959 %{
duke@0 2960 if ($reg$$reg < 8) {
duke@0 2961 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2962 } else {
duke@0 2963 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2964 }
duke@0 2965 %}
duke@0 2966
duke@0 2967 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2968 %{
duke@0 2969 if ($dst$$reg < 8) {
duke@0 2970 if ($src$$reg >= 8) {
duke@0 2971 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2972 }
duke@0 2973 } else {
duke@0 2974 if ($src$$reg < 8) {
duke@0 2975 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2976 } else {
duke@0 2977 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2978 }
duke@0 2979 }
duke@0 2980 %}
duke@0 2981
duke@0 2982 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2983 %{
duke@0 2984 if ($dst$$reg < 8) {
duke@0 2985 if ($src$$reg < 8) {
duke@0 2986 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2987 } else {
duke@0 2988 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2989 }
duke@0 2990 } else {
duke@0 2991 if ($src$$reg < 8) {
duke@0 2992 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2993 } else {
duke@0 2994 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2995 }
duke@0 2996 }
duke@0 2997 %}
duke@0 2998
duke@0 2999 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 3000 %{
duke@0 3001 if ($reg$$reg < 8) {
duke@0 3002 if ($mem$$base < 8) {
duke@0 3003 if ($mem$$index >= 8) {
duke@0 3004 emit_opcode(cbuf, Assembler::REX_X);
duke@0 3005 }
duke@0 3006 } else {
duke@0 3007 if ($mem$$index < 8) {
duke@0 3008 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3009 } else {
duke@0 3010 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 3011 }
duke@0 3012 }
duke@0 3013 } else {
duke@0 3014 if ($mem$$base < 8) {
duke@0 3015 if ($mem$$index < 8) {
duke@0 3016 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3017 } else {
duke@0 3018 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 3019 }
duke@0 3020 } else {
duke@0 3021 if ($mem$$index < 8) {
duke@0 3022 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 3023 } else {
duke@0 3024 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 3025 }
duke@0 3026 }
duke@0 3027 }
duke@0 3028 %}
duke@0 3029
duke@0 3030 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 3031 %{
duke@0 3032 if ($reg$$reg < 8) {
duke@0 3033 if ($mem$$base < 8) {
duke@0 3034 if ($mem$$index < 8) {
duke@0 3035 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3036 } else {
duke@0 3037 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 3038 }
duke@0 3039 } else {
duke@0 3040 if ($mem$$index < 8) {
duke@0 3041 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3042 } else {
duke@0 3043 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 3044 }
duke@0 3045 }
duke@0 3046 } else {
duke@0 3047 if ($mem$$base < 8) {
duke@0 3048 if ($mem$$index < 8) {
duke@0 3049 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3050 } else {
duke@0 3051 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 3052 }
duke@0 3053 } else {
duke@0 3054 if ($mem$$index < 8) {
duke@0 3055 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3056 } else {
duke@0 3057 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 3058 }
duke@0 3059 }
duke@0 3060 }
duke@0 3061 %}
duke@0 3062
duke@0 3063 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 3064 %{
duke@0 3065 // High registers handle in encode_RegMem
duke@0 3066 int reg = $ereg$$reg;
duke@0 3067 int base = $mem$$base;
duke@0 3068 int index = $mem$$index;
duke@0 3069 int scale = $mem$$scale;
duke@0 3070 int disp = $mem$$disp;
duke@0 3071 bool disp_is_oop = $mem->disp_is_oop();
duke@0 3072
duke@0 3073 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
duke@0 3074 %}
duke@0 3075
duke@0 3076 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 3077 %{
duke@0 3078 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 3079
duke@0 3080 // High registers handle in encode_RegMem
duke@0 3081 int base = $mem$$base;
duke@0 3082 int index = $mem$$index;
duke@0 3083 int scale = $mem$$scale;
duke@0 3084 int displace = $mem$$disp;
duke@0 3085
duke@0 3086 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
duke@0 3087 // working with static
duke@0 3088 // globals
duke@0 3089 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
duke@0 3090 disp_is_oop);
duke@0 3091 %}
duke@0 3092
duke@0 3093 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 3094 %{
duke@0 3095 int reg_encoding = $dst$$reg;
duke@0 3096 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 3097 int index = 0x04; // 0x04 indicates no index
duke@0 3098 int scale = 0x00; // 0x00 indicates no scale
duke@0 3099 int displace = $src1$$constant; // 0x00 indicates no displacement
duke@0 3100 bool disp_is_oop = false;
duke@0 3101 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
duke@0 3102 disp_is_oop);
duke@0 3103 %}
duke@0 3104
duke@0 3105 enc_class neg_reg(rRegI dst)
duke@0 3106 %{
duke@0 3107 int dstenc = $dst$$reg;
duke@0 3108 if (dstenc >= 8) {
duke@0 3109 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3110 dstenc -= 8;
duke@0 3111 }
duke@0 3112 // NEG $dst
duke@0 3113 emit_opcode(cbuf, 0xF7);
duke@0 3114 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3115 %}
duke@0 3116
duke@0 3117 enc_class neg_reg_wide(rRegI dst)
duke@0 3118 %{
duke@0 3119 int dstenc = $dst$$reg;
duke@0 3120 if (dstenc < 8) {
duke@0 3121 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3122 } else {
duke@0 3123 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3124 dstenc -= 8;
duke@0 3125 }
duke@0 3126 // NEG $dst
duke@0 3127 emit_opcode(cbuf, 0xF7);
duke@0 3128 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 3129 %}
duke@0 3130
duke@0 3131 enc_class setLT_reg(rRegI dst)
duke@0 3132 %{
duke@0 3133 int dstenc = $dst$$reg;
duke@0 3134 if (dstenc >= 8) {
duke@0 3135 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3136 dstenc -= 8;
duke@0 3137 } else if (dstenc >= 4) {
duke@0 3138 emit_opcode(cbuf, Assembler::REX);
duke@0 3139 }
duke@0 3140 // SETLT $dst
duke@0 3141 emit_opcode(cbuf, 0x0F);
duke@0 3142 emit_opcode(cbuf, 0x9C);
duke@0 3143 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3144 %}
duke@0 3145
duke@0 3146 enc_class setNZ_reg(rRegI dst)
duke@0 3147 %{
duke@0 3148 int dstenc = $dst$$reg;
duke@0 3149 if (dstenc >= 8) {
duke@0 3150 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3151 dstenc -= 8;
duke@0 3152 } else if (dstenc >= 4) {
duke@0 3153 emit_opcode(cbuf, Assembler::REX);
duke@0 3154 }
duke@0 3155 // SETNZ $dst
duke@0 3156 emit_opcode(cbuf, 0x0F);
duke@0 3157 emit_opcode(cbuf, 0x95);
duke@0 3158 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 3159 %}
duke@0 3160
duke@0 3161
duke@0 3162 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 3163 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 3164 %{
duke@0 3165 int src1enc = $src1$$reg;
duke@0 3166 int src2enc = $src2$$reg;
duke@0 3167 int dstenc = $dst$$reg;
duke@0 3168
duke@0 3169 // cmpq $src1, $src2
duke@0 3170 if (src1enc < 8) {
duke@0 3171 if (src2enc < 8) {
duke@0 3172 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3173 } else {
duke@0 3174 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 3175 }
duke@0 3176 } else {
duke@0 3177 if (src2enc < 8) {
duke@0 3178 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 3179 } else {
duke@0 3180 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 3181 }
duke@0 3182 }
duke@0 3183 emit_opcode(cbuf, 0x3B);
duke@0 3184 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 3185
duke@0 3186 // movl $dst, -1
duke@0 3187 if (dstenc >= 8) {
duke@0 3188 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3189 }
duke@0 3190 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 3191 emit_d32(cbuf, -1);
duke@0 3192
duke@0 3193 // jl,s done
duke@0 3194 emit_opcode(cbuf, 0x7C);
duke@0 3195 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 3196
duke@0 3197 // setne $dst
duke@0 3198 if (dstenc >= 4) {
duke@0 3199 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 3200 }
duke@0 3201 emit_opcode(cbuf, 0x0F);
duke@0 3202 emit_opcode(cbuf, 0x95);
duke@0 3203 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 3204
duke@0 3205 // movzbl $dst, $dst
duke@0 3206 if (dstenc >= 4) {
duke@0 3207 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 3208 }
duke@0 3209 emit_opcode(cbuf, 0x0F);
duke@0 3210 emit_opcode(cbuf, 0xB6);
duke@0 3211 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 3212 %}
duke@0 3213
duke@0 3214 enc_class Push_ResultXD(regD dst) %{
duke@0 3215 int dstenc = $dst$$reg;
duke@0 3216
duke@0 3217 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
duke@0 3218
duke@0 3219 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
duke@0 3220 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
duke@0 3221 if (dstenc >= 8) {
duke@0 3222 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3223 }
duke@0 3224 emit_opcode (cbuf, 0x0F );
duke@0 3225 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
duke@0 3226 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3227
duke@0 3228 // add rsp,8
duke@0 3229 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3230 emit_opcode(cbuf,0x83);
duke@0 3231 emit_rm(cbuf,0x3, 0x0, RSP_enc);
duke@0 3232 emit_d8(cbuf,0x08);
duke@0 3233 %}
duke@0 3234
duke@0 3235 enc_class Push_SrcXD(regD src) %{
duke@0 3236 int srcenc = $src$$reg;
duke@0 3237
duke@0 3238 // subq rsp,#8
duke@0 3239 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3240 emit_opcode(cbuf, 0x83);
duke@0 3241 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3242 emit_d8(cbuf, 0x8);
duke@0 3243
duke@0 3244 // movsd [rsp],src
duke@0 3245 emit_opcode(cbuf, 0xF2);
duke@0 3246 if (srcenc >= 8) {
duke@0 3247 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3248 }
duke@0 3249 emit_opcode(cbuf, 0x0F);
duke@0 3250 emit_opcode(cbuf, 0x11);
duke@0 3251 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
duke@0 3252
duke@0 3253 // fldd [rsp]
duke@0 3254 emit_opcode(cbuf, 0x66);
duke@0 3255 emit_opcode(cbuf, 0xDD);
duke@0 3256 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
duke@0 3257 %}
duke@0 3258
duke@0 3259
duke@0 3260 enc_class movq_ld(regD dst, memory mem) %{
duke@0 3261 MacroAssembler _masm(&cbuf);
twisti@624 3262 __ movq($dst$$XMMRegister, $mem$$Address);
duke@0 3263 %}
duke@0 3264
duke@0 3265 enc_class movq_st(memory mem, regD src) %{
duke@0 3266 MacroAssembler _masm(&cbuf);
twisti@624 3267 __ movq($mem$$Address, $src$$XMMRegister);
duke@0 3268 %}
duke@0 3269
duke@0 3270 enc_class pshufd_8x8(regF dst, regF src) %{
duke@0 3271 MacroAssembler _masm(&cbuf);
duke@0 3272
duke@0 3273 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
duke@0 3274 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
duke@0 3275 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
duke@0 3276 %}
duke@0 3277
duke@0 3278 enc_class pshufd_4x16(regF dst, regF src) %{
duke@0 3279 MacroAssembler _masm(&cbuf);
duke@0 3280
duke@0 3281 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
duke@0 3282 %}
duke@0 3283
duke@0 3284 enc_class pshufd(regD dst, regD src, int mode) %{
duke@0 3285 MacroAssembler _masm(&cbuf);
duke@0 3286
duke@0 3287 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
duke@0 3288 %}
duke@0 3289
duke@0 3290 enc_class pxor(regD dst, regD src) %{
duke@0 3291 MacroAssembler _masm(&cbuf);
duke@0 3292
duke@0 3293 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
duke@0 3294 %}
duke@0 3295
duke@0 3296 enc_class mov_i2x(regD dst, rRegI src) %{
duke@0 3297 MacroAssembler _masm(&cbuf);
duke@0 3298
duke@0 3299 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
duke@0 3300 %}
duke@0 3301
duke@0 3302 // obj: object to lock
duke@0 3303 // box: box address (header location) -- killed
duke@0 3304 // tmp: rax -- killed
duke@0 3305 // scr: rbx -- killed
duke@0 3306 //
duke@0 3307 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 3308 // from i486.ad. See that file for comments.
duke@0 3309 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 3310 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 3311
duke@0 3312
duke@0 3313 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 3314 %{
duke@0 3315 Register objReg = as_Register((int)$obj$$reg);
duke@0 3316 Register boxReg = as_Register((int)$box$$reg);
duke@0 3317 Register tmpReg = as_Register($tmp$$reg);
duke@0 3318 Register scrReg = as_Register($scr$$reg);
duke@0 3319 MacroAssembler masm(&cbuf);
duke@0 3320
duke@0 3321 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 3322 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 3323 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 3324
duke@0 3325 if (_counters != NULL) {
duke@0 3326 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 3327 }
duke@0 3328 if (EmitSync & 1) {
never@304 3329 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 3330 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 3331 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 3332 } else
duke@0 3333 if (EmitSync & 2) {
duke@0 3334 Label DONE_LABEL;
duke@0 3335 if (UseBiasedLocking) {
duke@0 3336 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 3337 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 3338 }
never@304 3339 // QQQ was movl...
never@304 3340 masm.movptr(tmpReg, 0x1);
never@304 3341 masm.orptr(tmpReg, Address(objReg, 0));
never@304 3342 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3343 if (os::is_MP()) {
duke@0 3344 masm.lock();
duke@0 3345 }
never@304 3346 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3347 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 3348
duke@0 3349 // Recursive locking
never@304 3350 masm.subptr(tmpReg, rsp);
never@304 3351 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3352 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3353
duke@0 3354 masm.bind(DONE_LABEL);
duke@0 3355 masm.nop(); // avoid branch to branch
duke@0 3356 } else {
duke@0 3357 Label DONE_LABEL, IsInflated, Egress;
duke@0 3358
iveresov@2251 3359 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 3360 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
iveresov@2251 3361 masm.jcc (Assembler::notZero, IsInflated) ;
iveresov@2251 3362
duke@0 3363 // it's stack-locked, biased or neutral
duke@0 3364 // TODO: optimize markword triage order to reduce the number of
duke@0 3365 // conditional branches in the most common cases.
duke@0 3366 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 3367 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 3368 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 3369
kvn@420 3370 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3371 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 3372 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 3373 }
duke@0 3374
never@304 3375 // was q will it destroy high?
iveresov@2251 3376 masm.orl (tmpReg, 1) ;
iveresov@2251 3377 masm.movptr(Address(boxReg, 0), tmpReg) ;
iveresov@2251 3378 if (os::is_MP()) { masm.lock(); }
never@304 3379 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 3380 if (_counters != NULL) {
duke@0 3381 masm.cond_inc32(Assembler::equal,
duke@0 3382 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3383 }
duke@0 3384 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 3385
duke@0 3386 // Recursive locking
never@304 3387 masm.subptr(tmpReg, rsp);
never@304 3388 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 3389 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 3390 if (_counters != NULL) {
duke@0 3391 masm.cond_inc32(Assembler::equal,
duke@0 3392 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 3393 }
duke@0 3394 masm.jmp (DONE_LABEL) ;
duke@0 3395
duke@0 3396 masm.bind (IsInflated) ;
duke@0 3397 // It's inflated
duke@0 3398
duke@0 3399 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 3400 // relocating (deferring) the following ST.
duke@0 3401 // We should also think about trying a CAS without having
duke@0 3402 // fetched _owner. If the CAS is successful we may
duke@0 3403 // avoid an RTO->RTS upgrade on the $line.
never@304 3404 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 3405 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 3406
iveresov@2251 3407 masm.mov (boxReg, tmpReg) ;
iveresov@2251 3408 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 3409 masm.testptr(tmpReg, tmpReg) ;
iveresov@2251 3410 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 3411
duke@0 3412 // It's inflated and appears unlocked
iveresov@2251 3413 if (os::is_MP()) { masm.lock(); }
iveresov@2251 3414 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 3415 // Intentional fall-through into DONE_LABEL ...
duke@0 3416
duke@0 3417 masm.bind (DONE_LABEL) ;
duke@0 3418 masm.nop () ; // avoid jmp to jmp
duke@0 3419 }
duke@0 3420 %}
duke@0 3421
duke@0 3422 // obj: object to unlock
duke@0 3423 // box: box address (displaced header location), killed
duke@0 3424 // RBX: killed tmp; cannot be obj nor box
duke@0 3425 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 3426 %{
duke@0 3427
duke@0 3428 Register objReg = as_Register($obj$$reg);
duke@0 3429 Register boxReg = as_Register($box$$reg);
duke@0 3430 Register tmpReg = as_Register($tmp$$reg);
duke@0 3431 MacroAssembler masm(&cbuf);
duke@0 3432
iveresov@2251 3433 if (EmitSync & 4) {
iveresov@2251 3434 masm.cmpptr(rsp, 0) ;
duke@0 3435 } else
duke@0 3436 if (EmitSync & 8) {
duke@0 3437 Label DONE_LABEL;
duke@0 3438 if (UseBiasedLocking) {
duke@0 3439 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3440 }
duke@0 3441
duke@0 3442 // Check whether the displaced header is 0
duke@0 3443 //(=> recursive unlock)
never@304 3444 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 3445 masm.testptr(tmpReg, tmpReg);
duke@0 3446 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 3447
duke@0 3448 // If not recursive lock, reset the header to displaced header
duke@0 3449 if (os::is_MP()) {
duke@0 3450 masm.lock();
duke@0 3451 }
never@304 3452 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3453 masm.bind(DONE_LABEL);
duke@0 3454 masm.nop(); // avoid branch to branch
duke@0 3455 } else {
duke@0 3456 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 3457
kvn@420 3458 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 3459 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 3460 }
iveresov@2251 3461
iveresov@2251 3462 masm.movptr(tmpReg, Address(objReg, 0)) ;
iveresov@2251 3463 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
iveresov@2251 3464 masm.jcc (Assembler::zero, DONE_LABEL) ;
iveresov@2251 3465 masm.testl (tmpReg, 0x02) ;
iveresov@2251 3466 masm.jcc (Assembler::zero, Stacked) ;
iveresov@2251 3467
duke@0 3468 // It's inflated
iveresov@2251 3469 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 3470 masm.xorptr(boxReg, r15_thread) ;
iveresov@2251 3471 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
iveresov@2251 3472 masm.jcc (Assembler::notZero, DONE_LABEL) ;
iveresov@2251 3473 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
iveresov@2251 3474 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
iveresov@2251 3475 masm.jcc (Assembler::notZero, CheckSucc) ;
iveresov@2251 3476 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
iveresov@2251 3477 masm.jmp (DONE_LABEL) ;
iveresov@2251 3478
iveresov@2251 3479 if ((EmitSync & 65536) == 0) {
duke@0 3480 Label LSuccess, LGoSlowPath ;
duke@0 3481 masm.bind (CheckSucc) ;
never@304 3482 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3483 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 3484
duke@0 3485 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 3486 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 3487 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 3488 // are all faster when the write buffer is populated.
never@304 3489 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3490 if (os::is_MP()) {
never@304 3491 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 3492 }
never@304 3493 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 3494 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 3495
never@304 3496 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 3497 if (os::is_MP()) { masm.lock(); }
never@304 3498 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 3499 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 3500 // Intentional fall-through into slow-path
duke@0 3501
duke@0 3502 masm.bind (LGoSlowPath) ;
duke@0 3503 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 3504 masm.jmp (DONE_LABEL) ;
duke@0 3505
duke@0 3506 masm.bind (LSuccess) ;
duke@0 3507 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 3508 masm.jmp (DONE_LABEL) ;
duke@0 3509 }
duke@0 3510
iveresov@2251 3511 masm.bind (Stacked) ;
never@304 3512 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
iveresov@2251 3513 if (os::is_MP()) { masm.lock(); }
never@304 3514 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 3515
duke@0 3516 if (EmitSync & 65536) {
duke@0 3517 masm.bind (CheckSucc) ;
duke@0 3518 }
duke@0 3519 masm.bind(DONE_LABEL);
duke@0 3520 if (EmitSync & 32768) {
duke@0 3521 masm.nop(); // avoid branch to branch
duke@0 3522 }
duke@0 3523 }
duke@0 3524 %}
duke@0 3525
rasbold@169 3526
duke@0 3527 enc_class enc_rethrow()
duke@0 3528 %{
twisti@1668 3529 cbuf.set_insts_mark();
duke@0 3530 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 3531 emit_d32_reloc(cbuf,
twisti@1668 3532 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 3533 runtime_call_Relocation::spec(),
duke@0 3534 RELOC_DISP32);
duke@0 3535 %}
duke@0 3536
duke@0 3537 enc_class absF_encoding(regF dst)
duke@0 3538 %{
duke@0 3539 int dstenc = $dst$$reg;
never@304 3540 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
duke@0 3541
twisti@1668 3542 cbuf.set_insts_mark();
duke@0 3543 if (dstenc >= 8) {
duke@0 3544 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3545 dstenc -= 8;
duke@0 3546 }
duke@0 3547 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3548 emit_opcode(cbuf, 0x0F);
duke@0 3549 emit_opcode(cbuf, 0x54);
duke@0 3550 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3551 emit_d32_reloc(cbuf, signmask_address);
duke@0 3552 %}
duke@0 3553
duke@0 3554 enc_class absD_encoding(regD dst)
duke@0 3555 %{
duke@0 3556 int dstenc = $dst$$reg;
never@304 3557 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
duke@0 3558
twisti@1668 3559 cbuf.set_insts_mark();
duke@0 3560 emit_opcode(cbuf, 0x66);
duke@0 3561 if (dstenc >= 8) {
duke@0 3562 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3563 dstenc -= 8;
duke@0 3564 }
duke@0 3565 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3566 emit_opcode(cbuf, 0x0F);
duke@0 3567 emit_opcode(cbuf, 0x54);
duke@0 3568 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3569 emit_d32_reloc(cbuf, signmask_address);
duke@0 3570 %}
duke@0 3571
duke@0 3572 enc_class negF_encoding(regF dst)
duke@0 3573 %{
duke@0 3574 int dstenc = $dst$$reg;
never@304 3575 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
duke@0 3576
twisti@1668 3577 cbuf.set_insts_mark();
duke@0 3578 if (dstenc >= 8) {
duke@0 3579 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3580 dstenc -= 8;
duke@0 3581 }
duke@0 3582 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3583 emit_opcode(cbuf, 0x0F);
duke@0 3584 emit_opcode(cbuf, 0x57);
duke@0 3585 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3586 emit_d32_reloc(cbuf, signflip_address);
duke@0 3587 %}
duke@0 3588
duke@0 3589 enc_class negD_encoding(regD dst)
duke@0 3590 %{
duke@0 3591 int dstenc = $dst$$reg;
never@304 3592 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3593
twisti@1668 3594 cbuf.set_insts_mark();
duke@0 3595 emit_opcode(cbuf, 0x66);
duke@0 3596 if (dstenc >= 8) {
duke@0 3597 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3598 dstenc -= 8;
duke@0 3599 }
duke@0 3600 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3601 emit_opcode(cbuf, 0x0F);
duke@0 3602 emit_opcode(cbuf, 0x57);
duke@0 3603 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
duke@0 3604 emit_d32_reloc(cbuf, signflip_address);
duke@0 3605 %}
duke@0 3606
duke@0 3607 enc_class f2i_fixup(rRegI dst, regF src)
duke@0 3608 %{
duke@0 3609 int dstenc = $dst$$reg;
duke@0 3610 int srcenc = $src$$reg;
duke@0 3611
duke@0 3612 // cmpl $dst, #0x80000000
duke@0 3613 if (dstenc >= 8) {
duke@0 3614 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3615 }
duke@0 3616 emit_opcode(cbuf, 0x81);
duke@0 3617 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3618 emit_d32(cbuf, 0x80000000);
duke@0 3619
duke@0 3620 // jne,s done
duke@0 3621 emit_opcode(cbuf, 0x75);
duke@0 3622 if (srcenc < 8 && dstenc < 8) {
duke@0 3623 emit_d8(cbuf, 0xF);
duke@0 3624 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3625 emit_d8(cbuf, 0x11);
duke@0 3626 } else {
duke@0 3627 emit_d8(cbuf, 0x10);
duke@0 3628 }
duke@0 3629
duke@0 3630 // subq rsp, #8
duke@0 3631 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3632 emit_opcode(cbuf, 0x83);
duke@0 3633 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3634 emit_d8(cbuf, 8);
duke@0 3635
duke@0 3636 // movss [rsp], $src
duke@0 3637 emit_opcode(cbuf, 0xF3);
duke@0 3638 if (srcenc >= 8) {
duke@0 3639 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3640 }
duke@0 3641 emit_opcode(cbuf, 0x0F);
duke@0 3642 emit_opcode(cbuf, 0x11);
duke@0 3643 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3644
duke@0 3645 // call f2i_fixup
twisti@1668 3646 cbuf.set_insts_mark();
duke@0 3647 emit_opcode(cbuf, 0xE8);
duke@0 3648 emit_d32_reloc(cbuf,
duke@0 3649 (int)
twisti@1668 3650 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4),
duke@0 3651 runtime_call_Relocation::spec(),
duke@0 3652 RELOC_DISP32);
duke@0 3653
duke@0 3654 // popq $dst
duke@0 3655 if (dstenc >= 8) {
duke@0 3656 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3657 }
duke@0 3658 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3659
duke@0 3660 // done:
duke@0 3661 %}
duke@0 3662
duke@0 3663 enc_class f2l_fixup(rRegL dst, regF src)
duke@0 3664 %{
duke@0 3665 int dstenc = $dst$$reg;
duke@0 3666 int srcenc = $src$$reg;
never@304 3667 address const_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3668
duke@0 3669 // cmpq $dst, [0x8000000000000000]
twisti@1668 3670 cbuf.set_insts_mark();
duke@0 3671 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 3672 emit_opcode(cbuf, 0x39);
duke@0 3673 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3674 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
duke@0 3675 emit_d32_reloc(cbuf, const_address);
duke@0 3676
duke@0 3677
duke@0 3678 // jne,s done
duke@0 3679 emit_opcode(cbuf, 0x75);
duke@0 3680 if (srcenc < 8 && dstenc < 8) {
duke@0 3681 emit_d8(cbuf, 0xF);
duke@0 3682 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3683 emit_d8(cbuf, 0x11);
duke@0 3684 } else {
duke@0 3685 emit_d8(cbuf, 0x10);
duke@0 3686 }
duke@0 3687
duke@0 3688 // subq rsp, #8
duke@0 3689 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3690 emit_opcode(cbuf, 0x83);
duke@0 3691 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3692 emit_d8(cbuf, 8);
duke@0 3693
duke@0 3694 // movss [rsp], $src
duke@0 3695 emit_opcode(cbuf, 0xF3);
duke@0 3696 if (srcenc >= 8) {
duke@0 3697 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3698 }
duke@0 3699 emit_opcode(cbuf, 0x0F);
duke@0 3700 emit_opcode(cbuf, 0x11);
duke@0 3701 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3702
duke@0 3703 // call f2l_fixup
twisti@1668 3704 cbuf.set_insts_mark();
duke@0 3705 emit_opcode(cbuf, 0xE8);
duke@0 3706 emit_d32_reloc(cbuf,
duke@0 3707 (int)
twisti@1668 3708 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4),
duke@0 3709 runtime_call_Relocation::spec(),
duke@0 3710 RELOC_DISP32);
duke@0 3711
duke@0 3712 // popq $dst
duke@0 3713 if (dstenc >= 8) {
duke@0 3714 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3715 }
duke@0 3716 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3717
duke@0 3718 // done:
duke@0 3719 %}
duke@0 3720
duke@0 3721 enc_class d2i_fixup(rRegI dst, regD src)
duke@0 3722 %{
duke@0 3723 int dstenc = $dst$$reg;
duke@0 3724 int srcenc = $src$$reg;
duke@0 3725
duke@0 3726 // cmpl $dst, #0x80000000
duke@0 3727 if (dstenc >= 8) {
duke@0 3728 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3729 }
duke@0 3730 emit_opcode(cbuf, 0x81);
duke@0 3731 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
duke@0 3732 emit_d32(cbuf, 0x80000000);
duke@0 3733
duke@0 3734 // jne,s done
duke@0 3735 emit_opcode(cbuf, 0x75);
duke@0 3736 if (srcenc < 8 && dstenc < 8) {
duke@0 3737 emit_d8(cbuf, 0xF);
duke@0 3738 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3739 emit_d8(cbuf, 0x11);
duke@0 3740 } else {
duke@0 3741 emit_d8(cbuf, 0x10);
duke@0 3742 }
duke@0 3743
duke@0 3744 // subq rsp, #8
duke@0 3745 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3746 emit_opcode(cbuf, 0x83);
duke@0 3747 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3748 emit_d8(cbuf, 8);
duke@0 3749
duke@0 3750 // movsd [rsp], $src
duke@0 3751 emit_opcode(cbuf, 0xF2);
duke@0 3752 if (srcenc >= 8) {
duke@0 3753 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3754 }
duke@0 3755 emit_opcode(cbuf, 0x0F);
duke@0 3756 emit_opcode(cbuf, 0x11);
duke@0 3757 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3758
duke@0 3759 // call d2i_fixup
twisti@1668 3760 cbuf.set_insts_mark();
duke@0 3761 emit_opcode(cbuf, 0xE8);
duke@0 3762 emit_d32_reloc(cbuf,
duke@0 3763 (int)
twisti@1668 3764 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4),
duke@0 3765 runtime_call_Relocation::spec(),
duke@0 3766 RELOC_DISP32);
duke@0 3767
duke@0 3768 // popq $dst
duke@0 3769 if (dstenc >= 8) {
duke@0 3770 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3771 }
duke@0 3772 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3773
duke@0 3774 // done:
duke@0 3775 %}
duke@0 3776
duke@0 3777 enc_class d2l_fixup(rRegL dst, regD src)
duke@0 3778 %{
duke@0 3779 int dstenc = $dst$$reg;
duke@0 3780 int srcenc = $src$$reg;
never@304 3781 address const_address = (address) StubRoutines::x86::double_sign_flip();
duke@0 3782
duke@0 3783 // cmpq $dst, [0x8000000000000000]
twisti@1668 3784 cbuf.set_insts_mark();
duke@0 3785 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 3786 emit_opcode(cbuf, 0x39);
duke@0 3787 // XXX reg_mem doesn't support RIP-relative addressing yet
duke@0 3788 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
duke@0 3789 emit_d32_reloc(cbuf, const_address);
duke@0 3790
duke@0 3791
duke@0 3792 // jne,s done
duke@0 3793 emit_opcode(cbuf, 0x75);
duke@0 3794 if (srcenc < 8 && dstenc < 8) {
duke@0 3795 emit_d8(cbuf, 0xF);
duke@0 3796 } else if (srcenc >= 8 && dstenc >= 8) {
duke@0 3797 emit_d8(cbuf, 0x11);
duke@0 3798 } else {
duke@0 3799 emit_d8(cbuf, 0x10);
duke@0 3800 }
duke@0 3801
duke@0 3802 // subq rsp, #8
duke@0 3803 emit_opcode(cbuf, Assembler::REX_W);
duke@0 3804 emit_opcode(cbuf, 0x83);
duke@0 3805 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
duke@0 3806 emit_d8(cbuf, 8);
duke@0 3807
duke@0 3808 // movsd [rsp], $src
duke@0 3809 emit_opcode(cbuf, 0xF2);
duke@0 3810 if (srcenc >= 8) {
duke@0 3811 emit_opcode(cbuf, Assembler::REX_R);
duke@0 3812 }
duke@0 3813 emit_opcode(cbuf, 0x0F);
duke@0 3814 emit_opcode(cbuf, 0x11);
duke@0 3815 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
duke@0 3816
duke@0 3817 // call d2l_fixup
twisti@1668 3818 cbuf.set_insts_mark();
duke@0 3819 emit_opcode(cbuf, 0xE8);
duke@0 3820 emit_d32_reloc(cbuf,
duke@0 3821 (int)
twisti@1668 3822 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4),
duke@0 3823 runtime_call_Relocation::spec(),
duke@0 3824 RELOC_DISP32);
duke@0 3825
duke@0 3826 // popq $dst
duke@0 3827 if (dstenc >= 8) {
duke@0 3828 emit_opcode(cbuf, Assembler::REX_B);
duke@0 3829 }
duke@0 3830 emit_opcode(cbuf, 0x58 | (dstenc & 7));
duke@0 3831
duke@0 3832 // done:
duke@0 3833 %}
duke@0 3834 %}
duke@0 3835
duke@0 3836
coleenp@113 3837
duke@0 3838 //----------FRAME--------------------------------------------------------------
duke@0 3839 // Definition of frame structure and management information.
duke@0 3840 //
duke@0 3841 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 3842 // | (to get allocators register number
duke@0 3843 // G Owned by | | v add OptoReg::stack0())
duke@0 3844 // r CALLER | |
duke@0 3845 // o | +--------+ pad to even-align allocators stack-slot
duke@0 3846 // w V | pad0 | numbers; owned by CALLER
duke@0 3847 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 3848 // h ^ | in | 5
duke@0 3849 // | | args | 4 Holes in incoming args owned by SELF
duke@0 3850 // | | | | 3
duke@0 3851 // | | +--------+
duke@0 3852 // V | | old out| Empty on Intel, window on Sparc
duke@0 3853 // | old |preserve| Must be even aligned.
duke@0 3854 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 3855 // | | in | 3 area for Intel ret address
duke@0 3856 // Owned by |preserve| Empty on Sparc.
duke@0 3857 // SELF +--------+
duke@0 3858 // | | pad2 | 2 pad to align old SP
duke@0 3859 // | +--------+ 1
duke@0 3860 // | | locks | 0
duke@0 3861 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 3862 // | | pad1 | 11 pad to align new SP
duke@0 3863 // | +--------+
duke@0 3864 // | | | 10
duke@0 3865 // | | spills | 9 spills
duke@0 3866 // V | | 8 (pad0 slot for callee)
duke@0 3867 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 3868 // ^ | out | 7
duke@0 3869 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 3870 // Owned by +--------+
duke@0 3871 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 3872 // | new |preserve| Must be even-aligned.
duke@0 3873 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 3874 // | | |
duke@0 3875 //
duke@0 3876 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 3877 // known from SELF's arguments and the Java calling convention.
duke@0 3878 // Region 6-7 is determined per call site.