annotate src/cpu/x86/vm/x86_64.ad @ 4438:e961c11b85fe

8011102: Clear AVX registers after return from JNI call Summary: Execute vzeroupper instruction after JNI call and on exits in jit compiled code which use 256bit vectors. Reviewed-by: roland
author kvn
date Wed, 03 Apr 2013 11:12:57 -0700
parents b30b3c2a0cf2
children 8be1318fbe77 a6e09d6dd8e5
rev   line source
duke@0 1 //
kvn@3142 2 // Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
trims@1472 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 // or visit www.oracle.com if you need additional information or have any
trims@1472 21 // questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // AMD64 Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31
duke@0 32 register %{
duke@0 33 //----------Architecture Description Register Definitions----------------------
duke@0 34 // General Registers
duke@0 35 // "reg_def" name ( register save type, C convention save type,
duke@0 36 // ideal register type, encoding );
duke@0 37 // Register Save Types:
duke@0 38 //
duke@0 39 // NS = No-Save: The register allocator assumes that these registers
duke@0 40 // can be used without saving upon entry to the method, &
duke@0 41 // that they do not need to be saved at call sites.
duke@0 42 //
duke@0 43 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 44 // can be used without saving upon entry to the method,
duke@0 45 // but that they must be saved at call sites.
duke@0 46 //
duke@0 47 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 48 // must be saved before using them upon entry to the
duke@0 49 // method, but they do not need to be saved at call
duke@0 50 // sites.
duke@0 51 //
duke@0 52 // AS = Always-Save: The register allocator assumes that these registers
duke@0 53 // must be saved before using them upon entry to the
duke@0 54 // method, & that they must be saved at call sites.
duke@0 55 //
duke@0 56 // Ideal Register Type is used to determine how to save & restore a
duke@0 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 59 //
duke@0 60 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 61
duke@0 62 // General Registers
duke@0 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
duke@0 64 // used as byte registers)
duke@0 65
duke@0 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
duke@0 67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
duke@0 68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
duke@0 69
duke@0 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
duke@0 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
duke@0 72
duke@0 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
duke@0 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
duke@0 75
duke@0 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
duke@0 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
duke@0 78
duke@0 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
duke@0 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
duke@0 81
duke@0 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
duke@0 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
duke@0 84
duke@0 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
duke@0 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
duke@0 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
duke@0 88
duke@0 89 #ifdef _WIN64
duke@0 90
duke@0 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
duke@0 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 93
duke@0 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
duke@0 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 96
duke@0 97 #else
duke@0 98
duke@0 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
duke@0 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
duke@0 101
duke@0 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
duke@0 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
duke@0 104
duke@0 105 #endif
duke@0 106
duke@0 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
duke@0 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
duke@0 109
duke@0 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
duke@0 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
duke@0 112
duke@0 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
duke@0 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
duke@0 115
duke@0 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
duke@0 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
duke@0 118
duke@0 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
duke@0 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
duke@0 121
duke@0 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
duke@0 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
duke@0 124
duke@0 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
duke@0 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
duke@0 127
duke@0 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
duke@0 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
duke@0 130
duke@0 131
duke@0 132 // Floating Point Registers
duke@0 133
duke@0 134 // Specify priority of register selection within phases of register
duke@0 135 // allocation. Highest priority is first. A useful heuristic is to
duke@0 136 // give registers a low priority when they are required by machine
duke@0 137 // instructions, like EAX and EDX on I486, and choose no-save registers
duke@0 138 // before save-on-call, & save-on-call before save-on-entry. Registers
duke@0 139 // which participate in fixed calling sequences should come last.
duke@0 140 // Registers which are used as pairs must fall on an even boundary.
duke@0 141
duke@0 142 alloc_class chunk0(R10, R10_H,
duke@0 143 R11, R11_H,
duke@0 144 R8, R8_H,
duke@0 145 R9, R9_H,
duke@0 146 R12, R12_H,
duke@0 147 RCX, RCX_H,
duke@0 148 RBX, RBX_H,
duke@0 149 RDI, RDI_H,
duke@0 150 RDX, RDX_H,
duke@0 151 RSI, RSI_H,
duke@0 152 RAX, RAX_H,
duke@0 153 RBP, RBP_H,
duke@0 154 R13, R13_H,
duke@0 155 R14, R14_H,
duke@0 156 R15, R15_H,
duke@0 157 RSP, RSP_H);
duke@0 158
duke@0 159
duke@0 160 //----------Architecture Description Register Classes--------------------------
duke@0 161 // Several register classes are automatically defined based upon information in
duke@0 162 // this architecture description.
duke@0 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
duke@0 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
duke@0 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
duke@0 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 167 //
duke@0 168
duke@0 169 // Class for all pointer registers (including RSP)
duke@0 170 reg_class any_reg(RAX, RAX_H,
duke@0 171 RDX, RDX_H,
duke@0 172 RBP, RBP_H,
duke@0 173 RDI, RDI_H,
duke@0 174 RSI, RSI_H,
duke@0 175 RCX, RCX_H,
duke@0 176 RBX, RBX_H,
duke@0 177 RSP, RSP_H,
duke@0 178 R8, R8_H,
duke@0 179 R9, R9_H,
duke@0 180 R10, R10_H,
duke@0 181 R11, R11_H,
duke@0 182 R12, R12_H,
duke@0 183 R13, R13_H,
duke@0 184 R14, R14_H,
duke@0 185 R15, R15_H);
duke@0 186
duke@0 187 // Class for all pointer registers except RSP
duke@0 188 reg_class ptr_reg(RAX, RAX_H,
duke@0 189 RDX, RDX_H,
duke@0 190 RBP, RBP_H,
duke@0 191 RDI, RDI_H,
duke@0 192 RSI, RSI_H,
duke@0 193 RCX, RCX_H,
duke@0 194 RBX, RBX_H,
duke@0 195 R8, R8_H,
duke@0 196 R9, R9_H,
duke@0 197 R10, R10_H,
duke@0 198 R11, R11_H,
duke@0 199 R13, R13_H,
duke@0 200 R14, R14_H);
duke@0 201
duke@0 202 // Class for all pointer registers except RAX and RSP
duke@0 203 reg_class ptr_no_rax_reg(RDX, RDX_H,
duke@0 204 RBP, RBP_H,
duke@0 205 RDI, RDI_H,
duke@0 206 RSI, RSI_H,
duke@0 207 RCX, RCX_H,
duke@0 208 RBX, RBX_H,
duke@0 209 R8, R8_H,
duke@0 210 R9, R9_H,
duke@0 211 R10, R10_H,
duke@0 212 R11, R11_H,
duke@0 213 R13, R13_H,
duke@0 214 R14, R14_H);
duke@0 215
duke@0 216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
duke@0 217 RAX, RAX_H,
duke@0 218 RDI, RDI_H,
duke@0 219 RSI, RSI_H,
duke@0 220 RCX, RCX_H,
duke@0 221 RBX, RBX_H,
duke@0 222 R8, R8_H,
duke@0 223 R9, R9_H,
duke@0 224 R10, R10_H,
duke@0 225 R11, R11_H,
duke@0 226 R13, R13_H,
duke@0 227 R14, R14_H);
duke@0 228
duke@0 229 // Class for all pointer registers except RAX, RBX and RSP
duke@0 230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
duke@0 231 RBP, RBP_H,
duke@0 232 RDI, RDI_H,
duke@0 233 RSI, RSI_H,
duke@0 234 RCX, RCX_H,
duke@0 235 R8, R8_H,
duke@0 236 R9, R9_H,
duke@0 237 R10, R10_H,
duke@0 238 R11, R11_H,
duke@0 239 R13, R13_H,
duke@0 240 R14, R14_H);
duke@0 241
duke@0 242 // Singleton class for RAX pointer register
duke@0 243 reg_class ptr_rax_reg(RAX, RAX_H);
duke@0 244
duke@0 245 // Singleton class for RBX pointer register
duke@0 246 reg_class ptr_rbx_reg(RBX, RBX_H);
duke@0 247
duke@0 248 // Singleton class for RSI pointer register
duke@0 249 reg_class ptr_rsi_reg(RSI, RSI_H);
duke@0 250
duke@0 251 // Singleton class for RDI pointer register
duke@0 252 reg_class ptr_rdi_reg(RDI, RDI_H);
duke@0 253
duke@0 254 // Singleton class for RBP pointer register
duke@0 255 reg_class ptr_rbp_reg(RBP, RBP_H);
duke@0 256
duke@0 257 // Singleton class for stack pointer
duke@0 258 reg_class ptr_rsp_reg(RSP, RSP_H);
duke@0 259
duke@0 260 // Singleton class for TLS pointer
duke@0 261 reg_class ptr_r15_reg(R15, R15_H);
duke@0 262
duke@0 263 // Class for all long registers (except RSP)
duke@0 264 reg_class long_reg(RAX, RAX_H,
duke@0 265 RDX, RDX_H,
duke@0 266 RBP, RBP_H,
duke@0 267 RDI, RDI_H,
duke@0 268 RSI, RSI_H,
duke@0 269 RCX, RCX_H,
duke@0 270 RBX, RBX_H,
duke@0 271 R8, R8_H,
duke@0 272 R9, R9_H,
duke@0 273 R10, R10_H,
duke@0 274 R11, R11_H,
duke@0 275 R13, R13_H,
duke@0 276 R14, R14_H);
duke@0 277
duke@0 278 // Class for all long registers except RAX, RDX (and RSP)
duke@0 279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
duke@0 280 RDI, RDI_H,
duke@0 281 RSI, RSI_H,
duke@0 282 RCX, RCX_H,
duke@0 283 RBX, RBX_H,
duke@0 284 R8, R8_H,
duke@0 285 R9, R9_H,
duke@0 286 R10, R10_H,
duke@0 287 R11, R11_H,
duke@0 288 R13, R13_H,
duke@0 289 R14, R14_H);
duke@0 290
duke@0 291 // Class for all long registers except RCX (and RSP)
duke@0 292 reg_class long_no_rcx_reg(RBP, RBP_H,
duke@0 293 RDI, RDI_H,
duke@0 294 RSI, RSI_H,
duke@0 295 RAX, RAX_H,
duke@0 296 RDX, RDX_H,
duke@0 297 RBX, RBX_H,
duke@0 298 R8, R8_H,
duke@0 299 R9, R9_H,
duke@0 300 R10, R10_H,
duke@0 301 R11, R11_H,
duke@0 302 R13, R13_H,
duke@0 303 R14, R14_H);
duke@0 304
duke@0 305 // Class for all long registers except RAX (and RSP)
duke@0 306 reg_class long_no_rax_reg(RBP, RBP_H,
duke@0 307 RDX, RDX_H,
duke@0 308 RDI, RDI_H,
duke@0 309 RSI, RSI_H,
duke@0 310 RCX, RCX_H,
duke@0 311 RBX, RBX_H,
duke@0 312 R8, R8_H,
duke@0 313 R9, R9_H,
duke@0 314 R10, R10_H,
duke@0 315 R11, R11_H,
duke@0 316 R13, R13_H,
duke@0 317 R14, R14_H);
duke@0 318
duke@0 319 // Singleton class for RAX long register
duke@0 320 reg_class long_rax_reg(RAX, RAX_H);
duke@0 321
duke@0 322 // Singleton class for RCX long register
duke@0 323 reg_class long_rcx_reg(RCX, RCX_H);
duke@0 324
duke@0 325 // Singleton class for RDX long register
duke@0 326 reg_class long_rdx_reg(RDX, RDX_H);
duke@0 327
duke@0 328 // Class for all int registers (except RSP)
duke@0 329 reg_class int_reg(RAX,
duke@0 330 RDX,
duke@0 331 RBP,
duke@0 332 RDI,
duke@0 333 RSI,
duke@0 334 RCX,
duke@0 335 RBX,
duke@0 336 R8,
duke@0 337 R9,
duke@0 338 R10,
duke@0 339 R11,
duke@0 340 R13,
duke@0 341 R14);
duke@0 342
duke@0 343 // Class for all int registers except RCX (and RSP)
duke@0 344 reg_class int_no_rcx_reg(RAX,
duke@0 345 RDX,
duke@0 346 RBP,
duke@0 347 RDI,
duke@0 348 RSI,
duke@0 349 RBX,
duke@0 350 R8,
duke@0 351 R9,
duke@0 352 R10,
duke@0 353 R11,
duke@0 354 R13,
duke@0 355 R14);
duke@0 356
duke@0 357 // Class for all int registers except RAX, RDX (and RSP)
duke@0 358 reg_class int_no_rax_rdx_reg(RBP,
never@304 359 RDI,
duke@0 360 RSI,
duke@0 361 RCX,
duke@0 362 RBX,
duke@0 363 R8,
duke@0 364 R9,
duke@0 365 R10,
duke@0 366 R11,
duke@0 367 R13,
duke@0 368 R14);
duke@0 369
duke@0 370 // Singleton class for RAX int register
duke@0 371 reg_class int_rax_reg(RAX);
duke@0 372
duke@0 373 // Singleton class for RBX int register
duke@0 374 reg_class int_rbx_reg(RBX);
duke@0 375
duke@0 376 // Singleton class for RCX int register
duke@0 377 reg_class int_rcx_reg(RCX);
duke@0 378
duke@0 379 // Singleton class for RCX int register
duke@0 380 reg_class int_rdx_reg(RDX);
duke@0 381
duke@0 382 // Singleton class for RCX int register
duke@0 383 reg_class int_rdi_reg(RDI);
duke@0 384
duke@0 385 // Singleton class for instruction pointer
duke@0 386 // reg_class ip_reg(RIP);
duke@0 387
kvn@3447 388 %}
duke@0 389
duke@0 390 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 391 // This is a block of C++ code which provides values, functions, and
duke@0 392 // definitions necessary in the rest of the architecture description
duke@0 393 source %{
never@304 394 #define RELOC_IMM64 Assembler::imm_operand
duke@0 395 #define RELOC_DISP32 Assembler::disp32_operand
duke@0 396
duke@0 397 #define __ _masm.
duke@0 398
twisti@1137 399 static int preserve_SP_size() {
kvn@2953 400 return 3; // rex.w, op, rm(reg/reg)
twisti@1137 401 }
kvn@4438 402 static int clear_avx_size() {
kvn@4438 403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
kvn@4438 404 }
twisti@1137 405
duke@0 406 // !!!!! Special hack to get all types of calls to specify the byte offset
duke@0 407 // from the start of the call to the point where the return address
duke@0 408 // will point.
duke@0 409 int MachCallStaticJavaNode::ret_addr_offset()
duke@0 410 {
twisti@1137 411 int offset = 5; // 5 bytes from start of call to where return address points
kvn@4438 412 offset += clear_avx_size();
twisti@1137 413 if (_method_handle_invoke)
twisti@1137 414 offset += preserve_SP_size();
twisti@1137 415 return offset;
duke@0 416 }
duke@0 417
duke@0 418 int MachCallDynamicJavaNode::ret_addr_offset()
duke@0 419 {
kvn@4438 420 int offset = 15; // 15 bytes from start of call to where return address points
kvn@4438 421 offset += clear_avx_size();
kvn@4438 422 return offset;
duke@0 423 }
duke@0 424
kvn@4438 425 int MachCallRuntimeNode::ret_addr_offset() {
kvn@4438 426 int offset = 13; // movq r10,#addr; callq (r10)
kvn@4438 427 offset += clear_avx_size();
kvn@4438 428 return offset;
kvn@4438 429 }
duke@0 430
iveresov@2251 431 // Indicate if the safepoint node needs the polling page as an input,
iveresov@2251 432 // it does if the polling page is more than disp32 away.
duke@0 433 bool SafePointNode::needs_polling_address_input()
duke@0 434 {
iveresov@2251 435 return Assembler::is_polling_page_far();
duke@0 436 }
duke@0 437
duke@0 438 //
duke@0 439 // Compute padding required for nodes which need alignment
duke@0 440 //
duke@0 441
duke@0 442 // The address of the call instruction needs to be 4-byte aligned to
duke@0 443 // ensure that it does not span a cache line so that it can be patched.
duke@0 444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
duke@0 445 {
kvn@4438 446 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 447 current_offset += 1; // skip call opcode byte
duke@0 448 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 449 }
duke@0 450
duke@0 451 // The address of the call instruction needs to be 4-byte aligned to
duke@0 452 // ensure that it does not span a cache line so that it can be patched.
twisti@1137 453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
twisti@1137 454 {
twisti@1137 455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
kvn@4438 456 current_offset += clear_avx_size(); // skip vzeroupper
twisti@1137 457 current_offset += 1; // skip call opcode byte
twisti@1137 458 return round_to(current_offset, alignment_required()) - current_offset;
twisti@1137 459 }
twisti@1137 460
twisti@1137 461 // The address of the call instruction needs to be 4-byte aligned to
twisti@1137 462 // ensure that it does not span a cache line so that it can be patched.
duke@0 463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
duke@0 464 {
kvn@4438 465 current_offset += clear_avx_size(); // skip vzeroupper
duke@0 466 current_offset += 11; // skip movq instruction + call opcode byte
duke@0 467 return round_to(current_offset, alignment_required()) - current_offset;
duke@0 468 }
duke@0 469
duke@0 470 // EMIT_RM()
twisti@1668 471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
duke@0 472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
twisti@1668 473 cbuf.insts()->emit_int8(c);
duke@0 474 }
duke@0 475
duke@0 476 // EMIT_CC()
twisti@1668 477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
duke@0 478 unsigned char c = (unsigned char) (f1 | f2);
twisti@1668 479 cbuf.insts()->emit_int8(c);
duke@0 480 }
duke@0 481
duke@0 482 // EMIT_OPCODE()
twisti@1668 483 void emit_opcode(CodeBuffer &cbuf, int code) {
twisti@1668 484 cbuf.insts()->emit_int8((unsigned char) code);
duke@0 485 }
duke@0 486
duke@0 487 // EMIT_OPCODE() w/ relocation information
duke@0 488 void emit_opcode(CodeBuffer &cbuf,
duke@0 489 int code, relocInfo::relocType reloc, int offset, int format)
duke@0 490 {
twisti@1668 491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
duke@0 492 emit_opcode(cbuf, code);
duke@0 493 }
duke@0 494
duke@0 495 // EMIT_D8()
twisti@1668 496 void emit_d8(CodeBuffer &cbuf, int d8) {
twisti@1668 497 cbuf.insts()->emit_int8((unsigned char) d8);
duke@0 498 }
duke@0 499
duke@0 500 // EMIT_D16()
twisti@1668 501 void emit_d16(CodeBuffer &cbuf, int d16) {
twisti@1668 502 cbuf.insts()->emit_int16(d16);
duke@0 503 }
duke@0 504
duke@0 505 // EMIT_D32()
twisti@1668 506 void emit_d32(CodeBuffer &cbuf, int d32) {
twisti@1668 507 cbuf.insts()->emit_int32(d32);
duke@0 508 }
duke@0 509
duke@0 510 // EMIT_D64()
twisti@1668 511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
twisti@1668 512 cbuf.insts()->emit_int64(d64);
duke@0 513 }
duke@0 514
duke@0 515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
duke@0 516 void emit_d32_reloc(CodeBuffer& cbuf,
duke@0 517 int d32,
duke@0 518 relocInfo::relocType reloc,
duke@0 519 int format)
duke@0 520 {
duke@0 521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
twisti@1668 522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 523 cbuf.insts()->emit_int32(d32);
duke@0 524 }
duke@0 525
duke@0 526 // emit 32 bit value and construct relocation entry from RelocationHolder
twisti@1668 527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
duke@0 528 #ifdef ASSERT
duke@0 529 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
coleenp@3602 531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
jrose@989 532 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
duke@0 533 }
duke@0 534 #endif
twisti@1668 535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 536 cbuf.insts()->emit_int32(d32);
duke@0 537 }
duke@0 538
duke@0 539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
twisti@1668 540 address next_ip = cbuf.insts_end() + 4;
duke@0 541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
duke@0 542 external_word_Relocation::spec(addr),
duke@0 543 RELOC_DISP32);
duke@0 544 }
duke@0 545
duke@0 546
duke@0 547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
twisti@1668 548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
twisti@1668 549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
twisti@1668 550 cbuf.insts()->emit_int64(d64);
duke@0 551 }
duke@0 552
duke@0 553 // emit 64 bit value and construct relocation entry from RelocationHolder
twisti@1668 554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
duke@0 555 #ifdef ASSERT
duke@0 556 if (rspec.reloc()->type() == relocInfo::oop_type &&
duke@0 557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
coleenp@3602 558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
jrose@989 559 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
jrose@989 560 "cannot embed scavengable oops in code");
duke@0 561 }
duke@0 562 #endif
twisti@1668 563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
twisti@1668 564 cbuf.insts()->emit_int64(d64);
duke@0 565 }
duke@0 566
duke@0 567 // Access stack slot for load or store
duke@0 568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
duke@0 569 {
duke@0 570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
duke@0 571 if (-0x80 <= disp && disp < 0x80) {
duke@0 572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
duke@0 573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 574 emit_d8(cbuf, disp); // Displacement // R/M byte
duke@0 575 } else {
duke@0 576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
duke@0 577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
duke@0 578 emit_d32(cbuf, disp); // Displacement // R/M byte
duke@0 579 }
duke@0 580 }
duke@0 581
duke@0 582 // rRegI ereg, memory mem) %{ // emit_reg_mem
duke@0 583 void encode_RegMem(CodeBuffer &cbuf,
duke@0 584 int reg,
coleenp@3602 585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
duke@0 586 {
coleenp@3602 587 assert(disp_reloc == relocInfo::none, "cannot have disp");
duke@0 588 int regenc = reg & 7;
duke@0 589 int baseenc = base & 7;
duke@0 590 int indexenc = index & 7;
duke@0 591
duke@0 592 // There is no index & no scale, use form without SIB byte
duke@0 593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
duke@0 594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
coleenp@3602 597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 598 // If 8-bit displacement, mode 0x1
duke@0 599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
duke@0 600 emit_d8(cbuf, disp);
duke@0 601 } else {
duke@0 602 // If 32-bit displacement
duke@0 603 if (base == -1) { // Special flag for absolute address
duke@0 604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
coleenp@3602 605 if (disp_reloc != relocInfo::none) {
duke@0 606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 607 } else {
duke@0 608 emit_d32(cbuf, disp);
duke@0 609 }
duke@0 610 } else {
duke@0 611 // Normal base + offset
duke@0 612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
coleenp@3602 613 if (disp_reloc != relocInfo::none) {
duke@0 614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 615 } else {
duke@0 616 emit_d32(cbuf, disp);
duke@0 617 }
duke@0 618 }
duke@0 619 }
duke@0 620 } else {
duke@0 621 // Else, encode with the SIB byte
duke@0 622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
duke@0 623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
duke@0 624 // If no displacement
duke@0 625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
duke@0 626 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 627 } else {
coleenp@3602 628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
duke@0 629 // If 8-bit displacement, mode 0x1
duke@0 630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
duke@0 631 emit_rm(cbuf, scale, indexenc, baseenc);
duke@0 632 emit_d8(cbuf, disp);
duke@0 633 } else {
duke@0 634 // If 32-bit displacement
duke@0 635 if (base == 0x04 ) {
duke@0 636 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
duke@0 638 } else {
duke@0 639 emit_rm(cbuf, 0x2, regenc, 0x4);
duke@0 640 emit_rm(cbuf, scale, indexenc, baseenc); // *
duke@0 641 }
coleenp@3602 642 if (disp_reloc != relocInfo::none) {
duke@0 643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
duke@0 644 } else {
duke@0 645 emit_d32(cbuf, disp);
duke@0 646 }
duke@0 647 }
duke@0 648 }
duke@0 649 }
duke@0 650 }
duke@0 651
never@2545 652 // This could be in MacroAssembler but it's fairly C2 specific
never@2545 653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
never@2545 654 Label exit;
never@2545 655 __ jccb(Assembler::noParity, exit);
never@2545 656 __ pushf();
kvn@2953 657 //
kvn@2953 658 // comiss/ucomiss instructions set ZF,PF,CF flags and
kvn@2953 659 // zero OF,AF,SF for NaN values.
kvn@2953 660 // Fixup flags by zeroing ZF,PF so that compare of NaN
kvn@2953 661 // values returns 'less than' result (CF is set).
kvn@2953 662 // Leave the rest of flags unchanged.
kvn@2953 663 //
kvn@2953 664 // 7 6 5 4 3 2 1 0
kvn@2953 665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
kvn@2953 666 // 0 0 1 0 1 0 1 1 (0x2B)
kvn@2953 667 //
never@2545 668 __ andq(Address(rsp, 0), 0xffffff2b);
never@2545 669 __ popf();
never@2545 670 __ bind(exit);
kvn@2953 671 }
kvn@2953 672
kvn@2953 673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
kvn@2953 674 Label done;
kvn@2953 675 __ movl(dst, -1);
kvn@2953 676 __ jcc(Assembler::parity, done);
kvn@2953 677 __ jcc(Assembler::below, done);
kvn@2953 678 __ setb(Assembler::notEqual, dst);
kvn@2953 679 __ movzbl(dst, dst);
kvn@2953 680 __ bind(done);
never@2545 681 }
never@2545 682
duke@0 683
duke@0 684 //=============================================================================
twisti@1915 685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
twisti@1915 686
twisti@2875 687 int Compile::ConstantTable::calculate_table_base_offset() const {
twisti@2875 688 return 0; // absolute addressing, no offset
twisti@2875 689 }
twisti@2875 690
twisti@1915 691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
twisti@1915 692 // Empty encoding
twisti@1915 693 }
twisti@1915 694
twisti@1915 695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
twisti@1915 696 return 0;
twisti@1915 697 }
twisti@1915 698
twisti@1915 699 #ifndef PRODUCT
twisti@1915 700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
twisti@1915 701 st->print("# MachConstantBaseNode (empty encoding)");
twisti@1915 702 }
twisti@1915 703 #endif
twisti@1915 704
twisti@1915 705
twisti@1915 706 //=============================================================================
duke@0 707 #ifndef PRODUCT
kvn@3139 708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
duke@0 709 Compile* C = ra_->C;
duke@0 710
duke@0 711 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
kvn@3139 713 // Remove wordSize for return addr which is already pushed.
kvn@3139 714 framesize -= wordSize;
kvn@3139 715
duke@0 716 if (C->need_stack_bang(framesize)) {
kvn@3139 717 framesize -= wordSize;
kvn@3139 718 st->print("# stack bang");
kvn@3139 719 st->print("\n\t");
kvn@3139 720 st->print("pushq rbp\t# Save rbp");
kvn@3139 721 if (framesize) {
kvn@3139 722 st->print("\n\t");
kvn@3139 723 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 724 }
kvn@3139 725 } else {
kvn@3139 726 st->print("subq rsp, #%d\t# Create frame",framesize);
kvn@3139 727 st->print("\n\t");
kvn@3139 728 framesize -= wordSize;
kvn@3139 729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
duke@0 730 }
duke@0 731
duke@0 732 if (VerifyStackAtCalls) {
kvn@3139 733 st->print("\n\t");
kvn@3139 734 framesize -= wordSize;
kvn@3139 735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
kvn@3139 736 #ifdef ASSERT
kvn@3139 737 st->print("\n\t");
kvn@3139 738 st->print("# stack alignment check");
kvn@3139 739 #endif
duke@0 740 }
kvn@3139 741 st->cr();
duke@0 742 }
duke@0 743 #endif
duke@0 744
kvn@3139 745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 746 Compile* C = ra_->C;
kvn@3139 747 MacroAssembler _masm(&cbuf);
duke@0 748
duke@0 749 int framesize = C->frame_slots() << LogBytesPerInt;
kvn@3139 750
kvn@3139 751 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
duke@0 752
twisti@1668 753 C->set_frame_complete(cbuf.insts_size());
duke@0 754
twisti@2875 755 if (C->has_mach_constant_base_node()) {
twisti@2875 756 // NOTE: We set the table base offset here because users might be
twisti@2875 757 // emitted before MachConstantBaseNode.
twisti@2875 758 Compile::ConstantTable& constant_table = C->constant_table();
twisti@2875 759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
twisti@2875 760 }
duke@0 761 }
duke@0 762
duke@0 763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
duke@0 764 {
duke@0 765 return MachNode::size(ra_); // too many variables; just compute it
duke@0 766 // the hard way
duke@0 767 }
duke@0 768
duke@0 769 int MachPrologNode::reloc() const
duke@0 770 {
duke@0 771 return 0; // a large enough number
duke@0 772 }
duke@0 773
duke@0 774 //=============================================================================
duke@0 775 #ifndef PRODUCT
duke@0 776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 777 {
duke@0 778 Compile* C = ra_->C;
kvn@4438 779 if (C->max_vector_size() > 16) {
kvn@4438 780 st->print("vzeroupper");
kvn@4438 781 st->cr(); st->print("\t");
kvn@4438 782 }
kvn@4438 783
duke@0 784 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 786 // Remove word for return adr already pushed
duke@0 787 // and RBP
duke@0 788 framesize -= 2*wordSize;
duke@0 789
duke@0 790 if (framesize) {
iveresov@2251 791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
duke@0 792 st->print("\t");
duke@0 793 }
duke@0 794
iveresov@2251 795 st->print_cr("popq rbp");
duke@0 796 if (do_polling() && C->is_method_compilation()) {
duke@0 797 st->print("\t");
iveresov@2251 798 if (Assembler::is_polling_page_far()) {
iveresov@2251 799 st->print_cr("movq rscratch1, #polling_page_address\n\t"
iveresov@2251 800 "testl rax, [rscratch1]\t"
iveresov@2251 801 "# Safepoint: poll for GC");
iveresov@2251 802 } else {
iveresov@2251 803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
iveresov@2251 804 "# Safepoint: poll for GC");
iveresov@2251 805 }
duke@0 806 }
duke@0 807 }
duke@0 808 #endif
duke@0 809
duke@0 810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 811 {
duke@0 812 Compile* C = ra_->C;
kvn@4438 813 if (C->max_vector_size() > 16) {
kvn@4438 814 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 815 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 816 MacroAssembler _masm(&cbuf);
kvn@4438 817 __ vzeroupper();
kvn@4438 818 }
kvn@4438 819
duke@0 820 int framesize = C->frame_slots() << LogBytesPerInt;
duke@0 821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
duke@0 822 // Remove word for return adr already pushed
duke@0 823 // and RBP
duke@0 824 framesize -= 2*wordSize;
duke@0 825
duke@0 826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
duke@0 827
duke@0 828 if (framesize) {
duke@0 829 emit_opcode(cbuf, Assembler::REX_W);
duke@0 830 if (framesize < 0x80) {
duke@0 831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
duke@0 832 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 833 emit_d8(cbuf, framesize);
duke@0 834 } else {
duke@0 835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
duke@0 836 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
duke@0 837 emit_d32(cbuf, framesize);
duke@0 838 }
duke@0 839 }
duke@0 840
duke@0 841 // popq rbp
duke@0 842 emit_opcode(cbuf, 0x58 | RBP_enc);
duke@0 843
duke@0 844 if (do_polling() && C->is_method_compilation()) {
iveresov@2251 845 MacroAssembler _masm(&cbuf);
iveresov@2251 846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
iveresov@2251 847 if (Assembler::is_polling_page_far()) {
iveresov@2251 848 __ lea(rscratch1, polling_page);
iveresov@2251 849 __ relocate(relocInfo::poll_return_type);
iveresov@2251 850 __ testl(rax, Address(rscratch1, 0));
iveresov@2251 851 } else {
iveresov@2251 852 __ testl(rax, polling_page);
iveresov@2251 853 }
duke@0 854 }
duke@0 855 }
duke@0 856
duke@0 857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
duke@0 858 {
iveresov@2251 859 return MachNode::size(ra_); // too many variables; just compute it
iveresov@2251 860 // the hard way
duke@0 861 }
duke@0 862
duke@0 863 int MachEpilogNode::reloc() const
duke@0 864 {
duke@0 865 return 2; // a large enough number
duke@0 866 }
duke@0 867
duke@0 868 const Pipeline* MachEpilogNode::pipeline() const
duke@0 869 {
duke@0 870 return MachNode::pipeline_class();
duke@0 871 }
duke@0 872
duke@0 873 int MachEpilogNode::safepoint_offset() const
duke@0 874 {
duke@0 875 return 0;
duke@0 876 }
duke@0 877
duke@0 878 //=============================================================================
duke@0 879
duke@0 880 enum RC {
duke@0 881 rc_bad,
duke@0 882 rc_int,
duke@0 883 rc_float,
duke@0 884 rc_stack
duke@0 885 };
duke@0 886
duke@0 887 static enum RC rc_class(OptoReg::Name reg)
duke@0 888 {
duke@0 889 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 890
duke@0 891 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 892
duke@0 893 VMReg r = OptoReg::as_VMReg(reg);
duke@0 894
duke@0 895 if (r->is_Register()) return rc_int;
duke@0 896
duke@0 897 assert(r->is_XMMRegister(), "must be");
duke@0 898 return rc_float;
duke@0 899 }
duke@0 900
kvn@3447 901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
kvn@3447 902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
kvn@3447 903 int src_hi, int dst_hi, uint ireg, outputStream* st);
kvn@3447 904
kvn@3447 905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
kvn@3447 906 int stack_offset, int reg, uint ireg, outputStream* st);
kvn@3447 907
kvn@3447 908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
kvn@3447 909 int dst_offset, uint ireg, outputStream* st) {
kvn@3447 910 if (cbuf) {
kvn@3447 911 MacroAssembler _masm(cbuf);
kvn@3447 912 switch (ireg) {
kvn@3447 913 case Op_VecS:
kvn@3447 914 __ movq(Address(rsp, -8), rax);
kvn@3447 915 __ movl(rax, Address(rsp, src_offset));
kvn@3447 916 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 917 __ movq(rax, Address(rsp, -8));
kvn@3447 918 break;
kvn@3447 919 case Op_VecD:
kvn@3447 920 __ pushq(Address(rsp, src_offset));
kvn@3447 921 __ popq (Address(rsp, dst_offset));
kvn@3447 922 break;
kvn@3447 923 case Op_VecX:
kvn@3447 924 __ pushq(Address(rsp, src_offset));
kvn@3447 925 __ popq (Address(rsp, dst_offset));
kvn@3447 926 __ pushq(Address(rsp, src_offset+8));
kvn@3447 927 __ popq (Address(rsp, dst_offset+8));
kvn@3447 928 break;
kvn@3447 929 case Op_VecY:
kvn@3447 930 __ vmovdqu(Address(rsp, -32), xmm0);
kvn@3447 931 __ vmovdqu(xmm0, Address(rsp, src_offset));
kvn@3447 932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
kvn@3447 933 __ vmovdqu(xmm0, Address(rsp, -32));
kvn@3447 934 break;
kvn@3447 935 default:
kvn@3447 936 ShouldNotReachHere();
kvn@3447 937 }
kvn@3447 938 #ifndef PRODUCT
kvn@3447 939 } else {
kvn@3447 940 switch (ireg) {
kvn@3447 941 case Op_VecS:
kvn@3447 942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 943 "movl rax, [rsp + #%d]\n\t"
kvn@3447 944 "movl [rsp + #%d], rax\n\t"
kvn@3447 945 "movq rax, [rsp - #8]",
kvn@3447 946 src_offset, dst_offset);
kvn@3447 947 break;
kvn@3447 948 case Op_VecD:
kvn@3447 949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 950 "popq [rsp + #%d]",
kvn@3447 951 src_offset, dst_offset);
kvn@3447 952 break;
kvn@3447 953 case Op_VecX:
kvn@3447 954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
kvn@3447 955 "popq [rsp + #%d]\n\t"
kvn@3447 956 "pushq [rsp + #%d]\n\t"
kvn@3447 957 "popq [rsp + #%d]",
kvn@3447 958 src_offset, dst_offset, src_offset+8, dst_offset+8);
kvn@3447 959 break;
kvn@3447 960 case Op_VecY:
kvn@3447 961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
kvn@3447 962 "vmovdqu xmm0, [rsp + #%d]\n\t"
kvn@3447 963 "vmovdqu [rsp + #%d], xmm0\n\t"
kvn@3447 964 "vmovdqu xmm0, [rsp - #32]",
kvn@3447 965 src_offset, dst_offset);
kvn@3447 966 break;
kvn@3447 967 default:
kvn@3447 968 ShouldNotReachHere();
kvn@3447 969 }
kvn@3447 970 #endif
kvn@3447 971 }
kvn@3447 972 }
kvn@3447 973
duke@0 974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
duke@0 975 PhaseRegAlloc* ra_,
duke@0 976 bool do_size,
kvn@3447 977 outputStream* st) const {
kvn@3447 978 assert(cbuf != NULL || st != NULL, "sanity");
duke@0 979 // Get registers to move
duke@0 980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 982 OptoReg::Name dst_second = ra_->get_reg_second(this);
duke@0 983 OptoReg::Name dst_first = ra_->get_reg_first(this);
duke@0 984
duke@0 985 enum RC src_second_rc = rc_class(src_second);
duke@0 986 enum RC src_first_rc = rc_class(src_first);
duke@0 987 enum RC dst_second_rc = rc_class(dst_second);
duke@0 988 enum RC dst_first_rc = rc_class(dst_first);
duke@0 989
duke@0 990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
duke@0 991 "must move at least 1 register" );
duke@0 992
duke@0 993 if (src_first == dst_first && src_second == dst_second) {
duke@0 994 // Self copy, no move
duke@0 995 return 0;
kvn@3447 996 }
kvn@3447 997 if (bottom_type()->isa_vect() != NULL) {
kvn@3447 998 uint ireg = ideal_reg();
kvn@3447 999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
kvn@3447 1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
kvn@3447 1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
kvn@3447 1002 // mem -> mem
kvn@3447 1003 int src_offset = ra_->reg2offset(src_first);
kvn@3447 1004 int dst_offset = ra_->reg2offset(dst_first);
kvn@3447 1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
kvn@3447 1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
kvn@3447 1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
kvn@3447 1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
kvn@3447 1009 int stack_offset = ra_->reg2offset(dst_first);
kvn@3447 1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
kvn@3447 1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
kvn@3447 1012 int stack_offset = ra_->reg2offset(src_first);
kvn@3447 1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
kvn@3447 1014 } else {
kvn@3447 1015 ShouldNotReachHere();
kvn@3447 1016 }
kvn@3447 1017 return 0;
kvn@3447 1018 }
kvn@3447 1019 if (src_first_rc == rc_stack) {
duke@0 1020 // mem ->
duke@0 1021 if (dst_first_rc == rc_stack) {
duke@0 1022 // mem -> mem
duke@0 1023 assert(src_second != dst_first, "overlap");
duke@0 1024 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1026 // 64-bit
duke@0 1027 int src_offset = ra_->reg2offset(src_first);
duke@0 1028 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1029 if (cbuf) {
kvn@3447 1030 MacroAssembler _masm(cbuf);
kvn@3447 1031 __ pushq(Address(rsp, src_offset));
kvn@3447 1032 __ popq (Address(rsp, dst_offset));
duke@0 1033 #ifndef PRODUCT
kvn@3447 1034 } else {
duke@0 1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
kvn@3447 1036 "popq [rsp + #%d]",
kvn@3447 1037 src_offset, dst_offset);
duke@0 1038 #endif
duke@0 1039 }
duke@0 1040 } else {
duke@0 1041 // 32-bit
duke@0 1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1044 // No pushl/popl, so:
duke@0 1045 int src_offset = ra_->reg2offset(src_first);
duke@0 1046 int dst_offset = ra_->reg2offset(dst_first);
duke@0 1047 if (cbuf) {
kvn@3447 1048 MacroAssembler _masm(cbuf);
kvn@3447 1049 __ movq(Address(rsp, -8), rax);
kvn@3447 1050 __ movl(rax, Address(rsp, src_offset));
kvn@3447 1051 __ movl(Address(rsp, dst_offset), rax);
kvn@3447 1052 __ movq(rax, Address(rsp, -8));
duke@0 1053 #ifndef PRODUCT
kvn@3447 1054 } else {
duke@0 1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
kvn@3447 1056 "movl rax, [rsp + #%d]\n\t"
kvn@3447 1057 "movl [rsp + #%d], rax\n\t"
kvn@3447 1058 "movq rax, [rsp - #8]",
kvn@3447 1059 src_offset, dst_offset);
duke@0 1060 #endif
duke@0 1061 }
duke@0 1062 }
kvn@3447 1063 return 0;
duke@0 1064 } else if (dst_first_rc == rc_int) {
duke@0 1065 // mem -> gpr
duke@0 1066 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1068 // 64-bit
duke@0 1069 int offset = ra_->reg2offset(src_first);
duke@0 1070 if (cbuf) {
kvn@3447 1071 MacroAssembler _masm(cbuf);
kvn@3447 1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1073 #ifndef PRODUCT
kvn@3447 1074 } else {
duke@0 1075 st->print("movq %s, [rsp + #%d]\t# spill",
duke@0 1076 Matcher::regName[dst_first],
duke@0 1077 offset);
duke@0 1078 #endif
duke@0 1079 }
duke@0 1080 } else {
duke@0 1081 // 32-bit
duke@0 1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1084 int offset = ra_->reg2offset(src_first);
duke@0 1085 if (cbuf) {
kvn@3447 1086 MacroAssembler _masm(cbuf);
kvn@3447 1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1088 #ifndef PRODUCT
kvn@3447 1089 } else {
duke@0 1090 st->print("movl %s, [rsp + #%d]\t# spill",
duke@0 1091 Matcher::regName[dst_first],
duke@0 1092 offset);
duke@0 1093 #endif
duke@0 1094 }
duke@0 1095 }
kvn@3447 1096 return 0;
duke@0 1097 } else if (dst_first_rc == rc_float) {
duke@0 1098 // mem-> xmm
duke@0 1099 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1101 // 64-bit
duke@0 1102 int offset = ra_->reg2offset(src_first);
duke@0 1103 if (cbuf) {
kvn@2953 1104 MacroAssembler _masm(cbuf);
kvn@2953 1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1106 #ifndef PRODUCT
kvn@3447 1107 } else {
duke@0 1108 st->print("%s %s, [rsp + #%d]\t# spill",
duke@0 1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
duke@0 1110 Matcher::regName[dst_first],
duke@0 1111 offset);
duke@0 1112 #endif
duke@0 1113 }
duke@0 1114 } else {
duke@0 1115 // 32-bit
duke@0 1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1118 int offset = ra_->reg2offset(src_first);
duke@0 1119 if (cbuf) {
kvn@2953 1120 MacroAssembler _masm(cbuf);
kvn@2953 1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
duke@0 1122 #ifndef PRODUCT
kvn@3447 1123 } else {
duke@0 1124 st->print("movss %s, [rsp + #%d]\t# spill",
duke@0 1125 Matcher::regName[dst_first],
duke@0 1126 offset);
duke@0 1127 #endif
duke@0 1128 }
duke@0 1129 }
kvn@3447 1130 return 0;
duke@0 1131 }
duke@0 1132 } else if (src_first_rc == rc_int) {
duke@0 1133 // gpr ->
duke@0 1134 if (dst_first_rc == rc_stack) {
duke@0 1135 // gpr -> mem
duke@0 1136 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1138 // 64-bit
duke@0 1139 int offset = ra_->reg2offset(dst_first);
duke@0 1140 if (cbuf) {
kvn@3447 1141 MacroAssembler _masm(cbuf);
kvn@3447 1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1143 #ifndef PRODUCT
kvn@3447 1144 } else {
duke@0 1145 st->print("movq [rsp + #%d], %s\t# spill",
duke@0 1146 offset,
duke@0 1147 Matcher::regName[src_first]);
duke@0 1148 #endif
duke@0 1149 }
duke@0 1150 } else {
duke@0 1151 // 32-bit
duke@0 1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1154 int offset = ra_->reg2offset(dst_first);
duke@0 1155 if (cbuf) {
kvn@3447 1156 MacroAssembler _masm(cbuf);
kvn@3447 1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
duke@0 1158 #ifndef PRODUCT
kvn@3447 1159 } else {
duke@0 1160 st->print("movl [rsp + #%d], %s\t# spill",
duke@0 1161 offset,
duke@0 1162 Matcher::regName[src_first]);
duke@0 1163 #endif
duke@0 1164 }
duke@0 1165 }
kvn@3447 1166 return 0;
duke@0 1167 } else if (dst_first_rc == rc_int) {
duke@0 1168 // gpr -> gpr
duke@0 1169 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1171 // 64-bit
duke@0 1172 if (cbuf) {
kvn@3447 1173 MacroAssembler _masm(cbuf);
kvn@3447 1174 __ movq(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1175 as_Register(Matcher::_regEncode[src_first]));
duke@0 1176 #ifndef PRODUCT
kvn@3447 1177 } else {
duke@0 1178 st->print("movq %s, %s\t# spill",
duke@0 1179 Matcher::regName[dst_first],
duke@0 1180 Matcher::regName[src_first]);
duke@0 1181 #endif
duke@0 1182 }
kvn@3447 1183 return 0;
duke@0 1184 } else {
duke@0 1185 // 32-bit
duke@0 1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1188 if (cbuf) {
kvn@3447 1189 MacroAssembler _masm(cbuf);
kvn@3447 1190 __ movl(as_Register(Matcher::_regEncode[dst_first]),
kvn@3447 1191 as_Register(Matcher::_regEncode[src_first]));
duke@0 1192 #ifndef PRODUCT
kvn@3447 1193 } else {
duke@0 1194 st->print("movl %s, %s\t# spill",
duke@0 1195 Matcher::regName[dst_first],
duke@0 1196 Matcher::regName[src_first]);
duke@0 1197 #endif
duke@0 1198 }
kvn@3447 1199 return 0;
duke@0 1200 }
duke@0 1201 } else if (dst_first_rc == rc_float) {
duke@0 1202 // gpr -> xmm
duke@0 1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1205 // 64-bit
duke@0 1206 if (cbuf) {
kvn@2953 1207 MacroAssembler _masm(cbuf);
kvn@2953 1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1209 #ifndef PRODUCT
kvn@3447 1210 } else {
duke@0 1211 st->print("movdq %s, %s\t# spill",
duke@0 1212 Matcher::regName[dst_first],
duke@0 1213 Matcher::regName[src_first]);
duke@0 1214 #endif
duke@0 1215 }
duke@0 1216 } else {
duke@0 1217 // 32-bit
duke@0 1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1220 if (cbuf) {
kvn@2953 1221 MacroAssembler _masm(cbuf);
kvn@2953 1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
duke@0 1223 #ifndef PRODUCT
kvn@3447 1224 } else {
duke@0 1225 st->print("movdl %s, %s\t# spill",
duke@0 1226 Matcher::regName[dst_first],
duke@0 1227 Matcher::regName[src_first]);
duke@0 1228 #endif
duke@0 1229 }
duke@0 1230 }
kvn@3447 1231 return 0;
duke@0 1232 }
duke@0 1233 } else if (src_first_rc == rc_float) {
duke@0 1234 // xmm ->
duke@0 1235 if (dst_first_rc == rc_stack) {
duke@0 1236 // xmm -> mem
duke@0 1237 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1239 // 64-bit
duke@0 1240 int offset = ra_->reg2offset(dst_first);
duke@0 1241 if (cbuf) {
kvn@2953 1242 MacroAssembler _masm(cbuf);
kvn@2953 1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1244 #ifndef PRODUCT
kvn@3447 1245 } else {
duke@0 1246 st->print("movsd [rsp + #%d], %s\t# spill",
duke@0 1247 offset,
duke@0 1248 Matcher::regName[src_first]);
duke@0 1249 #endif
duke@0 1250 }
duke@0 1251 } else {
duke@0 1252 // 32-bit
duke@0 1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1255 int offset = ra_->reg2offset(dst_first);
duke@0 1256 if (cbuf) {
kvn@2953 1257 MacroAssembler _masm(cbuf);
kvn@2953 1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1259 #ifndef PRODUCT
kvn@3447 1260 } else {
duke@0 1261 st->print("movss [rsp + #%d], %s\t# spill",
duke@0 1262 offset,
duke@0 1263 Matcher::regName[src_first]);
duke@0 1264 #endif
duke@0 1265 }
duke@0 1266 }
kvn@3447 1267 return 0;
duke@0 1268 } else if (dst_first_rc == rc_int) {
duke@0 1269 // xmm -> gpr
duke@0 1270 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1272 // 64-bit
duke@0 1273 if (cbuf) {
kvn@2953 1274 MacroAssembler _masm(cbuf);
kvn@2953 1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1276 #ifndef PRODUCT
kvn@3447 1277 } else {
duke@0 1278 st->print("movdq %s, %s\t# spill",
duke@0 1279 Matcher::regName[dst_first],
duke@0 1280 Matcher::regName[src_first]);
duke@0 1281 #endif
duke@0 1282 }
duke@0 1283 } else {
duke@0 1284 // 32-bit
duke@0 1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1287 if (cbuf) {
kvn@2953 1288 MacroAssembler _masm(cbuf);
kvn@2953 1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1290 #ifndef PRODUCT
kvn@3447 1291 } else {
duke@0 1292 st->print("movdl %s, %s\t# spill",
duke@0 1293 Matcher::regName[dst_first],
duke@0 1294 Matcher::regName[src_first]);
duke@0 1295 #endif
duke@0 1296 }
duke@0 1297 }
kvn@3447 1298 return 0;
duke@0 1299 } else if (dst_first_rc == rc_float) {
duke@0 1300 // xmm -> xmm
duke@0 1301 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
duke@0 1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
duke@0 1303 // 64-bit
duke@0 1304 if (cbuf) {
kvn@2953 1305 MacroAssembler _masm(cbuf);
kvn@2953 1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1307 #ifndef PRODUCT
kvn@3447 1308 } else {
duke@0 1309 st->print("%s %s, %s\t# spill",
duke@0 1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
duke@0 1311 Matcher::regName[dst_first],
duke@0 1312 Matcher::regName[src_first]);
duke@0 1313 #endif
duke@0 1314 }
duke@0 1315 } else {
duke@0 1316 // 32-bit
duke@0 1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
duke@0 1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
duke@0 1319 if (cbuf) {
kvn@2953 1320 MacroAssembler _masm(cbuf);
kvn@2953 1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
duke@0 1322 #ifndef PRODUCT
kvn@3447 1323 } else {
duke@0 1324 st->print("%s %s, %s\t# spill",
duke@0 1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
duke@0 1326 Matcher::regName[dst_first],
duke@0 1327 Matcher::regName[src_first]);
duke@0 1328 #endif
duke@0 1329 }
duke@0 1330 }
kvn@3447 1331 return 0;
duke@0 1332 }
duke@0 1333 }
duke@0 1334
duke@0 1335 assert(0," foo ");
duke@0 1336 Unimplemented();
duke@0 1337 return 0;
duke@0 1338 }
duke@0 1339
duke@0 1340 #ifndef PRODUCT
kvn@3447 1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
duke@0 1342 implementation(NULL, ra_, false, st);
duke@0 1343 }
duke@0 1344 #endif
duke@0 1345
kvn@3447 1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1347 implementation(&cbuf, ra_, false, NULL);
duke@0 1348 }
duke@0 1349
kvn@3447 1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
kvn@3447 1351 return MachNode::size(ra_);
duke@0 1352 }
duke@0 1353
duke@0 1354 //=============================================================================
duke@0 1355 #ifndef PRODUCT
duke@0 1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1357 {
duke@0 1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1359 int reg = ra_->get_reg_first(this);
duke@0 1360 st->print("leaq %s, [rsp + #%d]\t# box lock",
duke@0 1361 Matcher::regName[reg], offset);
duke@0 1362 }
duke@0 1363 #endif
duke@0 1364
duke@0 1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1366 {
duke@0 1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1368 int reg = ra_->get_encode(this);
duke@0 1369 if (offset >= 0x80) {
duke@0 1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1372 emit_rm(cbuf, 0x2, reg & 7, 0x04);
duke@0 1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1374 emit_d32(cbuf, offset);
duke@0 1375 } else {
duke@0 1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
duke@0 1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
duke@0 1378 emit_rm(cbuf, 0x1, reg & 7, 0x04);
duke@0 1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
duke@0 1380 emit_d8(cbuf, offset);
duke@0 1381 }
duke@0 1382 }
duke@0 1383
duke@0 1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
duke@0 1385 {
duke@0 1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1387 return (offset < 0x80) ? 5 : 8; // REX
duke@0 1388 }
duke@0 1389
duke@0 1390 //=============================================================================
duke@0 1391
duke@0 1392 // emit call stub, compiled java to interpreter
duke@0 1393 void emit_java_to_interp(CodeBuffer& cbuf)
duke@0 1394 {
duke@0 1395 // Stub is fixed up when the corresponding call is converted from
duke@0 1396 // calling compiled code to calling interpreted code.
duke@0 1397 // movq rbx, 0
duke@0 1398 // jmp -5 # to self
duke@0 1399
twisti@1668 1400 address mark = cbuf.insts_mark(); // get mark within main instrs section
twisti@1668 1401
twisti@1668 1402 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1403 // That's why we must use the macroassembler to generate a stub.
duke@0 1404 MacroAssembler _masm(&cbuf);
duke@0 1405
duke@0 1406 address base =
duke@0 1407 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1408 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1409 // static stub relocation stores the instruction address of the call
duke@0 1410 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
coleenp@3602 1411 // static stub relocation also tags the Method* in the code-stream.
coleenp@3602 1412 __ mov_metadata(rbx, (Metadata*) NULL); // method is zapped till fixup time
never@304 1413 // This is recognized as unresolved by relocs/nativeinst/ic code
duke@0 1414 __ jump(RuntimeAddress(__ pc()));
duke@0 1415
twisti@1668 1416 // Update current stubs pointer and restore insts_end.
duke@0 1417 __ end_a_stub();
duke@0 1418 }
duke@0 1419
duke@0 1420 // size of call stub, compiled java to interpretor
duke@0 1421 uint size_java_to_interp()
duke@0 1422 {
duke@0 1423 return 15; // movq (1+1+8); jmp (1+4)
duke@0 1424 }
duke@0 1425
duke@0 1426 // relocation entries for call stub, compiled java to interpretor
duke@0 1427 uint reloc_java_to_interp()
duke@0 1428 {
duke@0 1429 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1430 }
duke@0 1431
duke@0 1432 //=============================================================================
duke@0 1433 #ifndef PRODUCT
duke@0 1434 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
duke@0 1435 {
roland@3724 1436 if (UseCompressedKlassPointers) {
kvn@1491 1437 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
roland@3724 1438 if (Universe::narrow_klass_shift() != 0) {
roland@3724 1439 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
kvn@1491 1440 }
kvn@1491 1441 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
coleenp@113 1442 } else {
kvn@1491 1443 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
kvn@1491 1444 "# Inline cache check");
coleenp@113 1445 }
duke@0 1446 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
kvn@1491 1447 st->print_cr("\tnop\t# nops to align entry point");
duke@0 1448 }
duke@0 1449 #endif
duke@0 1450
duke@0 1451 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
duke@0 1452 {
duke@0 1453 MacroAssembler masm(&cbuf);
twisti@1668 1454 uint insts_size = cbuf.insts_size();
roland@3724 1455 if (UseCompressedKlassPointers) {
coleenp@113 1456 masm.load_klass(rscratch1, j_rarg0);
never@304 1457 masm.cmpptr(rax, rscratch1);
coleenp@113 1458 } else {
never@304 1459 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
coleenp@113 1460 }
duke@0 1461
duke@0 1462 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
duke@0 1463
duke@0 1464 /* WARNING these NOPs are critical so that verified entry point is properly
kvn@1491 1465 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
twisti@1668 1466 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
kvn@1491 1467 if (OptoBreakpoint) {
duke@0 1468 // Leave space for int3
kvn@1491 1469 nops_cnt -= 1;
duke@0 1470 }
kvn@1491 1471 nops_cnt &= 0x3; // Do not add nops if code is aligned.
kvn@1491 1472 if (nops_cnt > 0)
kvn@1491 1473 masm.nop(nops_cnt);
duke@0 1474 }
duke@0 1475
duke@0 1476 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
duke@0 1477 {
kvn@1491 1478 return MachNode::size(ra_); // too many variables; just compute it
kvn@1491 1479 // the hard way
duke@0 1480 }
duke@0 1481
duke@0 1482
duke@0 1483 //=============================================================================
duke@0 1484 uint size_exception_handler()
duke@0 1485 {
duke@0 1486 // NativeCall instruction size is the same as NativeJump.
duke@0 1487 // Note that this value is also credited (in output.cpp) to
duke@0 1488 // the size of the code section.
duke@0 1489 return NativeJump::instruction_size;
duke@0 1490 }
duke@0 1491
duke@0 1492 // Emit exception handler code.
duke@0 1493 int emit_exception_handler(CodeBuffer& cbuf)
duke@0 1494 {
duke@0 1495
twisti@1668 1496 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1497 // That's why we must use the macroassembler to generate a handler.
duke@0 1498 MacroAssembler _masm(&cbuf);
duke@0 1499 address base =
duke@0 1500 __ start_a_stub(size_exception_handler());
duke@0 1501 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1502 int offset = __ offset();
twisti@1668 1503 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
duke@0 1504 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1505 __ end_a_stub();
duke@0 1506 return offset;
duke@0 1507 }
duke@0 1508
duke@0 1509 uint size_deopt_handler()
duke@0 1510 {
duke@0 1511 // three 5 byte instructions
duke@0 1512 return 15;
duke@0 1513 }
duke@0 1514
duke@0 1515 // Emit deopt handler code.
duke@0 1516 int emit_deopt_handler(CodeBuffer& cbuf)
duke@0 1517 {
duke@0 1518
twisti@1668 1519 // Note that the code buffer's insts_mark is always relative to insts.
duke@0 1520 // That's why we must use the macroassembler to generate a handler.
duke@0 1521 MacroAssembler _masm(&cbuf);
duke@0 1522 address base =
duke@0 1523 __ start_a_stub(size_deopt_handler());
duke@0 1524 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1525 int offset = __ offset();
duke@0 1526 address the_pc = (address) __ pc();
duke@0 1527 Label next;
duke@0 1528 // push a "the_pc" on the stack without destroying any registers
duke@0 1529 // as they all may be live.
duke@0 1530
duke@0 1531 // push address of "next"
duke@0 1532 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
duke@0 1533 __ bind(next);
duke@0 1534 // adjust it so it matches "the_pc"
never@304 1535 __ subptr(Address(rsp, 0), __ offset() - offset);
duke@0 1536 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
duke@0 1537 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1538 __ end_a_stub();
duke@0 1539 return offset;
duke@0 1540 }
duke@0 1541
duke@0 1542 int Matcher::regnum_to_fpu_offset(int regnum)
duke@0 1543 {
duke@0 1544 return regnum - 32; // The FP registers are in the second chunk
duke@0 1545 }
duke@0 1546
duke@0 1547 // This is UltraSparc specific, true just means we have fast l2f conversion
duke@0 1548 const bool Matcher::convL2FSupported(void) {
duke@0 1549 return true;
duke@0 1550 }
duke@0 1551
duke@0 1552 // Is this branch offset short enough that a short branch can be used?
duke@0 1553 //
duke@0 1554 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1555 // this method should return false for offset 0.
kvn@2614 1556 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
kvn@2614 1557 // The passed offset is relative to address of the branch.
kvn@2614 1558 // On 86 a branch displacement is calculated relative to address
kvn@2614 1559 // of a next instruction.
kvn@2614 1560 offset -= br_size;
kvn@2614 1561
never@415 1562 // the short version of jmpConUCF2 contains multiple branches,
never@415 1563 // making the reach slightly less
never@415 1564 if (rule == jmpConUCF2_rule)
never@415 1565 return (-126 <= offset && offset <= 125);
never@415 1566 return (-128 <= offset && offset <= 127);
duke@0 1567 }
duke@0 1568
duke@0 1569 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1570 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1571 //return value == (int) value; // Cf. storeImmL and immL32.
duke@0 1572
duke@0 1573 // Probably always true, even if a temp register is required.
duke@0 1574 return true;
duke@0 1575 }
duke@0 1576
duke@0 1577 // The ecx parameter to rep stosq for the ClearArray node is in words.
duke@0 1578 const bool Matcher::init_array_count_is_in_bytes = false;
duke@0 1579
duke@0 1580 // Threshold size for cleararray.
duke@0 1581 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1582
kvn@2808 1583 // No additional cost for CMOVL.
kvn@2808 1584 const int Matcher::long_cmove_cost() { return 0; }
kvn@2808 1585
kvn@2808 1586 // No CMOVF/CMOVD with SSE2
kvn@2808 1587 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
kvn@2808 1588
duke@0 1589 // Should the Matcher clone shifts on addressing modes, expecting them
duke@0 1590 // to be subsumed into complex addressing expressions or compute them
duke@0 1591 // into registers? True for Intel but false for most RISCs
duke@0 1592 const bool Matcher::clone_shift_expressions = true;
duke@0 1593
roland@2248 1594 // Do we need to mask the count passed to shift instructions or does
roland@2248 1595 // the cpu only look at the lower 5/6 bits anyway?
roland@2248 1596 const bool Matcher::need_masked_shift_count = false;
roland@2248 1597
kvn@1495 1598 bool Matcher::narrow_oop_use_complex_address() {
kvn@1495 1599 assert(UseCompressedOops, "only for compressed oops code");
kvn@1495 1600 return (LogMinObjAlignmentInBytes <= 3);
kvn@1495 1601 }
kvn@1495 1602
roland@3724 1603 bool Matcher::narrow_klass_use_complex_address() {
roland@3724 1604 assert(UseCompressedKlassPointers, "only for compressed klass code");
roland@3724 1605 return (LogKlassAlignmentInBytes <= 3);
roland@3724 1606 }
roland@3724 1607
duke@0 1608 // Is it better to copy float constants, or load them directly from
duke@0 1609 // memory? Intel can load a float constant from a direct address,
duke@0 1610 // requiring no extra registers. Most RISCs will have to materialize
duke@0 1611 // an address into a register first, so they would do better to copy
duke@0 1612 // the constant from stack.
duke@0 1613 const bool Matcher::rematerialize_float_constants = true; // XXX
duke@0 1614
duke@0 1615 // If CPU can load and store mis-aligned doubles directly then no
duke@0 1616 // fixup is needed. Else we split the double into 2 integer pieces
duke@0 1617 // and move it piece-by-piece. Only happens when passing doubles into
duke@0 1618 // C code as the Java calling convention forces doubles to be aligned.
duke@0 1619 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1620
duke@0 1621 // No-op on amd64
duke@0 1622 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
duke@0 1623
duke@0 1624 // Advertise here if the CPU requires explicit rounding operations to
duke@0 1625 // implement the UseStrictFP mode.
duke@0 1626 const bool Matcher::strict_fp_requires_explicit_rounding = true;
duke@0 1627
kvn@1274 1628 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 1629 // On x64 it is stored without convertion so we can use normal access.
kvn@1274 1630 bool Matcher::float_in_double() { return false; }
kvn@1274 1631
duke@0 1632 // Do ints take an entire long register or just half?
duke@0 1633 const bool Matcher::int_in_long = true;
duke@0 1634
duke@0 1635 // Return whether or not this register is ever used as an argument.
duke@0 1636 // This function is used on startup to build the trampoline stubs in
duke@0 1637 // generateOptoStub. Registers not mentioned will be killed by the VM
duke@0 1638 // call in the trampoline, and arguments in those registers not be
duke@0 1639 // available to the callee.
duke@0 1640 bool Matcher::can_be_java_arg(int reg)
duke@0 1641 {
duke@0 1642 return
kvn@3447 1643 reg == RDI_num || reg == RDI_H_num ||
kvn@3447 1644 reg == RSI_num || reg == RSI_H_num ||
kvn@3447 1645 reg == RDX_num || reg == RDX_H_num ||
kvn@3447 1646 reg == RCX_num || reg == RCX_H_num ||
kvn@3447 1647 reg == R8_num || reg == R8_H_num ||
kvn@3447 1648 reg == R9_num || reg == R9_H_num ||
kvn@3447 1649 reg == R12_num || reg == R12_H_num ||
kvn@3447 1650 reg == XMM0_num || reg == XMM0b_num ||
kvn@3447 1651 reg == XMM1_num || reg == XMM1b_num ||
kvn@3447 1652 reg == XMM2_num || reg == XMM2b_num ||
kvn@3447 1653 reg == XMM3_num || reg == XMM3b_num ||
kvn@3447 1654 reg == XMM4_num || reg == XMM4b_num ||
kvn@3447 1655 reg == XMM5_num || reg == XMM5b_num ||
kvn@3447 1656 reg == XMM6_num || reg == XMM6b_num ||
kvn@3447 1657 reg == XMM7_num || reg == XMM7b_num;
duke@0 1658 }
duke@0 1659
duke@0 1660 bool Matcher::is_spillable_arg(int reg)
duke@0 1661 {
duke@0 1662 return can_be_java_arg(reg);
duke@0 1663 }
duke@0 1664
kvn@1834 1665 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
kvn@1834 1666 // In 64 bit mode a code which use multiply when
kvn@1834 1667 // devisor is constant is faster than hardware
kvn@1834 1668 // DIV instruction (it uses MulHiL).
kvn@1834 1669 return false;
kvn@1834 1670 }
kvn@1834 1671
duke@0 1672 // Register for DIVI projection of divmodI
duke@0 1673 RegMask Matcher::divI_proj_mask() {
roland@2882 1674 return INT_RAX_REG_mask();
duke@0 1675 }
duke@0 1676
duke@0 1677 // Register for MODI projection of divmodI
duke@0 1678 RegMask Matcher::modI_proj_mask() {
roland@2882 1679 return INT_RDX_REG_mask();
duke@0 1680 }
duke@0 1681
duke@0 1682 // Register for DIVL projection of divmodL
duke@0 1683 RegMask Matcher::divL_proj_mask() {
roland@2882 1684 return LONG_RAX_REG_mask();
duke@0 1685 }
duke@0 1686
duke@0 1687 // Register for MODL projection of divmodL
duke@0 1688 RegMask Matcher::modL_proj_mask() {
roland@2882 1689 return LONG_RDX_REG_mask();
duke@0 1690 }
duke@0 1691
twisti@1137 1692 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
roland@2882 1693 return PTR_RBP_REG_mask();
twisti@1137 1694 }
twisti@1137 1695
coleenp@113 1696 static Address build_address(int b, int i, int s, int d) {
coleenp@113 1697 Register index = as_Register(i);
coleenp@113 1698 Address::ScaleFactor scale = (Address::ScaleFactor)s;
coleenp@113 1699 if (index == rsp) {
coleenp@113 1700 index = noreg;
coleenp@113 1701 scale = Address::no_scale;
coleenp@113 1702 }
coleenp@113 1703 Address addr(as_Register(b), index, scale, d);
coleenp@113 1704 return addr;
coleenp@113 1705 }
coleenp@113 1706
duke@0 1707 %}
duke@0 1708
duke@0 1709 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1710 // This block specifies the encoding classes used by the compiler to
duke@0 1711 // output byte streams. Encoding classes are parameterized macros
duke@0 1712 // used by Machine Instruction Nodes in order to generate the bit
duke@0 1713 // encoding of the instruction. Operands specify their base encoding
duke@0 1714 // interface with the interface keyword. There are currently
duke@0 1715 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
duke@0 1716 // COND_INTER. REG_INTER causes an operand to generate a function
duke@0 1717 // which returns its register number when queried. CONST_INTER causes
duke@0 1718 // an operand to generate a function which returns the value of the
duke@0 1719 // constant when queried. MEMORY_INTER causes an operand to generate
duke@0 1720 // four functions which return the Base Register, the Index Register,
duke@0 1721 // the Scale Value, and the Offset Value of the operand when queried.
duke@0 1722 // COND_INTER causes an operand to generate six functions which return
duke@0 1723 // the encoding code (ie - encoding bits for the instruction)
duke@0 1724 // associated with each basic boolean condition for a conditional
duke@0 1725 // instruction.
duke@0 1726 //
duke@0 1727 // Instructions specify two basic values for encoding. Again, a
duke@0 1728 // function is available to check if the constant displacement is an
duke@0 1729 // oop. They use the ins_encode keyword to specify their encoding
duke@0 1730 // classes (which must be a sequence of enc_class names, and their
duke@0 1731 // parameters, specified in the encoding block), and they use the
duke@0 1732 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1733 // tertiary opcode. Only the opcode sections which a particular
duke@0 1734 // instruction needs for encoding need to be specified.
duke@0 1735 encode %{
duke@0 1736 // Build emit functions for each basic byte or larger field in the
duke@0 1737 // intel encoding scheme (opcode, rm, sib, immediate), and call them
duke@0 1738 // from C++ code in the enc_class source block. Emit functions will
duke@0 1739 // live in the main source block for now. In future, we can
duke@0 1740 // generalize this by adding a syntax that specifies the sizes of
duke@0 1741 // fields in an order, so that the adlc can build the emit functions
duke@0 1742 // automagically
duke@0 1743
duke@0 1744 // Emit primary opcode
duke@0 1745 enc_class OpcP
duke@0 1746 %{
duke@0 1747 emit_opcode(cbuf, $primary);
duke@0 1748 %}
duke@0 1749
duke@0 1750 // Emit secondary opcode
duke@0 1751 enc_class OpcS
duke@0 1752 %{
duke@0 1753 emit_opcode(cbuf, $secondary);
duke@0 1754 %}
duke@0 1755
duke@0 1756 // Emit tertiary opcode
duke@0 1757 enc_class OpcT
duke@0 1758 %{
duke@0 1759 emit_opcode(cbuf, $tertiary);
duke@0 1760 %}
duke@0 1761
duke@0 1762 // Emit opcode directly
duke@0 1763 enc_class Opcode(immI d8)
duke@0 1764 %{
duke@0 1765 emit_opcode(cbuf, $d8$$constant);
duke@0 1766 %}
duke@0 1767
duke@0 1768 // Emit size prefix
duke@0 1769 enc_class SizePrefix
duke@0 1770 %{
duke@0 1771 emit_opcode(cbuf, 0x66);
duke@0 1772 %}
duke@0 1773
duke@0 1774 enc_class reg(rRegI reg)
duke@0 1775 %{
duke@0 1776 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
duke@0 1777 %}
duke@0 1778
duke@0 1779 enc_class reg_reg(rRegI dst, rRegI src)
duke@0 1780 %{
duke@0 1781 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1782 %}
duke@0 1783
duke@0 1784 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
duke@0 1785 %{
duke@0 1786 emit_opcode(cbuf, $opcode$$constant);
duke@0 1787 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
duke@0 1788 %}
duke@0 1789
duke@0 1790 enc_class cdql_enc(no_rax_rdx_RegI div)
duke@0 1791 %{
duke@0 1792 // Full implementation of Java idiv and irem; checks for
duke@0 1793 // special case as described in JVM spec., p.243 & p.271.
duke@0 1794 //
duke@0 1795 // normal case special case
duke@0 1796 //
duke@0 1797 // input : rax: dividend min_int
duke@0 1798 // reg: divisor -1
duke@0 1799 //
duke@0 1800 // output: rax: quotient (= rax idiv reg) min_int
duke@0 1801 // rdx: remainder (= rax irem reg) 0
duke@0 1802 //
duke@0 1803 // Code sequnce:
duke@0 1804 //
duke@0 1805 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
duke@0 1806 // 5: 75 07/08 jne e <normal>
duke@0 1807 // 7: 33 d2 xor %edx,%edx
duke@0 1808 // [div >= 8 -> offset + 1]
duke@0 1809 // [REX_B]
duke@0 1810 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1811 // c: 74 03/04 je 11 <done>
duke@0 1812 // 000000000000000e <normal>:
duke@0 1813 // e: 99 cltd
duke@0 1814 // [div >= 8 -> offset + 1]
duke@0 1815 // [REX_B]
duke@0 1816 // f: f7 f9 idiv $div
duke@0 1817 // 0000000000000011 <done>:
duke@0 1818
duke@0 1819 // cmp $0x80000000,%eax
duke@0 1820 emit_opcode(cbuf, 0x3d);
duke@0 1821 emit_d8(cbuf, 0x00);
duke@0 1822 emit_d8(cbuf, 0x00);
duke@0 1823 emit_d8(cbuf, 0x00);
duke@0 1824 emit_d8(cbuf, 0x80);
duke@0 1825
duke@0 1826 // jne e <normal>
duke@0 1827 emit_opcode(cbuf, 0x75);
duke@0 1828 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
duke@0 1829
duke@0 1830 // xor %edx,%edx
duke@0 1831 emit_opcode(cbuf, 0x33);
duke@0 1832 emit_d8(cbuf, 0xD2);
duke@0 1833
duke@0 1834 // cmp $0xffffffffffffffff,%ecx
duke@0 1835 if ($div$$reg >= 8) {
duke@0 1836 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1837 }
duke@0 1838 emit_opcode(cbuf, 0x83);
duke@0 1839 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1840 emit_d8(cbuf, 0xFF);
duke@0 1841
duke@0 1842 // je 11 <done>
duke@0 1843 emit_opcode(cbuf, 0x74);
duke@0 1844 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
duke@0 1845
duke@0 1846 // <normal>
duke@0 1847 // cltd
duke@0 1848 emit_opcode(cbuf, 0x99);
duke@0 1849
duke@0 1850 // idivl (note: must be emitted by the user of this rule)
duke@0 1851 // <done>
duke@0 1852 %}
duke@0 1853
duke@0 1854 enc_class cdqq_enc(no_rax_rdx_RegL div)
duke@0 1855 %{
duke@0 1856 // Full implementation of Java ldiv and lrem; checks for
duke@0 1857 // special case as described in JVM spec., p.243 & p.271.
duke@0 1858 //
duke@0 1859 // normal case special case
duke@0 1860 //
duke@0 1861 // input : rax: dividend min_long
duke@0 1862 // reg: divisor -1
duke@0 1863 //
duke@0 1864 // output: rax: quotient (= rax idiv reg) min_long
duke@0 1865 // rdx: remainder (= rax irem reg) 0
duke@0 1866 //
duke@0 1867 // Code sequnce:
duke@0 1868 //
duke@0 1869 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
duke@0 1870 // 7: 00 00 80
duke@0 1871 // a: 48 39 d0 cmp %rdx,%rax
duke@0 1872 // d: 75 08 jne 17 <normal>
duke@0 1873 // f: 33 d2 xor %edx,%edx
duke@0 1874 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
duke@0 1875 // 15: 74 05 je 1c <done>
duke@0 1876 // 0000000000000017 <normal>:
duke@0 1877 // 17: 48 99 cqto
duke@0 1878 // 19: 48 f7 f9 idiv $div
duke@0 1879 // 000000000000001c <done>:
duke@0 1880
duke@0 1881 // mov $0x8000000000000000,%rdx
duke@0 1882 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1883 emit_opcode(cbuf, 0xBA);
duke@0 1884 emit_d8(cbuf, 0x00);
duke@0 1885 emit_d8(cbuf, 0x00);
duke@0 1886 emit_d8(cbuf, 0x00);
duke@0 1887 emit_d8(cbuf, 0x00);
duke@0 1888 emit_d8(cbuf, 0x00);
duke@0 1889 emit_d8(cbuf, 0x00);
duke@0 1890 emit_d8(cbuf, 0x00);
duke@0 1891 emit_d8(cbuf, 0x80);
duke@0 1892
duke@0 1893 // cmp %rdx,%rax
duke@0 1894 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1895 emit_opcode(cbuf, 0x39);
duke@0 1896 emit_d8(cbuf, 0xD0);
duke@0 1897
duke@0 1898 // jne 17 <normal>
duke@0 1899 emit_opcode(cbuf, 0x75);
duke@0 1900 emit_d8(cbuf, 0x08);
duke@0 1901
duke@0 1902 // xor %edx,%edx
duke@0 1903 emit_opcode(cbuf, 0x33);
duke@0 1904 emit_d8(cbuf, 0xD2);
duke@0 1905
duke@0 1906 // cmp $0xffffffffffffffff,$div
duke@0 1907 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
duke@0 1908 emit_opcode(cbuf, 0x83);
duke@0 1909 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
duke@0 1910 emit_d8(cbuf, 0xFF);
duke@0 1911
duke@0 1912 // je 1e <done>
duke@0 1913 emit_opcode(cbuf, 0x74);
duke@0 1914 emit_d8(cbuf, 0x05);
duke@0 1915
duke@0 1916 // <normal>
duke@0 1917 // cqto
duke@0 1918 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1919 emit_opcode(cbuf, 0x99);
duke@0 1920
duke@0 1921 // idivq (note: must be emitted by the user of this rule)
duke@0 1922 // <done>
duke@0 1923 %}
duke@0 1924
duke@0 1925 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
duke@0 1926 enc_class OpcSE(immI imm)
duke@0 1927 %{
duke@0 1928 // Emit primary opcode and set sign-extend bit
duke@0 1929 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1930 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1931 emit_opcode(cbuf, $primary | 0x02);
duke@0 1932 } else {
duke@0 1933 // 32-bit immediate
duke@0 1934 emit_opcode(cbuf, $primary);
duke@0 1935 }
duke@0 1936 %}
duke@0 1937
duke@0 1938 enc_class OpcSErm(rRegI dst, immI imm)
duke@0 1939 %{
duke@0 1940 // OpcSEr/m
duke@0 1941 int dstenc = $dst$$reg;
duke@0 1942 if (dstenc >= 8) {
duke@0 1943 emit_opcode(cbuf, Assembler::REX_B);
duke@0 1944 dstenc -= 8;
duke@0 1945 }
duke@0 1946 // Emit primary opcode and set sign-extend bit
duke@0 1947 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1948 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1949 emit_opcode(cbuf, $primary | 0x02);
duke@0 1950 } else {
duke@0 1951 // 32-bit immediate
duke@0 1952 emit_opcode(cbuf, $primary);
duke@0 1953 }
duke@0 1954 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1955 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1956 %}
duke@0 1957
duke@0 1958 enc_class OpcSErm_wide(rRegL dst, immI imm)
duke@0 1959 %{
duke@0 1960 // OpcSEr/m
duke@0 1961 int dstenc = $dst$$reg;
duke@0 1962 if (dstenc < 8) {
duke@0 1963 emit_opcode(cbuf, Assembler::REX_W);
duke@0 1964 } else {
duke@0 1965 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 1966 dstenc -= 8;
duke@0 1967 }
duke@0 1968 // Emit primary opcode and set sign-extend bit
duke@0 1969 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1970 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1971 emit_opcode(cbuf, $primary | 0x02);
duke@0 1972 } else {
duke@0 1973 // 32-bit immediate
duke@0 1974 emit_opcode(cbuf, $primary);
duke@0 1975 }
duke@0 1976 // Emit r/m byte with secondary opcode, after primary opcode.
duke@0 1977 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 1978 %}
duke@0 1979
duke@0 1980 enc_class Con8or32(immI imm)
duke@0 1981 %{
duke@0 1982 // Check for 8-bit immediate, and set sign extend bit in opcode
duke@0 1983 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
duke@0 1984 $$$emit8$imm$$constant;
duke@0 1985 } else {
duke@0 1986 // 32-bit immediate
duke@0 1987 $$$emit32$imm$$constant;
duke@0 1988 }
duke@0 1989 %}
duke@0 1990
duke@0 1991 enc_class opc2_reg(rRegI dst)
duke@0 1992 %{
duke@0 1993 // BSWAP
duke@0 1994 emit_cc(cbuf, $secondary, $dst$$reg);
duke@0 1995 %}
duke@0 1996
duke@0 1997 enc_class opc3_reg(rRegI dst)
duke@0 1998 %{
duke@0 1999 // BSWAP
duke@0 2000 emit_cc(cbuf, $tertiary, $dst$$reg);
duke@0 2001 %}
duke@0 2002
duke@0 2003 enc_class reg_opc(rRegI div)
duke@0 2004 %{
duke@0 2005 // INC, DEC, IDIV, IMOD, JMP indirect, ...
duke@0 2006 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
duke@0 2007 %}
duke@0 2008
duke@0 2009 enc_class enc_cmov(cmpOp cop)
duke@0 2010 %{
duke@0 2011 // CMOV
duke@0 2012 $$$emit8$primary;
duke@0 2013 emit_cc(cbuf, $secondary, $cop$$cmpcode);
duke@0 2014 %}
duke@0 2015
duke@0 2016 enc_class enc_PartialSubtypeCheck()
duke@0 2017 %{
duke@0 2018 Register Rrdi = as_Register(RDI_enc); // result register
duke@0 2019 Register Rrax = as_Register(RAX_enc); // super class
duke@0 2020 Register Rrcx = as_Register(RCX_enc); // killed
duke@0 2021 Register Rrsi = as_Register(RSI_enc); // sub class
jrose@644 2022 Label miss;
jrose@644 2023 const bool set_cond_codes = true;
duke@0 2024
duke@0 2025 MacroAssembler _masm(&cbuf);
jrose@644 2026 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
jrose@644 2027 NULL, &miss,
jrose@644 2028 /*set_cond_codes:*/ true);
duke@0 2029 if ($primary) {
never@304 2030 __ xorptr(Rrdi, Rrdi);
duke@0 2031 }
duke@0 2032 __ bind(miss);
duke@0 2033 %}
duke@0 2034
kvn@4438 2035 enc_class clear_avx %{
kvn@4438 2036 debug_only(int off0 = cbuf.insts_size());
kvn@4438 2037 if (ra_->C->max_vector_size() > 16) {
kvn@4438 2038 // Clear upper bits of YMM registers when current compiled code uses
kvn@4438 2039 // wide vectors to avoid AVX <-> SSE transition penalty during call.
kvn@4438 2040 MacroAssembler _masm(&cbuf);
kvn@4438 2041 __ vzeroupper();
kvn@4438 2042 }
kvn@4438 2043 debug_only(int off1 = cbuf.insts_size());
kvn@4438 2044 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
kvn@4438 2045 %}
kvn@4438 2046
kvn@4438 2047 enc_class Java_To_Runtime(method meth) %{
kvn@4438 2048 // No relocation needed
kvn@4438 2049 MacroAssembler _masm(&cbuf);
kvn@4438 2050 __ mov64(r10, (int64_t) $meth$$method);
kvn@4438 2051 __ call(r10);
kvn@4438 2052 %}
kvn@4438 2053
duke@0 2054 enc_class Java_To_Interpreter(method meth)
duke@0 2055 %{
duke@0 2056 // CALL Java_To_Interpreter
duke@0 2057 // This is the instruction starting address for relocation info.
twisti@1668 2058 cbuf.set_insts_mark();
duke@0 2059 $$$emit8$primary;
duke@0 2060 // CALL directly to the runtime
duke@0 2061 emit_d32_reloc(cbuf,
twisti@1668 2062 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2063 runtime_call_Relocation::spec(),
duke@0 2064 RELOC_DISP32);
duke@0 2065 %}
duke@0 2066
duke@0 2067 enc_class Java_Static_Call(method meth)
duke@0 2068 %{
duke@0 2069 // JAVA STATIC CALL
duke@0 2070 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
duke@0 2071 // determine who we intended to call.
twisti@1668 2072 cbuf.set_insts_mark();
duke@0 2073 $$$emit8$primary;
duke@0 2074
duke@0 2075 if (!_method) {
duke@0 2076 emit_d32_reloc(cbuf,
twisti@1668 2077 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2078 runtime_call_Relocation::spec(),
duke@0 2079 RELOC_DISP32);
duke@0 2080 } else if (_optimized_virtual) {
duke@0 2081 emit_d32_reloc(cbuf,
twisti@1668 2082 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2083 opt_virtual_call_Relocation::spec(),
duke@0 2084 RELOC_DISP32);
duke@0 2085 } else {
duke@0 2086 emit_d32_reloc(cbuf,
twisti@1668 2087 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
duke@0 2088 static_call_Relocation::spec(),
duke@0 2089 RELOC_DISP32);
duke@0 2090 }
duke@0 2091 if (_method) {
duke@0 2092 // Emit stub for static call
duke@0 2093 emit_java_to_interp(cbuf);
duke@0 2094 }
duke@0 2095 %}
duke@0 2096
coleenp@3602 2097 enc_class Java_Dynamic_Call(method meth) %{
coleenp@3602 2098 MacroAssembler _masm(&cbuf);
coleenp@3602 2099 __ ic_call((address)$meth$$method);
duke@0 2100 %}
duke@0 2101
duke@0 2102 enc_class Java_Compiled_Call(method meth)
duke@0 2103 %{
duke@0 2104 // JAVA COMPILED CALL
coleenp@3602 2105 int disp = in_bytes(Method:: from_compiled_offset());
duke@0 2106
duke@0 2107 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
duke@0 2108 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
duke@0 2109
duke@0 2110 // callq *disp(%rax)
twisti@1668 2111 cbuf.set_insts_mark();
duke@0 2112 $$$emit8$primary;
duke@0 2113 if (disp < 0x80) {
duke@0 2114 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
duke@0 2115 emit_d8(cbuf, disp); // Displacement
duke@0 2116 } else {
duke@0 2117 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
duke@0 2118 emit_d32(cbuf, disp); // Displacement
duke@0 2119 }
duke@0 2120 %}
duke@0 2121
duke@0 2122 enc_class reg_opc_imm(rRegI dst, immI8 shift)
duke@0 2123 %{
duke@0 2124 // SAL, SAR, SHR
duke@0 2125 int dstenc = $dst$$reg;
duke@0 2126 if (dstenc >= 8) {
duke@0 2127 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2128 dstenc -= 8;
duke@0 2129 }
duke@0 2130 $$$emit8$primary;
duke@0 2131 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2132 $$$emit8$shift$$constant;
duke@0 2133 %}
duke@0 2134
duke@0 2135 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
duke@0 2136 %{
duke@0 2137 // SAL, SAR, SHR
duke@0 2138 int dstenc = $dst$$reg;
duke@0 2139 if (dstenc < 8) {
duke@0 2140 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2141 } else {
duke@0 2142 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2143 dstenc -= 8;
duke@0 2144 }
duke@0 2145 $$$emit8$primary;
duke@0 2146 emit_rm(cbuf, 0x3, $secondary, dstenc);
duke@0 2147 $$$emit8$shift$$constant;
duke@0 2148 %}
duke@0 2149
duke@0 2150 enc_class load_immI(rRegI dst, immI src)
duke@0 2151 %{
duke@0 2152 int dstenc = $dst$$reg;
duke@0 2153 if (dstenc >= 8) {
duke@0 2154 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2155 dstenc -= 8;
duke@0 2156 }
duke@0 2157 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2158 $$$emit32$src$$constant;
duke@0 2159 %}
duke@0 2160
duke@0 2161 enc_class load_immL(rRegL dst, immL src)
duke@0 2162 %{
duke@0 2163 int dstenc = $dst$$reg;
duke@0 2164 if (dstenc < 8) {
duke@0 2165 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2166 } else {
duke@0 2167 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2168 dstenc -= 8;
duke@0 2169 }
duke@0 2170 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2171 emit_d64(cbuf, $src$$constant);
duke@0 2172 %}
duke@0 2173
duke@0 2174 enc_class load_immUL32(rRegL dst, immUL32 src)
duke@0 2175 %{
duke@0 2176 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2177 int dstenc = $dst$$reg;
duke@0 2178 if (dstenc >= 8) {
duke@0 2179 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2180 dstenc -= 8;
duke@0 2181 }
duke@0 2182 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2183 $$$emit32$src$$constant;
duke@0 2184 %}
duke@0 2185
duke@0 2186 enc_class load_immL32(rRegL dst, immL32 src)
duke@0 2187 %{
duke@0 2188 int dstenc = $dst$$reg;
duke@0 2189 if (dstenc < 8) {
duke@0 2190 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2191 } else {
duke@0 2192 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2193 dstenc -= 8;
duke@0 2194 }
duke@0 2195 emit_opcode(cbuf, 0xC7);
duke@0 2196 emit_rm(cbuf, 0x03, 0x00, dstenc);
duke@0 2197 $$$emit32$src$$constant;
duke@0 2198 %}
duke@0 2199
duke@0 2200 enc_class load_immP31(rRegP dst, immP32 src)
duke@0 2201 %{
duke@0 2202 // same as load_immI, but this time we care about zeroes in the high word
duke@0 2203 int dstenc = $dst$$reg;
duke@0 2204 if (dstenc >= 8) {
duke@0 2205 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2206 dstenc -= 8;
duke@0 2207 }
duke@0 2208 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2209 $$$emit32$src$$constant;
duke@0 2210 %}
duke@0 2211
duke@0 2212 enc_class load_immP(rRegP dst, immP src)
duke@0 2213 %{
duke@0 2214 int dstenc = $dst$$reg;
duke@0 2215 if (dstenc < 8) {
duke@0 2216 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2217 } else {
duke@0 2218 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2219 dstenc -= 8;
duke@0 2220 }
duke@0 2221 emit_opcode(cbuf, 0xB8 | dstenc);
duke@0 2222 // This next line should be generated from ADLC
coleenp@3602 2223 if ($src->constant_reloc() != relocInfo::none) {
coleenp@3602 2224 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
duke@0 2225 } else {
duke@0 2226 emit_d64(cbuf, $src$$constant);
duke@0 2227 }
duke@0 2228 %}
duke@0 2229
duke@0 2230 enc_class Con32(immI src)
duke@0 2231 %{
duke@0 2232 // Output immediate
duke@0 2233 $$$emit32$src$$constant;
duke@0 2234 %}
duke@0 2235
duke@0 2236 enc_class Con64(immL src)
duke@0 2237 %{
duke@0 2238 // Output immediate
duke@0 2239 emit_d64($src$$constant);
duke@0 2240 %}
duke@0 2241
duke@0 2242 enc_class Con32F_as_bits(immF src)
duke@0 2243 %{
duke@0 2244 // Output Float immediate bits
duke@0 2245 jfloat jf = $src$$constant;
duke@0 2246 jint jf_as_bits = jint_cast(jf);
duke@0 2247 emit_d32(cbuf, jf_as_bits);
duke@0 2248 %}
duke@0 2249
duke@0 2250 enc_class Con16(immI src)
duke@0 2251 %{
duke@0 2252 // Output immediate
duke@0 2253 $$$emit16$src$$constant;
duke@0 2254 %}
duke@0 2255
duke@0 2256 // How is this different from Con32??? XXX
duke@0 2257 enc_class Con_d32(immI src)
duke@0 2258 %{
duke@0 2259 emit_d32(cbuf,$src$$constant);
duke@0 2260 %}
duke@0 2261
duke@0 2262 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
duke@0 2263 // Output immediate memory reference
duke@0 2264 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
duke@0 2265 emit_d32(cbuf, 0x00);
duke@0 2266 %}
duke@0 2267
duke@0 2268 enc_class lock_prefix()
duke@0 2269 %{
duke@0 2270 if (os::is_MP()) {
duke@0 2271 emit_opcode(cbuf, 0xF0); // lock
duke@0 2272 }
duke@0 2273 %}
duke@0 2274
duke@0 2275 enc_class REX_mem(memory mem)
duke@0 2276 %{
duke@0 2277 if ($mem$$base >= 8) {
duke@0 2278 if ($mem$$index < 8) {
duke@0 2279 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2280 } else {
duke@0 2281 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2282 }
duke@0 2283 } else {
duke@0 2284 if ($mem$$index >= 8) {
duke@0 2285 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2286 }
duke@0 2287 }
duke@0 2288 %}
duke@0 2289
duke@0 2290 enc_class REX_mem_wide(memory mem)
duke@0 2291 %{
duke@0 2292 if ($mem$$base >= 8) {
duke@0 2293 if ($mem$$index < 8) {
duke@0 2294 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2295 } else {
duke@0 2296 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2297 }
duke@0 2298 } else {
duke@0 2299 if ($mem$$index < 8) {
duke@0 2300 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2301 } else {
duke@0 2302 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2303 }
duke@0 2304 }
duke@0 2305 %}
duke@0 2306
duke@0 2307 // for byte regs
duke@0 2308 enc_class REX_breg(rRegI reg)
duke@0 2309 %{
duke@0 2310 if ($reg$$reg >= 4) {
duke@0 2311 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2312 }
duke@0 2313 %}
duke@0 2314
duke@0 2315 // for byte regs
duke@0 2316 enc_class REX_reg_breg(rRegI dst, rRegI src)
duke@0 2317 %{
duke@0 2318 if ($dst$$reg < 8) {
duke@0 2319 if ($src$$reg >= 4) {
duke@0 2320 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2321 }
duke@0 2322 } else {
duke@0 2323 if ($src$$reg < 8) {
duke@0 2324 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2325 } else {
duke@0 2326 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2327 }
duke@0 2328 }
duke@0 2329 %}
duke@0 2330
duke@0 2331 // for byte regs
duke@0 2332 enc_class REX_breg_mem(rRegI reg, memory mem)
duke@0 2333 %{
duke@0 2334 if ($reg$$reg < 8) {
duke@0 2335 if ($mem$$base < 8) {
duke@0 2336 if ($mem$$index >= 8) {
duke@0 2337 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2338 } else if ($reg$$reg >= 4) {
duke@0 2339 emit_opcode(cbuf, Assembler::REX);
duke@0 2340 }
duke@0 2341 } else {
duke@0 2342 if ($mem$$index < 8) {
duke@0 2343 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2344 } else {
duke@0 2345 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2346 }
duke@0 2347 }
duke@0 2348 } else {
duke@0 2349 if ($mem$$base < 8) {
duke@0 2350 if ($mem$$index < 8) {
duke@0 2351 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2352 } else {
duke@0 2353 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2354 }
duke@0 2355 } else {
duke@0 2356 if ($mem$$index < 8) {
duke@0 2357 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2358 } else {
duke@0 2359 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2360 }
duke@0 2361 }
duke@0 2362 }
duke@0 2363 %}
duke@0 2364
duke@0 2365 enc_class REX_reg(rRegI reg)
duke@0 2366 %{
duke@0 2367 if ($reg$$reg >= 8) {
duke@0 2368 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2369 }
duke@0 2370 %}
duke@0 2371
duke@0 2372 enc_class REX_reg_wide(rRegI reg)
duke@0 2373 %{
duke@0 2374 if ($reg$$reg < 8) {
duke@0 2375 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2376 } else {
duke@0 2377 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2378 }
duke@0 2379 %}
duke@0 2380
duke@0 2381 enc_class REX_reg_reg(rRegI dst, rRegI src)
duke@0 2382 %{
duke@0 2383 if ($dst$$reg < 8) {
duke@0 2384 if ($src$$reg >= 8) {
duke@0 2385 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2386 }
duke@0 2387 } else {
duke@0 2388 if ($src$$reg < 8) {
duke@0 2389 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2390 } else {
duke@0 2391 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2392 }
duke@0 2393 }
duke@0 2394 %}
duke@0 2395
duke@0 2396 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
duke@0 2397 %{
duke@0 2398 if ($dst$$reg < 8) {
duke@0 2399 if ($src$$reg < 8) {
duke@0 2400 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2401 } else {
duke@0 2402 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2403 }
duke@0 2404 } else {
duke@0 2405 if ($src$$reg < 8) {
duke@0 2406 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2407 } else {
duke@0 2408 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2409 }
duke@0 2410 }
duke@0 2411 %}
duke@0 2412
duke@0 2413 enc_class REX_reg_mem(rRegI reg, memory mem)
duke@0 2414 %{
duke@0 2415 if ($reg$$reg < 8) {
duke@0 2416 if ($mem$$base < 8) {
duke@0 2417 if ($mem$$index >= 8) {
duke@0 2418 emit_opcode(cbuf, Assembler::REX_X);
duke@0 2419 }
duke@0 2420 } else {
duke@0 2421 if ($mem$$index < 8) {
duke@0 2422 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2423 } else {
duke@0 2424 emit_opcode(cbuf, Assembler::REX_XB);
duke@0 2425 }
duke@0 2426 }
duke@0 2427 } else {
duke@0 2428 if ($mem$$base < 8) {
duke@0 2429 if ($mem$$index < 8) {
duke@0 2430 emit_opcode(cbuf, Assembler::REX_R);
duke@0 2431 } else {
duke@0 2432 emit_opcode(cbuf, Assembler::REX_RX);
duke@0 2433 }
duke@0 2434 } else {
duke@0 2435 if ($mem$$index < 8) {
duke@0 2436 emit_opcode(cbuf, Assembler::REX_RB);
duke@0 2437 } else {
duke@0 2438 emit_opcode(cbuf, Assembler::REX_RXB);
duke@0 2439 }
duke@0 2440 }
duke@0 2441 }
duke@0 2442 %}
duke@0 2443
duke@0 2444 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
duke@0 2445 %{
duke@0 2446 if ($reg$$reg < 8) {
duke@0 2447 if ($mem$$base < 8) {
duke@0 2448 if ($mem$$index < 8) {
duke@0 2449 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2450 } else {
duke@0 2451 emit_opcode(cbuf, Assembler::REX_WX);
duke@0 2452 }
duke@0 2453 } else {
duke@0 2454 if ($mem$$index < 8) {
duke@0 2455 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2456 } else {
duke@0 2457 emit_opcode(cbuf, Assembler::REX_WXB);
duke@0 2458 }
duke@0 2459 }
duke@0 2460 } else {
duke@0 2461 if ($mem$$base < 8) {
duke@0 2462 if ($mem$$index < 8) {
duke@0 2463 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2464 } else {
duke@0 2465 emit_opcode(cbuf, Assembler::REX_WRX);
duke@0 2466 }
duke@0 2467 } else {
duke@0 2468 if ($mem$$index < 8) {
duke@0 2469 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2470 } else {
duke@0 2471 emit_opcode(cbuf, Assembler::REX_WRXB);
duke@0 2472 }
duke@0 2473 }
duke@0 2474 }
duke@0 2475 %}
duke@0 2476
duke@0 2477 enc_class reg_mem(rRegI ereg, memory mem)
duke@0 2478 %{
duke@0 2479 // High registers handle in encode_RegMem
duke@0 2480 int reg = $ereg$$reg;
duke@0 2481 int base = $mem$$base;
duke@0 2482 int index = $mem$$index;
duke@0 2483 int scale = $mem$$scale;
duke@0 2484 int disp = $mem$$disp;
coleenp@3602 2485 relocInfo::relocType disp_reloc = $mem->disp_reloc();
coleenp@3602 2486
coleenp@3602 2487 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
duke@0 2488 %}
duke@0 2489
duke@0 2490 enc_class RM_opc_mem(immI rm_opcode, memory mem)
duke@0 2491 %{
duke@0 2492 int rm_byte_opcode = $rm_opcode$$constant;
duke@0 2493
duke@0 2494 // High registers handle in encode_RegMem
duke@0 2495 int base = $mem$$base;
duke@0 2496 int index = $mem$$index;
duke@0 2497 int scale = $mem$$scale;
duke@0 2498 int displace = $mem$$disp;
duke@0 2499
coleenp@3602 2500 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
duke@0 2501 // working with static
duke@0 2502 // globals
duke@0 2503 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
coleenp@3602 2504 disp_reloc);
duke@0 2505 %}
duke@0 2506
duke@0 2507 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
duke@0 2508 %{
duke@0 2509 int reg_encoding = $dst$$reg;
duke@0 2510 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
duke@0 2511 int index = 0x04; // 0x04 indicates no index
duke@0 2512 int scale = 0x00; // 0x00 indicates no scale
duke@0 2513 int displace = $src1$$constant; // 0x00 indicates no displacement
coleenp@3602 2514 relocInfo::relocType disp_reloc = relocInfo::none;
duke@0 2515 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
coleenp@3602 2516 disp_reloc);
duke@0 2517 %}
duke@0 2518
duke@0 2519 enc_class neg_reg(rRegI dst)
duke@0 2520 %{
duke@0 2521 int dstenc = $dst$$reg;
duke@0 2522 if (dstenc >= 8) {
duke@0 2523 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2524 dstenc -= 8;
duke@0 2525 }
duke@0 2526 // NEG $dst
duke@0 2527 emit_opcode(cbuf, 0xF7);
duke@0 2528 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2529 %}
duke@0 2530
duke@0 2531 enc_class neg_reg_wide(rRegI dst)
duke@0 2532 %{
duke@0 2533 int dstenc = $dst$$reg;
duke@0 2534 if (dstenc < 8) {
duke@0 2535 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2536 } else {
duke@0 2537 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2538 dstenc -= 8;
duke@0 2539 }
duke@0 2540 // NEG $dst
duke@0 2541 emit_opcode(cbuf, 0xF7);
duke@0 2542 emit_rm(cbuf, 0x3, 0x03, dstenc);
duke@0 2543 %}
duke@0 2544
duke@0 2545 enc_class setLT_reg(rRegI dst)
duke@0 2546 %{
duke@0 2547 int dstenc = $dst$$reg;
duke@0 2548 if (dstenc >= 8) {
duke@0 2549 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2550 dstenc -= 8;
duke@0 2551 } else if (dstenc >= 4) {
duke@0 2552 emit_opcode(cbuf, Assembler::REX);
duke@0 2553 }
duke@0 2554 // SETLT $dst
duke@0 2555 emit_opcode(cbuf, 0x0F);
duke@0 2556 emit_opcode(cbuf, 0x9C);
duke@0 2557 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2558 %}
duke@0 2559
duke@0 2560 enc_class setNZ_reg(rRegI dst)
duke@0 2561 %{
duke@0 2562 int dstenc = $dst$$reg;
duke@0 2563 if (dstenc >= 8) {
duke@0 2564 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2565 dstenc -= 8;
duke@0 2566 } else if (dstenc >= 4) {
duke@0 2567 emit_opcode(cbuf, Assembler::REX);
duke@0 2568 }
duke@0 2569 // SETNZ $dst
duke@0 2570 emit_opcode(cbuf, 0x0F);
duke@0 2571 emit_opcode(cbuf, 0x95);
duke@0 2572 emit_rm(cbuf, 0x3, 0x0, dstenc);
duke@0 2573 %}
duke@0 2574
duke@0 2575
duke@0 2576 // Compare the lonogs and set -1, 0, or 1 into dst
duke@0 2577 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
duke@0 2578 %{
duke@0 2579 int src1enc = $src1$$reg;
duke@0 2580 int src2enc = $src2$$reg;
duke@0 2581 int dstenc = $dst$$reg;
duke@0 2582
duke@0 2583 // cmpq $src1, $src2
duke@0 2584 if (src1enc < 8) {
duke@0 2585 if (src2enc < 8) {
duke@0 2586 emit_opcode(cbuf, Assembler::REX_W);
duke@0 2587 } else {
duke@0 2588 emit_opcode(cbuf, Assembler::REX_WB);
duke@0 2589 }
duke@0 2590 } else {
duke@0 2591 if (src2enc < 8) {
duke@0 2592 emit_opcode(cbuf, Assembler::REX_WR);
duke@0 2593 } else {
duke@0 2594 emit_opcode(cbuf, Assembler::REX_WRB);
duke@0 2595 }
duke@0 2596 }
duke@0 2597 emit_opcode(cbuf, 0x3B);
duke@0 2598 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
duke@0 2599
duke@0 2600 // movl $dst, -1
duke@0 2601 if (dstenc >= 8) {
duke@0 2602 emit_opcode(cbuf, Assembler::REX_B);
duke@0 2603 }
duke@0 2604 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
duke@0 2605 emit_d32(cbuf, -1);
duke@0 2606
duke@0 2607 // jl,s done
duke@0 2608 emit_opcode(cbuf, 0x7C);
duke@0 2609 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
duke@0 2610
duke@0 2611 // setne $dst
duke@0 2612 if (dstenc >= 4) {
duke@0 2613 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
duke@0 2614 }
duke@0 2615 emit_opcode(cbuf, 0x0F);
duke@0 2616 emit_opcode(cbuf, 0x95);
duke@0 2617 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
duke@0 2618
duke@0 2619 // movzbl $dst, $dst
duke@0 2620 if (dstenc >= 4) {
duke@0 2621 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
duke@0 2622 }
duke@0 2623 emit_opcode(cbuf, 0x0F);
duke@0 2624 emit_opcode(cbuf, 0xB6);
duke@0 2625 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
duke@0 2626 %}
duke@0 2627
duke@0 2628 enc_class Push_ResultXD(regD dst) %{
kvn@2953 2629 MacroAssembler _masm(&cbuf);
kvn@2953 2630 __ fstp_d(Address(rsp, 0));
kvn@2953 2631 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
kvn@2953 2632 __ addptr(rsp, 8);
duke@0 2633 %}
duke@0 2634
duke@0 2635 enc_class Push_SrcXD(regD src) %{
duke@0 2636 MacroAssembler _masm(&cbuf);
kvn@2953 2637 __ subptr(rsp, 8);
kvn@2953 2638 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
kvn@2953 2639 __ fld_d(Address(rsp, 0));
kvn@2953 2640 %}
kvn@2953 2641
duke@0 2642
duke@0 2643 // obj: object to lock
duke@0 2644 // box: box address (header location) -- killed
duke@0 2645 // tmp: rax -- killed
duke@0 2646 // scr: rbx -- killed
duke@0 2647 //
duke@0 2648 // What follows is a direct transliteration of fast_lock() and fast_unlock()
duke@0 2649 // from i486.ad. See that file for comments.
duke@0 2650 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
duke@0 2651 // use the shorter encoding. (Movl clears the high-order 32-bits).
duke@0 2652
duke@0 2653
duke@0 2654 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
duke@0 2655 %{
duke@0 2656 Register objReg = as_Register((int)$obj$$reg);
duke@0 2657 Register boxReg = as_Register((int)$box$$reg);
duke@0 2658 Register tmpReg = as_Register($tmp$$reg);
duke@0 2659 Register scrReg = as_Register($scr$$reg);
duke@0 2660 MacroAssembler masm(&cbuf);
duke@0 2661
duke@0 2662 // Verify uniqueness of register assignments -- necessary but not sufficient
duke@0 2663 assert (objReg != boxReg && objReg != tmpReg &&
duke@0 2664 objReg != scrReg && tmpReg != scrReg, "invariant") ;
duke@0 2665
duke@0 2666 if (_counters != NULL) {
duke@0 2667 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
duke@0 2668 }
duke@0 2669 if (EmitSync & 1) {
never@304 2670 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 2671 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 2672 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
duke@0 2673 } else
duke@0 2674 if (EmitSync & 2) {
duke@0 2675 Label DONE_LABEL;
duke@0 2676 if (UseBiasedLocking) {
duke@0 2677 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
duke@0 2678 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
duke@0 2679 }
never@304 2680 // QQQ was movl...
never@304 2681 masm.movptr(tmpReg, 0x1);
never@304 2682 masm.orptr(tmpReg, Address(objReg, 0));
never@304 2683 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2684 if (os::is_MP()) {
duke@0 2685 masm.lock();
duke@0 2686 }
never@304 2687 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 2688 masm.jcc(Assembler::equal, DONE_LABEL);
duke@0 2689
duke@0 2690 // Recursive locking
never@304 2691 masm.subptr(tmpReg, rsp);
never@304 2692 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 2693 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2694
duke@0 2695 masm.bind(DONE_LABEL);
duke@0 2696 masm.nop(); // avoid branch to branch
duke@0 2697 } else {
duke@0 2698 Label DONE_LABEL, IsInflated, Egress;
duke@0 2699
iveresov@2251 2700 masm.movptr(tmpReg, Address(objReg, 0)) ;
never@304 2701 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
iveresov@2251 2702 masm.jcc (Assembler::notZero, IsInflated) ;
iveresov@2251 2703
duke@0 2704 // it's stack-locked, biased or neutral
duke@0 2705 // TODO: optimize markword triage order to reduce the number of
duke@0 2706 // conditional branches in the most common cases.
duke@0 2707 // Beware -- there's a subtle invariant that fetch of the markword
duke@0 2708 // at [FETCH], below, will never observe a biased encoding (*101b).
duke@0 2709 // If this invariant is not held we'll suffer exclusion (safety) failure.
duke@0 2710
kvn@420 2711 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 2712 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
never@304 2713 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
duke@0 2714 }
duke@0 2715
never@304 2716 // was q will it destroy high?
iveresov@2251 2717 masm.orl (tmpReg, 1) ;
iveresov@2251 2718 masm.movptr(Address(boxReg, 0), tmpReg) ;
iveresov@2251 2719 if (os::is_MP()) { masm.lock(); }
never@304 2720 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
duke@0 2721 if (_counters != NULL) {
duke@0 2722 masm.cond_inc32(Assembler::equal,
duke@0 2723 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 2724 }
duke@0 2725 masm.jcc (Assembler::equal, DONE_LABEL);
duke@0 2726
duke@0 2727 // Recursive locking
never@304 2728 masm.subptr(tmpReg, rsp);
never@304 2729 masm.andptr(tmpReg, 7 - os::vm_page_size());
never@304 2730 masm.movptr(Address(boxReg, 0), tmpReg);
duke@0 2731 if (_counters != NULL) {
duke@0 2732 masm.cond_inc32(Assembler::equal,
duke@0 2733 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
duke@0 2734 }
duke@0 2735 masm.jmp (DONE_LABEL) ;
duke@0 2736
duke@0 2737 masm.bind (IsInflated) ;
duke@0 2738 // It's inflated
duke@0 2739
duke@0 2740 // TODO: someday avoid the ST-before-CAS penalty by
duke@0 2741 // relocating (deferring) the following ST.
duke@0 2742 // We should also think about trying a CAS without having
duke@0 2743 // fetched _owner. If the CAS is successful we may
duke@0 2744 // avoid an RTO->RTS upgrade on the $line.
never@304 2745 // Without cast to int32_t a movptr will destroy r10 which is typically obj
iveresov@2251 2746 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
iveresov@2251 2747
iveresov@2251 2748 masm.mov (boxReg, tmpReg) ;
iveresov@2251 2749 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 2750 masm.testptr(tmpReg, tmpReg) ;
iveresov@2251 2751 masm.jcc (Assembler::notZero, DONE_LABEL) ;
duke@0 2752
duke@0 2753 // It's inflated and appears unlocked
iveresov@2251 2754 if (os::is_MP()) { masm.lock(); }
iveresov@2251 2755 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
duke@0 2756 // Intentional fall-through into DONE_LABEL ...
duke@0 2757
duke@0 2758 masm.bind (DONE_LABEL) ;
duke@0 2759 masm.nop () ; // avoid jmp to jmp
duke@0 2760 }
duke@0 2761 %}
duke@0 2762
duke@0 2763 // obj: object to unlock
duke@0 2764 // box: box address (displaced header location), killed
duke@0 2765 // RBX: killed tmp; cannot be obj nor box
duke@0 2766 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
duke@0 2767 %{
duke@0 2768
duke@0 2769 Register objReg = as_Register($obj$$reg);
duke@0 2770 Register boxReg = as_Register($box$$reg);
duke@0 2771 Register tmpReg = as_Register($tmp$$reg);
duke@0 2772 MacroAssembler masm(&cbuf);
duke@0 2773
iveresov@2251 2774 if (EmitSync & 4) {
iveresov@2251 2775 masm.cmpptr(rsp, 0) ;
duke@0 2776 } else
duke@0 2777 if (EmitSync & 8) {
duke@0 2778 Label DONE_LABEL;
duke@0 2779 if (UseBiasedLocking) {
duke@0 2780 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 2781 }
duke@0 2782
duke@0 2783 // Check whether the displaced header is 0
duke@0 2784 //(=> recursive unlock)
never@304 2785 masm.movptr(tmpReg, Address(boxReg, 0));
never@304 2786 masm.testptr(tmpReg, tmpReg);
duke@0 2787 masm.jcc(Assembler::zero, DONE_LABEL);
duke@0 2788
duke@0 2789 // If not recursive lock, reset the header to displaced header
duke@0 2790 if (os::is_MP()) {
duke@0 2791 masm.lock();
duke@0 2792 }
never@304 2793 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 2794 masm.bind(DONE_LABEL);
duke@0 2795 masm.nop(); // avoid branch to branch
duke@0 2796 } else {
duke@0 2797 Label DONE_LABEL, Stacked, CheckSucc ;
duke@0 2798
kvn@420 2799 if (UseBiasedLocking && !UseOptoBiasInlining) {
duke@0 2800 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
duke@0 2801 }
iveresov@2251 2802
iveresov@2251 2803 masm.movptr(tmpReg, Address(objReg, 0)) ;
iveresov@2251 2804 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
iveresov@2251 2805 masm.jcc (Assembler::zero, DONE_LABEL) ;
iveresov@2251 2806 masm.testl (tmpReg, 0x02) ;
iveresov@2251 2807 masm.jcc (Assembler::zero, Stacked) ;
iveresov@2251 2808
duke@0 2809 // It's inflated
iveresov@2251 2810 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
iveresov@2251 2811 masm.xorptr(boxReg, r15_thread) ;
iveresov@2251 2812 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
iveresov@2251 2813 masm.jcc (Assembler::notZero, DONE_LABEL) ;
iveresov@2251 2814 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
iveresov@2251 2815 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
iveresov@2251 2816 masm.jcc (Assembler::notZero, CheckSucc) ;
iveresov@2251 2817 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
iveresov@2251 2818 masm.jmp (DONE_LABEL) ;
iveresov@2251 2819
iveresov@2251 2820 if ((EmitSync & 65536) == 0) {
duke@0 2821 Label LSuccess, LGoSlowPath ;
duke@0 2822 masm.bind (CheckSucc) ;
never@304 2823 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2824 masm.jcc (Assembler::zero, LGoSlowPath) ;
duke@0 2825
duke@0 2826 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
duke@0 2827 // the explicit ST;MEMBAR combination, but masm doesn't currently support
duke@0 2828 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
duke@0 2829 // are all faster when the write buffer is populated.
never@304 2830 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2831 if (os::is_MP()) {
never@304 2832 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
duke@0 2833 }
never@304 2834 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
duke@0 2835 masm.jcc (Assembler::notZero, LSuccess) ;
duke@0 2836
never@304 2837 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
duke@0 2838 if (os::is_MP()) { masm.lock(); }
never@304 2839 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
duke@0 2840 masm.jcc (Assembler::notEqual, LSuccess) ;
duke@0 2841 // Intentional fall-through into slow-path
duke@0 2842
duke@0 2843 masm.bind (LGoSlowPath) ;
duke@0 2844 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
duke@0 2845 masm.jmp (DONE_LABEL) ;
duke@0 2846
duke@0 2847 masm.bind (LSuccess) ;
duke@0 2848 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
duke@0 2849 masm.jmp (DONE_LABEL) ;
duke@0 2850 }
duke@0 2851
iveresov@2251 2852 masm.bind (Stacked) ;
never@304 2853 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
iveresov@2251 2854 if (os::is_MP()) { masm.lock(); }
never@304 2855 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
duke@0 2856
duke@0 2857 if (EmitSync & 65536) {
duke@0 2858 masm.bind (CheckSucc) ;
duke@0 2859 }
duke@0 2860 masm.bind(DONE_LABEL);
duke@0 2861 if (EmitSync & 32768) {
duke@0 2862 masm.nop(); // avoid branch to branch
duke@0 2863 }
duke@0 2864 }
duke@0 2865 %}
duke@0 2866
rasbold@169 2867
duke@0 2868 enc_class enc_rethrow()
duke@0 2869 %{
twisti@1668 2870 cbuf.set_insts_mark();
duke@0 2871 emit_opcode(cbuf, 0xE9); // jmp entry
duke@0 2872 emit_d32_reloc(cbuf,
twisti@1668 2873 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
duke@0 2874 runtime_call_Relocation::spec(),
duke@0 2875 RELOC_DISP32);
duke@0 2876 %}
duke@0 2877
duke@0 2878 %}
duke@0 2879
duke@0 2880
coleenp@113 2881
duke@0 2882 //----------FRAME--------------------------------------------------------------
duke@0 2883 // Definition of frame structure and management information.
duke@0 2884 //
duke@0 2885 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 2886 // | (to get allocators register number
duke@0 2887 // G Owned by | | v add OptoReg::stack0())
duke@0 2888 // r CALLER | |
duke@0 2889 // o | +--------+ pad to even-align allocators stack-slot
duke@0 2890 // w V | pad0 | numbers; owned by CALLER
duke@0 2891 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 2892 // h ^ | in | 5
duke@0 2893 // | | args | 4 Holes in incoming args owned by SELF
duke@0 2894 // | | | | 3
duke@0 2895 // | | +--------+
duke@0 2896 // V | | old out| Empty on Intel, window on Sparc
duke@0 2897 // | old |preserve| Must be even aligned.
duke@0 2898 // | SP-+--------+----> Matcher::_old_SP, even aligned
duke@0 2899 // | | in | 3 area for Intel ret address
duke@0 2900 // Owned by |preserve| Empty on Sparc.
duke@0 2901 // SELF +--------+
duke@0 2902 // | | pad2 | 2 pad to align old SP
duke@0 2903 // | +--------+ 1
duke@0 2904 // | | locks | 0
duke@0 2905 // | +--------+----> OptoReg::stack0(), even aligned
duke@0 2906 // | | pad1 | 11 pad to align new SP
duke@0 2907 // | +--------+
duke@0 2908 // | | | 10
duke@0 2909 // | | spills | 9 spills
duke@0 2910 // V | | 8 (pad0 slot for callee)
duke@0 2911 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 2912 // ^ | out | 7
duke@0 2913 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 2914 // Owned by +--------+
duke@0 2915 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 2916 // | new |preserve| Must be even-aligned.
duke@0 2917 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 2918 // | | |
duke@0 2919 //
duke@0 2920 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 2921 // known from SELF's arguments and the Java calling convention.
duke@0 2922 // Region 6-7 is determined per call site.
duke@0 2923 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 2924 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 2925 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 2926 // incoming area, as the Java calling convention is completely under
duke@0 2927 // the control of the AD file. Doubles can be sorted and packed to
duke@0 2928 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 2929 // varargs C calling conventions.
duke@0 2930 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 2931 // even aligned with pad0 as needed.
duke@0 2932 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 2933 // region 6-11 is even aligned; it may be padded out more so that
duke@0 2934 // the region from SP to FP meets the minimum stack alignment.
duke@0 2935 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
duke@0 2936 // alignment. Region 11, pad1, may be dynamically extended so that
duke@0 2937 // SP meets the minimum alignment.
duke@0 2938
duke@0 2939 frame
duke@0 2940 %{
duke@0 2941 // What direction does stack grow in (assumed to be same for C & Java)
duke@0 2942 stack_direction(TOWARDS_LOW);
duke@0 2943
duke@0 2944 // These three registers define part of the calling convention
duke@0 2945 // between compiled code and the interpreter.
duke@0 2946 inline_cache_reg(RAX); // Inline Cache Register
duke@0 2947 interpreter_method_oop_reg(RBX); // Method Oop Register when
duke@0 2948 // calling interpreter
duke@0 2949
duke@0 2950 // Optional: name the operand used by cisc-spilling to access
duke@0 2951 // [stack_pointer + offset]
duke@0 2952 cisc_spilling_operand_name(indOffset32);
duke@0 2953
duke@0 2954 // Number of stack slots consumed by locking an object
duke@0 2955 sync_stack_slots(2);
duke@0 2956
duke@0 2957 // Compiled code's Frame Pointer
duke@0 2958 frame_pointer(RSP);
duke@0 2959
duke@0 2960 // Interpreter stores its frame pointer in a register which is
duke@0 2961 // stored to the stack by I2CAdaptors.
duke@0 2962 // I2CAdaptors convert from interpreted java to compiled java.
duke@0 2963 interpreter_frame_pointer(RBP);
duke@0 2964
duke@0 2965 // Stack alignment requirement
duke@0 2966 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
duke@0 2967
duke@0 2968 // Number of stack slots between incoming argument block and the start of
duke@0 2969 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 2970 // EPILOG must remove this many slots. amd64 needs two slots for
duke@0 2971 // return address.
duke@0 2972 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
duke@0 2973
duke@0 2974 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 2975 // for calls to C. Supports the var-args backing area for register parms.
duke@0 2976 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
duke@0 2977
duke@0 2978 // The after-PROLOG location of the return address. Location of
duke@0 2979 // return address specifies a type (REG or STACK) and a number
duke@0 2980 // representing the register number (i.e. - use a register name) or
duke@0 2981 // stack slot.
duke@0 2982 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
duke@0 2983 // Otherwise, it is above the locks and verification slot and alignment word
duke@0 2984 return_addr(STACK - 2 +
kvn@3142 2985 round_to((Compile::current()->in_preserve_stack_slots() +
kvn@3142 2986 Compile::current()->fixed_slots()),
kvn@3142 2987 stack_alignment_in_slots()));
duke@0 2988
duke@0 2989 // Body of function which returns an integer array locating
duke@0 2990 // arguments either in registers or in stack slots. Passed an array
duke@0 2991 // of ideal registers called "sig" and a "length" count. Stack-slot
duke@0 2992 // offsets are based on outgoing arguments, i.e. a CALLER setting up
duke@0 2993 // arguments for a CALLEE. Incoming stack arguments are
duke@0 2994 // automatically biased by the preserve_stack_slots field above.
duke@0 2995
duke@0 2996 calling_convention
duke@0 2997 %{
duke@0 2998 // No difference between ingoing/outgoing just pass false
duke@0 2999 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
duke@0 3000 %}
duke@0 3001
duke@0 3002 c_calling_convention
duke@0 3003 %{
duke@0 3004 // This is obviously always outgoing
duke@0 3005 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
duke@0 3006 %}
duke@0 3007
duke@0 3008 // Location of compiled Java return values. Same as C for now.
duke@0 3009 return_value
duke@0 3010 %{
duke@0 3011 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
duke@0 3012 "only return normal values");
duke@0 3013
duke@0 3014 static const int lo[Op_RegL + 1] = {
duke@0 3015 0,
duke@0 3016 0,
coleenp@113 3017 RAX_num, // Op_RegN
duke@0 3018 RAX_num, // Op_RegI
duke@0 3019 RAX_num, // Op_RegP
duke@0 3020 XMM0_num, // Op_RegF
duke@0 3021 XMM0_num, // Op_RegD
duke@0 3022 RAX_num // Op_RegL
duke@0 3023 };
duke@0 3024 static const int hi[Op_RegL + 1] = {
duke@0 3025 0,
duke@0 3026 0,
coleenp@113 3027 OptoReg::Bad, // Op_RegN
duke@0 3028 OptoReg::Bad, // Op_RegI
duke@0 3029 RAX_H_num, // Op_RegP
duke@0 3030 OptoReg::Bad, // Op_RegF
kvn@3447 3031 XMM0b_num, // Op_RegD
duke@0 3032 RAX_H_num // Op_RegL
duke@0 3033 };
kvn@3447 3034 // Excluded flags and vector registers.
kvn@3447 3035 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
duke@0 3036 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
duke@0 3037 %}
duke@0 3038 %}
duke@0 3039
duke@0 3040 //----------ATTRIBUTES---------------------------------------------------------
duke@0 3041 //----------Operand Attributes-------------------------------------------------
duke@0 3042 op_attrib op_cost(0); // Required cost attribute
duke@0 3043
duke@0 3044 //----------Instruction Attributes---------------------------------------------
duke@0 3045 ins_attrib ins_cost(100); // Required cost attribute
duke@0 3046 ins_attrib ins_size(8); // Required size attribute (in bits)
duke@0 3047 ins_attrib ins_short_branch(0); // Required flag: is this instruction
duke@0 3048 // a non-matching short branch variant
duke@0 3049 // of some long branch?
duke@0 3050 ins_attrib ins_alignment(1); // Required alignment attribute (must
duke@0 3051 // be a power of 2) specifies the
duke@0 3052 // alignment that some part of the
duke@0 3053 // instruction (not necessarily the
duke@0 3054 // start) requires. If > 1, a
duke@0 3055 // compute_padding() function must be
duke@0 3056 // provided for the instruction
duke@0 3057
duke@0 3058 //----------OPERANDS-----------------------------------------------------------
duke@0 3059 // Operand definitions must precede instruction definitions for correct parsing
duke@0 3060 // in the ADLC because operands constitute user defined types which are used in
duke@0 3061 // instruction definitions.
duke@0 3062
duke@0 3063 //----------Simple Operands----------------------------------------------------
duke@0 3064 // Immediate Operands
duke@0 3065 // Integer Immediate
duke@0 3066 operand immI()
duke@0 3067 %{
duke@0 3068 match(ConI);
duke@0 3069
duke@0 3070 op_cost(10);
duke@0 3071 format %{ %}
duke@0 3072 interface(CONST_INTER);
duke@0 3073 %}
duke@0 3074
duke@0 3075 // Constant for test vs zero
duke@0 3076 operand immI0()
duke@0 3077 %{
duke@0 3078 predicate(n->get_int() == 0);
duke@0 3079 match(ConI);
duke@0 3080
duke@0 3081 op_cost(0);
duke@0 3082 format %{ %}
duke@0 3083 interface(CONST_INTER);
duke@0 3084 %}
duke@0 3085
duke@0 3086 // Constant for increment
duke@0 3087 operand immI1()
duke@0 3088 %{
duke@0 3089 predicate(n->get_int() == 1);
duke@0 3090 match(ConI);
duke@0 3091
duke@0 3092 op_cost(0);
duke@0 3093 format %{ %}
duke@0 3094 interface(CONST_INTER);
duke@0 3095 %}
duke@0 3096
duke@0 3097 // Constant for decrement
duke@0 3098 operand immI_M1()
duke@0 3099 %{
duke@0 3100 predicate(n->get_int() == -1);
duke@0 3101 match(ConI);
duke@0 3102
duke@0 3103 op_cost(0);
duke@0 3104 format %{ %}
duke@0 3105 interface(CONST_INTER);
duke@0 3106 %}
duke@0 3107
duke@0 3108 // Valid scale values for addressing modes
duke@0 3109 operand immI2()
duke@0 3110 %{
duke@0 3111 predicate(0 <= n->get_int() && (n->get_int() <= 3));
duke@0 3112 match(ConI);
duke@0 3113
duke@0 3114 format %{ %}
duke@0 3115 interface(CONST_INTER);
duke@0 3116 %}
duke@0 3117
duke@0 3118 operand immI8()
duke@0 3119 %{
duke@0 3120 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
duke@0 3121 match(ConI);
duke@0 3122
duke@0 3123 op_cost(5);
duke@0 3124 format %{ %}
duke@0 3125 interface(CONST_INTER);
duke@0 3126 %}
duke@0 3127
duke@0 3128 operand immI16()
duke@0 3129 %{
duke@0 3130 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
duke@0 3131 match(ConI);
duke@0 3132
duke@0 3133 op_cost(10);
duke@0 3134 format %{ %}
duke@0 3135 interface(CONST_INTER);
duke@0 3136 %}
duke@0 3137
duke@0 3138 // Constant for long shifts
duke@0 3139 operand immI_32()
duke@0 3140 %{
duke@0 3141 predicate( n->get_int() == 32 );
duke@0 3142 match(ConI);
duke@0 3143
duke@0 3144 op_cost(0);
duke@0 3145 format %{ %}
duke@0 3146 interface(CONST_INTER);
duke@0 3147 %}
duke@0 3148
duke@0 3149 // Constant for long shifts
duke@0 3150 operand immI_64()
duke@0 3151 %{
duke@0 3152 predicate( n->get_int() == 64 );
duke@0 3153 match(ConI);
duke@0 3154
duke@0 3155 op_cost(0);
duke@0 3156 format %{ %}
duke@0 3157 interface(CONST_INTER);
duke@0 3158 %}
duke@0 3159
duke@0 3160 // Pointer Immediate
duke@0 3161 operand immP()
duke@0 3162 %{
duke@0 3163 match(ConP);
duke@0 3164
duke@0 3165 op_cost(10);
duke@0 3166 format %{ %}
duke@0 3167 interface(CONST_INTER);
duke@0 3168 %}
duke@0 3169
duke@0 3170 // NULL Pointer Immediate
duke@0 3171 operand immP0()
duke@0 3172 %{
duke@0 3173 predicate(n->get_ptr() == 0);
duke@0 3174 match(ConP);
duke@0 3175
duke@0 3176 op_cost(5);
duke@0 3177 format %{ %}
duke@0 3178 interface(CONST_INTER);
duke@0 3179 %}
duke@0 3180
coleenp@113 3181 // Pointer Immediate
coleenp@113 3182 operand immN() %{
coleenp@113 3183 match(ConN);
coleenp@113 3184
coleenp@113 3185 op_cost(10);
coleenp@113 3186 format %{ %}
coleenp@113 3187 interface(CONST_INTER);
coleenp@113 3188 %}
coleenp@113 3189
roland@3724 3190 operand immNKlass() %{
roland@3724 3191 match(ConNKlass);
roland@3724 3192
roland@3724 3193 op_cost(10);
roland@3724 3194 format %{ %}
roland@3724 3195 interface(CONST_INTER);
roland@3724 3196 %}
roland@3724 3197
coleenp@113 3198 // NULL Pointer Immediate
coleenp@113 3199 operand immN0() %{
coleenp@113 3200 predicate(n->get_narrowcon() == 0);
coleenp@113 3201 match(ConN);
coleenp@113 3202
coleenp@113 3203 op_cost(5);
coleenp@113 3204 format %{ %}
coleenp@113 3205 interface(CONST_INTER);
coleenp@113 3206 %}
coleenp@113 3207
duke@0 3208 operand immP31()
duke@0 3209 %{
coleenp@3602 3210 predicate(n->as_Type()->type()->reloc() == relocInfo::none
duke@0 3211 && (n->get_ptr() >> 31) == 0);
duke@0 3212 match(ConP);
duke@0 3213
duke@0 3214 op_cost(5);
duke@0 3215 format %{ %}
duke@0 3216 interface(CONST_INTER);
duke@0 3217 %}
duke@0 3218
coleenp@113 3219
duke@0 3220 // Long Immediate
duke@0 3221 operand immL()
duke@0 3222 %{
duke@0 3223 match(ConL);
duke@0 3224
duke@0 3225 op_cost(20);
duke@0 3226 format %{ %}
duke@0 3227 interface(CONST_INTER);
duke@0 3228 %}
duke@0 3229
duke@0 3230 // Long Immediate 8-bit
duke@0 3231 operand immL8()
duke@0 3232 %{
duke@0 3233 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
duke@0 3234 match(ConL);
duke@0 3235
duke@0 3236 op_cost(5);
duke@0 3237 format %{ %}
duke@0 3238 interface(CONST_INTER);
duke@0 3239 %}
duke@0 3240
duke@0 3241 // Long Immediate 32-bit unsigned
duke@0 3242 operand immUL32()
duke@0 3243 %{
duke@0 3244 predicate(n->get_long() == (unsigned int) (n->get_long()));
duke@0 3245 match(ConL);
duke@0 3246
duke@0 3247 op_cost(10);
duke@0 3248 format %{ %}
duke@0 3249 interface(CONST_INTER);
duke@0 3250 %}
duke@0 3251
duke@0 3252 // Long Immediate 32-bit signed
duke@0 3253 operand immL32()
duke@0 3254 %{
duke@0 3255 predicate(n->get_long() == (int) (n->get_long()));
duke@0 3256 match(ConL);
duke@0 3257
duke@0 3258 op_cost(15);
duke@0 3259 format %{ %}
duke@0 3260 interface(CONST_INTER);
duke@0 3261 %}
duke@0 3262
duke@0 3263 // Long Immediate zero
duke@0 3264 operand immL0()
duke@0 3265 %{
duke@0 3266 predicate(n->get_long() == 0L);
duke@0 3267 match(ConL);
duke@0 3268
duke@0 3269 op_cost(10);
duke@0 3270 format %{ %}
duke@0 3271 interface(CONST_INTER);
duke@0 3272 %}
duke@0 3273
duke@0 3274 // Constant for increment
duke@0 3275 operand immL1()
duke@0 3276 %{
duke@0 3277 predicate(n->get_long() == 1);
duke@0 3278 match(ConL);
duke@0 3279
duke@0 3280 format %{ %}
duke@0 3281 interface(CONST_INTER);
duke@0 3282 %}
duke@0 3283
duke@0 3284 // Constant for decrement
duke@0 3285 operand immL_M1()
duke@0 3286 %{
duke@0 3287 predicate(n->get_long() == -1);
duke@0 3288 match(ConL);
duke@0 3289
duke@0 3290 format %{ %}
duke@0 3291 interface(CONST_INTER);
duke@0 3292 %}
duke@0 3293
duke@0 3294 // Long Immediate: the value 10
duke@0 3295 operand immL10()
duke@0 3296 %{
duke@0 3297 predicate(n->get_long() == 10);
duke@0 3298 match(ConL);
duke@0 3299
duke@0 3300 format %{ %}
duke@0 3301 interface(CONST_INTER);
duke@0 3302 %}
duke@0 3303
duke@0 3304 // Long immediate from 0 to 127.
duke@0 3305 // Used for a shorter form of long mul by 10.
duke@0 3306 operand immL_127()
duke@0 3307 %{
duke@0 3308 predicate(0 <= n->get_long() && n->get_long() < 0x80);
duke@0 3309 match(ConL);
duke@0 3310
duke@0 3311 op_cost(10);
duke@0 3312 format %{ %}
duke@0 3313 interface(CONST_INTER);
duke@0 3314 %}
duke@0 3315
duke@0 3316 // Long Immediate: low 32-bit mask
duke@0 3317 operand immL_32bits()
duke@0 3318 %{
duke@0 3319 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 3320 match(ConL);
duke@0 3321 op_cost(20);
duke@0 3322
duke@0 3323 format %{ %}
duke@0 3324 interface(CONST_INTER);
duke@0 3325 %}
duke@0 3326
duke@0 3327 // Float Immediate zero
duke@0 3328 operand immF0()
duke@0 3329 %{
duke@0 3330 predicate(jint_cast(n->getf()) == 0);
duke@0 3331 match(ConF);
duke@0 3332
duke@0 3333 op_cost(5);
duke@0 3334 format %{ %}
duke@0 3335 interface(CONST_INTER);
duke@0 3336 %}
duke@0 3337
duke@0 3338 // Float Immediate
duke@0 3339 operand immF()
duke@0 3340 %{
duke@0 3341 match(ConF);
duke@0 3342
duke@0 3343 op_cost(15);
duke@0 3344 format %{ %}
duke@0 3345 interface(CONST_INTER);
duke@0 3346 %}
duke@0 3347
duke@0 3348 // Double Immediate zero
duke@0 3349 operand immD0()
duke@0 3350 %{
duke@0 3351 predicate(jlong_cast(n->getd()) == 0);
duke@0 3352 match(ConD);
duke@0 3353
duke@0 3354 op_cost(5);
duke@0 3355 format %{ %}
duke@0 3356 interface(CONST_INTER);
duke@0 3357 %}
duke@0 3358
duke@0 3359 // Double Immediate
duke@0 3360 operand immD()
duke@0 3361 %{
duke@0 3362 match(ConD);
duke@0 3363
duke@0 3364 op_cost(15);
duke@0 3365 format %{ %}
duke@0 3366 interface(CONST_INTER);
duke@0 3367 %}
duke@0 3368
duke@0 3369 // Immediates for special shifts (sign extend)
duke@0 3370
duke@0 3371 // Constants for increment
duke@0 3372 operand immI_16()
duke@0 3373 %{
duke@0 3374 predicate(n->get_int() == 16);
duke@0 3375 match(ConI);
duke@0 3376
duke@0 3377 format %{ %}
duke@0 3378 interface(CONST_INTER);
duke@0 3379 %}
duke@0 3380
duke@0 3381 operand immI_24()
duke@0 3382 %{
duke@0 3383 predicate(n->get_int() == 24);
duke@0 3384 match(ConI);
duke@0 3385
duke@0 3386 format %{ %}
duke@0 3387 interface(CONST_INTER);
duke@0 3388 %}
duke@0 3389
duke@0 3390 // Constant for byte-wide masking
duke@0 3391 operand immI_255()
duke@0 3392 %{
duke@0 3393 predicate(n->get_int() == 255);
duke@0 3394 match(ConI);
duke@0 3395
duke@0 3396 format %{ %}
duke@0 3397 interface(CONST_INTER);
duke@0 3398 %}
duke@0 3399
duke@0 3400 // Constant for short-wide masking
duke@0 3401 operand immI_65535()
duke@0 3402 %{
duke@0 3403 predicate(n->get_int() == 65535);
duke@0 3404 match(ConI);
duke@0 3405
duke@0 3406 format %{ %}
duke@0 3407 interface(CONST_INTER);
duke@0 3408 %}
duke@0 3409
duke@0 3410 // Constant for byte-wide masking
duke@0 3411 operand immL_255()
duke@0 3412 %{
duke@0 3413 predicate(n->get_long() == 255);
duke@0 3414 match(ConL);
duke@0 3415
duke@0 3416 format %{ %}
duke@0 3417 interface(CONST_INTER);
duke@0 3418 %}
duke@0 3419
duke@0 3420 // Constant for short-wide masking
duke@0 3421 operand immL_65535()
duke@0 3422 %{
duke@0 3423 predicate(n->get_long() == 65535);
duke@0 3424 match(ConL);
duke@0 3425
duke@0 3426 format %{ %}
duke@0 3427 interface(CONST_INTER);
duke@0 3428 %}
duke@0 3429
duke@0 3430 // Register Operands
duke@0 3431 // Integer Register
duke@0 3432 operand rRegI()
duke@0 3433 %{
duke@0 3434 constraint(ALLOC_IN_RC(int_reg));
duke@0 3435 match(RegI);
duke@0 3436
duke@0 3437 match(rax_RegI);
duke@0 3438 match(rbx_RegI);
duke@0 3439 match(rcx_RegI);
duke@0 3440 match(rdx_RegI);
duke@0 3441 match(rdi_RegI);
duke@0 3442
duke@0 3443 format %{ %}
duke@0 3444 interface(REG_INTER);
duke@0 3445 %}
duke@0 3446
duke@0 3447 // Special Registers
duke@0 3448 operand rax_RegI()
duke@0 3449 %{
duke@0 3450 constraint(ALLOC_IN_RC(int_rax_reg));
duke@0 3451 match(RegI);
duke@0 3452 match(rRegI);
duke@0 3453
duke@0 3454 format %{ "RAX" %}
duke@0 3455 interface(REG_INTER);
duke@0 3456 %}
duke@0 3457
duke@0 3458 // Special Registers
duke@0 3459 operand rbx_RegI()
duke@0 3460 %{
duke@0 3461 constraint(ALLOC_IN_RC(int_rbx_reg));
duke@0 3462 match(RegI);
duke@0 3463 match(rRegI);
duke@0 3464
duke@0 3465 format %{ "RBX" %}
duke@0 3466 interface(REG_INTER);
duke@0 3467 %}
duke@0 3468
duke@0 3469 operand rcx_RegI()
duke@0 3470 %{
duke@0 3471 constraint(ALLOC_IN_RC(int_rcx_reg));
duke@0 3472 match(RegI);
duke@0 3473 match(rRegI);
duke@0 3474
duke@0 3475 format %{ "RCX" %}
duke@0 3476 interface(REG_INTER);
duke@0 3477 %}
duke@0 3478
duke@0 3479 operand rdx_RegI()
duke@0 3480 %{
duke@0 3481 constraint(ALLOC_IN_RC(int_rdx_reg));
duke@0 3482 match(RegI);
duke@0 3483 match(rRegI);
duke@0 3484
duke@0 3485 format %{ "RDX" %}
duke@0 3486 interface(REG_INTER);
duke@0 3487 %}
duke@0 3488
duke@0 3489 operand rdi_RegI()
duke@0 3490 %{
duke@0 3491 constraint(ALLOC_IN_RC(int_rdi_reg));
duke@0 3492 match(RegI);
duke@0 3493 match(rRegI);
duke@0 3494
duke@0 3495 format %{ "RDI" %}
duke@0 3496 interface(REG_INTER);
duke@0 3497 %}
duke@0 3498
duke@0 3499 operand no_rcx_RegI()
duke@0 3500 %{
duke@0 3501 constraint(ALLOC_IN_RC(int_no_rcx_reg));
duke@0 3502 match(RegI);
duke@0 3503 match(rax_RegI);
duke@0 3504 match(rbx_RegI);
duke@0 3505 match(rdx_RegI);
duke@0 3506 match(rdi_RegI);
duke@0 3507
duke@0 3508 format %{ %}
duke@0 3509 interface(REG_INTER);
duke@0 3510 %}
duke@0 3511
duke@0 3512 operand no_rax_rdx_RegI()
duke@0 3513 %{
duke@0 3514 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
duke@0 3515 match(RegI);
duke@0 3516 match(rbx_RegI);
duke@0 3517 match(rcx_RegI);
duke@0 3518 match(rdi_RegI);
duke@0 3519
duke@0 3520 format %{ %}
duke@0 3521 interface(REG_INTER);
duke@0 3522 %}
duke@0 3523
duke@0 3524 // Pointer Register
duke@0 3525 operand any_RegP()
duke@0 3526 %{
duke@0 3527 constraint(ALLOC_IN_RC(any_reg));
duke@0 3528 match(RegP);
duke@0 3529 match(rax_RegP);
duke@0 3530 match(rbx_RegP);
duke@0 3531 match(rdi_RegP);
duke@0 3532 match(rsi_RegP);
duke@0 3533 match(rbp_RegP);
duke@0 3534 match(r15_RegP);
duke@0 3535 match(rRegP);
duke@0 3536
duke@0 3537 format %{ %}
duke@0 3538 interface(REG_INTER);
duke@0 3539 %}
duke@0 3540
duke@0 3541 operand rRegP()
duke@0 3542 %{
duke@0 3543 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3544 match(RegP);
duke@0 3545 match(rax_RegP);
duke@0 3546 match(rbx_RegP);
duke@0 3547 match(rdi_RegP);
duke@0 3548 match(rsi_RegP);
duke@0 3549 match(rbp_RegP);
duke@0 3550 match(r15_RegP); // See Q&A below about r15_RegP.
duke@0 3551
duke@0 3552 format %{ %}
duke@0 3553 interface(REG_INTER);
duke@0 3554 %}
duke@0 3555
coleenp@113 3556 operand rRegN() %{
coleenp@113 3557 constraint(ALLOC_IN_RC(int_reg));
coleenp@113 3558 match(RegN);
coleenp@113 3559
coleenp@113 3560 format %{ %}
coleenp@113 3561 interface(REG_INTER);
coleenp@113 3562 %}
coleenp@113 3563
duke@0 3564 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
duke@0 3565 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
duke@0 3566 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
duke@0 3567 // The output of an instruction is controlled by the allocator, which respects
duke@0 3568 // register class masks, not match rules. Unless an instruction mentions
duke@0 3569 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
duke@0 3570 // by the allocator as an input.
duke@0 3571
duke@0 3572 operand no_rax_RegP()
duke@0 3573 %{
duke@0 3574 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
duke@0 3575 match(RegP);
duke@0 3576 match(rbx_RegP);
duke@0 3577 match(rsi_RegP);
duke@0 3578 match(rdi_RegP);
duke@0 3579
duke@0 3580 format %{ %}
duke@0 3581 interface(REG_INTER);
duke@0 3582 %}
duke@0 3583
duke@0 3584 operand no_rbp_RegP()
duke@0 3585 %{
duke@0 3586 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
duke@0 3587 match(RegP);
duke@0 3588 match(rbx_RegP);
duke@0 3589 match(rsi_RegP);
duke@0 3590 match(rdi_RegP);
duke@0 3591
duke@0 3592 format %{ %}
duke@0 3593 interface(REG_INTER);
duke@0 3594 %}
duke@0 3595
duke@0 3596 operand no_rax_rbx_RegP()
duke@0 3597 %{
duke@0 3598 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
duke@0 3599 match(RegP);
duke@0 3600 match(rsi_RegP);
duke@0 3601 match(rdi_RegP);
duke@0 3602
duke@0 3603 format %{ %}
duke@0 3604 interface(REG_INTER);
duke@0 3605 %}
duke@0 3606
duke@0 3607 // Special Registers
duke@0 3608 // Return a pointer value
duke@0 3609 operand rax_RegP()
duke@0 3610 %{
duke@0 3611 constraint(ALLOC_IN_RC(ptr_rax_reg));
duke@0 3612 match(RegP);
duke@0 3613 match(rRegP);
duke@0 3614
duke@0 3615 format %{ %}
duke@0 3616 interface(REG_INTER);
duke@0 3617 %}
duke@0 3618
coleenp@113 3619 // Special Registers
coleenp@113 3620 // Return a compressed pointer value
coleenp@113 3621 operand rax_RegN()
coleenp@113 3622 %{
coleenp@113 3623 constraint(ALLOC_IN_RC(int_rax_reg));
coleenp@113 3624 match(RegN);
coleenp@113 3625 match(rRegN);
coleenp@113 3626
coleenp@113 3627 format %{ %}
coleenp@113 3628 interface(REG_INTER);
coleenp@113 3629 %}
coleenp@113 3630
duke@0 3631 // Used in AtomicAdd
duke@0 3632 operand rbx_RegP()
duke@0 3633 %{
duke@0 3634 constraint(ALLOC_IN_RC(ptr_rbx_reg));
duke@0 3635 match(RegP);
duke@0 3636 match(rRegP);
duke@0 3637
duke@0 3638 format %{ %}
duke@0 3639 interface(REG_INTER);
duke@0 3640 %}
duke@0 3641
duke@0 3642 operand rsi_RegP()
duke@0 3643 %{
duke@0 3644 constraint(ALLOC_IN_RC(ptr_rsi_reg));
duke@0 3645 match(RegP);
duke@0 3646 match(rRegP);
duke@0 3647
duke@0 3648 format %{ %}
duke@0 3649 interface(REG_INTER);
duke@0 3650 %}
duke@0 3651
duke@0 3652 // Used in rep stosq
duke@0 3653 operand rdi_RegP()
duke@0 3654 %{
duke@0 3655 constraint(ALLOC_IN_RC(ptr_rdi_reg));
duke@0 3656 match(RegP);
duke@0 3657 match(rRegP);
duke@0 3658
duke@0 3659 format %{ %}
duke@0 3660 interface(REG_INTER);
duke@0 3661 %}
duke@0 3662
duke@0 3663 operand rbp_RegP()
duke@0 3664 %{
duke@0 3665 constraint(ALLOC_IN_RC(ptr_rbp_reg));
duke@0 3666 match(RegP);
duke@0 3667 match(rRegP);
duke@0 3668
duke@0 3669 format %{ %}
duke@0 3670 interface(REG_INTER);
duke@0 3671 %}
duke@0 3672
duke@0 3673 operand r15_RegP()
duke@0 3674 %{
duke@0 3675 constraint(ALLOC_IN_RC(ptr_r15_reg));
duke@0 3676 match(RegP);
duke@0 3677 match(rRegP);
duke@0 3678
duke@0 3679 format %{ %}
duke@0 3680 interface(REG_INTER);
duke@0 3681 %}
duke@0 3682
duke@0 3683 operand rRegL()
duke@0 3684 %{
duke@0 3685 constraint(ALLOC_IN_RC(long_reg));
duke@0 3686 match(RegL);
duke@0 3687 match(rax_RegL);
duke@0 3688 match(rdx_RegL);
duke@0 3689
duke@0 3690 format %{ %}
duke@0 3691 interface(REG_INTER);
duke@0 3692 %}
duke@0 3693
duke@0 3694 // Special Registers
duke@0 3695 operand no_rax_rdx_RegL()
duke@0 3696 %{
duke@0 3697 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3698 match(RegL);
duke@0 3699 match(rRegL);
duke@0 3700
duke@0 3701 format %{ %}
duke@0 3702 interface(REG_INTER);
duke@0 3703 %}
duke@0 3704
duke@0 3705 operand no_rax_RegL()
duke@0 3706 %{
duke@0 3707 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
duke@0 3708 match(RegL);
duke@0 3709 match(rRegL);
duke@0 3710 match(rdx_RegL);
duke@0 3711
duke@0 3712 format %{ %}
duke@0 3713 interface(REG_INTER);
duke@0 3714 %}
duke@0 3715
duke@0 3716 operand no_rcx_RegL()
duke@0 3717 %{
duke@0 3718 constraint(ALLOC_IN_RC(long_no_rcx_reg));
duke@0 3719 match(RegL);
duke@0 3720 match(rRegL);
duke@0 3721
duke@0 3722 format %{ %}
duke@0 3723 interface(REG_INTER);
duke@0 3724 %}
duke@0 3725
duke@0 3726 operand rax_RegL()
duke@0 3727 %{
duke@0 3728 constraint(ALLOC_IN_RC(long_rax_reg));
duke@0 3729 match(RegL);
duke@0 3730 match(rRegL);
duke@0 3731
duke@0 3732 format %{ "RAX" %}
duke@0 3733 interface(REG_INTER);
duke@0 3734 %}
duke@0 3735
duke@0 3736 operand rcx_RegL()
duke@0 3737 %{
duke@0 3738 constraint(ALLOC_IN_RC(long_rcx_reg));
duke@0 3739 match(RegL);
duke@0 3740 match(rRegL);
duke@0 3741
duke@0 3742 format %{ %}
duke@0 3743 interface(REG_INTER);
duke@0 3744 %}
duke@0 3745
duke@0 3746 operand rdx_RegL()
duke@0 3747 %{
duke@0 3748 constraint(ALLOC_IN_RC(long_rdx_reg));
duke@0 3749 match(RegL);
duke@0 3750 match(rRegL);
duke@0 3751
duke@0 3752 format %{ %}
duke@0 3753 interface(REG_INTER);
duke@0 3754 %}
duke@0 3755
duke@0 3756 // Flags register, used as output of compare instructions
duke@0 3757 operand rFlagsReg()
duke@0 3758 %{
duke@0 3759 constraint(ALLOC_IN_RC(int_flags));
duke@0 3760 match(RegFlags);
duke@0 3761
duke@0 3762 format %{ "RFLAGS" %}
duke@0 3763 interface(REG_INTER);
duke@0 3764 %}
duke@0 3765
duke@0 3766 // Flags register, used as output of FLOATING POINT compare instructions
duke@0 3767 operand rFlagsRegU()
duke@0 3768 %{
duke@0 3769 constraint(ALLOC_IN_RC(int_flags));
duke@0 3770 match(RegFlags);
duke@0 3771
duke@0 3772 format %{ "RFLAGS_U" %}
duke@0 3773 interface(REG_INTER);
duke@0 3774 %}
duke@0 3775
never@415 3776 operand rFlagsRegUCF() %{
never@415 3777 constraint(ALLOC_IN_RC(int_flags));
never@415 3778 match(RegFlags);
never@415 3779 predicate(false);
never@415 3780
never@415 3781 format %{ "RFLAGS_U_CF" %}
never@415 3782 interface(REG_INTER);
never@415 3783 %}
never@415 3784
duke@0 3785 // Float register operands
duke@0 3786 operand regF()
duke@0 3787 %{
duke@0 3788 constraint(ALLOC_IN_RC(float_reg));
duke@0 3789 match(RegF);
duke@0 3790
duke@0 3791 format %{ %}
duke@0 3792 interface(REG_INTER);
duke@0 3793 %}
duke@0 3794
duke@0 3795 // Double register operands
iveresov@2251 3796 operand regD()
duke@0 3797 %{
duke@0 3798 constraint(ALLOC_IN_RC(double_reg));
duke@0 3799 match(RegD);
duke@0 3800
duke@0 3801 format %{ %}
duke@0 3802 interface(REG_INTER);
duke@0 3803 %}
duke@0 3804
duke@0 3805 //----------Memory Operands----------------------------------------------------
duke@0 3806 // Direct Memory Operand
duke@0 3807 // operand direct(immP addr)
duke@0 3808 // %{
duke@0 3809 // match(addr);
duke@0 3810
duke@0 3811 // format %{ "[$addr]" %}
duke@0 3812 // interface(MEMORY_INTER) %{
duke@0 3813 // base(0xFFFFFFFF);
duke@0 3814 // index(0x4);
duke@0 3815 // scale(0x0);
duke@0 3816 // disp($addr);
duke@0 3817 // %}
duke@0 3818 // %}
duke@0 3819
duke@0 3820 // Indirect Memory Operand
duke@0 3821 operand indirect(any_RegP reg)
duke@0 3822 %{
duke@0 3823 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3824 match(reg);
duke@0 3825
duke@0 3826 format %{ "[$reg]" %}
duke@0 3827 interface(MEMORY_INTER) %{
duke@0 3828 base($reg);
duke@0 3829 index(0x4);
duke@0 3830 scale(0x0);
duke@0 3831 disp(0x0);
duke@0 3832 %}
duke@0 3833 %}
duke@0 3834
duke@0 3835 // Indirect Memory Plus Short Offset Operand
duke@0 3836 operand indOffset8(any_RegP reg, immL8 off)
duke@0 3837 %{
duke@0 3838 constraint(ALLOC_IN_RC(ptr_reg));
duke@0 3839 match(AddP reg off);
duke@0 3840
duke@0 3841 format %{ "[$reg + $off (8-bit)]" %}
duke@0 3842 interface(MEMORY_INTER) %{
duke@0 3843 base($reg);
duke@0 3844 index(0x4);
duke@0 3845 scale(0x0);
duke@0 3846 disp($off);
duke@0 3847 %}
duke@0 3848 %}
duke@0 3849
duke@0 3850 // Indirect Memory Plus Long Offset Operand
duke@0 3851 operand indOffset32(any_RegP reg, immL32 off)