annotate src/cpu/sparc/vm/sparc.ad @ 747:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents fb4c18a2ec66
children 2056494941db
rev   line source
duke@0 1 //
twisti@603 2 // Copyright 1998-2009 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 //
duke@0 5 // This code is free software; you can redistribute it and/or modify it
duke@0 6 // under the terms of the GNU General Public License version 2 only, as
duke@0 7 // published by the Free Software Foundation.
duke@0 8 //
duke@0 9 // This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 // version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 // accompanied this code).
duke@0 14 //
duke@0 15 // You should have received a copy of the GNU General Public License version
duke@0 16 // 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 //
duke@0 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 // CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 // have any questions.
duke@0 22 //
duke@0 23 //
duke@0 24
duke@0 25 // SPARC Architecture Description File
duke@0 26
duke@0 27 //----------REGISTER DEFINITION BLOCK------------------------------------------
duke@0 28 // This information is used by the matcher and the register allocator to
duke@0 29 // describe individual registers and classes of registers within the target
duke@0 30 // archtecture.
duke@0 31 register %{
duke@0 32 //----------Architecture Description Register Definitions----------------------
duke@0 33 // General Registers
duke@0 34 // "reg_def" name ( register save type, C convention save type,
duke@0 35 // ideal register type, encoding, vm name );
duke@0 36 // Register Save Types:
duke@0 37 //
duke@0 38 // NS = No-Save: The register allocator assumes that these registers
duke@0 39 // can be used without saving upon entry to the method, &
duke@0 40 // that they do not need to be saved at call sites.
duke@0 41 //
duke@0 42 // SOC = Save-On-Call: The register allocator assumes that these registers
duke@0 43 // can be used without saving upon entry to the method,
duke@0 44 // but that they must be saved at call sites.
duke@0 45 //
duke@0 46 // SOE = Save-On-Entry: The register allocator assumes that these registers
duke@0 47 // must be saved before using them upon entry to the
duke@0 48 // method, but they do not need to be saved at call
duke@0 49 // sites.
duke@0 50 //
duke@0 51 // AS = Always-Save: The register allocator assumes that these registers
duke@0 52 // must be saved before using them upon entry to the
duke@0 53 // method, & that they must be saved at call sites.
duke@0 54 //
duke@0 55 // Ideal Register Type is used to determine how to save & restore a
duke@0 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
duke@0 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
duke@0 58 //
duke@0 59 // The encoding number is the actual bit-pattern placed into the opcodes.
duke@0 60
duke@0 61
duke@0 62 // ----------------------------
duke@0 63 // Integer/Long Registers
duke@0 64 // ----------------------------
duke@0 65
duke@0 66 // Need to expose the hi/lo aspect of 64-bit registers
duke@0 67 // This register set is used for both the 64-bit build and
duke@0 68 // the 32-bit build with 1-register longs.
duke@0 69
duke@0 70 // Global Registers 0-7
duke@0 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
duke@0 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
duke@0 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
duke@0 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
duke@0 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
duke@0 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
duke@0 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
duke@0 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
duke@0 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
duke@0 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
duke@0 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
duke@0 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
duke@0 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
duke@0 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
duke@0 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
duke@0 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
duke@0 87
duke@0 88 // Output Registers 0-7
duke@0 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
duke@0 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
duke@0 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
duke@0 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
duke@0 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
duke@0 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
duke@0 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
duke@0 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
duke@0 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
duke@0 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
duke@0 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
duke@0 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
duke@0 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
duke@0 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
duke@0 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
duke@0 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
duke@0 105
duke@0 106 // Local Registers 0-7
duke@0 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
duke@0 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
duke@0 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
duke@0 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
duke@0 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
duke@0 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
duke@0 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
duke@0 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
duke@0 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
duke@0 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
duke@0 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
duke@0 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
duke@0 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
duke@0 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
duke@0 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
duke@0 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
duke@0 123
duke@0 124 // Input Registers 0-7
duke@0 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
duke@0 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
duke@0 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
duke@0 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
duke@0 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
duke@0 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
duke@0 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
duke@0 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
duke@0 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
duke@0 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
duke@0 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
duke@0 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
duke@0 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
duke@0 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
duke@0 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
duke@0 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
duke@0 141
duke@0 142 // ----------------------------
duke@0 143 // Float/Double Registers
duke@0 144 // ----------------------------
duke@0 145
duke@0 146 // Float Registers
duke@0 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
duke@0 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
duke@0 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
duke@0 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
duke@0 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
duke@0 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
duke@0 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
duke@0 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
duke@0 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
duke@0 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
duke@0 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
duke@0 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
duke@0 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
duke@0 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
duke@0 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
duke@0 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
duke@0 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
duke@0 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
duke@0 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
duke@0 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
duke@0 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
duke@0 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
duke@0 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
duke@0 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
duke@0 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
duke@0 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
duke@0 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
duke@0 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
duke@0 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
duke@0 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
duke@0 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
duke@0 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
duke@0 179
duke@0 180 // Double Registers
duke@0 181 // The rules of ADL require that double registers be defined in pairs.
duke@0 182 // Each pair must be two 32-bit values, but not necessarily a pair of
duke@0 183 // single float registers. In each pair, ADLC-assigned register numbers
duke@0 184 // must be adjacent, with the lower number even. Finally, when the
duke@0 185 // CPU stores such a register pair to memory, the word associated with
duke@0 186 // the lower ADLC-assigned number must be stored to the lower address.
duke@0 187
duke@0 188 // These definitions specify the actual bit encodings of the sparc
duke@0 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
duke@0 190 // wants 0-63, so we have to convert every time we want to use fp regs
duke@0 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
twisti@580 192 // 255 is a flag meaning "don't go here".
duke@0 193 // I believe we can't handle callee-save doubles D32 and up until
duke@0 194 // the place in the sparc stack crawler that asserts on the 255 is
duke@0 195 // fixed up.
duke@0 196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
duke@0 197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
duke@0 198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
duke@0 199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
duke@0 200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
duke@0 201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
duke@0 202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
duke@0 203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
duke@0 204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
duke@0 205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
duke@0 206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
duke@0 207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
duke@0 208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
duke@0 209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
duke@0 210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
duke@0 211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
duke@0 212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
duke@0 213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
duke@0 214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
duke@0 215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
duke@0 216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
duke@0 217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
duke@0 218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
duke@0 219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
duke@0 220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
duke@0 221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
duke@0 222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
duke@0 223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
duke@0 224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
duke@0 225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
duke@0 226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
duke@0 227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
duke@0 228
duke@0 229
duke@0 230 // ----------------------------
duke@0 231 // Special Registers
duke@0 232 // Condition Codes Flag Registers
duke@0 233 // I tried to break out ICC and XCC but it's not very pretty.
duke@0 234 // Every Sparc instruction which defs/kills one also kills the other.
duke@0 235 // Hence every compare instruction which defs one kind of flags ends
duke@0 236 // up needing a kill of the other.
duke@0 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
duke@0 238
duke@0 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
duke@0 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
duke@0 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
duke@0 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
duke@0 243
duke@0 244 // ----------------------------
duke@0 245 // Specify the enum values for the registers. These enums are only used by the
duke@0 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
duke@0 247 // for visibility to the rest of the vm. The order of this enum influences the
duke@0 248 // register allocator so having the freedom to set this order and not be stuck
duke@0 249 // with the order that is natural for the rest of the vm is worth it.
duke@0 250 alloc_class chunk0(
duke@0 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
duke@0 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
duke@0 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
duke@0 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
duke@0 255
duke@0 256 // Note that a register is not allocatable unless it is also mentioned
duke@0 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
duke@0 258
duke@0 259 alloc_class chunk1(
duke@0 260 // The first registers listed here are those most likely to be used
duke@0 261 // as temporaries. We move F0..F7 away from the front of the list,
duke@0 262 // to reduce the likelihood of interferences with parameters and
duke@0 263 // return values. Likewise, we avoid using F0/F1 for parameters,
duke@0 264 // since they are used for return values.
duke@0 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
duke@0 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
duke@0 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
duke@0 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
duke@0 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
duke@0 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
duke@0 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
duke@0 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
duke@0 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
duke@0 274
duke@0 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
duke@0 276
duke@0 277 //----------Architecture Description Register Classes--------------------------
duke@0 278 // Several register classes are automatically defined based upon information in
duke@0 279 // this architecture description.
duke@0 280 // 1) reg_class inline_cache_reg ( as defined in frame section )
duke@0 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
duke@0 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
duke@0 283 //
duke@0 284
duke@0 285 // G0 is not included in integer class since it has special meaning.
duke@0 286 reg_class g0_reg(R_G0);
duke@0 287
duke@0 288 // ----------------------------
duke@0 289 // Integer Register Classes
duke@0 290 // ----------------------------
duke@0 291 // Exclusions from i_reg:
duke@0 292 // R_G0: hardwired zero
duke@0 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
duke@0 294 // R_G6: reserved by Solaris ABI to tools
duke@0 295 // R_G7: reserved by Solaris ABI to libthread
duke@0 296 // R_O7: Used as a temp in many encodings
duke@0 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
duke@0 298
duke@0 299 // Class for all integer registers, except the G registers. This is used for
duke@0 300 // encodings which use G registers as temps. The regular inputs to such
duke@0 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
duke@0 302 // will not put an input into a temp register.
duke@0 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
duke@0 304
duke@0 305 reg_class g1_regI(R_G1);
duke@0 306 reg_class g3_regI(R_G3);
duke@0 307 reg_class g4_regI(R_G4);
duke@0 308 reg_class o0_regI(R_O0);
duke@0 309 reg_class o7_regI(R_O7);
duke@0 310
duke@0 311 // ----------------------------
duke@0 312 // Pointer Register Classes
duke@0 313 // ----------------------------
duke@0 314 #ifdef _LP64
duke@0 315 // 64-bit build means 64-bit pointers means hi/lo pairs
duke@0 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
duke@0 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
duke@0 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
duke@0 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
duke@0 320 // Lock encodings use G3 and G4 internally
duke@0 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
duke@0 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
duke@0 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
duke@0 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
duke@0 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
duke@0 326 // It is also used for memory addressing, allowing direct TLS addressing.
duke@0 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
duke@0 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
duke@0 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
duke@0 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
duke@0 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
duke@0 332 // We use it to save R_G2 across calls out of Java.
duke@0 333 reg_class l7_regP(R_L7H,R_L7);
duke@0 334
duke@0 335 // Other special pointer regs
duke@0 336 reg_class g1_regP(R_G1H,R_G1);
duke@0 337 reg_class g2_regP(R_G2H,R_G2);
duke@0 338 reg_class g3_regP(R_G3H,R_G3);
duke@0 339 reg_class g4_regP(R_G4H,R_G4);
duke@0 340 reg_class g5_regP(R_G5H,R_G5);
duke@0 341 reg_class i0_regP(R_I0H,R_I0);
duke@0 342 reg_class o0_regP(R_O0H,R_O0);
duke@0 343 reg_class o1_regP(R_O1H,R_O1);
duke@0 344 reg_class o2_regP(R_O2H,R_O2);
duke@0 345 reg_class o7_regP(R_O7H,R_O7);
duke@0 346
duke@0 347 #else // _LP64
duke@0 348 // 32-bit build means 32-bit pointers means 1 register.
duke@0 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
duke@0 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
duke@0 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
duke@0 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
duke@0 353 // Lock encodings use G3 and G4 internally
duke@0 354 reg_class lock_ptr_reg(R_G1, R_G5,
duke@0 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
duke@0 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
duke@0 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
duke@0 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
duke@0 359 // It is also used for memory addressing, allowing direct TLS addressing.
duke@0 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
duke@0 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
duke@0 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
duke@0 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
duke@0 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
duke@0 365 // We use it to save R_G2 across calls out of Java.
duke@0 366 reg_class l7_regP(R_L7);
duke@0 367
duke@0 368 // Other special pointer regs
duke@0 369 reg_class g1_regP(R_G1);
duke@0 370 reg_class g2_regP(R_G2);
duke@0 371 reg_class g3_regP(R_G3);
duke@0 372 reg_class g4_regP(R_G4);
duke@0 373 reg_class g5_regP(R_G5);
duke@0 374 reg_class i0_regP(R_I0);
duke@0 375 reg_class o0_regP(R_O0);
duke@0 376 reg_class o1_regP(R_O1);
duke@0 377 reg_class o2_regP(R_O2);
duke@0 378 reg_class o7_regP(R_O7);
duke@0 379 #endif // _LP64
duke@0 380
duke@0 381
duke@0 382 // ----------------------------
duke@0 383 // Long Register Classes
duke@0 384 // ----------------------------
duke@0 385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
duke@0 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
duke@0 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
duke@0 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
duke@0 389 #ifdef _LP64
duke@0 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
duke@0 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
duke@0 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
duke@0 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
duke@0 394 #endif // _LP64
duke@0 395 );
duke@0 396
duke@0 397 reg_class g1_regL(R_G1H,R_G1);
kvn@411 398 reg_class g3_regL(R_G3H,R_G3);
duke@0 399 reg_class o2_regL(R_O2H,R_O2);
duke@0 400 reg_class o7_regL(R_O7H,R_O7);
duke@0 401
duke@0 402 // ----------------------------
duke@0 403 // Special Class for Condition Code Flags Register
duke@0 404 reg_class int_flags(CCR);
duke@0 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
duke@0 406 reg_class float_flag0(FCC0);
duke@0 407
duke@0 408
duke@0 409 // ----------------------------
duke@0 410 // Float Point Register Classes
duke@0 411 // ----------------------------
duke@0 412 // Skip F30/F31, they are reserved for mem-mem copies
duke@0 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
duke@0 414
duke@0 415 // Paired floating point registers--they show up in the same order as the floats,
duke@0 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
duke@0 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
duke@0 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
duke@0 419 /* Use extra V9 double registers; this AD file does not support V8 */
duke@0 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
duke@0 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
duke@0 422 );
duke@0 423
duke@0 424 // Paired floating point registers--they show up in the same order as the floats,
duke@0 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
duke@0 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
duke@0 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
duke@0 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
duke@0 429 %}
duke@0 430
duke@0 431 //----------DEFINITION BLOCK---------------------------------------------------
duke@0 432 // Define name --> value mappings to inform the ADLC of an integer valued name
duke@0 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
duke@0 434 // Format:
duke@0 435 // int_def <name> ( <int_value>, <expression>);
duke@0 436 // Generated Code in ad_<arch>.hpp
duke@0 437 // #define <name> (<expression>)
duke@0 438 // // value == <int_value>
duke@0 439 // Generated code in ad_<arch>.cpp adlc_verification()
duke@0 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
duke@0 441 //
duke@0 442 definitions %{
duke@0 443 // The default cost (of an ALU instruction).
duke@0 444 int_def DEFAULT_COST ( 100, 100);
duke@0 445 int_def HUGE_COST (1000000, 1000000);
duke@0 446
duke@0 447 // Memory refs are twice as expensive as run-of-the-mill.
duke@0 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
duke@0 449
duke@0 450 // Branches are even more expensive.
duke@0 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
duke@0 452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
duke@0 453 %}
duke@0 454
duke@0 455
duke@0 456 //----------SOURCE BLOCK-------------------------------------------------------
duke@0 457 // This is a block of C++ code which provides values, functions, and
duke@0 458 // definitions necessary in the rest of the architecture description
duke@0 459 source_hpp %{
duke@0 460 // Must be visible to the DFA in dfa_sparc.cpp
duke@0 461 extern bool can_branch_register( Node *bol, Node *cmp );
duke@0 462
duke@0 463 // Macros to extract hi & lo halves from a long pair.
duke@0 464 // G0 is not part of any long pair, so assert on that.
twisti@580 465 // Prevents accidentally using G1 instead of G0.
duke@0 466 #define LONG_HI_REG(x) (x)
duke@0 467 #define LONG_LO_REG(x) (x)
duke@0 468
duke@0 469 %}
duke@0 470
duke@0 471 source %{
duke@0 472 #define __ _masm.
duke@0 473
duke@0 474 // tertiary op of a LoadP or StoreP encoding
duke@0 475 #define REGP_OP true
duke@0 476
duke@0 477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
duke@0 478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
duke@0 479 static Register reg_to_register_object(int register_encoding);
duke@0 480
duke@0 481 // Used by the DFA in dfa_sparc.cpp.
duke@0 482 // Check for being able to use a V9 branch-on-register. Requires a
duke@0 483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
duke@0 484 // extended. Doesn't work following an integer ADD, for example, because of
duke@0 485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
duke@0 486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
duke@0 487 // replace them with zero, which could become sign-extension in a different OS
duke@0 488 // release. There's no obvious reason why an interrupt will ever fill these
duke@0 489 // bits with non-zero junk (the registers are reloaded with standard LD
duke@0 490 // instructions which either zero-fill or sign-fill).
duke@0 491 bool can_branch_register( Node *bol, Node *cmp ) {
duke@0 492 if( !BranchOnRegister ) return false;
duke@0 493 #ifdef _LP64
duke@0 494 if( cmp->Opcode() == Op_CmpP )
duke@0 495 return true; // No problems with pointer compares
duke@0 496 #endif
duke@0 497 if( cmp->Opcode() == Op_CmpL )
duke@0 498 return true; // No problems with long compares
duke@0 499
duke@0 500 if( !SparcV9RegsHiBitsZero ) return false;
duke@0 501 if( bol->as_Bool()->_test._test != BoolTest::ne &&
duke@0 502 bol->as_Bool()->_test._test != BoolTest::eq )
duke@0 503 return false;
duke@0 504
duke@0 505 // Check for comparing against a 'safe' value. Any operation which
duke@0 506 // clears out the high word is safe. Thus, loads and certain shifts
duke@0 507 // are safe, as are non-negative constants. Any operation which
duke@0 508 // preserves zero bits in the high word is safe as long as each of its
duke@0 509 // inputs are safe. Thus, phis and bitwise booleans are safe if their
duke@0 510 // inputs are safe. At present, the only important case to recognize
duke@0 511 // seems to be loads. Constants should fold away, and shifts &
duke@0 512 // logicals can use the 'cc' forms.
duke@0 513 Node *x = cmp->in(1);
duke@0 514 if( x->is_Load() ) return true;
duke@0 515 if( x->is_Phi() ) {
duke@0 516 for( uint i = 1; i < x->req(); i++ )
duke@0 517 if( !x->in(i)->is_Load() )
duke@0 518 return false;
duke@0 519 return true;
duke@0 520 }
duke@0 521 return false;
duke@0 522 }
duke@0 523
duke@0 524 // ****************************************************************************
duke@0 525
duke@0 526 // REQUIRED FUNCTIONALITY
duke@0 527
duke@0 528 // !!!!! Special hack to get all type of calls to specify the byte offset
duke@0 529 // from the start of the call to the point where the return address
duke@0 530 // will point.
duke@0 531 // The "return address" is the address of the call instruction, plus 8.
duke@0 532
duke@0 533 int MachCallStaticJavaNode::ret_addr_offset() {
duke@0 534 return NativeCall::instruction_size; // call; delay slot
duke@0 535 }
duke@0 536
duke@0 537 int MachCallDynamicJavaNode::ret_addr_offset() {
duke@0 538 int vtable_index = this->_vtable_index;
duke@0 539 if (vtable_index < 0) {
duke@0 540 // must be invalid_vtable_index, not nonvirtual_vtable_index
duke@0 541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
duke@0 542 return (NativeMovConstReg::instruction_size +
duke@0 543 NativeCall::instruction_size); // sethi; setlo; call; delay slot
duke@0 544 } else {
duke@0 545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
duke@0 546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
duke@0 547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
coleenp@108 548 int klass_load_size;
coleenp@108 549 if (UseCompressedOops) {
kvn@619 550 assert(Universe::heap() != NULL, "java heap should be initialized");
kvn@619 551 if (Universe::narrow_oop_base() == NULL)
kvn@619 552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
kvn@619 553 else
kvn@619 554 klass_load_size = 3*BytesPerInstWord;
coleenp@108 555 } else {
coleenp@108 556 klass_load_size = 1*BytesPerInstWord;
coleenp@108 557 }
duke@0 558 if( Assembler::is_simm13(v_off) ) {
coleenp@108 559 return klass_load_size +
coleenp@108 560 (2*BytesPerInstWord + // ld_ptr, ld_ptr
duke@0 561 NativeCall::instruction_size); // call; delay slot
duke@0 562 } else {
coleenp@108 563 return klass_load_size +
coleenp@108 564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
duke@0 565 NativeCall::instruction_size); // call; delay slot
duke@0 566 }
duke@0 567 }
duke@0 568 }
duke@0 569
duke@0 570 int MachCallRuntimeNode::ret_addr_offset() {
duke@0 571 #ifdef _LP64
duke@0 572 return NativeFarCall::instruction_size; // farcall; delay slot
duke@0 573 #else
duke@0 574 return NativeCall::instruction_size; // call; delay slot
duke@0 575 #endif
duke@0 576 }
duke@0 577
duke@0 578 // Indicate if the safepoint node needs the polling page as an input.
duke@0 579 // Since Sparc does not have absolute addressing, it does.
duke@0 580 bool SafePointNode::needs_polling_address_input() {
duke@0 581 return true;
duke@0 582 }
duke@0 583
duke@0 584 // emit an interrupt that is caught by the debugger (for debugging compiler)
duke@0 585 void emit_break(CodeBuffer &cbuf) {
duke@0 586 MacroAssembler _masm(&cbuf);
duke@0 587 __ breakpoint_trap();
duke@0 588 }
duke@0 589
duke@0 590 #ifndef PRODUCT
duke@0 591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
duke@0 592 st->print("TA");
duke@0 593 }
duke@0 594 #endif
duke@0 595
duke@0 596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 597 emit_break(cbuf);
duke@0 598 }
duke@0 599
duke@0 600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
duke@0 601 return MachNode::size(ra_);
duke@0 602 }
duke@0 603
duke@0 604 // Traceable jump
duke@0 605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
duke@0 606 MacroAssembler _masm(&cbuf);
duke@0 607 Register rdest = reg_to_register_object(jump_target);
duke@0 608 __ JMP(rdest, 0);
duke@0 609 __ delayed()->nop();
duke@0 610 }
duke@0 611
duke@0 612 // Traceable jump and set exception pc
duke@0 613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
duke@0 614 MacroAssembler _masm(&cbuf);
duke@0 615 Register rdest = reg_to_register_object(jump_target);
duke@0 616 __ JMP(rdest, 0);
duke@0 617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
duke@0 618 }
duke@0 619
duke@0 620 void emit_nop(CodeBuffer &cbuf) {
duke@0 621 MacroAssembler _masm(&cbuf);
duke@0 622 __ nop();
duke@0 623 }
duke@0 624
duke@0 625 void emit_illtrap(CodeBuffer &cbuf) {
duke@0 626 MacroAssembler _masm(&cbuf);
duke@0 627 __ illtrap(0);
duke@0 628 }
duke@0 629
duke@0 630
duke@0 631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
duke@0 632 assert(n->rule() != loadUB_rule, "");
duke@0 633
duke@0 634 intptr_t offset = 0;
duke@0 635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
duke@0 636 const Node* addr = n->get_base_and_disp(offset, adr_type);
duke@0 637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
duke@0 638 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
duke@0 639 assert(addr->bottom_type()->isa_oopptr() == atype, "");
duke@0 640 atype = atype->add_offset(offset);
duke@0 641 assert(disp32 == offset, "wrong disp32");
duke@0 642 return atype->_offset;
duke@0 643 }
duke@0 644
duke@0 645
duke@0 646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
duke@0 647 assert(n->rule() != loadUB_rule, "");
duke@0 648
duke@0 649 intptr_t offset = 0;
duke@0 650 Node* addr = n->in(2);
duke@0 651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
duke@0 652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
duke@0 653 Node* a = addr->in(2/*AddPNode::Address*/);
duke@0 654 Node* o = addr->in(3/*AddPNode::Offset*/);
duke@0 655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
duke@0 656 atype = a->bottom_type()->is_ptr()->add_offset(offset);
duke@0 657 assert(atype->isa_oop_ptr(), "still an oop");
duke@0 658 }
duke@0 659 offset = atype->is_ptr()->_offset;
duke@0 660 if (offset != Type::OffsetBot) offset += disp32;
duke@0 661 return offset;
duke@0 662 }
duke@0 663
duke@0 664 // Standard Sparc opcode form2 field breakdown
duke@0 665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
duke@0 666 f0 &= (1<<19)-1; // Mask displacement to 19 bits
duke@0 667 int op = (f30 << 30) |
duke@0 668 (f29 << 29) |
duke@0 669 (f25 << 25) |
duke@0 670 (f22 << 22) |
duke@0 671 (f20 << 20) |
duke@0 672 (f19 << 19) |
duke@0 673 (f0 << 0);
duke@0 674 *((int*)(cbuf.code_end())) = op;
duke@0 675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 676 }
duke@0 677
duke@0 678 // Standard Sparc opcode form2 field breakdown
duke@0 679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
duke@0 680 f0 >>= 10; // Drop 10 bits
duke@0 681 f0 &= (1<<22)-1; // Mask displacement to 22 bits
duke@0 682 int op = (f30 << 30) |
duke@0 683 (f25 << 25) |
duke@0 684 (f22 << 22) |
duke@0 685 (f0 << 0);
duke@0 686 *((int*)(cbuf.code_end())) = op;
duke@0 687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 688 }
duke@0 689
duke@0 690 // Standard Sparc opcode form3 field breakdown
duke@0 691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
duke@0 692 int op = (f30 << 30) |
duke@0 693 (f25 << 25) |
duke@0 694 (f19 << 19) |
duke@0 695 (f14 << 14) |
duke@0 696 (f5 << 5) |
duke@0 697 (f0 << 0);
duke@0 698 *((int*)(cbuf.code_end())) = op;
duke@0 699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 700 }
duke@0 701
duke@0 702 // Standard Sparc opcode form3 field breakdown
duke@0 703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
duke@0 704 simm13 &= (1<<13)-1; // Mask to 13 bits
duke@0 705 int op = (f30 << 30) |
duke@0 706 (f25 << 25) |
duke@0 707 (f19 << 19) |
duke@0 708 (f14 << 14) |
duke@0 709 (1 << 13) | // bit to indicate immediate-mode
duke@0 710 (simm13<<0);
duke@0 711 *((int*)(cbuf.code_end())) = op;
duke@0 712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 713 }
duke@0 714
duke@0 715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
duke@0 716 simm10 &= (1<<10)-1; // Mask to 10 bits
duke@0 717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
duke@0 718 }
duke@0 719
duke@0 720 #ifdef ASSERT
duke@0 721 // Helper function for VerifyOops in emit_form3_mem_reg
duke@0 722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
duke@0 723 warning("VerifyOops encountered unexpected instruction:");
duke@0 724 n->dump(2);
duke@0 725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
duke@0 726 }
duke@0 727 #endif
duke@0 728
duke@0 729
duke@0 730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
duke@0 731 int src1_enc, int disp32, int src2_enc, int dst_enc) {
duke@0 732
duke@0 733 #ifdef ASSERT
duke@0 734 // The following code implements the +VerifyOops feature.
duke@0 735 // It verifies oop values which are loaded into or stored out of
duke@0 736 // the current method activation. +VerifyOops complements techniques
duke@0 737 // like ScavengeALot, because it eagerly inspects oops in transit,
duke@0 738 // as they enter or leave the stack, as opposed to ScavengeALot,
duke@0 739 // which inspects oops "at rest", in the stack or heap, at safepoints.
duke@0 740 // For this reason, +VerifyOops can sometimes detect bugs very close
duke@0 741 // to their point of creation. It can also serve as a cross-check
duke@0 742 // on the validity of oop maps, when used toegether with ScavengeALot.
duke@0 743
duke@0 744 // It would be good to verify oops at other points, especially
duke@0 745 // when an oop is used as a base pointer for a load or store.
duke@0 746 // This is presently difficult, because it is hard to know when
duke@0 747 // a base address is biased or not. (If we had such information,
duke@0 748 // it would be easy and useful to make a two-argument version of
duke@0 749 // verify_oop which unbiases the base, and performs verification.)
duke@0 750
duke@0 751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
duke@0 752 bool is_verified_oop_base = false;
duke@0 753 bool is_verified_oop_load = false;
duke@0 754 bool is_verified_oop_store = false;
duke@0 755 int tmp_enc = -1;
duke@0 756 if (VerifyOops && src1_enc != R_SP_enc) {
duke@0 757 // classify the op, mainly for an assert check
duke@0 758 int st_op = 0, ld_op = 0;
duke@0 759 switch (primary) {
duke@0 760 case Assembler::stb_op3: st_op = Op_StoreB; break;
duke@0 761 case Assembler::sth_op3: st_op = Op_StoreC; break;
duke@0 762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
duke@0 763 case Assembler::stw_op3: st_op = Op_StoreI; break;
duke@0 764 case Assembler::std_op3: st_op = Op_StoreL; break;
duke@0 765 case Assembler::stf_op3: st_op = Op_StoreF; break;
duke@0 766 case Assembler::stdf_op3: st_op = Op_StoreD; break;
duke@0 767
duke@0 768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
twisti@515 769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
duke@0 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
duke@0 771 case Assembler::ldx_op3: // may become LoadP or stay LoadI
duke@0 772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
duke@0 773 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
duke@0 774 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
duke@0 775 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
duke@0 776 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
duke@0 777 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
duke@0 778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
duke@0 779
duke@0 780 default: ShouldNotReachHere();
duke@0 781 }
duke@0 782 if (tertiary == REGP_OP) {
duke@0 783 if (st_op == Op_StoreI) st_op = Op_StoreP;
duke@0 784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
duke@0 785 else ShouldNotReachHere();
duke@0 786 if (st_op) {
duke@0 787 // a store
duke@0 788 // inputs are (0:control, 1:memory, 2:address, 3:value)
duke@0 789 Node* n2 = n->in(3);
duke@0 790 if (n2 != NULL) {
duke@0 791 const Type* t = n2->bottom_type();
duke@0 792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
duke@0 793 }
duke@0 794 } else {
duke@0 795 // a load
duke@0 796 const Type* t = n->bottom_type();
duke@0 797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
duke@0 798 }
duke@0 799 }
duke@0 800
duke@0 801 if (ld_op) {
duke@0 802 // a Load
duke@0 803 // inputs are (0:control, 1:memory, 2:address)
duke@0 804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
duke@0 805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
duke@0 806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
duke@0 807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
duke@0 808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
duke@0 809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
duke@0 810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
duke@0 811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
duke@0 812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
duke@0 813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
duke@0 814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
duke@0 815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
duke@0 816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
duke@0 817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
duke@0 818 !(n->rule() == loadUB_rule)) {
duke@0 819 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
duke@0 820 }
duke@0 821 } else if (st_op) {
duke@0 822 // a Store
duke@0 823 // inputs are (0:control, 1:memory, 2:address, 3:value)
duke@0 824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
duke@0 825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
duke@0 826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
duke@0 827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
duke@0 828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
duke@0 829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
duke@0 830 verify_oops_warning(n, n->ideal_Opcode(), st_op);
duke@0 831 }
duke@0 832 }
duke@0 833
duke@0 834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
duke@0 835 Node* addr = n->in(2);
duke@0 836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
duke@0 837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
duke@0 838 if (atype != NULL) {
duke@0 839 intptr_t offset = get_offset_from_base(n, atype, disp32);
duke@0 840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
duke@0 841 if (offset != offset_2) {
duke@0 842 get_offset_from_base(n, atype, disp32);
duke@0 843 get_offset_from_base_2(n, atype, disp32);
duke@0 844 }
duke@0 845 assert(offset == offset_2, "different offsets");
duke@0 846 if (offset == disp32) {
duke@0 847 // we now know that src1 is a true oop pointer
duke@0 848 is_verified_oop_base = true;
duke@0 849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
duke@0 850 if( primary == Assembler::ldd_op3 ) {
duke@0 851 is_verified_oop_base = false; // Cannot 'ldd' into O7
duke@0 852 } else {
duke@0 853 tmp_enc = dst_enc;
duke@0 854 dst_enc = R_O7_enc; // Load into O7; preserve source oop
duke@0 855 assert(src1_enc != dst_enc, "");
duke@0 856 }
duke@0 857 }
duke@0 858 }
duke@0 859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
duke@0 860 || offset == oopDesc::mark_offset_in_bytes())) {
duke@0 861 // loading the mark should not be allowed either, but
duke@0 862 // we don't check this since it conflicts with InlineObjectHash
duke@0 863 // usage of LoadINode to get the mark. We could keep the
duke@0 864 // check if we create a new LoadMarkNode
duke@0 865 // but do not verify the object before its header is initialized
duke@0 866 ShouldNotReachHere();
duke@0 867 }
duke@0 868 }
duke@0 869 }
duke@0 870 }
duke@0 871 }
duke@0 872 #endif
duke@0 873
duke@0 874 uint instr;
duke@0 875 instr = (Assembler::ldst_op << 30)
duke@0 876 | (dst_enc << 25)
duke@0 877 | (primary << 19)
duke@0 878 | (src1_enc << 14);
duke@0 879
duke@0 880 uint index = src2_enc;
duke@0 881 int disp = disp32;
duke@0 882
duke@0 883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
duke@0 884 disp += STACK_BIAS;
duke@0 885
duke@0 886 // We should have a compiler bailout here rather than a guarantee.
duke@0 887 // Better yet would be some mechanism to handle variable-size matches correctly.
duke@0 888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
duke@0 889
duke@0 890 if( disp == 0 ) {
duke@0 891 // use reg-reg form
duke@0 892 // bit 13 is already zero
duke@0 893 instr |= index;
duke@0 894 } else {
duke@0 895 // use reg-imm form
duke@0 896 instr |= 0x00002000; // set bit 13 to one
duke@0 897 instr |= disp & 0x1FFF;
duke@0 898 }
duke@0 899
duke@0 900 uint *code = (uint*)cbuf.code_end();
duke@0 901 *code = instr;
duke@0 902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 903
duke@0 904 #ifdef ASSERT
duke@0 905 {
duke@0 906 MacroAssembler _masm(&cbuf);
duke@0 907 if (is_verified_oop_base) {
duke@0 908 __ verify_oop(reg_to_register_object(src1_enc));
duke@0 909 }
duke@0 910 if (is_verified_oop_store) {
duke@0 911 __ verify_oop(reg_to_register_object(dst_enc));
duke@0 912 }
duke@0 913 if (tmp_enc != -1) {
duke@0 914 __ mov(O7, reg_to_register_object(tmp_enc));
duke@0 915 }
duke@0 916 if (is_verified_oop_load) {
duke@0 917 __ verify_oop(reg_to_register_object(dst_enc));
duke@0 918 }
duke@0 919 }
duke@0 920 #endif
duke@0 921 }
duke@0 922
duke@0 923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
duke@0 924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
duke@0 925
duke@0 926 uint instr;
duke@0 927 instr = (Assembler::ldst_op << 30)
duke@0 928 | (dst_enc << 25)
duke@0 929 | (primary << 19)
duke@0 930 | (src1_enc << 14);
duke@0 931
duke@0 932 int disp = disp32;
duke@0 933 int index = src2_enc;
duke@0 934
duke@0 935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
duke@0 936 disp += STACK_BIAS;
duke@0 937
duke@0 938 // We should have a compiler bailout here rather than a guarantee.
duke@0 939 // Better yet would be some mechanism to handle variable-size matches correctly.
duke@0 940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
duke@0 941
duke@0 942 if( disp != 0 ) {
duke@0 943 // use reg-reg form
duke@0 944 // set src2=R_O7 contains offset
duke@0 945 index = R_O7_enc;
duke@0 946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
duke@0 947 }
duke@0 948 instr |= (asi << 5);
duke@0 949 instr |= index;
duke@0 950 uint *code = (uint*)cbuf.code_end();
duke@0 951 *code = instr;
duke@0 952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 953 }
duke@0 954
duke@0 955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
duke@0 956 // The method which records debug information at every safepoint
duke@0 957 // expects the call to be the first instruction in the snippet as
duke@0 958 // it creates a PcDesc structure which tracks the offset of a call
duke@0 959 // from the start of the codeBlob. This offset is computed as
duke@0 960 // code_end() - code_begin() of the code which has been emitted
duke@0 961 // so far.
duke@0 962 // In this particular case we have skirted around the problem by
duke@0 963 // putting the "mov" instruction in the delay slot but the problem
duke@0 964 // may bite us again at some other point and a cleaner/generic
duke@0 965 // solution using relocations would be needed.
duke@0 966 MacroAssembler _masm(&cbuf);
duke@0 967 __ set_inst_mark();
duke@0 968
duke@0 969 // We flush the current window just so that there is a valid stack copy
duke@0 970 // the fact that the current window becomes active again instantly is
duke@0 971 // not a problem there is nothing live in it.
duke@0 972
duke@0 973 #ifdef ASSERT
duke@0 974 int startpos = __ offset();
duke@0 975 #endif /* ASSERT */
duke@0 976
duke@0 977 #ifdef _LP64
duke@0 978 // Calls to the runtime or native may not be reachable from compiled code,
duke@0 979 // so we generate the far call sequence on 64 bit sparc.
duke@0 980 // This code sequence is relocatable to any address, even on LP64.
duke@0 981 if ( force_far_call ) {
duke@0 982 __ relocate(rtype);
twisti@720 983 AddressLiteral dest(entry_point);
twisti@720 984 __ jumpl_to(dest, O7, O7);
duke@0 985 }
duke@0 986 else
duke@0 987 #endif
duke@0 988 {
duke@0 989 __ call((address)entry_point, rtype);
duke@0 990 }
duke@0 991
duke@0 992 if (preserve_g2) __ delayed()->mov(G2, L7);
duke@0 993 else __ delayed()->nop();
duke@0 994
duke@0 995 if (preserve_g2) __ mov(L7, G2);
duke@0 996
duke@0 997 #ifdef ASSERT
duke@0 998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
duke@0 999 #ifdef _LP64
duke@0 1000 // Trash argument dump slots.
duke@0 1001 __ set(0xb0b8ac0db0b8ac0d, G1);
duke@0 1002 __ mov(G1, G5);
duke@0 1003 __ stx(G1, SP, STACK_BIAS + 0x80);
duke@0 1004 __ stx(G1, SP, STACK_BIAS + 0x88);
duke@0 1005 __ stx(G1, SP, STACK_BIAS + 0x90);
duke@0 1006 __ stx(G1, SP, STACK_BIAS + 0x98);
duke@0 1007 __ stx(G1, SP, STACK_BIAS + 0xA0);
duke@0 1008 __ stx(G1, SP, STACK_BIAS + 0xA8);
duke@0 1009 #else // _LP64
duke@0 1010 // this is also a native call, so smash the first 7 stack locations,
duke@0 1011 // and the various registers
duke@0 1012
duke@0 1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
duke@0 1014 // while [SP+0x44..0x58] are the argument dump slots.
duke@0 1015 __ set((intptr_t)0xbaadf00d, G1);
duke@0 1016 __ mov(G1, G5);
duke@0 1017 __ sllx(G1, 32, G1);
duke@0 1018 __ or3(G1, G5, G1);
duke@0 1019 __ mov(G1, G5);
duke@0 1020 __ stx(G1, SP, 0x40);
duke@0 1021 __ stx(G1, SP, 0x48);
duke@0 1022 __ stx(G1, SP, 0x50);
duke@0 1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
duke@0 1024 #endif // _LP64
duke@0 1025 }
duke@0 1026 #endif /*ASSERT*/
duke@0 1027 }
duke@0 1028
duke@0 1029 //=============================================================================
duke@0 1030 // REQUIRED FUNCTIONALITY for encoding
duke@0 1031 void emit_lo(CodeBuffer &cbuf, int val) { }
duke@0 1032 void emit_hi(CodeBuffer &cbuf, int val) { }
duke@0 1033
duke@0 1034
duke@0 1035 //=============================================================================
duke@0 1036
duke@0 1037 #ifndef PRODUCT
duke@0 1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
duke@0 1039 Compile* C = ra_->C;
duke@0 1040
duke@0 1041 for (int i = 0; i < OptoPrologueNops; i++) {
duke@0 1042 st->print_cr("NOP"); st->print("\t");
duke@0 1043 }
duke@0 1044
duke@0 1045 if( VerifyThread ) {
duke@0 1046 st->print_cr("Verify_Thread"); st->print("\t");
duke@0 1047 }
duke@0 1048
duke@0 1049 size_t framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1050
duke@0 1051 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 1052 // We require that their callers must bang for them. But be careful, because
duke@0 1053 // some VM calls (such as call site linkage) can use several kilobytes of
duke@0 1054 // stack. But the stack safety zone should account for that.
duke@0 1055 // See bugs 4446381, 4468289, 4497237.
duke@0 1056 if (C->need_stack_bang(framesize)) {
duke@0 1057 st->print_cr("! stack bang"); st->print("\t");
duke@0 1058 }
duke@0 1059
duke@0 1060 if (Assembler::is_simm13(-framesize)) {
duke@0 1061 st->print ("SAVE R_SP,-%d,R_SP",framesize);
duke@0 1062 } else {
duke@0 1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
duke@0 1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
duke@0 1065 st->print ("SAVE R_SP,R_G3,R_SP");
duke@0 1066 }
duke@0 1067
duke@0 1068 }
duke@0 1069 #endif
duke@0 1070
duke@0 1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1072 Compile* C = ra_->C;
duke@0 1073 MacroAssembler _masm(&cbuf);
duke@0 1074
duke@0 1075 for (int i = 0; i < OptoPrologueNops; i++) {
duke@0 1076 __ nop();
duke@0 1077 }
duke@0 1078
duke@0 1079 __ verify_thread();
duke@0 1080
duke@0 1081 size_t framesize = C->frame_slots() << LogBytesPerInt;
duke@0 1082 assert(framesize >= 16*wordSize, "must have room for reg. save area");
duke@0 1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
duke@0 1084
duke@0 1085 // Calls to C2R adapters often do not accept exceptional returns.
duke@0 1086 // We require that their callers must bang for them. But be careful, because
duke@0 1087 // some VM calls (such as call site linkage) can use several kilobytes of
duke@0 1088 // stack. But the stack safety zone should account for that.
duke@0 1089 // See bugs 4446381, 4468289, 4497237.
duke@0 1090 if (C->need_stack_bang(framesize)) {
duke@0 1091 __ generate_stack_overflow_check(framesize);
duke@0 1092 }
duke@0 1093
duke@0 1094 if (Assembler::is_simm13(-framesize)) {
duke@0 1095 __ save(SP, -framesize, SP);
duke@0 1096 } else {
duke@0 1097 __ sethi(-framesize & ~0x3ff, G3);
duke@0 1098 __ add(G3, -framesize & 0x3ff, G3);
duke@0 1099 __ save(SP, G3, SP);
duke@0 1100 }
duke@0 1101 C->set_frame_complete( __ offset() );
duke@0 1102 }
duke@0 1103
duke@0 1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
duke@0 1105 return MachNode::size(ra_);
duke@0 1106 }
duke@0 1107
duke@0 1108 int MachPrologNode::reloc() const {
duke@0 1109 return 10; // a large enough number
duke@0 1110 }
duke@0 1111
duke@0 1112 //=============================================================================
duke@0 1113 #ifndef PRODUCT
duke@0 1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
duke@0 1115 Compile* C = ra_->C;
duke@0 1116
duke@0 1117 if( do_polling() && ra_->C->is_method_compilation() ) {
duke@0 1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
duke@0 1119 #ifdef _LP64
duke@0 1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
duke@0 1121 #else
duke@0 1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
duke@0 1123 #endif
duke@0 1124 }
duke@0 1125
duke@0 1126 if( do_polling() )
duke@0 1127 st->print("RET\n\t");
duke@0 1128
duke@0 1129 st->print("RESTORE");
duke@0 1130 }
duke@0 1131 #endif
duke@0 1132
duke@0 1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1134 MacroAssembler _masm(&cbuf);
duke@0 1135 Compile* C = ra_->C;
duke@0 1136
duke@0 1137 __ verify_thread();
duke@0 1138
duke@0 1139 // If this does safepoint polling, then do it here
duke@0 1140 if( do_polling() && ra_->C->is_method_compilation() ) {
twisti@720 1141 AddressLiteral polling_page(os::get_polling_page());
twisti@720 1142 __ sethi(polling_page, L0);
duke@0 1143 __ relocate(relocInfo::poll_return_type);
duke@0 1144 __ ld_ptr( L0, 0, G0 );
duke@0 1145 }
duke@0 1146
duke@0 1147 // If this is a return, then stuff the restore in the delay slot
duke@0 1148 if( do_polling() ) {
duke@0 1149 __ ret();
duke@0 1150 __ delayed()->restore();
duke@0 1151 } else {
duke@0 1152 __ restore();
duke@0 1153 }
duke@0 1154 }
duke@0 1155
duke@0 1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
duke@0 1157 return MachNode::size(ra_);
duke@0 1158 }
duke@0 1159
duke@0 1160 int MachEpilogNode::reloc() const {
duke@0 1161 return 16; // a large enough number
duke@0 1162 }
duke@0 1163
duke@0 1164 const Pipeline * MachEpilogNode::pipeline() const {
duke@0 1165 return MachNode::pipeline_class();
duke@0 1166 }
duke@0 1167
duke@0 1168 int MachEpilogNode::safepoint_offset() const {
duke@0 1169 assert( do_polling(), "no return for this epilog node");
duke@0 1170 return MacroAssembler::size_of_sethi(os::get_polling_page());
duke@0 1171 }
duke@0 1172
duke@0 1173 //=============================================================================
duke@0 1174
duke@0 1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
duke@0 1176 enum RC { rc_bad, rc_int, rc_float, rc_stack };
duke@0 1177 static enum RC rc_class( OptoReg::Name reg ) {
duke@0 1178 if( !OptoReg::is_valid(reg) ) return rc_bad;
duke@0 1179 if (OptoReg::is_stack(reg)) return rc_stack;
duke@0 1180 VMReg r = OptoReg::as_VMReg(reg);
duke@0 1181 if (r->is_Register()) return rc_int;
duke@0 1182 assert(r->is_FloatRegister(), "must be");
duke@0 1183 return rc_float;
duke@0 1184 }
duke@0 1185
duke@0 1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
duke@0 1187 if( cbuf ) {
duke@0 1188 // Better yet would be some mechanism to handle variable-size matches correctly
duke@0 1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
duke@0 1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
duke@0 1191 } else {
duke@0 1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
duke@0 1193 }
duke@0 1194 }
duke@0 1195 #ifndef PRODUCT
duke@0 1196 else if( !do_size ) {
duke@0 1197 if( size != 0 ) st->print("\n\t");
duke@0 1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
duke@0 1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
duke@0 1200 }
duke@0 1201 #endif
duke@0 1202 return size+4;
duke@0 1203 }
duke@0 1204
duke@0 1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
duke@0 1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
duke@0 1207 #ifndef PRODUCT
duke@0 1208 else if( !do_size ) {
duke@0 1209 if( size != 0 ) st->print("\n\t");
duke@0 1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
duke@0 1211 }
duke@0 1212 #endif
duke@0 1213 return size+4;
duke@0 1214 }
duke@0 1215
duke@0 1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
duke@0 1217 PhaseRegAlloc *ra_,
duke@0 1218 bool do_size,
duke@0 1219 outputStream* st ) const {
duke@0 1220 // Get registers to move
duke@0 1221 OptoReg::Name src_second = ra_->get_reg_second(in(1));
duke@0 1222 OptoReg::Name src_first = ra_->get_reg_first(in(1));
duke@0 1223 OptoReg::Name dst_second = ra_->get_reg_second(this );
duke@0 1224 OptoReg::Name dst_first = ra_->get_reg_first(this );
duke@0 1225
duke@0 1226 enum RC src_second_rc = rc_class(src_second);
duke@0 1227 enum RC src_first_rc = rc_class(src_first);
duke@0 1228 enum RC dst_second_rc = rc_class(dst_second);
duke@0 1229 enum RC dst_first_rc = rc_class(dst_first);
duke@0 1230
duke@0 1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
duke@0 1232
duke@0 1233 // Generate spill code!
duke@0 1234 int size = 0;
duke@0 1235
duke@0 1236 if( src_first == dst_first && src_second == dst_second )
duke@0 1237 return size; // Self copy, no move
duke@0 1238
duke@0 1239 // --------------------------------------
duke@0 1240 // Check for mem-mem move. Load into unused float registers and fall into
duke@0 1241 // the float-store case.
duke@0 1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
duke@0 1243 int offset = ra_->reg2offset(src_first);
duke@0 1244 // Further check for aligned-adjacent pair, so we can use a double load
duke@0 1245 if( (src_first&1)==0 && src_first+1 == src_second ) {
duke@0 1246 src_second = OptoReg::Name(R_F31_num);
duke@0 1247 src_second_rc = rc_float;
duke@0 1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
duke@0 1249 } else {
duke@0 1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
duke@0 1251 }
duke@0 1252 src_first = OptoReg::Name(R_F30_num);
duke@0 1253 src_first_rc = rc_float;
duke@0 1254 }
duke@0 1255
duke@0 1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
duke@0 1257 int offset = ra_->reg2offset(src_second);
duke@0 1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
duke@0 1259 src_second = OptoReg::Name(R_F31_num);
duke@0 1260 src_second_rc = rc_float;
duke@0 1261 }
duke@0 1262
duke@0 1263 // --------------------------------------
duke@0 1264 // Check for float->int copy; requires a trip through memory
duke@0 1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
duke@0 1266 int offset = frame::register_save_words*wordSize;
duke@0 1267 if( cbuf ) {
duke@0 1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
duke@0 1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
duke@0 1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
duke@0 1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
duke@0 1272 }
duke@0 1273 #ifndef PRODUCT
duke@0 1274 else if( !do_size ) {
duke@0 1275 if( size != 0 ) st->print("\n\t");
duke@0 1276 st->print( "SUB R_SP,16,R_SP\n");
duke@0 1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
duke@0 1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
duke@0 1279 st->print("\tADD R_SP,16,R_SP\n");
duke@0 1280 }
duke@0 1281 #endif
duke@0 1282 size += 16;
duke@0 1283 }
duke@0 1284
duke@0 1285 // --------------------------------------
duke@0 1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
duke@0 1287 // In such cases, I have to do the big-endian swap. For aligned targets, the
duke@0 1288 // hardware does the flop for me. Doubles are always aligned, so no problem
duke@0 1289 // there. Misaligned sources only come from native-long-returns (handled
duke@0 1290 // special below).
duke@0 1291 #ifndef _LP64
duke@0 1292 if( src_first_rc == rc_int && // source is already big-endian
duke@0 1293 src_second_rc != rc_bad && // 64-bit move
duke@0 1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
duke@0 1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
duke@0 1296 // Do the big-endian flop.
duke@0 1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
duke@0 1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
duke@0 1299 }
duke@0 1300 #endif
duke@0 1301
duke@0 1302 // --------------------------------------
duke@0 1303 // Check for integer reg-reg copy
duke@0 1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
duke@0 1305 #ifndef _LP64
duke@0 1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
duke@0 1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
duke@0 1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
duke@0 1309 // operand contains the least significant word of the 64-bit value and vice versa.
duke@0 1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
duke@0 1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
duke@0 1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
duke@0 1313 if( cbuf ) {
duke@0 1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
duke@0 1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
duke@0 1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
duke@0 1317 #ifndef PRODUCT
duke@0 1318 } else if( !do_size ) {
duke@0 1319 if( size != 0 ) st->print("\n\t");
duke@0 1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
duke@0 1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
duke@0 1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
duke@0 1323 #endif
duke@0 1324 }
duke@0 1325 return size+12;
duke@0 1326 }
duke@0 1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
duke@0 1328 // returning a long value in I0/I1
duke@0 1329 // a SpillCopy must be able to target a return instruction's reg_class
duke@0 1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
duke@0 1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
duke@0 1332 // operand contains the least significant word of the 64-bit value and vice versa.
duke@0 1333 OptoReg::Name tdest = dst_first;
duke@0 1334
duke@0 1335 if (src_first == dst_first) {
duke@0 1336 tdest = OptoReg::Name(R_O7_num);
duke@0 1337 size += 4;
duke@0 1338 }
duke@0 1339
duke@0 1340 if( cbuf ) {
duke@0 1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
duke@0 1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
duke@0 1343 // ShrL_reg_imm6
duke@0 1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
duke@0 1345 // ShrR_reg_imm6 src, 0, dst
duke@0 1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
duke@0 1347 if (tdest != dst_first) {
duke@0 1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
duke@0 1349 }
duke@0 1350 }
duke@0 1351 #ifndef PRODUCT
duke@0 1352 else if( !do_size ) {
duke@0 1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
duke@0 1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
duke@0 1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
duke@0 1356 if (tdest != dst_first) {
duke@0 1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
duke@0 1358 }
duke@0 1359 }
duke@0 1360 #endif // PRODUCT
duke@0 1361 return size+8;
duke@0 1362 }
duke@0 1363 #endif // !_LP64
duke@0 1364 // Else normal reg-reg copy
duke@0 1365 assert( src_second != dst_first, "smashed second before evacuating it" );
duke@0 1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
duke@0 1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
duke@0 1368 // This moves an aligned adjacent pair.
duke@0 1369 // See if we are done.
duke@0 1370 if( src_first+1 == src_second && dst_first+1 == dst_second )
duke@0 1371 return size;
duke@0 1372 }
duke@0 1373
duke@0 1374 // Check for integer store
duke@0 1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
duke@0 1376 int offset = ra_->reg2offset(dst_first);
duke@0 1377 // Further check for aligned-adjacent pair, so we can use a double store
duke@0 1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
duke@0 1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
duke@0 1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
duke@0 1381 }
duke@0 1382
duke@0 1383 // Check for integer load
duke@0 1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
duke@0 1385 int offset = ra_->reg2offset(src_first);
duke@0 1386 // Further check for aligned-adjacent pair, so we can use a double load
duke@0 1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
duke@0 1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
duke@0 1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
duke@0 1390 }
duke@0 1391
duke@0 1392 // Check for float reg-reg copy
duke@0 1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
duke@0 1394 // Further check for aligned-adjacent pair, so we can use a double move
duke@0 1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
duke@0 1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
duke@0 1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
duke@0 1398 }
duke@0 1399
duke@0 1400 // Check for float store
duke@0 1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
duke@0 1402 int offset = ra_->reg2offset(dst_first);
duke@0 1403 // Further check for aligned-adjacent pair, so we can use a double store
duke@0 1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
duke@0 1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
duke@0 1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
duke@0 1407 }
duke@0 1408
duke@0 1409 // Check for float load
duke@0 1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
duke@0 1411 int offset = ra_->reg2offset(src_first);
duke@0 1412 // Further check for aligned-adjacent pair, so we can use a double load
duke@0 1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
duke@0 1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
duke@0 1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
duke@0 1416 }
duke@0 1417
duke@0 1418 // --------------------------------------------------------------------
duke@0 1419 // Check for hi bits still needing moving. Only happens for misaligned
duke@0 1420 // arguments to native calls.
duke@0 1421 if( src_second == dst_second )
duke@0 1422 return size; // Self copy; no move
duke@0 1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
duke@0 1424
duke@0 1425 #ifndef _LP64
duke@0 1426 // In the LP64 build, all registers can be moved as aligned/adjacent
twisti@580 1427 // pairs, so there's never any need to move the high bits separately.
duke@0 1428 // The 32-bit builds have to deal with the 32-bit ABI which can force
duke@0 1429 // all sorts of silly alignment problems.
duke@0 1430
duke@0 1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top
duke@0 1432 // 32-bits of a 64-bit register, but are needed in low bits of another
duke@0 1433 // register (else it's a hi-bits-to-hi-bits copy which should have
duke@0 1434 // happened already as part of a 64-bit move)
duke@0 1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
duke@0 1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
duke@0 1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
duke@0 1438 // Shift src_second down to dst_second's low bits.
duke@0 1439 if( cbuf ) {
duke@0 1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
duke@0 1441 #ifndef PRODUCT
duke@0 1442 } else if( !do_size ) {
duke@0 1443 if( size != 0 ) st->print("\n\t");
duke@0 1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
duke@0 1445 #endif
duke@0 1446 }
duke@0 1447 return size+4;
duke@0 1448 }
duke@0 1449
duke@0 1450 // Check for high word integer store. Must down-shift the hi bits
duke@0 1451 // into a temp register, then fall into the case of storing int bits.
duke@0 1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
duke@0 1453 // Shift src_second down to dst_second's low bits.
duke@0 1454 if( cbuf ) {
duke@0 1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
duke@0 1456 #ifndef PRODUCT
duke@0 1457 } else if( !do_size ) {
duke@0 1458 if( size != 0 ) st->print("\n\t");
duke@0 1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
duke@0 1460 #endif
duke@0 1461 }
duke@0 1462 size+=4;
duke@0 1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
duke@0 1464 }
duke@0 1465
duke@0 1466 // Check for high word integer load
duke@0 1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
duke@0 1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
duke@0 1469
duke@0 1470 // Check for high word integer store
duke@0 1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
duke@0 1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
duke@0 1473
duke@0 1474 // Check for high word float store
duke@0 1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
duke@0 1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
duke@0 1477
duke@0 1478 #endif // !_LP64
duke@0 1479
duke@0 1480 Unimplemented();
duke@0 1481 }
duke@0 1482
duke@0 1483 #ifndef PRODUCT
duke@0 1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
duke@0 1485 implementation( NULL, ra_, false, st );
duke@0 1486 }
duke@0 1487 #endif
duke@0 1488
duke@0 1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1490 implementation( &cbuf, ra_, false, NULL );
duke@0 1491 }
duke@0 1492
duke@0 1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
duke@0 1494 return implementation( NULL, ra_, true, NULL );
duke@0 1495 }
duke@0 1496
duke@0 1497 //=============================================================================
duke@0 1498 #ifndef PRODUCT
duke@0 1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
duke@0 1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
duke@0 1501 }
duke@0 1502 #endif
duke@0 1503
duke@0 1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
duke@0 1505 MacroAssembler _masm(&cbuf);
duke@0 1506 for(int i = 0; i < _count; i += 1) {
duke@0 1507 __ nop();
duke@0 1508 }
duke@0 1509 }
duke@0 1510
duke@0 1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
duke@0 1512 return 4 * _count;
duke@0 1513 }
duke@0 1514
duke@0 1515
duke@0 1516 //=============================================================================
duke@0 1517 #ifndef PRODUCT
duke@0 1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
duke@0 1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
duke@0 1520 int reg = ra_->get_reg_first(this);
duke@0 1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
duke@0 1522 }
duke@0 1523 #endif
duke@0 1524
duke@0 1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1526 MacroAssembler _masm(&cbuf);
duke@0 1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
duke@0 1528 int reg = ra_->get_encode(this);
duke@0 1529
duke@0 1530 if (Assembler::is_simm13(offset)) {
duke@0 1531 __ add(SP, offset, reg_to_register_object(reg));
duke@0 1532 } else {
duke@0 1533 __ set(offset, O7);
duke@0 1534 __ add(SP, O7, reg_to_register_object(reg));
duke@0 1535 }
duke@0 1536 }
duke@0 1537
duke@0 1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
duke@0 1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
duke@0 1540 assert(ra_ == ra_->C->regalloc(), "sanity");
duke@0 1541 return ra_->C->scratch_emit_size(this);
duke@0 1542 }
duke@0 1543
duke@0 1544 //=============================================================================
duke@0 1545
duke@0 1546 // emit call stub, compiled java to interpretor
duke@0 1547 void emit_java_to_interp(CodeBuffer &cbuf ) {
duke@0 1548
duke@0 1549 // Stub is fixed up when the corresponding call is converted from calling
duke@0 1550 // compiled code to calling interpreted code.
duke@0 1551 // set (empty), G5
duke@0 1552 // jmp -1
duke@0 1553
duke@0 1554 address mark = cbuf.inst_mark(); // get mark within main instrs section
duke@0 1555
duke@0 1556 MacroAssembler _masm(&cbuf);
duke@0 1557
duke@0 1558 address base =
duke@0 1559 __ start_a_stub(Compile::MAX_stubs_size);
duke@0 1560 if (base == NULL) return; // CodeBuffer::expand failed
duke@0 1561
duke@0 1562 // static stub relocation stores the instruction address of the call
duke@0 1563 __ relocate(static_stub_Relocation::spec(mark));
duke@0 1564
duke@0 1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
duke@0 1566
duke@0 1567 __ set_inst_mark();
twisti@720 1568 AddressLiteral addrlit(-1);
twisti@720 1569 __ JUMP(addrlit, G3, 0);
duke@0 1570
duke@0 1571 __ delayed()->nop();
duke@0 1572
duke@0 1573 // Update current stubs pointer and restore code_end.
duke@0 1574 __ end_a_stub();
duke@0 1575 }
duke@0 1576
duke@0 1577 // size of call stub, compiled java to interpretor
duke@0 1578 uint size_java_to_interp() {
duke@0 1579 // This doesn't need to be accurate but it must be larger or equal to
duke@0 1580 // the real size of the stub.
duke@0 1581 return (NativeMovConstReg::instruction_size + // sethi/setlo;
duke@0 1582 NativeJump::instruction_size + // sethi; jmp; nop
duke@0 1583 (TraceJumps ? 20 * BytesPerInstWord : 0) );
duke@0 1584 }
duke@0 1585 // relocation entries for call stub, compiled java to interpretor
duke@0 1586 uint reloc_java_to_interp() {
duke@0 1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
duke@0 1588 }
duke@0 1589
duke@0 1590
duke@0 1591 //=============================================================================
duke@0 1592 #ifndef PRODUCT
duke@0 1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
duke@0 1594 st->print_cr("\nUEP:");
duke@0 1595 #ifdef _LP64
coleenp@108 1596 if (UseCompressedOops) {
kvn@619 1597 assert(Universe::heap() != NULL, "java heap should be initialized");
coleenp@108 1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
coleenp@108 1599 st->print_cr("\tSLL R_G5,3,R_G5");
kvn@619 1600 if (Universe::narrow_oop_base() != NULL)
kvn@619 1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
coleenp@108 1602 } else {
coleenp@108 1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
coleenp@108 1604 }
duke@0 1605 st->print_cr("\tCMP R_G5,R_G3" );
duke@0 1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
duke@0 1607 #else // _LP64
duke@0 1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
duke@0 1609 st->print_cr("\tCMP R_G5,R_G3" );
duke@0 1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
duke@0 1611 #endif // _LP64
duke@0 1612 }
duke@0 1613 #endif
duke@0 1614
duke@0 1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
duke@0 1616 MacroAssembler _masm(&cbuf);
duke@0 1617 Label L;
duke@0 1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
duke@0 1619 Register temp_reg = G3;
duke@0 1620 assert( G5_ic_reg != temp_reg, "conflicting registers" );
duke@0 1621
twisti@580 1622 // Load klass from receiver
coleenp@108 1623 __ load_klass(O0, temp_reg);
duke@0 1624 // Compare against expected klass
duke@0 1625 __ cmp(temp_reg, G5_ic_reg);
duke@0 1626 // Branch to miss code, checks xcc or icc depending
duke@0 1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
duke@0 1628 }
duke@0 1629
duke@0 1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
duke@0 1631 return MachNode::size(ra_);
duke@0 1632 }
duke@0 1633
duke@0 1634
duke@0 1635 //=============================================================================
duke@0 1636
duke@0 1637 uint size_exception_handler() {
duke@0 1638 if (TraceJumps) {
duke@0 1639 return (400); // just a guess
duke@0 1640 }
duke@0 1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop
duke@0 1642 }
duke@0 1643
duke@0 1644 uint size_deopt_handler() {
duke@0 1645 if (TraceJumps) {
duke@0 1646 return (400); // just a guess
duke@0 1647 }
duke@0 1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
duke@0 1649 }
duke@0 1650
duke@0 1651 // Emit exception handler code.
duke@0 1652 int emit_exception_handler(CodeBuffer& cbuf) {
duke@0 1653 Register temp_reg = G3;
twisti@720 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
duke@0 1655 MacroAssembler _masm(&cbuf);
duke@0 1656
duke@0 1657 address base =
duke@0 1658 __ start_a_stub(size_exception_handler());
duke@0 1659 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1660
duke@0 1661 int offset = __ offset();
duke@0 1662
twisti@720 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
duke@0 1664 __ delayed()->nop();
duke@0 1665
duke@0 1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
duke@0 1667
duke@0 1668 __ end_a_stub();
duke@0 1669
duke@0 1670 return offset;
duke@0 1671 }
duke@0 1672
duke@0 1673 int emit_deopt_handler(CodeBuffer& cbuf) {
duke@0 1674 // Can't use any of the current frame's registers as we may have deopted
duke@0 1675 // at a poll and everything (including G3) can be live.
duke@0 1676 Register temp_reg = L0;
twisti@720 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
duke@0 1678 MacroAssembler _masm(&cbuf);
duke@0 1679
duke@0 1680 address base =
duke@0 1681 __ start_a_stub(size_deopt_handler());
duke@0 1682 if (base == NULL) return 0; // CodeBuffer::expand failed
duke@0 1683
duke@0 1684 int offset = __ offset();
duke@0 1685 __ save_frame(0);
twisti@720 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
duke@0 1687 __ delayed()->restore();
duke@0 1688
duke@0 1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
duke@0 1690
duke@0 1691 __ end_a_stub();
duke@0 1692 return offset;
duke@0 1693
duke@0 1694 }
duke@0 1695
duke@0 1696 // Given a register encoding, produce a Integer Register object
duke@0 1697 static Register reg_to_register_object(int register_encoding) {
duke@0 1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
duke@0 1699 return as_Register(register_encoding);
duke@0 1700 }
duke@0 1701
duke@0 1702 // Given a register encoding, produce a single-precision Float Register object
duke@0 1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
duke@0 1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
duke@0 1705 return as_SingleFloatRegister(register_encoding);
duke@0 1706 }
duke@0 1707
duke@0 1708 // Given a register encoding, produce a double-precision Float Register object
duke@0 1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
duke@0 1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
duke@0 1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
duke@0 1712 return as_DoubleFloatRegister(register_encoding);
duke@0 1713 }
duke@0 1714
twisti@747 1715 const bool Matcher::match_rule_supported(int opcode) {
twisti@747 1716 if (!has_match_rule(opcode))
twisti@747 1717 return false;
twisti@747 1718
twisti@747 1719 switch (opcode) {
twisti@747 1720 case Op_CountLeadingZerosI:
twisti@747 1721 case Op_CountLeadingZerosL:
twisti@747 1722 case Op_CountTrailingZerosI:
twisti@747 1723 case Op_CountTrailingZerosL:
twisti@747 1724 if (!UsePopCountInstruction)
twisti@747 1725 return false;
twisti@747 1726 break;
twisti@747 1727 }
twisti@747 1728
twisti@747 1729 return true; // Per default match rules are supported.
twisti@747 1730 }
twisti@747 1731
duke@0 1732 int Matcher::regnum_to_fpu_offset(int regnum) {
duke@0 1733 return regnum - 32; // The FP registers are in the second chunk
duke@0 1734 }
duke@0 1735
duke@0 1736 #ifdef ASSERT
duke@0 1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding
duke@0 1738 #endif
duke@0 1739
duke@0 1740 // Vector width in bytes
duke@0 1741 const uint Matcher::vector_width_in_bytes(void) {
duke@0 1742 return 8;
duke@0 1743 }
duke@0 1744
duke@0 1745 // Vector ideal reg
duke@0 1746 const uint Matcher::vector_ideal_reg(void) {
duke@0 1747 return Op_RegD;
duke@0 1748 }
duke@0 1749
duke@0 1750 // USII supports fxtof through the whole range of number, USIII doesn't
duke@0 1751 const bool Matcher::convL2FSupported(void) {
duke@0 1752 return VM_Version::has_fast_fxtof();
duke@0 1753 }
duke@0 1754
duke@0 1755 // Is this branch offset short enough that a short branch can be used?
duke@0 1756 //
duke@0 1757 // NOTE: If the platform does not provide any short branch variants, then
duke@0 1758 // this method should return false for offset 0.
never@406 1759 bool Matcher::is_short_branch_offset(int rule, int offset) {
duke@0 1760 return false;
duke@0 1761 }
duke@0 1762
duke@0 1763 const bool Matcher::isSimpleConstant64(jlong value) {
duke@0 1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
duke@0 1765 // Depends on optimizations in MacroAssembler::setx.
duke@0 1766 int hi = (int)(value >> 32);
duke@0 1767 int lo = (int)(value & ~0);
duke@0 1768 return (hi == 0) || (hi == -1) || (lo == 0);
duke@0 1769 }
duke@0 1770
duke@0 1771 // No scaling for the parameter the ClearArray node.
duke@0 1772 const bool Matcher::init_array_count_is_in_bytes = true;
duke@0 1773
duke@0 1774 // Threshold size for cleararray.
duke@0 1775 const int Matcher::init_array_short_size = 8 * BytesPerLong;
duke@0 1776
duke@0 1777 // Should the Matcher clone shifts on addressing modes, expecting them to
duke@0 1778 // be subsumed into complex addressing expressions or compute them into
duke@0 1779 // registers? True for Intel but false for most RISCs
duke@0 1780 const bool Matcher::clone_shift_expressions = false;
duke@0 1781
duke@0 1782 // Is it better to copy float constants, or load them directly from memory?
duke@0 1783 // Intel can load a float constant from a direct address, requiring no
duke@0 1784 // extra registers. Most RISCs will have to materialize an address into a
duke@0 1785 // register first, so they would do better to copy the constant from stack.
duke@0 1786 const bool Matcher::rematerialize_float_constants = false;
duke@0 1787
duke@0 1788 // If CPU can load and store mis-aligned doubles directly then no fixup is
duke@0 1789 // needed. Else we split the double into 2 integer pieces and move it
duke@0 1790 // piece-by-piece. Only happens when passing doubles into C code as the
duke@0 1791 // Java calling convention forces doubles to be aligned.
duke@0 1792 #ifdef _LP64
duke@0 1793 const bool Matcher::misaligned_doubles_ok = true;
duke@0 1794 #else
duke@0 1795 const bool Matcher::misaligned_doubles_ok = false;
duke@0 1796 #endif
duke@0 1797
duke@0 1798 // No-op on SPARC.
duke@0 1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
duke@0 1800 }
duke@0 1801
duke@0 1802 // Advertise here if the CPU requires explicit rounding operations
duke@0 1803 // to implement the UseStrictFP mode.
duke@0 1804 const bool Matcher::strict_fp_requires_explicit_rounding = false;
duke@0 1805
duke@0 1806 // Do floats take an entire double register or just half?
duke@0 1807 const bool Matcher::float_in_double = false;
duke@0 1808
duke@0 1809 // Do ints take an entire long register or just half?
duke@0 1810 // Note that we if-def off of _LP64.
duke@0 1811 // The relevant question is how the int is callee-saved. In _LP64
duke@0 1812 // the whole long is written but de-opt'ing will have to extract
duke@0 1813 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
duke@0 1814 #ifdef _LP64
duke@0 1815 const bool Matcher::int_in_long = true;
duke@0 1816 #else
duke@0 1817 const bool Matcher::int_in_long = false;
duke@0 1818 #endif
duke@0 1819
duke@0 1820 // Return whether or not this register is ever used as an argument. This
duke@0 1821 // function is used on startup to build the trampoline stubs in generateOptoStub.
duke@0 1822 // Registers not mentioned will be killed by the VM call in the trampoline, and
duke@0 1823 // arguments in those registers not be available to the callee.
duke@0 1824 bool Matcher::can_be_java_arg( int reg ) {
duke@0 1825 // Standard sparc 6 args in registers
duke@0 1826 if( reg == R_I0_num ||
duke@0 1827 reg == R_I1_num ||
duke@0 1828 reg == R_I2_num ||
duke@0 1829 reg == R_I3_num ||
duke@0 1830 reg == R_I4_num ||
duke@0 1831 reg == R_I5_num ) return true;
duke@0 1832 #ifdef _LP64
duke@0 1833 // 64-bit builds can pass 64-bit pointers and longs in
duke@0 1834 // the high I registers
duke@0 1835 if( reg == R_I0H_num ||
duke@0 1836 reg == R_I1H_num ||
duke@0 1837 reg == R_I2H_num ||
duke@0 1838 reg == R_I3H_num ||
duke@0 1839 reg == R_I4H_num ||
duke@0 1840 reg == R_I5H_num ) return true;
coleenp@108 1841
coleenp@108 1842 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
coleenp@108 1843 return true;
coleenp@108 1844 }
coleenp@108 1845
duke@0 1846 #else
duke@0 1847 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
duke@0 1848 // Longs cannot be passed in O regs, because O regs become I regs
duke@0 1849 // after a 'save' and I regs get their high bits chopped off on
duke@0 1850 // interrupt.
duke@0 1851 if( reg == R_G1H_num || reg == R_G1_num ) return true;
duke@0 1852 if( reg == R_G4H_num || reg == R_G4_num ) return true;
duke@0 1853 #endif
duke@0 1854 // A few float args in registers
duke@0 1855 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
duke@0 1856
duke@0 1857 return false;
duke@0 1858 }
duke@0 1859
duke@0 1860 bool Matcher::is_spillable_arg( int reg ) {
duke@0 1861 return can_be_java_arg(reg);
duke@0 1862 }
duke@0 1863
duke@0 1864 // Register for DIVI projection of divmodI
duke@0 1865 RegMask Matcher::divI_proj_mask() {
duke@0 1866 ShouldNotReachHere();
duke@0 1867 return RegMask();
duke@0 1868 }
duke@0 1869
duke@0 1870 // Register for MODI projection of divmodI
duke@0 1871 RegMask Matcher::modI_proj_mask() {
duke@0 1872 ShouldNotReachHere();
duke@0 1873 return RegMask();
duke@0 1874 }
duke@0 1875
duke@0 1876 // Register for DIVL projection of divmodL
duke@0 1877 RegMask Matcher::divL_proj_mask() {
duke@0 1878 ShouldNotReachHere();
duke@0 1879 return RegMask();
duke@0 1880 }
duke@0 1881
duke@0 1882 // Register for MODL projection of divmodL
duke@0 1883 RegMask Matcher::modL_proj_mask() {
duke@0 1884 ShouldNotReachHere();
duke@0 1885 return RegMask();
duke@0 1886 }
duke@0 1887
duke@0 1888 %}
duke@0 1889
duke@0 1890
duke@0 1891 // The intptr_t operand types, defined by textual substitution.
duke@0 1892 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
duke@0 1893 #ifdef _LP64
duke@0 1894 #define immX immL
duke@0 1895 #define immX13 immL13
duke@0 1896 #define iRegX iRegL
duke@0 1897 #define g1RegX g1RegL
duke@0 1898 #else
duke@0 1899 #define immX immI
duke@0 1900 #define immX13 immI13
duke@0 1901 #define iRegX iRegI
duke@0 1902 #define g1RegX g1RegI
duke@0 1903 #endif
duke@0 1904
duke@0 1905 //----------ENCODING BLOCK-----------------------------------------------------
duke@0 1906 // This block specifies the encoding classes used by the compiler to output
duke@0 1907 // byte streams. Encoding classes are parameterized macros used by
duke@0 1908 // Machine Instruction Nodes in order to generate the bit encoding of the
duke@0 1909 // instruction. Operands specify their base encoding interface with the
duke@0 1910 // interface keyword. There are currently supported four interfaces,
duke@0 1911 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
duke@0 1912 // operand to generate a function which returns its register number when
duke@0 1913 // queried. CONST_INTER causes an operand to generate a function which
duke@0 1914 // returns the value of the constant when queried. MEMORY_INTER causes an
duke@0 1915 // operand to generate four functions which return the Base Register, the
duke@0 1916 // Index Register, the Scale Value, and the Offset Value of the operand when
duke@0 1917 // queried. COND_INTER causes an operand to generate six functions which
duke@0 1918 // return the encoding code (ie - encoding bits for the instruction)
duke@0 1919 // associated with each basic boolean condition for a conditional instruction.
duke@0 1920 //
duke@0 1921 // Instructions specify two basic values for encoding. Again, a function
duke@0 1922 // is available to check if the constant displacement is an oop. They use the
duke@0 1923 // ins_encode keyword to specify their encoding classes (which must be
duke@0 1924 // a sequence of enc_class names, and their parameters, specified in
duke@0 1925 // the encoding block), and they use the
duke@0 1926 // opcode keyword to specify, in order, their primary, secondary, and
duke@0 1927 // tertiary opcode. Only the opcode sections which a particular instruction
duke@0 1928 // needs for encoding need to be specified.
duke@0 1929 encode %{
duke@0 1930 enc_class enc_untested %{
duke@0 1931 #ifdef ASSERT
duke@0 1932 MacroAssembler _masm(&cbuf);
duke@0 1933 __ untested("encoding");
duke@0 1934 #endif
duke@0 1935 %}
duke@0 1936
duke@0 1937 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
duke@0 1938 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
duke@0 1939 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
duke@0 1940 %}
duke@0 1941
never@406 1942 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
never@406 1943 emit_form3_mem_reg(cbuf, this, $primary, -1,
never@406 1944 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
never@406 1945 %}
never@406 1946
duke@0 1947 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
never@406 1948 emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
duke@0 1949 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
duke@0 1950 %}
duke@0 1951
duke@0 1952 enc_class form3_mem_prefetch_read( memory mem ) %{
never@406 1953 emit_form3_mem_reg(cbuf, this, $primary, -1,
duke@0 1954 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
duke@0 1955 %}
duke@0 1956
duke@0 1957 enc_class form3_mem_prefetch_write( memory mem ) %{
never@406 1958 emit_form3_mem_reg(cbuf, this, $primary, -1,
duke@0 1959 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
duke@0 1960 %}
duke@0 1961
duke@0 1962 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
duke@0 1963 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
duke@0 1964 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
duke@0 1965 guarantee($mem$$index == R_G0_enc, "double index?");
never@406 1966 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
never@406 1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
duke@0 1968 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
duke@0 1969 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
duke@0 1970 %}
duke@0 1971
duke@0 1972 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
duke@0 1973 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
duke@0 1974 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
duke@0 1975 guarantee($mem$$index == R_G0_enc, "double index?");
duke@0 1976 // Load long with 2 instructions
never@406 1977 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
never@406 1978 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
duke@0 1979 %}
duke@0 1980
duke@0 1981 //%%% form3_mem_plus_4_reg is a hack--get rid of it
duke@0 1982 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
duke@0 1983 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
never@406 1984 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
duke@0 1985 %}
duke@0 1986
duke@0 1987 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
duke@0 1988 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 1989 if( $rs2$$reg != $rd$$reg )
duke@0 1990 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
duke@0 1991 %}
duke@0 1992
duke@0 1993 // Target lo half of long
duke@0 1994 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
duke@0 1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 1996 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
duke@0 1997 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
duke@0 1998 %}
duke@0 1999
duke@0 2000 // Source lo half of long
duke@0 2001 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
duke@0 2002 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2003 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
duke@0 2004 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
duke@0 2005 %}
duke@0 2006
duke@0 2007 // Target hi half of long
duke@0 2008 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
duke@0 2009 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
duke@0 2010 %}
duke@0 2011
duke@0 2012 // Source lo half of long, and leave it sign extended.
duke@0 2013 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
duke@0 2014 // Sign extend low half
duke@0 2015 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
duke@0 2016 %}
duke@0 2017
duke@0 2018 // Source hi half of long, and leave it sign extended.
duke@0 2019 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
duke@0 2020 // Shift high half to low half
duke@0 2021 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
duke@0 2022 %}
duke@0 2023
duke@0 2024 // Source hi half of long
duke@0 2025 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
duke@0 2026 // Encode a reg-reg copy. If it is useless, then empty encoding.
duke@0 2027 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
duke@0 2028 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
duke@0 2029 %}
duke@0 2030
duke@0 2031 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
duke@0 2032 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
duke@0 2033 %}
duke@0 2034
duke@0 2035 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
duke@0 2036 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
duke@0 2037 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
duke@0 2038 %}
duke@0 2039
duke@0 2040 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
duke@0 2041 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
duke@0 2042 // clear if nothing else is happening
duke@0 2043 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
duke@0 2044 // blt,a,pn done
duke@0 2045 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
duke@0 2046 // mov dst,-1 in delay slot
duke@0 2047 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
duke@0 2048 %}
duke@0 2049
duke@0 2050 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
duke@0 2051 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
duke@0 2052 %}
duke@0 2053
duke@0 2054 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
duke@0 2055 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
duke@0 2056 %}
duke@0 2057
duke@0 2058 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
duke@0 2059 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
duke@0 2060 %}
duke@0 2061
duke@0 2062 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
duke@0 2063 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
duke@0 2064 %}
duke@0 2065
duke@0 2066 enc_class move_return_pc_to_o1() %{
duke@0 2067 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
duke@0 2068 %}
duke@0 2069
duke@0 2070 #ifdef _LP64
duke@0 2071 /* %%% merge with enc_to_bool */
duke@0 2072 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
duke@0 2073 MacroAssembler _masm(&cbuf);
duke@0 2074
duke@0 2075 Register src_reg = reg_to_register_object($src$$reg);
duke@0 2076 Register dst_reg = reg_to_register_object($dst$$reg);
duke@0 2077 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
duke@0 2078 %}
duke@0 2079 #endif
duke@0 2080
duke@0 2081 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
duke@0 2082 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
duke@0 2083 MacroAssembler _masm(&cbuf);
duke@0 2084
duke@0 2085 Register p_reg = reg_to_register_object($p$$reg);
duke@0 2086 Register q_reg = reg_to_register_object($q$$reg);
duke@0 2087 Register y_reg = reg_to_register_object($y$$reg);
duke@0 2088 Register tmp_reg = reg_to_register_object($tmp$$reg);
duke@0 2089
duke@0 2090 __ subcc( p_reg, q_reg, p_reg );
duke@0 2091 __ add ( p_reg, y_reg, tmp_reg );
duke@0 2092 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
duke@0 2093 %}
duke@0 2094
duke@0 2095 enc_class form_d2i_helper(regD src, regF dst) %{
duke@0 2096 // fcmp %fcc0,$src,$src
duke@0 2097 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
duke@0 2098 // branch %fcc0 not-nan, predict taken
duke@0 2099 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
duke@0 2100 // fdtoi $src,$dst
duke@0 2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
duke@0 2102 // fitos $dst,$dst (if nan)
duke@0 2103 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
duke@0 2104 // clear $dst (if nan)
duke@0 2105 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
duke@0 2106 // carry on here...
duke@0 2107 %}
duke@0 2108
duke@0 2109 enc_class form_d2l_helper(regD src, regD dst) %{
duke@0 2110 // fcmp %fcc0,$src,$src check for NAN
duke@0 2111 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
duke@0 2112 // branch %fcc0 not-nan, predict taken
duke@0 2113 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
duke@0 2114 // fdtox $src,$dst convert in delay slot
duke@0 2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
duke@0 2116 // fxtod $dst,$dst (if nan)
duke@0 2117 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
duke@0 2118 // clear $dst (if nan)
duke@0 2119 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
duke@0 2120 // carry on here...
duke@0 2121 %}
duke@0 2122
duke@0 2123 enc_class form_f2i_helper(regF src, regF dst) %{
duke@0 2124 // fcmps %fcc0,$src,$src
duke@0 2125 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
duke@0 2126 // branch %fcc0 not-nan, predict taken
duke@0 2127 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
duke@0 2128 // fstoi $src,$dst
duke@0 2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
duke@0 2130 // fitos $dst,$dst (if nan)
duke@0 2131 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
duke@0 2132 // clear $dst (if nan)
duke@0 2133 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
duke@0 2134 // carry on here...
duke@0 2135 %}
duke@0 2136
duke@0 2137 enc_class form_f2l_helper(regF src, regD dst) %{
duke@0 2138 // fcmps %fcc0,$src,$src
duke@0 2139 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
duke@0 2140 // branch %fcc0 not-nan, predict taken
duke@0 2141 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
duke@0 2142 // fstox $src,$dst
duke@0 2143 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
duke@0 2144 // fxtod $dst,$dst (if nan)
duke@0 2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
duke@0 2146 // clear $dst (if nan)
duke@0 2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
duke@0 2148 // carry on here...
duke@0 2149 %}
duke@0 2150
duke@0 2151 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
duke@0 2152 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
duke@0 2153 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
duke@0 2154 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
duke@0 2155
duke@0 2156 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
duke@0 2157
duke@0 2158 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
duke@0 2159 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
duke@0 2160
duke@0 2161 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
duke@0 2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
duke@0 2163 %}
duke@0 2164
duke@0 2165 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
duke@0 2166 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
duke@0 2167 %}
duke@0 2168
duke@0 2169 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
duke@0 2170 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
duke@0 2171 %}
duke@0 2172
duke@0 2173 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
duke@0 2174 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
duke@0 2175 %}
duke@0 2176
duke@0 2177 enc_class form3_convI2F(regF rs2, regF rd) %{
duke@0 2178 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
duke@0 2179 %}
duke@0 2180
duke@0 2181 // Encloding class for traceable jumps
duke@0 2182 enc_class form_jmpl(g3RegP dest) %{
duke@0 2183 emit_jmpl(cbuf, $dest$$reg);
duke@0 2184 %}
duke@0 2185
duke@0 2186 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
duke@0 2187 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
duke@0 2188 %}
duke@0 2189
duke@0 2190 enc_class form2_nop() %{
duke@0 2191 emit_nop(cbuf);
duke@0 2192 %}
duke@0 2193
duke@0 2194 enc_class form2_illtrap() %{
duke@0 2195 emit_illtrap(cbuf);
duke@0 2196 %}
duke@0 2197
duke@0 2198
duke@0 2199 // Compare longs and convert into -1, 0, 1.
duke@0 2200 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
duke@0 2201 // CMP $src1,$src2
duke@0 2202 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
duke@0 2203 // blt,a,pn done
duke@0 2204 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
duke@0 2205 // mov dst,-1 in delay slot
duke@0 2206 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
duke@0 2207 // bgt,a,pn done
duke@0 2208 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
duke@0 2209 // mov dst,1 in delay slot
duke@0 2210 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
duke@0 2211 // CLR $dst
duke@0 2212 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
duke@0 2213 %}
duke@0 2214
duke@0 2215 enc_class enc_PartialSubtypeCheck() %{
duke@0 2216 MacroAssembler _masm(&cbuf);
duke@0 2217 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
duke@0 2218 __ delayed()->nop();
duke@0 2219 %}
duke@0 2220
duke@0 2221 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
duke@0 2222 MacroAssembler _masm(&cbuf);
duke@0 2223 Label &L = *($labl$$label);
duke@0 2224 Assembler::Predict predict_taken =
duke@0 2225 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
duke@0 2226
duke@0 2227 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
duke@0 2228 __ delayed()->nop();
duke@0 2229 %}
duke@0 2230
duke@0 2231 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
duke@0 2232 MacroAssembler _masm(&cbuf);
duke@0 2233 Label &L = *($labl$$label);
duke@0 2234 Assembler::Predict predict_taken =
duke@0 2235 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
duke@0 2236
duke@0 2237 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
duke@0 2238 __ delayed()->nop();
duke@0 2239 %}
duke@0 2240
duke@0 2241 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
duke@0 2242 MacroAssembler _masm(&cbuf);
duke@0 2243 Label &L = *($labl$$label);
duke@0 2244 Assembler::Predict predict_taken =
duke@0 2245 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
duke@0 2246
duke@0 2247 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
duke@0 2248 __ delayed()->nop();
duke@0 2249 %}
duke@0 2250
duke@0 2251 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
duke@0 2252 MacroAssembler _masm(&cbuf);
duke@0 2253 Label &L = *($labl$$label);
duke@0 2254 Assembler::Predict predict_taken =
duke@0 2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
duke@0 2256
duke@0 2257 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
duke@0 2258 __ delayed()->nop();
duke@0 2259 %}
duke@0 2260
duke@0 2261 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
duke@0 2262 MacroAssembler _masm(&cbuf);
duke@0 2263
duke@0 2264 Register switch_reg = as_Register($switch_val$$reg);
duke@0 2265 Register table_reg = O7;
duke@0 2266
duke@0 2267 address table_base = __ address_table_constant(_index2label);
duke@0 2268 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
duke@0 2269
twisti@720 2270 // Move table address into a register.
twisti@720 2271 __ set(table_base, table_reg, rspec);
duke@0 2272
duke@0 2273 // Jump to base address + switch value
duke@0 2274 __ ld_ptr(table_reg, switch_reg, table_reg);
duke@0 2275 __ jmp(table_reg, G0);
duke@0 2276 __ delayed()->nop();
duke@0 2277
duke@0 2278 %}
duke@0 2279
duke@0 2280 enc_class enc_ba( Label labl ) %{
duke@0 2281 MacroAssembler _masm(&cbuf);
duke@0 2282 Label &L = *($labl$$label);
duke@0 2283 __ ba(false, L);
duke@0 2284 __ delayed()->nop();
duke@0 2285 %}
duke@0 2286
duke@0 2287 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
duke@0 2288 MacroAssembler _masm(&cbuf);
duke@0 2289 Label &L = *$labl$$label;
duke@0 2290 Assembler::Predict predict_taken =
duke@0 2291 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
duke@0 2292
duke@0 2293 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
duke@0 2294 __ delayed()->nop();
duke@0 2295 %}
duke@0 2296
duke@0 2297 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
duke@0 2298 int op = (Assembler::arith_op << 30) |
duke@0 2299 ($dst$$reg << 25) |
duke@0 2300 (Assembler::movcc_op3 << 19) |
duke@0 2301 (1 << 18) | // cc2 bit for 'icc'
duke@0 2302 ($cmp$$cmpcode << 14) |
duke@0 2303 (0 << 13) | // select register move
duke@0 2304 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
duke@0 2305 ($src$$reg << 0);
duke@0 2306 *((int*)(cbuf.code_end())) = op;
duke@0 2307 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2308 %}
duke@0 2309
duke@0 2310 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
duke@0 2311 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
duke@0 2312 int op = (Assembler::arith_op << 30) |
duke@0 2313 ($dst$$reg << 25) |
duke@0 2314 (Assembler::movcc_op3 << 19) |
duke@0 2315 (1 << 18) | // cc2 bit for 'icc'
duke@0 2316 ($cmp$$cmpcode << 14) |
duke@0 2317 (1 << 13) | // select immediate move
duke@0 2318 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
duke@0 2319 (simm11 << 0);
duke@0 2320 *((int*)(cbuf.code_end())) = op;
duke@0 2321 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2322 %}
duke@0 2323
duke@0 2324 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
duke@0 2325 int op = (Assembler::arith_op << 30) |
duke@0 2326 ($dst$$reg << 25) |
duke@0 2327 (Assembler::movcc_op3 << 19) |
duke@0 2328 (0 << 18) | // cc2 bit for 'fccX'
duke@0 2329 ($cmp$$cmpcode << 14) |
duke@0 2330 (0 << 13) | // select register move
duke@0 2331 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
duke@0 2332 ($src$$reg << 0);
duke@0 2333 *((int*)(cbuf.code_end())) = op;
duke@0 2334 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2335 %}
duke@0 2336
duke@0 2337 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
duke@0 2338 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
duke@0 2339 int op = (Assembler::arith_op << 30) |
duke@0 2340 ($dst$$reg << 25) |
duke@0 2341 (Assembler::movcc_op3 << 19) |
duke@0 2342 (0 << 18) | // cc2 bit for 'fccX'
duke@0 2343 ($cmp$$cmpcode << 14) |
duke@0 2344 (1 << 13) | // select immediate move
duke@0 2345 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
duke@0 2346 (simm11 << 0);
duke@0 2347 *((int*)(cbuf.code_end())) = op;
duke@0 2348 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2349 %}
duke@0 2350
duke@0 2351 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
duke@0 2352 int op = (Assembler::arith_op << 30) |
duke@0 2353 ($dst$$reg << 25) |
duke@0 2354 (Assembler::fpop2_op3 << 19) |
duke@0 2355 (0 << 18) |
duke@0 2356 ($cmp$$cmpcode << 14) |
duke@0 2357 (1 << 13) | // select register move
duke@0 2358 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
duke@0 2359 ($primary << 5) | // select single, double or quad
duke@0 2360 ($src$$reg << 0);
duke@0 2361 *((int*)(cbuf.code_end())) = op;
duke@0 2362 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2363 %}
duke@0 2364
duke@0 2365 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
duke@0 2366 int op = (Assembler::arith_op << 30) |
duke@0 2367 ($dst$$reg << 25) |
duke@0 2368 (Assembler::fpop2_op3 << 19) |
duke@0 2369 (0 << 18) |
duke@0 2370 ($cmp$$cmpcode << 14) |
duke@0 2371 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
duke@0 2372 ($primary << 5) | // select single, double or quad
duke@0 2373 ($src$$reg << 0);
duke@0 2374 *((int*)(cbuf.code_end())) = op;
duke@0 2375 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2376 %}
duke@0 2377
duke@0 2378 // Used by the MIN/MAX encodings. Same as a CMOV, but
duke@0 2379 // the condition comes from opcode-field instead of an argument.
duke@0 2380 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
duke@0 2381 int op = (Assembler::arith_op << 30) |
duke@0 2382 ($dst$$reg << 25) |
duke@0 2383 (Assembler::movcc_op3 << 19) |
duke@0 2384 (1 << 18) | // cc2 bit for 'icc'
duke@0 2385 ($primary << 14) |
duke@0 2386 (0 << 13) | // select register move
duke@0 2387 (0 << 11) | // cc1, cc0 bits for 'icc'
duke@0 2388 ($src$$reg << 0);
duke@0 2389 *((int*)(cbuf.code_end())) = op;
duke@0 2390 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2391 %}
duke@0 2392
duke@0 2393 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
duke@0 2394 int op = (Assembler::arith_op << 30) |
duke@0 2395 ($dst$$reg << 25) |
duke@0 2396 (Assembler::movcc_op3 << 19) |
duke@0 2397 (6 << 16) | // cc2 bit for 'xcc'
duke@0 2398 ($primary << 14) |
duke@0 2399 (0 << 13) | // select register move
duke@0 2400 (0 << 11) | // cc1, cc0 bits for 'icc'
duke@0 2401 ($src$$reg << 0);
duke@0 2402 *((int*)(cbuf.code_end())) = op;
duke@0 2403 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 2404 %}
duke@0 2405
duke@0 2406 // Utility encoding for loading a 64 bit Pointer into a register
duke@0 2407 // The 64 bit pointer is stored in the generated code stream
duke@0 2408 enc_class SetPtr( immP src, iRegP rd ) %{
duke@0 2409 Register dest = reg_to_register_object($rd$$reg);
twisti@720 2410 MacroAssembler _masm(&cbuf);
duke@0 2411 // [RGV] This next line should be generated from ADLC
duke@0 2412 if ( _opnds[1]->constant_is_oop() ) {
duke@0 2413 intptr_t val = $src$$constant;
duke@0 2414 __ set_oop_constant((jobject)val, dest);
duke@0 2415 } else { // non-oop pointers, e.g. card mark base, heap top
twisti@720 2416 __ set($src$$constant, dest);
duke@0 2417 }
duke@0 2418 %}
duke@0 2419
duke@0 2420 enc_class Set13( immI13 src, iRegI rd ) %{
duke@0 2421 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
duke@0 2422 %}
duke@0 2423
duke@0 2424 enc_class SetHi22( immI src, iRegI rd ) %{
duke@0 2425 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
duke@0 2426 %}
duke@0 2427
duke@0 2428 enc_class Set32( immI src, iRegI rd ) %{
duke@0 2429 MacroAssembler _masm(&cbuf);
duke@0 2430 __ set($src$$constant, reg_to_register_object($rd$$reg));
duke@0 2431 %}
duke@0 2432
duke@0 2433 enc_class SetNull( iRegI rd ) %{
duke@0 2434 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
duke@0 2435 %}
duke@0 2436
duke@0 2437 enc_class call_epilog %{
duke@0 2438 if( VerifyStackAtCalls ) {
duke@0 2439 MacroAssembler _masm(&cbuf);
duke@0 2440 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
duke@0 2441 Register temp_reg = G3;
duke@0 2442 __ add(SP, framesize, temp_reg);
duke@0 2443 __ cmp(temp_reg, FP);
duke@0 2444 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
duke@0 2445 }
duke@0 2446 %}
duke@0 2447
duke@0 2448 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
duke@0 2449 // to G1 so the register allocator will not have to deal with the misaligned register
duke@0 2450 // pair.
duke@0 2451 enc_class adjust_long_from_native_call %{
duke@0 2452 #ifndef _LP64
duke@0 2453 if (returns_long()) {
duke@0 2454 // sllx O0,32,O0
duke@0 2455 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
duke@0 2456 // srl O1,0,O1
duke@0 2457 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
duke@0 2458 // or O0,O1,G1
duke@0 2459 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
duke@0 2460 }
duke@0 2461 #endif
duke@0 2462 %}
duke@0 2463
duke@0 2464 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
duke@0 2465 // CALL directly to the runtime
duke@0 2466 // The user of this is responsible for ensuring that R_L7 is empty (killed).
duke@0 2467 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
duke@0 2468 /*preserve_g2=*/true, /*force far call*/true);
duke@0 2469 %}
duke@0 2470
duke@0 2471 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
duke@0 2472 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2473 // who we intended to call.
duke@0 2474 if ( !_method ) {
duke@0 2475 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
duke@0 2476 } else if (_optimized_virtual) {
duke@0 2477 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
duke@0 2478 } else {
duke@0 2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
duke@0 2480 }
duke@0 2481 if( _method ) { // Emit stub for static call
duke@0 2482 emit_java_to_interp(cbuf);
duke@0 2483 }
duke@0 2484 %}
duke@0 2485
duke@0 2486 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
duke@0 2487 MacroAssembler _masm(&cbuf);
duke@0 2488 __ set_inst_mark();
duke@0 2489 int vtable_index = this->_vtable_index;
duke@0 2490 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
duke@0 2491 if (vtable_index < 0) {
duke@0 2492 // must be invalid_vtable_index, not nonvirtual_vtable_index
duke@0 2493 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
duke@0 2494 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
duke@0 2495 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
duke@0 2496 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
duke@0 2497 // !!!!!
duke@0 2498 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
duke@0 2499 // emit_call_dynamic_prologue( cbuf );
duke@0 2500 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
duke@0 2501
duke@0 2502 address virtual_call_oop_addr = __ inst_mark();
duke@0 2503 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
duke@0 2504 // who we intended to call.
duke@0 2505 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
duke@0 2506 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
duke@0 2507 } else {
duke@0 2508 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
duke@0 2509 // Just go thru the vtable
duke@0 2510 // get receiver klass (receiver already checked for non-null)
duke@0 2511 // If we end up going thru a c2i adapter interpreter expects method in G5
duke@0 2512 int off = __ offset();
coleenp@108 2513 __ load_klass(O0, G3_scratch);
coleenp@108 2514 int klass_load_size;
coleenp@108 2515 if (UseCompressedOops) {
kvn@619 2516 assert(Universe::heap() != NULL, "java heap should be initialized");
kvn@619 2517 if (Universe::narrow_oop_base() == NULL)
kvn@619 2518 klass_load_size = 2*BytesPerInstWord;
kvn@619 2519 else
kvn@619 2520 klass_load_size = 3*BytesPerInstWord;
coleenp@108 2521 } else {
coleenp@108 2522 klass_load_size = 1*BytesPerInstWord;
coleenp@108 2523 }
duke@0 2524 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
duke@0 2525 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
duke@0 2526 if( __ is_simm13(v_off) ) {
duke@0 2527 __ ld_ptr(G3, v_off, G5_method);
duke@0 2528 } else {
duke@0 2529 // Generate 2 instructions
duke@0 2530 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
duke@0 2531 __ or3(G5_method, v_off & 0x3ff, G5_method);
duke@0 2532 // ld_ptr, set_hi, set
coleenp@108 2533 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
coleenp@108 2534 "Unexpected instruction size(s)");
duke@0 2535 __ ld_ptr(G3, G5_method, G5_method);
duke@0 2536 }
duke@0 2537 // NOTE: for vtable dispatches, the vtable entry will never be null.
duke@0 2538 // However it may very well end up in handle_wrong_method if the
duke@0 2539 // method is abstract for the particular class.
duke@0 2540 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
duke@0 2541 // jump to target (either compiled code or c2iadapter)
duke@0 2542 __ jmpl(G3_scratch, G0, O7);
duke@0 2543 __ delayed()->nop();
duke@0 2544 }
duke@0 2545 %}
duke@0 2546
duke@0 2547 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
duke@0 2548 MacroAssembler _masm(&cbuf);
duke@0 2549
duke@0 2550 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
duke@0 2551 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
duke@0 2552 // we might be calling a C2I adapter which needs it.
duke@0 2553
duke@0 2554 assert(temp_reg != G5_ic_reg, "conflicting registers");
duke@0 2555 // Load nmethod
duke@0 2556 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
duke@0 2557
duke@0 2558 // CALL to compiled java, indirect the contents of G3
duke@0 2559 __ set_inst_mark();
duke@0 2560 __ callr(temp_reg, G0);
duke@0 2561 __ delayed()->nop();
duke@0 2562 %}
duke@0 2563
duke@0 2564 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
duke@0 2565 MacroAssembler _masm(&cbuf);
duke@0 2566 Register Rdividend = reg_to_register_object($src1$$reg);
duke@0 2567 Register Rdivisor = reg_to_register_object($src2$$reg);
duke@0 2568 Register Rresult = reg_to_register_object($dst$$reg);
duke@0 2569
duke@0 2570 __ sra(Rdivisor, 0, Rdivisor);
duke@0 2571 __ sra(Rdividend, 0, Rdividend);
duke@0 2572 __ sdivx(Rdividend, Rdivisor, Rresult);
duke@0 2573 %}
duke@0 2574
duke@0 2575 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
duke@0 2576 MacroAssembler _masm(&cbuf);
duke@0 2577
duke@0 2578 Register Rdividend = reg_to_register_object($src1$$reg);
duke@0 2579 int divisor = $imm$$constant;
duke@0 2580 Register Rresult = reg_to_register_object($dst$$reg);
duke@0 2581
duke@0 2582 __ sra(Rdividend, 0, Rdividend);
duke@0 2583 __ sdivx(Rdividend, divisor, Rresult);
duke@0 2584 %}
duke@0 2585
duke@0 2586 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
duke@0 2587 MacroAssembler _masm(&cbuf);
duke@0 2588 Register Rsrc1 = reg_to_register_object($src1$$reg);
duke@0 2589 Register Rsrc2 = reg_to_register_object($src2$$reg);
duke@0 2590 Register Rdst = reg_to_register_object($dst$$reg);
duke@0 2591
duke@0 2592 __ sra( Rsrc1, 0, Rsrc1 );
duke@0 2593 __ sra( Rsrc2, 0, Rsrc2 );
duke@0 2594 __ mulx( Rsrc1, Rsrc2, Rdst );
duke@0 2595 __ srlx( Rdst, 32, Rdst );
duke@0 2596 %}
duke@0 2597
duke@0 2598 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
duke@0 2599 MacroAssembler _masm(&cbuf);
duke@0 2600 Register Rdividend = reg_to_register_object($src1$$reg);
duke@0 2601 Register Rdivisor = reg_to_register_object($src2$$reg);
duke@0 2602 Register Rresult = reg_to_register_object($dst$$reg);
duke@0 2603 Register Rscratch = reg_to_register_object($scratch$$reg);
duke@0 2604
duke@0 2605 assert(Rdividend != Rscratch, "");
duke@0 2606 assert(Rdivisor != Rscratch, "");
duke@0 2607
duke@0 2608 __ sra(Rdividend, 0, Rdividend);
duke@0 2609 __ sra(Rdivisor, 0, Rdivisor);
duke@0 2610 __ sdivx(Rdividend, Rdivisor, Rscratch);
duke@0 2611 __ mulx(Rscratch, Rdivisor, Rscratch);
duke@0 2612 __ sub(Rdividend, Rscratch, Rresult);
duke@0 2613 %}
duke@0 2614
duke@0 2615 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
duke@0 2616 MacroAssembler _masm(&cbuf);
duke@0 2617
duke@0 2618 Register Rdividend = reg_to_register_object($src1$$reg);
duke@0 2619 int divisor = $imm$$constant;
duke@0 2620 Register Rresult = reg_to_register_object($dst$$reg);
duke@0 2621 Register Rscratch = reg_to_register_object($scratch$$reg);
duke@0 2622
duke@0 2623 assert(Rdividend != Rscratch, "");
duke@0 2624
duke@0 2625 __ sra(Rdividend, 0, Rdividend);
duke@0 2626 __ sdivx(Rdividend, divisor, Rscratch);
duke@0 2627 __ mulx(Rscratch, divisor, Rscratch);
duke@0 2628 __ sub(Rdividend, Rscratch, Rresult);
duke@0 2629 %}
duke@0 2630
duke@0 2631 enc_class fabss (sflt_reg dst, sflt_reg src) %{
duke@0 2632 MacroAssembler _masm(&cbuf);
duke@0 2633
duke@0 2634 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
duke@0 2635 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
duke@0 2636
duke@0 2637 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
duke@0 2638 %}
duke@0 2639
duke@0 2640 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
duke@0 2641 MacroAssembler _masm(&cbuf);
duke@0 2642
duke@0 2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
duke@0 2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
duke@0 2645
duke@0 2646 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
duke@0 2647 %}
duke@0 2648
duke@0 2649 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
duke@0 2650 MacroAssembler _masm(&cbuf);
duke@0 2651
duke@0 2652 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
duke@0 2653 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
duke@0 2654
duke@0 2655 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
duke@0 2656 %}
duke@0 2657
duke@0 2658 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
duke@0 2659 MacroAssembler _masm(&cbuf);
duke@0 2660
duke@0 2661 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
duke@0 2662 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
duke@0 2663
duke@0 2664 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
duke@0 2665 %}
duke@0 2666
duke@0 2667 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
duke@0 2668 MacroAssembler _masm(&cbuf);
duke@0 2669
duke@0 2670 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
duke@0 2671 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
duke@0 2672
duke@0 2673 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
duke@0 2674 %}
duke@0 2675
duke@0 2676 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
duke@0 2677 MacroAssembler _masm(&cbuf);
duke@0 2678
duke@0 2679 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
duke@0 2680 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
duke@0 2681
duke@0 2682 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
duke@0 2683 %}
duke@0 2684
duke@0 2685 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
duke@0 2686 MacroAssembler _masm(&cbuf);
duke@0 2687
duke@0 2688 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
duke@0 2689 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
duke@0 2690
duke@0 2691 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
duke@0 2692 %}
duke@0 2693
duke@0 2694 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
duke@0 2695 MacroAssembler _masm(&cbuf);
duke@0 2696
duke@0 2697 Register Roop = reg_to_register_object($oop$$reg);
duke@0 2698 Register Rbox = reg_to_register_object($box$$reg);
duke@0 2699 Register Rscratch = reg_to_register_object($scratch$$reg);
duke@0 2700 Register Rmark = reg_to_register_object($scratch2$$reg);
duke@0 2701
duke@0 2702 assert(Roop != Rscratch, "");
duke@0 2703 assert(Roop != Rmark, "");
duke@0 2704 assert(Rbox != Rscratch, "");
duke@0 2705 assert(Rbox != Rmark, "");
duke@0 2706
kvn@411 2707 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
duke@0 2708 %}
duke@0 2709
duke@0 2710 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
duke@0 2711 MacroAssembler _masm(&cbuf);
duke@0 2712
duke@0 2713 Register Roop = reg_to_register_object($oop$$reg);
duke@0 2714 Register Rbox = reg_to_register_object($box$$reg);
duke@0 2715 Register Rscratch = reg_to_register_object($scratch$$reg);
duke@0 2716 Register Rmark = reg_to_register_object($scratch2$$reg);
duke@0 2717
duke@0 2718 assert(Roop != Rscratch, "");
duke@0 2719 assert(Roop != Rmark, "");
duke@0 2720 assert(Rbox != Rscratch, "");
duke@0 2721 assert(Rbox != Rmark, "");
duke@0 2722
kvn@411 2723 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
duke@0 2724 %}
duke@0 2725
duke@0 2726 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
duke@0 2727 MacroAssembler _masm(&cbuf);
duke@0 2728 Register Rmem = reg_to_register_object($mem$$reg);
duke@0 2729 Register Rold = reg_to_register_object($old$$reg);
duke@0 2730 Register Rnew = reg_to_register_object($new$$reg);
duke@0 2731
duke@0 2732 // casx_under_lock picks 1 of 3 encodings:
duke@0 2733 // For 32-bit pointers you get a 32-bit CAS
duke@0 2734 // For 64-bit pointers you get a 64-bit CASX
kvn@411 2735 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
duke@0 2736 __ cmp( Rold, Rnew );
duke@0 2737 %}
duke@0 2738
duke@0 2739 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
duke@0 2740 Register Rmem = reg_to_register_object($mem$$reg);
duke@0 2741 Register Rold = reg_to_register_object($old$$reg);
duke@0 2742 Register Rnew = reg_to_register_object($new$$reg);
duke@0 2743
duke@0 2744 MacroAssembler _masm(&cbuf);
duke@0 2745 __ mov(Rnew, O7);
duke@0 2746 __ casx(Rmem, Rold, O7);
duke@0 2747 __ cmp( Rold, O7 );
duke@0 2748 %}
duke@0 2749
duke@0 2750 // raw int cas, used for compareAndSwap
duke@0 2751 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
duke@0 2752 Register Rmem = reg_to_register_object($mem$$reg);
duke@0 2753 Register Rold = reg_to_register_object($old$$reg);
duke@0 2754 Register Rnew = reg_to_register_object($new$$reg);
duke@0 2755
duke@0 2756 MacroAssembler _masm(&cbuf);
duke@0 2757 __ mov(Rnew, O7);
duke@0 2758 __ cas(Rmem, Rold, O7);
duke@0 2759 __ cmp( Rold, O7 );
duke@0 2760 %}
duke@0 2761
duke@0 2762 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
duke@0 2763 Register Rres = reg_to_register_object($res$$reg);
duke@0 2764
duke@0 2765 MacroAssembler _masm(&cbuf);
duke@0 2766 __ mov(1, Rres);
duke@0 2767 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
duke@0 2768 %}
duke@0 2769
duke@0 2770 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
duke@0 2771 Register Rres = reg_to_register_object($res$$reg);
duke@0 2772
duke@0 2773 MacroAssembler _masm(&cbuf);
duke@0 2774 __ mov(1, Rres);
duke@0 2775 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
duke@0 2776 %}
duke@0 2777
duke@0 2778 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
duke@0 2779 MacroAssembler _masm(&cbuf);
duke@0 2780 Register Rdst = reg_to_register_object($dst$$reg);
duke@0 2781 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
duke@0 2782 : reg_to_DoubleFloatRegister_object($src1$$reg);
duke@0 2783 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
duke@0 2784 : reg_to_DoubleFloatRegister_object($src2$$reg);
duke@0 2785
duke@0 2786 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
duke@0 2787 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
duke@0 2788 %}
duke@0 2789
duke@0 2790 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
duke@0 2791 MacroAssembler _masm(&cbuf);
duke@0 2792 Register dest = reg_to_register_object($dst$$reg);
duke@0 2793 Register temp = reg_to_register_object($tmp$$reg);
duke@0 2794 __ set64( $src$$constant, dest, temp );
duke@0 2795 %}
duke@0 2796
duke@0 2797 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
duke@0 2798 // Load a constant replicated "count" times with width "width"
duke@0 2799 int bit_width = $width$$constant * 8;
duke@0 2800 jlong elt_val = $src$$constant;
duke@0 2801 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
duke@0 2802 jlong val = elt_val;
duke@0 2803 for (int i = 0; i < $count$$constant - 1; i++) {
duke@0 2804 val <<= bit_width;
duke@0 2805 val |= elt_val;
duke@0 2806 }
duke@0 2807 jdouble dval = *(jdouble*)&val; // coerce to double type
twisti@720 2808 MacroAssembler _masm(&cbuf);
twisti@720 2809 address double_address = __ double_constant(dval);
duke@0 2810 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
twisti@720 2811 AddressLiteral addrlit(double_address, rspec);
twisti@720 2812
twisti@720 2813 __ sethi(addrlit, $tmp$$Register);
never@725 2814 // XXX This is a quick fix for 6833573.
never@725 2815 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
never@725 2816 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
duke@0 2817 %}
duke@0 2818
duke@0 2819 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
duke@0 2820 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
duke@0 2821 MacroAssembler _masm(&cbuf);
duke@0 2822 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
duke@0 2823 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
duke@0 2824 Register base_pointer_arg = reg_to_register_object($base$$reg);
duke@0 2825
duke@0 2826 Label loop;
duke@0 2827 __ mov(nof_bytes_arg, nof_bytes_tmp);
duke@0 2828
duke@0 2829 // Loop and clear, walking backwards through the array.
duke@0 2830 // nof_bytes_tmp (if >0) is always the number of bytes to zero
duke@0 2831 __ bind(loop);
duke@0 2832 __ deccc(nof_bytes_tmp, 8);
duke@0 2833 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
duke@0 2834 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
duke@0 2835 // %%%% this mini-loop must not cross a cache boundary!
duke@0 2836 %}
duke@0 2837
duke@0 2838
duke@0 2839 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
duke@0 2840 Label Ldone, Lloop;
duke@0 2841 MacroAssembler _masm(&cbuf);
duke@0 2842
duke@0 2843 Register str1_reg = reg_to_register_object($str1$$reg);
duke@0 2844 Register str2_reg = reg_to_register_object($str2$$reg);
duke@0 2845 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
duke@0 2846 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
duke@0 2847 Register result_reg = reg_to_register_object($result$$reg);
duke@0 2848
duke@0 2849 // Get the first character position in both strings
duke@0 2850 // [8] char array, [12] offset, [16] count
duke@0 2851 int value_offset = java_lang_String:: value_offset_in_bytes();
duke@0 2852 int offset_offset = java_lang_String::offset_offset_in_bytes();
duke@0 2853 int count_offset = java_lang_String:: count_offset_in_bytes();
duke@0 2854
duke@0 2855 // load str1 (jchar*) base address into tmp1_reg
twisti@720 2856 __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
twisti@720 2857 __ ld(str1_reg, offset_offset, result_reg);
duke@0 2858 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
twisti@720 2859 __ ld(str1_reg, count_offset, str1_reg); // hoisted
duke@0 2860 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
twisti@720 2861 __ load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
duke@0 2862 __ add(result_reg, tmp1_reg, tmp1_reg);
duke@0 2863
duke@0 2864 // load str2 (jchar*) base address into tmp2_reg
twisti@720 2865 // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
twisti@720 2866 __ ld(str2_reg, offset_offset, result_reg);
duke@0 2867 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
twisti@720 2868 __ ld(str2_reg, count_offset, str2_reg); // hoisted
duke@0 2869 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
duke@0 2870 __ subcc(str1_reg, str2_reg, O7); // hoisted
duke@0 2871 __ add(result_reg, tmp2_reg, tmp2_reg);
duke@0 2872
duke@0 2873 // Compute the minimum of the string lengths(str1_reg) and the
duke@0 2874 // difference of the string lengths (stack)
duke@0 2875
duke@0 2876 // discard string base pointers, after loading up the lengths
twisti@720 2877 // __ ld(str1_reg, count_offset, str1_reg); // hoisted
twisti@720 2878 // __ ld(str2_reg, count_offset, str2_reg); // hoisted
duke@0 2879
duke@0 2880 // See if the lengths are different, and calculate min in str1_reg.
duke@0 2881 // Stash diff in O7 in case we need it for a tie-breaker.
duke@0 2882 Label Lskip;
duke@0 2883 // __ subcc(str1_reg, str2_reg, O7); // hoisted
duke@0 2884 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
duke@0 2885 __ br(Assembler::greater, true, Assembler::pt, Lskip);
duke@0 2886 // str2 is shorter, so use its count:
duke@0 2887 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
duke@0 2888 __ bind(Lskip);
duke@0 2889
duke@0 2890 // reallocate str1_reg, str2_reg, result_reg
duke@0 2891 // Note: limit_reg holds the string length pre-scaled by 2
duke@0 2892 Register limit_reg = str1_reg;
duke@0 2893 Register chr2_reg = str2_reg;
duke@0 2894 Register chr1_reg = result_reg;
duke@0 2895 // tmp{12} are the base pointers
duke@0 2896
duke@0 2897 // Is the minimum length zero?
duke@0 2898 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
duke@0 2899 __ br(Assembler::equal, true, Assembler::pn, Ldone);
duke@0 2900 __ delayed()->mov(O7, result_reg); // result is difference in lengths
duke@0 2901
duke@0 2902 // Load first characters
duke@0 2903 __ lduh(tmp1_reg, 0, chr1_reg);
duke@0 2904 __ lduh(tmp2_reg, 0, chr2_reg);
duke@0 2905
duke@0 2906 // Compare first characters
duke@0 2907 __ subcc(chr1_reg, chr2_reg, chr1_reg);
duke@0 2908 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
duke@0 2909 assert(chr1_reg == result_reg, "result must be pre-placed");
duke@0 2910 __ delayed()->nop();
duke@0 2911
duke@0 2912 {
duke@0 2913 // Check after comparing first character to see if strings are equivalent
duke@0 2914 Label LSkip2;
duke@0 2915 // Check if the strings start at same location
duke@0 2916 __ cmp(tmp1_reg, tmp2_reg);
duke@0 2917 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
duke@0 2918 __ delayed()->nop();
duke@0 2919
duke@0 2920 // Check if the length difference is zero (in O7)
duke@0 2921 __ cmp(G0, O7);
duke@0 2922 __ br(Assembler::equal, true, Assembler::pn, Ldone);
duke@0 2923 __ delayed()->mov(G0, result_reg); // result is zero
duke@0 2924
duke@0 2925 // Strings might not be equal
duke@0 2926 __ bind(LSkip2);
duke@0 2927 }
duke@0 2928
duke@0 2929 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
duke@0 2930 __ br(Assembler::equal, true, Assembler::pn, Ldone);
duke@0 2931 __ delayed()->mov(O7, result_reg); // result is difference in lengths
duke@0 2932
duke@0 2933 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
duke@0 2934 __ add(tmp1_reg, limit_reg, tmp1_reg);
duke@0 2935 __ add(tmp2_reg, limit_reg, tmp2_reg);
duke@0 2936 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
duke@0 2937
duke@0 2938 // Compare the rest of the characters
duke@0 2939 __ lduh(tmp1_reg, limit_reg, chr1_reg);
duke@0 2940 __ bind(Lloop);
duke@0 2941 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
duke@0 2942 __ lduh(tmp2_reg, limit_reg, chr2_reg);
duke@0 2943 __ subcc(chr1_reg, chr2_reg, chr1_reg);
duke@0 2944 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
duke@0 2945 assert(chr1_reg == result_reg, "result must be pre-placed");
duke@0 2946 __ delayed()->inccc(limit_reg, sizeof(jchar));
duke@0 2947 // annul LDUH if branch is not taken to prevent access past end of string
duke@0 2948 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
duke@0 2949 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
duke@0 2950
duke@0 2951 // If strings are equal up to min length, return the length difference.
duke@0 2952 __ mov(O7, result_reg);
duke@0 2953
duke@0 2954 // Otherwise, return the difference between the first mismatched chars.
duke@0 2955 __ bind(Ldone);
duke@0 2956 %}
duke@0 2957
cfang@674 2958 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
cfang@674 2959 Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
cfang@674 2960 MacroAssembler _masm(&cbuf);
cfang@674 2961
cfang@674 2962 Register str1_reg = reg_to_register_object($str1$$reg);
cfang@674 2963 Register str2_reg = reg_to_register_object($str2$$reg);
cfang@674 2964 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
cfang@674 2965 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
cfang@674 2966 Register result_reg = reg_to_register_object($result$$reg);
cfang@674 2967
cfang@674 2968 // Get the first character position in both strings
cfang@674 2969 // [8] char array, [12] offset, [16] count
cfang@674 2970 int value_offset = java_lang_String:: value_offset_in_bytes();
cfang@674 2971 int offset_offset = java_lang_String::offset_offset_in_bytes();
cfang@674 2972 int count_offset = java_lang_String:: count_offset_in_bytes();
cfang@674 2973
cfang@674 2974 // load str1 (jchar*) base address into tmp1_reg
twisti@720 2975 __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
twisti@720 2976 __ ld(Address(str1_reg, offset_offset), result_reg);
cfang@674 2977 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
twisti@720 2978 __ ld(Address(str1_reg, count_offset), str1_reg); // hoisted
cfang@674 2979 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
twisti@720 2980 __ load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
cfang@674 2981 __ add(result_reg, tmp1_reg, tmp1_reg);
cfang@674 2982
cfang@674 2983 // load str2 (jchar*) base address into tmp2_reg
twisti@720 2984 // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
twisti@720 2985 __ ld(Address(str2_reg, offset_offset), result_reg);
cfang@674 2986 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
twisti@720 2987 __ ld(Address(str2_reg, count_offset), str2_reg); // hoisted
cfang@674 2988 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
cfang@674 2989 __ cmp(str1_reg, str2_reg); // hoisted
cfang@674 2990 __ add(result_reg, tmp2_reg, tmp2_reg);
cfang@674 2991
cfang@674 2992 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
cfang@674 2993 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
cfang@674 2994 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 2995
cfang@674 2996 __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
cfang@674 2997 __ delayed()->add(G0, 1, result_reg); //equals
cfang@674 2998
cfang@674 2999 __ cmp(tmp1_reg, tmp2_reg); //same string ?
cfang@674 3000 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
cfang@674 3001 __ delayed()->add(G0, 1, result_reg);
cfang@674 3002
cfang@674 3003 //rename registers
cfang@674 3004 Register limit_reg = str1_reg;
cfang@674 3005 Register chr2_reg = str2_reg;
cfang@674 3006 Register chr1_reg = result_reg;
cfang@674 3007 // tmp{12} are the base pointers
cfang@674 3008
cfang@674 3009 //check for alignment and position the pointers to the ends
cfang@674 3010 __ or3(tmp1_reg, tmp2_reg, chr1_reg);
cfang@674 3011 __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
cfang@674 3012 __ br(Assembler::notZero, false, Assembler::pn, Lchar);
cfang@674 3013 __ delayed()->nop();
cfang@674 3014
cfang@674 3015 __ bind(Lword);
cfang@674 3016 __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
cfang@674 3017 __ andn(limit_reg, 0x3, limit_reg);
cfang@674 3018 __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
cfang@674 3019 __ delayed()->nop();
cfang@674 3020
cfang@674 3021 __ add(tmp1_reg, limit_reg, tmp1_reg);
cfang@674 3022 __ add(tmp2_reg, limit_reg, tmp2_reg);
cfang@674 3023 __ neg(limit_reg);
cfang@674 3024
cfang@674 3025 __ lduw(tmp1_reg, limit_reg, chr1_reg);
cfang@674 3026 __ bind(Lword_loop);
cfang@674 3027 __ lduw(tmp2_reg, limit_reg, chr2_reg);
cfang@674 3028 __ cmp(chr1_reg, chr2_reg);
cfang@674 3029 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
cfang@674 3030 __ delayed()->mov(G0, result_reg);
cfang@674 3031 __ inccc(limit_reg, 2*sizeof(jchar));
cfang@674 3032 // annul LDUW if branch i s not taken to prevent access past end of string
cfang@674 3033 __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
cfang@674 3034 __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted
cfang@674 3035
cfang@674 3036 __ bind(Lpost_word);
cfang@674 3037 __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
cfang@674 3038 __ delayed()->add(G0, 1, result_reg);
cfang@674 3039
cfang@674 3040 __ lduh(tmp1_reg, 0, chr1_reg);
cfang@674 3041 __ lduh(tmp2_reg, 0, chr2_reg);
cfang@674 3042 __ cmp (chr1_reg, chr2_reg);
cfang@674 3043 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
cfang@674 3044 __ delayed()->mov(G0, result_reg);
cfang@674 3045 __ ba(false,Ldone);
cfang@674 3046 __ delayed()->add(G0, 1, result_reg);
cfang@674 3047
cfang@674 3048 __ bind(Lchar);
cfang@674 3049 __ add(tmp1_reg, limit_reg, tmp1_reg);
cfang@674 3050 __ add(tmp2_reg, limit_reg, tmp2_reg);
cfang@674 3051 __ neg(limit_reg); //negate count
cfang@674 3052
cfang@674 3053 __ lduh(tmp1_reg, limit_reg, chr1_reg);
cfang@674 3054 __ bind(Lchar_loop);
cfang@674 3055 __ lduh(tmp2_reg, limit_reg, chr2_reg);
cfang@674 3056 __ cmp(chr1_reg, chr2_reg);
cfang@674 3057 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
cfang@674 3058 __ delayed()->mov(G0, result_reg); //not equal
cfang@674 3059 __ inccc(limit_reg, sizeof(jchar));
cfang@674 3060 // annul LDUH if branch is not taken to prevent access past end of string
cfang@674 3061 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
cfang@674 3062 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
cfang@674 3063
cfang@674 3064 __ add(G0, 1, result_reg); //equal
cfang@674 3065
cfang@674 3066 __ bind(Ldone);
cfang@674 3067 %}
cfang@674 3068
cfang@674 3069 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
cfang@674 3070 Label Lvector, Ldone, Lloop;
cfang@674 3071 MacroAssembler _masm(&cbuf);
cfang@674 3072
cfang@674 3073 Register ary1_reg = reg_to_register_object($ary1$$reg);
cfang@674 3074 Register ary2_reg = reg_to_register_object($ary2$$reg);
cfang@674 3075 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
cfang@674 3076 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
cfang@674 3077 Register result_reg = reg_to_register_object($result$$reg);
cfang@674 3078
cfang@674 3079 int length_offset = arrayOopDesc::length_offset_in_bytes();
cfang@674 3080 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
cfang@674 3081
cfang@674 3082 // return true if the same array
cfang@674 3083 __ cmp(ary1_reg, ary2_reg);
cfang@674 3084 __ br(Assembler::equal, true, Assembler::pn, Ldone);
cfang@674 3085 __ delayed()->add(G0, 1, result_reg); // equal
cfang@674 3086
cfang@674 3087 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
cfang@674 3088 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 3089
cfang@674 3090 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
cfang@674 3091 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 3092
cfang@674 3093 //load the lengths of arrays
twisti@720 3094 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
twisti@720 3095 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
cfang@674 3096
cfang@674 3097 // return false if the two arrays are not equal length
cfang@674 3098 __ cmp(tmp1_reg, tmp2_reg);
cfang@674 3099 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
cfang@674 3100 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 3101
cfang@674 3102 __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
cfang@674 3103 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
cfang@674 3104
cfang@674 3105 // load array addresses
cfang@674 3106 __ add(ary1_reg, base_offset, ary1_reg);
cfang@674 3107 __ add(ary2_reg, base_offset, ary2_reg);
cfang@674 3108
cfang@674 3109 // renaming registers
cfang@674 3110 Register chr1_reg = tmp2_reg; // for characters in ary1
cfang@674 3111 Register chr2_reg = result_reg; // for characters in ary2
cfang@674 3112 Register limit_reg = tmp1_reg; // length
cfang@674 3113
cfang@674 3114 // set byte count
cfang@674 3115 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
cfang@674 3116 __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
cfang@674 3117 __ br(Assembler::zero, false, Assembler::pt, Lvector);
cfang@674 3118 __ delayed()->nop();
cfang@674 3119
cfang@674 3120 //compare the trailing char
cfang@674 3121 __ sub(limit_reg, sizeof(jchar), limit_reg);
cfang@674 3122 __ lduh(ary1_reg, limit_reg, chr1_reg);
cfang@674 3123 __ lduh(ary2_reg, limit_reg, chr2_reg);
cfang@674 3124 __ cmp(chr1_reg, chr2_reg);
cfang@674 3125 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
cfang@674 3126 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 3127
cfang@674 3128 // only one char ?
cfang@674 3129 __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
cfang@674 3130 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
cfang@674 3131
cfang@674 3132 __ bind(Lvector);
cfang@674 3133 // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
cfang@674 3134 __ add(ary1_reg, limit_reg, ary1_reg);
cfang@674 3135 __ add(ary2_reg, limit_reg, ary2_reg);
cfang@674 3136 __ neg(limit_reg, limit_reg);
cfang@674 3137
cfang@674 3138 __ lduw(ary1_reg, limit_reg, chr1_reg);
cfang@674 3139 __ bind(Lloop);
cfang@674 3140 __ lduw(ary2_reg, limit_reg, chr2_reg);
cfang@674 3141 __ cmp(chr1_reg, chr2_reg);
cfang@674 3142 __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
cfang@674 3143 __ delayed()->mov(G0, result_reg); // not equal
cfang@674 3144 __ inccc(limit_reg, 2*sizeof(jchar));
cfang@674 3145 // annul LDUW if branch is not taken to prevent access past end of string
cfang@674 3146 __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
cfang@674 3147 __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted
cfang@674 3148
cfang@674 3149 __ add(G0, 1, result_reg); // equals
cfang@674 3150
cfang@674 3151 __ bind(Ldone);
cfang@674 3152 %}
cfang@674 3153
duke@0 3154 enc_class enc_rethrow() %{
duke@0 3155 cbuf.set_inst_mark();
duke@0 3156 Register temp_reg = G3;
twisti@720 3157 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
duke@0 3158 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
duke@0 3159 MacroAssembler _masm(&cbuf);
duke@0 3160 #ifdef ASSERT
duke@0 3161 __ save_frame(0);
twisti@720 3162 AddressLiteral last_rethrow_addrlit(&last_rethrow);
twisti@720 3163 __ sethi(last_rethrow_addrlit, L1);
twisti@720 3164 Address addr(L1, last_rethrow_addrlit.low10());
duke@0 3165 __ get_pc(L2);
duke@0 3166 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
twisti@720 3167 __ st_ptr(L2, addr);
duke@0 3168 __ restore();
duke@0 3169 #endif
twisti@720 3170 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
duke@0 3171 __ delayed()->nop();
duke@0 3172 %}
duke@0 3173
duke@0 3174 enc_class emit_mem_nop() %{
duke@0 3175 // Generates the instruction LDUXA [o6,g0],#0x82,g0
duke@0 3176 unsigned int *code = (unsigned int*)cbuf.code_end();
duke@0 3177 *code = (unsigned int)0xc0839040;
duke@0 3178 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 3179 %}
duke@0 3180
duke@0 3181 enc_class emit_fadd_nop() %{
duke@0 3182 // Generates the instruction FMOVS f31,f31
duke@0 3183 unsigned int *code = (unsigned int*)cbuf.code_end();
duke@0 3184 *code = (unsigned int)0xbfa0003f;
duke@0 3185 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 3186 %}
duke@0 3187
duke@0 3188 enc_class emit_br_nop() %{
duke@0 3189 // Generates the instruction BPN,PN .
duke@0 3190 unsigned int *code = (unsigned int*)cbuf.code_end();
duke@0 3191 *code = (unsigned int)0x00400000;
duke@0 3192 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
duke@0 3193 %}
duke@0 3194
duke@0 3195 enc_class enc_membar_acquire %{
duke@0 3196 MacroAssembler _masm(&cbuf);
duke@0 3197 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
duke@0 3198 %}
duke@0 3199
duke@0 3200 enc_class enc_membar_release %{
duke@0 3201 MacroAssembler _masm(&cbuf);
duke@0 3202 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
duke@0 3203 %}
duke@0 3204
duke@0 3205 enc_class enc_membar_volatile %{
duke@0 3206 MacroAssembler _masm(&cbuf);
duke@0 3207 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
duke@0 3208 %}
coleenp@108 3209
duke@0 3210 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
duke@0 3211 MacroAssembler _masm(&cbuf);
duke@0 3212 Register src_reg = reg_to_register_object($src$$reg);
duke@0 3213 Register dst_reg = reg_to_register_object($dst$$reg);
duke@0 3214 __ sllx(src_reg, 56, dst_reg);
duke@0 3215 __ srlx(dst_reg, 8, O7);
duke@0 3216 __ or3 (dst_reg, O7, dst_reg);
duke@0 3217 __ srlx(dst_reg, 16, O7);
duke@0 3218 __ or3 (dst_reg, O7, dst_reg);
duke@0 3219 __ srlx(dst_reg, 32, O7);
duke@0 3220 __ or3 (dst_reg, O7, dst_reg);
duke@0 3221 %}
duke@0 3222
duke@0 3223 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
duke@0 3224 MacroAssembler _masm(&cbuf);
duke@0 3225 Register src_reg = reg_to_register_object($src$$reg);
duke@0 3226 Register dst_reg = reg_to_register_object($dst$$reg);
duke@0 3227 __ sll(src_reg, 24, dst_reg);
duke@0 3228 __ srl(dst_reg, 8, O7);
duke@0 3229 __ or3(dst_reg, O7, dst_reg);
duke@0 3230 __ srl(dst_reg, 16, O7);
duke@0 3231 __ or3(dst_reg, O7, dst_reg);
duke@0 3232 %}
duke@0 3233
duke@0 3234 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
duke@0 3235 MacroAssembler _masm(&cbuf);
duke@0 3236 Register src_reg = reg_to_register_object($src$$reg);
duke@0 3237 Register dst_reg = reg_to_register_object($dst$$reg);
duke@0 3238 __ sllx(src_reg, 48, dst_reg);
duke@0 3239 __ srlx(dst_reg, 16, O7);
duke@0 3240 __ or3 (dst_reg, O7, dst_reg);
duke@0 3241 __ srlx(dst_reg, 32, O7);
duke@0 3242 __ or3 (dst_reg, O7, dst_reg);
duke@0 3243 %}
duke@0 3244
duke@0 3245 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
duke@0 3246 MacroAssembler _masm(&cbuf);
duke@0 3247 Register src_reg = reg_to_register_object($src$$reg);
duke@0 3248 Register dst_reg = reg_to_register_object($dst$$reg);
duke@0 3249 __ sllx(src_reg, 32, dst_reg);
duke@0 3250 __ srlx(dst_reg, 32, O7);
duke@0 3251 __ or3 (dst_reg, O7, dst_reg);
duke@0 3252 %}
duke@0 3253
duke@0 3254 %}
duke@0 3255
duke@0 3256 //----------FRAME--------------------------------------------------------------
duke@0 3257 // Definition of frame structure and management information.
duke@0 3258 //
duke@0 3259 // S T A C K L A Y O U T Allocators stack-slot number
duke@0 3260 // | (to get allocators register number
duke@0 3261 // G Owned by | | v add VMRegImpl::stack0)
duke@0 3262 // r CALLER | |
duke@0 3263 // o | +--------+ pad to even-align allocators stack-slot
duke@0 3264 // w V | pad0 | numbers; owned by CALLER
duke@0 3265 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
duke@0 3266 // h ^ | in | 5
duke@0 3267 // | | args | 4 Holes in incoming args owned by SELF
duke@0 3268 // | | | | 3
duke@0 3269 // | | +--------+
duke@0 3270 // V | | old out| Empty on Intel, window on Sparc
duke@0 3271 // | old |preserve| Must be even aligned.
duke@0 3272 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
duke@0 3273 // | | in | 3 area for Intel ret address
duke@0 3274 // Owned by |preserve| Empty on Sparc.
duke@0 3275 // SELF +--------+
duke@0 3276 // | | pad2 | 2 pad to align old SP
duke@0 3277 // | +--------+ 1
duke@0 3278 // | | locks | 0
duke@0 3279 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
duke@0 3280 // | | pad1 | 11 pad to align new SP
duke@0 3281 // | +--------+
duke@0 3282 // | | | 10
duke@0 3283 // | | spills | 9 spills
duke@0 3284 // V | | 8 (pad0 slot for callee)
duke@0 3285 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
duke@0 3286 // ^ | out | 7
duke@0 3287 // | | args | 6 Holes in outgoing args owned by CALLEE
duke@0 3288 // Owned by +--------+
duke@0 3289 // CALLEE | new out| 6 Empty on Intel, window on Sparc
duke@0 3290 // | new |preserve| Must be even-aligned.
duke@0 3291 // | SP-+--------+----> Matcher::_new_SP, even aligned
duke@0 3292 // | | |
duke@0 3293 //
duke@0 3294 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
duke@0 3295 // known from SELF's arguments and the Java calling convention.
duke@0 3296 // Region 6-7 is determined per call site.
duke@0 3297 // Note 2: If the calling convention leaves holes in the incoming argument
duke@0 3298 // area, those holes are owned by SELF. Holes in the outgoing area
duke@0 3299 // are owned by the CALLEE. Holes should not be nessecary in the
duke@0 3300 // incoming area, as the Java calling convention is completely under
duke@0 3301 // the control of the AD file. Doubles can be sorted and packed to
duke@0 3302 // avoid holes. Holes in the outgoing arguments may be nessecary for
duke@0 3303 // varargs C calling conventions.
duke@0 3304 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
duke@0 3305 // even aligned with pad0 as needed.
duke@0 3306 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
duke@0 3307 // region 6-11 is even aligned; it may be padded out more so that
duke@0 3308 // the region from SP to FP meets the minimum stack alignment.
duke@0 3309
duke@0 3310 frame %{
duke@0 3311 // What direction does stack grow in (assumed to be same for native & Java)
duke@0 3312 stack_direction(TOWARDS_LOW);
duke@0 3313
duke@0 3314 // These two registers define part of the calling convention
duke@0 3315 // between compiled code and the interpreter.
duke@0 3316 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
duke@0 3317 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
duke@0 3318
duke@0 3319 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
duke@0 3320 cisc_spilling_operand_name(indOffset);
duke@0 3321
duke@0 3322 // Number of stack slots consumed by a Monitor enter
duke@0 3323 #ifdef _LP64
duke@0 3324 sync_stack_slots(2);
duke@0 3325 #else
duke@0 3326 sync_stack_slots(1);
duke@0 3327 #endif
duke@0 3328
duke@0 3329 // Compiled code's Frame Pointer
duke@0 3330 frame_pointer(R_SP);
duke@0 3331
duke@0 3332 // Stack alignment requirement
duke@0 3333 stack_alignment(StackAlignmentInBytes);
duke@0 3334 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
duke@0 3335 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
duke@0 3336
duke@0 3337 // Number of stack slots between incoming argument block and the start of
duke@0 3338 // a new frame. The PROLOG must add this many slots to the stack. The
duke@0 3339 // EPILOG must remove this many slots.
duke@0 3340 in_preserve_stack_slots(0);
duke@0 3341
duke@0 3342 // Number of outgoing stack slots killed above the out_preserve_stack_slots
duke@0 3343 // for calls to C. Supports the var-args backing area for register parms.
duke@0 3344 // ADLC doesn't support parsing expressions, so I folded the math by hand.
duke@0 3345 #ifdef _LP64
duke@0 3346 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
duke@0 3347 varargs_C_out_slots_killed(12);
duke@0 3348 #else
duke@0 3349 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
duke@0 3350 varargs_C_out_slots_killed( 7);
duke@0 3351 #endif
duke@0 3352
duke@0 3353 // The after-PROLOG location of the return address. Location of
duke@0 3354 // return address specifies a type (REG or STACK) and a number
duke@0 3355 // representing the register number (i.e. - use a register name) or
duke@0 3356 // stack slot.
duke@0 3357 return_addr(REG R_I7); // Ret Addr is in register I7
duke@0 3358
duke@0 3359 // Body of function which returns an OptoRegs array locating
duke@0 3360 // arguments either in registers or in stack slots for calling
duke@0 3361 // java
duke@0 3362 calling_convention %{
duke@0 3363 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
duke@0 3364
duke@0 3365 %}
duke@0 3366
duke@0 3367 // Body of function which returns an OptoRegs array locating
duke@0 3368 // arguments either in registers or in stack slots for callin
duke@0 3369 // C.
duke@0 3370 c_calling_convention %{
duke@0 3371 // This is obviously always outgoing
duke@0 3372 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
duke@0 3373 %}
duke@0 3374
duke@0 3375 // Location of native (C/C++) and interpreter return values. This is specified to
duke@0 3376 // be the same as Java. In the 32-bit VM, long values are actually returned from
duke@0 3377 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
duke@0 3378 // to and from the register pairs is done by the appropriate call and epilog
duke@0 3379 // opcodes. This simplifies the register allocator.
duke@0 3380 c_return_value %{
duke@0 3381 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
duke@0 3382 #ifdef _LP64
coleenp@108 3383 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
coleenp@108 3384 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
coleenp@108 3385 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
coleenp@108 3386 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
duke@0 3387 #else // !_LP64
coleenp@108 3388 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
coleenp@108 3389 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
coleenp@108 3390 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
coleenp@108 3391 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
duke@0 3392 #endif
duke@0 3393 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
duke@0 3394 (is_outgoing?lo_out:lo_in)[ideal_reg] );
duke@0 3395 %}
duke@0 3396
duke@0 3397 // Location of compiled Java return values. Same as C
duke@0 3398 return_value %{
duke@0 3399 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
duke@0 3400 #ifdef _LP64
coleenp@108 3401 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
coleenp@108 3402 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
coleenp@108 3403 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
coleenp@108 3404 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
duke@0 3405 #else // !_LP64
coleenp@108 3406 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
coleenp@108 3407 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
coleenp@108 3408 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
coleenp@108 3409 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
duke@0 3410 #endif
duke@0 3411 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
duke@0 3412 (is_outgoing?lo_out:lo_in)[ideal_reg] );
duke@0 3413 %}
duke@0 3414
duke@0 3415 %}
duke@0 3416
duke@0 3417
duke@0 3418 //----------ATTRIBUTES---------------------------------------------------------
duke@0 3419 //----------Operand Attributes-------------------------------------------------
duke@0 3420 op_attrib op_cost(1); // Required cost attribute
duke@0 3421
duke@0 3422 //----------Instruction Attributes---------------------------------------------
duke@0 3423 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
duke@0 3424 ins_attrib ins_size(32); // Required size attribute (in bits)
duke@0 3425 ins_attrib ins_pc_relative(0); // Required PC Relative flag
duke@0 3426 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
duke@0 3427 // non-matching short branch variant of some
duke@0 3428 // long branch?
duke@0 3429
duke@0 3430 //----------OPERANDS-----------------------------------------------------------
duke@0 3431 // Operand definitions must precede instruction definitions for correct parsing
duke@0 3432 // in the ADLC because operands constitute user defined types which are used in
duke@0 3433 // instruction definitions.
duke@0 3434
duke@0 3435 //----------Simple Operands----------------------------------------------------
duke@0 3436 // Immediate Operands
duke@0 3437 // Integer Immediate: 32-bit
duke@0 3438 operand immI() %{
duke@0 3439 match(ConI);
duke@0 3440
duke@0 3441 op_cost(0);
duke@0 3442 // formats are generated automatically for constants and base registers
duke@0 3443 format %{ %}
duke@0 3444 interface(CONST_INTER);
duke@0 3445 %}
duke@0 3446
duke@0 3447 // Integer Immediate: 13-bit
duke@0 3448 operand immI13() %{
duke@0 3449 predicate(Assembler::is_simm13(n->get_int()));
duke@0 3450 match(ConI);
duke@0 3451 op_cost(0);
duke@0 3452
duke@0 3453 format %{ %}
duke@0 3454 interface(CONST_INTER);
duke@0 3455 %}
duke@0 3456
duke@0 3457 // Unsigned (positive) Integer Immediate: 13-bit
duke@0 3458 operand immU13() %{
duke@0 3459 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
duke@0 3460 match(ConI);
duke@0 3461 op_cost(0);
duke@0 3462
duke@0 3463 format %{ %}
duke@0 3464 interface(CONST_INTER);
duke@0 3465 %}
duke@0 3466
duke@0 3467 // Integer Immediate: 6-bit
duke@0 3468 operand immU6() %{
duke@0 3469 predicate(n->get_int() >= 0 && n->get_int() <= 63);
duke@0 3470 match(ConI);
duke@0 3471 op_cost(0);
duke@0 3472 format %{ %}
duke@0 3473 interface(CONST_INTER);
duke@0 3474 %}
duke@0 3475
duke@0 3476 // Integer Immediate: 11-bit
duke@0 3477 operand immI11() %{
duke@0 3478 predicate(Assembler::is_simm(n->get_int(),11));
duke@0 3479 match(ConI);
duke@0 3480 op_cost(0);
duke@0 3481 format %{ %}
duke@0 3482 interface(CONST_INTER);
duke@0 3483 %}
duke@0 3484
duke@0 3485 // Integer Immediate: 0-bit
duke@0 3486 operand immI0() %{
duke@0 3487 predicate(n->get_int() == 0);
duke@0 3488 match(ConI);
duke@0 3489 op_cost(0);
duke@0 3490
duke@0 3491 format %{ %}
duke@0 3492 interface(CONST_INTER);
duke@0 3493 %}
duke@0 3494
duke@0 3495 // Integer Immediate: the value 10
duke@0 3496 operand immI10() %{
duke@0 3497 predicate(n->get_int() == 10);
duke@0 3498 match(ConI);
duke@0 3499 op_cost(0);
duke@0 3500
duke@0 3501 format %{ %}
duke@0 3502 interface(CONST_INTER);
duke@0 3503 %}
duke@0 3504
duke@0 3505 // Integer Immediate: the values 0-31
duke@0 3506 operand immU5() %{
duke@0 3507 predicate(n->get_int() >= 0 && n->get_int() <= 31);
duke@0 3508 match(ConI);
duke@0 3509 op_cost(0);
duke@0 3510
duke@0 3511 format %{ %}
duke@0 3512 interface(CONST_INTER);
duke@0 3513 %}
duke@0 3514
duke@0 3515 // Integer Immediate: the values 1-31
duke@0 3516 operand immI_1_31() %{
duke@0 3517 predicate(n->get_int() >= 1 && n->get_int() <= 31);
duke@0 3518 match(ConI);
duke@0 3519 op_cost(0);
duke@0 3520
duke@0 3521 format %{ %}
duke@0 3522 interface(CONST_INTER);
duke@0 3523 %}
duke@0 3524
duke@0 3525 // Integer Immediate: the values 32-63
duke@0 3526 operand immI_32_63() %{
duke@0 3527 predicate(n->get_int() >= 32 && n->get_int() <= 63);
duke@0 3528 match(ConI);
duke@0 3529 op_cost(0);
duke@0 3530
duke@0 3531 format %{ %}
duke@0 3532 interface(CONST_INTER);
duke@0 3533 %}
duke@0 3534
duke@0 3535 // Integer Immediate: the value 255
duke@0 3536 operand immI_255() %{
duke@0 3537 predicate( n->get_int() == 255 );
duke@0 3538 match(ConI);
duke@0 3539 op_cost(0);
duke@0 3540
duke@0 3541 format %{ %}
duke@0 3542 interface(CONST_INTER);
duke@0 3543 %}
duke@0 3544
duke@0 3545 // Long Immediate: the value FF
duke@0 3546 operand immL_FF() %{
duke@0 3547 predicate( n->get_long() == 0xFFL );
duke@0 3548 match(ConL);
duke@0 3549 op_cost(0);
duke@0 3550
duke@0 3551 format %{ %}
duke@0 3552 interface(CONST_INTER);
duke@0 3553 %}
duke@0 3554
duke@0 3555 // Long Immediate: the value FFFF
duke@0 3556 operand immL_FFFF() %{
duke@0 3557 predicate( n->get_long() == 0xFFFFL );
duke@0 3558 match(ConL);
duke@0 3559 op_cost(0);
duke@0 3560
duke@0 3561 format %{ %}
duke@0 3562 interface(CONST_INTER);
duke@0 3563 %}
duke@0 3564
duke@0 3565 // Pointer Immediate: 32 or 64-bit
duke@0 3566 operand immP() %{
duke@0 3567 match(ConP);
duke@0 3568
duke@0 3569 op_cost(5);
duke@0 3570 // formats are generated automatically for constants and base registers
duke@0 3571 format %{ %}
duke@0 3572 interface(CONST_INTER);
duke@0 3573 %}
duke@0 3574
duke@0 3575 operand immP13() %{
duke@0 3576 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
duke@0 3577 match(ConP);
duke@0 3578 op_cost(0);
duke@0 3579
duke@0 3580 format %{ %}
duke@0 3581 interface(CONST_INTER);
duke@0 3582 %}
duke@0 3583
duke@0 3584 operand immP0() %{
duke@0 3585 predicate(n->get_ptr() == 0);
duke@0 3586 match(ConP);
duke@0 3587 op_cost(0);
duke@0 3588
duke@0 3589 format %{ %}
duke@0 3590 interface(CONST_INTER);
duke@0 3591 %}
duke@0 3592
duke@0 3593 operand immP_poll() %{
duke@0 3594 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
duke@0 3595 match(ConP);
duke@0 3596
duke@0 3597 // formats are generated automatically for constants and base registers
duke@0 3598 format %{ %}
duke@0 3599 interface(CONST_INTER);
duke@0 3600 %}
duke@0 3601
coleenp@108 3602 // Pointer Immediate
coleenp@108 3603 operand immN()
coleenp@108 3604 %{
coleenp@108 3605 match(ConN);
coleenp@108 3606
coleenp@108 3607 op_cost(10);
coleenp@108 3608 format %{ %}
coleenp@108 3609 interface(CONST_INTER);
coleenp@108 3610 %}
coleenp@108 3611
coleenp@108 3612 // NULL Pointer Immediate
coleenp@108 3613 operand immN0()
coleenp@108 3614 %{
coleenp@108 3615 predicate(n->get_narrowcon() == 0);
coleenp@108 3616 match(ConN);
coleenp@108 3617
coleenp@108 3618 op_cost(0);
coleenp@108 3619 format %{ %}
coleenp@108 3620 interface(CONST_INTER);
coleenp@108 3621 %}
coleenp@108 3622
duke@0 3623 operand immL() %{
duke@0 3624 match(ConL);
duke@0 3625 op_cost(40);
duke@0 3626 // formats are generated automatically for constants and base registers
duke@0 3627 format %{ %}
duke@0 3628 interface(CONST_INTER);
duke@0 3629 %}
duke@0 3630
duke@0 3631 operand immL0() %{
duke@0 3632 predicate(n->get_long() == 0L);
duke@0 3633 match(ConL);
duke@0 3634 op_cost(0);
duke@0 3635 // formats are generated automatically for constants and base registers
duke@0 3636 format %{ %}
duke@0 3637 interface(CONST_INTER);
duke@0 3638 %}
duke@0 3639
duke@0 3640 // Long Immediate: 13-bit
duke@0 3641 operand immL13() %{
duke@0 3642 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
duke@0 3643 match(ConL);
duke@0 3644 op_cost(0);
duke@0 3645
duke@0 3646 format %{ %}
duke@0 3647 interface(CONST_INTER);
duke@0 3648 %}
duke@0 3649
duke@0 3650 // Long Immediate: low 32-bit mask
duke@0 3651 operand immL_32bits() %{
duke@0 3652 predicate(n->get_long() == 0xFFFFFFFFL);
duke@0 3653 match(ConL);
duke@0 3654 op_cost(0);
duke@0 3655
duke@0 3656 format %{ %}
duke@0 3657 interface(CONST_INTER);
duke@0 3658 %}
duke@0 3659
duke@0 3660 // Double Immediate
duke@0 3661 operand immD() %{
duke@0 3662 match(ConD);
duke@0 3663
duke@0 3664 op_cost(40);
duke@0 3665 format %{ %}
duke@0 3666