annotate src/cpu/x86/vm/assembler_x86.cpp @ 747:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents e5b0439ef4ae
children df6caf649ff7
rev   line source
duke@0 1 /*
twisti@603 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 #include "incls/_precompiled.incl"
never@297 26 #include "incls/_assembler_x86.cpp.incl"
duke@0 27
duke@0 28 // Implementation of AddressLiteral
duke@0 29
duke@0 30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
duke@0 31 _is_lval = false;
duke@0 32 _target = target;
duke@0 33 switch (rtype) {
duke@0 34 case relocInfo::oop_type:
duke@0 35 // Oops are a special case. Normally they would be their own section
duke@0 36 // but in cases like icBuffer they are literals in the code stream that
duke@0 37 // we don't have a section for. We use none so that we get a literal address
duke@0 38 // which is always patchable.
duke@0 39 break;
duke@0 40 case relocInfo::external_word_type:
duke@0 41 _rspec = external_word_Relocation::spec(target);
duke@0 42 break;
duke@0 43 case relocInfo::internal_word_type:
duke@0 44 _rspec = internal_word_Relocation::spec(target);
duke@0 45 break;
duke@0 46 case relocInfo::opt_virtual_call_type:
duke@0 47 _rspec = opt_virtual_call_Relocation::spec();
duke@0 48 break;
duke@0 49 case relocInfo::static_call_type:
duke@0 50 _rspec = static_call_Relocation::spec();
duke@0 51 break;
duke@0 52 case relocInfo::runtime_call_type:
duke@0 53 _rspec = runtime_call_Relocation::spec();
duke@0 54 break;
duke@0 55 case relocInfo::poll_type:
duke@0 56 case relocInfo::poll_return_type:
duke@0 57 _rspec = Relocation::spec_simple(rtype);
duke@0 58 break;
duke@0 59 case relocInfo::none:
duke@0 60 break;
duke@0 61 default:
duke@0 62 ShouldNotReachHere();
duke@0 63 break;
duke@0 64 }
duke@0 65 }
duke@0 66
duke@0 67 // Implementation of Address
duke@0 68
never@297 69 #ifdef _LP64
never@297 70
duke@0 71 Address Address::make_array(ArrayAddress adr) {
duke@0 72 // Not implementable on 64bit machines
duke@0 73 // Should have been handled higher up the call chain.
duke@0 74 ShouldNotReachHere();
never@297 75 return Address();
never@297 76 }
never@297 77
never@297 78 // exceedingly dangerous constructor
never@297 79 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
never@297 80 _base = noreg;
never@297 81 _index = noreg;
never@297 82 _scale = no_scale;
never@297 83 _disp = disp;
never@297 84 switch (rtype) {
never@297 85 case relocInfo::external_word_type:
never@297 86 _rspec = external_word_Relocation::spec(loc);
never@297 87 break;
never@297 88 case relocInfo::internal_word_type:
never@297 89 _rspec = internal_word_Relocation::spec(loc);
never@297 90 break;
never@297 91 case relocInfo::runtime_call_type:
never@297 92 // HMM
never@297 93 _rspec = runtime_call_Relocation::spec();
never@297 94 break;
never@297 95 case relocInfo::poll_type:
never@297 96 case relocInfo::poll_return_type:
never@297 97 _rspec = Relocation::spec_simple(rtype);
never@297 98 break;
never@297 99 case relocInfo::none:
never@297 100 break;
never@297 101 default:
never@297 102 ShouldNotReachHere();
never@297 103 }
never@297 104 }
never@297 105 #else // LP64
never@297 106
never@297 107 Address Address::make_array(ArrayAddress adr) {
duke@0 108 AddressLiteral base = adr.base();
duke@0 109 Address index = adr.index();
duke@0 110 assert(index._disp == 0, "must not have disp"); // maybe it can?
duke@0 111 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
duke@0 112 array._rspec = base._rspec;
duke@0 113 return array;
never@297 114 }
duke@0 115
duke@0 116 // exceedingly dangerous constructor
duke@0 117 Address::Address(address loc, RelocationHolder spec) {
duke@0 118 _base = noreg;
duke@0 119 _index = noreg;
duke@0 120 _scale = no_scale;
duke@0 121 _disp = (intptr_t) loc;
duke@0 122 _rspec = spec;
duke@0 123 }
never@297 124
duke@0 125 #endif // _LP64
duke@0 126
never@297 127
never@297 128
duke@0 129 // Convert the raw encoding form into the form expected by the constructor for
duke@0 130 // Address. An index of 4 (rsp) corresponds to having no index, so convert
duke@0 131 // that to noreg for the Address constructor.
twisti@603 132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
twisti@603 133 RelocationHolder rspec;
twisti@603 134 if (disp_is_oop) {
twisti@603 135 rspec = Relocation::spec_simple(relocInfo::oop_type);
twisti@603 136 }
duke@0 137 bool valid_index = index != rsp->encoding();
duke@0 138 if (valid_index) {
duke@0 139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
twisti@603 140 madr._rspec = rspec;
duke@0 141 return madr;
duke@0 142 } else {
duke@0 143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
twisti@603 144 madr._rspec = rspec;
duke@0 145 return madr;
duke@0 146 }
duke@0 147 }
duke@0 148
duke@0 149 // Implementation of Assembler
duke@0 150
duke@0 151 int AbstractAssembler::code_fill_byte() {
duke@0 152 return (u_char)'\xF4'; // hlt
duke@0 153 }
duke@0 154
duke@0 155 // make this go away someday
duke@0 156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
duke@0 157 if (rtype == relocInfo::none)
duke@0 158 emit_long(data);
duke@0 159 else emit_data(data, Relocation::spec_simple(rtype), format);
duke@0 160 }
duke@0 161
duke@0 162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
never@297 163 assert(imm_operand == 0, "default format must be immediate in this file");
duke@0 164 assert(inst_mark() != NULL, "must be inside InstructionMark");
duke@0 165 if (rspec.type() != relocInfo::none) {
duke@0 166 #ifdef ASSERT
duke@0 167 check_relocation(rspec, format);
duke@0 168 #endif
duke@0 169 // Do not use AbstractAssembler::relocate, which is not intended for
duke@0 170 // embedded words. Instead, relocate to the enclosing instruction.
duke@0 171
duke@0 172 // hack. call32 is too wide for mask so use disp32
duke@0 173 if (format == call32_operand)
duke@0 174 code_section()->relocate(inst_mark(), rspec, disp32_operand);
duke@0 175 else
duke@0 176 code_section()->relocate(inst_mark(), rspec, format);
duke@0 177 }
duke@0 178 emit_long(data);
duke@0 179 }
duke@0 180
never@297 181 static int encode(Register r) {
never@297 182 int enc = r->encoding();
never@297 183 if (enc >= 8) {
never@297 184 enc -= 8;
never@297 185 }
never@297 186 return enc;
never@297 187 }
never@297 188
never@297 189 static int encode(XMMRegister r) {
never@297 190 int enc = r->encoding();
never@297 191 if (enc >= 8) {
never@297 192 enc -= 8;
never@297 193 }
never@297 194 return enc;
never@297 195 }
duke@0 196
duke@0 197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
duke@0 198 assert(dst->has_byte_register(), "must have byte register");
duke@0 199 assert(isByte(op1) && isByte(op2), "wrong opcode");
duke@0 200 assert(isByte(imm8), "not a byte");
duke@0 201 assert((op1 & 0x01) == 0, "should be 8bit operation");
duke@0 202 emit_byte(op1);
never@297 203 emit_byte(op2 | encode(dst));
duke@0 204 emit_byte(imm8);
duke@0 205 }
duke@0 206
duke@0 207
never@297 208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
duke@0 209 assert(isByte(op1) && isByte(op2), "wrong opcode");
duke@0 210 assert((op1 & 0x01) == 1, "should be 32bit operation");
duke@0 211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
duke@0 212 if (is8bit(imm32)) {
duke@0 213 emit_byte(op1 | 0x02); // set sign bit
never@297 214 emit_byte(op2 | encode(dst));
duke@0 215 emit_byte(imm32 & 0xFF);
duke@0 216 } else {
duke@0 217 emit_byte(op1);
never@297 218 emit_byte(op2 | encode(dst));
duke@0 219 emit_long(imm32);
duke@0 220 }
duke@0 221 }
duke@0 222
duke@0 223 // immediate-to-memory forms
never@297 224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
duke@0 225 assert((op1 & 0x01) == 1, "should be 32bit operation");
duke@0 226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
duke@0 227 if (is8bit(imm32)) {
duke@0 228 emit_byte(op1 | 0x02); // set sign bit
never@297 229 emit_operand(rm, adr, 1);
duke@0 230 emit_byte(imm32 & 0xFF);
duke@0 231 } else {
duke@0 232 emit_byte(op1);
never@297 233 emit_operand(rm, adr, 4);
duke@0 234 emit_long(imm32);
duke@0 235 }
duke@0 236 }
duke@0 237
duke@0 238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
never@297 239 LP64_ONLY(ShouldNotReachHere());
duke@0 240 assert(isByte(op1) && isByte(op2), "wrong opcode");
duke@0 241 assert((op1 & 0x01) == 1, "should be 32bit operation");
duke@0 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
duke@0 243 InstructionMark im(this);
duke@0 244 emit_byte(op1);
never@297 245 emit_byte(op2 | encode(dst));
never@297 246 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
duke@0 247 }
duke@0 248
duke@0 249
duke@0 250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
duke@0 251 assert(isByte(op1) && isByte(op2), "wrong opcode");
duke@0 252 emit_byte(op1);
never@297 253 emit_byte(op2 | encode(dst) << 3 | encode(src));
never@297 254 }
never@297 255
never@297 256
never@297 257 void Assembler::emit_operand(Register reg, Register base, Register index,
never@297 258 Address::ScaleFactor scale, int disp,
never@297 259 RelocationHolder const& rspec,
never@297 260 int rip_relative_correction) {
duke@0 261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
never@297 262
never@297 263 // Encode the registers as needed in the fields they are used in
never@297 264
never@297 265 int regenc = encode(reg) << 3;
never@297 266 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
never@297 267 int baseenc = base->is_valid() ? encode(base) : 0;
never@297 268
duke@0 269 if (base->is_valid()) {
duke@0 270 if (index->is_valid()) {
duke@0 271 assert(scale != Address::no_scale, "inconsistent address");
duke@0 272 // [base + index*scale + disp]
never@297 273 if (disp == 0 && rtype == relocInfo::none &&
never@297 274 base != rbp LP64_ONLY(&& base != r13)) {
duke@0 275 // [base + index*scale]
duke@0 276 // [00 reg 100][ss index base]
duke@0 277 assert(index != rsp, "illegal addressing mode");
never@297 278 emit_byte(0x04 | regenc);
never@297 279 emit_byte(scale << 6 | indexenc | baseenc);
duke@0 280 } else if (is8bit(disp) && rtype == relocInfo::none) {
duke@0 281 // [base + index*scale + imm8]
duke@0 282 // [01 reg 100][ss index base] imm8
duke@0 283 assert(index != rsp, "illegal addressing mode");
never@297 284 emit_byte(0x44 | regenc);
never@297 285 emit_byte(scale << 6 | indexenc | baseenc);
duke@0 286 emit_byte(disp & 0xFF);
duke@0 287 } else {
never@297 288 // [base + index*scale + disp32]
never@297 289 // [10 reg 100][ss index base] disp32
duke@0 290 assert(index != rsp, "illegal addressing mode");
never@297 291 emit_byte(0x84 | regenc);
never@297 292 emit_byte(scale << 6 | indexenc | baseenc);
duke@0 293 emit_data(disp, rspec, disp32_operand);
duke@0 294 }
never@297 295 } else if (base == rsp LP64_ONLY(|| base == r12)) {
never@297 296 // [rsp + disp]
duke@0 297 if (disp == 0 && rtype == relocInfo::none) {
never@297 298 // [rsp]
duke@0 299 // [00 reg 100][00 100 100]
never@297 300 emit_byte(0x04 | regenc);
duke@0 301 emit_byte(0x24);
duke@0 302 } else if (is8bit(disp) && rtype == relocInfo::none) {
never@297 303 // [rsp + imm8]
never@297 304 // [01 reg 100][00 100 100] disp8
never@297 305 emit_byte(0x44 | regenc);
duke@0 306 emit_byte(0x24);
duke@0 307 emit_byte(disp & 0xFF);
duke@0 308 } else {
never@297 309 // [rsp + imm32]
never@297 310 // [10 reg 100][00 100 100] disp32
never@297 311 emit_byte(0x84 | regenc);
duke@0 312 emit_byte(0x24);
duke@0 313 emit_data(disp, rspec, disp32_operand);
duke@0 314 }
duke@0 315 } else {
duke@0 316 // [base + disp]
never@297 317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
never@297 318 if (disp == 0 && rtype == relocInfo::none &&
never@297 319 base != rbp LP64_ONLY(&& base != r13)) {
duke@0 320 // [base]
duke@0 321 // [00 reg base]
never@297 322 emit_byte(0x00 | regenc | baseenc);
duke@0 323 } else if (is8bit(disp) && rtype == relocInfo::none) {
never@297 324 // [base + disp8]
never@297 325 // [01 reg base] disp8
never@297 326 emit_byte(0x40 | regenc | baseenc);
duke@0 327 emit_byte(disp & 0xFF);
duke@0 328 } else {
never@297 329 // [base + disp32]
never@297 330 // [10 reg base] disp32
never@297 331 emit_byte(0x80 | regenc | baseenc);
duke@0 332 emit_data(disp, rspec, disp32_operand);
duke@0 333 }
duke@0 334 }
duke@0 335 } else {
duke@0 336 if (index->is_valid()) {
duke@0 337 assert(scale != Address::no_scale, "inconsistent address");
duke@0 338 // [index*scale + disp]
never@297 339 // [00 reg 100][ss index 101] disp32
duke@0 340 assert(index != rsp, "illegal addressing mode");
never@297 341 emit_byte(0x04 | regenc);
never@297 342 emit_byte(scale << 6 | indexenc | 0x05);
duke@0 343 emit_data(disp, rspec, disp32_operand);
never@297 344 } else if (rtype != relocInfo::none ) {
never@297 345 // [disp] (64bit) RIP-RELATIVE (32bit) abs
never@297 346 // [00 000 101] disp32
never@297 347
never@297 348 emit_byte(0x05 | regenc);
never@297 349 // Note that the RIP-rel. correction applies to the generated
never@297 350 // disp field, but _not_ to the target address in the rspec.
never@297 351
never@297 352 // disp was created by converting the target address minus the pc
never@297 353 // at the start of the instruction. That needs more correction here.
never@297 354 // intptr_t disp = target - next_ip;
never@297 355 assert(inst_mark() != NULL, "must be inside InstructionMark");
never@297 356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
never@297 357 int64_t adjusted = disp;
never@297 358 // Do rip-rel adjustment for 64bit
never@297 359 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
never@297 360 assert(is_simm32(adjusted),
never@297 361 "must be 32bit offset (RIP relative address)");
never@297 362 emit_data((int32_t) adjusted, rspec, disp32_operand);
never@297 363
duke@0 364 } else {
never@297 365 // 32bit never did this, did everything as the rip-rel/disp code above
never@297 366 // [disp] ABSOLUTE
never@297 367 // [00 reg 100][00 100 101] disp32
never@297 368 emit_byte(0x04 | regenc);
never@297 369 emit_byte(0x25);
duke@0 370 emit_data(disp, rspec, disp32_operand);
duke@0 371 }
duke@0 372 }
duke@0 373 }
duke@0 374
never@297 375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
never@297 376 Address::ScaleFactor scale, int disp,
never@297 377 RelocationHolder const& rspec) {
never@297 378 emit_operand((Register)reg, base, index, scale, disp, rspec);
never@297 379 }
never@297 380
duke@0 381 // Secret local extension to Assembler::WhichOperand:
duke@0 382 #define end_pc_operand (_WhichOperand_limit)
duke@0 383
duke@0 384 address Assembler::locate_operand(address inst, WhichOperand which) {
duke@0 385 // Decode the given instruction, and return the address of
duke@0 386 // an embedded 32-bit operand word.
duke@0 387
duke@0 388 // If "which" is disp32_operand, selects the displacement portion
duke@0 389 // of an effective address specifier.
never@297 390 // If "which" is imm64_operand, selects the trailing immediate constant.
duke@0 391 // If "which" is call32_operand, selects the displacement of a call or jump.
duke@0 392 // Caller is responsible for ensuring that there is such an operand,
never@297 393 // and that it is 32/64 bits wide.
duke@0 394
duke@0 395 // If "which" is end_pc_operand, find the end of the instruction.
duke@0 396
duke@0 397 address ip = inst;
never@297 398 bool is_64bit = false;
never@297 399
never@297 400 debug_only(bool has_disp32 = false);
never@297 401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
never@297 402
never@297 403 again_after_prefix:
duke@0 404 switch (0xFF & *ip++) {
duke@0 405
duke@0 406 // These convenience macros generate groups of "case" labels for the switch.
never@297 407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
never@297 408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
duke@0 409 case (x)+4: case (x)+5: case (x)+6: case (x)+7
never@297 410 #define REP16(x) REP8((x)+0): \
duke@0 411 case REP8((x)+8)
duke@0 412
duke@0 413 case CS_segment:
duke@0 414 case SS_segment:
duke@0 415 case DS_segment:
duke@0 416 case ES_segment:
duke@0 417 case FS_segment:
duke@0 418 case GS_segment:
never@297 419 // Seems dubious
never@297 420 LP64_ONLY(assert(false, "shouldn't have that prefix"));
duke@0 421 assert(ip == inst+1, "only one prefix allowed");
duke@0 422 goto again_after_prefix;
duke@0 423
never@297 424 case 0x67:
never@297 425 case REX:
never@297 426 case REX_B:
never@297 427 case REX_X:
never@297 428 case REX_XB:
never@297 429 case REX_R:
never@297 430 case REX_RB:
never@297 431 case REX_RX:
never@297 432 case REX_RXB:
never@297 433 NOT_LP64(assert(false, "64bit prefixes"));
never@297 434 goto again_after_prefix;
never@297 435
never@297 436 case REX_W:
never@297 437 case REX_WB:
never@297 438 case REX_WX:
never@297 439 case REX_WXB:
never@297 440 case REX_WR:
never@297 441 case REX_WRB:
never@297 442 case REX_WRX:
never@297 443 case REX_WRXB:
never@297 444 NOT_LP64(assert(false, "64bit prefixes"));
never@297 445 is_64bit = true;
never@297 446 goto again_after_prefix;
never@297 447
never@297 448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
duke@0 449 case 0x88: // movb a, r
duke@0 450 case 0x89: // movl a, r
duke@0 451 case 0x8A: // movb r, a
duke@0 452 case 0x8B: // movl r, a
duke@0 453 case 0x8F: // popl a
never@297 454 debug_only(has_disp32 = true);
duke@0 455 break;
duke@0 456
never@297 457 case 0x68: // pushq #32
never@297 458 if (which == end_pc_operand) {
never@297 459 return ip + 4;
never@297 460 }
never@297 461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
duke@0 462 return ip; // not produced by emit_operand
duke@0 463
duke@0 464 case 0x66: // movw ... (size prefix)
never@297 465 again_after_size_prefix2:
duke@0 466 switch (0xFF & *ip++) {
never@297 467 case REX:
never@297 468 case REX_B:
never@297 469 case REX_X:
never@297 470 case REX_XB:
never@297 471 case REX_R:
never@297 472 case REX_RB:
never@297 473 case REX_RX:
never@297 474 case REX_RXB:
never@297 475 case REX_W:
never@297 476 case REX_WB:
never@297 477 case REX_WX:
never@297 478 case REX_WXB:
never@297 479 case REX_WR:
never@297 480 case REX_WRB:
never@297 481 case REX_WRX:
never@297 482 case REX_WRXB:
never@297 483 NOT_LP64(assert(false, "64bit prefix found"));
never@297 484 goto again_after_size_prefix2;
duke@0 485 case 0x8B: // movw r, a
duke@0 486 case 0x89: // movw a, r
never@297 487 debug_only(has_disp32 = true);
duke@0 488 break;
duke@0 489 case 0xC7: // movw a, #16
never@297 490 debug_only(has_disp32 = true);
duke@0 491 tail_size = 2; // the imm16
duke@0 492 break;
duke@0 493 case 0x0F: // several SSE/SSE2 variants
duke@0 494 ip--; // reparse the 0x0F
duke@0 495 goto again_after_prefix;
duke@0 496 default:
duke@0 497 ShouldNotReachHere();
duke@0 498 }
duke@0 499 break;
duke@0 500
never@297 501 case REP8(0xB8): // movl/q r, #32/#64(oop?)
never@297 502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
never@297 503 // these asserts are somewhat nonsensical
never@297 504 #ifndef _LP64
never@297 505 assert(which == imm_operand || which == disp32_operand, "");
never@297 506 #else
never@297 507 assert((which == call32_operand || which == imm_operand) && is_64bit ||
never@297 508 which == narrow_oop_operand && !is_64bit, "");
never@297 509 #endif // _LP64
duke@0 510 return ip;
duke@0 511
duke@0 512 case 0x69: // imul r, a, #32
duke@0 513 case 0xC7: // movl a, #32(oop?)
duke@0 514 tail_size = 4;
never@297 515 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 516 break;
duke@0 517
duke@0 518 case 0x0F: // movx..., etc.
duke@0 519 switch (0xFF & *ip++) {
duke@0 520 case 0x12: // movlps
duke@0 521 case 0x28: // movaps
duke@0 522 case 0x2E: // ucomiss
duke@0 523 case 0x2F: // comiss
duke@0 524 case 0x54: // andps
duke@0 525 case 0x55: // andnps
duke@0 526 case 0x56: // orps
duke@0 527 case 0x57: // xorps
duke@0 528 case 0x6E: // movd
duke@0 529 case 0x7E: // movd
duke@0 530 case 0xAE: // ldmxcsr a
never@297 531 // 64bit side says it these have both operands but that doesn't
never@297 532 // appear to be true
never@297 533 debug_only(has_disp32 = true);
duke@0 534 break;
duke@0 535
duke@0 536 case 0xAD: // shrd r, a, %cl
duke@0 537 case 0xAF: // imul r, a
never@297 538 case 0xBE: // movsbl r, a (movsxb)
never@297 539 case 0xBF: // movswl r, a (movsxw)
never@297 540 case 0xB6: // movzbl r, a (movzxb)
never@297 541 case 0xB7: // movzwl r, a (movzxw)
duke@0 542 case REP16(0x40): // cmovl cc, r, a
duke@0 543 case 0xB0: // cmpxchgb
duke@0 544 case 0xB1: // cmpxchg
duke@0 545 case 0xC1: // xaddl
duke@0 546 case 0xC7: // cmpxchg8
duke@0 547 case REP16(0x90): // setcc a
never@297 548 debug_only(has_disp32 = true);
duke@0 549 // fall out of the switch to decode the address
duke@0 550 break;
never@297 551
duke@0 552 case 0xAC: // shrd r, a, #8
never@297 553 debug_only(has_disp32 = true);
duke@0 554 tail_size = 1; // the imm8
duke@0 555 break;
never@297 556
duke@0 557 case REP16(0x80): // jcc rdisp32
duke@0 558 if (which == end_pc_operand) return ip + 4;
never@297 559 assert(which == call32_operand, "jcc has no disp32 or imm");
duke@0 560 return ip;
duke@0 561 default:
duke@0 562 ShouldNotReachHere();
duke@0 563 }
duke@0 564 break;
duke@0 565
duke@0 566 case 0x81: // addl a, #32; addl r, #32
duke@0 567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
never@297 568 // on 32bit in the case of cmpl, the imm might be an oop
duke@0 569 tail_size = 4;
never@297 570 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 571 break;
duke@0 572
duke@0 573 case 0x83: // addl a, #8; addl r, #8
duke@0 574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
never@297 575 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 576 tail_size = 1;
duke@0 577 break;
duke@0 578
duke@0 579 case 0x9B:
duke@0 580 switch (0xFF & *ip++) {
duke@0 581 case 0xD9: // fnstcw a
never@297 582 debug_only(has_disp32 = true);
duke@0 583 break;
duke@0 584 default:
duke@0 585 ShouldNotReachHere();
duke@0 586 }
duke@0 587 break;
duke@0 588
duke@0 589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
duke@0 590 case REP4(0x10): // adc...
duke@0 591 case REP4(0x20): // and...
duke@0 592 case REP4(0x30): // xor...
duke@0 593 case REP4(0x08): // or...
duke@0 594 case REP4(0x18): // sbb...
duke@0 595 case REP4(0x28): // sub...
never@297 596 case 0xF7: // mull a
never@297 597 case 0x8D: // lea r, a
never@297 598 case 0x87: // xchg r, a
duke@0 599 case REP4(0x38): // cmp...
never@297 600 case 0x85: // test r, a
never@297 601 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 602 break;
duke@0 603
duke@0 604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
duke@0 605 case 0xC6: // movb a, #8
duke@0 606 case 0x80: // cmpb a, #8
duke@0 607 case 0x6B: // imul r, a, #8
never@297 608 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 609 tail_size = 1; // the imm8
duke@0 610 break;
duke@0 611
duke@0 612 case 0xE8: // call rdisp32
duke@0 613 case 0xE9: // jmp rdisp32
duke@0 614 if (which == end_pc_operand) return ip + 4;
never@297 615 assert(which == call32_operand, "call has no disp32 or imm");
duke@0 616 return ip;
duke@0 617
duke@0 618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
duke@0 619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
duke@0 620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
duke@0 621 case 0xDD: // fld_d a; fst_d a; fstp_d a
duke@0 622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
duke@0 623 case 0xDF: // fild_d a; fistp_d a
duke@0 624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
duke@0 625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
duke@0 626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
never@297 627 debug_only(has_disp32 = true);
duke@0 628 break;
duke@0 629
kvn@411 630 case 0xF0: // Lock
kvn@411 631 assert(os::is_MP(), "only on MP");
kvn@411 632 goto again_after_prefix;
kvn@411 633
duke@0 634 case 0xF3: // For SSE
duke@0 635 case 0xF2: // For SSE2
never@297 636 switch (0xFF & *ip++) {
never@297 637 case REX:
never@297 638 case REX_B:
never@297 639 case REX_X:
never@297 640 case REX_XB:
never@297 641 case REX_R:
never@297 642 case REX_RB:
never@297 643 case REX_RX:
never@297 644 case REX_RXB:
never@297 645 case REX_W:
never@297 646 case REX_WB:
never@297 647 case REX_WX:
never@297 648 case REX_WXB:
never@297 649 case REX_WR:
never@297 650 case REX_WRB:
never@297 651 case REX_WRX:
never@297 652 case REX_WRXB:
never@297 653 NOT_LP64(assert(false, "found 64bit prefix"));
never@297 654 ip++;
never@297 655 default:
never@297 656 ip++;
never@297 657 }
never@297 658 debug_only(has_disp32 = true); // has both kinds of operands!
duke@0 659 break;
duke@0 660
duke@0 661 default:
duke@0 662 ShouldNotReachHere();
duke@0 663
never@297 664 #undef REP8
never@297 665 #undef REP16
duke@0 666 }
duke@0 667
duke@0 668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
never@297 669 #ifdef _LP64
never@297 670 assert(which != imm_operand, "instruction is not a movq reg, imm64");
never@297 671 #else
never@297 672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
never@297 673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
never@297 674 #endif // LP64
never@297 675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
duke@0 676
duke@0 677 // parse the output of emit_operand
duke@0 678 int op2 = 0xFF & *ip++;
duke@0 679 int base = op2 & 0x07;
duke@0 680 int op3 = -1;
duke@0 681 const int b100 = 4;
duke@0 682 const int b101 = 5;
duke@0 683 if (base == b100 && (op2 >> 6) != 3) {
duke@0 684 op3 = 0xFF & *ip++;
duke@0 685 base = op3 & 0x07; // refetch the base
duke@0 686 }
duke@0 687 // now ip points at the disp (if any)
duke@0 688
duke@0 689 switch (op2 >> 6) {
duke@0 690 case 0:
duke@0 691 // [00 reg 100][ss index base]
never@297 692 // [00 reg 100][00 100 esp]
duke@0 693 // [00 reg base]
duke@0 694 // [00 reg 100][ss index 101][disp32]
duke@0 695 // [00 reg 101] [disp32]
duke@0 696
duke@0 697 if (base == b101) {
duke@0 698 if (which == disp32_operand)
duke@0 699 return ip; // caller wants the disp32
duke@0 700 ip += 4; // skip the disp32
duke@0 701 }
duke@0 702 break;
duke@0 703
duke@0 704 case 1:
duke@0 705 // [01 reg 100][ss index base][disp8]
never@297 706 // [01 reg 100][00 100 esp][disp8]
duke@0 707 // [01 reg base] [disp8]
duke@0 708 ip += 1; // skip the disp8
duke@0 709 break;
duke@0 710
duke@0 711 case 2:
duke@0 712 // [10 reg 100][ss index base][disp32]
never@297 713 // [10 reg 100][00 100 esp][disp32]
duke@0 714 // [10 reg base] [disp32]
duke@0 715 if (which == disp32_operand)
duke@0 716 return ip; // caller wants the disp32
duke@0 717 ip += 4; // skip the disp32
duke@0 718 break;
duke@0 719
duke@0 720 case 3:
duke@0 721 // [11 reg base] (not a memory addressing mode)
duke@0 722 break;
duke@0 723 }
duke@0 724
duke@0 725 if (which == end_pc_operand) {
duke@0 726 return ip + tail_size;
duke@0 727 }
duke@0 728
never@297 729 #ifdef _LP64
kvn@619 730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
never@297 731 #else
never@297 732 assert(which == imm_operand, "instruction has only an imm field");
never@297 733 #endif // LP64
duke@0 734 return ip;
duke@0 735 }
duke@0 736
duke@0 737 address Assembler::locate_next_instruction(address inst) {
duke@0 738 // Secretly share code with locate_operand:
duke@0 739 return locate_operand(inst, end_pc_operand);
duke@0 740 }
duke@0 741
duke@0 742
duke@0 743 #ifdef ASSERT
duke@0 744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
duke@0 745 address inst = inst_mark();
duke@0 746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
duke@0 747 address opnd;
duke@0 748
duke@0 749 Relocation* r = rspec.reloc();
duke@0 750 if (r->type() == relocInfo::none) {
duke@0 751 return;
duke@0 752 } else if (r->is_call() || format == call32_operand) {
duke@0 753 // assert(format == imm32_operand, "cannot specify a nonzero format");
duke@0 754 opnd = locate_operand(inst, call32_operand);
duke@0 755 } else if (r->is_data()) {
never@297 756 assert(format == imm_operand || format == disp32_operand
never@297 757 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
duke@0 758 opnd = locate_operand(inst, (WhichOperand)format);
duke@0 759 } else {
never@297 760 assert(format == imm_operand, "cannot specify a format");
duke@0 761 return;
duke@0 762 }
duke@0 763 assert(opnd == pc(), "must put operand where relocs can find it");
duke@0 764 }
never@297 765 #endif // ASSERT
never@297 766
never@297 767 void Assembler::emit_operand32(Register reg, Address adr) {
never@297 768 assert(reg->encoding() < 8, "no extended registers");
never@297 769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
never@297 770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
never@297 771 adr._rspec);
never@297 772 }
never@297 773
never@297 774 void Assembler::emit_operand(Register reg, Address adr,
never@297 775 int rip_relative_correction) {
never@297 776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
never@297 777 adr._rspec,
never@297 778 rip_relative_correction);
never@297 779 }
never@297 780
never@297 781 void Assembler::emit_operand(XMMRegister reg, Address adr) {
never@297 782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
never@297 783 adr._rspec);
never@297 784 }
never@297 785
never@297 786 // MMX operations
never@297 787 void Assembler::emit_operand(MMXRegister reg, Address adr) {
never@297 788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
never@297 789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
never@297 790 }
never@297 791
never@297 792 // work around gcc (3.2.1-7a) bug
never@297 793 void Assembler::emit_operand(Address adr, MMXRegister reg) {
never@297 794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
never@297 795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
duke@0 796 }
duke@0 797
duke@0 798
duke@0 799 void Assembler::emit_farith(int b1, int b2, int i) {
duke@0 800 assert(isByte(b1) && isByte(b2), "wrong opcode");
duke@0 801 assert(0 <= i && i < 8, "illegal stack offset");
duke@0 802 emit_byte(b1);
duke@0 803 emit_byte(b2 + i);
duke@0 804 }
duke@0 805
duke@0 806
never@297 807 // Now the Assembler instruction (identical for 32/64 bits)
never@297 808
never@297 809 void Assembler::adcl(Register dst, int32_t imm32) {
never@297 810 prefix(dst);
duke@0 811 emit_arith(0x81, 0xD0, dst, imm32);
duke@0 812 }
duke@0 813
duke@0 814 void Assembler::adcl(Register dst, Address src) {
duke@0 815 InstructionMark im(this);
never@297 816 prefix(src, dst);
duke@0 817 emit_byte(0x13);
duke@0 818 emit_operand(dst, src);
duke@0 819 }
duke@0 820
duke@0 821 void Assembler::adcl(Register dst, Register src) {
never@297 822 (void) prefix_and_encode(dst->encoding(), src->encoding());
duke@0 823 emit_arith(0x13, 0xC0, dst, src);
duke@0 824 }
duke@0 825
never@297 826 void Assembler::addl(Address dst, int32_t imm32) {
never@297 827 InstructionMark im(this);
never@297 828 prefix(dst);
never@297 829 emit_arith_operand(0x81, rax, dst, imm32);
never@297 830 }
duke@0 831
duke@0 832 void Assembler::addl(Address dst, Register src) {
duke@0 833 InstructionMark im(this);
never@297 834 prefix(dst, src);
duke@0 835 emit_byte(0x01);
duke@0 836 emit_operand(src, dst);
duke@0 837 }
duke@0 838
never@297 839 void Assembler::addl(Register dst, int32_t imm32) {
never@297 840 prefix(dst);
duke@0 841 emit_arith(0x81, 0xC0, dst, imm32);
duke@0 842 }
duke@0 843
duke@0 844 void Assembler::addl(Register dst, Address src) {
duke@0 845 InstructionMark im(this);
never@297 846 prefix(src, dst);
duke@0 847 emit_byte(0x03);
duke@0 848 emit_operand(dst, src);
duke@0 849 }
duke@0 850
duke@0 851 void Assembler::addl(Register dst, Register src) {
never@297 852 (void) prefix_and_encode(dst->encoding(), src->encoding());
duke@0 853 emit_arith(0x03, 0xC0, dst, src);
duke@0 854 }
duke@0 855
duke@0 856 void Assembler::addr_nop_4() {
duke@0 857 // 4 bytes: NOP DWORD PTR [EAX+0]
duke@0 858 emit_byte(0x0F);
duke@0 859 emit_byte(0x1F);
duke@0 860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
duke@0 861 emit_byte(0); // 8-bits offset (1 byte)
duke@0 862 }
duke@0 863
duke@0 864 void Assembler::addr_nop_5() {
duke@0 865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
duke@0 866 emit_byte(0x0F);
duke@0 867 emit_byte(0x1F);
duke@0 868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
duke@0 869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
duke@0 870 emit_byte(0); // 8-bits offset (1 byte)
duke@0 871 }
duke@0 872
duke@0 873 void Assembler::addr_nop_7() {
duke@0 874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
duke@0 875 emit_byte(0x0F);
duke@0 876 emit_byte(0x1F);
duke@0 877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
duke@0 878 emit_long(0); // 32-bits offset (4 bytes)
duke@0 879 }
duke@0 880
duke@0 881 void Assembler::addr_nop_8() {
duke@0 882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
duke@0 883 emit_byte(0x0F);
duke@0 884 emit_byte(0x1F);
duke@0 885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
duke@0 886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
duke@0 887 emit_long(0); // 32-bits offset (4 bytes)
duke@0 888 }
duke@0 889
never@297 890 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
never@297 891 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 892 emit_byte(0xF2);
never@297 893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 894 emit_byte(0x0F);
never@297 895 emit_byte(0x58);
never@297 896 emit_byte(0xC0 | encode);
never@297 897 }
never@297 898
never@297 899 void Assembler::addsd(XMMRegister dst, Address src) {
never@297 900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 901 InstructionMark im(this);
never@297 902 emit_byte(0xF2);
never@297 903 prefix(src, dst);
never@297 904 emit_byte(0x0F);
never@297 905 emit_byte(0x58);
never@297 906 emit_operand(dst, src);
never@297 907 }
never@297 908
never@297 909 void Assembler::addss(XMMRegister dst, XMMRegister src) {
never@297 910 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 911 emit_byte(0xF3);
never@297 912 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 913 emit_byte(0x0F);
never@297 914 emit_byte(0x58);
never@297 915 emit_byte(0xC0 | encode);
never@297 916 }
never@297 917
never@297 918 void Assembler::addss(XMMRegister dst, Address src) {
never@297 919 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 920 InstructionMark im(this);
never@297 921 emit_byte(0xF3);
never@297 922 prefix(src, dst);
never@297 923 emit_byte(0x0F);
never@297 924 emit_byte(0x58);
never@297 925 emit_operand(dst, src);
never@297 926 }
never@297 927
never@297 928 void Assembler::andl(Register dst, int32_t imm32) {
never@297 929 prefix(dst);
never@297 930 emit_arith(0x81, 0xE0, dst, imm32);
never@297 931 }
never@297 932
never@297 933 void Assembler::andl(Register dst, Address src) {
never@297 934 InstructionMark im(this);
never@297 935 prefix(src, dst);
never@297 936 emit_byte(0x23);
never@297 937 emit_operand(dst, src);
never@297 938 }
never@297 939
never@297 940 void Assembler::andl(Register dst, Register src) {
never@297 941 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 942 emit_arith(0x23, 0xC0, dst, src);
never@297 943 }
never@297 944
never@297 945 void Assembler::andpd(XMMRegister dst, Address src) {
never@297 946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 947 InstructionMark im(this);
never@297 948 emit_byte(0x66);
never@297 949 prefix(src, dst);
never@297 950 emit_byte(0x0F);
never@297 951 emit_byte(0x54);
never@297 952 emit_operand(dst, src);
never@297 953 }
never@297 954
twisti@747 955 void Assembler::bsfl(Register dst, Register src) {
twisti@747 956 int encode = prefix_and_encode(dst->encoding(), src->encoding());
twisti@747 957 emit_byte(0x0F);
twisti@747 958 emit_byte(0xBC);
twisti@747 959 emit_byte(0xC0 | encode);
twisti@747 960 }
twisti@747 961
twisti@747 962 void Assembler::bsrl(Register dst, Register src) {
twisti@747 963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
twisti@747 964 int encode = prefix_and_encode(dst->encoding(), src->encoding());
twisti@747 965 emit_byte(0x0F);
twisti@747 966 emit_byte(0xBD);
twisti@747 967 emit_byte(0xC0 | encode);
twisti@747 968 }
twisti@747 969
never@297 970 void Assembler::bswapl(Register reg) { // bswap
never@297 971 int encode = prefix_and_encode(reg->encoding());
never@297 972 emit_byte(0x0F);
never@297 973 emit_byte(0xC8 | encode);
never@297 974 }
never@297 975
never@297 976 void Assembler::call(Label& L, relocInfo::relocType rtype) {
never@297 977 // suspect disp32 is always good
never@297 978 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
never@297 979
never@297 980 if (L.is_bound()) {
never@297 981 const int long_size = 5;
never@297 982 int offs = (int)( target(L) - pc() );
never@297 983 assert(offs <= 0, "assembler error");
never@297 984 InstructionMark im(this);
never@297 985 // 1110 1000 #32-bit disp
never@297 986 emit_byte(0xE8);
never@297 987 emit_data(offs - long_size, rtype, operand);
never@297 988 } else {
never@297 989 InstructionMark im(this);
never@297 990 // 1110 1000 #32-bit disp
never@297 991 L.add_patch_at(code(), locator());
never@297 992
never@297 993 emit_byte(0xE8);
never@297 994 emit_data(int(0), rtype, operand);
never@297 995 }
never@297 996 }
never@297 997
never@297 998 void Assembler::call(Register dst) {
never@297 999 // This was originally using a 32bit register encoding
never@297 1000 // and surely we want 64bit!
never@297 1001 // this is a 32bit encoding but in 64bit mode the default
never@297 1002 // operand size is 64bit so there is no need for the
never@297 1003 // wide prefix. So prefix only happens if we use the
never@297 1004 // new registers. Much like push/pop.
never@297 1005 int x = offset();
never@297 1006 // this may be true but dbx disassembles it as if it
never@297 1007 // were 32bits...
never@297 1008 // int encode = prefix_and_encode(dst->encoding());
never@297 1009 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
never@297 1010 int encode = prefixq_and_encode(dst->encoding());
never@297 1011
never@297 1012 emit_byte(0xFF);
never@297 1013 emit_byte(0xD0 | encode);
never@297 1014 }
never@297 1015
never@297 1016
never@297 1017 void Assembler::call(Address adr) {
never@297 1018 InstructionMark im(this);
never@297 1019 prefix(adr);
never@297 1020 emit_byte(0xFF);
never@297 1021 emit_operand(rdx, adr);
never@297 1022 }
never@297 1023
never@297 1024 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
never@297 1025 assert(entry != NULL, "call most probably wrong");
never@297 1026 InstructionMark im(this);
never@297 1027 emit_byte(0xE8);
never@297 1028 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
never@297 1029 assert(is_simm32(disp), "must be 32bit offset (call2)");
never@297 1030 // Technically, should use call32_operand, but this format is
never@297 1031 // implied by the fact that we're emitting a call instruction.
never@297 1032
never@297 1033 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
never@297 1034 emit_data((int) disp, rspec, operand);
never@297 1035 }
never@297 1036
never@297 1037 void Assembler::cdql() {
never@297 1038 emit_byte(0x99);
never@297 1039 }
never@297 1040
never@297 1041 void Assembler::cmovl(Condition cc, Register dst, Register src) {
never@297 1042 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
never@297 1043 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1044 emit_byte(0x0F);
never@297 1045 emit_byte(0x40 | cc);
never@297 1046 emit_byte(0xC0 | encode);
never@297 1047 }
never@297 1048
never@297 1049
never@297 1050 void Assembler::cmovl(Condition cc, Register dst, Address src) {
never@297 1051 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
never@297 1052 prefix(src, dst);
never@297 1053 emit_byte(0x0F);
never@297 1054 emit_byte(0x40 | cc);
never@297 1055 emit_operand(dst, src);
never@297 1056 }
never@297 1057
never@297 1058 void Assembler::cmpb(Address dst, int imm8) {
never@297 1059 InstructionMark im(this);
never@297 1060 prefix(dst);
never@297 1061 emit_byte(0x80);
never@297 1062 emit_operand(rdi, dst, 1);
never@297 1063 emit_byte(imm8);
never@297 1064 }
never@297 1065
never@297 1066 void Assembler::cmpl(Address dst, int32_t imm32) {
never@297 1067 InstructionMark im(this);
never@297 1068 prefix(dst);
never@297 1069 emit_byte(0x81);
never@297 1070 emit_operand(rdi, dst, 4);
never@297 1071 emit_long(imm32);
never@297 1072 }
never@297 1073
never@297 1074 void Assembler::cmpl(Register dst, int32_t imm32) {
never@297 1075 prefix(dst);
never@297 1076 emit_arith(0x81, 0xF8, dst, imm32);
never@297 1077 }
never@297 1078
never@297 1079 void Assembler::cmpl(Register dst, Register src) {
never@297 1080 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 1081 emit_arith(0x3B, 0xC0, dst, src);
never@297 1082 }
never@297 1083
never@297 1084
never@297 1085 void Assembler::cmpl(Register dst, Address src) {
never@297 1086 InstructionMark im(this);
never@297 1087 prefix(src, dst);
never@297 1088 emit_byte(0x3B);
never@297 1089 emit_operand(dst, src);
never@297 1090 }
never@297 1091
never@297 1092 void Assembler::cmpw(Address dst, int imm16) {
never@297 1093 InstructionMark im(this);
never@297 1094 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
never@297 1095 emit_byte(0x66);
never@297 1096 emit_byte(0x81);
never@297 1097 emit_operand(rdi, dst, 2);
never@297 1098 emit_word(imm16);
never@297 1099 }
never@297 1100
never@297 1101 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
never@297 1102 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
never@297 1103 // The ZF is set if the compared values were equal, and cleared otherwise.
never@297 1104 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
never@297 1105 if (Atomics & 2) {
never@297 1106 // caveat: no instructionmark, so this isn't relocatable.
never@297 1107 // Emit a synthetic, non-atomic, CAS equivalent.
never@297 1108 // Beware. The synthetic form sets all ICCs, not just ZF.
never@297 1109 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
never@297 1110 cmpl(rax, adr);
never@297 1111 movl(rax, adr);
never@297 1112 if (reg != rax) {
never@297 1113 Label L ;
never@297 1114 jcc(Assembler::notEqual, L);
never@297 1115 movl(adr, reg);
never@297 1116 bind(L);
never@297 1117 }
never@297 1118 } else {
never@297 1119 InstructionMark im(this);
never@297 1120 prefix(adr, reg);
never@297 1121 emit_byte(0x0F);
never@297 1122 emit_byte(0xB1);
never@297 1123 emit_operand(reg, adr);
never@297 1124 }
never@297 1125 }
never@297 1126
never@297 1127 void Assembler::comisd(XMMRegister dst, Address src) {
never@297 1128 // NOTE: dbx seems to decode this as comiss even though the
never@297 1129 // 0x66 is there. Strangly ucomisd comes out correct
never@297 1130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1131 emit_byte(0x66);
never@297 1132 comiss(dst, src);
never@297 1133 }
never@297 1134
never@297 1135 void Assembler::comiss(XMMRegister dst, Address src) {
never@297 1136 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1137
never@297 1138 InstructionMark im(this);
never@297 1139 prefix(src, dst);
never@297 1140 emit_byte(0x0F);
never@297 1141 emit_byte(0x2F);
never@297 1142 emit_operand(dst, src);
never@297 1143 }
never@297 1144
never@297 1145 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
never@297 1146 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1147 emit_byte(0xF3);
never@297 1148 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1149 emit_byte(0x0F);
never@297 1150 emit_byte(0xE6);
never@297 1151 emit_byte(0xC0 | encode);
never@297 1152 }
never@297 1153
never@297 1154 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
never@297 1155 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1156 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1157 emit_byte(0x0F);
never@297 1158 emit_byte(0x5B);
never@297 1159 emit_byte(0xC0 | encode);
never@297 1160 }
never@297 1161
never@297 1162 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
never@297 1163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1164 emit_byte(0xF2);
never@297 1165 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1166 emit_byte(0x0F);
never@297 1167 emit_byte(0x5A);
never@297 1168 emit_byte(0xC0 | encode);
never@297 1169 }
never@297 1170
never@297 1171 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
never@297 1172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1173 emit_byte(0xF2);
never@297 1174 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1175 emit_byte(0x0F);
never@297 1176 emit_byte(0x2A);
never@297 1177 emit_byte(0xC0 | encode);
never@297 1178 }
never@297 1179
never@297 1180 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
never@297 1181 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1182 emit_byte(0xF3);
never@297 1183 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1184 emit_byte(0x0F);
never@297 1185 emit_byte(0x2A);
never@297 1186 emit_byte(0xC0 | encode);
never@297 1187 }
never@297 1188
never@297 1189 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
never@297 1190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1191 emit_byte(0xF3);
never@297 1192 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1193 emit_byte(0x0F);
never@297 1194 emit_byte(0x5A);
never@297 1195 emit_byte(0xC0 | encode);
never@297 1196 }
never@297 1197
never@297 1198 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
never@297 1199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1200 emit_byte(0xF2);
never@297 1201 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1202 emit_byte(0x0F);
never@297 1203 emit_byte(0x2C);
never@297 1204 emit_byte(0xC0 | encode);
never@297 1205 }
never@297 1206
never@297 1207 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
never@297 1208 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1209 emit_byte(0xF3);
never@297 1210 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1211 emit_byte(0x0F);
never@297 1212 emit_byte(0x2C);
never@297 1213 emit_byte(0xC0 | encode);
never@297 1214 }
never@297 1215
never@297 1216 void Assembler::decl(Address dst) {
never@297 1217 // Don't use it directly. Use MacroAssembler::decrement() instead.
never@297 1218 InstructionMark im(this);
never@297 1219 prefix(dst);
never@297 1220 emit_byte(0xFF);
never@297 1221 emit_operand(rcx, dst);
never@297 1222 }
never@297 1223
never@297 1224 void Assembler::divsd(XMMRegister dst, Address src) {
never@297 1225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1226 InstructionMark im(this);
never@297 1227 emit_byte(0xF2);
never@297 1228 prefix(src, dst);
never@297 1229 emit_byte(0x0F);
never@297 1230 emit_byte(0x5E);
never@297 1231 emit_operand(dst, src);
never@297 1232 }
never@297 1233
never@297 1234 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
never@297 1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1236 emit_byte(0xF2);
never@297 1237 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1238 emit_byte(0x0F);
never@297 1239 emit_byte(0x5E);
never@297 1240 emit_byte(0xC0 | encode);
never@297 1241 }
never@297 1242
never@297 1243 void Assembler::divss(XMMRegister dst, Address src) {
never@297 1244 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1245 InstructionMark im(this);
never@297 1246 emit_byte(0xF3);
never@297 1247 prefix(src, dst);
never@297 1248 emit_byte(0x0F);
never@297 1249 emit_byte(0x5E);
never@297 1250 emit_operand(dst, src);
never@297 1251 }
never@297 1252
never@297 1253 void Assembler::divss(XMMRegister dst, XMMRegister src) {
never@297 1254 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1255 emit_byte(0xF3);
never@297 1256 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1257 emit_byte(0x0F);
never@297 1258 emit_byte(0x5E);
never@297 1259 emit_byte(0xC0 | encode);
never@297 1260 }
never@297 1261
never@297 1262 void Assembler::emms() {
never@297 1263 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
never@297 1264 emit_byte(0x0F);
never@297 1265 emit_byte(0x77);
never@297 1266 }
never@297 1267
never@297 1268 void Assembler::hlt() {
never@297 1269 emit_byte(0xF4);
never@297 1270 }
never@297 1271
never@297 1272 void Assembler::idivl(Register src) {
never@297 1273 int encode = prefix_and_encode(src->encoding());
never@297 1274 emit_byte(0xF7);
never@297 1275 emit_byte(0xF8 | encode);
never@297 1276 }
never@297 1277
never@297 1278 void Assembler::imull(Register dst, Register src) {
never@297 1279 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1280 emit_byte(0x0F);
never@297 1281 emit_byte(0xAF);
never@297 1282 emit_byte(0xC0 | encode);
never@297 1283 }
never@297 1284
never@297 1285
never@297 1286 void Assembler::imull(Register dst, Register src, int value) {
never@297 1287 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1288 if (is8bit(value)) {
never@297 1289 emit_byte(0x6B);
never@297 1290 emit_byte(0xC0 | encode);
never@297 1291 emit_byte(value);
never@297 1292 } else {
never@297 1293 emit_byte(0x69);
never@297 1294 emit_byte(0xC0 | encode);
never@297 1295 emit_long(value);
never@297 1296 }
never@297 1297 }
never@297 1298
never@297 1299 void Assembler::incl(Address dst) {
never@297 1300 // Don't use it directly. Use MacroAssembler::increment() instead.
never@297 1301 InstructionMark im(this);
never@297 1302 prefix(dst);
never@297 1303 emit_byte(0xFF);
never@297 1304 emit_operand(rax, dst);
never@297 1305 }
never@297 1306
never@297 1307 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
never@297 1308 InstructionMark im(this);
never@297 1309 relocate(rtype);
never@297 1310 assert((0 <= cc) && (cc < 16), "illegal cc");
never@297 1311 if (L.is_bound()) {
never@297 1312 address dst = target(L);
never@297 1313 assert(dst != NULL, "jcc most probably wrong");
never@297 1314
never@297 1315 const int short_size = 2;
never@297 1316 const int long_size = 6;
never@297 1317 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
never@297 1318 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
never@297 1319 // 0111 tttn #8-bit disp
never@297 1320 emit_byte(0x70 | cc);
never@297 1321 emit_byte((offs - short_size) & 0xFF);
never@297 1322 } else {
never@297 1323 // 0000 1111 1000 tttn #32-bit disp
never@297 1324 assert(is_simm32(offs - long_size),
never@297 1325 "must be 32bit offset (call4)");
never@297 1326 emit_byte(0x0F);
never@297 1327 emit_byte(0x80 | cc);
never@297 1328 emit_long(offs - long_size);
never@297 1329 }
never@297 1330 } else {
never@297 1331 // Note: could eliminate cond. jumps to this jump if condition
never@297 1332 // is the same however, seems to be rather unlikely case.
never@297 1333 // Note: use jccb() if label to be bound is very close to get
never@297 1334 // an 8-bit displacement
never@297 1335 L.add_patch_at(code(), locator());
never@297 1336 emit_byte(0x0F);
never@297 1337 emit_byte(0x80 | cc);
never@297 1338 emit_long(0);
never@297 1339 }
never@297 1340 }
never@297 1341
never@297 1342 void Assembler::jccb(Condition cc, Label& L) {
never@297 1343 if (L.is_bound()) {
never@297 1344 const int short_size = 2;
never@297 1345 address entry = target(L);
never@297 1346 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
never@297 1347 "Dispacement too large for a short jmp");
never@297 1348 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
never@297 1349 // 0111 tttn #8-bit disp
never@297 1350 emit_byte(0x70 | cc);
never@297 1351 emit_byte((offs - short_size) & 0xFF);
never@297 1352 } else {
never@297 1353 InstructionMark im(this);
never@297 1354 L.add_patch_at(code(), locator());
never@297 1355 emit_byte(0x70 | cc);
never@297 1356 emit_byte(0);
never@297 1357 }
never@297 1358 }
never@297 1359
never@297 1360 void Assembler::jmp(Address adr) {
never@297 1361 InstructionMark im(this);
never@297 1362 prefix(adr);
never@297 1363 emit_byte(0xFF);
never@297 1364 emit_operand(rsp, adr);
never@297 1365 }
never@297 1366
never@297 1367 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
never@297 1368 if (L.is_bound()) {
never@297 1369 address entry = target(L);
never@297 1370 assert(entry != NULL, "jmp most probably wrong");
never@297 1371 InstructionMark im(this);
never@297 1372 const int short_size = 2;
never@297 1373 const int long_size = 5;
never@297 1374 intptr_t offs = entry - _code_pos;
never@297 1375 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
never@297 1376 emit_byte(0xEB);
never@297 1377 emit_byte((offs - short_size) & 0xFF);
never@297 1378 } else {
never@297 1379 emit_byte(0xE9);
never@297 1380 emit_long(offs - long_size);
never@297 1381 }
never@297 1382 } else {
never@297 1383 // By default, forward jumps are always 32-bit displacements, since
never@297 1384 // we can't yet know where the label will be bound. If you're sure that
never@297 1385 // the forward jump will not run beyond 256 bytes, use jmpb to
never@297 1386 // force an 8-bit displacement.
never@297 1387 InstructionMark im(this);
never@297 1388 relocate(rtype);
never@297 1389 L.add_patch_at(code(), locator());
never@297 1390 emit_byte(0xE9);
never@297 1391 emit_long(0);
never@297 1392 }
never@297 1393 }
never@297 1394
never@297 1395 void Assembler::jmp(Register entry) {
never@297 1396 int encode = prefix_and_encode(entry->encoding());
never@297 1397 emit_byte(0xFF);
never@297 1398 emit_byte(0xE0 | encode);
never@297 1399 }
never@297 1400
never@297 1401 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
never@297 1402 InstructionMark im(this);
never@297 1403 emit_byte(0xE9);
never@297 1404 assert(dest != NULL, "must have a target");
never@297 1405 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
never@297 1406 assert(is_simm32(disp), "must be 32bit offset (jmp)");
never@297 1407 emit_data(disp, rspec.reloc(), call32_operand);
never@297 1408 }
never@297 1409
never@297 1410 void Assembler::jmpb(Label& L) {
never@297 1411 if (L.is_bound()) {
never@297 1412 const int short_size = 2;
never@297 1413 address entry = target(L);
never@297 1414 assert(is8bit((entry - _code_pos) + short_size),
never@297 1415 "Dispacement too large for a short jmp");
never@297 1416 assert(entry != NULL, "jmp most probably wrong");
never@297 1417 intptr_t offs = entry - _code_pos;
never@297 1418 emit_byte(0xEB);
never@297 1419 emit_byte((offs - short_size) & 0xFF);
never@297 1420 } else {
never@297 1421 InstructionMark im(this);
never@297 1422 L.add_patch_at(code(), locator());
never@297 1423 emit_byte(0xEB);
never@297 1424 emit_byte(0);
never@297 1425 }
never@297 1426 }
never@297 1427
never@297 1428 void Assembler::ldmxcsr( Address src) {
never@297 1429 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1430 InstructionMark im(this);
never@297 1431 prefix(src);
never@297 1432 emit_byte(0x0F);
never@297 1433 emit_byte(0xAE);
never@297 1434 emit_operand(as_Register(2), src);
never@297 1435 }
never@297 1436
never@297 1437 void Assembler::leal(Register dst, Address src) {
never@297 1438 InstructionMark im(this);
never@297 1439 #ifdef _LP64
never@297 1440 emit_byte(0x67); // addr32
never@297 1441 prefix(src, dst);
never@297 1442 #endif // LP64
never@297 1443 emit_byte(0x8D);
never@297 1444 emit_operand(dst, src);
never@297 1445 }
never@297 1446
never@297 1447 void Assembler::lock() {
never@297 1448 if (Atomics & 1) {
never@297 1449 // Emit either nothing, a NOP, or a NOP: prefix
never@297 1450 emit_byte(0x90) ;
never@297 1451 } else {
never@297 1452 emit_byte(0xF0);
never@297 1453 }
never@297 1454 }
never@297 1455
twisti@747 1456 void Assembler::lzcntl(Register dst, Register src) {
twisti@747 1457 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
twisti@747 1458 emit_byte(0xF3);
twisti@747 1459 int encode = prefix_and_encode(dst->encoding(), src->encoding());
twisti@747 1460 emit_byte(0x0F);
twisti@747 1461 emit_byte(0xBD);
twisti@747 1462 emit_byte(0xC0 | encode);
twisti@747 1463 }
twisti@747 1464
never@652 1465 // Emit mfence instruction
never@297 1466 void Assembler::mfence() {
never@652 1467 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
never@652 1468 emit_byte( 0x0F );
never@652 1469 emit_byte( 0xAE );
never@652 1470 emit_byte( 0xF0 );
never@297 1471 }
never@297 1472
never@297 1473 void Assembler::mov(Register dst, Register src) {
never@297 1474 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
never@297 1475 }
never@297 1476
never@297 1477 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
never@297 1478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1479 int dstenc = dst->encoding();
never@297 1480 int srcenc = src->encoding();
never@297 1481 emit_byte(0x66);
never@297 1482 if (dstenc < 8) {
never@297 1483 if (srcenc >= 8) {
never@297 1484 prefix(REX_B);
never@297 1485 srcenc -= 8;
never@297 1486 }
never@297 1487 } else {
never@297 1488 if (srcenc < 8) {
never@297 1489 prefix(REX_R);
never@297 1490 } else {
never@297 1491 prefix(REX_RB);
never@297 1492 srcenc -= 8;
never@297 1493 }
never@297 1494 dstenc -= 8;
never@297 1495 }
never@297 1496 emit_byte(0x0F);
never@297 1497 emit_byte(0x28);
never@297 1498 emit_byte(0xC0 | dstenc << 3 | srcenc);
never@297 1499 }
never@297 1500
never@297 1501 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
never@297 1502 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1503 int dstenc = dst->encoding();
never@297 1504 int srcenc = src->encoding();
never@297 1505 if (dstenc < 8) {
never@297 1506 if (srcenc >= 8) {
never@297 1507 prefix(REX_B);
never@297 1508 srcenc -= 8;
never@297 1509 }
never@297 1510 } else {
never@297 1511 if (srcenc < 8) {
never@297 1512 prefix(REX_R);
never@297 1513 } else {
never@297 1514 prefix(REX_RB);
never@297 1515 srcenc -= 8;
never@297 1516 }
never@297 1517 dstenc -= 8;
never@297 1518 }
never@297 1519 emit_byte(0x0F);
never@297 1520 emit_byte(0x28);
never@297 1521 emit_byte(0xC0 | dstenc << 3 | srcenc);
never@297 1522 }
never@297 1523
never@297 1524 void Assembler::movb(Register dst, Address src) {
never@297 1525 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
never@297 1526 InstructionMark im(this);
never@297 1527 prefix(src, dst, true);
never@297 1528 emit_byte(0x8A);
never@297 1529 emit_operand(dst, src);
never@297 1530 }
never@297 1531
never@297 1532
never@297 1533 void Assembler::movb(Address dst, int imm8) {
never@297 1534 InstructionMark im(this);
never@297 1535 prefix(dst);
never@297 1536 emit_byte(0xC6);
never@297 1537 emit_operand(rax, dst, 1);
never@297 1538 emit_byte(imm8);
never@297 1539 }
never@297 1540
never@297 1541
never@297 1542 void Assembler::movb(Address dst, Register src) {
never@297 1543 assert(src->has_byte_register(), "must have byte register");
never@297 1544 InstructionMark im(this);
never@297 1545 prefix(dst, src, true);
never@297 1546 emit_byte(0x88);
never@297 1547 emit_operand(src, dst);
never@297 1548 }
never@297 1549
never@297 1550 void Assembler::movdl(XMMRegister dst, Register src) {
never@297 1551 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1552 emit_byte(0x66);
never@297 1553 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1554 emit_byte(0x0F);
never@297 1555 emit_byte(0x6E);
never@297 1556 emit_byte(0xC0 | encode);
never@297 1557 }
never@297 1558
never@297 1559 void Assembler::movdl(Register dst, XMMRegister src) {
never@297 1560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1561 emit_byte(0x66);
never@297 1562 // swap src/dst to get correct prefix
never@297 1563 int encode = prefix_and_encode(src->encoding(), dst->encoding());
never@297 1564 emit_byte(0x0F);
never@297 1565 emit_byte(0x7E);
never@297 1566 emit_byte(0xC0 | encode);
never@297 1567 }
never@297 1568
never@297 1569 void Assembler::movdqa(XMMRegister dst, Address src) {
never@297 1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1571 InstructionMark im(this);
never@297 1572 emit_byte(0x66);
never@297 1573 prefix(src, dst);
never@297 1574 emit_byte(0x0F);
never@297 1575 emit_byte(0x6F);
never@297 1576 emit_operand(dst, src);
never@297 1577 }
never@297 1578
never@297 1579 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
never@297 1580 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1581 emit_byte(0x66);
never@297 1582 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
never@297 1583 emit_byte(0x0F);
never@297 1584 emit_byte(0x6F);
never@297 1585 emit_byte(0xC0 | encode);
never@297 1586 }
never@297 1587
never@297 1588 void Assembler::movdqa(Address dst, XMMRegister src) {
never@297 1589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1590 InstructionMark im(this);
never@297 1591 emit_byte(0x66);
never@297 1592 prefix(dst, src);
never@297 1593 emit_byte(0x0F);
never@297 1594 emit_byte(0x7F);
never@297 1595 emit_operand(src, dst);
never@297 1596 }
never@297 1597
kvn@387 1598 void Assembler::movdqu(XMMRegister dst, Address src) {
kvn@387 1599 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
kvn@387 1600 InstructionMark im(this);
kvn@387 1601 emit_byte(0xF3);
kvn@387 1602 prefix(src, dst);
kvn@387 1603 emit_byte(0x0F);
kvn@387 1604 emit_byte(0x6F);
kvn@387 1605 emit_operand(dst, src);
kvn@387 1606 }
kvn@387 1607
kvn@387 1608 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
kvn@387 1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
kvn@387 1610 emit_byte(0xF3);
kvn@387 1611 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
kvn@387 1612 emit_byte(0x0F);
kvn@387 1613 emit_byte(0x6F);
kvn@387 1614 emit_byte(0xC0 | encode);
kvn@387 1615 }
kvn@387 1616
kvn@387 1617 void Assembler::movdqu(Address dst, XMMRegister src) {
kvn@387 1618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
kvn@387 1619 InstructionMark im(this);
kvn@387 1620 emit_byte(0xF3);
kvn@387 1621 prefix(dst, src);
kvn@387 1622 emit_byte(0x0F);
kvn@387 1623 emit_byte(0x7F);
kvn@387 1624 emit_operand(src, dst);
kvn@387 1625 }
kvn@387 1626
never@297 1627 // Uses zero extension on 64bit
never@297 1628
never@297 1629 void Assembler::movl(Register dst, int32_t imm32) {
never@297 1630 int encode = prefix_and_encode(dst->encoding());
never@297 1631 emit_byte(0xB8 | encode);
never@297 1632 emit_long(imm32);
never@297 1633 }
never@297 1634
never@297 1635 void Assembler::movl(Register dst, Register src) {
never@297 1636 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1637 emit_byte(0x8B);
never@297 1638 emit_byte(0xC0 | encode);
never@297 1639 }
never@297 1640
never@297 1641 void Assembler::movl(Register dst, Address src) {
never@297 1642 InstructionMark im(this);
never@297 1643 prefix(src, dst);
never@297 1644 emit_byte(0x8B);
never@297 1645 emit_operand(dst, src);
never@297 1646 }
never@297 1647
never@297 1648 void Assembler::movl(Address dst, int32_t imm32) {
never@297 1649 InstructionMark im(this);
never@297 1650 prefix(dst);
never@297 1651 emit_byte(0xC7);
never@297 1652 emit_operand(rax, dst, 4);
never@297 1653 emit_long(imm32);
never@297 1654 }
never@297 1655
never@297 1656 void Assembler::movl(Address dst, Register src) {
never@297 1657 InstructionMark im(this);
never@297 1658 prefix(dst, src);
never@297 1659 emit_byte(0x89);
never@297 1660 emit_operand(src, dst);
never@297 1661 }
never@297 1662
never@297 1663 // New cpus require to use movsd and movss to avoid partial register stall
never@297 1664 // when loading from memory. But for old Opteron use movlpd instead of movsd.
never@297 1665 // The selection is done in MacroAssembler::movdbl() and movflt().
never@297 1666 void Assembler::movlpd(XMMRegister dst, Address src) {
never@297 1667 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1668 InstructionMark im(this);
never@297 1669 emit_byte(0x66);
never@297 1670 prefix(src, dst);
never@297 1671 emit_byte(0x0F);
never@297 1672 emit_byte(0x12);
never@297 1673 emit_operand(dst, src);
never@297 1674 }
never@297 1675
never@297 1676 void Assembler::movq( MMXRegister dst, Address src ) {
never@297 1677 assert( VM_Version::supports_mmx(), "" );
never@297 1678 emit_byte(0x0F);
never@297 1679 emit_byte(0x6F);
never@297 1680 emit_operand(dst, src);
never@297 1681 }
never@297 1682
never@297 1683 void Assembler::movq( Address dst, MMXRegister src ) {
never@297 1684 assert( VM_Version::supports_mmx(), "" );
never@297 1685 emit_byte(0x0F);
never@297 1686 emit_byte(0x7F);
never@297 1687 // workaround gcc (3.2.1-7a) bug
never@297 1688 // In that version of gcc with only an emit_operand(MMX, Address)
never@297 1689 // gcc will tail jump and try and reverse the parameters completely
never@297 1690 // obliterating dst in the process. By having a version available
never@297 1691 // that doesn't need to swap the args at the tail jump the bug is
never@297 1692 // avoided.
never@297 1693 emit_operand(dst, src);
never@297 1694 }
never@297 1695
never@297 1696 void Assembler::movq(XMMRegister dst, Address src) {
never@297 1697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1698 InstructionMark im(this);
never@297 1699 emit_byte(0xF3);
never@297 1700 prefix(src, dst);
never@297 1701 emit_byte(0x0F);
never@297 1702 emit_byte(0x7E);
never@297 1703 emit_operand(dst, src);
never@297 1704 }
never@297 1705
never@297 1706 void Assembler::movq(Address dst, XMMRegister src) {
never@297 1707 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1708 InstructionMark im(this);
never@297 1709 emit_byte(0x66);
never@297 1710 prefix(dst, src);
never@297 1711 emit_byte(0x0F);
never@297 1712 emit_byte(0xD6);
never@297 1713 emit_operand(src, dst);
never@297 1714 }
never@297 1715
never@297 1716 void Assembler::movsbl(Register dst, Address src) { // movsxb
never@297 1717 InstructionMark im(this);
never@297 1718 prefix(src, dst);
never@297 1719 emit_byte(0x0F);
never@297 1720 emit_byte(0xBE);
never@297 1721 emit_operand(dst, src);
never@297 1722 }
never@297 1723
never@297 1724 void Assembler::movsbl(Register dst, Register src) { // movsxb
never@297 1725 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
never@297 1726 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
never@297 1727 emit_byte(0x0F);
never@297 1728 emit_byte(0xBE);
never@297 1729 emit_byte(0xC0 | encode);
never@297 1730 }
never@297 1731
never@297 1732 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
never@297 1733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1734 emit_byte(0xF2);
never@297 1735 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1736 emit_byte(0x0F);
never@297 1737 emit_byte(0x10);
never@297 1738 emit_byte(0xC0 | encode);
never@297 1739 }
never@297 1740
never@297 1741 void Assembler::movsd(XMMRegister dst, Address src) {
never@297 1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1743 InstructionMark im(this);
never@297 1744 emit_byte(0xF2);
never@297 1745 prefix(src, dst);
never@297 1746 emit_byte(0x0F);
never@297 1747 emit_byte(0x10);
never@297 1748 emit_operand(dst, src);
never@297 1749 }
never@297 1750
never@297 1751 void Assembler::movsd(Address dst, XMMRegister src) {
never@297 1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1753 InstructionMark im(this);
never@297 1754 emit_byte(0xF2);
never@297 1755 prefix(dst, src);
never@297 1756 emit_byte(0x0F);
never@297 1757 emit_byte(0x11);
never@297 1758 emit_operand(src, dst);
never@297 1759 }
never@297 1760
never@297 1761 void Assembler::movss(XMMRegister dst, XMMRegister src) {
never@297 1762 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1763 emit_byte(0xF3);
never@297 1764 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1765 emit_byte(0x0F);
never@297 1766 emit_byte(0x10);
never@297 1767 emit_byte(0xC0 | encode);
never@297 1768 }
never@297 1769
never@297 1770 void Assembler::movss(XMMRegister dst, Address src) {
never@297 1771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1772 InstructionMark im(this);
never@297 1773 emit_byte(0xF3);
never@297 1774 prefix(src, dst);
never@297 1775 emit_byte(0x0F);
never@297 1776 emit_byte(0x10);
never@297 1777 emit_operand(dst, src);
never@297 1778 }
never@297 1779
never@297 1780 void Assembler::movss(Address dst, XMMRegister src) {
never@297 1781 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1782 InstructionMark im(this);
never@297 1783 emit_byte(0xF3);
never@297 1784 prefix(dst, src);
never@297 1785 emit_byte(0x0F);
never@297 1786 emit_byte(0x11);
never@297 1787 emit_operand(src, dst);
never@297 1788 }
never@297 1789
never@297 1790 void Assembler::movswl(Register dst, Address src) { // movsxw
never@297 1791 InstructionMark im(this);
never@297 1792 prefix(src, dst);
never@297 1793 emit_byte(0x0F);
never@297 1794 emit_byte(0xBF);
never@297 1795 emit_operand(dst, src);
never@297 1796 }
never@297 1797
never@297 1798 void Assembler::movswl(Register dst, Register src) { // movsxw
never@297 1799 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1800 emit_byte(0x0F);
never@297 1801 emit_byte(0xBF);
never@297 1802 emit_byte(0xC0 | encode);
never@297 1803 }
never@297 1804
never@297 1805 void Assembler::movw(Address dst, int imm16) {
never@297 1806 InstructionMark im(this);
never@297 1807
never@297 1808 emit_byte(0x66); // switch to 16-bit mode
never@297 1809 prefix(dst);
never@297 1810 emit_byte(0xC7);
never@297 1811 emit_operand(rax, dst, 2);
never@297 1812 emit_word(imm16);
never@297 1813 }
never@297 1814
never@297 1815 void Assembler::movw(Register dst, Address src) {
never@297 1816 InstructionMark im(this);
never@297 1817 emit_byte(0x66);
never@297 1818 prefix(src, dst);
never@297 1819 emit_byte(0x8B);
never@297 1820 emit_operand(dst, src);
never@297 1821 }
never@297 1822
never@297 1823 void Assembler::movw(Address dst, Register src) {
never@297 1824 InstructionMark im(this);
never@297 1825 emit_byte(0x66);
never@297 1826 prefix(dst, src);
never@297 1827 emit_byte(0x89);
never@297 1828 emit_operand(src, dst);
never@297 1829 }
never@297 1830
never@297 1831 void Assembler::movzbl(Register dst, Address src) { // movzxb
never@297 1832 InstructionMark im(this);
never@297 1833 prefix(src, dst);
never@297 1834 emit_byte(0x0F);
never@297 1835 emit_byte(0xB6);
never@297 1836 emit_operand(dst, src);
never@297 1837 }
never@297 1838
never@297 1839 void Assembler::movzbl(Register dst, Register src) { // movzxb
never@297 1840 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
never@297 1841 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
never@297 1842 emit_byte(0x0F);
never@297 1843 emit_byte(0xB6);
never@297 1844 emit_byte(0xC0 | encode);
never@297 1845 }
never@297 1846
never@297 1847 void Assembler::movzwl(Register dst, Address src) { // movzxw
never@297 1848 InstructionMark im(this);
never@297 1849 prefix(src, dst);
never@297 1850 emit_byte(0x0F);
never@297 1851 emit_byte(0xB7);
never@297 1852 emit_operand(dst, src);
never@297 1853 }
never@297 1854
never@297 1855 void Assembler::movzwl(Register dst, Register src) { // movzxw
never@297 1856 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1857 emit_byte(0x0F);
never@297 1858 emit_byte(0xB7);
never@297 1859 emit_byte(0xC0 | encode);
never@297 1860 }
never@297 1861
never@297 1862 void Assembler::mull(Address src) {
never@297 1863 InstructionMark im(this);
never@297 1864 prefix(src);
never@297 1865 emit_byte(0xF7);
never@297 1866 emit_operand(rsp, src);
never@297 1867 }
never@297 1868
never@297 1869 void Assembler::mull(Register src) {
never@297 1870 int encode = prefix_and_encode(src->encoding());
never@297 1871 emit_byte(0xF7);
never@297 1872 emit_byte(0xE0 | encode);
never@297 1873 }
never@297 1874
never@297 1875 void Assembler::mulsd(XMMRegister dst, Address src) {
never@297 1876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1877 InstructionMark im(this);
never@297 1878 emit_byte(0xF2);
never@297 1879 prefix(src, dst);
never@297 1880 emit_byte(0x0F);
never@297 1881 emit_byte(0x59);
never@297 1882 emit_operand(dst, src);
never@297 1883 }
never@297 1884
never@297 1885 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
never@297 1886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 1887 emit_byte(0xF2);
never@297 1888 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1889 emit_byte(0x0F);
never@297 1890 emit_byte(0x59);
never@297 1891 emit_byte(0xC0 | encode);
never@297 1892 }
never@297 1893
never@297 1894 void Assembler::mulss(XMMRegister dst, Address src) {
never@297 1895 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1896 InstructionMark im(this);
never@297 1897 emit_byte(0xF3);
never@297 1898 prefix(src, dst);
never@297 1899 emit_byte(0x0F);
never@297 1900 emit_byte(0x59);
never@297 1901 emit_operand(dst, src);
never@297 1902 }
never@297 1903
never@297 1904 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
never@297 1905 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 1906 emit_byte(0xF3);
never@297 1907 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 1908 emit_byte(0x0F);
never@297 1909 emit_byte(0x59);
never@297 1910 emit_byte(0xC0 | encode);
never@297 1911 }
never@297 1912
never@297 1913 void Assembler::negl(Register dst) {
never@297 1914 int encode = prefix_and_encode(dst->encoding());
never@297 1915 emit_byte(0xF7);
never@297 1916 emit_byte(0xD8 | encode);
never@297 1917 }
never@297 1918
duke@0 1919 void Assembler::nop(int i) {
never@297 1920 #ifdef ASSERT
duke@0 1921 assert(i > 0, " ");
never@297 1922 // The fancy nops aren't currently recognized by debuggers making it a
never@297 1923 // pain to disassemble code while debugging. If asserts are on clearly
never@297 1924 // speed is not an issue so simply use the single byte traditional nop
never@297 1925 // to do alignment.
never@297 1926
never@297 1927 for (; i > 0 ; i--) emit_byte(0x90);
never@297 1928 return;
never@297 1929
never@297 1930 #endif // ASSERT
never@297 1931
duke@0 1932 if (UseAddressNop && VM_Version::is_intel()) {
duke@0 1933 //
duke@0 1934 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
duke@0 1935 // 1: 0x90
duke@0 1936 // 2: 0x66 0x90
duke@0 1937 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
duke@0 1938 // 4: 0x0F 0x1F 0x40 0x00
duke@0 1939 // 5: 0x0F 0x1F 0x44 0x00 0x00
duke@0 1940 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
duke@0 1941 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
duke@0 1942 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 1943 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 1944 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 1945 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 1946
duke@0 1947 // The rest coding is Intel specific - don't use consecutive address nops
duke@0 1948
duke@0 1949 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
duke@0 1950 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
duke@0 1951 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
duke@0 1952 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
duke@0 1953
duke@0 1954 while(i >= 15) {
duke@0 1955 // For Intel don't generate consecutive addess nops (mix with regular nops)
duke@0 1956 i -= 15;
duke@0 1957 emit_byte(0x66); // size prefix
duke@0 1958 emit_byte(0x66); // size prefix
duke@0 1959 emit_byte(0x66); // size prefix
duke@0 1960 addr_nop_8();
duke@0 1961 emit_byte(0x66); // size prefix
duke@0 1962 emit_byte(0x66); // size prefix
duke@0 1963 emit_byte(0x66); // size prefix
duke@0 1964 emit_byte(0x90); // nop
duke@0 1965 }
duke@0 1966 switch (i) {
duke@0 1967 case 14:
duke@0 1968 emit_byte(0x66); // size prefix
duke@0 1969 case 13:
duke@0 1970 emit_byte(0x66); // size prefix
duke@0 1971 case 12:
duke@0 1972 addr_nop_8();
duke@0 1973 emit_byte(0x66); // size prefix
duke@0 1974 emit_byte(0x66); // size prefix
duke@0 1975 emit_byte(0x66); // size prefix
duke@0 1976 emit_byte(0x90); // nop
duke@0 1977 break;
duke@0 1978 case 11:
duke@0 1979 emit_byte(0x66); // size prefix
duke@0 1980 case 10:
duke@0 1981 emit_byte(0x66); // size prefix
duke@0 1982 case 9:
duke@0 1983 emit_byte(0x66); // size prefix
duke@0 1984 case 8:
duke@0 1985 addr_nop_8();
duke@0 1986 break;
duke@0 1987 case 7:
duke@0 1988 addr_nop_7();
duke@0 1989 break;
duke@0 1990 case 6:
duke@0 1991 emit_byte(0x66); // size prefix
duke@0 1992 case 5:
duke@0 1993 addr_nop_5();
duke@0 1994 break;
duke@0 1995 case 4:
duke@0 1996 addr_nop_4();
duke@0 1997 break;
duke@0 1998 case 3:
duke@0 1999 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
duke@0 2000 emit_byte(0x66); // size prefix
duke@0 2001 case 2:
duke@0 2002 emit_byte(0x66); // size prefix
duke@0 2003 case 1:
duke@0 2004 emit_byte(0x90); // nop
duke@0 2005 break;
duke@0 2006 default:
duke@0 2007 assert(i == 0, " ");
duke@0 2008 }
duke@0 2009 return;
duke@0 2010 }
duke@0 2011 if (UseAddressNop && VM_Version::is_amd()) {
duke@0 2012 //
duke@0 2013 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
duke@0 2014 // 1: 0x90
duke@0 2015 // 2: 0x66 0x90
duke@0 2016 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
duke@0 2017 // 4: 0x0F 0x1F 0x40 0x00
duke@0 2018 // 5: 0x0F 0x1F 0x44 0x00 0x00
duke@0 2019 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
duke@0 2020 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
duke@0 2021 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 2022 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 2023 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 2024 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 2025
duke@0 2026 // The rest coding is AMD specific - use consecutive address nops
duke@0 2027
duke@0 2028 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
duke@0 2029 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
duke@0 2030 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
duke@0 2031 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
duke@0 2032 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
duke@0 2033 // Size prefixes (0x66) are added for larger sizes
duke@0 2034
duke@0 2035 while(i >= 22) {
duke@0 2036 i -= 11;
duke@0 2037 emit_byte(0x66); // size prefix
duke@0 2038 emit_byte(0x66); // size prefix
duke@0 2039 emit_byte(0x66); // size prefix
duke@0 2040 addr_nop_8();
duke@0 2041 }
duke@0 2042 // Generate first nop for size between 21-12
duke@0 2043 switch (i) {
duke@0 2044 case 21:
duke@0 2045 i -= 1;
duke@0 2046 emit_byte(0x66); // size prefix
duke@0 2047 case 20:
duke@0 2048 case 19:
duke@0 2049 i -= 1;
duke@0 2050 emit_byte(0x66); // size prefix
duke@0 2051 case 18:
duke@0 2052 case 17:
duke@0 2053 i -= 1;
duke@0 2054 emit_byte(0x66); // size prefix
duke@0 2055 case 16:
duke@0 2056 case 15:
duke@0 2057 i -= 8;
duke@0 2058 addr_nop_8();
duke@0 2059 break;
duke@0 2060 case 14:
duke@0 2061 case 13:
duke@0 2062 i -= 7;
duke@0 2063 addr_nop_7();
duke@0 2064 break;
duke@0 2065 case 12:
duke@0 2066 i -= 6;
duke@0 2067 emit_byte(0x66); // size prefix
duke@0 2068 addr_nop_5();
duke@0 2069 break;
duke@0 2070 default:
duke@0 2071 assert(i < 12, " ");
duke@0 2072 }
duke@0 2073
duke@0 2074 // Generate second nop for size between 11-1
duke@0 2075 switch (i) {
duke@0 2076 case 11:
duke@0 2077 emit_byte(0x66); // size prefix
duke@0 2078 case 10:
duke@0 2079 emit_byte(0x66); // size prefix
duke@0 2080 case 9:
duke@0 2081 emit_byte(0x66); // size prefix
duke@0 2082 case 8:
duke@0 2083 addr_nop_8();
duke@0 2084 break;
duke@0 2085 case 7:
duke@0 2086 addr_nop_7();
duke@0 2087 break;
duke@0 2088 case 6:
duke@0 2089 emit_byte(0x66); // size prefix
duke@0 2090 case 5:
duke@0 2091 addr_nop_5();
duke@0 2092 break;
duke@0 2093 case 4:
duke@0 2094 addr_nop_4();
duke@0 2095 break;
duke@0 2096 case 3:
duke@0 2097 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
duke@0 2098 emit_byte(0x66); // size prefix
duke@0 2099 case 2:
duke@0 2100 emit_byte(0x66); // size prefix
duke@0 2101 case 1:
duke@0 2102 emit_byte(0x90); // nop
duke@0 2103 break;
duke@0 2104 default:
duke@0 2105 assert(i == 0, " ");
duke@0 2106 }
duke@0 2107 return;
duke@0 2108 }
duke@0 2109
duke@0 2110 // Using nops with size prefixes "0x66 0x90".
duke@0 2111 // From AMD Optimization Guide:
duke@0 2112 // 1: 0x90
duke@0 2113 // 2: 0x66 0x90
duke@0 2114 // 3: 0x66 0x66 0x90
duke@0 2115 // 4: 0x66 0x66 0x66 0x90
duke@0 2116 // 5: 0x66 0x66 0x90 0x66 0x90
duke@0 2117 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
duke@0 2118 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
duke@0 2119 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
duke@0 2120 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
duke@0 2121 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
duke@0 2122 //
duke@0 2123 while(i > 12) {
duke@0 2124 i -= 4;
duke@0 2125 emit_byte(0x66); // size prefix
duke@0 2126 emit_byte(0x66);
duke@0 2127 emit_byte(0x66);
duke@0 2128 emit_byte(0x90); // nop
duke@0 2129 }
duke@0 2130 // 1 - 12 nops
duke@0 2131 if(i > 8) {
duke@0 2132 if(i > 9) {
duke@0 2133 i -= 1;
duke@0 2134 emit_byte(0x66);
duke@0 2135 }
duke@0 2136 i -= 3;
duke@0 2137 emit_byte(0x66);
duke@0 2138 emit_byte(0x66);
duke@0 2139 emit_byte(0x90);
duke@0 2140 }
duke@0 2141 // 1 - 8 nops
duke@0 2142 if(i > 4) {
duke@0 2143 if(i > 6) {
duke@0 2144 i -= 1;
duke@0 2145 emit_byte(0x66);
duke@0 2146 }
duke@0 2147 i -= 3;
duke@0 2148 emit_byte(0x66);
duke@0 2149 emit_byte(0x66);
duke@0 2150 emit_byte(0x90);
duke@0 2151 }
duke@0 2152 switch (i) {
duke@0 2153 case 4:
duke@0 2154 emit_byte(0x66);
duke@0 2155 case 3:
duke@0 2156 emit_byte(0x66);
duke@0 2157 case 2:
duke@0 2158 emit_byte(0x66);
duke@0 2159 case 1:
duke@0 2160 emit_byte(0x90);
duke@0 2161 break;
duke@0 2162 default:
duke@0 2163 assert(i == 0, " ");
duke@0 2164 }
duke@0 2165 }
duke@0 2166
never@297 2167 void Assembler::notl(Register dst) {
never@297 2168 int encode = prefix_and_encode(dst->encoding());
never@297 2169 emit_byte(0xF7);
never@297 2170 emit_byte(0xD0 | encode );
never@297 2171 }
never@297 2172
never@297 2173 void Assembler::orl(Address dst, int32_t imm32) {
never@297 2174 InstructionMark im(this);
never@297 2175 prefix(dst);
never@297 2176 emit_byte(0x81);
never@297 2177 emit_operand(rcx, dst, 4);
never@297 2178 emit_long(imm32);
never@297 2179 }
never@297 2180
never@297 2181 void Assembler::orl(Register dst, int32_t imm32) {
never@297 2182 prefix(dst);
never@297 2183 emit_arith(0x81, 0xC8, dst, imm32);
never@297 2184 }
never@297 2185
never@297 2186
never@297 2187 void Assembler::orl(Register dst, Address src) {
never@297 2188 InstructionMark im(this);
never@297 2189 prefix(src, dst);
never@297 2190 emit_byte(0x0B);
never@297 2191 emit_operand(dst, src);
never@297 2192 }
never@297 2193
never@297 2194
never@297 2195 void Assembler::orl(Register dst, Register src) {
never@297 2196 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 2197 emit_arith(0x0B, 0xC0, dst, src);
never@297 2198 }
never@297 2199
cfang@674 2200 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
cfang@674 2201 assert(VM_Version::supports_sse4_2(), "");
cfang@674 2202
cfang@674 2203 InstructionMark im(this);
cfang@674 2204 emit_byte(0x66);
cfang@674 2205 prefix(src, dst);
cfang@674 2206 emit_byte(0x0F);
cfang@674 2207 emit_byte(0x3A);
cfang@674 2208 emit_byte(0x61);
cfang@674 2209 emit_operand(dst, src);
cfang@674 2210 emit_byte(imm8);
cfang@674 2211 }
cfang@674 2212
cfang@674 2213 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
cfang@674 2214 assert(VM_Version::supports_sse4_2(), "");
cfang@674 2215
cfang@674 2216 emit_byte(0x66);
cfang@674 2217 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
cfang@674 2218 emit_byte(0x0F);
cfang@674 2219 emit_byte(0x3A);
cfang@674 2220 emit_byte(0x61);
cfang@674 2221 emit_byte(0xC0 | encode);
cfang@674 2222 emit_byte(imm8);
cfang@674 2223 }
cfang@674 2224
never@297 2225 // generic
never@297 2226 void Assembler::pop(Register dst) {
never@297 2227 int encode = prefix_and_encode(dst->encoding());
never@297 2228 emit_byte(0x58 | encode);
never@297 2229 }
never@297 2230
twisti@620 2231 void Assembler::popcntl(Register dst, Address src) {
twisti@620 2232 assert(VM_Version::supports_popcnt(), "must support");
twisti@620 2233 InstructionMark im(this);
twisti@620 2234 emit_byte(0xF3);
twisti@620 2235 prefix(src, dst);
twisti@620 2236 emit_byte(0x0F);
twisti@620 2237 emit_byte(0xB8);
twisti@620 2238 emit_operand(dst, src);
twisti@620 2239 }
twisti@620 2240
twisti@620 2241 void Assembler::popcntl(Register dst, Register src) {
twisti@620 2242 assert(VM_Version::supports_popcnt(), "must support");
twisti@620 2243 emit_byte(0xF3);
twisti@620 2244 int encode = prefix_and_encode(dst->encoding(), src->encoding());
twisti@620 2245 emit_byte(0x0F);
twisti@620 2246 emit_byte(0xB8);
twisti@620 2247 emit_byte(0xC0 | encode);
twisti@620 2248 }
twisti@620 2249
never@297 2250 void Assembler::popf() {
never@297 2251 emit_byte(0x9D);
never@297 2252 }
never@297 2253
never@297 2254 void Assembler::popl(Address dst) {
never@297 2255 // NOTE: this will adjust stack by 8byte on 64bits
never@297 2256 InstructionMark im(this);
never@297 2257 prefix(dst);
never@297 2258 emit_byte(0x8F);
never@297 2259 emit_operand(rax, dst);
never@297 2260 }
never@297 2261
never@297 2262 void Assembler::prefetch_prefix(Address src) {
never@297 2263 prefix(src);
never@297 2264 emit_byte(0x0F);
never@297 2265 }
never@297 2266
never@297 2267 void Assembler::prefetchnta(Address src) {
never@297 2268 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
never@297 2269 InstructionMark im(this);
never@297 2270 prefetch_prefix(src);
never@297 2271 emit_byte(0x18);
never@297 2272 emit_operand(rax, src); // 0, src
never@297 2273 }
never@297 2274
never@297 2275 void Assembler::prefetchr(Address src) {
never@297 2276 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
never@297 2277 InstructionMark im(this);
never@297 2278 prefetch_prefix(src);
never@297 2279 emit_byte(0x0D);
never@297 2280 emit_operand(rax, src); // 0, src
never@297 2281 }
never@297 2282
never@297 2283 void Assembler::prefetcht0(Address src) {
never@297 2284 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
never@297 2285 InstructionMark im(this);
never@297 2286 prefetch_prefix(src);
never@297 2287 emit_byte(0x18);
never@297 2288 emit_operand(rcx, src); // 1, src
never@297 2289 }
never@297 2290
never@297 2291 void Assembler::prefetcht1(Address src) {
never@297 2292 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
never@297 2293 InstructionMark im(this);
never@297 2294 prefetch_prefix(src);
never@297 2295 emit_byte(0x18);
never@297 2296 emit_operand(rdx, src); // 2, src
never@297 2297 }
never@297 2298
never@297 2299 void Assembler::prefetcht2(Address src) {
never@297 2300 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
never@297 2301 InstructionMark im(this);
never@297 2302 prefetch_prefix(src);
never@297 2303 emit_byte(0x18);
never@297 2304 emit_operand(rbx, src); // 3, src
never@297 2305 }
never@297 2306
never@297 2307 void Assembler::prefetchw(Address src) {
never@297 2308 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
never@297 2309 InstructionMark im(this);
never@297 2310 prefetch_prefix(src);
never@297 2311 emit_byte(0x0D);
never@297 2312 emit_operand(rcx, src); // 1, src
never@297 2313 }
never@297 2314
never@297 2315 void Assembler::prefix(Prefix p) {
never@297 2316 a_byte(p);
never@297 2317 }
never@297 2318
never@297 2319 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
never@297 2320 assert(isByte(mode), "invalid value");
never@297 2321 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2322
never@297 2323 emit_byte(0x66);
never@297 2324 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2325 emit_byte(0x0F);
never@297 2326 emit_byte(0x70);
never@297 2327 emit_byte(0xC0 | encode);
never@297 2328 emit_byte(mode & 0xFF);
never@297 2329
never@297 2330 }
never@297 2331
never@297 2332 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
never@297 2333 assert(isByte(mode), "invalid value");
never@297 2334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2335
never@297 2336 InstructionMark im(this);
never@297 2337 emit_byte(0x66);
never@297 2338 prefix(src, dst);
never@297 2339 emit_byte(0x0F);
never@297 2340 emit_byte(0x70);
never@297 2341 emit_operand(dst, src);
never@297 2342 emit_byte(mode & 0xFF);
never@297 2343 }
never@297 2344
never@297 2345 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
never@297 2346 assert(isByte(mode), "invalid value");
never@297 2347 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2348
never@297 2349 emit_byte(0xF2);
never@297 2350 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2351 emit_byte(0x0F);
never@297 2352 emit_byte(0x70);
never@297 2353 emit_byte(0xC0 | encode);
never@297 2354 emit_byte(mode & 0xFF);
never@297 2355 }
never@297 2356
never@297 2357 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
never@297 2358 assert(isByte(mode), "invalid value");
never@297 2359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2360
never@297 2361 InstructionMark im(this);
never@297 2362 emit_byte(0xF2);
never@297 2363 prefix(src, dst); // QQ new
never@297 2364 emit_byte(0x0F);
never@297 2365 emit_byte(0x70);
never@297 2366 emit_operand(dst, src);
never@297 2367 emit_byte(mode & 0xFF);
never@297 2368 }
never@297 2369
never@297 2370 void Assembler::psrlq(XMMRegister dst, int shift) {
never@297 2371 // HMM Table D-1 says sse2 or mmx
never@297 2372 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2373
never@297 2374 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
never@297 2375 emit_byte(0x66);
never@297 2376 emit_byte(0x0F);
never@297 2377 emit_byte(0x73);
never@297 2378 emit_byte(0xC0 | encode);
never@297 2379 emit_byte(shift);
never@297 2380 }
never@297 2381
cfang@674 2382 void Assembler::ptest(XMMRegister dst, Address src) {
cfang@674 2383 assert(VM_Version::supports_sse4_1(), "");
cfang@674 2384
cfang@674 2385 InstructionMark im(this);
cfang@674 2386 emit_byte(0x66);
cfang@674 2387 prefix(src, dst);
cfang@674 2388 emit_byte(0x0F);
cfang@674 2389 emit_byte(0x38);
cfang@674 2390 emit_byte(0x17);
cfang@674 2391 emit_operand(dst, src);
cfang@674 2392 }
cfang@674 2393
cfang@674 2394 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
cfang@674 2395 assert(VM_Version::supports_sse4_1(), "");
cfang@674 2396
cfang@674 2397 emit_byte(0x66);
cfang@674 2398 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
cfang@674 2399 emit_byte(0x0F);
cfang@674 2400 emit_byte(0x38);
cfang@674 2401 emit_byte(0x17);
cfang@674 2402 emit_byte(0xC0 | encode);
cfang@674 2403 }
cfang@674 2404
never@297 2405 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
never@297 2406 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2407 emit_byte(0x66);
never@297 2408 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2409 emit_byte(0x0F);
never@297 2410 emit_byte(0x60);
never@297 2411 emit_byte(0xC0 | encode);
never@297 2412 }
never@297 2413
never@297 2414 void Assembler::push(int32_t imm32) {
never@297 2415 // in 64bits we push 64bits onto the stack but only
never@297 2416 // take a 32bit immediate
never@297 2417 emit_byte(0x68);
never@297 2418 emit_long(imm32);
never@297 2419 }
never@297 2420
never@297 2421 void Assembler::push(Register src) {
never@297 2422 int encode = prefix_and_encode(src->encoding());
never@297 2423
never@297 2424 emit_byte(0x50 | encode);
never@297 2425 }
never@297 2426
never@297 2427 void Assembler::pushf() {
never@297 2428 emit_byte(0x9C);
never@297 2429 }
never@297 2430
never@297 2431 void Assembler::pushl(Address src) {
never@297 2432 // Note this will push 64bit on 64bit
never@297 2433 InstructionMark im(this);
never@297 2434 prefix(src);
never@297 2435 emit_byte(0xFF);
never@297 2436 emit_operand(rsi, src);
never@297 2437 }
never@297 2438
never@297 2439 void Assembler::pxor(XMMRegister dst, Address src) {
never@297 2440 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2441 InstructionMark im(this);
never@297 2442 emit_byte(0x66);
never@297 2443 prefix(src, dst);
never@297 2444 emit_byte(0x0F);
never@297 2445 emit_byte(0xEF);
never@297 2446 emit_operand(dst, src);
never@297 2447 }
never@297 2448
never@297 2449 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
never@297 2450 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2451 InstructionMark im(this);
never@297 2452 emit_byte(0x66);
never@297 2453 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2454 emit_byte(0x0F);
never@297 2455 emit_byte(0xEF);
never@297 2456 emit_byte(0xC0 | encode);
never@297 2457 }
never@297 2458
never@297 2459 void Assembler::rcll(Register dst, int imm8) {
never@297 2460 assert(isShiftCount(imm8), "illegal shift count");
never@297 2461 int encode = prefix_and_encode(dst->encoding());
never@297 2462 if (imm8 == 1) {
never@297 2463 emit_byte(0xD1);
never@297 2464 emit_byte(0xD0 | encode);
never@297 2465 } else {
never@297 2466 emit_byte(0xC1);
never@297 2467 emit_byte(0xD0 | encode);
never@297 2468 emit_byte(imm8);
never@297 2469 }
never@297 2470 }
never@297 2471
never@297 2472 // copies data from [esi] to [edi] using rcx pointer sized words
never@297 2473 // generic
never@297 2474 void Assembler::rep_mov() {
never@297 2475 emit_byte(0xF3);
never@297 2476 // MOVSQ
never@297 2477 LP64_ONLY(prefix(REX_W));
never@297 2478 emit_byte(0xA5);
never@297 2479 }
never@297 2480
never@297 2481 // sets rcx pointer sized words with rax, value at [edi]
never@297 2482 // generic
never@297 2483 void Assembler::rep_set() { // rep_set
never@297 2484 emit_byte(0xF3);
never@297 2485 // STOSQ
never@297 2486 LP64_ONLY(prefix(REX_W));
never@297 2487 emit_byte(0xAB);
never@297 2488 }
never@297 2489
never@297 2490 // scans rcx pointer sized words at [edi] for occurance of rax,
never@297 2491 // generic
never@297 2492 void Assembler::repne_scan() { // repne_scan
never@297 2493 emit_byte(0xF2);
never@297 2494 // SCASQ
never@297 2495 LP64_ONLY(prefix(REX_W));
never@297 2496 emit_byte(0xAF);
never@297 2497 }
never@297 2498
never@297 2499 #ifdef _LP64
never@297 2500 // scans rcx 4 byte words at [edi] for occurance of rax,
never@297 2501 // generic
never@297 2502 void Assembler::repne_scanl() { // repne_scan
never@297 2503 emit_byte(0xF2);
never@297 2504 // SCASL
never@297 2505 emit_byte(0xAF);
never@297 2506 }
never@297 2507 #endif
never@297 2508
duke@0 2509 void Assembler::ret(int imm16) {
duke@0 2510 if (imm16 == 0) {
duke@0 2511 emit_byte(0xC3);
duke@0 2512 } else {
duke@0 2513 emit_byte(0xC2);
duke@0 2514 emit_word(imm16);
duke@0 2515 }
duke@0 2516 }
duke@0 2517
never@297 2518 void Assembler::sahf() {
never@297 2519 #ifdef _LP64
never@297 2520 // Not supported in 64bit mode
never@297 2521 ShouldNotReachHere();
never@297 2522 #endif
never@297 2523 emit_byte(0x9E);
never@297 2524 }
never@297 2525
never@297 2526 void Assembler::sarl(Register dst, int imm8) {
never@297 2527 int encode = prefix_and_encode(dst->encoding());
never@297 2528 assert(isShiftCount(imm8), "illegal shift count");
never@297 2529 if (imm8 == 1) {
never@297 2530 emit_byte(0xD1);
never@297 2531 emit_byte(0xF8 | encode);
never@297 2532 } else {
never@297 2533 emit_byte(0xC1);
never@297 2534 emit_byte(0xF8 | encode);
never@297 2535 emit_byte(imm8);
never@297 2536 }
never@297 2537 }
never@297 2538
never@297 2539 void Assembler::sarl(Register dst) {
never@297 2540 int encode = prefix_and_encode(dst->encoding());
never@297 2541 emit_byte(0xD3);
never@297 2542 emit_byte(0xF8 | encode);
never@297 2543 }
never@297 2544
never@297 2545 void Assembler::sbbl(Address dst, int32_t imm32) {
never@297 2546 InstructionMark im(this);
never@297 2547 prefix(dst);
never@297 2548 emit_arith_operand(0x81, rbx, dst, imm32);
never@297 2549 }
never@297 2550
never@297 2551 void Assembler::sbbl(Register dst, int32_t imm32) {
never@297 2552 prefix(dst);
never@297 2553 emit_arith(0x81, 0xD8, dst, imm32);
never@297 2554 }
never@297 2555
never@297 2556
never@297 2557 void Assembler::sbbl(Register dst, Address src) {
never@297 2558 InstructionMark im(this);
never@297 2559 prefix(src, dst);
never@297 2560 emit_byte(0x1B);
never@297 2561 emit_operand(dst, src);
never@297 2562 }
never@297 2563
never@297 2564 void Assembler::sbbl(Register dst, Register src) {
never@297 2565 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 2566 emit_arith(0x1B, 0xC0, dst, src);
never@297 2567 }
never@297 2568
never@297 2569 void Assembler::setb(Condition cc, Register dst) {
never@297 2570 assert(0 <= cc && cc < 16, "illegal cc");
never@297 2571 int encode = prefix_and_encode(dst->encoding(), true);
duke@0 2572 emit_byte(0x0F);
never@297 2573 emit_byte(0x90 | cc);
never@297 2574 emit_byte(0xC0 | encode);
never@297 2575 }
never@297 2576
never@297 2577 void Assembler::shll(Register dst, int imm8) {
never@297 2578 assert(isShiftCount(imm8), "illegal shift count");
never@297 2579 int encode = prefix_and_encode(dst->encoding());
never@297 2580 if (imm8 == 1 ) {
never@297 2581 emit_byte(0xD1);
never@297 2582 emit_byte(0xE0 | encode);
never@297 2583 } else {
never@297 2584 emit_byte(0xC1);
never@297 2585 emit_byte(0xE0 | encode);
never@297 2586 emit_byte(imm8);
never@297 2587 }
never@297 2588 }
never@297 2589
never@297 2590 void Assembler::shll(Register dst) {
never@297 2591 int encode = prefix_and_encode(dst->encoding());
never@297 2592 emit_byte(0xD3);
never@297 2593 emit_byte(0xE0 | encode);
never@297 2594 }
never@297 2595
never@297 2596 void Assembler::shrl(Register dst, int imm8) {
never@297 2597 assert(isShiftCount(imm8), "illegal shift count");
never@297 2598 int encode = prefix_and_encode(dst->encoding());
never@297 2599 emit_byte(0xC1);
never@297 2600 emit_byte(0xE8 | encode);
never@297 2601 emit_byte(imm8);
never@297 2602 }
never@297 2603
never@297 2604 void Assembler::shrl(Register dst) {
never@297 2605 int encode = prefix_and_encode(dst->encoding());
never@297 2606 emit_byte(0xD3);
never@297 2607 emit_byte(0xE8 | encode);
never@297 2608 }
duke@0 2609
duke@0 2610 // copies a single word from [esi] to [edi]
duke@0 2611 void Assembler::smovl() {
duke@0 2612 emit_byte(0xA5);
duke@0 2613 }
duke@0 2614
never@297 2615 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
never@297 2616 // HMM Table D-1 says sse2
never@297 2617 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2619 emit_byte(0xF2);
never@297 2620 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2621 emit_byte(0x0F);
never@297 2622 emit_byte(0x51);
never@297 2623 emit_byte(0xC0 | encode);
never@297 2624 }
never@297 2625
never@297 2626 void Assembler::stmxcsr( Address dst) {
never@297 2627 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2628 InstructionMark im(this);
never@297 2629 prefix(dst);
never@297 2630 emit_byte(0x0F);
never@297 2631 emit_byte(0xAE);
never@297 2632 emit_operand(as_Register(3), dst);
never@297 2633 }
never@297 2634
never@297 2635 void Assembler::subl(Address dst, int32_t imm32) {
never@297 2636 InstructionMark im(this);
never@297 2637 prefix(dst);
never@297 2638 if (is8bit(imm32)) {
never@297 2639 emit_byte(0x83);
never@297 2640 emit_operand(rbp, dst, 1);
never@297 2641 emit_byte(imm32 & 0xFF);
never@297 2642 } else {
never@297 2643 emit_byte(0x81);
never@297 2644 emit_operand(rbp, dst, 4);
never@297 2645 emit_long(imm32);
never@297 2646 }
never@297 2647 }
never@297 2648
never@297 2649 void Assembler::subl(Register dst, int32_t imm32) {
never@297 2650 prefix(dst);
never@297 2651 emit_arith(0x81, 0xE8, dst, imm32);
never@297 2652 }
never@297 2653
never@297 2654 void Assembler::subl(Address dst, Register src) {
never@297 2655 InstructionMark im(this);
never@297 2656 prefix(dst, src);
never@297 2657 emit_byte(0x29);
never@297 2658 emit_operand(src, dst);
never@297 2659 }
never@297 2660
never@297 2661 void Assembler::subl(Register dst, Address src) {
never@297 2662 InstructionMark im(this);
never@297 2663 prefix(src, dst);
never@297 2664 emit_byte(0x2B);
never@297 2665 emit_operand(dst, src);
never@297 2666 }
never@297 2667
never@297 2668 void Assembler::subl(Register dst, Register src) {
never@297 2669 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 2670 emit_arith(0x2B, 0xC0, dst, src);
never@297 2671 }
never@297 2672
never@297 2673 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
never@297 2674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2675 emit_byte(0xF2);
never@297 2676 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2677 emit_byte(0x0F);
never@297 2678 emit_byte(0x5C);
never@297 2679 emit_byte(0xC0 | encode);
never@297 2680 }
never@297 2681
never@297 2682 void Assembler::subsd(XMMRegister dst, Address src) {
never@297 2683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2684 InstructionMark im(this);
never@297 2685 emit_byte(0xF2);
never@297 2686 prefix(src, dst);
never@297 2687 emit_byte(0x0F);
never@297 2688 emit_byte(0x5C);
never@297 2689 emit_operand(dst, src);
never@297 2690 }
never@297 2691
never@297 2692 void Assembler::subss(XMMRegister dst, XMMRegister src) {
never@297 2693 NOT_LP64(assert(VM_Version::supports_sse(), ""));
duke@0 2694 emit_byte(0xF3);
never@297 2695 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2696 emit_byte(0x0F);
never@297 2697 emit_byte(0x5C);
never@297 2698 emit_byte(0xC0 | encode);
never@297 2699 }
never@297 2700
never@297 2701 void Assembler::subss(XMMRegister dst, Address src) {
never@297 2702 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2703 InstructionMark im(this);
duke@0 2704 emit_byte(0xF3);
never@297 2705 prefix(src, dst);
duke@0 2706 emit_byte(0x0F);
never@297 2707 emit_byte(0x5C);
never@297 2708 emit_operand(dst, src);
never@297 2709 }
never@297 2710
never@297 2711 void Assembler::testb(Register dst, int imm8) {
never@297 2712 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
never@297 2713 (void) prefix_and_encode(dst->encoding(), true);
never@297 2714 emit_arith_b(0xF6, 0xC0, dst, imm8);
never@297 2715 }
never@297 2716
never@297 2717 void Assembler::testl(Register dst, int32_t imm32) {
never@297 2718 // not using emit_arith because test
never@297 2719 // doesn't support sign-extension of
never@297 2720 // 8bit operands
never@297 2721 int encode = dst->encoding();
never@297 2722 if (encode == 0) {
never@297 2723 emit_byte(0xA9);
duke@0 2724 } else {
never@297 2725 encode = prefix_and_encode(encode);
never@297 2726 emit_byte(0xF7);
never@297 2727 emit_byte(0xC0 | encode);
never@297 2728 }
never@297 2729 emit_long(imm32);
never@297 2730 }
never@297 2731
never@297 2732 void Assembler::testl(Register dst, Register src) {
never@297 2733 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 2734 emit_arith(0x85, 0xC0, dst, src);
never@297 2735 }
never@297 2736
never@297 2737 void Assembler::testl(Register dst, Address src) {
never@297 2738 InstructionMark im(this);
never@297 2739 prefix(src, dst);
never@297 2740 emit_byte(0x85);
never@297 2741 emit_operand(dst, src);
never@297 2742 }
never@297 2743
never@297 2744 void Assembler::ucomisd(XMMRegister dst, Address src) {
never@297 2745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2746 emit_byte(0x66);
never@297 2747 ucomiss(dst, src);
never@297 2748 }
never@297 2749
never@297 2750 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
never@297 2751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2752 emit_byte(0x66);
never@297 2753 ucomiss(dst, src);
never@297 2754 }
never@297 2755
never@297 2756 void Assembler::ucomiss(XMMRegister dst, Address src) {
never@297 2757 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2758
never@297 2759 InstructionMark im(this);
never@297 2760 prefix(src, dst);
never@297 2761 emit_byte(0x0F);
never@297 2762 emit_byte(0x2E);
never@297 2763 emit_operand(dst, src);
never@297 2764 }
never@297 2765
never@297 2766 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
never@297 2767 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2768 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2769 emit_byte(0x0F);
never@297 2770 emit_byte(0x2E);
never@297 2771 emit_byte(0xC0 | encode);
never@297 2772 }
never@297 2773
never@297 2774
never@297 2775 void Assembler::xaddl(Address dst, Register src) {
never@297 2776 InstructionMark im(this);
never@297 2777 prefix(dst, src);
never@297 2778 emit_byte(0x0F);
never@297 2779 emit_byte(0xC1);
never@297 2780 emit_operand(src, dst);
never@297 2781 }
never@297 2782
never@297 2783 void Assembler::xchgl(Register dst, Address src) { // xchg
never@297 2784 InstructionMark im(this);
never@297 2785 prefix(src, dst);
never@297 2786 emit_byte(0x87);
never@297 2787 emit_operand(dst, src);
never@297 2788 }
never@297 2789
never@297 2790 void Assembler::xchgl(Register dst, Register src) {
never@297 2791 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2792 emit_byte(0x87);
never@297 2793 emit_byte(0xc0 | encode);
never@297 2794 }
never@297 2795
never@297 2796 void Assembler::xorl(Register dst, int32_t imm32) {
never@297 2797 prefix(dst);
never@297 2798 emit_arith(0x81, 0xF0, dst, imm32);
never@297 2799 }
never@297 2800
never@297 2801 void Assembler::xorl(Register dst, Address src) {
never@297 2802 InstructionMark im(this);
never@297 2803 prefix(src, dst);
never@297 2804 emit_byte(0x33);
never@297 2805 emit_operand(dst, src);
never@297 2806 }
never@297 2807
never@297 2808 void Assembler::xorl(Register dst, Register src) {
never@297 2809 (void) prefix_and_encode(dst->encoding(), src->encoding());
never@297 2810 emit_arith(0x33, 0xC0, dst, src);
never@297 2811 }
never@297 2812
never@297 2813 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
never@297 2814 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2815 emit_byte(0x66);
never@297 2816 xorps(dst, src);
never@297 2817 }
never@297 2818
never@297 2819 void Assembler::xorpd(XMMRegister dst, Address src) {
never@297 2820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
never@297 2821 InstructionMark im(this);
never@297 2822 emit_byte(0x66);
never@297 2823 prefix(src, dst);
never@297 2824 emit_byte(0x0F);
never@297 2825 emit_byte(0x57);
never@297 2826 emit_operand(dst, src);
never@297 2827 }
never@297 2828
never@297 2829
never@297 2830 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
never@297 2831 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2832 int encode = prefix_and_encode(dst->encoding(), src->encoding());
never@297 2833 emit_byte(0x0F);
never@297 2834 emit_byte(0x57);
never@297 2835 emit_byte(0xC0 | encode);
never@297 2836 }
never@297 2837
never@297 2838 void Assembler::xorps(XMMRegister dst, Address src) {
never@297 2839 NOT_LP64(assert(VM_Version::supports_sse(), ""));
never@297 2840 InstructionMark im(this);
never@297 2841 prefix(src, dst);
never@297 2842 emit_byte(0x0F);
never@297 2843 emit_byte(0x57);
never@297 2844 emit_operand(dst, src);
never@297 2845 }
never@297 2846
never@297 2847 #ifndef _LP64
never@297 2848 // 32bit only pieces of the assembler
never@297 2849
never@297 2850 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
never@297 2851 // NO PREFIX AS NEVER 64BIT
never@297 2852 InstructionMark im(this);
never@297 2853 emit_byte(0x81);
never@297 2854 emit_byte(0xF8 | src1->encoding());
never@297 2855 emit_data(imm32, rspec, 0);
never@297 2856 }
never@297 2857
never@297 2858 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
never@297 2859 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
never@297 2860 InstructionMark im(this);
never@297 2861 emit_byte(0x81);
never@297 2862 emit_operand(rdi, src1);
never@297 2863 emit_data(imm32, rspec, 0);
never@297 2864 }
never@297 2865
never@297 2866 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
never@297 2867 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
never@297 2868 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
never@297 2869 void Assembler::cmpxchg8(Address adr) {
never@297 2870 InstructionMark im(this);
never@297 2871 emit_byte(0x0F);
never@297 2872 emit_byte(0xc7);
never@297 2873 emit_operand(rcx, adr);
never@297 2874 }
never@297 2875
never@297 2876 void Assembler::decl(Register dst) {
never@297 2877 // Don't use it directly. Use MacroAssembler::decrementl() instead.
never@297 2878 emit_byte(0x48 | dst->encoding());
never@297 2879 }
never@297 2880
never@297 2881 #endif // _LP64
never@297 2882
never@297 2883 // 64bit typically doesn't use the x87 but needs to for the trig funcs
never@297 2884
never@297 2885 void Assembler::fabs() {
never@297 2886 emit_byte(0xD9);
never@297 2887 emit_byte(0xE1);
never@297 2888 }
never@297 2889
never@297 2890 void Assembler::fadd(int i) {
never@297 2891 emit_farith(0xD8, 0xC0, i);
never@297 2892 }
never@297 2893
never@297 2894 void Assembler::fadd_d(Address src) {
never@297 2895 InstructionMark im(this);
never@297 2896 emit_byte(0xDC);
never@297 2897 emit_operand32(rax, src);
never@297 2898 }
never@297 2899
never@297 2900 void Assembler::fadd_s(Address src) {
never@297 2901 InstructionMark im(this);
never@297 2902 emit_byte(0xD8);
never@297 2903 emit_operand32(rax, src);
never@297 2904 }
never@297 2905
never@297 2906 void Assembler::fadda(int i) {
never@297 2907 emit_farith(0xDC, 0xC0, i);
never@297 2908 }
never@297 2909
never@297 2910 void Assembler::faddp(int i) {
never@297 2911 emit_farith(0xDE, 0xC0, i);
never@297 2912 }
never@297 2913
never@297 2914 void Assembler::fchs() {
never@297 2915 emit_byte(0xD9);
never@297 2916 emit_byte(0xE0);
never@297 2917 }
never@297 2918
never@297 2919 void Assembler::fcom(int i) {
never@297 2920 emit_farith(0xD8, 0xD0, i);
never@297 2921 }
never@297 2922
never@297 2923 void Assembler::fcomp(int i) {
never@297 2924 emit_farith(0xD8, 0xD8, i);
never@297 2925 }
never@297 2926
never@297 2927 void Assembler::fcomp_d(Address src) {
never@297 2928 InstructionMark im(this);
never@297 2929 emit_byte(0xDC);
never@297 2930 emit_operand32(rbx, src);
never@297 2931 }
never@297 2932
never@297 2933 void Assembler::fcomp_s(Address src) {
never@297 2934 InstructionMark im(this);
never@297 2935 emit_byte(0xD8);
never@297 2936 emit_operand32(rbx, src);
never@297 2937 }
never@297 2938
never@297 2939 void Assembler::fcompp() {
never@297 2940 emit_byte(0xDE);
never@297 2941 emit_byte(0xD9);
never@297 2942 }
never@297 2943
never@297 2944 void Assembler::fcos() {
never@297 2945 emit_byte(0xD9);
duke@0 2946 emit_byte(0xFF);
never@297 2947 }
never@297 2948
never@297 2949 void Assembler::fdecstp() {
never@297 2950 emit_byte(0xD9);
never@297 2951 emit_byte(0xF6);
never@297 2952 }
never@297 2953
never@297 2954 void Assembler::fdiv(int i) {
never@297 2955 emit_farith(0xD8, 0xF0, i);
never@297 2956 }
never@297 2957
never@297 2958 void Assembler::fdiv_d(Address src) {
never@297 2959 InstructionMark im(this);
never@297 2960 emit_byte(0xDC);
never@297 2961 emit_operand32(rsi, src);
never@297 2962 }
never@297 2963
never@297 2964 void Assembler::fdiv_s(Address src) {
never@297 2965 InstructionMark im(this);
never@297 2966 emit_byte(0xD8);
never@297 2967 emit_operand32(rsi, src);
never@297 2968 }
never@297 2969
never@297 2970 void Assembler::fdiva(int i) {
never@297 2971 emit_farith(0xDC, 0xF8, i);
never@297 2972 }
never@297 2973
never@297 2974 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
never@297 2975 // is erroneous for some of the floating-point instructions below.
never@297 2976
never@297 2977 void Assembler::fdivp(int i) {
never@297 2978 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
never@297 2979 }
never@297 2980
never@297 2981 void Assembler::fdivr(int i) {
never@297 2982 emit_farith(0xD8, 0xF8, i);
never@297 2983 }
never@297 2984
never@297 2985 void Assembler::fdivr_d(Address src) {
never@297 2986 InstructionMark im(this);
never@297 2987 emit_byte(0xDC);
never@297 2988 emit_operand32(rdi, src);
never@297 2989 }
never@297 2990
never@297 2991 void Assembler::fdivr_s(Address src) {
never@297 2992 InstructionMark im(this);
never@297 2993 emit_byte(0xD8);
never@297 2994 emit_operand32(rdi, src);
never@297 2995 }
never@297 2996
never@297 2997 void Assembler::fdivra(int i) {
never@297 2998 emit_farith(0xDC, 0xF0, i);
never@297 2999 }
never@297 3000
never@297 3001 void Assembler::fdivrp(int i) {
never@297 3002 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
never@297 3003 }
never@297 3004
never@297 3005 void Assembler::ffree(int i) {
never@297 3006 emit_farith(0xDD, 0xC0, i);
never@297 3007 }
never@297 3008
never@297 3009 void Assembler::fild_d(Address adr) {
never@297 3010 InstructionMark im(this);
never@297 3011 emit_byte(0xDF);
never@297 3012 emit_operand32(rbp, adr);
never@297 3013 }
never@297 3014
never@297 3015 void Assembler::fild_s(Address adr) {
never@297 3016 InstructionMark im(this);
never@297 3017 emit_byte(0xDB);
never@297 3018 emit_operand32(rax, adr);
never@297 3019 }
never@297 3020
never@297 3021 void Assembler::fincstp() {
never@297 3022 emit_byte(0xD9);
never@297 3023 emit_byte(0xF7);
never@297 3024 }
never@297 3025
never@297 3026 void Assembler::finit() {
never@297 3027 emit_byte(0x9B);
never@297 3028 emit_byte(0xDB);
never@297 3029 emit_byte(0xE3);
never@297 3030 }
never@297 3031
never@297 3032 void Assembler::fist_s(Address adr) {
never@297 3033 InstructionMark im(this);
never@297 3034 emit_byte(0xDB);
never@297 3035 emit_operand32(rdx, adr);
never@297 3036 }
never@297 3037
never@297 3038 void Assembler::fistp_d(Address adr) {
never@297 3039 InstructionMark im(this);
never@297 3040 emit_byte(0xDF);
never@297 3041 emit_operand32(rdi, adr);
never@297 3042 }
never@297 3043
never@297 3044 void Assembler::fistp_s(Address adr) {
never@297 3045 InstructionMark im(this);
never@297 3046 emit_byte(0xDB);
never@297 3047 emit_operand32(rbx, adr);
never@297 3048 }
duke@0 3049
duke@0 3050 void Assembler::fld1() {
duke@0 3051 emit_byte(0xD9);
duke@0 3052 emit_byte(0xE8);
duke@0 3053 }
duke@0 3054
never@297 3055 void Assembler::fld_d(Address adr) {
never@297 3056 InstructionMark im(this);
never@297 3057 emit_byte(0xDD);
never@297 3058 emit_operand32(rax, adr);
never@297 3059 }
never@297 3060
never@297 3061 void Assembler::fld_s(Address adr) {
never@297 3062 InstructionMark im(this);
never@297 3063 emit_byte(0xD9);
never@297 3064 emit_operand32(rax, adr);
never@297 3065 }
never@297 3066
never@297 3067
never@297 3068 void Assembler::fld_s(int index) {
never@297 3069 emit_farith(0xD9, 0xC0, index);
never@297 3070 }
never@297 3071
never@297 3072 void Assembler::fld_x(Address adr) {
never@297 3073 InstructionMark im(this);
never@297 3074 emit_byte(0xDB);
never@297 3075 emit_operand32(rbp, adr);
never@297 3076 }
never@297 3077
never@297 3078 void Assembler::fldcw(Address src) {
never@297 3079 InstructionMark im(this);
never@297 3080 emit_byte(0xd9);
never@297 3081 emit_operand32(rbp, src);
never@297 3082 }
never@297 3083
never@297 3084 void Assembler::fldenv(Address src) {
never@297 3085 InstructionMark im(this);
never@297 3086 emit_byte(0xD9);
never@297 3087 emit_operand32(rsp, src);
never@297 3088 }
never@297 3089
never@297 3090 void Assembler::fldlg2() {
never@297 3091 emit_byte(0xD9);
never@297 3092 emit_byte(0xEC);
never@297 3093 }
never@297 3094
never@297 3095 void Assembler::fldln2() {
never@297 3096 emit_byte(0xD9);
never@297 3097 emit_byte(0xED);
never@297 3098 }
duke@0 3099
duke@0 3100 void Assembler::fldz() {
duke@0 3101 emit_byte(0xD9);
duke@0 3102 emit_byte(0xEE);
duke@0 3103 }
duke@0 3104
duke@0 3105 void Assembler::flog() {
duke@0 3106 fldln2();
duke@0 3107 fxch();
duke@0 3108 fyl2x();
duke@0 3109 }
duke@0 3110
duke@0 3111 void Assembler::flog10() {
duke@0 3112 fldlg2();
duke@0 3113 fxch();
duke@0 3114 fyl2x();
duke@0 3115 }
duke@0 3116
never@297 3117 void Assembler::fmul(int i) {
never@297 3118 emit_farith(0xD8, 0xC8, i);
never@297 3119 }
never@297 3120
never@297 3121 void Assembler::fmul_d(Address src) {
never@297 3122 InstructionMark im(this);
never@297 3123 emit_byte(0xDC);
never@297 3124 emit_operand32(rcx, src);
never@297 3125 }
never@297 3126
never@297 3127 void Assembler::fmul_s(Address src) {
never@297 3128 InstructionMark im(this);
never@297 3129 emit_byte(0xD8);
never@297 3130 emit_operand32(rcx, src);
never@297 3131 }
never@297 3132
never@297 3133 void Assembler::fmula(int i) {
never@297 3134 emit_farith(0xDC, 0xC8, i);
never@297 3135 }
never@297 3136
never@297 3137 void Assembler::fmulp(int i) {
never@297 3138 emit_farith(0xDE, 0xC8, i);
never@297 3139 }
never@297 3140
never@297 3141 void Assembler::fnsave(Address dst) {
never@297 3142 InstructionMark im(this);
never@297 3143 emit_byte(0xDD);
never@297 3144 emit_operand32(rsi, dst);
never@297 3145 }
never@297 3146
never@297 3147 void Assembler::fnstcw(Address src) {
never@297 3148 InstructionMark im(this);
never@297 3149 emit_byte(0x9B);
never@297 3150 emit_byte(0xD9);
never@297 3151 emit_operand32(rdi, src);
never@297 3152 }
never@297 3153
never@297 3154 void Assembler::fnstsw_ax() {
never@297 3155 emit_byte(0xdF);
never@297 3156 emit_byte(0xE0);
never@297 3157 }
never@297 3158
never@297 3159 void Assembler::fprem() {
never@297 3160 emit_byte(0xD9);
never@297 3161 emit_byte(0xF8);
never@297 3162 }
never@297 3163
never@297 3164 void Assembler::fprem1() {
never@297 3165 emit_byte(0xD9);
never@297 3166 emit_byte(0xF5);
never@297 3167 }
never@297 3168
never@297 3169 void Assembler::frstor(Address src) {
never@297 3170 InstructionMark im(this);
never@297 3171 emit_byte(0xDD);
never@297 3172 emit_operand32(rsp, src);
never@297 3173 }
duke@0 3174
duke@0 3175 void Assembler::fsin() {
duke@0 3176 emit_byte(0xD9);
duke@0 3177 emit_byte(0xFE);
duke@0 3178 }
duke@0 3179
never@297 3180 void Assembler::fsqrt() {
duke@0 3181 emit_byte(0xD9);
never@297 3182 emit_byte(0xFA);
never@297 3183 }
never@297 3184
never@297 3185 void Assembler::fst_d(Address adr) {
never@297 3186 InstructionMark im(this);
never@297 3187 emit_byte(0xDD);
never@297 3188 emit_operand32(rdx, adr);
never@297 3189 }
never@297 3190
never@297 3191 void Assembler::fst_s(Address adr) {
never@297 3192 InstructionMark im(this);
never@297 3193 emit_byte(0xD9);
never@297 3194 emit_operand32(rdx, adr);
never@297 3195 }
never@297 3196
never@297 3197 void Assembler::fstp_d(Address adr) {
never@297 3198 InstructionMark im(this);
never@297 3199 emit_byte(0xDD);
never@297 3200 emit_operand32(rbx, adr);
never@297 3201 }
never@297 3202
never@297 3203 void Assembler::fstp_d(int index) {
never@297 3204 emit_farith(0xDD, 0xD8, index);
never@297 3205 }
never@297 3206
never@297 3207 void Assembler::fstp_s(Address adr) {
never@297 3208 InstructionMark im(this);
never@297 3209 emit_byte(0xD9);
never@297 3210 emit_operand32(rbx, adr);
never@297 3211 }
never@297 3212
never@297 3213 void Assembler::fstp_x(Address adr) {
never@297 3214 InstructionMark im(this);
never@297 3215 emit_byte(0xDB);
never@297 3216 emit_operand32(rdi, adr);
never@297 3217 }
never@297 3218
never@297 3219 void Assembler::fsub(int i) {
never@297 3220 emit_farith(0xD8, 0xE0, i);
never@297 3221 }
never@297 3222
never@297 3223 void Assembler::fsub_d(Address src) {
never@297 3224 InstructionMark im(this);
never@297 3225 emit_byte(0xDC);
never@297 3226 emit_operand32(rsp, src);
never@297 3227 }
never@297 3228
never@297 3229 void Assembler::fsub_s(Address src) {
never@297 3230 InstructionMark im(this);
never@297 3231 emit_byte(0xD8);
never@297 3232 emit_operand32(rsp, src);
never@297 3233 }
never@297 3234
never@297 3235 void Assembler::fsuba(int i) {
never@297 3236 emit_farith(0xDC, 0xE8, i);
never@297 3237 }
never@297 3238
never@297 3239 void Assembler::fsubp(int i) {
never@297 3240 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
never@297 3241 }
never@297 3242
never@297 3243 void Assembler::fsubr(int i) {
never@297 3244 emit_farith(0xD8, 0xE8, i);
never@297 3245 }
never@297 3246
never@297 3247 void Assembler::fsubr_d(Address src) {
never@297 3248 InstructionMark im(this);
never@297 3249 emit_byte(0xDC);
never@297 3250 emit_operand32(rbp, src);
never@297 3251 }
never@297 3252
never@297 3253 void Assembler::fsubr_s(Address src) {
never@297 3254 InstructionMark im(this);
never@297 3255 emit_byte(0xD8);
never@297 3256 emit_operand32(rbp, src);
never@297 3257 }
never@297 3258
never@297 3259 void Assembler::fsubra(int i) {
never@297 3260 emit_farith(0xDC, 0xE0, i);
never@297 3261 }
never@297 3262
never@297 3263 void Assembler::fsubrp(int i) {
never@297 3264 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
duke@0 3265 }
duke@0 3266
duke@0 3267 void Assembler::ftan() {
duke@0 3268 emit_byte(0xD9);
duke@0 3269 emit_byte(0xF2);
duke@0 3270 emit_byte(0xDD);
duke@0 3271 emit_byte(0xD8);
duke@0 3272 }
duke@0 3273
never@297 3274 void Assembler::ftst() {
duke@0 3275 emit_byte(0xD9);
never@297 3276 emit_byte(0xE4);
never@297 3277 }
duke@0 3278
duke@0 3279 void Assembler::fucomi(int i) {
duke@0 3280 // make sure the instruction is supported (introduced for P6, together with cmov)
duke@0 3281 guarantee(VM_Version::supports_cmov(), "illegal instruction");
duke@0 3282 emit_farith(0xDB, 0xE8, i);
duke@0 3283 }
duke@0 3284
duke@0 3285 void Assembler::fucomip(int i) {
duke@0 3286 // make sure the instruction is supported (introduced for P6, together with cmov)
duke@0 3287 guarantee(VM_Version::supports_cmov(), "illegal instruction");
duke@0 3288 emit_farith(0xDF, 0xE8, i);
duke@0 3289 }
duke@0 3290
duke@0 3291 void Assembler::fwait() {
duke@0 3292 emit_byte(0x9B);
duke@0 3293 }
duke@0 3294
never@297 3295 void Assembler::fxch(int i) {
never@297 3296 emit_farith(0xD9, 0xC8, i);
never@297 3297 }
never@297 3298
never@297 3299 void Assembler::fyl2x() {
duke@0 3300 emit_byte(0xD9);
never@297 3301 emit_byte(0xF1);
never@297 3302 }
never@297 3303
never@297 3304
never@297 3305 #ifndef _LP64
never@297 3306
never@297 3307 void Assembler::incl(Register dst) {
never@297 3308 // Don't use it directly. Use MacroAssembler::incrementl() instead.
never@297 3309 emit_byte(0x40 | dst->encoding());
never@297 3310 }
never@297 3311
never@297 3312 void Assembler::lea(Register dst, Address src) {
never@297 3313 leal(dst, src);
never@297 3314 }
never@297 3315
never@297 3316 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
never@297 3317 InstructionMark im(this);
never@297 3318 emit_byte(0xC7);
never@297 3319 emit_operand(rax, dst);
never@297 3320 emit_data((int)imm32, rspec, 0);
never@297 3321 }
never@297 3322
kvn@619 3323 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
kvn@619 3324 InstructionMark im(this);
kvn@619 3325 int encode = prefix_and_encode(dst->encoding());
kvn@619 3326 emit_byte(0xB8 | encode);
kvn@619 3327 emit_data((int)imm32, rspec, 0);
kvn@619 3328 }
never@297 3329
never@297 3330 void Assembler::popa() { // 32bit
never@297 3331 emit_byte(0x61);
never@297 3332 }
never@297 3333
never@297 3334 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
never@297 3335 InstructionMark im(this);
never@297 3336 emit_byte(0x68);
never@297 3337 emit_data(imm32, rspec, 0);
never@297 3338 }
never@297 3339
never@297 3340 void Assembler::pusha() { // 32bit
never@297 3341 emit_byte(0x60);
never@297 3342 }
never@297 3343
never@297 3344 void Assembler::set_byte_if_not_zero(Register dst) {
duke@0 3345 emit_byte(0x0F);
never@297 3346 emit_byte(0x95);
never@297 3347 emit_byte(0xE0 | dst->encoding());
never@297 3348 }
never@297 3349
never@297 3350 void Assembler::shldl(Register dst, Register src) {
duke@0 3351 emit_byte(0x0F);
never@297 3352 emit_byte(0xA5);
never@297 3353 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
never@297 3354 }
never@297 3355
never@297 3356 void Assembler::shrdl(Register dst, Register src) {
duke@0 3357 emit_byte(0x0F);
never@297 3358 emit_byte(0xAD);
never@297 3359 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
never@297 3360 }
never@297 3361
never@297 3362 #else // LP64
never@297 3363
never@297 3364 // 64bit only pieces of the assembler
never@297 3365 // This should only be used by 64bit instructions that can use rip-relative
never@297 3366 // it cannot be used by instructions that want an immediate value.
never@297 3367
never@297 3368 bool Assembler::reachable(AddressLiteral adr) {
never@297 3369 int64_t disp;
never@297 3370 // None will force a 64bit literal to the code stream. Likely a placeholder
never@297 3371 // for something that will be patched later and we need to certain it will
never@297 3372 // always be reachable.
never@297 3373 if (adr.reloc() == relocInfo::none) {
never@297 3374 return false;
never@297 3375 }
never@297 3376 if (adr.reloc() == relocInfo::internal_word_type) {
never@297 3377 // This should be rip relative and easily reachable.
never@297 3378 return true;
never@297 3379 }
never@297 3380 if (adr.reloc() == relocInfo::virtual_call_type ||
never@297 3381 adr.reloc() == relocInfo::opt_virtual_call_type ||
never@297 3382 adr.reloc() == relocInfo::static_call_type ||
never@297 3383 adr.reloc() == relocInfo::static_stub_type ) {
never@297 3384 // This should be rip relative within the code cache and easily
never@297 3385 // reachable until we get huge code caches. (At which point
never@297 3386 // ic code is going to have issues).
never@297 3387 return true;
never@297 3388 }
never@297 3389 if (adr.reloc() != relocInfo::external_word_type &&
never@297 3390 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
never@297 3391 adr.reloc() != relocInfo::poll_type && // relocs to identify them
never@297 3392 adr.reloc() != relocInfo::runtime_call_type ) {
never@297 3393 return false;
never@297 3394 }
never@297 3395
never@297 3396 // Stress the correction code
never@297 3397 if (ForceUnreachable) {
never@297 3398 // Must be runtimecall reloc, see if it is in the codecache
never@297 3399 // Flipping stuff in the codecache to be unreachable causes issues
never@297 3400 // with things like inline caches where the additional instructions
never@297 3401 // are not handled.
never@297 3402 if (CodeCache::find_blob(adr._target) == NULL) {
never@297 3403 return false;
never@297 3404 }
never@297 3405 }
never@297 3406 // For external_word_type/runtime_call_type if it is reachable from where we
never@297 3407 // are now (possibly a temp buffer) and where we might end up
never@297 3408 // anywhere in the codeCache then we are always reachable.
never@297 3409 // This would have to change if we ever save/restore shared code
never@297 3410 // to be more pessimistic.
never@297 3411
never@297 3412 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
never@297 3413 if (!is_simm32(disp)) return false;
never@297 3414 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
never@297 3415 if (!is_simm32(disp)) return false;
never@297 3416
never@297 3417 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
never@297 3418
never@297 3419 // Because rip relative is a disp + address_of_next_instruction and we
never@297 3420 // don't know the value of address_of_next_instruction we apply a fudge factor
never@297 3421 // to make sure we will be ok no matter the size of the instruction we get placed into.
never@297 3422 // We don't have to fudge the checks above here because they are already worst case.
never@297 3423
never@297 3424 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
never@297 3425 // + 4 because better safe than sorry.
never@297 3426 const int fudge = 12 + 4;
never@297 3427 if (disp < 0) {
never@297 3428 disp -= fudge;
never@297 3429 } else {
never@297 3430 disp += fudge;
never@297 3431 }
never@297 3432 return is_simm32(disp);
never@297 3433 }
never@297 3434
never@297 3435 void Assembler::emit_data64(jlong data,
never@297 3436 relocInfo::relocType rtype,
never@297 3437 int format) {
never@297 3438 if (rtype == relocInfo::none) {
never@297 3439 emit_long64(data);
never@297 3440 } else {
never@297 3441 emit_data64(data, Relocation::spec_simple(rtype), format);
never@297 3442 }
never@297 3443 }
never@297 3444
never@297 3445 void Assembler::emit_data64(jlong data,
never@297 3446 RelocationHolder const& rspec,
never@297 3447 int format) {
never@297 3448 assert(imm_operand == 0, "default format must be immediate in this file");
never@297 3449 assert(imm_operand == format, "must be immediate");
never@297 3450 assert(inst_mark() != NULL, "must be inside InstructionMark");
never@297 3451 // Do not use AbstractAssembler::relocate, which is not intended for
never@297 3452 // embedded words. Instead, relocate to the enclosing instruction.
never@297 3453 code_section()->relocate(inst_mark(), rspec, format);
never@297 3454 #ifdef ASSERT
never@297 3455 check_relocation(rspec, format);
never@297 3456 #endif
never@297 3457 emit_long64(data);
never@297 3458 }
never@297 3459
never@297 3460 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
never@297 3461 if (reg_enc >= 8) {
never@297 3462 prefix(REX_B);
never@297 3463 reg_enc -= 8;