annotate src/cpu/x86/vm/assembler_x86.hpp @ 747:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents e5b0439ef4ae
children 62001a362ce9
rev   line source
duke@0 1 /*
twisti@603 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 class BiasedLockingCounters;
duke@0 26
duke@0 27 // Contains all the definitions needed for x86 assembly code generation.
duke@0 28
duke@0 29 // Calling convention
duke@0 30 class Argument VALUE_OBJ_CLASS_SPEC {
duke@0 31 public:
duke@0 32 enum {
duke@0 33 #ifdef _LP64
duke@0 34 #ifdef _WIN64
duke@0 35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
duke@0 36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
duke@0 37 #else
duke@0 38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
duke@0 39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
duke@0 40 #endif // _WIN64
duke@0 41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
duke@0 42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
duke@0 43 #else
duke@0 44 n_register_parameters = 0 // 0 registers used to pass arguments
duke@0 45 #endif // _LP64
duke@0 46 };
duke@0 47 };
duke@0 48
duke@0 49
duke@0 50 #ifdef _LP64
duke@0 51 // Symbolically name the register arguments used by the c calling convention.
duke@0 52 // Windows is different from linux/solaris. So much for standards...
duke@0 53
duke@0 54 #ifdef _WIN64
duke@0 55
duke@0 56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
duke@0 57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
duke@0 58 REGISTER_DECLARATION(Register, c_rarg2, r8);
duke@0 59 REGISTER_DECLARATION(Register, c_rarg3, r9);
duke@0 60
never@297 61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
never@297 62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
never@297 63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
never@297 64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
duke@0 65
duke@0 66 #else
duke@0 67
duke@0 68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
duke@0 69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
duke@0 70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
duke@0 71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
duke@0 72 REGISTER_DECLARATION(Register, c_rarg4, r8);
duke@0 73 REGISTER_DECLARATION(Register, c_rarg5, r9);
duke@0 74
never@297 75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
never@297 76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
never@297 77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
never@297 78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
never@297 79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
never@297 80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
never@297 81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
never@297 82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
duke@0 83
duke@0 84 #endif // _WIN64
duke@0 85
duke@0 86 // Symbolically name the register arguments used by the Java calling convention.
duke@0 87 // We have control over the convention for java so we can do what we please.
duke@0 88 // What pleases us is to offset the java calling convention so that when
duke@0 89 // we call a suitable jni method the arguments are lined up and we don't
duke@0 90 // have to do little shuffling. A suitable jni method is non-static and a
duke@0 91 // small number of arguments (two fewer args on windows)
duke@0 92 //
duke@0 93 // |-------------------------------------------------------|
duke@0 94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
duke@0 95 // |-------------------------------------------------------|
duke@0 96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
duke@0 97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
duke@0 98 // |-------------------------------------------------------|
duke@0 99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
duke@0 100 // |-------------------------------------------------------|
duke@0 101
duke@0 102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
duke@0 103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
duke@0 104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
duke@0 105 // Windows runs out of register args here
duke@0 106 #ifdef _WIN64
duke@0 107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
duke@0 108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
duke@0 109 #else
duke@0 110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
duke@0 111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
duke@0 112 #endif /* _WIN64 */
duke@0 113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
duke@0 114
never@297 115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
never@297 116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
never@297 117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
never@297 118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
never@297 119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
never@297 120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
never@297 121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
never@297 122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
duke@0 123
duke@0 124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
duke@0 125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
duke@0 126
never@297 127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
duke@0 128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
duke@0 129
never@297 130 #else
never@297 131 // rscratch1 will apear in 32bit code that is dead but of course must compile
never@297 132 // Using noreg ensures if the dead code is incorrectly live and executed it
never@297 133 // will cause an assertion failure
never@297 134 #define rscratch1 noreg
never@297 135
duke@0 136 #endif // _LP64
duke@0 137
duke@0 138 // Address is an abstraction used to represent a memory location
duke@0 139 // using any of the amd64 addressing modes with one object.
duke@0 140 //
duke@0 141 // Note: A register location is represented via a Register, not
duke@0 142 // via an address for efficiency & simplicity reasons.
duke@0 143
duke@0 144 class ArrayAddress;
duke@0 145
duke@0 146 class Address VALUE_OBJ_CLASS_SPEC {
duke@0 147 public:
duke@0 148 enum ScaleFactor {
duke@0 149 no_scale = -1,
duke@0 150 times_1 = 0,
duke@0 151 times_2 = 1,
duke@0 152 times_4 = 2,
never@297 153 times_8 = 3,
never@297 154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
duke@0 155 };
jrose@601 156 static ScaleFactor times(int size) {
jrose@601 157 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
jrose@601 158 if (size == 8) return times_8;
jrose@601 159 if (size == 4) return times_4;
jrose@601 160 if (size == 2) return times_2;
jrose@601 161 return times_1;
jrose@601 162 }
jrose@601 163 static int scale_size(ScaleFactor scale) {
jrose@601 164 assert(scale != no_scale, "");
jrose@601 165 assert(((1 << (int)times_1) == 1 &&
jrose@601 166 (1 << (int)times_2) == 2 &&
jrose@601 167 (1 << (int)times_4) == 4 &&
jrose@601 168 (1 << (int)times_8) == 8), "");
jrose@601 169 return (1 << (int)scale);
jrose@601 170 }
duke@0 171
duke@0 172 private:
duke@0 173 Register _base;
duke@0 174 Register _index;
duke@0 175 ScaleFactor _scale;
duke@0 176 int _disp;
duke@0 177 RelocationHolder _rspec;
duke@0 178
never@297 179 // Easily misused constructors make them private
never@297 180 // %%% can we make these go away?
never@297 181 NOT_LP64(Address(address loc, RelocationHolder spec);)
never@297 182 Address(int disp, address loc, relocInfo::relocType rtype);
never@297 183 Address(int disp, address loc, RelocationHolder spec);
duke@0 184
duke@0 185 public:
never@297 186
never@297 187 int disp() { return _disp; }
duke@0 188 // creation
duke@0 189 Address()
duke@0 190 : _base(noreg),
duke@0 191 _index(noreg),
duke@0 192 _scale(no_scale),
duke@0 193 _disp(0) {
duke@0 194 }
duke@0 195
duke@0 196 // No default displacement otherwise Register can be implicitly
duke@0 197 // converted to 0(Register) which is quite a different animal.
duke@0 198
duke@0 199 Address(Register base, int disp)
duke@0 200 : _base(base),
duke@0 201 _index(noreg),
duke@0 202 _scale(no_scale),
duke@0 203 _disp(disp) {
duke@0 204 }
duke@0 205
duke@0 206 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
duke@0 207 : _base (base),
duke@0 208 _index(index),
duke@0 209 _scale(scale),
duke@0 210 _disp (disp) {
duke@0 211 assert(!index->is_valid() == (scale == Address::no_scale),
duke@0 212 "inconsistent address");
duke@0 213 }
duke@0 214
jrose@646 215 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
jrose@601 216 : _base (base),
jrose@601 217 _index(index.register_or_noreg()),
jrose@601 218 _scale(scale),
jrose@601 219 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
jrose@601 220 if (!index.is_register()) scale = Address::no_scale;
jrose@601 221 assert(!_index->is_valid() == (scale == Address::no_scale),
jrose@601 222 "inconsistent address");
jrose@601 223 }
jrose@601 224
jrose@601 225 Address plus_disp(int disp) const {
jrose@601 226 Address a = (*this);
jrose@601 227 a._disp += disp;
jrose@601 228 return a;
jrose@601 229 }
jrose@601 230
duke@0 231 // The following two overloads are used in connection with the
duke@0 232 // ByteSize type (see sizes.hpp). They simplify the use of
duke@0 233 // ByteSize'd arguments in assembly code. Note that their equivalent
duke@0 234 // for the optimized build are the member functions with int disp
duke@0 235 // argument since ByteSize is mapped to an int type in that case.
duke@0 236 //
duke@0 237 // Note: DO NOT introduce similar overloaded functions for WordSize
duke@0 238 // arguments as in the optimized mode, both ByteSize and WordSize
duke@0 239 // are mapped to the same type and thus the compiler cannot make a
duke@0 240 // distinction anymore (=> compiler errors).
duke@0 241
duke@0 242 #ifdef ASSERT
duke@0 243 Address(Register base, ByteSize disp)
duke@0 244 : _base(base),
duke@0 245 _index(noreg),
duke@0 246 _scale(no_scale),
duke@0 247 _disp(in_bytes(disp)) {
duke@0 248 }
duke@0 249
duke@0 250 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
duke@0 251 : _base(base),
duke@0 252 _index(index),
duke@0 253 _scale(scale),
duke@0 254 _disp(in_bytes(disp)) {
duke@0 255 assert(!index->is_valid() == (scale == Address::no_scale),
duke@0 256 "inconsistent address");
duke@0 257 }
jrose@601 258
jrose@646 259 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
jrose@601 260 : _base (base),
jrose@601 261 _index(index.register_or_noreg()),
jrose@601 262 _scale(scale),
jrose@601 263 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
jrose@601 264 if (!index.is_register()) scale = Address::no_scale;
jrose@601 265 assert(!_index->is_valid() == (scale == Address::no_scale),
jrose@601 266 "inconsistent address");
jrose@601 267 }
jrose@601 268
duke@0 269 #endif // ASSERT
duke@0 270
duke@0 271 // accessors
ysr@344 272 bool uses(Register reg) const { return _base == reg || _index == reg; }
ysr@344 273 Register base() const { return _base; }
ysr@344 274 Register index() const { return _index; }
ysr@344 275 ScaleFactor scale() const { return _scale; }
ysr@344 276 int disp() const { return _disp; }
duke@0 277
duke@0 278 // Convert the raw encoding form into the form expected by the constructor for
duke@0 279 // Address. An index of 4 (rsp) corresponds to having no index, so convert
duke@0 280 // that to noreg for the Address constructor.
twisti@603 281 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
duke@0 282
duke@0 283 static Address make_array(ArrayAddress);
duke@0 284
duke@0 285 private:
duke@0 286 bool base_needs_rex() const {
duke@0 287 return _base != noreg && _base->encoding() >= 8;
duke@0 288 }
duke@0 289
duke@0 290 bool index_needs_rex() const {
duke@0 291 return _index != noreg &&_index->encoding() >= 8;
duke@0 292 }
duke@0 293
duke@0 294 relocInfo::relocType reloc() const { return _rspec.type(); }
duke@0 295
duke@0 296 friend class Assembler;
duke@0 297 friend class MacroAssembler;
duke@0 298 friend class LIR_Assembler; // base/index/scale/disp
duke@0 299 };
duke@0 300
duke@0 301 //
duke@0 302 // AddressLiteral has been split out from Address because operands of this type
duke@0 303 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
duke@0 304 // the few instructions that need to deal with address literals are unique and the
duke@0 305 // MacroAssembler does not have to implement every instruction in the Assembler
duke@0 306 // in order to search for address literals that may need special handling depending
duke@0 307 // on the instruction and the platform. As small step on the way to merging i486/amd64
duke@0 308 // directories.
duke@0 309 //
duke@0 310 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
duke@0 311 friend class ArrayAddress;
duke@0 312 RelocationHolder _rspec;
duke@0 313 // Typically we use AddressLiterals we want to use their rval
duke@0 314 // However in some situations we want the lval (effect address) of the item.
duke@0 315 // We provide a special factory for making those lvals.
duke@0 316 bool _is_lval;
duke@0 317
duke@0 318 // If the target is far we'll need to load the ea of this to
duke@0 319 // a register to reach it. Otherwise if near we can do rip
duke@0 320 // relative addressing.
duke@0 321
duke@0 322 address _target;
duke@0 323
duke@0 324 protected:
duke@0 325 // creation
duke@0 326 AddressLiteral()
duke@0 327 : _is_lval(false),
duke@0 328 _target(NULL)
duke@0 329 {}
duke@0 330
duke@0 331 public:
duke@0 332
duke@0 333
duke@0 334 AddressLiteral(address target, relocInfo::relocType rtype);
duke@0 335
duke@0 336 AddressLiteral(address target, RelocationHolder const& rspec)
duke@0 337 : _rspec(rspec),
duke@0 338 _is_lval(false),
duke@0 339 _target(target)
duke@0 340 {}
duke@0 341
duke@0 342 AddressLiteral addr() {
duke@0 343 AddressLiteral ret = *this;
duke@0 344 ret._is_lval = true;
duke@0 345 return ret;
duke@0 346 }
duke@0 347
duke@0 348
duke@0 349 private:
duke@0 350
duke@0 351 address target() { return _target; }
duke@0 352 bool is_lval() { return _is_lval; }
duke@0 353
duke@0 354 relocInfo::relocType reloc() const { return _rspec.type(); }
duke@0 355 const RelocationHolder& rspec() const { return _rspec; }
duke@0 356
duke@0 357 friend class Assembler;
duke@0 358 friend class MacroAssembler;
duke@0 359 friend class Address;
duke@0 360 friend class LIR_Assembler;
duke@0 361 };
duke@0 362
duke@0 363 // Convience classes
duke@0 364 class RuntimeAddress: public AddressLiteral {
duke@0 365
duke@0 366 public:
duke@0 367
duke@0 368 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
duke@0 369
duke@0 370 };
duke@0 371
duke@0 372 class OopAddress: public AddressLiteral {
duke@0 373
duke@0 374 public:
duke@0 375
duke@0 376 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
duke@0 377
duke@0 378 };
duke@0 379
duke@0 380 class ExternalAddress: public AddressLiteral {
duke@0 381
duke@0 382 public:
duke@0 383
duke@0 384 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
duke@0 385
duke@0 386 };
duke@0 387
duke@0 388 class InternalAddress: public AddressLiteral {
duke@0 389
duke@0 390 public:
duke@0 391
duke@0 392 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
duke@0 393
duke@0 394 };
duke@0 395
duke@0 396 // x86 can do array addressing as a single operation since disp can be an absolute
duke@0 397 // address amd64 can't. We create a class that expresses the concept but does extra
duke@0 398 // magic on amd64 to get the final result
duke@0 399
duke@0 400 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
duke@0 401 private:
duke@0 402
duke@0 403 AddressLiteral _base;
duke@0 404 Address _index;
duke@0 405
duke@0 406 public:
duke@0 407
duke@0 408 ArrayAddress() {};
duke@0 409 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
duke@0 410 AddressLiteral base() { return _base; }
duke@0 411 Address index() { return _index; }
duke@0 412
duke@0 413 };
duke@0 414
never@297 415 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
duke@0 416
duke@0 417 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
duke@0 418 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
duke@0 419 // is what you get. The Assembler is generating code into a CodeBuffer.
duke@0 420
duke@0 421 class Assembler : public AbstractAssembler {
duke@0 422 friend class AbstractAssembler; // for the non-virtual hack
duke@0 423 friend class LIR_Assembler; // as_Address()
never@297 424 friend class StubGenerator;
duke@0 425
duke@0 426 public:
duke@0 427 enum Condition { // The x86 condition codes used for conditional jumps/moves.
duke@0 428 zero = 0x4,
duke@0 429 notZero = 0x5,
duke@0 430 equal = 0x4,
duke@0 431 notEqual = 0x5,
duke@0 432 less = 0xc,
duke@0 433 lessEqual = 0xe,
duke@0 434 greater = 0xf,
duke@0 435 greaterEqual = 0xd,
duke@0 436 below = 0x2,
duke@0 437 belowEqual = 0x6,
duke@0 438 above = 0x7,
duke@0 439 aboveEqual = 0x3,
duke@0 440 overflow = 0x0,
duke@0 441 noOverflow = 0x1,
duke@0 442 carrySet = 0x2,
duke@0 443 carryClear = 0x3,
duke@0 444 negative = 0x8,
duke@0 445 positive = 0x9,
duke@0 446 parity = 0xa,
duke@0 447 noParity = 0xb
duke@0 448 };
duke@0 449
duke@0 450 enum Prefix {
duke@0 451 // segment overrides
duke@0 452 CS_segment = 0x2e,
duke@0 453 SS_segment = 0x36,
duke@0 454 DS_segment = 0x3e,
duke@0 455 ES_segment = 0x26,
duke@0 456 FS_segment = 0x64,
duke@0 457 GS_segment = 0x65,
duke@0 458
duke@0 459 REX = 0x40,
duke@0 460
duke@0 461 REX_B = 0x41,
duke@0 462 REX_X = 0x42,
duke@0 463 REX_XB = 0x43,
duke@0 464 REX_R = 0x44,
duke@0 465 REX_RB = 0x45,
duke@0 466 REX_RX = 0x46,
duke@0 467 REX_RXB = 0x47,
duke@0 468
duke@0 469 REX_W = 0x48,
duke@0 470
duke@0 471 REX_WB = 0x49,
duke@0 472 REX_WX = 0x4A,
duke@0 473 REX_WXB = 0x4B,
duke@0 474 REX_WR = 0x4C,
duke@0 475 REX_WRB = 0x4D,
duke@0 476 REX_WRX = 0x4E,
duke@0 477 REX_WRXB = 0x4F
duke@0 478 };
duke@0 479
duke@0 480 enum WhichOperand {
duke@0 481 // input to locate_operand, and format code for relocations
never@297 482 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
duke@0 483 disp32_operand = 1, // embedded 32-bit displacement or address
duke@0 484 call32_operand = 2, // embedded 32-bit self-relative displacement
never@297 485 #ifndef _LP64
duke@0 486 _WhichOperand_limit = 3
never@297 487 #else
never@297 488 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
never@297 489 _WhichOperand_limit = 4
never@297 490 #endif
duke@0 491 };
duke@0 492
never@297 493
never@297 494
never@297 495 // NOTE: The general philopsophy of the declarations here is that 64bit versions
never@297 496 // of instructions are freely declared without the need for wrapping them an ifdef.
never@297 497 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
never@297 498 // In the .cpp file the implementations are wrapped so that they are dropped out
never@297 499 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
never@297 500 // to the size it was prior to merging up the 32bit and 64bit assemblers.
never@297 501 //
never@297 502 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
never@297 503 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
never@297 504
never@297 505 private:
never@297 506
never@297 507
never@297 508 // 64bit prefixes
never@297 509 int prefix_and_encode(int reg_enc, bool byteinst = false);
never@297 510 int prefixq_and_encode(int reg_enc);
never@297 511
never@297 512 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
never@297 513 int prefixq_and_encode(int dst_enc, int src_enc);
never@297 514
never@297 515 void prefix(Register reg);
never@297 516 void prefix(Address adr);
never@297 517 void prefixq(Address adr);
never@297 518
never@297 519 void prefix(Address adr, Register reg, bool byteinst = false);
never@297 520 void prefixq(Address adr, Register reg);
never@297 521
never@297 522 void prefix(Address adr, XMMRegister reg);
never@297 523
never@297 524 void prefetch_prefix(Address src);
never@297 525
never@297 526 // Helper functions for groups of instructions
never@297 527 void emit_arith_b(int op1, int op2, Register dst, int imm8);
never@297 528
never@297 529 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
never@297 530 // only 32bit??
never@297 531 void emit_arith(int op1, int op2, Register dst, jobject obj);
never@297 532 void emit_arith(int op1, int op2, Register dst, Register src);
never@297 533
never@297 534 void emit_operand(Register reg,
never@297 535 Register base, Register index, Address::ScaleFactor scale,
never@297 536 int disp,
never@297 537 RelocationHolder const& rspec,
never@297 538 int rip_relative_correction = 0);
never@297 539
never@297 540 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
never@297 541
never@297 542 // operands that only take the original 32bit registers
never@297 543 void emit_operand32(Register reg, Address adr);
never@297 544
never@297 545 void emit_operand(XMMRegister reg,
never@297 546 Register base, Register index, Address::ScaleFactor scale,
never@297 547 int disp,
never@297 548 RelocationHolder const& rspec);
never@297 549
never@297 550 void emit_operand(XMMRegister reg, Address adr);
never@297 551
never@297 552 void emit_operand(MMXRegister reg, Address adr);
never@297 553
never@297 554 // workaround gcc (3.2.1-7) bug
never@297 555 void emit_operand(Address adr, MMXRegister reg);
never@297 556
never@297 557
never@297 558 // Immediate-to-memory forms
never@297 559 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
never@297 560
never@297 561 void emit_farith(int b1, int b2, int i);
never@297 562
duke@0 563
duke@0 564 protected:
never@297 565 #ifdef ASSERT
never@297 566 void check_relocation(RelocationHolder const& rspec, int format);
never@297 567 #endif
never@297 568
never@297 569 inline void emit_long64(jlong x);
never@297 570
never@297 571 void emit_data(jint data, relocInfo::relocType rtype, int format);
never@297 572 void emit_data(jint data, RelocationHolder const& rspec, int format);
never@297 573 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
never@297 574 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
never@297 575
never@297 576
never@297 577 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
never@297 578
never@297 579 // These are all easily abused and hence protected
never@297 580
never@297 581 // 32BIT ONLY SECTION
never@297 582 #ifndef _LP64
never@297 583 // Make these disappear in 64bit mode since they would never be correct
never@297 584 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@297 585 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@297 586
kvn@619 587 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@297 588 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@297 589
never@297 590 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
never@297 591 #else
never@297 592 // 64BIT ONLY SECTION
never@297 593 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
kvn@619 594
kvn@619 595 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
kvn@619 596 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
kvn@619 597
kvn@619 598 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
kvn@619 599 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
never@297 600 #endif // _LP64
never@297 601
never@297 602 // These are unique in that we are ensured by the caller that the 32bit
never@297 603 // relative in these instructions will always be able to reach the potentially
never@297 604 // 64bit address described by entry. Since they can take a 64bit address they
never@297 605 // don't have the 32 suffix like the other instructions in this class.
never@297 606
never@297 607 void call_literal(address entry, RelocationHolder const& rspec);
never@297 608 void jmp_literal(address entry, RelocationHolder const& rspec);
never@297 609
never@297 610 // Avoid using directly section
never@297 611 // Instructions in this section are actually usable by anyone without danger
never@297 612 // of failure but have performance issues that are addressed my enhanced
never@297 613 // instructions which will do the proper thing base on the particular cpu.
never@297 614 // We protect them because we don't trust you...
never@297 615
duke@0 616 // Don't use next inc() and dec() methods directly. INC & DEC instructions
duke@0 617 // could cause a partial flag stall since they don't set CF flag.
duke@0 618 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
duke@0 619 // which call inc() & dec() or add() & sub() in accordance with
duke@0 620 // the product flag UseIncDec value.
duke@0 621
duke@0 622 void decl(Register dst);
duke@0 623 void decl(Address dst);
never@297 624 void decq(Register dst);
never@297 625 void decq(Address dst);
duke@0 626
duke@0 627 void incl(Register dst);
duke@0 628 void incl(Address dst);
never@297 629 void incq(Register dst);
never@297 630 void incq(Address dst);
never@297 631
never@297 632 // New cpus require use of movsd and movss to avoid partial register stall
never@297 633 // when loading from memory. But for old Opteron use movlpd instead of movsd.
never@297 634 // The selection is done in MacroAssembler::movdbl() and movflt().
never@297 635
never@297 636 // Move Scalar Single-Precision Floating-Point Values
never@297 637 void movss(XMMRegister dst, Address src);
never@297 638 void movss(XMMRegister dst, XMMRegister src);
never@297 639 void movss(Address dst, XMMRegister src);
never@297 640
never@297 641 // Move Scalar Double-Precision Floating-Point Values
never@297 642 void movsd(XMMRegister dst, Address src);
never@297 643 void movsd(XMMRegister dst, XMMRegister src);
never@297 644 void movsd(Address dst, XMMRegister src);
never@297 645 void movlpd(XMMRegister dst, Address src);
never@297 646
never@297 647 // New cpus require use of movaps and movapd to avoid partial register stall
never@297 648 // when moving between registers.
never@297 649 void movaps(XMMRegister dst, XMMRegister src);
never@297 650 void movapd(XMMRegister dst, XMMRegister src);
never@297 651
never@297 652 // End avoid using directly
never@297 653
never@297 654
never@297 655 // Instruction prefixes
never@297 656 void prefix(Prefix p);
never@297 657
never@297 658 public:
never@297 659
never@297 660 // Creation
never@297 661 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
never@297 662
never@297 663 // Decoding
never@297 664 static address locate_operand(address inst, WhichOperand which);
never@297 665 static address locate_next_instruction(address inst);
never@297 666
never@297 667 // Utilities
never@297 668
never@297 669 #ifdef _LP64
never@297 670 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
never@297 671 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
never@297 672 #else
never@297 673 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
never@297 674 static bool is_simm32(int32_t x) { return true; }
never@297 675 #endif // LP64
never@297 676
never@297 677 // Generic instructions
never@297 678 // Does 32bit or 64bit as needed for the platform. In some sense these
never@297 679 // belong in macro assembler but there is no need for both varieties to exist
never@297 680
never@297 681 void lea(Register dst, Address src);
never@297 682
never@297 683 void mov(Register dst, Register src);
never@297 684
never@297 685 void pusha();
never@297 686 void popa();
never@297 687
never@297 688 void pushf();
never@297 689 void popf();
never@297 690
never@297 691 void push(int32_t imm32);
never@297 692
never@297 693 void push(Register src);
never@297 694
never@297 695 void pop(Register dst);
never@297 696
never@297 697 // These are dummies to prevent surprise implicit conversions to Register
never@297 698 void push(void* v);
never@297 699 void pop(void* v);
never@297 700
never@297 701
never@297 702 // These do register sized moves/scans
never@297 703 void rep_mov();
never@297 704 void rep_set();
never@297 705 void repne_scan();
never@297 706 #ifdef _LP64
never@297 707 void repne_scanl();
never@297 708 #endif
never@297 709
never@297 710 // Vanilla instructions in lexical order
never@297 711
never@297 712 void adcl(Register dst, int32_t imm32);
never@297 713 void adcl(Register dst, Address src);
never@297 714 void adcl(Register dst, Register src);
never@297 715
never@297 716 void adcq(Register dst, int32_t imm32);
never@297 717 void adcq(Register dst, Address src);
never@297 718 void adcq(Register dst, Register src);
never@297 719
never@297 720
never@297 721 void addl(Address dst, int32_t imm32);
never@297 722 void addl(Address dst, Register src);
never@297 723 void addl(Register dst, int32_t imm32);
never@297 724 void addl(Register dst, Address src);
never@297 725 void addl(Register dst, Register src);
never@297 726
never@297 727 void addq(Address dst, int32_t imm32);
never@297 728 void addq(Address dst, Register src);
never@297 729 void addq(Register dst, int32_t imm32);
never@297 730 void addq(Register dst, Address src);
never@297 731 void addq(Register dst, Register src);
never@297 732
never@297 733
duke@0 734 void addr_nop_4();
duke@0 735 void addr_nop_5();
duke@0 736 void addr_nop_7();
duke@0 737 void addr_nop_8();
duke@0 738
never@297 739 // Add Scalar Double-Precision Floating-Point Values
never@297 740 void addsd(XMMRegister dst, Address src);
never@297 741 void addsd(XMMRegister dst, XMMRegister src);
never@297 742
never@297 743 // Add Scalar Single-Precision Floating-Point Values
never@297 744 void addss(XMMRegister dst, Address src);
never@297 745 void addss(XMMRegister dst, XMMRegister src);
never@297 746
never@297 747 void andl(Register dst, int32_t imm32);
never@297 748 void andl(Register dst, Address src);
never@297 749 void andl(Register dst, Register src);
never@297 750
never@297 751 void andq(Register dst, int32_t imm32);
never@297 752 void andq(Register dst, Address src);
never@297 753 void andq(Register dst, Register src);
never@297 754
never@297 755
never@297 756 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
never@297 757 void andpd(XMMRegister dst, Address src);
never@297 758 void andpd(XMMRegister dst, XMMRegister src);
never@297 759
twisti@747 760 void bsfl(Register dst, Register src);
twisti@747 761 void bsrl(Register dst, Register src);
twisti@747 762
twisti@747 763 #ifdef _LP64
twisti@747 764 void bsfq(Register dst, Register src);
twisti@747 765 void bsrq(Register dst, Register src);
twisti@747 766 #endif
twisti@747 767
never@297 768 void bswapl(Register reg);
never@297 769
never@297 770 void bswapq(Register reg);
never@297 771
duke@0 772 void call(Label& L, relocInfo::relocType rtype);
duke@0 773 void call(Register reg); // push pc; pc <- reg
duke@0 774 void call(Address adr); // push pc; pc <- adr
duke@0 775
never@297 776 void cdql();
never@297 777
never@297 778 void cdqq();
never@297 779
never@297 780 void cld() { emit_byte(0xfc); }
never@297 781
never@297 782 void clflush(Address adr);
never@297 783
never@297 784 void cmovl(Condition cc, Register dst, Register src);
never@297 785 void cmovl(Condition cc, Register dst, Address src);
never@297 786
never@297 787 void cmovq(Condition cc, Register dst, Register src);
never@297 788 void cmovq(Condition cc, Register dst, Address src);
never@297 789
never@297 790
never@297 791 void cmpb(Address dst, int imm8);
never@297 792
never@297 793 void cmpl(Address dst, int32_t imm32);
never@297 794
never@297 795 void cmpl(Register dst, int32_t imm32);
never@297 796 void cmpl(Register dst, Register src);
never@297 797 void cmpl(Register dst, Address src);
never@297 798
never@297 799 void cmpq(Address dst, int32_t imm32);
never@297 800 void cmpq(Address dst, Register src);
never@297 801
never@297 802 void cmpq(Register dst, int32_t imm32);
never@297 803 void cmpq(Register dst, Register src);
never@297 804 void cmpq(Register dst, Address src);
never@297 805
never@297 806 // these are dummies used to catch attempting to convert NULL to Register
never@297 807 void cmpl(Register dst, void* junk); // dummy
never@297 808 void cmpq(Register dst, void* junk); // dummy
never@297 809
never@297 810 void cmpw(Address dst, int imm16);
never@297 811
never@297 812 void cmpxchg8 (Address adr);
never@297 813
never@297 814 void cmpxchgl(Register reg, Address adr);
never@297 815
never@297 816 void cmpxchgq(Register reg, Address adr);
never@297 817
never@297 818 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
never@297 819 void comisd(XMMRegister dst, Address src);
never@297 820
never@297 821 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
never@297 822 void comiss(XMMRegister dst, Address src);
never@297 823
never@297 824 // Identify processor type and features
never@297 825 void cpuid() {
never@297 826 emit_byte(0x0F);
never@297 827 emit_byte(0xA2);
never@297 828 }
never@297 829
never@297 830 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
never@297 831 void cvtsd2ss(XMMRegister dst, XMMRegister src);
never@297 832
never@297 833 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
never@297 834 void cvtsi2sdl(XMMRegister dst, Register src);
never@297 835 void cvtsi2sdq(XMMRegister dst, Register src);
never@297 836
never@297 837 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
never@297 838 void cvtsi2ssl(XMMRegister dst, Register src);
never@297 839 void cvtsi2ssq(XMMRegister dst, Register src);
never@297 840
never@297 841 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
never@297 842 void cvtdq2pd(XMMRegister dst, XMMRegister src);
never@297 843
never@297 844 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
never@297 845 void cvtdq2ps(XMMRegister dst, XMMRegister src);
never@297 846
never@297 847 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
never@297 848 void cvtss2sd(XMMRegister dst, XMMRegister src);
never@297 849
never@297 850 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
never@297 851 void cvttsd2sil(Register dst, Address src);
never@297 852 void cvttsd2sil(Register dst, XMMRegister src);
never@297 853 void cvttsd2siq(Register dst, XMMRegister src);
never@297 854
never@297 855 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
never@297 856 void cvttss2sil(Register dst, XMMRegister src);
never@297 857 void cvttss2siq(Register dst, XMMRegister src);
never@297 858
never@297 859 // Divide Scalar Double-Precision Floating-Point Values
never@297 860 void divsd(XMMRegister dst, Address src);
never@297 861 void divsd(XMMRegister dst, XMMRegister src);
never@297 862
never@297 863 // Divide Scalar Single-Precision Floating-Point Values
never@297 864 void divss(XMMRegister dst, Address src);
never@297 865 void divss(XMMRegister dst, XMMRegister src);
never@297 866
never@297 867 void emms();
never@297 868
never@297 869 void fabs();
never@297 870
never@297 871 void fadd(int i);
never@297 872
never@297 873 void fadd_d(Address src);
never@297 874 void fadd_s(Address src);
never@297 875
never@297 876 // "Alternate" versions of x87 instructions place result down in FPU
never@297 877 // stack instead of on TOS
never@297 878
never@297 879 void fadda(int i); // "alternate" fadd
never@297 880 void faddp(int i = 1);
never@297 881
never@297 882 void fchs();
never@297 883
never@297 884 void fcom(int i);
never@297 885
never@297 886 void fcomp(int i = 1);
never@297 887 void fcomp_d(Address src);
never@297 888 void fcomp_s(Address src);
never@297 889
never@297 890 void fcompp();
never@297 891
never@297 892 void fcos();
never@297 893
never@297 894 void fdecstp();
never@297 895
never@297 896 void fdiv(int i);
never@297 897 void fdiv_d(Address src);
never@297 898 void fdivr_s(Address src);
never@297 899 void fdiva(int i); // "alternate" fdiv
never@297 900 void fdivp(int i = 1);
never@297 901
never@297 902 void fdivr(int i);
never@297 903 void fdivr_d(Address src);
never@297 904 void fdiv_s(Address src);
never@297 905
never@297 906 void fdivra(int i); // "alternate" reversed fdiv
never@297 907
never@297 908 void fdivrp(int i = 1);
never@297 909
never@297 910 void ffree(int i = 0);
never@297 911
never@297 912 void fild_d(Address adr);
never@297 913 void fild_s(Address adr);
never@297 914
never@297 915 void fincstp();
never@297 916
never@297 917 void finit();
never@297 918
never@297 919 void fist_s (Address adr);
never@297 920 void fistp_d(Address adr);
never@297 921 void fistp_s(Address adr);
never@297 922
never@297 923 void fld1();
never@297 924
never@297 925 void fld_d(Address adr);
never@297 926 void fld_s(Address adr);
never@297 927 void fld_s(int index);
never@297 928 void fld_x(Address adr); // extended-precision (80-bit) format
never@297 929
never@297 930 void fldcw(Address src);
never@297 931
never@297 932 void fldenv(Address src);
never@297 933
never@297 934 void fldlg2();
never@297 935
never@297 936 void fldln2();
never@297 937
never@297 938 void fldz();
never@297 939
never@297 940 void flog();
never@297 941 void flog10();
never@297 942
never@297 943 void fmul(int i);
never@297 944
never@297 945 void fmul_d(Address src);
never@297 946 void fmul_s(Address src);
never@297 947
never@297 948 void fmula(int i); // "alternate" fmul
never@297 949
never@297 950 void fmulp(int i = 1);
never@297 951
never@297 952 void fnsave(Address dst);
never@297 953
never@297 954 void fnstcw(Address src);
never@297 955
never@297 956 void fnstsw_ax();
never@297 957
never@297 958 void fprem();
never@297 959 void fprem1();
never@297 960
never@297 961 void frstor(Address src);
never@297 962
never@297 963 void fsin();
never@297 964
never@297 965 void fsqrt();
never@297 966
never@297 967 void fst_d(Address adr);
never@297 968 void fst_s(Address adr);
never@297 969
never@297 970 void fstp_d(Address adr);
never@297 971 void fstp_d(int index);
never@297 972 void fstp_s(Address adr);
never@297 973 void fstp_x(Address adr); // extended-precision (80-bit) format
never@297 974
never@297 975 void fsub(int i);
never@297 976 void fsub_d(Address src);
never@297 977 void fsub_s(Address src);
never@297 978
never@297 979 void fsuba(int i); // "alternate" fsub
never@297 980
never@297 981 void fsubp(int i = 1);
never@297 982
never@297 983 void fsubr(int i);
never@297 984 void fsubr_d(Address src);
never@297 985 void fsubr_s(Address src);
never@297 986
never@297 987 void fsubra(int i); // "alternate" reversed fsub
never@297 988
never@297 989 void fsubrp(int i = 1);
never@297 990
never@297 991 void ftan();
never@297 992
never@297 993 void ftst();
never@297 994
never@297 995 void fucomi(int i = 1);
never@297 996 void fucomip(int i = 1);
never@297 997
never@297 998 void fwait();
never@297 999
never@297 1000 void fxch(int i = 1);
never@297 1001
never@297 1002 void fxrstor(Address src);
never@297 1003
never@297 1004 void fxsave(Address dst);
never@297 1005
never@297 1006 void fyl2x();
never@297 1007
never@297 1008 void hlt();
never@297 1009
never@297 1010 void idivl(Register src);
never@297 1011
never@297 1012 void idivq(Register src);
never@297 1013
never@297 1014 void imull(Register dst, Register src);
never@297 1015 void imull(Register dst, Register src, int value);
never@297 1016
never@297 1017 void imulq(Register dst, Register src);
never@297 1018 void imulq(Register dst, Register src, int value);
never@297 1019
duke@0 1020
duke@0 1021 // jcc is the generic conditional branch generator to run-
duke@0 1022 // time routines, jcc is used for branches to labels. jcc
duke@0 1023 // takes a branch opcode (cc) and a label (L) and generates
duke@0 1024 // either a backward branch or a forward branch and links it
duke@0 1025 // to the label fixup chain. Usage:
duke@0 1026 //
duke@0 1027 // Label L; // unbound label
duke@0 1028 // jcc(cc, L); // forward branch to unbound label
duke@0 1029 // bind(L); // bind label to the current pc
duke@0 1030 // jcc(cc, L); // backward branch to bound label
duke@0 1031 // bind(L); // illegal: a label may be bound only once
duke@0 1032 //
duke@0 1033 // Note: The same Label can be used for forward and backward branches
duke@0 1034 // but it may be bound only once.
duke@0 1035
duke@0 1036 void jcc(Condition cc, Label& L,
duke@0 1037 relocInfo::relocType rtype = relocInfo::none);
duke@0 1038
duke@0 1039 // Conditional jump to a 8-bit offset to L.
duke@0 1040 // WARNING: be very careful using this for forward jumps. If the label is
duke@0 1041 // not bound within an 8-bit offset of this instruction, a run-time error
duke@0 1042 // will occur.
duke@0 1043 void jccb(Condition cc, Label& L);
duke@0 1044
never@297 1045 void jmp(Address entry); // pc <- entry
never@297 1046
never@297 1047 // Label operations & relative jumps (PPUM Appendix D)
never@297 1048 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
never@297 1049
never@297 1050 void jmp(Register entry); // pc <- entry
never@297 1051
never@297 1052 // Unconditional 8-bit offset jump to L.
never@297 1053 // WARNING: be very careful using this for forward jumps. If the label is
never@297 1054 // not bound within an 8-bit offset of this instruction, a run-time error
never@297 1055 // will occur.
never@297 1056 void jmpb(Label& L);
never@297 1057
never@297 1058 void ldmxcsr( Address src );
never@297 1059
never@297 1060 void leal(Register dst, Address src);
never@297 1061
never@297 1062 void leaq(Register dst, Address src);
never@297 1063
never@297 1064 void lfence() {
never@297 1065 emit_byte(0x0F);
never@297 1066 emit_byte(0xAE);
never@297 1067 emit_byte(0xE8);
never@297 1068 }
never@297 1069
never@297 1070 void lock();
never@297 1071
twisti@747 1072 void lzcntl(Register dst, Register src);
twisti@747 1073
twisti@747 1074 #ifdef _LP64
twisti@747 1075 void lzcntq(Register dst, Register src);
twisti@747 1076 #endif
twisti@747 1077
never@297 1078 enum Membar_mask_bits {
never@297 1079 StoreStore = 1 << 3,
never@297 1080 LoadStore = 1 << 2,
never@297 1081 StoreLoad = 1 << 1,
never@297 1082 LoadLoad = 1 << 0
never@297 1083 };
never@297 1084
never@652 1085 // Serializes memory and blows flags
never@297 1086 void membar(Membar_mask_bits order_constraint) {
never@652 1087 if (os::is_MP()) {
never@652 1088 // We only have to handle StoreLoad
never@652 1089 if (order_constraint & StoreLoad) {
never@652 1090 // All usable chips support "locked" instructions which suffice
never@652 1091 // as barriers, and are much faster than the alternative of
never@652 1092 // using cpuid instruction. We use here a locked add [esp],0.
never@652 1093 // This is conveniently otherwise a no-op except for blowing
never@652 1094 // flags.
never@652 1095 // Any change to this code may need to revisit other places in
never@652 1096 // the code where this idiom is used, in particular the
never@652 1097 // orderAccess code.
never@652 1098 lock();
never@652 1099 addl(Address(rsp, 0), 0);// Assert the lock# signal here
never@652 1100 }
never@652 1101 }
never@297 1102 }
never@297 1103
never@297 1104 void mfence();
never@297 1105
never@297 1106 // Moves
never@297 1107
never@297 1108 void mov64(Register dst, int64_t imm64);
never@297 1109
never@297 1110 void movb(Address dst, Register src);
never@297 1111 void movb(Address dst, int imm8);
never@297 1112 void movb(Register dst, Address src);
never@297 1113
never@297 1114 void movdl(XMMRegister dst, Register src);
never@297 1115 void movdl(Register dst, XMMRegister src);
never@297 1116
never@297 1117 // Move Double Quadword
never@297 1118 void movdq(XMMRegister dst, Register src);
never@297 1119 void movdq(Register dst, XMMRegister src);
never@297 1120
never@297 1121 // Move Aligned Double Quadword
never@297 1122 void movdqa(Address dst, XMMRegister src);
never@297 1123 void movdqa(XMMRegister dst, Address src);
never@297 1124 void movdqa(XMMRegister dst, XMMRegister src);
never@297 1125
kvn@387 1126 // Move Unaligned Double Quadword
kvn@387 1127 void movdqu(Address dst, XMMRegister src);
kvn@387 1128 void movdqu(XMMRegister dst, Address src);
kvn@387 1129 void movdqu(XMMRegister dst, XMMRegister src);
kvn@387 1130
never@297 1131 void movl(Register dst, int32_t imm32);
never@297 1132 void movl(Address dst, int32_t imm32);
never@297 1133 void movl(Register dst, Register src);
never@297 1134 void movl(Register dst, Address src);
never@297 1135 void movl(Address dst, Register src);
never@297 1136
never@297 1137 // These dummies prevent using movl from converting a zero (like NULL) into Register
never@297 1138 // by giving the compiler two choices it can't resolve
never@297 1139
never@297 1140 void movl(Address dst, void* junk);
never@297 1141 void movl(Register dst, void* junk);
never@297 1142
never@297 1143 #ifdef _LP64
never@297 1144 void movq(Register dst, Register src);
never@297 1145 void movq(Register dst, Address src);
never@297 1146 void movq(Address dst, Register src);
never@297 1147 #endif
never@297 1148
never@297 1149 void movq(Address dst, MMXRegister src );
never@297 1150 void movq(MMXRegister dst, Address src );
never@297 1151
never@297 1152 #ifdef _LP64
never@297 1153 // These dummies prevent using movq from converting a zero (like NULL) into Register
never@297 1154 // by giving the compiler two choices it can't resolve
never@297 1155
never@297 1156 void movq(Address dst, void* dummy);
never@297 1157 void movq(Register dst, void* dummy);
never@297 1158 #endif
never@297 1159
never@297 1160 // Move Quadword
never@297 1161 void movq(Address dst, XMMRegister src);
never@297 1162 void movq(XMMRegister dst, Address src);
never@297 1163
never@297 1164 void movsbl(Register dst, Address src);
never@297 1165 void movsbl(Register dst, Register src);
never@297 1166
never@297 1167 #ifdef _LP64
twisti@603 1168 void movsbq(Register dst, Address src);
twisti@603 1169 void movsbq(Register dst, Register src);
twisti@603 1170
never@297 1171 // Move signed 32bit immediate to 64bit extending sign
never@297 1172 void movslq(Address dst, int32_t imm64);
never@297 1173 void movslq(Register dst, int32_t imm64);
never@297 1174
never@297 1175 void movslq(Register dst, Address src);
never@297 1176 void movslq(Register dst, Register src);
never@297 1177 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
never@297 1178 #endif
never@297 1179
never@297 1180 void movswl(Register dst, Address src);
never@297 1181 void movswl(Register dst, Register src);
never@297 1182
twisti@603 1183 #ifdef _LP64
twisti@603 1184 void movswq(Register dst, Address src);
twisti@603 1185 void movswq(Register dst, Register src);
twisti@603 1186 #endif
twisti@603 1187
never@297 1188 void movw(Address dst, int imm16);
never@297 1189 void movw(Register dst, Address src);
never@297 1190 void movw(Address dst, Register src);
never@297 1191
never@297 1192 void movzbl(Register dst, Address src);
never@297 1193 void movzbl(Register dst, Register src);
never@297 1194
twisti@603 1195 #ifdef _LP64
twisti@603 1196 void movzbq(Register dst, Address src);
twisti@603 1197 void movzbq(Register dst, Register src);
twisti@603 1198 #endif
twisti@603 1199
never@297 1200 void movzwl(Register dst, Address src);
never@297 1201 void movzwl(Register dst, Register src);
never@297 1202
twisti@603 1203 #ifdef _LP64
twisti@603 1204 void movzwq(Register dst, Address src);
twisti@603 1205 void movzwq(Register dst, Register src);
twisti@603 1206 #endif
twisti@603 1207
never@297 1208 void mull(Address src);
never@297 1209 void mull(Register src);
never@297 1210
never@297 1211 // Multiply Scalar Double-Precision Floating-Point Values
never@297 1212 void mulsd(XMMRegister dst, Address src);
never@297 1213 void mulsd(XMMRegister dst, XMMRegister src);
never@297 1214
never@297 1215 // Multiply Scalar Single-Precision Floating-Point Values
never@297 1216 void mulss(XMMRegister dst, Address src);
never@297 1217 void mulss(XMMRegister dst, XMMRegister src);
never@297 1218
never@297 1219 void negl(Register dst);
never@297 1220
never@297 1221 #ifdef _LP64
never@297 1222 void negq(Register dst);
never@297 1223 #endif
never@297 1224
never@297 1225 void nop(int i = 1);
never@297 1226
never@297 1227 void notl(Register dst);
never@297 1228
never@297 1229 #ifdef _LP64
never@297 1230 void notq(Register dst);
never@297 1231 #endif
never@297 1232
never@297 1233 void orl(Address dst, int32_t imm32);
never@297 1234 void orl(Register dst, int32_t imm32);
never@297 1235 void orl(Register dst, Address src);
never@297 1236 void orl(Register dst, Register src);
never@297 1237
never@297 1238 void orq(Address dst, int32_t imm32);
never@297 1239 void orq(Register dst, int32_t imm32);
never@297 1240 void orq(Register dst, Address src);
never@297 1241 void orq(Register dst, Register src);
never@297 1242
cfang@674 1243 // SSE4.2 string instructions
cfang@674 1244 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
cfang@674 1245 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
cfang@674 1246
never@297 1247 void popl(Address dst);
never@297 1248
never@297 1249 #ifdef _LP64
never@297 1250 void popq(Address dst);
never@297 1251 #endif
never@297 1252
twisti@620 1253 void popcntl(Register dst, Address src);
twisti@620 1254 void popcntl(Register dst, Register src);
twisti@620 1255
twisti@620 1256 #ifdef _LP64
twisti@620 1257 void popcntq(Register dst, Address src);
twisti@620 1258 void popcntq(Register dst, Register src);
twisti@620 1259 #endif
twisti@620 1260
never@297 1261 // Prefetches (SSE, SSE2, 3DNOW only)
never@297 1262
never@297 1263 void prefetchnta(Address src);
never@297 1264 void prefetchr(Address src);
never@297 1265 void prefetcht0(Address src);
never@297 1266 void prefetcht1(Address src);
never@297 1267 void prefetcht2(Address src);
never@297 1268 void prefetchw(Address src);
never@297 1269
never@297 1270 // Shuffle Packed Doublewords
never@297 1271 void pshufd(XMMRegister dst, XMMRegister src, int mode);
never@297 1272 void pshufd(XMMRegister dst, Address src, int mode);
never@297 1273
never@297 1274 // Shuffle Packed Low Words
never@297 1275 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
never@297 1276 void pshuflw(XMMRegister dst, Address src, int mode);
never@297 1277
never@297 1278 // Shift Right Logical Quadword Immediate
never@297 1279 void psrlq(XMMRegister dst, int shift);
never@297 1280
cfang@674 1281 // Logical Compare Double Quadword
cfang@674 1282 void ptest(XMMRegister dst, XMMRegister src);
cfang@674 1283 void ptest(XMMRegister dst, Address src);
cfang@674 1284
never@297 1285 // Interleave Low Bytes
never@297 1286 void punpcklbw(XMMRegister dst, XMMRegister src);
never@297 1287
never@297 1288 void pushl(Address src);
never@297 1289
never@297 1290 void pushq(Address src);
never@297 1291
never@297 1292 // Xor Packed Byte Integer Values
never@297 1293 void pxor(XMMRegister dst, Address src);
never@297 1294 void pxor(XMMRegister dst, XMMRegister src);
never@297 1295
never@297 1296 void rcll(Register dst, int imm8);
never@297 1297
never@297 1298 void rclq(Register dst, int imm8);
never@297 1299
never@297 1300 void ret(int imm16);
duke@0 1301
duke@0 1302 void sahf();
duke@0 1303
never@297 1304 void sarl(Register dst, int imm8);
never@297 1305 void sarl(Register dst);
never@297 1306
never@297 1307 void sarq(Register dst, int imm8);
never@297 1308 void sarq(Register dst);
never@297 1309
never@297 1310 void sbbl(Address dst, int32_t imm32);
never@297 1311 void sbbl(Register dst, int32_t imm32);
never@297 1312 void sbbl(Register dst, Address src);
never@297 1313 void sbbl(Register dst, Register src);
never@297 1314
never@297 1315 void sbbq(Address dst, int32_t imm32);
never@297 1316 void sbbq(Register dst, int32_t imm32);
never@297 1317 void sbbq(Register dst, Address src);
never@297 1318 void sbbq(Register dst, Register src);
never@297 1319
never@297 1320 void setb(Condition cc, Register dst);
never@297 1321
never@297 1322 void shldl(Register dst, Register src);
never@297 1323
never@297 1324 void shll(Register dst, int imm8);
never@297 1325 void shll(Register dst);
never@297 1326
never@297 1327 void shlq(Register dst, int imm8);
never@297 1328 void shlq(Register dst);
never@297 1329
never@297 1330 void shrdl(Register dst, Register src);
never@297 1331
never@297 1332 void shrl(Register dst, int imm8);
never@297 1333 void shrl(Register dst);
never@297 1334
never@297 1335 void shrq(Register dst, int imm8);
never@297 1336 void shrq(Register dst);
never@297 1337
never@297 1338 void smovl(); // QQQ generic?
never@297 1339
never@297 1340 // Compute Square Root of Scalar Double-Precision Floating-Point Value
never@297 1341 void sqrtsd(XMMRegister dst, Address src);
never@297 1342 void sqrtsd(XMMRegister dst, XMMRegister src);
never@297 1343
never@297 1344 void std() { emit_byte(0xfd); }
never@297 1345
never@297 1346 void stmxcsr( Address dst );
never@297 1347
never@297 1348 void subl(Address dst, int32_t imm32);
never@297 1349 void subl(Address dst, Register src);
never@297 1350 void subl(Register dst, int32_t imm32);
never@297 1351 void subl(Register dst, Address src);
never@297 1352 void subl(Register dst, Register src);
never@297 1353
never@297 1354 void subq(Address dst, int32_t imm32);
never@297 1355 void subq(Address dst, Register src);
never@297 1356 void subq(Register dst, int32_t imm32);
never@297 1357 void subq(Register dst, Address src);
never@297 1358 void subq(Register dst, Register src);
never@297 1359
never@297 1360
never@297 1361 // Subtract Scalar Double-Precision Floating-Point Values
never@297 1362 void subsd(XMMRegister dst, Address src);
never@297 1363 void subsd(XMMRegister dst, XMMRegister src);
never@297 1364
never@297 1365 // Subtract Scalar Single-Precision Floating-Point Values
never@297 1366 void subss(XMMRegister dst, Address src);
duke@0 1367 void subss(XMMRegister dst, XMMRegister src);
never@297 1368
never@297 1369 void testb(Register dst, int imm8);
never@297 1370
never@297 1371 void testl(Register dst, int32_t imm32);
never@297 1372 void testl(Register dst, Register src);
never@297 1373 void testl(Register dst, Address src);
never@297 1374
never@297 1375 void testq(Register dst, int32_t imm32);
never@297 1376 void testq(Register dst, Register src);
never@297 1377
never@297 1378
never@297 1379 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
never@297 1380 void ucomisd(XMMRegister dst, Address src);
never@297 1381 void ucomisd(XMMRegister dst, XMMRegister src);
never@297 1382
never@297 1383 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
never@297 1384 void ucomiss(XMMRegister dst, Address src);
duke@0 1385 void ucomiss(XMMRegister dst, XMMRegister src);
never@297 1386
never@297 1387 void xaddl(Address dst, Register src);
never@297 1388
never@297 1389 void xaddq(Address dst, Register src);
never@297 1390
never@297 1391 void xchgl(Register reg, Address adr);
never@297 1392 void xchgl(Register dst, Register src);
never@297 1393
never@297 1394 void xchgq(Register reg, Address adr);
never@297 1395 void xchgq(Register dst, Register src);
never@297 1396
never@297 1397 void xorl(Register dst, int32_t imm32);
never@297 1398 void xorl(Register dst, Address src);
never@297 1399 void xorl(Register dst, Register src);
never@297 1400
never@297 1401 void xorq(Register dst, Address src);
never@297 1402 void xorq(Register dst, Register src);
never@297 1403
never@297 1404 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
never@297 1405 void xorpd(XMMRegister dst, Address src);
never@297 1406 void xorpd(XMMRegister dst, XMMRegister src);
never@297 1407
never@297 1408 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
never@297 1409 void xorps(XMMRegister dst, Address src);
duke@0 1410 void xorps(XMMRegister dst, XMMRegister src);
never@297 1411
never@297 1412 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
duke@0 1413 };
duke@0 1414
duke@0 1415
duke@0 1416 // MacroAssembler extends Assembler by frequently used macros.
duke@0 1417 //
duke@0 1418 // Instructions for which a 'better' code sequence exists depending
duke@0 1419 // on arguments should also go in here.
duke@0 1420
duke@0 1421 class MacroAssembler: public Assembler {
ysr@344 1422 friend class LIR_Assembler;
ysr@344 1423 friend class Runtime1; // as_Address()
duke@0 1424 protected:
duke@0 1425
duke@0 1426 Address as_Address(AddressLiteral adr);
duke@0 1427 Address as_Address(ArrayAddress adr);
duke@0 1428
duke@0 1429 // Support for VM calls
duke@0 1430 //
duke@0 1431 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
duke@0 1432 // may customize this version by overriding it for its purposes (e.g., to save/restore
duke@0 1433 // additional registers when doing a VM call).
duke@0 1434 #ifdef CC_INTERP
duke@0 1435 // c++ interpreter never wants to use interp_masm version of call_VM
duke@0 1436 #define VIRTUAL
duke@0 1437 #else
duke@0 1438 #define VIRTUAL virtual
duke@0 1439 #endif
duke@0 1440
duke@0 1441 VIRTUAL void call_VM_leaf_base(
duke@0 1442 address entry_point, // the entry point
duke@0 1443 int number_of_arguments // the number of arguments to pop after the call
duke@0 1444 );
duke@0 1445
duke@0 1446 // This is the base routine called by the different versions of call_VM. The interpreter
duke@0 1447 // may customize this version by overriding it for its purposes (e.g., to save/restore
duke@0 1448 // additional registers when doing a VM call).
duke@0 1449 //
duke@0 1450 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
duke@0 1451 // returns the register which contains the thread upon return. If a thread register has been
duke@0 1452 // specified, the return value will correspond to that register. If no last_java_sp is specified
duke@0 1453 // (noreg) than rsp will be used instead.
duke@0 1454 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
duke@0 1455 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
duke@0 1456 Register java_thread, // the thread if computed before ; use noreg otherwise
duke@0 1457 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
duke@0 1458 address entry_point, // the entry point
duke@0 1459 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
duke@0 1460 bool check_exceptions // whether to check for pending exceptions after return
duke@0 1461 );
duke@0 1462
duke@0 1463 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
duke@0 1464 // The implementation is only non-empty for the InterpreterMacroAssembler,
duke@0 1465 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
duke@0 1466 virtual void check_and_handle_popframe(Register java_thread);
duke@0 1467 virtual void check_and_handle_earlyret(Register java_thread);
duke@0 1468
duke@0 1469 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
duke@0 1470
duke@0 1471 // helpers for FPU flag access
duke@0 1472 // tmp is a temporary register, if none is available use noreg
duke@0 1473 void save_rax (Register tmp);
duke@0 1474 void restore_rax(Register tmp);
duke@0 1475
duke@0 1476 public:
duke@0 1477 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
duke@0 1478
duke@0 1479 // Support for NULL-checks
duke@0 1480 //
duke@0 1481 // Generates code that causes a NULL OS exception if the content of reg is NULL.
duke@0 1482 // If the accessed location is M[reg + offset] and the offset is known, provide the
duke@0 1483 // offset. No explicit code generation is needed if the offset is within a certain
duke@0 1484 // range (0 <= offset <= page_size).
duke@0 1485
duke@0 1486 void null_check(Register reg, int offset = -1);
kvn@156 1487 static bool needs_explicit_null_check(intptr_t offset);
duke@0 1488
duke@0 1489 // Required platform-specific helpers for Label::patch_instructions.
duke@0 1490 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
duke@0 1491 void pd_patch_instruction(address branch, address target);
duke@0 1492 #ifndef PRODUCT
duke@0 1493 static void pd_print_patched_instruction(address branch);
duke@0 1494 #endif
duke@0 1495
duke@0 1496 // The following 4 methods return the offset of the appropriate move instruction
duke@0 1497
jrose@601 1498 // Support for fast byte/short loading with zero extension (depending on particular CPU)
duke@0 1499 int load_unsigned_byte(Register dst, Address src);
jrose@601 1500 int load_unsigned_short(Register dst, Address src);
jrose@601 1501
jrose@601 1502 // Support for fast byte/short loading with sign extension (depending on particular CPU)
duke@0 1503 int load_signed_byte(Register dst, Address src);
jrose@601 1504 int load_signed_short(Register dst, Address src);
duke@0 1505
duke@0 1506 // Support for sign-extension (hi:lo = extend_sign(lo))
duke@0 1507 void extend_sign(Register hi, Register lo);
duke@0 1508
jrose@601 1509 // Loading values by size and signed-ness
jrose@601 1510 void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed);
jrose@601 1511
duke@0 1512 // Support for inc/dec with optimal instruction selection depending on value
never@297 1513
never@297 1514 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
never@297 1515 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
never@297 1516
never@297 1517 void decrementl(Address dst, int value = 1);
never@297 1518 void decrementl(Register reg, int value = 1);
never@297 1519
never@297 1520 void decrementq(Register reg, int value = 1);
never@297 1521 void decrementq(Address dst, int value = 1);
never@297 1522
never@297 1523 void incrementl(Address dst, int value = 1);
never@297 1524 void incrementl(Register reg, int value = 1);
never@297 1525
never@297 1526 void incrementq(Register reg, int value = 1);
never@297 1527 void incrementq(Address dst, int value = 1);
never@297 1528
duke@0 1529
duke@0 1530 // Support optimal SSE move instructions.
duke@0 1531 void movflt(XMMRegister dst, XMMRegister src) {
duke@0 1532 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
duke@0 1533 else { movss (dst, src); return; }
duke@0 1534 }
duke@0 1535 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
duke@0 1536 void movflt(XMMRegister dst, AddressLiteral src);
duke@0 1537 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
duke@0 1538
duke@0 1539 void movdbl(XMMRegister dst, XMMRegister src) {
duke@0 1540 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
duke@0 1541 else { movsd (dst, src); return; }
duke@0 1542 }
duke@0 1543
duke@0 1544 void movdbl(XMMRegister dst, AddressLiteral src);
duke@0 1545
duke@0 1546 void movdbl(XMMRegister dst, Address src) {
duke@0 1547 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
duke@0 1548 else { movlpd(dst, src); return; }
duke@0 1549 }
duke@0 1550 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
duke@0 1551
never@297 1552 void incrementl(AddressLiteral dst);
never@297 1553 void incrementl(ArrayAddress dst);
duke@0 1554
duke@0 1555 // Alignment
duke@0 1556 void align(int modulus);
duke@0 1557
duke@0 1558 // Misc
duke@0 1559 void fat_nop(); // 5 byte nop
duke@0 1560
duke@0 1561 // Stack frame creation/removal
duke@0 1562 void enter();
duke@0 1563 void leave();
duke@0 1564
duke@0 1565 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
duke@0 1566 // The pointer will be loaded into the thread register.
duke@0 1567 void get_thread(Register thread);
duke@0 1568
apetrusenko@364 1569
duke@0 1570 // Support for VM calls
duke@0 1571 //
duke@0 1572 // It is imperative that all calls into the VM are handled via the call_VM macros.
duke@0 1573 // They make sure that the stack linkage is setup correctly. call_VM's correspond
duke@0 1574 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
duke@0 1575
never@297 1576
never@297 1577 void call_VM(Register oop_result,
never@297 1578 address entry_point,
never@297 1579 bool check_exceptions = true);
never@297 1580 void call_VM(Register oop_result,
never@297 1581 address entry_point,
never@297 1582 Register arg_1,
never@297 1583 bool check_exceptions = true);
never@297 1584 void call_VM(Register oop_result,
never@297 1585 address entry_point,
never@297 1586 Register arg_1, Register arg_2,
never@297 1587 bool check_exceptions = true);
never@297 1588 void call_VM(Register oop_result,
never@297 1589 address entry_point,
never@297 1590 Register arg_1, Register arg_2, Register arg_3,
never@297 1591 bool check_exceptions = true);
never@297 1592
never@297 1593 // Overloadings with last_Java_sp
never@297 1594 void call_VM(Register oop_result,
never@297 1595 Register last_java_sp,
never@297 1596 address entry_point,
never@297 1597 int number_of_arguments = 0,
never@297 1598 bool check_exceptions = true);
never@297 1599 void call_VM(Register oop_result,
never@297 1600 Register last_java_sp,
never@297 1601 address entry_point,
never@297 1602 Register arg_1, bool
never@297 1603 check_exceptions = true);
never@297 1604 void call_VM(Register oop_result,
never@297 1605 Register last_java_sp,
never@297 1606 address entry_point,
never@297 1607 Register arg_1, Register arg_2,
never@297 1608 bool check_exceptions = true);
never@297 1609 void call_VM(Register oop_result,
never@297 1610 Register last_java_sp,
never@297 1611 address entry_point,
never@297 1612 Register arg_1, Register arg_2, Register arg_3,
never@297 1613 bool check_exceptions = true);
never@297 1614
never@297 1615 void call_VM_leaf(address entry_point,
never@297 1616 int number_of_arguments = 0);
never@297 1617 void call_VM_leaf(address entry_point,
never@297 1618 Register arg_1);
never@297 1619 void call_VM_leaf(address entry_point,
never@297 1620 Register arg_1, Register arg_2);
never@297 1621 void call_VM_leaf(address entry_point,
never@297 1622 Register arg_1, Register arg_2, Register arg_3);
duke@0 1623
duke@0 1624 // last Java Frame (fills frame anchor)
never@297 1625 void set_last_Java_frame(Register thread,
never@297 1626 Register last_java_sp,
never@297 1627 Register last_java_fp,
never@297 1628 address last_java_pc);
never@297 1629
never@297 1630 // thread in the default location (r15_thread on 64bit)
never@297 1631 void set_last_Java_frame(Register last_java_sp,
never@297 1632 Register last_java_fp,
never@297 1633 address last_java_pc);
never@297 1634
duke@0 1635 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
duke@0 1636
never@297 1637 // thread in the default location (r15_thread on 64bit)
never@297 1638 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
never@297 1639
duke@0 1640 // Stores
duke@0 1641 void store_check(Register obj); // store check for obj - register is destroyed afterwards
duke@0 1642 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
duke@0 1643
apetrusenko@364 1644 void g1_write_barrier_pre(Register obj,
apetrusenko@364 1645 #ifndef _LP64
apetrusenko@364 1646 Register thread,
apetrusenko@364 1647 #endif
apetrusenko@364 1648 Register tmp,
apetrusenko@364 1649 Register tmp2,
apetrusenko@364 1650 bool tosca_live);
apetrusenko@364 1651 void g1_write_barrier_post(Register store_addr,
apetrusenko@364 1652 Register new_val,
apetrusenko@364 1653 #ifndef _LP64
apetrusenko@364 1654 Register thread,
apetrusenko@364 1655 #endif
apetrusenko@364 1656 Register tmp,
apetrusenko@364 1657 Register tmp2);
ysr@344 1658
ysr@344 1659
duke@0 1660 // split store_check(Register obj) to enhance instruction interleaving
duke@0 1661 void store_check_part_1(Register obj);
duke@0 1662 void store_check_part_2(Register obj);
duke@0 1663
duke@0 1664 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
duke@0 1665 void c2bool(Register x);
duke@0 1666
duke@0 1667 // C++ bool manipulation
duke@0 1668
duke@0 1669 void movbool(Register dst, Address src);
duke@0 1670 void movbool(Address dst, bool boolconst);
duke@0 1671 void movbool(Address dst, Register src);
duke@0 1672 void testbool(Register dst);
duke@0 1673
never@297 1674 // oop manipulations
never@297 1675 void load_klass(Register dst, Register src);
never@297 1676 void store_klass(Register dst, Register src);
never@297 1677
never@297 1678 void load_prototype_header(Register dst, Register src);
never@297 1679
never@297 1680 #ifdef _LP64
never@297 1681 void store_klass_gap(Register dst, Register src);
never@297 1682
never@297 1683 void load_heap_oop(Register dst, Address src);
never@297 1684 void store_heap_oop(Address dst, Register src);
never@297 1685 void encode_heap_oop(Register r);
never@297 1686 void decode_heap_oop(Register r);
never@297 1687 void encode_heap_oop_not_null(Register r);
never@297 1688 void decode_heap_oop_not_null(Register r);
never@297 1689 void encode_heap_oop_not_null(Register dst, Register src);
never@297 1690 void decode_heap_oop_not_null(Register dst, Register src);
never@297 1691
never@297 1692 void set_narrow_oop(Register dst, jobject obj);
kvn@619 1693 void set_narrow_oop(Address dst, jobject obj);
kvn@619 1694 void cmp_narrow_oop(Register dst, jobject obj);
kvn@619 1695 void cmp_narrow_oop(Address dst, jobject obj);
never@297 1696
never@297 1697 // if heap base register is used - reinit it with the correct value
never@297 1698 void reinit_heapbase();
never@297 1699 #endif // _LP64
never@297 1700
never@297 1701 // Int division/remainder for Java
duke@0 1702 // (as idivl, but checks for special case as described in JVM spec.)
duke@0 1703 // returns idivl instruction offset for implicit exception handling
duke@0 1704 int corrected_idivl(Register reg);
duke@0 1705
never@297 1706 // Long division/remainder for Java
never@297 1707 // (as idivq, but checks for special case as described in JVM spec.)
never@297 1708 // returns idivq instruction offset for implicit exception handling
never@297 1709 int corrected_idivq(Register reg);
never@297 1710
duke@0 1711 void int3();
duke@0 1712
never@297 1713 // Long operation macros for a 32bit cpu
duke@0 1714 // Long negation for Java
duke@0 1715 void lneg(Register hi, Register lo);
duke@0 1716
duke@0 1717 // Long multiplication for Java
never@297 1718 // (destroys contents of eax, ebx, ecx and edx)
duke@0 1719 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
duke@0 1720
duke@0 1721 // Long shifts for Java
duke@0 1722 // (semantics as described in JVM spec.)
duke@0 1723 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
duke@0 1724 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
duke@0 1725
duke@0 1726 // Long compare for Java
duke@0 1727 // (semantics as described in JVM spec.)
duke@0 1728 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
duke@0 1729
never@297 1730
never@297 1731 // misc
never@297 1732
never@297 1733 // Sign extension
never@297 1734 void sign_extend_short(Register reg);
never@297 1735 void sign_extend_byte(Register reg);
never@297 1736
never@297 1737 // Division by power of 2, rounding towards 0
never@297 1738 void division_with_shift(Register reg, int shift_value);
never@297 1739
duke@0 1740 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
duke@0 1741 //
duke@0 1742 // CF (corresponds to C0) if x < y
duke@0 1743 // PF (corresponds to C2) if unordered
duke@0 1744 // ZF (corresponds to C3) if x = y
duke@0 1745 //
duke@0 1746 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
duke@0 1747 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
duke@0 1748 void fcmp(Register tmp);
duke@0 1749 // Variant of the above which allows y to be further down the stack
duke@0 1750 // and which only pops x and y if specified. If pop_right is
duke@0 1751 // specified then pop_left must also be specified.
duke@0 1752 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
duke@0 1753
duke@0 1754 // Floating-point comparison for Java
duke@0 1755 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
duke@0 1756 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
duke@0 1757 // (semantics as described in JVM spec.)
duke@0 1758 void fcmp2int(Register dst, bool unordered_is_less);
duke@0 1759 // Variant of the above which allows y to be further down the stack
duke@0 1760 // and which only pops x and y if specified. If pop_right is
duke@0 1761 // specified then pop_left must also be specified.
duke@0 1762 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
duke@0 1763
duke@0 1764 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
duke@0 1765 // tmp is a temporary register, if none is available use noreg
duke@0 1766 void fremr(Register tmp);
duke@0 1767
duke@0 1768
duke@0 1769 // same as fcmp2int, but using SSE2
duke@0 1770 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
duke@0 1771 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
duke@0 1772
duke@0 1773 // Inlined sin/cos generator for Java; must not use CPU instruction
duke@0 1774 // directly on Intel as it does not have high enough precision
duke@0 1775 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
duke@0 1776 // number of FPU stack slots in use; all but the topmost will
duke@0 1777 // require saving if a slow case is necessary. Assumes argument is
duke@0 1778 // on FP TOS; result is on FP TOS. No cpu registers are changed by
duke@0 1779 // this code.
duke@0 1780 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
duke@0 1781
duke@0 1782 // branch to L if FPU flag C2 is set/not set
duke@0 1783 // tmp is a temporary register, if none is available use noreg
duke@0 1784 void jC2 (Register tmp, Label& L);
duke@0 1785 void jnC2(Register tmp, Label& L);
duke@0 1786
duke@0 1787 // Pop ST (ffree & fincstp combined)
duke@0 1788 void fpop();
duke@0 1789
duke@0 1790 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
duke@0 1791 void push_fTOS();
duke@0 1792
duke@0 1793 // pops double TOS element from CPU stack and pushes on FPU stack
duke@0 1794 void pop_fTOS();
duke@0 1795
duke@0 1796 void empty_FPU_stack();
duke@0 1797
duke@0 1798 void push_IU_state();
duke@0 1799 void pop_IU_state();
duke@0 1800
duke@0 1801 void push_FPU_state();
duke@0 1802 void pop_FPU_state();
duke@0 1803
duke@0 1804 void push_CPU_state();
duke@0 1805 void pop_CPU_state();
duke@0 1806
duke@0 1807 // Round up to a power of two
duke@0 1808 void round_to(Register reg, int modulus);
duke@0 1809
duke@0 1810 // Callee saved registers handling
duke@0 1811 void push_callee_saved_registers();
duke@0 1812 void pop_callee_saved_registers();
duke@0 1813
duke@0 1814 // allocation
duke@0 1815 void eden_allocate(
duke@0 1816 Register obj, // result: pointer to object after successful allocation
duke@0 1817 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@0 1818 int con_size_in_bytes, // object size in bytes if known at compile time
duke@0 1819 Register t1, // temp register
duke@0 1820 Label& slow_case // continuation point if fast allocation fails
duke@0 1821 );
duke@0 1822 void tlab_allocate(
duke@0 1823 Register obj, // result: pointer to object after successful allocation
duke@0 1824 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
duke@0 1825 int con_size_in_bytes, // object size in bytes if known at compile time
duke@0 1826 Register t1, // temp register
duke@0 1827 Register t2, // temp register
duke@0 1828 Label& slow_case // continuation point if fast allocation fails
duke@0 1829 );
duke@0 1830 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
duke@0 1831
jrose@602 1832 // interface method calling
jrose@602 1833 void lookup_interface_method(Register recv_klass,
jrose@602 1834 Register intf_klass,
jrose@646 1835 RegisterOrConstant itable_index,
jrose@602 1836 Register method_result,
jrose@602 1837 Register scan_temp,
jrose@602 1838 Label& no_such_interface);
jrose@602 1839
jrose@621 1840 // Test sub_klass against super_klass, with fast and slow paths.
jrose@621 1841
jrose@621 1842 // The fast path produces a tri-state answer: yes / no / maybe-slow.
jrose@621 1843 // One of the three labels can be NULL, meaning take the fall-through.
jrose@621 1844 // If super_check_offset is -1, the value is loaded up from super_klass.
jrose@621 1845 // No registers are killed, except temp_reg.
jrose@621 1846 void check_klass_subtype_fast_path(Register sub_klass,
jrose@621 1847 Register super_klass,
jrose@621 1848 Register temp_reg,
jrose@621 1849 Label* L_success,
jrose@621 1850 Label* L_failure,
jrose@621 1851 Label* L_slow_path,
jrose@646 1852 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
jrose@621 1853
jrose@621 1854 // The rest of the type check; must be wired to a corresponding fast path.
jrose@621 1855 // It does not repeat the fast path logic, so don't use it standalone.
jrose@621 1856 // The temp_reg and temp2_reg can be noreg, if no temps are available.
jrose@621 1857 // Updates the sub's secondary super cache as necessary.
jrose@621 1858 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
jrose@621 1859 void check_klass_subtype_slow_path(Register sub_klass,
jrose@621 1860 Register super_klass,
jrose@621 1861 Register temp_reg,
jrose@621 1862 Register temp2_reg,
jrose@621 1863 Label* L_success,
jrose@621 1864 Label* L_failure,
jrose@621 1865 bool set_cond_codes = false);
jrose@621 1866
jrose@621 1867 // Simplified, combined version, good for typical uses.
jrose@621 1868 // Falls through on failure.
jrose@621 1869 void check_klass_subtype(Register sub_klass,
jrose@621 1870 Register super_klass,
jrose@621 1871 Register temp_reg,
jrose@621 1872 Label& L_success);
jrose@621 1873
jrose@689 1874 // method handles (JSR 292)
jrose@689 1875 void check_method_handle_type(Register mtype_reg, Register mh_reg,
jrose@689 1876 Register temp_reg,
jrose@689 1877 Label& wrong_method_type);
jrose@689 1878 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
jrose@689 1879 Register temp_reg);
jrose@689 1880 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
jrose@689 1881 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
jrose@689 1882
jrose@689 1883
duke@0 1884 //----
duke@0 1885 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
duke@0 1886
duke@0 1887 // Debugging
never@297 1888
never@297 1889 // only if +VerifyOops
never@297 1890 void verify_oop(Register reg, const char* s = "broken oop");
duke@0 1891 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
duke@0 1892
never@297 1893 // only if +VerifyFPU
never@297 1894 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
never@297 1895
never@297 1896 // prints msg, dumps registers and stops execution
never@297 1897 void stop(const char* msg);
never@297 1898
never@297 1899 // prints msg and continues
never@297 1900 void warn(const char* msg);
never@297 1901
never@297 1902 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
never@297 1903 static void debug64(char* msg, int64_t pc, int64_t regs[]);
never@297 1904
duke@0 1905 void os_breakpoint();
never@297 1906
duke@0 1907 void untested() { stop("untested"); }
never@297 1908
duke@0 1909 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
never@297 1910
duke@0 1911 void should_not_reach_here() { stop("should not reach here"); }
never@297 1912
duke@0 1913 void print_CPU_state();
duke@0 1914
duke@0 1915 // Stack overflow checking
duke@0 1916 void bang_stack_with_offset(int offset) {
duke@0 1917 // stack grows down, caller passes positive offset
duke@0 1918 assert(offset > 0, "must bang with negative offset");
duke@0 1919 movl(Address(rsp, (-offset)), rax);
duke@0 1920 }
duke@0 1921
duke@0 1922 // Writes to stack successive pages until offset reached to check for
duke@0 1923 // stack overflow + shadow pages. Also, clobbers tmp
duke@0 1924 void bang_stack_size(Register size, Register tmp);
duke@0 1925
jrose@646 1926 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
jrose@646 1927 Register tmp,
jrose@646 1928 int offset);
jrose@601 1929
duke@0 1930 // Support for serializing memory accesses between threads
duke@0 1931 void serialize_memory(Register thread, Register tmp);
duke@0 1932
duke@0 1933 void verify_tlab();
duke@0 1934
duke@0 1935 // Biased locking support
duke@0 1936 // lock_reg and obj_reg must be loaded up with the appropriate values.
duke@0 1937 // swap_reg must be rax, and is killed.
duke@0 1938 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
duke@0 1939 // be killed; if not supplied, push/pop will be used internally to
duke@0 1940 // allocate a temporary (inefficient, avoid if possible).
duke@0 1941 // Optional slow case is for implementations (interpreter and C1) which branch to
duke@0 1942 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
duke@0 1943 // Returns offset of first potentially-faulting instruction for null
duke@0 1944 // check info (currently consumed only by C1). If
duke@0 1945 // swap_reg_contains_mark is true then returns -1 as it is assumed
duke@0 1946 // the calling code has already passed any potential faults.
kvn@411 1947 int biased_locking_enter(Register lock_reg, Register obj_reg,
kvn@411 1948 Register swap_reg, Register tmp_reg,
duke@0 1949 bool swap_reg_contains_mark,
duke@0 1950 Label& done, Label* slow_case = NULL,
duke@0 1951 BiasedLockingCounters* counters = NULL);
duke@0 1952 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
duke@0 1953
duke@0 1954
duke@0 1955 Condition negate_condition(Condition cond);
duke@0 1956
duke@0 1957 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
duke@0 1958 // operands. In general the names are modified to avoid hiding the instruction in Assembler
duke@0 1959 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
duke@0 1960 // here in MacroAssembler. The major exception to this rule is call
duke@0 1961
duke@0 1962 // Arithmetics
duke@0 1963
never@297 1964
never@297 1965 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
never@297 1966 void addptr(Address dst, Register src);
never@297 1967
never@297 1968 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
never@297 1969 void addptr(Register dst, int32_t src);
never@297 1970 void addptr(Register dst, Register src);
never@297 1971
never@297 1972 void andptr(Register dst, int32_t src);
never@297 1973 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
never@297 1974
never@297 1975 void cmp8(AddressLiteral src1, int imm);
never@297 1976
never@297 1977 // renamed to drag out the casting of address to int32_t/intptr_t
duke@0 1978 void cmp32(Register src1, int32_t imm);
duke@0 1979
duke@0 1980 void cmp32(AddressLiteral src1, int32_t imm);
duke@0 1981 // compare reg - mem, or reg - &mem
duke@0 1982 void cmp32(Register src1, AddressLiteral src2);
duke@0 1983
duke@0 1984 void cmp32(Register src1, Address src2);
duke@0 1985
never@297 1986 #ifndef _LP64
never@297 1987 void cmpoop(Address dst, jobject obj);
never@297 1988 void cmpoop(Register dst, jobject obj);
never@297 1989 #endif // _LP64
never@297 1990
duke@0 1991 // NOTE src2 must be the lval. This is NOT an mem-mem compare
duke@0 1992 void cmpptr(Address src1, AddressLiteral src2);
duke@0 1993
duke@0 1994 void cmpptr(Register src1, AddressLiteral src2);
duke@0 1995
never@297 1996 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@297 1997 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@297 1998 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@297 1999
never@297 2000 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@297 2001 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
never@297 2002
never@297 2003 // cmp64 to avoild hiding cmpq
never@297 2004 void cmp64(Register src1, AddressLiteral src);
never@297 2005
never@297 2006 void cmpxchgptr(Register reg, Address adr);
never@297 2007
never@297 2008 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
never@297 2009
never@297 2010
never@297 2011 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
never@297 2012
never@297 2013
never@297 2014 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
never@297 2015
never@297 2016 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
never@297 2017
never@297 2018 void shlptr(Register dst, int32_t shift);
never@297 2019 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
never@297 2020
never@297 2021 void shrptr(Register dst, int32_t shift);
never@297 2022 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
never@297 2023
never@297 2024 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
never@297 2025 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
never@297 2026
never@297 2027 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
never@297 2028
never@297 2029 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
never@297 2030 void subptr(Register dst, int32_t src);
never@297 2031 void subptr(Register dst, Register src);
never@297 2032
never@297 2033
never@297 2034 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
never@297 2035 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
never@297 2036
never@297 2037 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
never@297 2038 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
never@297 2039
never@297 2040 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
never@297 2041
never@297 2042
duke@0 2043
duke@0 2044 // Helper functions for statistics gathering.
duke@0 2045 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
duke@0 2046 void cond_inc32(Condition cond, AddressLiteral counter_addr);
duke@0 2047 // Unconditional atomic increment.
duke@0 2048 void atomic_incl(AddressLiteral counter_addr);
duke@0 2049
duke@0 2050 void lea(Register dst, AddressLiteral adr);
duke@0 2051 void lea(Address dst, AddressLiteral adr);
never@297 2052 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
never@297 2053
never@297 2054 void leal32(Register dst, Address src) { leal(dst, src); }
never@297 2055
never@297 2056 void test32(Register src1, AddressLiteral src2);
never@297 2057
never@297 2058 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@297 2059 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@297 2060 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
never@297 2061
never@297 2062 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
never@297 2063 void testptr(Register src1, Register src2);
never@297 2064
never@297 2065 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
never@297 2066 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
duke@0 2067
duke@0 2068 // Calls
duke@0 2069
duke@0 2070 void call(Label& L, relocInfo::relocType rtype);
duke@0 2071 void call(Register entry);
duke@0 2072
duke@0 2073 // NOTE: this call tranfers to the effective address of entry NOT
duke@0 2074 // the address contained by entry. This is because this is more natural
duke@0 2075 // for jumps/calls.
duke@0 2076 void call(AddressLiteral entry);
duke@0 2077
duke@0 2078 // Jumps
duke@0 2079
duke@0 2080 // NOTE: these jumps tranfer to the effective address of dst NOT
duke@0 2081 // the address contained by dst. This is because this is more natural
duke@0 2082 // for jumps/calls.
duke@0 2083 void jump(AddressLiteral dst);
duke@0 2084 void jump_cc(Condition cc, AddressLiteral dst);
duke@0 2085
duke@0 2086 // 32bit can do a case table jump in one instruction but we no longer allow the base
duke@0 2087 // to be installed in the Address class. This jump will tranfers to the address
duke@0 2088 // contained in the location described by entry (not the address of entry)
duke@0 2089 void jump(ArrayAddress entry);
duke@0 2090
duke@0 2091 // Floating
duke@0 2092
duke@0 2093 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
duke@0 2094 void andpd(XMMRegister dst, AddressLiteral src);
duke@0 2095
duke@0 2096 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
duke@0 2097 void comiss(XMMRegister dst, AddressLiteral src);
duke@0 2098
duke@0 2099 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
duke@0 2100 void comisd(XMMRegister dst, AddressLiteral src);
duke@0 2101
duke@0 2102 void fldcw(Address src) { Assembler::fldcw(src); }
duke@0 2103 void fldcw(AddressLiteral src);
duke@0 2104
duke@0 2105 void fld_s(int index) { Assembler::fld_s(index); }
duke@0 2106 void fld_s(Address src) { Assembler::fld_s(src); }
duke@0 2107 void fld_s(AddressLiteral src);
duke@0 2108
duke@0 2109 void fld_d(Address src) { Assembler::fld_d(src); }
duke@0 2110 void fld_d(AddressLiteral src);
duke@0 2111
duke@0 2112 void fld_x(Address src) { Assembler::fld_x(src); }
duke@0 2113 void fld_x(AddressLiteral src);
duke@0 2114
duke@0 2115 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
duke@0 2116 void ldmxcsr(AddressLiteral src);
duke@0 2117
never@297 2118 private:
never@297 2119 // these are private because users should be doing movflt/movdbl
never@297 2120
duke@0 2121 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
duke@0 2122 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
duke@0 2123 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
duke@0 2124 void movss(XMMRegister dst, AddressLiteral src);
duke@0 2125
never@297 2126 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
never@297 2127 void movlpd(XMMRegister dst, AddressLiteral src);
never@297 2128
never@297 2129 public:
never@297 2130
duke@0 2131 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
duke@0 2132 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
duke@0 2133 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
duke@0 2134 void movsd(XMMRegister dst, AddressLiteral src);
duke@0 2135
duke@0 2136 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
duke@0 2137 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
duke@0 2138 void ucomiss(XMMRegister dst, AddressLiteral src);
duke@0 2139
duke@0 2140 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
duke@0 2141 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
duke@0 2142 void ucomisd(XMMRegister dst, AddressLiteral src);
duke@0 2143
duke@0 2144 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
duke@0 2145 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
duke@0 2146 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
duke@0 2147 void xorpd(XMMRegister dst, AddressLiteral src);
duke@0 2148
duke@0 2149 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
duke@0 2150 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
duke@0 2151 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
duke@0 2152 void xorps(XMMRegister dst, AddressLiteral src);
duke@0 2153
duke@0 2154 // Data
duke@0 2155
never@297 2156 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@297 2157
never@297 2158 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@297 2159 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
never@297 2160
duke@0 2161 void movoop(Register dst, jobject obj);
duke@0 2162 void movoop(Address dst, jobject obj);
duke@0 2163
duke@0 2164 void movptr(ArrayAddress dst, Register src);
duke@0 2165 // can this do an lea?
duke@0 2166 void movptr(Register dst, ArrayAddress src);
duke@0 2167
never@297 2168 void movptr(Register dst, Address src);
never@297 2169
duke@0 2170 void movptr(Register dst, AddressLiteral src);
duke@0 2171
never@297 2172 void movptr(Register dst, intptr_t src);
never@297 2173 void movptr(Register dst, Register src);
never@297 2174 void movptr(Address dst, intptr_t src);
never@297 2175
never@297 2176 void movptr(Address dst, Register src);
never@297 2177
never@297 2178 #ifdef _LP64
never@297 2179 // Generally the next two are only used for moving NULL
never@297 2180 // Although there are situations in initializing the mark word where
never@297 2181 // they could be used. They are dangerous.
never@297 2182
never@297 2183 // They only exist on LP64 so that int32_t and intptr_t are not the same
never@297 2184 // and we have ambiguous declarations.
never@297 2185
never@297 2186 void movptr(Address dst, int32_t imm32);
never@297 2187 void movptr(Register dst, int32_t imm32);
never@297 2188 #endif // _LP64
never@297 2189
duke@0 2190 // to avoid hiding movl
duke@0 2191 void mov32(AddressLiteral dst, Register src);
duke@0 2192 void mov32(Register dst, AddressLiteral src);
never@297 2193
duke@0 2194 // to avoid hiding movb
duke@0 2195 void movbyte(ArrayAddress dst, int src);
duke@0 2196
duke@0 2197 // Can push value or effective address
duke@0 2198 void pushptr(AddressLiteral src);
duke@0 2199
never@297 2200 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
never@297 2201 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
never@297 2202
never@297 2203 void pushoop(jobject obj);
never@297 2204
never@297 2205 // sign extend as need a l to ptr sized element
never@297 2206 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
never@297 2207 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
never@297 2208
never@297 2209
duke@0 2210 #undef VIRTUAL
duke@0 2211
duke@0 2212 };
duke@0 2213
duke@0 2214 /**
duke@0 2215 * class SkipIfEqual:
duke@0 2216 *
duke@0 2217 * Instantiating this class will result in assembly code being output that will
duke@0 2218 * jump around any code emitted between the creation of the instance and it's
duke@0 2219 * automatic destruction at the end of a scope block, depending on the value of
duke@0 2220 * the flag passed to the constructor, which will be checked at run-time.
duke@0 2221 */
duke@0 2222 class SkipIfEqual {
duke@0 2223 private:
duke@0 2224 MacroAssembler* _masm;
duke@0 2225 Label _label;
duke@0 2226
duke@0 2227 public:
duke@0 2228 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
duke@0 2229 ~SkipIfEqual();
duke@0 2230 };
duke@0 2231
duke@0 2232 #ifdef ASSERT
duke@0 2233 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
duke@0 2234 #endif