annotate src/cpu/x86/vm/vm_version_x86.cpp @ 747:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents fbde8ec322d0
children 323bd24c6520
rev   line source
twisti@569 1 /*
twisti@569 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
twisti@569 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@569 4 *
twisti@569 5 * This code is free software; you can redistribute it and/or modify it
twisti@569 6 * under the terms of the GNU General Public License version 2 only, as
twisti@569 7 * published by the Free Software Foundation.
twisti@569 8 *
twisti@569 9 * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@569 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@569 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
twisti@569 12 * version 2 for more details (a copy is included in the LICENSE file that
twisti@569 13 * accompanied this code).
twisti@569 14 *
twisti@569 15 * You should have received a copy of the GNU General Public License version
twisti@569 16 * 2 along with this work; if not, write to the Free Software Foundation,
twisti@569 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@569 18 *
twisti@569 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
twisti@569 20 * CA 95054 USA or visit www.sun.com if you need additional information or
twisti@569 21 * have any questions.
twisti@569 22 *
twisti@569 23 */
twisti@569 24
twisti@569 25 # include "incls/_precompiled.incl"
twisti@569 26 # include "incls/_vm_version_x86.cpp.incl"
twisti@569 27
twisti@569 28
twisti@569 29 int VM_Version::_cpu;
twisti@569 30 int VM_Version::_model;
twisti@569 31 int VM_Version::_stepping;
twisti@569 32 int VM_Version::_cpuFeatures;
twisti@569 33 const char* VM_Version::_features_str = "";
twisti@569 34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
twisti@569 35
twisti@569 36 static BufferBlob* stub_blob;
twisti@569 37 static const int stub_size = 300;
twisti@569 38
twisti@569 39 extern "C" {
twisti@569 40 typedef void (*getPsrInfo_stub_t)(void*);
twisti@569 41 }
twisti@569 42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
twisti@569 43
twisti@569 44
twisti@569 45 class VM_Version_StubGenerator: public StubCodeGenerator {
twisti@569 46 public:
twisti@569 47
twisti@569 48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
twisti@569 49
twisti@569 50 address generate_getPsrInfo() {
twisti@569 51 // Flags to test CPU type.
twisti@569 52 const uint32_t EFL_AC = 0x40000;
twisti@569 53 const uint32_t EFL_ID = 0x200000;
twisti@569 54 // Values for when we don't have a CPUID instruction.
twisti@569 55 const int CPU_FAMILY_SHIFT = 8;
twisti@569 56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
twisti@569 57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
twisti@569 58
twisti@569 59 Label detect_486, cpu486, detect_586, std_cpuid1;
twisti@569 60 Label ext_cpuid1, ext_cpuid5, done;
twisti@569 61
twisti@569 62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
twisti@569 63 # define __ _masm->
twisti@569 64
twisti@569 65 address start = __ pc();
twisti@569 66
twisti@569 67 //
twisti@569 68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
twisti@569 69 //
twisti@569 70 // LP64: rcx and rdx are first and second argument registers on windows
twisti@569 71
twisti@569 72 __ push(rbp);
twisti@569 73 #ifdef _LP64
twisti@569 74 __ mov(rbp, c_rarg0); // cpuid_info address
twisti@569 75 #else
twisti@569 76 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
twisti@569 77 #endif
twisti@569 78 __ push(rbx);
twisti@569 79 __ push(rsi);
twisti@569 80 __ pushf(); // preserve rbx, and flags
twisti@569 81 __ pop(rax);
twisti@569 82 __ push(rax);
twisti@569 83 __ mov(rcx, rax);
twisti@569 84 //
twisti@569 85 // if we are unable to change the AC flag, we have a 386
twisti@569 86 //
twisti@569 87 __ xorl(rax, EFL_AC);
twisti@569 88 __ push(rax);
twisti@569 89 __ popf();
twisti@569 90 __ pushf();
twisti@569 91 __ pop(rax);
twisti@569 92 __ cmpptr(rax, rcx);
twisti@569 93 __ jccb(Assembler::notEqual, detect_486);
twisti@569 94
twisti@569 95 __ movl(rax, CPU_FAMILY_386);
twisti@569 96 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
twisti@569 97 __ jmp(done);
twisti@569 98
twisti@569 99 //
twisti@569 100 // If we are unable to change the ID flag, we have a 486 which does
twisti@569 101 // not support the "cpuid" instruction.
twisti@569 102 //
twisti@569 103 __ bind(detect_486);
twisti@569 104 __ mov(rax, rcx);
twisti@569 105 __ xorl(rax, EFL_ID);
twisti@569 106 __ push(rax);
twisti@569 107 __ popf();
twisti@569 108 __ pushf();
twisti@569 109 __ pop(rax);
twisti@569 110 __ cmpptr(rcx, rax);
twisti@569 111 __ jccb(Assembler::notEqual, detect_586);
twisti@569 112
twisti@569 113 __ bind(cpu486);
twisti@569 114 __ movl(rax, CPU_FAMILY_486);
twisti@569 115 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
twisti@569 116 __ jmp(done);
twisti@569 117
twisti@569 118 //
twisti@569 119 // At this point, we have a chip which supports the "cpuid" instruction
twisti@569 120 //
twisti@569 121 __ bind(detect_586);
twisti@569 122 __ xorl(rax, rax);
twisti@569 123 __ cpuid();
twisti@569 124 __ orl(rax, rax);
twisti@569 125 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
twisti@569 126 // value of at least 1, we give up and
twisti@569 127 // assume a 486
twisti@569 128 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
twisti@569 129 __ movl(Address(rsi, 0), rax);
twisti@569 130 __ movl(Address(rsi, 4), rbx);
twisti@569 131 __ movl(Address(rsi, 8), rcx);
twisti@569 132 __ movl(Address(rsi,12), rdx);
twisti@569 133
twisti@569 134 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
twisti@569 135 __ jccb(Assembler::belowEqual, std_cpuid1);
twisti@569 136
twisti@569 137 //
twisti@569 138 // cpuid(0x4) Deterministic cache params
twisti@569 139 //
twisti@569 140 __ movl(rax, 4);
twisti@569 141 __ xorl(rcx, rcx); // L1 cache
twisti@569 142 __ cpuid();
twisti@569 143 __ push(rax);
twisti@569 144 __ andl(rax, 0x1f); // Determine if valid cache parameters used
twisti@569 145 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
twisti@569 146 __ pop(rax);
twisti@569 147 __ jccb(Assembler::equal, std_cpuid1);
twisti@569 148
twisti@569 149 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
twisti@569 150 __ movl(Address(rsi, 0), rax);
twisti@569 151 __ movl(Address(rsi, 4), rbx);
twisti@569 152 __ movl(Address(rsi, 8), rcx);
twisti@569 153 __ movl(Address(rsi,12), rdx);
twisti@569 154
twisti@569 155 //
twisti@569 156 // Standard cpuid(0x1)
twisti@569 157 //
twisti@569 158 __ bind(std_cpuid1);
twisti@569 159 __ movl(rax, 1);
twisti@569 160 __ cpuid();
twisti@569 161 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
twisti@569 162 __ movl(Address(rsi, 0), rax);
twisti@569 163 __ movl(Address(rsi, 4), rbx);
twisti@569 164 __ movl(Address(rsi, 8), rcx);
twisti@569 165 __ movl(Address(rsi,12), rdx);
twisti@569 166
twisti@569 167 __ movl(rax, 0x80000000);
twisti@569 168 __ cpuid();
twisti@569 169 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
twisti@569 170 __ jcc(Assembler::belowEqual, done);
twisti@569 171 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
twisti@569 172 __ jccb(Assembler::belowEqual, ext_cpuid1);
twisti@569 173 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
twisti@569 174 __ jccb(Assembler::belowEqual, ext_cpuid5);
twisti@569 175 //
twisti@569 176 // Extended cpuid(0x80000008)
twisti@569 177 //
twisti@569 178 __ movl(rax, 0x80000008);
twisti@569 179 __ cpuid();
twisti@569 180 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
twisti@569 181 __ movl(Address(rsi, 0), rax);
twisti@569 182 __ movl(Address(rsi, 4), rbx);
twisti@569 183 __ movl(Address(rsi, 8), rcx);
twisti@569 184 __ movl(Address(rsi,12), rdx);
twisti@569 185
twisti@569 186 //
twisti@569 187 // Extended cpuid(0x80000005)
twisti@569 188 //
twisti@569 189 __ bind(ext_cpuid5);
twisti@569 190 __ movl(rax, 0x80000005);
twisti@569 191 __ cpuid();
twisti@569 192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
twisti@569 193 __ movl(Address(rsi, 0), rax);
twisti@569 194 __ movl(Address(rsi, 4), rbx);
twisti@569 195 __ movl(Address(rsi, 8), rcx);
twisti@569 196 __ movl(Address(rsi,12), rdx);
twisti@569 197
twisti@569 198 //
twisti@569 199 // Extended cpuid(0x80000001)
twisti@569 200 //
twisti@569 201 __ bind(ext_cpuid1);
twisti@569 202 __ movl(rax, 0x80000001);
twisti@569 203 __ cpuid();
twisti@569 204 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
twisti@569 205 __ movl(Address(rsi, 0), rax);
twisti@569 206 __ movl(Address(rsi, 4), rbx);
twisti@569 207 __ movl(Address(rsi, 8), rcx);
twisti@569 208 __ movl(Address(rsi,12), rdx);
twisti@569 209
twisti@569 210 //
twisti@569 211 // return
twisti@569 212 //
twisti@569 213 __ bind(done);
twisti@569 214 __ popf();
twisti@569 215 __ pop(rsi);
twisti@569 216 __ pop(rbx);
twisti@569 217 __ pop(rbp);
twisti@569 218 __ ret(0);
twisti@569 219
twisti@569 220 # undef __
twisti@569 221
twisti@569 222 return start;
twisti@569 223 };
twisti@569 224 };
twisti@569 225
twisti@569 226
twisti@569 227 void VM_Version::get_processor_features() {
twisti@569 228
twisti@569 229 _cpu = 4; // 486 by default
twisti@569 230 _model = 0;
twisti@569 231 _stepping = 0;
twisti@569 232 _cpuFeatures = 0;
twisti@569 233 _logical_processors_per_package = 1;
twisti@569 234
twisti@569 235 if (!Use486InstrsOnly) {
twisti@569 236 // Get raw processor info
twisti@569 237 getPsrInfo_stub(&_cpuid_info);
twisti@569 238 assert_is_initialized();
twisti@569 239 _cpu = extended_cpu_family();
twisti@569 240 _model = extended_cpu_model();
twisti@569 241 _stepping = cpu_stepping();
twisti@569 242
twisti@569 243 if (cpu_family() > 4) { // it supports CPUID
twisti@569 244 _cpuFeatures = feature_flags();
twisti@569 245 // Logical processors are only available on P4s and above,
twisti@569 246 // and only if hyperthreading is available.
twisti@569 247 _logical_processors_per_package = logical_processor_count();
twisti@569 248 }
twisti@569 249 }
twisti@569 250
twisti@569 251 _supports_cx8 = supports_cmpxchg8();
twisti@569 252
twisti@569 253 #ifdef _LP64
twisti@569 254 // OS should support SSE for x64 and hardware should support at least SSE2.
twisti@569 255 if (!VM_Version::supports_sse2()) {
twisti@569 256 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
twisti@569 257 }
twisti@569 258 #endif
twisti@569 259
twisti@569 260 // If the OS doesn't support SSE, we can't use this feature even if the HW does
twisti@569 261 if (!os::supports_sse())
twisti@569 262 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
twisti@569 263
twisti@569 264 if (UseSSE < 4) {
twisti@569 265 _cpuFeatures &= ~CPU_SSE4_1;
twisti@569 266 _cpuFeatures &= ~CPU_SSE4_2;
twisti@569 267 }
twisti@569 268
twisti@569 269 if (UseSSE < 3) {
twisti@569 270 _cpuFeatures &= ~CPU_SSE3;
twisti@569 271 _cpuFeatures &= ~CPU_SSSE3;
twisti@569 272 _cpuFeatures &= ~CPU_SSE4A;
twisti@569 273 }
twisti@569 274
twisti@569 275 if (UseSSE < 2)
twisti@569 276 _cpuFeatures &= ~CPU_SSE2;
twisti@569 277
twisti@569 278 if (UseSSE < 1)
twisti@569 279 _cpuFeatures &= ~CPU_SSE;
twisti@569 280
twisti@569 281 if (logical_processors_per_package() == 1) {
twisti@569 282 // HT processor could be installed on a system which doesn't support HT.
twisti@569 283 _cpuFeatures &= ~CPU_HT;
twisti@569 284 }
twisti@569 285
twisti@569 286 char buf[256];
twisti@747 287 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
twisti@569 288 cores_per_cpu(), threads_per_core(),
twisti@569 289 cpu_family(), _model, _stepping,
twisti@569 290 (supports_cmov() ? ", cmov" : ""),
twisti@569 291 (supports_cmpxchg8() ? ", cx8" : ""),
twisti@569 292 (supports_fxsr() ? ", fxsr" : ""),
twisti@569 293 (supports_mmx() ? ", mmx" : ""),
twisti@569 294 (supports_sse() ? ", sse" : ""),
twisti@569 295 (supports_sse2() ? ", sse2" : ""),
twisti@569 296 (supports_sse3() ? ", sse3" : ""),
twisti@569 297 (supports_ssse3()? ", ssse3": ""),
twisti@569 298 (supports_sse4_1() ? ", sse4.1" : ""),
twisti@569 299 (supports_sse4_2() ? ", sse4.2" : ""),
twisti@620 300 (supports_popcnt() ? ", popcnt" : ""),
twisti@569 301 (supports_mmx_ext() ? ", mmxext" : ""),
twisti@569 302 (supports_3dnow() ? ", 3dnow" : ""),
twisti@569 303 (supports_3dnow2() ? ", 3dnowext" : ""),
twisti@747 304 (supports_lzcnt() ? ", lzcnt": ""),
twisti@569 305 (supports_sse4a() ? ", sse4a": ""),
twisti@569 306 (supports_ht() ? ", ht": ""));
twisti@569 307 _features_str = strdup(buf);
twisti@569 308
twisti@569 309 // UseSSE is set to the smaller of what hardware supports and what
twisti@569 310 // the command line requires. I.e., you cannot set UseSSE to 2 on
twisti@569 311 // older Pentiums which do not support it.
twisti@569 312 if( UseSSE > 4 ) UseSSE=4;
twisti@569 313 if( UseSSE < 0 ) UseSSE=0;
twisti@569 314 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
twisti@569 315 UseSSE = MIN2((intx)3,UseSSE);
twisti@569 316 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
twisti@569 317 UseSSE = MIN2((intx)2,UseSSE);
twisti@569 318 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
twisti@569 319 UseSSE = MIN2((intx)1,UseSSE);
twisti@569 320 if( !supports_sse () ) // Drop to 0 if no SSE support
twisti@569 321 UseSSE = 0;
twisti@569 322
twisti@569 323 // On new cpus instructions which update whole XMM register should be used
twisti@569 324 // to prevent partial register stall due to dependencies on high half.
twisti@569 325 //
twisti@569 326 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
twisti@569 327 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
twisti@569 328 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
twisti@569 329 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
twisti@569 330
twisti@569 331 if( is_amd() ) { // AMD cpus specific settings
twisti@569 332 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
twisti@569 333 // Use it on new AMD cpus starting from Opteron.
twisti@569 334 UseAddressNop = true;
twisti@569 335 }
twisti@569 336 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
twisti@569 337 // Use it on new AMD cpus starting from Opteron.
twisti@569 338 UseNewLongLShift = true;
twisti@569 339 }
twisti@569 340 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
twisti@569 341 if( supports_sse4a() ) {
twisti@569 342 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
twisti@569 343 } else {
twisti@569 344 UseXmmLoadAndClearUpper = false;
twisti@569 345 }
twisti@569 346 }
twisti@569 347 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
twisti@569 348 if( supports_sse4a() ) {
twisti@569 349 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
twisti@569 350 } else {
twisti@569 351 UseXmmRegToRegMoveAll = false;
twisti@569 352 }
twisti@569 353 }
twisti@569 354 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
twisti@569 355 if( supports_sse4a() ) {
twisti@569 356 UseXmmI2F = true;
twisti@569 357 } else {
twisti@569 358 UseXmmI2F = false;
twisti@569 359 }
twisti@569 360 }
twisti@569 361 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
twisti@569 362 if( supports_sse4a() ) {
twisti@569 363 UseXmmI2D = true;
twisti@569 364 } else {
twisti@569 365 UseXmmI2D = false;
twisti@569 366 }
twisti@569 367 }
twisti@747 368
twisti@747 369 // Use count leading zeros count instruction if available.
twisti@747 370 if (supports_lzcnt()) {
twisti@747 371 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
twisti@747 372 UseCountLeadingZerosInstruction = true;
twisti@747 373 }
twisti@747 374 }
twisti@569 375 }
twisti@569 376
twisti@569 377 if( is_intel() ) { // Intel cpus specific settings
twisti@569 378 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
twisti@569 379 UseStoreImmI16 = false; // don't use it on Intel cpus
twisti@569 380 }
twisti@569 381 if( cpu_family() == 6 || cpu_family() == 15 ) {
twisti@569 382 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
twisti@569 383 // Use it on all Intel cpus starting from PentiumPro
twisti@569 384 UseAddressNop = true;
twisti@569 385 }
twisti@569 386 }
twisti@569 387 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
twisti@569 388 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
twisti@569 389 }
twisti@569 390 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
twisti@569 391 if( supports_sse3() ) {
twisti@569 392 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
twisti@569 393 } else {
twisti@569 394 UseXmmRegToRegMoveAll = false;
twisti@569 395 }
twisti@569 396 }
twisti@569 397 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
twisti@569 398 #ifdef COMPILER2
twisti@569 399 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
twisti@569 400 // For new Intel cpus do the next optimization:
twisti@569 401 // don't align the beginning of a loop if there are enough instructions
twisti@569 402 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
twisti@569 403 // in current fetch line (OptoLoopAlignment) or the padding
twisti@569 404 // is big (> MaxLoopPad).
twisti@569 405 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
twisti@569 406 // generated NOP instructions. 11 is the largest size of one
twisti@569 407 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
twisti@569 408 MaxLoopPad = 11;
twisti@569 409 }
twisti@569 410 #endif // COMPILER2
twisti@569 411 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
twisti@569 412 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
twisti@569 413 }
twisti@569 414 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
twisti@569 415 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
twisti@569 416 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
twisti@569 417 }
twisti@569 418 }
cfang@674 419 if( supports_sse4_2() && UseSSE >= 4 ) {
cfang@674 420 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
cfang@674 421 UseSSE42Intrinsics = true;
cfang@674 422 }
cfang@674 423 }
twisti@569 424 }
twisti@569 425 }
twisti@569 426
twisti@620 427 // Use population count instruction if available.
twisti@620 428 if (supports_popcnt()) {
twisti@620 429 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
twisti@620 430 UsePopCountInstruction = true;
twisti@620 431 }
twisti@620 432 }
twisti@620 433
twisti@569 434 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
twisti@569 435 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
twisti@569 436
twisti@569 437 // set valid Prefetch instruction
twisti@569 438 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
twisti@569 439 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
twisti@569 440 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
twisti@569 441 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
twisti@569 442
twisti@569 443 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
twisti@569 444 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
twisti@569 445 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
twisti@569 446 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
twisti@569 447
twisti@569 448 // Allocation prefetch settings
twisti@569 449 intx cache_line_size = L1_data_cache_line_size();
twisti@569 450 if( cache_line_size > AllocatePrefetchStepSize )
twisti@569 451 AllocatePrefetchStepSize = cache_line_size;
twisti@569 452 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
twisti@569 453 AllocatePrefetchLines = 3; // Optimistic value
twisti@569 454 assert(AllocatePrefetchLines > 0, "invalid value");
twisti@569 455 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
twisti@569 456 AllocatePrefetchLines = 1; // Conservative value
twisti@569 457
twisti@569 458 AllocatePrefetchDistance = allocate_prefetch_distance();
twisti@569 459 AllocatePrefetchStyle = allocate_prefetch_style();
twisti@569 460
twisti@569 461 if( AllocatePrefetchStyle == 2 && is_intel() &&
twisti@569 462 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
twisti@569 463 #ifdef _LP64
twisti@569 464 AllocatePrefetchDistance = 384;
twisti@569 465 #else
twisti@569 466 AllocatePrefetchDistance = 320;
twisti@569 467 #endif
twisti@569 468 }
twisti@569 469 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
twisti@569 470
twisti@569 471 #ifdef _LP64
twisti@569 472 // Prefetch settings
twisti@569 473 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
twisti@569 474 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
twisti@569 475 PrefetchFieldsAhead = prefetch_fields_ahead();
twisti@569 476 #endif
twisti@569 477
twisti@569 478 #ifndef PRODUCT
twisti@569 479 if (PrintMiscellaneous && Verbose) {
twisti@569 480 tty->print_cr("Logical CPUs per core: %u",
twisti@569 481 logical_processors_per_package());
twisti@569 482 tty->print_cr("UseSSE=%d",UseSSE);
twisti@569 483 tty->print("Allocation: ");
twisti@569 484 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
twisti@569 485 tty->print_cr("no prefetching");
twisti@569 486 } else {
twisti@569 487 if (UseSSE == 0 && supports_3dnow()) {
twisti@569 488 tty->print("PREFETCHW");
twisti@569 489 } else if (UseSSE >= 1) {
twisti@569 490 if (AllocatePrefetchInstr == 0) {
twisti@569 491 tty->print("PREFETCHNTA");
twisti@569 492 } else if (AllocatePrefetchInstr == 1) {
twisti@569 493 tty->print("PREFETCHT0");
twisti@569 494 } else if (AllocatePrefetchInstr == 2) {
twisti@569 495 tty->print("PREFETCHT2");
twisti@569 496 } else if (AllocatePrefetchInstr == 3) {
twisti@569 497 tty->print("PREFETCHW");
twisti@569 498 }
twisti@569 499 }
twisti@569 500 if (AllocatePrefetchLines > 1) {
twisti@569 501 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
twisti@569 502 } else {
twisti@569 503 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
twisti@569 504 }
twisti@569 505 }
twisti@569 506
twisti@569 507 if (PrefetchCopyIntervalInBytes > 0) {
twisti@569 508 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
twisti@569 509 }
twisti@569 510 if (PrefetchScanIntervalInBytes > 0) {
twisti@569 511 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
twisti@569 512 }
twisti@569 513 if (PrefetchFieldsAhead > 0) {
twisti@569 514 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
twisti@569 515 }
twisti@569 516 }
twisti@569 517 #endif // !PRODUCT
twisti@569 518 }
twisti@569 519
twisti@569 520 void VM_Version::initialize() {
twisti@569 521 ResourceMark rm;
twisti@569 522 // Making this stub must be FIRST use of assembler
twisti@569 523
twisti@569 524 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
twisti@569 525 if (stub_blob == NULL) {
twisti@569 526 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
twisti@569 527 }
twisti@569 528 CodeBuffer c(stub_blob->instructions_begin(),
twisti@569 529 stub_blob->instructions_size());
twisti@569 530 VM_Version_StubGenerator g(&c);
twisti@569 531 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
twisti@569 532 g.generate_getPsrInfo());
twisti@569 533
twisti@569 534 get_processor_features();
twisti@569 535 }