annotate src/cpu/x86/vm/vm_version_x86.hpp @ 747:93c14e5562c4

6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}() Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions. Reviewed-by: kvn, never
author twisti
date Wed, 06 May 2009 00:27:52 -0700
parents c771b7f43bbf
children c18cbe5936b8
rev   line source
twisti@569 1 /*
twisti@569 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
twisti@569 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
twisti@569 4 *
twisti@569 5 * This code is free software; you can redistribute it and/or modify it
twisti@569 6 * under the terms of the GNU General Public License version 2 only, as
twisti@569 7 * published by the Free Software Foundation.
twisti@569 8 *
twisti@569 9 * This code is distributed in the hope that it will be useful, but WITHOUT
twisti@569 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
twisti@569 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
twisti@569 12 * version 2 for more details (a copy is included in the LICENSE file that
twisti@569 13 * accompanied this code).
twisti@569 14 *
twisti@569 15 * You should have received a copy of the GNU General Public License version
twisti@569 16 * 2 along with this work; if not, write to the Free Software Foundation,
twisti@569 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
twisti@569 18 *
twisti@569 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
twisti@569 20 * CA 95054 USA or visit www.sun.com if you need additional information or
twisti@569 21 * have any questions.
twisti@569 22 *
twisti@569 23 */
twisti@569 24
twisti@569 25 class VM_Version : public Abstract_VM_Version {
twisti@569 26 public:
twisti@569 27 // cpuid result register layouts. These are all unions of a uint32_t
twisti@569 28 // (in case anyone wants access to the register as a whole) and a bitfield.
twisti@569 29
twisti@569 30 union StdCpuid1Eax {
twisti@569 31 uint32_t value;
twisti@569 32 struct {
twisti@569 33 uint32_t stepping : 4,
twisti@569 34 model : 4,
twisti@569 35 family : 4,
twisti@569 36 proc_type : 2,
twisti@569 37 : 2,
twisti@569 38 ext_model : 4,
twisti@569 39 ext_family : 8,
twisti@569 40 : 4;
twisti@569 41 } bits;
twisti@569 42 };
twisti@569 43
twisti@569 44 union StdCpuid1Ebx { // example, unused
twisti@569 45 uint32_t value;
twisti@569 46 struct {
twisti@569 47 uint32_t brand_id : 8,
twisti@569 48 clflush_size : 8,
twisti@569 49 threads_per_cpu : 8,
twisti@569 50 apic_id : 8;
twisti@569 51 } bits;
twisti@569 52 };
twisti@569 53
twisti@569 54 union StdCpuid1Ecx {
twisti@569 55 uint32_t value;
twisti@569 56 struct {
twisti@569 57 uint32_t sse3 : 1,
twisti@569 58 : 2,
twisti@569 59 monitor : 1,
twisti@569 60 : 1,
twisti@569 61 vmx : 1,
twisti@569 62 : 1,
twisti@569 63 est : 1,
twisti@569 64 : 1,
twisti@569 65 ssse3 : 1,
twisti@569 66 cid : 1,
twisti@569 67 : 2,
twisti@569 68 cmpxchg16: 1,
twisti@569 69 : 4,
twisti@569 70 dca : 1,
twisti@569 71 sse4_1 : 1,
twisti@569 72 sse4_2 : 1,
twisti@620 73 : 2,
twisti@620 74 popcnt : 1,
twisti@620 75 : 8;
twisti@569 76 } bits;
twisti@569 77 };
twisti@569 78
twisti@569 79 union StdCpuid1Edx {
twisti@569 80 uint32_t value;
twisti@569 81 struct {
twisti@569 82 uint32_t : 4,
twisti@569 83 tsc : 1,
twisti@569 84 : 3,
twisti@569 85 cmpxchg8 : 1,
twisti@569 86 : 6,
twisti@569 87 cmov : 1,
twisti@569 88 : 7,
twisti@569 89 mmx : 1,
twisti@569 90 fxsr : 1,
twisti@569 91 sse : 1,
twisti@569 92 sse2 : 1,
twisti@569 93 : 1,
twisti@569 94 ht : 1,
twisti@569 95 : 3;
twisti@569 96 } bits;
twisti@569 97 };
twisti@569 98
twisti@569 99 union DcpCpuid4Eax {
twisti@569 100 uint32_t value;
twisti@569 101 struct {
twisti@569 102 uint32_t cache_type : 5,
twisti@569 103 : 21,
twisti@569 104 cores_per_cpu : 6;
twisti@569 105 } bits;
twisti@569 106 };
twisti@569 107
twisti@569 108 union DcpCpuid4Ebx {
twisti@569 109 uint32_t value;
twisti@569 110 struct {
twisti@569 111 uint32_t L1_line_size : 12,
twisti@569 112 partitions : 10,
twisti@569 113 associativity : 10;
twisti@569 114 } bits;
twisti@569 115 };
twisti@569 116
twisti@569 117 union ExtCpuid1Ecx {
twisti@569 118 uint32_t value;
twisti@569 119 struct {
twisti@569 120 uint32_t LahfSahf : 1,
twisti@569 121 CmpLegacy : 1,
twisti@569 122 : 4,
twisti@747 123 lzcnt : 1,
twisti@569 124 sse4a : 1,
twisti@569 125 misalignsse : 1,
twisti@569 126 prefetchw : 1,
twisti@569 127 : 22;
twisti@569 128 } bits;
twisti@569 129 };
twisti@569 130
twisti@569 131 union ExtCpuid1Edx {
twisti@569 132 uint32_t value;
twisti@569 133 struct {
twisti@569 134 uint32_t : 22,
twisti@569 135 mmx_amd : 1,
twisti@569 136 mmx : 1,
twisti@569 137 fxsr : 1,
twisti@569 138 : 4,
twisti@569 139 long_mode : 1,
twisti@569 140 tdnow2 : 1,
twisti@569 141 tdnow : 1;
twisti@569 142 } bits;
twisti@569 143 };
twisti@569 144
twisti@569 145 union ExtCpuid5Ex {
twisti@569 146 uint32_t value;
twisti@569 147 struct {
twisti@569 148 uint32_t L1_line_size : 8,
twisti@569 149 L1_tag_lines : 8,
twisti@569 150 L1_assoc : 8,
twisti@569 151 L1_size : 8;
twisti@569 152 } bits;
twisti@569 153 };
twisti@569 154
twisti@569 155 union ExtCpuid8Ecx {
twisti@569 156 uint32_t value;
twisti@569 157 struct {
twisti@569 158 uint32_t cores_per_cpu : 8,
twisti@569 159 : 24;
twisti@569 160 } bits;
twisti@569 161 };
twisti@569 162
twisti@569 163 protected:
twisti@569 164 static int _cpu;
twisti@569 165 static int _model;
twisti@569 166 static int _stepping;
twisti@569 167 static int _cpuFeatures; // features returned by the "cpuid" instruction
twisti@569 168 // 0 if this instruction is not available
twisti@569 169 static const char* _features_str;
twisti@569 170
twisti@569 171 enum {
twisti@569 172 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
twisti@569 173 CPU_CMOV = (1 << 1),
twisti@569 174 CPU_FXSR = (1 << 2),
twisti@569 175 CPU_HT = (1 << 3),
twisti@569 176 CPU_MMX = (1 << 4),
twisti@569 177 CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
twisti@569 178 CPU_SSE = (1 << 6),
twisti@569 179 CPU_SSE2 = (1 << 7),
twisti@569 180 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
twisti@569 181 CPU_SSSE3 = (1 << 9),
twisti@569 182 CPU_SSE4A = (1 << 10),
twisti@569 183 CPU_SSE4_1 = (1 << 11),
twisti@620 184 CPU_SSE4_2 = (1 << 12),
twisti@747 185 CPU_POPCNT = (1 << 13),
twisti@747 186 CPU_LZCNT = (1 << 14)
twisti@569 187 } cpuFeatureFlags;
twisti@569 188
twisti@569 189 // cpuid information block. All info derived from executing cpuid with
twisti@569 190 // various function numbers is stored here. Intel and AMD info is
twisti@569 191 // merged in this block: accessor methods disentangle it.
twisti@569 192 //
twisti@569 193 // The info block is laid out in subblocks of 4 dwords corresponding to
twisti@569 194 // eax, ebx, ecx and edx, whether or not they contain anything useful.
twisti@569 195 struct CpuidInfo {
twisti@569 196 // cpuid function 0
twisti@569 197 uint32_t std_max_function;
twisti@569 198 uint32_t std_vendor_name_0;
twisti@569 199 uint32_t std_vendor_name_1;
twisti@569 200 uint32_t std_vendor_name_2;
twisti@569 201
twisti@569 202 // cpuid function 1
twisti@569 203 StdCpuid1Eax std_cpuid1_eax;
twisti@569 204 StdCpuid1Ebx std_cpuid1_ebx;
twisti@569 205 StdCpuid1Ecx std_cpuid1_ecx;
twisti@569 206 StdCpuid1Edx std_cpuid1_edx;
twisti@569 207
twisti@569 208 // cpuid function 4 (deterministic cache parameters)
twisti@569 209 DcpCpuid4Eax dcp_cpuid4_eax;
twisti@569 210 DcpCpuid4Ebx dcp_cpuid4_ebx;
twisti@569 211 uint32_t dcp_cpuid4_ecx; // unused currently
twisti@569 212 uint32_t dcp_cpuid4_edx; // unused currently
twisti@569 213
twisti@569 214 // cpuid function 0x80000000 // example, unused
twisti@569 215 uint32_t ext_max_function;
twisti@569 216 uint32_t ext_vendor_name_0;
twisti@569 217 uint32_t ext_vendor_name_1;
twisti@569 218 uint32_t ext_vendor_name_2;
twisti@569 219
twisti@569 220 // cpuid function 0x80000001
twisti@569 221 uint32_t ext_cpuid1_eax; // reserved
twisti@569 222 uint32_t ext_cpuid1_ebx; // reserved
twisti@569 223 ExtCpuid1Ecx ext_cpuid1_ecx;
twisti@569 224 ExtCpuid1Edx ext_cpuid1_edx;
twisti@569 225
twisti@569 226 // cpuid functions 0x80000002 thru 0x80000004: example, unused
twisti@569 227 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
twisti@569 228 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
twisti@569 229 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
twisti@569 230
twisti@569 231 // cpuid function 0x80000005 //AMD L1, Intel reserved
twisti@569 232 uint32_t ext_cpuid5_eax; // unused currently
twisti@569 233 uint32_t ext_cpuid5_ebx; // reserved
twisti@569 234 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
twisti@569 235 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
twisti@569 236
twisti@569 237 // cpuid function 0x80000008
twisti@569 238 uint32_t ext_cpuid8_eax; // unused currently
twisti@569 239 uint32_t ext_cpuid8_ebx; // reserved
twisti@569 240 ExtCpuid8Ecx ext_cpuid8_ecx;
twisti@569 241 uint32_t ext_cpuid8_edx; // reserved
twisti@569 242 };
twisti@569 243
twisti@569 244 // The actual cpuid info block
twisti@569 245 static CpuidInfo _cpuid_info;
twisti@569 246
twisti@569 247 // Extractors and predicates
twisti@569 248 static uint32_t extended_cpu_family() {
twisti@569 249 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
twisti@569 250 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
twisti@569 251 return result;
twisti@569 252 }
twisti@569 253 static uint32_t extended_cpu_model() {
twisti@569 254 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
twisti@569 255 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
twisti@569 256 return result;
twisti@569 257 }
twisti@569 258 static uint32_t cpu_stepping() {
twisti@569 259 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
twisti@569 260 return result;
twisti@569 261 }
twisti@569 262 static uint logical_processor_count() {
twisti@569 263 uint result = threads_per_core();
twisti@569 264 return result;
twisti@569 265 }
twisti@569 266 static uint32_t feature_flags() {
twisti@569 267 uint32_t result = 0;
twisti@569 268 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
twisti@569 269 result |= CPU_CX8;
twisti@569 270 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
twisti@569 271 result |= CPU_CMOV;
twisti@569 272 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || is_amd() &&
twisti@569 273 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)
twisti@569 274 result |= CPU_FXSR;
twisti@569 275 // HT flag is set for multi-core processors also.
twisti@569 276 if (threads_per_core() > 1)
twisti@569 277 result |= CPU_HT;
twisti@569 278 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || is_amd() &&
twisti@569 279 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)
twisti@569 280 result |= CPU_MMX;
twisti@569 281 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
twisti@569 282 result |= CPU_SSE;
twisti@569 283 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
twisti@569 284 result |= CPU_SSE2;
twisti@569 285 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
twisti@569 286 result |= CPU_SSE3;
twisti@569 287 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
twisti@569 288 result |= CPU_SSSE3;
twisti@569 289 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
twisti@569 290 result |= CPU_SSE4_1;
twisti@569 291 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
twisti@569 292 result |= CPU_SSE4_2;
twisti@620 293 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
twisti@620 294 result |= CPU_POPCNT;
twisti@747 295
twisti@747 296 // AMD features.
twisti@747 297 if (is_amd()) {
twisti@747 298 if (_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0)
twisti@747 299 result |= CPU_3DNOW;
twisti@747 300 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
twisti@747 301 result |= CPU_LZCNT;
twisti@747 302 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
twisti@747 303 result |= CPU_SSE4A;
twisti@747 304 }
twisti@747 305
twisti@569 306 return result;
twisti@569 307 }
twisti@569 308
twisti@569 309 static void get_processor_features();
twisti@569 310
twisti@569 311 public:
twisti@569 312 // Offsets for cpuid asm stub
twisti@569 313 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
twisti@569 314 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
twisti@569 315 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
twisti@569 316 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
twisti@569 317 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
twisti@569 318 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
twisti@569 319
twisti@569 320 // Initialization
twisti@569 321 static void initialize();
twisti@569 322
twisti@569 323 // Asserts
twisti@569 324 static void assert_is_initialized() {
twisti@569 325 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
twisti@569 326 }
twisti@569 327
twisti@569 328 //
twisti@569 329 // Processor family:
twisti@569 330 // 3 - 386
twisti@569 331 // 4 - 486
twisti@569 332 // 5 - Pentium
twisti@569 333 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
twisti@569 334 // Pentium M, Core Solo, Core Duo, Core2 Duo
twisti@569 335 // family 6 model: 9, 13, 14, 15
twisti@569 336 // 0x0f - Pentium 4, Opteron
twisti@569 337 //
twisti@569 338 // Note: The cpu family should be used to select between
twisti@569 339 // instruction sequences which are valid on all Intel
twisti@569 340 // processors. Use the feature test functions below to
twisti@569 341 // determine whether a particular instruction is supported.
twisti@569 342 //
twisti@569 343 static int cpu_family() { return _cpu;}
twisti@569 344 static bool is_P6() { return cpu_family() >= 6; }
twisti@569 345
twisti@569 346 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
twisti@569 347 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
twisti@569 348
twisti@569 349 static uint cores_per_cpu() {
twisti@569 350 uint result = 1;
twisti@569 351 if (is_intel()) {
twisti@569 352 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
twisti@569 353 } else if (is_amd()) {
twisti@569 354 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
twisti@569 355 }
twisti@569 356 return result;
twisti@569 357 }
twisti@569 358
twisti@569 359 static uint threads_per_core() {
twisti@569 360 uint result = 1;
twisti@569 361 if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
twisti@569 362 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
twisti@569 363 cores_per_cpu();
twisti@569 364 }
twisti@569 365 return result;
twisti@569 366 }
twisti@569 367
twisti@569 368 static intx L1_data_cache_line_size() {
twisti@569 369 intx result = 0;
twisti@569 370 if (is_intel()) {
twisti@569 371 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
twisti@569 372 } else if (is_amd()) {
twisti@569 373 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
twisti@569 374 }
twisti@569 375 if (result < 32) // not defined ?
twisti@569 376 result = 32; // 32 bytes by default on x86 and other x64
twisti@569 377 return result;
twisti@569 378 }
twisti@569 379
twisti@569 380 //
twisti@569 381 // Feature identification
twisti@569 382 //
twisti@569 383 static bool supports_cpuid() { return _cpuFeatures != 0; }
twisti@569 384 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
twisti@569 385 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
twisti@569 386 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
twisti@569 387 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
twisti@569 388 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
twisti@569 389 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
twisti@569 390 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
twisti@569 391 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
twisti@569 392 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
twisti@569 393 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
twisti@569 394 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
twisti@620 395 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
twisti@569 396 //
twisti@569 397 // AMD features
twisti@569 398 //
twisti@569 399 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
twisti@569 400 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
twisti@569 401 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; }
twisti@747 402 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
twisti@569 403 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
twisti@569 404
twisti@569 405 static bool supports_compare_and_exchange() { return true; }
twisti@569 406
twisti@569 407 static const char* cpu_features() { return _features_str; }
twisti@569 408
twisti@569 409 static intx allocate_prefetch_distance() {
twisti@569 410 // This method should be called before allocate_prefetch_style().
twisti@569 411 //
twisti@569 412 // Hardware prefetching (distance/size in bytes):
twisti@569 413 // Pentium 3 - 64 / 32
twisti@569 414 // Pentium 4 - 256 / 128
twisti@569 415 // Athlon - 64 / 32 ????
twisti@569 416 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
twisti@569 417 // Core - 128 / 64
twisti@569 418 //
twisti@569 419 // Software prefetching (distance in bytes / instruction with best score):
twisti@569 420 // Pentium 3 - 128 / prefetchnta
twisti@569 421 // Pentium 4 - 512 / prefetchnta
twisti@569 422 // Athlon - 128 / prefetchnta
twisti@569 423 // Opteron - 256 / prefetchnta
twisti@569 424 // Core - 256 / prefetchnta
twisti@569 425 // It will be used only when AllocatePrefetchStyle > 0
twisti@569 426
twisti@569 427 intx count = AllocatePrefetchDistance;
twisti@569 428 if (count < 0) { // default ?
twisti@569 429 if (is_amd()) { // AMD
twisti@569 430 if (supports_sse2())
twisti@569 431 count = 256; // Opteron
twisti@569 432 else
twisti@569 433 count = 128; // Athlon
twisti@569 434 } else { // Intel
twisti@569 435 if (supports_sse2())
twisti@569 436 if (cpu_family() == 6) {
twisti@569 437 count = 256; // Pentium M, Core, Core2
twisti@569 438 } else {
twisti@569 439 count = 512; // Pentium 4
twisti@569 440 }
twisti@569 441 else
twisti@569 442 count = 128; // Pentium 3 (and all other old CPUs)
twisti@569 443 }
twisti@569 444 }
twisti@569 445 return count;
twisti@569 446 }
twisti@569 447 static intx allocate_prefetch_style() {
twisti@569 448 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
twisti@569 449 // Return 0 if AllocatePrefetchDistance was not defined.
twisti@569 450 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
twisti@569 451 }
twisti@569 452
twisti@569 453 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
twisti@569 454 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
twisti@569 455 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
twisti@569 456 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
twisti@569 457
twisti@569 458 // gc copy/scan is disabled if prefetchw isn't supported, because
twisti@569 459 // Prefetch::write emits an inlined prefetchw on Linux.
twisti@569 460 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
twisti@569 461 // The used prefetcht0 instruction works for both amd64 and em64t.
twisti@569 462 static intx prefetch_copy_interval_in_bytes() {
twisti@569 463 intx interval = PrefetchCopyIntervalInBytes;
twisti@569 464 return interval >= 0 ? interval : 576;
twisti@569 465 }
twisti@569 466 static intx prefetch_scan_interval_in_bytes() {
twisti@569 467 intx interval = PrefetchScanIntervalInBytes;
twisti@569 468 return interval >= 0 ? interval : 576;
twisti@569 469 }
twisti@569 470 static intx prefetch_fields_ahead() {
twisti@569 471 intx count = PrefetchFieldsAhead;
twisti@569 472 return count >= 0 ? count : 1;
twisti@569 473 }
twisti@569 474 };