annotate src/share/vm/c1/c1_LIR.cpp @ 2718:5cceda753a4a

7091764: Tiered: enable aastore profiling Summary: Turn on aastore profiling Reviewed-by: jrose, twisti
author iveresov
date Mon, 19 Sep 2011 15:21:03 -0700
parents 10ee2b297ccd
children b642b49f9738
rev   line source
duke@0 1 /*
never@2053 2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1472 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 * or visit www.oracle.com if you need additional information or have any
trims@1472 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1879 25 #include "precompiled.hpp"
stefank@1879 26 #include "c1/c1_InstructionPrinter.hpp"
stefank@1879 27 #include "c1/c1_LIR.hpp"
stefank@1879 28 #include "c1/c1_LIRAssembler.hpp"
stefank@1879 29 #include "c1/c1_ValueStack.hpp"
stefank@1879 30 #include "ci/ciInstance.hpp"
stefank@1879 31 #include "runtime/sharedRuntime.hpp"
duke@0 32
duke@0 33 Register LIR_OprDesc::as_register() const {
duke@0 34 return FrameMap::cpu_rnr2reg(cpu_regnr());
duke@0 35 }
duke@0 36
duke@0 37 Register LIR_OprDesc::as_register_lo() const {
duke@0 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
duke@0 39 }
duke@0 40
duke@0 41 Register LIR_OprDesc::as_register_hi() const {
duke@0 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
duke@0 43 }
duke@0 44
never@304 45 #if defined(X86)
duke@0 46
duke@0 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
duke@0 48 return FrameMap::nr2xmmreg(xmm_regnr());
duke@0 49 }
duke@0 50
duke@0 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
duke@0 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
duke@0 53 return FrameMap::nr2xmmreg(xmm_regnrLo());
duke@0 54 }
duke@0 55
never@304 56 #endif // X86
duke@0 57
bobv@1601 58 #if defined(SPARC) || defined(PPC)
duke@0 59
duke@0 60 FloatRegister LIR_OprDesc::as_float_reg() const {
duke@0 61 return FrameMap::nr2floatreg(fpu_regnr());
duke@0 62 }
duke@0 63
duke@0 64 FloatRegister LIR_OprDesc::as_double_reg() const {
duke@0 65 return FrameMap::nr2floatreg(fpu_regnrHi());
duke@0 66 }
duke@0 67
duke@0 68 #endif
duke@0 69
bobv@1601 70 #ifdef ARM
bobv@1601 71
bobv@1601 72 FloatRegister LIR_OprDesc::as_float_reg() const {
bobv@1601 73 return as_FloatRegister(fpu_regnr());
bobv@1601 74 }
bobv@1601 75
bobv@1601 76 FloatRegister LIR_OprDesc::as_double_reg() const {
bobv@1601 77 return as_FloatRegister(fpu_regnrLo());
bobv@1601 78 }
bobv@1601 79
bobv@1601 80 #endif
bobv@1601 81
bobv@1601 82
duke@0 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
duke@0 84
duke@0 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
duke@0 86 ValueTag tag = type->tag();
duke@0 87 switch (tag) {
duke@0 88 case objectTag : {
duke@0 89 ClassConstant* c = type->as_ClassConstant();
duke@0 90 if (c != NULL && !c->value()->is_loaded()) {
duke@0 91 return LIR_OprFact::oopConst(NULL);
duke@0 92 } else {
duke@0 93 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
duke@0 94 }
duke@0 95 }
roland@1297 96 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
duke@0 97 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
duke@0 98 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
duke@0 99 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
duke@0 100 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
never@304 101 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
duke@0 102 }
duke@0 103 }
duke@0 104
duke@0 105
duke@0 106 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
duke@0 107 switch (type->tag()) {
duke@0 108 case objectTag: return LIR_OprFact::oopConst(NULL);
roland@1297 109 case addressTag:return LIR_OprFact::addressConst(0);
duke@0 110 case intTag: return LIR_OprFact::intConst(0);
duke@0 111 case floatTag: return LIR_OprFact::floatConst(0.0);
duke@0 112 case longTag: return LIR_OprFact::longConst(0);
duke@0 113 case doubleTag: return LIR_OprFact::doubleConst(0.0);
never@304 114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
duke@0 115 }
duke@0 116 return illegalOpr;
duke@0 117 }
duke@0 118
duke@0 119
duke@0 120
duke@0 121 //---------------------------------------------------
duke@0 122
duke@0 123
duke@0 124 LIR_Address::Scale LIR_Address::scale(BasicType type) {
kvn@29 125 int elem_size = type2aelembytes(type);
duke@0 126 switch (elem_size) {
duke@0 127 case 1: return LIR_Address::times_1;
duke@0 128 case 2: return LIR_Address::times_2;
duke@0 129 case 4: return LIR_Address::times_4;
duke@0 130 case 8: return LIR_Address::times_8;
duke@0 131 }
duke@0 132 ShouldNotReachHere();
duke@0 133 return LIR_Address::times_1;
duke@0 134 }
duke@0 135
duke@0 136
duke@0 137 #ifndef PRODUCT
duke@0 138 void LIR_Address::verify() const {
bobv@1601 139 #if defined(SPARC) || defined(PPC)
bobv@1601 140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
duke@0 141 assert(disp() == 0 || index()->is_illegal(), "can't have both");
duke@0 142 #endif
bobv@1601 143 #ifdef ARM
bobv@1601 144 assert(disp() == 0 || index()->is_illegal(), "can't have both");
bdelsart@2706 145 // Note: offsets higher than 4096 must not be rejected here. They can
bdelsart@2706 146 // be handled by the back-end or will be rejected if not.
bobv@1601 147 #endif
duke@0 148 #ifdef _LP64
duke@0 149 assert(base()->is_cpu_register(), "wrong base operand");
duke@0 150 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
duke@0 151 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
duke@0 152 "wrong type for addresses");
duke@0 153 #else
duke@0 154 assert(base()->is_single_cpu(), "wrong base operand");
duke@0 155 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
duke@0 156 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
duke@0 157 "wrong type for addresses");
duke@0 158 #endif
duke@0 159 }
duke@0 160 #endif
duke@0 161
duke@0 162
duke@0 163 //---------------------------------------------------
duke@0 164
duke@0 165 char LIR_OprDesc::type_char(BasicType t) {
duke@0 166 switch (t) {
duke@0 167 case T_ARRAY:
duke@0 168 t = T_OBJECT;
duke@0 169 case T_BOOLEAN:
duke@0 170 case T_CHAR:
duke@0 171 case T_FLOAT:
duke@0 172 case T_DOUBLE:
duke@0 173 case T_BYTE:
duke@0 174 case T_SHORT:
duke@0 175 case T_INT:
duke@0 176 case T_LONG:
duke@0 177 case T_OBJECT:
duke@0 178 case T_ADDRESS:
duke@0 179 case T_VOID:
duke@0 180 return ::type2char(t);
duke@0 181
duke@0 182 case T_ILLEGAL:
duke@0 183 return '?';
duke@0 184
duke@0 185 default:
duke@0 186 ShouldNotReachHere();
never@304 187 return '?';
duke@0 188 }
duke@0 189 }
duke@0 190
duke@0 191 #ifndef PRODUCT
duke@0 192 void LIR_OprDesc::validate_type() const {
duke@0 193
duke@0 194 #ifdef ASSERT
duke@0 195 if (!is_pointer() && !is_illegal()) {
duke@0 196 switch (as_BasicType(type_field())) {
duke@0 197 case T_LONG:
bobv@1601 198 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
bobv@1601 199 size_field() == double_size, "must match");
duke@0 200 break;
duke@0 201 case T_FLOAT:
bobv@1601 202 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
bobv@1601 203 assert((kind_field() == fpu_register || kind_field() == stack_value
bobv@1601 204 ARM_ONLY(|| kind_field() == cpu_register)
bobv@1601 205 PPC_ONLY(|| kind_field() == cpu_register) ) &&
bobv@1601 206 size_field() == single_size, "must match");
duke@0 207 break;
duke@0 208 case T_DOUBLE:
bobv@1601 209 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
bobv@1601 210 assert((kind_field() == fpu_register || kind_field() == stack_value
bobv@1601 211 ARM_ONLY(|| kind_field() == cpu_register)
bobv@1601 212 PPC_ONLY(|| kind_field() == cpu_register) ) &&
bobv@1601 213 size_field() == double_size, "must match");
duke@0 214 break;
duke@0 215 case T_BOOLEAN:
duke@0 216 case T_CHAR:
duke@0 217 case T_BYTE:
duke@0 218 case T_SHORT:
duke@0 219 case T_INT:
never@1736 220 case T_ADDRESS:
duke@0 221 case T_OBJECT:
duke@0 222 case T_ARRAY:
bobv@1601 223 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
bobv@1601 224 size_field() == single_size, "must match");
duke@0 225 break;
duke@0 226
duke@0 227 case T_ILLEGAL:
duke@0 228 // XXX TKR also means unknown right now
duke@0 229 // assert(is_illegal(), "must match");
duke@0 230 break;
duke@0 231
duke@0 232 default:
duke@0 233 ShouldNotReachHere();
duke@0 234 }
duke@0 235 }
duke@0 236 #endif
duke@0 237
duke@0 238 }
duke@0 239 #endif // PRODUCT
duke@0 240
duke@0 241
duke@0 242 bool LIR_OprDesc::is_oop() const {
duke@0 243 if (is_pointer()) {
duke@0 244 return pointer()->is_oop_pointer();
duke@0 245 } else {
duke@0 246 OprType t= type_field();
duke@0 247 assert(t != unknown_type, "not set");
duke@0 248 return t == object_type;
duke@0 249 }
duke@0 250 }
duke@0 251
duke@0 252
duke@0 253
duke@0 254 void LIR_Op2::verify() const {
duke@0 255 #ifdef ASSERT
duke@0 256 switch (code()) {
duke@0 257 case lir_cmove:
duke@0 258 break;
duke@0 259
duke@0 260 default:
duke@0 261 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
duke@0 262 "can't produce oops from arith");
duke@0 263 }
duke@0 264
duke@0 265 if (TwoOperandLIRForm) {
duke@0 266 switch (code()) {
duke@0 267 case lir_add:
duke@0 268 case lir_sub:
duke@0 269 case lir_mul:
duke@0 270 case lir_mul_strictfp:
duke@0 271 case lir_div:
duke@0 272 case lir_div_strictfp:
duke@0 273 case lir_rem:
duke@0 274 case lir_logic_and:
duke@0 275 case lir_logic_or:
duke@0 276 case lir_logic_xor:
duke@0 277 case lir_shl:
duke@0 278 case lir_shr:
duke@0 279 assert(in_opr1() == result_opr(), "opr1 and result must match");
duke@0 280 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
duke@0 281 break;
duke@0 282
duke@0 283 // special handling for lir_ushr because of write barriers
duke@0 284 case lir_ushr:
duke@0 285 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
duke@0 286 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
duke@0 287 break;
duke@0 288
duke@0 289 }
duke@0 290 }
duke@0 291 #endif
duke@0 292 }
duke@0 293
duke@0 294
duke@0 295 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
duke@0 296 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
duke@0 297 , _cond(cond)
duke@0 298 , _type(type)
duke@0 299 , _label(block->label())
duke@0 300 , _block(block)
duke@0 301 , _ublock(NULL)
duke@0 302 , _stub(NULL) {
duke@0 303 }
duke@0 304
duke@0 305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
duke@0 306 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
duke@0 307 , _cond(cond)
duke@0 308 , _type(type)
duke@0 309 , _label(stub->entry())
duke@0 310 , _block(NULL)
duke@0 311 , _ublock(NULL)
duke@0 312 , _stub(stub) {
duke@0 313 }
duke@0 314
duke@0 315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
duke@0 316 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
duke@0 317 , _cond(cond)
duke@0 318 , _type(type)
duke@0 319 , _label(block->label())
duke@0 320 , _block(block)
duke@0 321 , _ublock(ublock)
duke@0 322 , _stub(NULL)
duke@0 323 {
duke@0 324 }
duke@0 325
duke@0 326 void LIR_OpBranch::change_block(BlockBegin* b) {
duke@0 327 assert(_block != NULL, "must have old block");
duke@0 328 assert(_block->label() == label(), "must be equal");
duke@0 329
duke@0 330 _block = b;
duke@0 331 _label = b->label();
duke@0 332 }
duke@0 333
duke@0 334 void LIR_OpBranch::change_ublock(BlockBegin* b) {
duke@0 335 assert(_ublock != NULL, "must have old block");
duke@0 336 _ublock = b;
duke@0 337 }
duke@0 338
duke@0 339 void LIR_OpBranch::negate_cond() {
duke@0 340 switch (_cond) {
duke@0 341 case lir_cond_equal: _cond = lir_cond_notEqual; break;
duke@0 342 case lir_cond_notEqual: _cond = lir_cond_equal; break;
duke@0 343 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
duke@0 344 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
duke@0 345 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
duke@0 346 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
duke@0 347 default: ShouldNotReachHere();
duke@0 348 }
duke@0 349 }
duke@0 350
duke@0 351
duke@0 352 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
duke@0 353 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
duke@0 354 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
iveresov@1703 355 CodeStub* stub)
iveresov@1703 356
duke@0 357 : LIR_Op(code, result, NULL)
duke@0 358 , _object(object)
duke@0 359 , _array(LIR_OprFact::illegalOpr)
duke@0 360 , _klass(klass)
duke@0 361 , _tmp1(tmp1)
duke@0 362 , _tmp2(tmp2)
duke@0 363 , _tmp3(tmp3)
duke@0 364 , _fast_check(fast_check)
duke@0 365 , _stub(stub)
duke@0 366 , _info_for_patch(info_for_patch)
duke@0 367 , _info_for_exception(info_for_exception)
iveresov@1703 368 , _profiled_method(NULL)
iveresov@1703 369 , _profiled_bci(-1)
iveresov@1703 370 , _should_profile(false)
iveresov@1703 371 {
duke@0 372 if (code == lir_checkcast) {
duke@0 373 assert(info_for_exception != NULL, "checkcast throws exceptions");
duke@0 374 } else if (code == lir_instanceof) {
duke@0 375 assert(info_for_exception == NULL, "instanceof throws no exceptions");
duke@0 376 } else {
duke@0 377 ShouldNotReachHere();
duke@0 378 }
duke@0 379 }
duke@0 380
duke@0 381
duke@0 382
iveresov@1703 383 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
duke@0 384 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
duke@0 385 , _object(object)
duke@0 386 , _array(array)
duke@0 387 , _klass(NULL)
duke@0 388 , _tmp1(tmp1)
duke@0 389 , _tmp2(tmp2)
duke@0 390 , _tmp3(tmp3)
duke@0 391 , _fast_check(false)
duke@0 392 , _stub(NULL)
duke@0 393 , _info_for_patch(NULL)
duke@0 394 , _info_for_exception(info_for_exception)
iveresov@1703 395 , _profiled_method(NULL)
iveresov@1703 396 , _profiled_bci(-1)
iveresov@1703 397 , _should_profile(false)
iveresov@1703 398 {
duke@0 399 if (code == lir_store_check) {
never@2053 400 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
duke@0 401 assert(info_for_exception != NULL, "store_check throws exceptions");
duke@0 402 } else {
duke@0 403 ShouldNotReachHere();
duke@0 404 }
duke@0 405 }
duke@0 406
duke@0 407
duke@0 408 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
duke@0 409 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
duke@0 410 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
duke@0 411 , _tmp(tmp)
duke@0 412 , _src(src)
duke@0 413 , _src_pos(src_pos)
duke@0 414 , _dst(dst)
duke@0 415 , _dst_pos(dst_pos)
duke@0 416 , _flags(flags)
duke@0 417 , _expected_type(expected_type)
duke@0 418 , _length(length) {
duke@0 419 _stub = new ArrayCopyStub(this);
duke@0 420 }
duke@0 421
duke@0 422
duke@0 423 //-------------------verify--------------------------
duke@0 424
duke@0 425 void LIR_Op1::verify() const {
duke@0 426 switch(code()) {
duke@0 427 case lir_move:
duke@0 428 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
duke@0 429 break;
duke@0 430 case lir_null_check:
duke@0 431 assert(in_opr()->is_register(), "must be");
duke@0 432 break;
duke@0 433 case lir_return:
duke@0 434 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
duke@0 435 break;
duke@0 436 }
duke@0 437 }
duke@0 438
duke@0 439 void LIR_OpRTCall::verify() const {
duke@0 440 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
duke@0 441 }
duke@0 442
duke@0 443 //-------------------visits--------------------------
duke@0 444
duke@0 445 // complete rework of LIR instruction visitor.
duke@0 446 // The virtual calls for each instruction type is replaced by a big
duke@0 447 // switch that adds the operands for each instruction
duke@0 448
duke@0 449 void LIR_OpVisitState::visit(LIR_Op* op) {
duke@0 450 // copy information from the LIR_Op
duke@0 451 reset();
duke@0 452 set_op(op);
duke@0 453
duke@0 454 switch (op->code()) {
duke@0 455
duke@0 456 // LIR_Op0
duke@0 457 case lir_word_align: // result and info always invalid
duke@0 458 case lir_backwardbranch_target: // result and info always invalid
duke@0 459 case lir_build_frame: // result and info always invalid
duke@0 460 case lir_fpop_raw: // result and info always invalid
duke@0 461 case lir_24bit_FPU: // result and info always invalid
duke@0 462 case lir_reset_FPU: // result and info always invalid
duke@0 463 case lir_breakpoint: // result and info always invalid
duke@0 464 case lir_membar: // result and info always invalid
duke@0 465 case lir_membar_acquire: // result and info always invalid
duke@0 466 case lir_membar_release: // result and info always invalid
duke@0 467 {
duke@0 468 assert(op->as_Op0() != NULL, "must be");
duke@0 469 assert(op->_info == NULL, "info not used by this instruction");
duke@0 470 assert(op->_result->is_illegal(), "not used");
duke@0 471 break;
duke@0 472 }
duke@0 473
duke@0 474 case lir_nop: // may have info, result always invalid
duke@0 475 case lir_std_entry: // may have result, info always invalid
duke@0 476 case lir_osr_entry: // may have result, info always invalid
duke@0 477 case lir_get_thread: // may have result, info always invalid
duke@0 478 {
duke@0 479 assert(op->as_Op0() != NULL, "must be");
duke@0 480 if (op->_info != NULL) do_info(op->_info);
duke@0 481 if (op->_result->is_valid()) do_output(op->_result);
duke@0 482 break;
duke@0 483 }
duke@0 484
duke@0 485
duke@0 486 // LIR_OpLabel
duke@0 487 case lir_label: // result and info always invalid
duke@0 488 {
duke@0 489 assert(op->as_OpLabel() != NULL, "must be");
duke@0 490 assert(op->_info == NULL, "info not used by this instruction");
duke@0 491 assert(op->_result->is_illegal(), "not used");
duke@0 492 break;
duke@0 493 }
duke@0 494
duke@0 495
duke@0 496 // LIR_Op1
duke@0 497 case lir_fxch: // input always valid, result and info always invalid
duke@0 498 case lir_fld: // input always valid, result and info always invalid
duke@0 499 case lir_ffree: // input always valid, result and info always invalid
duke@0 500 case lir_push: // input always valid, result and info always invalid
duke@0 501 case lir_pop: // input always valid, result and info always invalid
duke@0 502 case lir_return: // input always valid, result and info always invalid
duke@0 503 case lir_leal: // input and result always valid, info always invalid
duke@0 504 case lir_neg: // input and result always valid, info always invalid
duke@0 505 case lir_monaddr: // input and result always valid, info always invalid
duke@0 506 case lir_null_check: // input and info always valid, result always invalid
duke@0 507 case lir_move: // input and result always valid, may have info
iveresov@1703 508 case lir_pack64: // input and result always valid
iveresov@1703 509 case lir_unpack64: // input and result always valid
duke@0 510 case lir_prefetchr: // input always valid, result and info always invalid
duke@0 511 case lir_prefetchw: // input always valid, result and info always invalid
duke@0 512 {
duke@0 513 assert(op->as_Op1() != NULL, "must be");
duke@0 514 LIR_Op1* op1 = (LIR_Op1*)op;
duke@0 515
duke@0 516 if (op1->_info) do_info(op1->_info);
duke@0 517 if (op1->_opr->is_valid()) do_input(op1->_opr);
duke@0 518 if (op1->_result->is_valid()) do_output(op1->_result);
duke@0 519
duke@0 520 break;
duke@0 521 }
duke@0 522
duke@0 523 case lir_safepoint:
duke@0 524 {
duke@0 525 assert(op->as_Op1() != NULL, "must be");
duke@0 526 LIR_Op1* op1 = (LIR_Op1*)op;
duke@0 527
duke@0 528 assert(op1->_info != NULL, ""); do_info(op1->_info);
duke@0 529 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
duke@0 530 assert(op1->_result->is_illegal(), "safepoint does not produce value");
duke@0 531
duke@0 532 break;
duke@0 533 }
duke@0 534
duke@0 535 // LIR_OpConvert;
duke@0 536 case lir_convert: // input and result always valid, info always invalid
duke@0 537 {
duke@0 538 assert(op->as_OpConvert() != NULL, "must be");
duke@0 539 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
duke@0 540
duke@0 541 assert(opConvert->_info == NULL, "must be");
duke@0 542 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
duke@0 543 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
bobv@1601 544 #ifdef PPC
bobv@1601 545 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
bobv@1601 546 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
bobv@1601 547 #endif
duke@0 548 do_stub(opConvert->_stub);
duke@0 549
duke@0 550 break;
duke@0 551 }
duke@0 552
duke@0 553 // LIR_OpBranch;
duke@0 554 case lir_branch: // may have info, input and result register always invalid
duke@0 555 case lir_cond_float_branch: // may have info, input and result register always invalid
duke@0 556 {
duke@0 557 assert(op->as_OpBranch() != NULL, "must be");
duke@0 558 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
duke@0 559
duke@0 560 if (opBranch->_info != NULL) do_info(opBranch->_info);
duke@0 561 assert(opBranch->_result->is_illegal(), "not used");
duke@0 562 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
duke@0 563
duke@0 564 break;
duke@0 565 }
duke@0 566
duke@0 567
duke@0 568 // LIR_OpAllocObj
duke@0 569 case lir_alloc_object:
duke@0 570 {
duke@0 571 assert(op->as_OpAllocObj() != NULL, "must be");
duke@0 572 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
duke@0 573
duke@0 574 if (opAllocObj->_info) do_info(opAllocObj->_info);
bobv@1601 575 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
bobv@1601 576 do_temp(opAllocObj->_opr);
bobv@1601 577 }
duke@0 578 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
duke@0 579 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
duke@0 580 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
duke@0 581 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
duke@0 582 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
duke@0 583 do_stub(opAllocObj->_stub);
duke@0 584 break;
duke@0 585 }
duke@0 586
duke@0 587
duke@0 588 // LIR_OpRoundFP;
duke@0 589 case lir_roundfp: {
duke@0 590 assert(op->as_OpRoundFP() != NULL, "must be");
duke@0 591 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
duke@0 592
duke@0 593 assert(op->_info == NULL, "info not used by this instruction");
duke@0 594 assert(opRoundFP->_tmp->is_illegal(), "not used");
duke@0 595 do_input(opRoundFP->_opr);
duke@0 596 do_output(opRoundFP->_result);
duke@0 597
duke@0 598 break;
duke@0 599 }
duke@0 600
duke@0 601
duke@0 602 // LIR_Op2
duke@0 603 case lir_cmp:
duke@0 604 case lir_cmp_l2i:
duke@0 605 case lir_ucmp_fd2i:
duke@0 606 case lir_cmp_fd2i:
duke@0 607 case lir_add:
duke@0 608 case lir_sub:
duke@0 609 case lir_mul:
duke@0 610 case lir_div:
duke@0 611 case lir_rem:
duke@0 612 case lir_sqrt:
duke@0 613 case lir_abs:
duke@0 614 case lir_logic_and:
duke@0 615 case lir_logic_or:
duke@0 616 case lir_logic_xor:
duke@0 617 case lir_shl:
duke@0 618 case lir_shr:
duke@0 619 case lir_ushr:
duke@0 620 {
duke@0 621 assert(op->as_Op2() != NULL, "must be");
duke@0 622 LIR_Op2* op2 = (LIR_Op2*)op;
duke@0 623
duke@0 624 if (op2->_info) do_info(op2->_info);
duke@0 625 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
duke@0 626 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
duke@0 627 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
duke@0 628 if (op2->_result->is_valid()) do_output(op2->_result);
duke@0 629
duke@0 630 break;
duke@0 631 }
duke@0 632
duke@0 633 // special handling for cmove: right input operand must not be equal
duke@0 634 // to the result operand, otherwise the backend fails
duke@0 635 case lir_cmove:
duke@0 636 {
duke@0 637 assert(op->as_Op2() != NULL, "must be");
duke@0 638 LIR_Op2* op2 = (LIR_Op2*)op;
duke@0 639
duke@0 640 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used");
duke@0 641 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
duke@0 642
duke@0 643 do_input(op2->_opr1);
duke@0 644 do_input(op2->_opr2);
duke@0 645 do_temp(op2->_opr2);
duke@0 646 do_output(op2->_result);
duke@0 647
duke@0 648 break;
duke@0 649 }
duke@0 650
duke@0 651 // vspecial handling for strict operations: register input operands
duke@0 652 // as temp to guarantee that they do not overlap with other
duke@0 653 // registers
duke@0 654 case lir_mul_strictfp:
duke@0 655 case lir_div_strictfp:
duke@0 656 {
duke@0 657 assert(op->as_Op2() != NULL, "must be");
duke@0 658 LIR_Op2* op2 = (LIR_Op2*)op;
duke@0 659
duke@0 660 assert(op2->_info == NULL, "not used");
duke@0 661 assert(op2->_opr1->is_valid(), "used");
duke@0 662 assert(op2->_opr2->is_valid(), "used");
duke@0 663 assert(op2->_result->is_valid(), "used");
duke@0 664
duke@0 665 do_input(op2->_opr1); do_temp(op2->_opr1);
duke@0 666 do_input(op2->_opr2); do_temp(op2->_opr2);
duke@0 667 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
duke@0 668 do_output(op2->_result);
duke@0 669
duke@0 670 break;
duke@0 671 }
duke@0 672
never@1378 673 case lir_throw: {
duke@0 674 assert(op->as_Op2() != NULL, "must be");
duke@0 675 LIR_Op2* op2 = (LIR_Op2*)op;
duke@0 676
duke@0 677 if (op2->_info) do_info(op2->_info);
duke@0 678 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
duke@0 679 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
duke@0 680 assert(op2->_result->is_illegal(), "no result");
duke@0 681
duke@0 682 break;
duke@0 683 }
duke@0 684
never@1378 685 case lir_unwind: {
never@1378 686 assert(op->as_Op1() != NULL, "must be");
never@1378 687 LIR_Op1* op1 = (LIR_Op1*)op;
never@1378 688
never@1378 689 assert(op1->_info == NULL, "no info");
never@1378 690 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
never@1378 691 assert(op1->_result->is_illegal(), "no result");
never@1378 692
never@1378 693 break;
never@1378 694 }
never@1378 695
duke@0 696
duke@0 697 case lir_tan:
duke@0 698 case lir_sin:
never@953 699 case lir_cos:
never@953 700 case lir_log:
never@953 701 case lir_log10: {
duke@0 702 assert(op->as_Op2() != NULL, "must be");
duke@0 703 LIR_Op2* op2 = (LIR_Op2*)op;
duke@0 704
never@953 705 // On x86 tan/sin/cos need two temporary fpu stack slots and
never@953 706 // log/log10 need one so handle opr2 and tmp as temp inputs.
never@953 707 // Register input operand as temp to guarantee that it doesn't
never@953 708 // overlap with the input.
duke@0 709 assert(op2->_info == NULL, "not used");
duke@0 710 assert(op2->_opr1->is_valid(), "used");
duke@0 711 do_input(op2->_opr1); do_temp(op2->_opr1);
duke@0 712
duke@0 713 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
duke@0 714 if (op2->_tmp->is_valid()) do_temp(op2->_tmp);
duke@0 715 if (op2->_result->is_valid()) do_output(op2->_result);
duke@0 716
duke@0 717 break;
duke@0 718 }
duke@0 719
duke@0 720
duke@0 721 // LIR_Op3
duke@0 722 case lir_idiv:
duke@0 723 case lir_irem: {
duke@0 724 assert(op->as_Op3() != NULL, "must be");
duke@0 725 LIR_Op3* op3= (LIR_Op3*)op;
duke@0 726
duke@0 727 if (op3->_info) do_info(op3->_info);
duke@0 728 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
duke@0 729
duke@0 730 // second operand is input and temp, so ensure that second operand
duke@0 731 // and third operand get not the same register
duke@0 732 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
duke@0 733 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
duke@0 734 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
duke@0 735
duke@0 736 if (op3->_result->is_valid()) do_output(op3->_result);
duke@0 737
duke@0 738 break;
duke@0 739 }
duke@0 740
duke@0 741
duke@0 742 // LIR_OpJavaCall
duke@0 743 case lir_static_call:
duke@0 744 case lir_optvirtual_call:
duke@0 745 case lir_icvirtual_call:
twisti@1295 746 case lir_virtual_call:
twisti@1295 747 case lir_dynamic_call: {
twisti@1295 748 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
twisti@1295 749 assert(opJavaCall != NULL, "must be");
duke@0 750
duke@0 751 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
duke@0 752
duke@0 753 // only visit register parameters
duke@0 754 int n = opJavaCall->_arguments->length();
duke@0 755 for (int i = 0; i < n; i++) {
duke@0 756 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
duke@0 757 do_input(*opJavaCall->_arguments->adr_at(i));
duke@0 758 }
duke@0 759 }
duke@0 760
duke@0 761 if (opJavaCall->_info) do_info(opJavaCall->_info);
twisti@1484 762 if (opJavaCall->is_method_handle_invoke()) {
twisti@1484 763 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
twisti@1484 764 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
twisti@1484 765 }
duke@0 766 do_call();
duke@0 767 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
duke@0 768
duke@0 769 break;
duke@0 770 }
duke@0 771
duke@0 772
duke@0 773 // LIR_OpRTCall
duke@0 774 case lir_rtcall: {
duke@0 775 assert(op->as_OpRTCall() != NULL, "must be");
duke@0 776 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
duke@0 777
duke@0 778 // only visit register parameters
duke@0 779 int n = opRTCall->_arguments->length();
duke@0 780 for (int i = 0; i < n; i++) {
duke@0 781 if (!opRTCall->_arguments->at(i)->is_pointer()) {
duke@0 782 do_input(*opRTCall->_arguments->adr_at(i));
duke@0 783 }
duke@0 784 }
duke@0 785 if (opRTCall->_info) do_info(opRTCall->_info);
duke@0 786 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
duke@0 787 do_call();
duke@0 788 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
duke@0 789
duke@0 790 break;
duke@0 791 }
duke@0 792
duke@0 793
duke@0 794 // LIR_OpArrayCopy
duke@0 795 case lir_arraycopy: {
duke@0 796 assert(op->as_OpArrayCopy() != NULL, "must be");
duke@0 797 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
duke@0 798
duke@0 799 assert(opArrayCopy->_result->is_illegal(), "unused");
duke@0 800 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
duke@0 801 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
duke@0 802 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
duke@0 803 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
duke@0 804 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
duke@0 805 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
duke@0 806 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
duke@0 807
duke@0 808 // the implementation of arraycopy always has a call into the runtime
duke@0 809 do_call();
duke@0 810
duke@0 811 break;
duke@0 812 }
duke@0 813
duke@0 814
duke@0 815 // LIR_OpLock
duke@0 816 case lir_lock:
duke@0 817 case lir_unlock: {
duke@0 818 assert(op->as_OpLock() != NULL, "must be");
duke@0 819 LIR_OpLock* opLock = (LIR_OpLock*)op;
duke@0 820
duke@0 821 if (opLock->_info) do_info(opLock->_info);
duke@0 822
duke@0 823 // TODO: check if these operands really have to be temp
duke@0 824 // (or if input is sufficient). This may have influence on the oop map!
duke@0 825 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
duke@0 826 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
duke@0 827 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
duke@0 828
duke@0 829 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
duke@0 830 assert(opLock->_result->is_illegal(), "unused");
duke@0 831
duke@0 832 do_stub(opLock->_stub);
duke@0 833
duke@0 834 break;
duke@0 835 }
duke@0 836
duke@0 837
duke@0 838 // LIR_OpDelay
duke@0 839 case lir_delay_slot: {
duke@0 840 assert(op->as_OpDelay() != NULL, "must be");
duke@0 841 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
duke@0 842
duke@0 843 visit(opDelay->delay_op());
duke@0 844 break;
duke@0 845 }
duke@0 846
duke@0 847 // LIR_OpTypeCheck
duke@0 848 case lir_instanceof:
duke@0 849 case lir_checkcast:
duke@0 850 case lir_store_check: {
duke@0 851 assert(op->as_OpTypeCheck() != NULL, "must be");
duke@0 852 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
duke@0 853
duke@0 854 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
duke@0 855 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
duke@0 856 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
duke@0 857 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
duke@0 858 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
duke@0 859 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
duke@0 860 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
duke@0 861 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
duke@0 862 do_stub(opTypeCheck->_stub);
duke@0 863 break;
duke@0 864 }
duke@0 865
duke@0 866 // LIR_OpCompareAndSwap
duke@0 867 case lir_cas_long:
duke@0 868 case lir_cas_obj:
duke@0 869 case lir_cas_int: {
duke@0 870 assert(op->as_OpCompareAndSwap() != NULL, "must be");
duke@0 871 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
duke@0 872
bobv@1601 873 assert(opCompareAndSwap->_addr->is_valid(), "used");
bobv@1601 874 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
bobv@1601 875 assert(opCompareAndSwap->_new_value->is_valid(), "used");
duke@0 876 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
bobv@1601 877 do_input(opCompareAndSwap->_addr);
bobv@1601 878 do_temp(opCompareAndSwap->_addr);
bobv@1601 879 do_input(opCompareAndSwap->_cmp_value);
bobv@1601 880 do_temp(opCompareAndSwap->_cmp_value);
bobv@1601 881 do_input(opCompareAndSwap->_new_value);
bobv@1601 882 do_temp(opCompareAndSwap->_new_value);
duke@0 883 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
duke@0 884 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
duke@0 885 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
duke@0 886
duke@0 887 break;
duke@0 888 }
duke@0 889
duke@0 890
duke@0 891 // LIR_OpAllocArray;
duke@0 892 case lir_alloc_array: {
duke@0 893 assert(op->as_OpAllocArray() != NULL, "must be");
duke@0 894 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
duke@0 895
duke@0 896 if (opAllocArray->_info) do_info(opAllocArray->_info);
duke@0 897 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
duke@0 898 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
duke@0 899 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
duke@0 900 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
duke@0 901 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
duke@0 902 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
duke@0 903 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
duke@0 904 do_stub(opAllocArray->_stub);
duke@0 905 break;
duke@0 906 }
duke@0 907
duke@0 908 // LIR_OpProfileCall:
duke@0 909 case lir_profile_call: {
duke@0 910 assert(op->as_OpProfileCall() != NULL, "must be");
duke@0 911 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
duke@0 912
duke@0 913 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
duke@0 914 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
duke@0 915 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
duke@0 916 break;
duke@0 917 }
duke@0 918 default:
duke@0 919 ShouldNotReachHere();
duke@0 920 }
duke@0 921 }
duke@0 922
duke@0 923
duke@0 924 void LIR_OpVisitState::do_stub(CodeStub* stub) {
duke@0 925 if (stub != NULL) {
duke@0 926 stub->visit(this);
duke@0 927 }
duke@0 928 }
duke@0 929
duke@0 930 XHandlers* LIR_OpVisitState::all_xhandler() {
duke@0 931 XHandlers* result = NULL;
duke@0 932
duke@0 933 int i;
duke@0 934 for (i = 0; i < info_count(); i++) {
duke@0 935 if (info_at(i)->exception_handlers() != NULL) {
duke@0 936 result = info_at(i)->exception_handlers();
duke@0 937 break;
duke@0 938 }
duke@0 939 }
duke@0 940
duke@0 941 #ifdef ASSERT
duke@0 942 for (i = 0; i < info_count(); i++) {
duke@0 943 assert(info_at(i)->exception_handlers() == NULL ||
duke@0 944 info_at(i)->exception_handlers() == result,
duke@0 945 "only one xhandler list allowed per LIR-operation");
duke@0 946 }
duke@0 947 #endif
duke@0 948
duke@0 949 if (result != NULL) {
duke@0 950 return result;
duke@0 951 } else {
duke@0 952 return new XHandlers();
duke@0 953 }
duke@0 954
duke@0 955 return result;
duke@0 956 }
duke@0 957
duke@0 958
duke@0 959 #ifdef ASSERT
duke@0 960 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
duke@0 961 visit(op);
duke@0 962
duke@0 963 return opr_count(inputMode) == 0 &&
duke@0 964 opr_count(outputMode) == 0 &&
duke@0 965 opr_count(tempMode) == 0 &&
duke@0 966 info_count() == 0 &&
duke@0 967 !has_call() &&
duke@0 968 !has_slow_case();
duke@0 969 }
duke@0 970 #endif
duke@0 971
duke@0 972 //---------------------------------------------------
duke@0 973
duke@0 974
duke@0 975 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
duke@0 976 masm->emit_call(this);
duke@0 977 }
duke@0 978
duke@0 979 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
duke@0 980 masm->emit_rtcall(this);
duke@0 981 }
duke@0 982
duke@0 983 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
duke@0 984 masm->emit_opLabel(this);
duke@0 985 }
duke@0 986
duke@0 987 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
duke@0 988 masm->emit_arraycopy(this);
duke@0 989 masm->emit_code_stub(stub());
duke@0 990 }
duke@0 991
duke@0 992 void LIR_Op0::emit_code(LIR_Assembler* masm) {
duke@0 993 masm->emit_op0(this);
duke@0 994 }
duke@0 995
duke@0 996 void LIR_Op1::emit_code(LIR_Assembler* masm) {
duke@0 997 masm->emit_op1(this);
duke@0 998 }
duke@0 999
duke@0 1000 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
duke@0 1001 masm->emit_alloc_obj(this);
duke@0 1002 masm->emit_code_stub(stub());
duke@0 1003 }
duke@0 1004
duke@0 1005 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
duke@0 1006 masm->emit_opBranch(this);
duke@0 1007 if (stub()) {
duke@0 1008 masm->emit_code_stub(stub());
duke@0 1009 }
duke@0 1010 }
duke@0 1011
duke@0 1012 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
duke@0 1013 masm->emit_opConvert(this);
duke@0 1014 if (stub() != NULL) {
duke@0 1015 masm->emit_code_stub(stub());
duke@0 1016 }
duke@0 1017 }
duke@0 1018
duke@0 1019 void LIR_Op2::emit_code(LIR_Assembler* masm) {
duke@0 1020 masm->emit_op2(this);
duke@0 1021 }
duke@0 1022
duke@0 1023 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
duke@0 1024 masm->emit_alloc_array(this);
duke@0 1025 masm->emit_code_stub(stub());
duke@0 1026 }
duke@0 1027
duke@0 1028 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
iveresov@1711 1029 masm->emit_opTypeCheck(this);
duke@0 1030 if (stub()) {
duke@0 1031 masm->emit_code_stub(stub());
duke@0 1032 }
duke@0 1033 }
duke@0 1034
duke@0 1035 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
duke@0 1036 masm->emit_compare_and_swap(this);
duke@0 1037 }
duke@0 1038
duke@0 1039 void LIR_Op3::emit_code(LIR_Assembler* masm) {
duke@0 1040 masm->emit_op3(this);
duke@0 1041 }
duke@0 1042
duke@0 1043 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
duke@0 1044 masm->emit_lock(this);
duke@0 1045 if (stub()) {
duke@0 1046 masm->emit_code_stub(stub());
duke@0 1047 }
duke@0 1048 }
duke@0 1049
duke@0 1050
duke@0 1051 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
duke@0 1052 masm->emit_delay(this);
duke@0 1053 }
duke@0 1054
duke@0 1055 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
duke@0 1056 masm->emit_profile_call(this);
duke@0 1057 }
duke@0 1058
duke@0 1059 // LIR_List
duke@0 1060 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
duke@0 1061 : _operations(8)
duke@0 1062 , _compilation(compilation)
duke@0 1063 #ifndef PRODUCT
duke@0 1064 , _block(block)
duke@0 1065 #endif
duke@0 1066 #ifdef ASSERT
duke@0 1067 , _file(NULL)
duke@0 1068 , _line(0)
duke@0 1069 #endif
duke@0 1070 { }
duke@0 1071
duke@0 1072
duke@0 1073 #ifdef ASSERT
duke@0 1074 void LIR_List::set_file_and_line(const char * file, int line) {
duke@0 1075 const char * f = strrchr(file, '/');
duke@0 1076 if (f == NULL) f = strrchr(file, '\\');
duke@0 1077 if (f == NULL) {
duke@0 1078 f = file;
duke@0 1079 } else {
duke@0 1080 f++;
duke@0 1081 }
duke@0 1082 _file = f;
duke@0 1083 _line = line;
duke@0 1084 }
duke@0 1085 #endif
duke@0 1086
duke@0 1087
duke@0 1088 void LIR_List::append(LIR_InsertionBuffer* buffer) {
duke@0 1089 assert(this == buffer->lir_list(), "wrong lir list");
duke@0 1090 const int n = _operations.length();
duke@0 1091
duke@0 1092 if (buffer->number_of_ops() > 0) {
duke@0 1093 // increase size of instructions list
duke@0 1094 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
duke@0 1095 // insert ops from buffer into instructions list
duke@0 1096 int op_index = buffer->number_of_ops() - 1;
duke@0 1097 int ip_index = buffer->number_of_insertion_points() - 1;
duke@0 1098 int from_index = n - 1;
duke@0 1099 int to_index = _operations.length() - 1;
duke@0 1100 for (; ip_index >= 0; ip_index --) {
duke@0 1101 int index = buffer->index_at(ip_index);
duke@0 1102 // make room after insertion point
duke@0 1103 while (index < from_index) {
duke@0 1104 _operations.at_put(to_index --, _operations.at(from_index --));
duke@0 1105 }
duke@0 1106 // insert ops from buffer
duke@0 1107 for (int i = buffer->count_at(ip_index); i > 0; i --) {
duke@0 1108 _operations.at_put(to_index --, buffer->op_at(op_index --));
duke@0 1109 }
duke@0 1110 }
duke@0 1111 }
duke@0 1112
duke@0 1113 buffer->finish();
duke@0 1114 }
duke@0 1115
duke@0 1116
duke@0 1117 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
duke@0 1118 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
duke@0 1119 }
duke@0 1120
duke@0 1121
duke@0 1122 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1123 append(new LIR_Op1(
duke@0 1124 lir_move,
duke@0 1125 LIR_OprFact::address(addr),
duke@0 1126 src,
duke@0 1127 addr->type(),
duke@0 1128 patch_code,
duke@0 1129 info));
duke@0 1130 }
duke@0 1131
duke@0 1132
duke@0 1133 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1134 append(new LIR_Op1(
duke@0 1135 lir_move,
duke@0 1136 LIR_OprFact::address(address),
duke@0 1137 dst,
duke@0 1138 address->type(),
duke@0 1139 patch_code,
duke@0 1140 info, lir_move_volatile));
duke@0 1141 }
duke@0 1142
duke@0 1143 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1144 append(new LIR_Op1(
duke@0 1145 lir_move,
duke@0 1146 LIR_OprFact::address(new LIR_Address(base, offset, type)),
duke@0 1147 dst,
duke@0 1148 type,
duke@0 1149 patch_code,
duke@0 1150 info, lir_move_volatile));
duke@0 1151 }
duke@0 1152
duke@0 1153
duke@0 1154 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
duke@0 1155 append(new LIR_Op1(
duke@0 1156 is_store ? lir_prefetchw : lir_prefetchr,
duke@0 1157 LIR_OprFact::address(addr)));
duke@0 1158 }
duke@0 1159
duke@0 1160
duke@0 1161 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1162 append(new LIR_Op1(
duke@0 1163 lir_move,
duke@0 1164 LIR_OprFact::intConst(v),
duke@0 1165 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
duke@0 1166 type,
duke@0 1167 patch_code,
duke@0 1168 info));
duke@0 1169 }
duke@0 1170
duke@0 1171
duke@0 1172 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1173 append(new LIR_Op1(
duke@0 1174 lir_move,
duke@0 1175 LIR_OprFact::oopConst(o),
duke@0 1176 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
duke@0 1177 type,
duke@0 1178 patch_code,
duke@0 1179 info));
duke@0 1180 }
duke@0 1181
duke@0 1182
duke@0 1183 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1184 append(new LIR_Op1(
duke@0 1185 lir_move,
duke@0 1186 src,
duke@0 1187 LIR_OprFact::address(addr),
duke@0 1188 addr->type(),
duke@0 1189 patch_code,
duke@0 1190 info));
duke@0 1191 }
duke@0 1192
duke@0 1193
duke@0 1194 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1195 append(new LIR_Op1(
duke@0 1196 lir_move,
duke@0 1197 src,
duke@0 1198 LIR_OprFact::address(addr),
duke@0 1199 addr->type(),
duke@0 1200 patch_code,
duke@0 1201 info,
duke@0 1202 lir_move_volatile));
duke@0 1203 }
duke@0 1204
duke@0 1205 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
duke@0 1206 append(new LIR_Op1(
duke@0 1207 lir_move,
duke@0 1208 src,
duke@0 1209 LIR_OprFact::address(new LIR_Address(base, offset, type)),
duke@0 1210 type,
duke@0 1211 patch_code,
duke@0 1212 info, lir_move_volatile));
duke@0 1213 }
duke@0 1214
duke@0 1215
duke@0 1216 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 1217 append(new LIR_Op3(
duke@0 1218 lir_idiv,
duke@0 1219 left,
duke@0 1220 right,
duke@0 1221 tmp,
duke@0 1222 res,
duke@0 1223 info));
duke@0 1224 }
duke@0 1225
duke@0 1226
duke@0 1227 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 1228 append(new LIR_Op3(
duke@0 1229 lir_idiv,
duke@0 1230 left,
duke@0 1231 LIR_OprFact::intConst(right),
duke@0 1232 tmp,
duke@0 1233 res,
duke@0 1234 info));
duke@0 1235 }
duke@0 1236
duke@0 1237
duke@0 1238 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 1239 append(new LIR_Op3(
duke@0 1240 lir_irem,
duke@0 1241 left,
duke@0 1242 right,
duke@0 1243 tmp,
duke@0 1244 res,
duke@0 1245 info));
duke@0 1246 }
duke@0 1247
duke@0 1248
duke@0 1249 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
duke@0 1250 append(new LIR_Op3(
duke@0 1251 lir_irem,
duke@0 1252 left,
duke@0 1253 LIR_OprFact::intConst(right),
duke@0 1254 tmp,
duke@0 1255 res,
duke@0 1256 info));
duke@0 1257 }
duke@0 1258
duke@0 1259
duke@0 1260 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
duke@0 1261 append(new LIR_Op2(
duke@0 1262 lir_cmp,
duke@0 1263 condition,
duke@0 1264 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
duke@0 1265 LIR_OprFact::intConst(c),
duke@0 1266 info));
duke@0 1267 }
duke@0 1268
duke@0 1269
duke@0 1270 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
duke@0 1271 append(new LIR_Op2(
duke@0 1272 lir_cmp,
duke@0 1273 condition,
duke@0 1274 reg,
duke@0 1275 LIR_OprFact::address(addr),
duke@0 1276 info));
duke@0 1277 }
duke@0 1278
duke@0 1279 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
duke@0 1280 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
duke@0 1281 append(new LIR_OpAllocObj(
duke@0 1282 klass,
duke@0 1283 dst,
duke@0 1284 t1,
duke@0 1285 t2,
duke@0 1286 t3,
duke@0 1287 t4,
duke@0 1288 header_size,
duke@0 1289 object_size,
duke@0 1290 init_check,
duke@0 1291 stub));
duke@0 1292 }
duke@0 1293
duke@0 1294 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
duke@0 1295 append(new LIR_OpAllocArray(
duke@0 1296 klass,
duke@0 1297 len,
duke@0 1298 dst,
duke@0 1299 t1,
duke@0 1300 t2,
duke@0 1301 t3,
duke@0 1302 t4,
duke@0 1303 type,
duke@0 1304 stub));
duke@0 1305 }
duke@0 1306
duke@0 1307 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
duke@0 1308 append(new LIR_Op2(
duke@0 1309 lir_shl,
duke@0 1310 value,
duke@0 1311 count,
duke@0 1312 dst,
duke@0 1313 tmp));
duke@0 1314 }
duke@0 1315
duke@0 1316 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
duke@0 1317 append(new LIR_Op2(
duke@0 1318 lir_shr,
duke@0 1319 value,
duke@0 1320 count,
duke@0 1321 dst,
duke@0 1322 tmp));
duke@0 1323 }
duke@0 1324
duke@0 1325
duke@0 1326 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
duke@0 1327 append(new LIR_Op2(
duke@0 1328 lir_ushr,
duke@0 1329 value,
duke@0 1330 count,
duke@0 1331 dst,
duke@0 1332 tmp));
duke@0 1333 }
duke@0 1334
duke@0 1335 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
duke@0 1336 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
duke@0 1337 left,
duke@0 1338 right,
duke@0 1339 dst));
duke@0 1340 }
duke@0 1341
duke@0 1342 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
duke@0 1343 append(new LIR_OpLock(
duke@0 1344 lir_lock,
duke@0 1345 hdr,
duke@0 1346 obj,
duke@0 1347 lock,
duke@0 1348 scratch,
duke@0 1349 stub,
duke@0 1350 info));
duke@0 1351 }
duke@0 1352
bobv@1601 1353 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
duke@0 1354 append(new LIR_OpLock(
duke@0 1355 lir_unlock,
duke@0 1356 hdr,
duke@0 1357 obj,
duke@0 1358 lock,
bobv@1601 1359 scratch,
duke@0 1360 stub,
duke@0 1361 NULL));
duke@0 1362 }
duke@0 1363
duke@0 1364
duke@0 1365 void check_LIR() {
duke@0 1366 // cannot do the proper checking as PRODUCT and other modes return different results
duke@0 1367 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
duke@0 1368 }
duke@0 1369
duke@0 1370
duke@0 1371
duke@0 1372 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
duke@0 1373 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
duke@0 1374 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
duke@0 1375 ciMethod* profiled_method, int profiled_bci) {
iveresov@1703 1376 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
iveresov@1703 1377 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
iveresov@1703 1378 if (profiled_method != NULL) {
iveresov@1703 1379 c->set_profiled_method(profiled_method);
iveresov@1703 1380 c->set_profiled_bci(profiled_bci);
iveresov@1703 1381 c->set_should_profile(true);
iveresov@1703 1382 }
iveresov@1703 1383 append(c);
duke@0 1384 }
duke@0 1385
iveresov@1711 1386 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
iveresov@1711 1387 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
iveresov@1711 1388 if (profiled_method != NULL) {
iveresov@1711 1389 c->set_profiled_method(profiled_method);
iveresov@1711 1390 c->set_profiled_bci(profiled_bci);
iveresov@1711 1391 c->set_should_profile(true);
iveresov@1711 1392 }
iveresov@1711 1393 append(c);
duke@0 1394 }
duke@0 1395
duke@0 1396
iveresov@2718 1397 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
iveresov@2718 1398 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
iveresov@2718 1399 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
iveresov@2718 1400 if (profiled_method != NULL) {
iveresov@2718 1401 c->set_profiled_method(profiled_method);
iveresov@2718 1402 c->set_profiled_bci(profiled_bci);
iveresov@2718 1403 c->set_should_profile(true);
iveresov@2718 1404 }
iveresov@2718 1405 append(c);
duke@0 1406 }
duke@0 1407
duke@0 1408
bobv@1601 1409 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
bobv@1601 1410 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
bobv@1601 1411 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
duke@0 1412 }
duke@0 1413
bobv@1601 1414 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
bobv@1601 1415 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
bobv@1601 1416 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
duke@0 1417 }
duke@0 1418
bobv@1601 1419 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
bobv@1601 1420 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
bobv@1601 1421 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
duke@0 1422 }
duke@0 1423
duke@0 1424
duke@0 1425 #ifdef PRODUCT
duke@0 1426
duke@0 1427 void print_LIR(BlockList* blocks) {
duke@0 1428 }
duke@0 1429
duke@0 1430 #else
duke@0 1431 // LIR_OprDesc
duke@0 1432 void LIR_OprDesc::print() const {
duke@0 1433 print(tty);
duke@0 1434 }
duke@0 1435
duke@0 1436 void LIR_OprDesc::print(outputStream* out) const {
duke@0 1437 if (is_illegal()) {
duke@0 1438 return;
duke@0 1439 }
duke@0 1440
duke@0 1441 out->print("[");
duke@0 1442 if (is_pointer()) {
duke@0 1443 pointer()->print_value_on(out);
duke@0 1444 } else if (is_single_stack()) {
duke@0 1445 out->print("stack:%d", single_stack_ix());
duke@0 1446 } else if (is_double_stack()) {
duke@0 1447 out->print("dbl_stack:%d",double_stack_ix());
duke@0 1448 } else if (is_virtual()) {
duke@0 1449 out->print("R%d", vreg_number());
duke@0 1450 } else if (is_single_cpu()) {
duke@0 1451 out->print(as_register()->name());
duke@0 1452 } else if (is_double_cpu()) {
duke@0 1453 out->print(as_register_hi()->name());
duke@0 1454 out->print(as_register_lo()->name());
never@304 1455 #if defined(X86)
duke@0 1456 } else if (is_single_xmm()) {
duke@0 1457 out->print(as_xmm_float_reg()->name());
duke@0 1458 } else if (is_double_xmm()) {
duke@0 1459 out->print(as_xmm_double_reg()->name());
duke@0 1460 } else if (is_single_fpu()) {
duke@0 1461 out->print("fpu%d", fpu_regnr());
duke@0 1462 } else if (is_double_fpu()) {
duke@0 1463 out->print("fpu%d", fpu_regnrLo());
bobv@1601 1464 #elif defined(ARM)
bobv@1601 1465 } else if (is_single_fpu()) {
bobv@1601 1466 out->print("s%d", fpu_regnr());
bobv@1601 1467 } else if (is_double_fpu()) {
bobv@1601 1468 out->print("d%d", fpu_regnrLo() >> 1);
duke@0 1469 #else
duke@0 1470 } else if (is_single_fpu()) {
duke@0 1471 out->print(as_float_reg()->name());
duke@0 1472 } else if (is_double_fpu()) {
duke@0 1473 out->print(as_double_reg()->name());
duke@0 1474 #endif
duke@0 1475
duke@0 1476 } else if (is_illegal()) {
duke@0 1477 out->print("-");
duke@0 1478 } else {
duke@0 1479 out->print("Unknown Operand");
duke@0 1480 }
duke@0 1481 if (!is_illegal()) {
duke@0 1482 out->print("|%c", type_char());
duke@0 1483 }
duke@0 1484 if (is_register() && is_last_use()) {
duke@0 1485 out->print("(last_use)");
duke@0 1486 }
duke@0 1487 out->print("]");
duke@0 1488 }
duke@0 1489
duke@0 1490
duke@0 1491 // LIR_Address
duke@0 1492 void LIR_Const::print_value_on(outputStream* out) const {
duke@0 1493 switch (type()) {
roland@1297 1494 case T_ADDRESS:out->print("address:%d",as_jint()); break;
duke@0 1495 case T_INT: out->print("int:%d", as_jint()); break;
duke@0 1496 case T_LONG: out->print("lng:%lld", as_jlong()); break;
duke@0 1497 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
duke@0 1498 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
duke@0 1499 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
duke@0 1500 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
duke@0 1501 }
duke@0 1502 }
duke@0 1503
duke@0 1504 // LIR_Address
duke@0 1505 void LIR_Address::print_value_on(outputStream* out) const {
duke@0 1506 out->print("Base:"); _base->print(out);
duke@0 1507 if (!_index->is_illegal()) {
duke@0 1508 out->print(" Index:"); _index->print(out);
duke@0 1509 switch (scale()) {
duke@0 1510 case times_1: break;
duke@0 1511 case times_2: out->print(" * 2"); break;
duke@0 1512 case times_4: out->print(" * 4"); break;
duke@0 1513 case times_8: out->print(" * 8"); break;
duke@0 1514 }
duke@0 1515 }
duke@0 1516 out->print(" Disp: %d", _disp);
duke@0 1517 }
duke@0 1518
duke@0 1519 // debug output of block header without InstructionPrinter
duke@0 1520 // (because phi functions are not necessary for LIR)
duke@0 1521 static void print_block(BlockBegin* x) {
duke@0 1522 // print block id
duke@0 1523 BlockEnd* end = x->end();
duke@0 1524 tty->print("B%d ", x->block_id());
duke@0 1525
duke@0 1526 // print flags
duke@0 1527 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
duke@0 1528 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
duke@0 1529 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
duke@0 1530 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
duke@0 1531 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
duke@0 1532 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
duke@0 1533 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
duke@0 1534
duke@0 1535 // print block bci range
roland@1739 1536 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
duke@0 1537
duke@0 1538 // print predecessors and successors
duke@0 1539 if (x->number_of_preds() > 0) {
duke@0 1540 tty->print("preds: ");
duke@0 1541 for (int i = 0; i < x->number_of_preds(); i ++) {
duke@0 1542 tty->print("B%d ", x->pred_at(i)->block_id());
duke@0 1543 }
duke@0 1544 }
duke@0 1545
duke@0 1546 if (x->number_of_sux() > 0) {
duke@0 1547 tty->print("sux: ");
duke@0 1548 for (int i = 0; i < x->number_of_sux(); i ++) {
duke@0 1549 tty->print("B%d ", x->sux_at(i)->block_id());
duke@0 1550 }
duke@0 1551 }
duke@0 1552
duke@0 1553 // print exception handlers
duke@0 1554 if (x->number_of_exception_handlers() > 0) {
duke@0 1555 tty->print("xhandler: ");
duke@0 1556 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
duke@0 1557 tty->print("B%d ", x->exception_handler_at(i)->block_id());
duke@0 1558 }
duke@0 1559 }
duke@0 1560
duke@0 1561 tty->cr();
duke@0 1562 }
duke@0 1563
duke@0 1564 void print_LIR(BlockList* blocks) {
duke@0 1565 tty->print_cr("LIR:");
duke@0 1566 int i;
duke@0 1567 for (i = 0; i < blocks->length(); i++) {
duke@0 1568 BlockBegin* bb = blocks->at(i);
duke@0 1569 print_block(bb);
duke@0 1570 tty->print("__id_Instruction___________________________________________"); tty->cr();
duke@0 1571 bb->lir()->print_instructions();
duke@0 1572 }
duke@0 1573 }
duke@0 1574
duke@0 1575 void LIR_List::print_instructions() {
duke@0 1576 for (int i = 0; i < _operations.length(); i++) {
duke@0 1577 _operations.at(i)->print(); tty->cr();
duke@0 1578 }
duke@0 1579 tty->cr();
duke@0 1580 }
duke@0 1581
duke@0 1582 // LIR_Ops printing routines
duke@0 1583 // LIR_Op
duke@0 1584 void LIR_Op::print_on(outputStream* out) const {
duke@0 1585 if (id() != -1 || PrintCFGToFile) {
duke@0 1586 out->print("%4d ", id());
duke@0 1587 } else {
duke@0 1588 out->print(" ");
duke@0 1589 }
duke@0 1590 out->print(name()); out->print(" ");
duke@0 1591 print_instr(out);
roland@1739 1592 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
duke@0 1593 #ifdef ASSERT
duke@0 1594 if (Verbose && _file != NULL) {
duke@0 1595 out->print(" (%s:%d)", _file, _line);
duke@0 1596 }
duke@0 1597 #endif
duke@0 1598 }
duke@0 1599
duke@0 1600 const char * LIR_Op::name() const {
duke@0 1601 const char* s = NULL;
duke@0 1602 switch(code()) {
duke@0 1603 // LIR_Op0
duke@0 1604 case lir_membar: s = "membar"; break;
duke@0 1605 case lir_membar_acquire: s = "membar_acquire"; break;
duke@0 1606 case lir_membar_release: s = "membar_release"; break;
duke@0 1607 case lir_word_align: s = "word_align"; break;
duke@0 1608 case lir_label: s = "label"; break;
duke@0 1609 case lir_nop: s = "nop"; break;
duke@0 1610 case lir_backwardbranch_target: s = "backbranch"; break;
duke@0 1611 case lir_std_entry: s = "std_entry"; break;
duke@0 1612 case lir_osr_entry: s = "osr_entry"; break;
duke@0 1613 case lir_build_frame: s = "build_frm"; break;
duke@0 1614 case lir_fpop_raw: s = "fpop_raw"; break;
duke@0 1615 case lir_24bit_FPU: s = "24bit_FPU"; break;
duke@0 1616 case lir_reset_FPU: s = "reset_FPU"; break;
duke@0 1617 case lir_breakpoint: s = "breakpoint"; break;
duke@0 1618 case lir_get_thread: s = "get_thread"; break;
duke@0 1619 // LIR_Op1
duke@0 1620 case lir_fxch: s = "fxch"; break;
duke@0 1621 case lir_fld: s = "fld"; break;
duke@0 1622 case lir_ffree: s = "ffree"; break;
duke@0 1623 case lir_push: s = "push"; break;
duke@0 1624 case lir_pop: s = "pop"; break;
duke@0 1625 case lir_null_check: s = "null_check"; break;
duke@0 1626 case lir_return: s = "return"; break;
duke@0 1627 case lir_safepoint: s = "safepoint"; break;
duke@0 1628 case lir_neg: s = "neg"; break;
duke@0 1629 case lir_leal: s = "leal"; break;
duke@0 1630 case lir_branch: s = "branch"; break;
duke@0 1631 case lir_cond_float_branch: s = "flt_cond_br"; break;
duke@0 1632 case lir_move: s = "move"; break;
duke@0 1633 case lir_roundfp: s = "roundfp"; break;
duke@0 1634 case lir_rtcall: s = "rtcall"; break;
duke@0 1635 case lir_throw: s = "throw"; break;
duke@0 1636 case lir_unwind: s = "unwind"; break;
duke@0 1637 case lir_convert: s = "convert"; break;
duke@0 1638 case lir_alloc_object: s = "alloc_obj"; break;
duke@0 1639 case lir_monaddr: s = "mon_addr"; break;
iveresov@1703 1640 case lir_pack64: s = "pack64"; break;
iveresov@1703 1641 case lir_unpack64: s = "unpack64"; break;
duke@0 1642 // LIR_Op2
duke@0 1643 case lir_cmp: s = "cmp"; break;
duke@0 1644 case lir_cmp_l2i: s = "cmp_l2i"; break;
duke@0 1645 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
duke@0 1646 case lir_cmp_fd2i: s = "comp_fd2i"; break;
duke@0 1647 case lir_cmove: s = "cmove"; break;
duke@0 1648 case lir_add: s = "add"; break;
duke@0 1649 case lir_sub: s = "sub"; break;
duke@0 1650 case lir_mul: s = "mul"; break;
duke@0 1651 case lir_mul_strictfp: s = "mul_strictfp"; break;
duke@0 1652 case lir_div: s = "div"; break;
duke@0 1653 case lir_div_strictfp: s = "div_strictfp"; break;
duke@0 1654 case lir_rem: s = "rem"; break;
duke@0 1655 case lir_abs: s = "abs"; break;
duke@0 1656 case lir_sqrt: s = "sqrt"; break;
duke@0 1657 case lir_sin: s = "sin"; break;
duke@0 1658 case lir_cos: s = "cos"; break;
duke@0 1659 case lir_tan: s = "tan"; break;
duke@0 1660 case lir_log: s = "log"; break;
duke@0 1661 case lir_log10: s = "log10"; break;
duke@0 1662 case lir_logic_and: s = "logic_and"; break;
duke@0 1663 case lir_logic_or: s = "logic_or"; break;
duke@0 1664 case lir_logic_xor: s = "logic_xor"; break;
duke@0 1665 case lir_shl: s = "shift_left"; break;
duke@0 1666 case lir_shr: s = "shift_right"; break;
duke@0 1667 case lir_ushr: s = "ushift_right"; break;
duke@0 1668 case lir_alloc_array: s = "alloc_array"; break;
duke@0 1669 // LIR_Op3
duke@0 1670 case lir_idiv: s = "idiv"; break;
duke@0 1671 case lir_irem: s = "irem"; break;
duke@0 1672 // LIR_OpJavaCall
duke@0 1673 case lir_static_call: s = "static"; break;
duke@0 1674 case lir_optvirtual_call: s = "optvirtual"; break;
duke@0 1675 case lir_icvirtual_call: s = "icvirtual"; break;
duke@0 1676 case lir_virtual_call: s = "virtual"; break;
twisti@1295 1677 case lir_dynamic_call: s = "dynamic"; break;
duke@0 1678 // LIR_OpArrayCopy
duke@0 1679 case lir_arraycopy: s = "arraycopy"; break;
duke@0 1680 // LIR_OpLock
duke@0 1681 case lir_lock: s = "lock"; break;
duke@0 1682 case lir_unlock: s = "unlock"; break;
duke@0 1683 // LIR_OpDelay
duke@0 1684 case lir_delay_slot: s = "delay"; break;
duke@0 1685 // LIR_OpTypeCheck
duke@0 1686 case lir_instanceof: s = "instanceof"; break;
duke@0 1687 case lir_checkcast: s = "checkcast"; break;
duke@0 1688 case lir_store_check: s = "store_check"; break;
duke@0 1689 // LIR_OpCompareAndSwap
duke@0 1690 case lir_cas_long: s = "cas_long"; break;
duke@0 1691 case lir_cas_obj: s = "cas_obj"; break;
duke@0 1692 case lir_cas_int: s = "cas_int"; break;
duke@0 1693 // LIR_OpProfileCall
duke@0 1694 case lir_profile_call: s = "profile_call"; break;
duke@0 1695 case lir_none: ShouldNotReachHere();break;
duke@0 1696 default: s = "illegal_op"; break;
duke@0 1697 }
duke@0 1698 return s;
duke@0 1699 }
duke@0 1700
duke@0 1701 // LIR_OpJavaCall
duke@0 1702 void LIR_OpJavaCall::print_instr(outputStream* out) const {
duke@0 1703 out->print("call: ");
duke@0 1704 out->print("[addr: 0x%x]", address());
duke@0 1705 if (receiver()->is_valid()) {
duke@0 1706 out->print(" [recv: "); receiver()->print(out); out->print("]");
duke@0 1707 }
duke@0 1708 if (result_opr()->is_valid()) {
duke@0 1709 out->print(" [result: "); result_opr()->print(out); out->print("]");
duke@0 1710 }
duke@0 1711 }
duke@0 1712
duke@0 1713 // LIR_OpLabel
duke@0 1714 void LIR_OpLabel::print_instr(outputStream* out) const {
duke@0 1715 out->print("[label:0x%x]", _label);
duke@0 1716 }
duke@0 1717
duke@0 1718 // LIR_OpArrayCopy
duke@0 1719 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
duke@0 1720 src()->print(out); out->print(" ");
duke@0 1721 src_pos()->print(out); out->print(" ");
duke@0 1722 dst()->print(out); out->print(" ");
duke@0 1723 dst_pos()->print(out); out->print(" ");
duke@0 1724 length()->print(out); out->print(" ");
duke@0 1725 tmp()->print(out); out->print(" ");
duke@0 1726 }
duke@0 1727
duke@0 1728 // LIR_OpCompareAndSwap
duke@0 1729 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
duke@0 1730 addr()->print(out); out->print(" ");
duke@0 1731 cmp_value()->print(out); out->print(" ");
duke@0 1732 new_value()->print(out); out->print(" ");
duke@0 1733 tmp1()->print(out); out->print(" ");
duke@0 1734 tmp2()->print(out); out->print(" ");
duke@0 1735
duke@0 1736 }
duke@0 1737
duke@0 1738 // LIR_Op0
duke@0 1739 void LIR_Op0::print_instr(outputStream* out) const {
duke@0 1740 result_opr()->print(out);
duke@0 1741 }
duke@0 1742
duke@0 1743 // LIR_Op1
duke@0 1744 const char * LIR_Op1::name() const {
duke@0 1745 if (code() == lir_move) {
duke@0 1746 switch (move_kind()) {
duke@0 1747 case lir_move_normal:
duke@0 1748 return "move";
duke@0 1749 case lir_move_unaligned:
duke@0 1750 return "unaligned move";
duke@0 1751 case lir_move_volatile:
duke@0 1752 return "volatile_move";
iveresov@1909 1753 case lir_move_wide:
iveresov@1909 1754 return "wide_move";
duke@0 1755 default:
duke@0 1756 ShouldNotReachHere();
duke@0 1757 return "illegal_op";
duke@0 1758 }
duke@0 1759 } else {
duke@0 1760 return LIR_Op::name();
duke@0 1761 }
duke@0 1762 }
duke@0 1763
duke@0 1764
duke@0 1765 void LIR_Op1::print_instr(outputStream* out) const {
duke@0 1766 _opr->print(out); out->print(" ");
duke@0 1767 result_opr()->print(out); out->print(" ");
duke@0 1768 print_patch_code(out, patch_code());
duke@0 1769 }
duke@0 1770
duke@0 1771
duke@0 1772 // LIR_Op1
duke@0 1773 void LIR_OpRTCall::print_instr(outputStream* out) const {
duke@0 1774 intx a = (intx)addr();
duke@0 1775 out->print(Runtime1::name_for_address(addr()));
duke@0 1776 out->print(" ");
duke@0 1777 tmp()->print(out);
duke@0 1778 }
duke@0 1779
duke@0 1780 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
duke@0 1781 switch(code) {
duke@0 1782 case lir_patch_none: break;
duke@0 1783 case lir_patch_low: out->print("[patch_low]"); break;
duke@0 1784 case lir_patch_high: out->print("[patch_high]"); break;
duke@0 1785 case lir_patch_normal: out->print("[patch_normal]"); break;
duke@0 1786 default: ShouldNotReachHere();
duke@0 1787 }
duke@0 1788 }
duke@0 1789
duke@0 1790 // LIR_OpBranch
duke@0 1791 void LIR_OpBranch::print_instr(outputStream* out) const {
duke@0 1792 print_condition(out, cond()); out->print(" ");
duke@0 1793 if (block() != NULL) {
duke@0 1794 out->print("[B%d] ", block()->block_id());
duke@0 1795 } else if (stub() != NULL) {
duke@0 1796 out->print("[");
duke@0 1797 stub()->print_name(out);
duke@0 1798 out->print(": 0x%x]", stub());
roland@1739 1799 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
duke@0 1800 } else {
duke@0 1801 out->print("[label:0x%x] ", label());
duke@0 1802 }
duke@0 1803 if (ublock() != NULL) {
duke@0 1804 out->print("unordered: [B%d] ", ublock()->block_id());
duke@0 1805 }
duke@0 1806 }
duke@0 1807
duke@0 1808 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
duke@0 1809 switch(cond) {
duke@0 1810 case lir_cond_equal: out->print("[EQ]"); break;
duke@0 1811 case lir_cond_notEqual: out->print("[NE]"); break;
duke@0 1812 case lir_cond_less: out->print("[LT]"); break;
duke@0 1813 case lir_cond_lessEqual: out->print("[LE]"); break;
duke@0 1814 case lir_cond_greaterEqual: out->print("[GE]"); break;
duke@0 1815 case lir_cond_greater: out->print("[GT]"); break;
duke@0 1816 case lir_cond_belowEqual: out->print("[BE]"); break;
duke@0 1817 case lir_cond_aboveEqual: out->print("[AE]"); break;
duke@0 1818 case lir_cond_always: out->print("[AL]"); break;
duke@0 1819 default: out->print("[%d]",cond); break;
duke@0 1820 }
duke@0 1821 }
duke@0 1822
duke@0 1823 // LIR_OpConvert
duke@0 1824 void LIR_OpConvert::print_instr(outputStream* out) const {
duke@0 1825 print_bytecode(out, bytecode());
duke@0 1826 in_opr()->print(out); out->print(" ");
duke@0 1827 result_opr()->print(out); out->print(" ");
bobv@1601 1828 #ifdef PPC
bobv@1601 1829 if(tmp1()->is_valid()) {
bobv@1601 1830 tmp1()->print(out); out->print(" ");
bobv@1601 1831 tmp2()->print(out); out->print(" ");
bobv@1601 1832 }
bobv@1601 1833 #endif
duke@0 1834 }
duke@0 1835
duke@0 1836 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
duke@0 1837 switch(code) {
duke@0 1838 case Bytecodes::_d2f: out->print("[d2f] "); break;
duke@0 1839 case Bytecodes::_d2i: out->print("[d2i] "); break;
duke@0 1840 case Bytecodes::_d2l: out->print("[d2l] "); break;
duke@0 1841 case Bytecodes::_f2d: out->print("[f2d] "); break;
duke@0 1842 case Bytecodes::_f2i: out->print("[f2i] "); break;
duke@0 1843 case Bytecodes::_f2l: out->print("[f2l] "); break;
duke@0 1844 case Bytecodes::_i2b: out->print("[i2b] "); break;
duke@0 1845 case Bytecodes::_i2c: out->print("[i2c] "); break;
duke@0 1846 case Bytecodes::_i2d: out->print("[i2d] "); break;
duke@0 1847 case Bytecodes::_i2f: out->print("[i2f] "); break;
duke@0 1848 case Bytecodes::_i2l: out->print("[i2l] "); break;
duke@0 1849 case Bytecodes::_i2s: out->print("[i2s] "); break;
duke@0 1850 case Bytecodes::_l2i: out->print("[l2i] "); break;
duke@0 1851 case Bytecodes::_l2f: out->print("[l2f] "); break;
duke@0 1852 case Bytecodes::_l2d: out->print("[l2d] "); break;
duke@0 1853 default:
duke@0 1854 out->print("[?%d]",code);
duke@0 1855 break;
duke@0 1856 }
duke@0 1857 }
duke@0 1858
duke@0 1859 void LIR_OpAllocObj::print_instr(outputStream* out) const {
duke@0 1860 klass()->print(out); out->print(" ");
duke@0 1861 obj()->print(out); out->print(" ");
duke@0 1862 tmp1()->print(out); out->print(" ");
duke@0 1863 tmp2()->print(out); out->print(" ");
duke@0 1864 tmp3()->print(out); out->print(" ");
duke@0 1865 tmp4()->print(out); out->print(" ");
duke@0 1866 out->print("[hdr:%d]", header_size()); out->print(" ");
duke@0 1867 out->print("[obj:%d]", object_size()); out->print(" ");
duke@0 1868 out->print("[lbl:0x%x]", stub()->entry());
duke@0 1869 }
duke@0 1870
duke@0 1871 void LIR_OpRoundFP::print_instr(outputStream* out) const {
duke@0 1872 _opr->print(out); out->print(" ");
duke@0 1873 tmp()->print(out); out->print(" ");
duke@0 1874 result_opr()->print(out); out->print(" ");
duke@0 1875 }
duke@0 1876
duke@0 1877 // LIR_Op2
duke@0 1878 void LIR_Op2::print_instr(outputStream* out) const {
duke@0 1879 if (code() == lir_cmove) {
duke@0 1880 print_condition(out, condition()); out->print(" ");
duke@0 1881 }
duke@0 1882 in_opr1()->print(out); out->print(" ");
duke@0 1883 in_opr2()->print(out); out->print(" ");
duke@0 1884 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); }
duke@0 1885 result_opr()->print(out);
duke@0 1886 }
duke@0 1887
duke@0 1888 void LIR_OpAllocArray::print_instr(outputStream* out) const {
duke@0 1889 klass()->print(out); out->print(" ");
duke@0 1890 len()->print(out); out->print(" ");
duke@0 1891 obj()->print(out); out->print(" ");
duke@0 1892 tmp1()->print(out); out->print(" ");
duke@0 1893 tmp2()->print(out); out->print(" ");
duke@0 1894 tmp3()->print(out); out->print(" ");
duke@0 1895 tmp4()->print(out); out->print(" ");
duke@0 1896 out->print("[type:0x%x]", type()); out->print(" ");
duke@0 1897 out->print("[label:0x%x]", stub()->entry());
duke@0 1898 }
duke@0 1899
duke@0 1900
duke@0 1901 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
duke@0 1902 object()->print(out); out->print(" ");
duke@0 1903 if (code() == lir_store_check) {
duke@0 1904 array()->print(out); out->print(" ");
duke@0 1905 }
duke@0 1906 if (code() != lir_store_check) {
duke@0 1907 klass()->print_name_on(out); out->print(" ");
duke@0 1908 if (fast_check()) out->print("fast_check ");
duke@0 1909 }
duke@0 1910 tmp1()->print(out); out->print(" ");
duke@0 1911 tmp2()->print(out); out->print(" ");
duke@0 1912 tmp3()->print(out); out->print(" ");
duke@0 1913 result_opr()->print(out); out->print(" ");
roland@1739 1914 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
duke@0 1915 }
duke@0 1916
duke@0 1917
duke@0 1918 // LIR_Op3
duke@0 1919 void LIR_Op3::print_instr(outputStream* out) const {
duke@0 1920 in_opr1()->print(out); out->print(" ");
duke@0 1921 in_opr2()->print(out); out->print(" ");
duke@0 1922 in_opr3()->print(out); out->print(" ");
duke@0 1923 result_opr()->print(out);
duke@0 1924 }
duke@0 1925
duke@0 1926
duke@0 1927 void LIR_OpLock::print_instr(outputStream* out) const {
duke@0 1928 hdr_opr()->print(out); out->print(" ");
duke@0 1929 obj_opr()->print(out); out->print(" ");
duke@0 1930 lock_opr()->print(out); out->print(" ");
duke@0 1931 if (_scratch->is_valid()) {
duke@0 1932 _scratch->print(out); out->print(" ");
duke@0 1933 }
duke@0 1934 out->print("[lbl:0x%x]", stub()->entry());
duke@0 1935 }
duke@0 1936
duke@0 1937
duke@0 1938 void LIR_OpDelay::print_instr(outputStream* out) const {
duke@0 1939 _op->print_on(out);
duke@0 1940 }
duke@0 1941
duke@0 1942
duke@0 1943 // LIR_OpProfileCall
duke@0 1944 void LIR_OpProfileCall::print_instr(outputStream* out) const {
duke@0 1945 profiled_method()->name()->print_symbol_on(out);
duke@0 1946 out->print(".");
duke@0 1947 profiled_method()->holder()->name()->print_symbol_on(out);
duke@0 1948 out->print(" @ %d ", profiled_bci());
duke@0 1949 mdo()->print(out); out->print(" ");
duke@0 1950 recv()->print(out); out->print(" ");
duke@0 1951 tmp1()->print(out); out->print(" ");
duke@0 1952 }
duke@0 1953
duke@0 1954 #endif // PRODUCT
duke@0 1955
duke@0 1956 // Implementation of LIR_InsertionBuffer
duke@0 1957
duke@0 1958 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
duke@0 1959 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
duke@0 1960
duke@0 1961 int i = number_of_insertion_points() - 1;
duke@0 1962 if (i < 0 || index_at(i) < index) {
duke@0 1963 append_new(index, 1);
duke@0 1964 } else {
duke@0 1965 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
duke@0 1966 assert(count_at(i) > 0, "check");
duke@0 1967 set_count_at(i, count_at(i) + 1);
duke@0 1968 }
duke@0 1969 _ops.push(op);
duke@0 1970
duke@0 1971 DEBUG_ONLY(verify());
duke@0 1972 }
duke@0 1973
duke@0 1974 #ifdef ASSERT
duke@0 1975 void LIR_InsertionBuffer::verify() {
duke@0 1976 int sum = 0;
duke@0 1977 int prev_idx = -1;
duke@0 1978
duke@0 1979 for (int i = 0; i < number_of_insertion_points(); i++) {
duke@0 1980 assert(prev_idx < index_at(i), "index must be ordered ascending");
duke@0 1981 sum += count_at(i);
duke@0 1982 }
duke@0 1983 assert(sum == number_of_ops(), "wrong total sum");
duke@0 1984 }
duke@0 1985 #endif