annotate src/share/vm/opto/matcher.hpp @ 2614:95134e034042

7063629: use cbcond in C2 generated code on T4 Summary: Use new short branch instruction in C2 generated code. Reviewed-by: never
author kvn
date Thu, 11 Aug 2011 12:08:11 -0700
parents f1c12354c3f7
children d8cb48376797
rev   line source
duke@0 1 /*
trims@2273 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1472 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 * or visit www.oracle.com if you need additional information or have any
trims@1472 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1879 25 #ifndef SHARE_VM_OPTO_MATCHER_HPP
stefank@1879 26 #define SHARE_VM_OPTO_MATCHER_HPP
stefank@1879 27
stefank@1879 28 #include "libadt/vectset.hpp"
stefank@1879 29 #include "memory/resourceArea.hpp"
stefank@1879 30 #include "opto/node.hpp"
stefank@1879 31 #include "opto/phaseX.hpp"
stefank@1879 32 #include "opto/regmask.hpp"
stefank@1879 33
duke@0 34 class Compile;
duke@0 35 class Node;
duke@0 36 class MachNode;
duke@0 37 class MachTypeNode;
duke@0 38 class MachOper;
duke@0 39
duke@0 40 //---------------------------Matcher-------------------------------------------
duke@0 41 class Matcher : public PhaseTransform {
duke@0 42 friend class VMStructs;
duke@0 43 // Private arena of State objects
duke@0 44 ResourceArea _states_arena;
duke@0 45
duke@0 46 VectorSet _visited; // Visit bits
duke@0 47
duke@0 48 // Used to control the Label pass
duke@0 49 VectorSet _shared; // Shared Ideal Node
duke@0 50 VectorSet _dontcare; // Nothing the matcher cares about
duke@0 51
duke@0 52 // Private methods which perform the actual matching and reduction
duke@0 53 // Walks the label tree, generating machine nodes
duke@0 54 MachNode *ReduceInst( State *s, int rule, Node *&mem);
duke@0 55 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
duke@0 56 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
duke@0 57 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
duke@0 58
duke@0 59 // If this node already matched using "rule", return the MachNode for it.
kvn@168 60 MachNode* find_shared_node(Node* n, uint rule);
duke@0 61
duke@0 62 // Convert a dense opcode number to an expanded rule number
duke@0 63 const int *_reduceOp;
duke@0 64 const int *_leftOp;
duke@0 65 const int *_rightOp;
duke@0 66
duke@0 67 // Map dense opcode number to info on when rule is swallowed constant.
duke@0 68 const bool *_swallowed;
duke@0 69
duke@0 70 // Map dense rule number to determine if this is an instruction chain rule
duke@0 71 const uint _begin_inst_chain_rule;
duke@0 72 const uint _end_inst_chain_rule;
duke@0 73
duke@0 74 // We want to clone constants and possible CmpI-variants.
duke@0 75 // If we do not clone CmpI, then we can have many instances of
duke@0 76 // condition codes alive at once. This is OK on some chips and
duke@0 77 // bad on others. Hence the machine-dependent table lookup.
duke@0 78 const char *_must_clone;
duke@0 79
duke@0 80 // Find shared Nodes, or Nodes that otherwise are Matcher roots
duke@0 81 void find_shared( Node *n );
duke@0 82
duke@0 83 // Debug and profile information for nodes in old space:
duke@0 84 GrowableArray<Node_Notes*>* _old_node_note_array;
duke@0 85
duke@0 86 // Node labeling iterator for instruction selection
duke@0 87 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
duke@0 88
duke@0 89 Node *transform( Node *dummy );
duke@0 90
duke@0 91 Node_List &_proj_list; // For Machine nodes killing many values
duke@0 92
kvn@168 93 Node_Array _shared_nodes;
duke@0 94
duke@0 95 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
never@222 96 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
duke@0 97
duke@0 98 // Accessors for the inherited field PhaseTransform::_nodes:
duke@0 99 void grow_new_node_array(uint idx_limit) {
duke@0 100 _nodes.map(idx_limit-1, NULL);
duke@0 101 }
duke@0 102 bool has_new_node(const Node* n) const {
duke@0 103 return _nodes.at(n->_idx) != NULL;
duke@0 104 }
duke@0 105 Node* new_node(const Node* n) const {
duke@0 106 assert(has_new_node(n), "set before get");
duke@0 107 return _nodes.at(n->_idx);
duke@0 108 }
duke@0 109 void set_new_node(const Node* n, Node *nn) {
duke@0 110 assert(!has_new_node(n), "set only once");
duke@0 111 _nodes.map(n->_idx, nn);
duke@0 112 }
duke@0 113
duke@0 114 #ifdef ASSERT
duke@0 115 // Make sure only new nodes are reachable from this node
duke@0 116 void verify_new_nodes_only(Node* root);
kvn@216 117
kvn@216 118 Node* _mem_node; // Ideal memory node consumed by mach node
duke@0 119 #endif
duke@0 120
kvn@729 121 // Mach node for ConP #NULL
kvn@729 122 MachNode* _mach_null;
kvn@729 123
duke@0 124 public:
duke@0 125 int LabelRootDepth;
duke@0 126 static const int base2reg[]; // Map Types to machine register types
duke@0 127 // Convert ideal machine register to a register mask for spill-loads
duke@0 128 static const RegMask *idealreg2regmask[];
twisti@1137 129 RegMask *idealreg2spillmask [_last_machine_leaf];
twisti@1137 130 RegMask *idealreg2debugmask [_last_machine_leaf];
twisti@1137 131 RegMask *idealreg2mhdebugmask[_last_machine_leaf];
duke@0 132 void init_spill_mask( Node *ret );
duke@0 133 // Convert machine register number to register mask
duke@0 134 static uint mreg2regmask_max;
duke@0 135 static RegMask mreg2regmask[];
duke@0 136 static RegMask STACK_ONLY_mask;
duke@0 137
kvn@729 138 MachNode* mach_null() const { return _mach_null; }
kvn@729 139
duke@0 140 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
duke@0 141 void set_shared( Node *n ) { _shared.set(n->_idx); }
duke@0 142 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
duke@0 143 void set_visited( Node *n ) { _visited.set(n->_idx); }
duke@0 144 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
duke@0 145 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
duke@0 146
duke@0 147 // Mode bit to tell DFA and expand rules whether we are running after
duke@0 148 // (or during) register selection. Usually, the matcher runs before,
duke@0 149 // but it will also get called to generate post-allocation spill code.
duke@0 150 // In this situation, it is a deadly error to attempt to allocate more
duke@0 151 // temporary registers.
duke@0 152 bool _allocation_started;
duke@0 153
duke@0 154 // Machine register names
duke@0 155 static const char *regName[];
duke@0 156 // Machine register encodings
duke@0 157 static const unsigned char _regEncode[];
duke@0 158 // Machine Node names
duke@0 159 const char **_ruleName;
duke@0 160 // Rules that are cheaper to rematerialize than to spill
duke@0 161 static const uint _begin_rematerialize;
duke@0 162 static const uint _end_rematerialize;
duke@0 163
duke@0 164 // An array of chars, from 0 to _last_Mach_Reg.
duke@0 165 // No Save = 'N' (for register windows)
duke@0 166 // Save on Entry = 'E'
duke@0 167 // Save on Call = 'C'
duke@0 168 // Always Save = 'A' (same as SOE + SOC)
duke@0 169 const char *_register_save_policy;
duke@0 170 const char *_c_reg_save_policy;
duke@0 171 // Convert a machine register to a machine register type, so-as to
duke@0 172 // properly match spill code.
duke@0 173 const int *_register_save_type;
duke@0 174 // Maps from machine register to boolean; true if machine register can
duke@0 175 // be holding a call argument in some signature.
duke@0 176 static bool can_be_java_arg( int reg );
duke@0 177 // Maps from machine register to boolean; true if machine register holds
duke@0 178 // a spillable argument.
duke@0 179 static bool is_spillable_arg( int reg );
duke@0 180
duke@0 181 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
duke@0 182 // List is valid in the post-matching space.
duke@0 183 Node_List _null_check_tests;
kvn@368 184 void collect_null_checks( Node *proj, Node *orig_proj );
duke@0 185 void validate_null_checks( );
duke@0 186
duke@0 187 Matcher( Node_List &proj_list );
duke@0 188
duke@0 189 // Select instructions for entire method
duke@0 190 void match( );
duke@0 191 // Helper for match
duke@0 192 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
duke@0 193
duke@0 194 // Transform, then walk. Does implicit DCE while walking.
duke@0 195 // Name changed from "transform" to avoid it being virtual.
duke@0 196 Node *xform( Node *old_space_node, int Nodes );
duke@0 197
duke@0 198 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
duke@0 199 MachNode *match_tree( const Node *n );
duke@0 200 MachNode *match_sfpt( SafePointNode *sfpt );
duke@0 201 // Helper for match_sfpt
duke@0 202 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
duke@0 203
duke@0 204 // Initialize first stack mask and related masks.
duke@0 205 void init_first_stack_mask();
duke@0 206
duke@0 207 // If we should save-on-entry this register
duke@0 208 bool is_save_on_entry( int reg );
duke@0 209
duke@0 210 // Fixup the save-on-entry registers
duke@0 211 void Fixup_Save_On_Entry( );
duke@0 212
duke@0 213 // --- Frame handling ---
duke@0 214
duke@0 215 // Register number of the stack slot corresponding to the incoming SP.
duke@0 216 // Per the Big Picture in the AD file, it is:
duke@0 217 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
duke@0 218 OptoReg::Name _old_SP;
duke@0 219
duke@0 220 // Register number of the stack slot corresponding to the highest incoming
duke@0 221 // argument on the stack. Per the Big Picture in the AD file, it is:
duke@0 222 // _old_SP + out_preserve_stack_slots + incoming argument size.
duke@0 223 OptoReg::Name _in_arg_limit;
duke@0 224
duke@0 225 // Register number of the stack slot corresponding to the new SP.
duke@0 226 // Per the Big Picture in the AD file, it is:
duke@0 227 // _in_arg_limit + pad0
duke@0 228 OptoReg::Name _new_SP;
duke@0 229
duke@0 230 // Register number of the stack slot corresponding to the highest outgoing
duke@0 231 // argument on the stack. Per the Big Picture in the AD file, it is:
duke@0 232 // _new_SP + max outgoing arguments of all calls
duke@0 233 OptoReg::Name _out_arg_limit;
duke@0 234
duke@0 235 OptoRegPair *_parm_regs; // Array of machine registers per argument
duke@0 236 RegMask *_calling_convention_mask; // Array of RegMasks per argument
duke@0 237
twisti@775 238 // Does matcher have a match rule for this ideal node?
duke@0 239 static const bool has_match_rule(int opcode);
duke@0 240 static const bool _hasMatchRule[_last_opcode];
duke@0 241
twisti@775 242 // Does matcher have a match rule for this ideal node and is the
twisti@775 243 // predicate (if there is one) true?
twisti@775 244 // NOTE: If this function is used more commonly in the future, ADLC
twisti@775 245 // should generate this one.
twisti@775 246 static const bool match_rule_supported(int opcode);
twisti@775 247
duke@0 248 // Used to determine if we have fast l2f conversion
duke@0 249 // USII has it, USIII doesn't
duke@0 250 static const bool convL2FSupported(void);
duke@0 251
duke@0 252 // Vector width in bytes
duke@0 253 static const uint vector_width_in_bytes(void);
duke@0 254
duke@0 255 // Vector ideal reg
duke@0 256 static const uint vector_ideal_reg(void);
duke@0 257
duke@0 258 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
duke@0 259 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
duke@0 260 // Depends on the details of 64-bit constant generation on the CPU.
duke@0 261 static const bool isSimpleConstant64(jlong con);
duke@0 262
duke@0 263 // These calls are all generated by the ADLC
duke@0 264
duke@0 265 // TRUE - grows up, FALSE - grows down (Intel)
duke@0 266 virtual bool stack_direction() const;
duke@0 267
duke@0 268 // Java-Java calling convention
duke@0 269 // (what you use when Java calls Java)
duke@0 270
duke@0 271 // Alignment of stack in bytes, standard Intel word alignment is 4.
duke@0 272 // Sparc probably wants at least double-word (8).
duke@0 273 static uint stack_alignment_in_bytes();
duke@0 274 // Alignment of stack, measured in stack slots.
duke@0 275 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
duke@0 276 static uint stack_alignment_in_slots() {
duke@0 277 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
duke@0 278 }
duke@0 279
duke@0 280 // Array mapping arguments to registers. Argument 0 is usually the 'this'
duke@0 281 // pointer. Registers can include stack-slots and regular registers.
duke@0 282 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
duke@0 283
duke@0 284 // Convert a sig into a calling convention register layout
duke@0 285 // and find interesting things about it.
duke@0 286 static OptoReg::Name find_receiver( bool is_outgoing );
duke@0 287 // Return address register. On Intel it is a stack-slot. On PowerPC
duke@0 288 // it is the Link register. On Sparc it is r31?
duke@0 289 virtual OptoReg::Name return_addr() const;
duke@0 290 RegMask _return_addr_mask;
duke@0 291 // Return value register. On Intel it is EAX. On Sparc i0/o0.
duke@0 292 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
duke@0 293 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
duke@0 294 RegMask _return_value_mask;
duke@0 295 // Inline Cache Register
duke@0 296 static OptoReg::Name inline_cache_reg();
duke@0 297 static const RegMask &inline_cache_reg_mask();
duke@0 298 static int inline_cache_reg_encode();
duke@0 299
duke@0 300 // Register for DIVI projection of divmodI
duke@0 301 static RegMask divI_proj_mask();
duke@0 302 // Register for MODI projection of divmodI
duke@0 303 static RegMask modI_proj_mask();
duke@0 304
duke@0 305 // Register for DIVL projection of divmodL
duke@0 306 static RegMask divL_proj_mask();
duke@0 307 // Register for MODL projection of divmodL
duke@0 308 static RegMask modL_proj_mask();
duke@0 309
kvn@1834 310 // Use hardware DIV instruction when it is faster than
kvn@1834 311 // a code which use multiply for division by constant.
kvn@1834 312 static bool use_asm_for_ldiv_by_con( jlong divisor );
kvn@1834 313
twisti@1137 314 static const RegMask method_handle_invoke_SP_save_mask();
twisti@1137 315
duke@0 316 // Java-Interpreter calling convention
duke@0 317 // (what you use when calling between compiled-Java and Interpreted-Java
duke@0 318
duke@0 319 // Number of callee-save + always-save registers
duke@0 320 // Ignores frame pointer and "special" registers
duke@0 321 static int number_of_saved_registers();
duke@0 322
duke@0 323 // The Method-klass-holder may be passed in the inline_cache_reg
duke@0 324 // and then expanded into the inline_cache_reg and a method_oop register
duke@0 325
duke@0 326 static OptoReg::Name interpreter_method_oop_reg();
duke@0 327 static const RegMask &interpreter_method_oop_reg_mask();
duke@0 328 static int interpreter_method_oop_reg_encode();
duke@0 329
duke@0 330 static OptoReg::Name compiler_method_oop_reg();
duke@0 331 static const RegMask &compiler_method_oop_reg_mask();
duke@0 332 static int compiler_method_oop_reg_encode();
duke@0 333
duke@0 334 // Interpreter's Frame Pointer Register
duke@0 335 static OptoReg::Name interpreter_frame_pointer_reg();
duke@0 336 static const RegMask &interpreter_frame_pointer_reg_mask();
duke@0 337
duke@0 338 // Java-Native calling convention
duke@0 339 // (what you use when intercalling between Java and C++ code)
duke@0 340
duke@0 341 // Array mapping arguments to registers. Argument 0 is usually the 'this'
duke@0 342 // pointer. Registers can include stack-slots and regular registers.
duke@0 343 static void c_calling_convention( BasicType*, VMRegPair *, uint );
duke@0 344 // Frame pointer. The frame pointer is kept at the base of the stack
duke@0 345 // and so is probably the stack pointer for most machines. On Intel
duke@0 346 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
duke@0 347 OptoReg::Name c_frame_pointer() const;
duke@0 348 static RegMask c_frame_ptr_mask;
duke@0 349
duke@0 350 // !!!!! Special stuff for building ScopeDescs
duke@0 351 virtual int regnum_to_fpu_offset(int regnum);
duke@0 352
duke@0 353 // Is this branch offset small enough to be addressed by a short branch?
kvn@2614 354 bool is_short_branch_offset(int rule, int br_size, int offset);
duke@0 355
duke@0 356 // Optional scaling for the parameter to the ClearArray/CopyArray node.
duke@0 357 static const bool init_array_count_is_in_bytes;
duke@0 358
duke@0 359 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
duke@0 360 // Anything this size or smaller may get converted to discrete scalar stores.
duke@0 361 static const int init_array_short_size;
duke@0 362
duke@0 363 // Should the Matcher clone shifts on addressing modes, expecting them to
duke@0 364 // be subsumed into complex addressing expressions or compute them into
duke@0 365 // registers? True for Intel but false for most RISCs
duke@0 366 static const bool clone_shift_expressions;
duke@0 367
twisti@1915 368 // Should constant table entries be accessed with loads using
twisti@1915 369 // absolute addressing? True for x86 but false for most RISCs.
twisti@1915 370 static const bool constant_table_absolute_addressing;
twisti@1915 371
kvn@1495 372 static bool narrow_oop_use_complex_address();
kvn@1495 373
kvn@1495 374 // Generate implicit null check for narrow oops if it can fold
kvn@1495 375 // into address expression (x64).
kvn@1495 376 //
kvn@1495 377 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression
kvn@1495 378 // NullCheck narrow_oop_reg
kvn@1495 379 //
kvn@1495 380 // When narrow oops can't fold into address expression (Sparc) and
kvn@1495 381 // base is not null use decode_not_null and normal implicit null check.
kvn@1495 382 // Note, decode_not_null node can be used here since it is referenced
kvn@1495 383 // only on non null path but it requires special handling, see
kvn@1495 384 // collect_null_checks():
kvn@1495 385 //
kvn@1495 386 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base'
kvn@1495 387 // [oop_reg + offset]
kvn@1495 388 // NullCheck oop_reg
kvn@1495 389 //
kvn@1495 390 // With Zero base and when narrow oops can not fold into address
kvn@1495 391 // expression use normal implicit null check since only shift
kvn@1495 392 // is needed to decode narrow oop.
kvn@1495 393 //
kvn@1495 394 // decode narrow_oop_reg, oop_reg // only 'shift'
kvn@1495 395 // [oop_reg + offset]
kvn@1495 396 // NullCheck oop_reg
kvn@1495 397 //
kvn@1495 398 inline static bool gen_narrow_oop_implicit_null_checks() {
kvn@1495 399 return Universe::narrow_oop_use_implicit_null_checks() &&
kvn@1495 400 (narrow_oop_use_complex_address() ||
kvn@1495 401 Universe::narrow_oop_base() != NULL);
kvn@1495 402 }
kvn@1495 403
duke@0 404 // Is it better to copy float constants, or load them directly from memory?
duke@0 405 // Intel can load a float constant from a direct address, requiring no
duke@0 406 // extra registers. Most RISCs will have to materialize an address into a
duke@0 407 // register first, so they may as well materialize the constant immediately.
duke@0 408 static const bool rematerialize_float_constants;
duke@0 409
duke@0 410 // If CPU can load and store mis-aligned doubles directly then no fixup is
duke@0 411 // needed. Else we split the double into 2 integer pieces and move it
duke@0 412 // piece-by-piece. Only happens when passing doubles into C code or when
duke@0 413 // calling i2c adapters as the Java calling convention forces doubles to be
duke@0 414 // aligned.
duke@0 415 static const bool misaligned_doubles_ok;
duke@0 416
duke@0 417 // Perform a platform dependent implicit null fixup. This is needed
duke@0 418 // on windows95 to take care of some unusual register constraints.
duke@0 419 void pd_implicit_null_fixup(MachNode *load, uint idx);
duke@0 420
duke@0 421 // Advertise here if the CPU requires explicit rounding operations
duke@0 422 // to implement the UseStrictFP mode.
duke@0 423 static const bool strict_fp_requires_explicit_rounding;
duke@0 424
kvn@1274 425 // Are floats conerted to double when stored to stack during deoptimization?
kvn@1274 426 static bool float_in_double();
duke@0 427 // Do ints take an entire long register or just half?
duke@0 428 static const bool int_in_long;
duke@0 429
roland@2248 430 // Do the processor's shift instructions only use the low 5/6 bits
roland@2248 431 // of the count for 32/64 bit ints? If not we need to do the masking
roland@2248 432 // ourselves.
roland@2248 433 static const bool need_masked_shift_count;
roland@2248 434
duke@0 435 // This routine is run whenever a graph fails to match.
duke@0 436 // If it returns, the compiler should bailout to interpreter without error.
duke@0 437 // In non-product mode, SoftMatchFailure is false to detect non-canonical
duke@0 438 // graphs. Print a message and exit.
duke@0 439 static void soft_match_failure() {
duke@0 440 if( SoftMatchFailure ) return;
duke@0 441 else { fatal("SoftMatchFailure is not allowed except in product"); }
duke@0 442 }
duke@0 443
duke@0 444 // Check for a following volatile memory barrier without an
duke@0 445 // intervening load and thus we don't need a barrier here. We
duke@0 446 // retain the Node to act as a compiler ordering barrier.
duke@0 447 static bool post_store_load_barrier(const Node* mb);
duke@0 448
duke@0 449
duke@0 450 #ifdef ASSERT
duke@0 451 void dump_old2new_map(); // machine-independent to machine-dependent
never@222 452
never@222 453 Node* find_old_node(Node* new_node) {
never@222 454 return _new2old_map[new_node->_idx];
never@222 455 }
duke@0 456 #endif
duke@0 457 };
stefank@1879 458
stefank@1879 459 #endif // SHARE_VM_OPTO_MATCHER_HPP