annotate src/share/vm/opto/matcher.hpp @ 168:7793bd37a336

6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops Summary: Generate addresses and implicit null checks with narrow oops to avoid decoding. Reviewed-by: jrose, never
author kvn
date Thu, 29 May 2008 12:04:14 -0700
parents a61af66fc99e
children d1605aabd0a1 8d191a7697e2
rev   line source
duke@0 1 /*
duke@0 2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 class Compile;
duke@0 26 class Node;
duke@0 27 class MachNode;
duke@0 28 class MachTypeNode;
duke@0 29 class MachOper;
duke@0 30
duke@0 31 //---------------------------Matcher-------------------------------------------
duke@0 32 class Matcher : public PhaseTransform {
duke@0 33 friend class VMStructs;
duke@0 34 // Private arena of State objects
duke@0 35 ResourceArea _states_arena;
duke@0 36
duke@0 37 VectorSet _visited; // Visit bits
duke@0 38
duke@0 39 // Used to control the Label pass
duke@0 40 VectorSet _shared; // Shared Ideal Node
duke@0 41 VectorSet _dontcare; // Nothing the matcher cares about
duke@0 42
duke@0 43 // Private methods which perform the actual matching and reduction
duke@0 44 // Walks the label tree, generating machine nodes
duke@0 45 MachNode *ReduceInst( State *s, int rule, Node *&mem);
duke@0 46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
duke@0 47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
duke@0 48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
duke@0 49
duke@0 50 // If this node already matched using "rule", return the MachNode for it.
kvn@168 51 MachNode* find_shared_node(Node* n, uint rule);
duke@0 52
duke@0 53 // Convert a dense opcode number to an expanded rule number
duke@0 54 const int *_reduceOp;
duke@0 55 const int *_leftOp;
duke@0 56 const int *_rightOp;
duke@0 57
duke@0 58 // Map dense opcode number to info on when rule is swallowed constant.
duke@0 59 const bool *_swallowed;
duke@0 60
duke@0 61 // Map dense rule number to determine if this is an instruction chain rule
duke@0 62 const uint _begin_inst_chain_rule;
duke@0 63 const uint _end_inst_chain_rule;
duke@0 64
duke@0 65 // We want to clone constants and possible CmpI-variants.
duke@0 66 // If we do not clone CmpI, then we can have many instances of
duke@0 67 // condition codes alive at once. This is OK on some chips and
duke@0 68 // bad on others. Hence the machine-dependent table lookup.
duke@0 69 const char *_must_clone;
duke@0 70
duke@0 71 // Find shared Nodes, or Nodes that otherwise are Matcher roots
duke@0 72 void find_shared( Node *n );
duke@0 73
duke@0 74 // Debug and profile information for nodes in old space:
duke@0 75 GrowableArray<Node_Notes*>* _old_node_note_array;
duke@0 76
duke@0 77 // Node labeling iterator for instruction selection
duke@0 78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
duke@0 79
duke@0 80 Node *transform( Node *dummy );
duke@0 81
duke@0 82 Node_List &_proj_list; // For Machine nodes killing many values
duke@0 83
kvn@168 84 Node_Array _shared_nodes;
duke@0 85
duke@0 86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
duke@0 87
duke@0 88 // Accessors for the inherited field PhaseTransform::_nodes:
duke@0 89 void grow_new_node_array(uint idx_limit) {
duke@0 90 _nodes.map(idx_limit-1, NULL);
duke@0 91 }
duke@0 92 bool has_new_node(const Node* n) const {
duke@0 93 return _nodes.at(n->_idx) != NULL;
duke@0 94 }
duke@0 95 Node* new_node(const Node* n) const {
duke@0 96 assert(has_new_node(n), "set before get");
duke@0 97 return _nodes.at(n->_idx);
duke@0 98 }
duke@0 99 void set_new_node(const Node* n, Node *nn) {
duke@0 100 assert(!has_new_node(n), "set only once");
duke@0 101 _nodes.map(n->_idx, nn);
duke@0 102 }
duke@0 103
duke@0 104 #ifdef ASSERT
duke@0 105 // Make sure only new nodes are reachable from this node
duke@0 106 void verify_new_nodes_only(Node* root);
duke@0 107 #endif
duke@0 108
duke@0 109 public:
duke@0 110 int LabelRootDepth;
duke@0 111 static const int base2reg[]; // Map Types to machine register types
duke@0 112 // Convert ideal machine register to a register mask for spill-loads
duke@0 113 static const RegMask *idealreg2regmask[];
duke@0 114 RegMask *idealreg2spillmask[_last_machine_leaf];
duke@0 115 RegMask *idealreg2debugmask[_last_machine_leaf];
duke@0 116 void init_spill_mask( Node *ret );
duke@0 117 // Convert machine register number to register mask
duke@0 118 static uint mreg2regmask_max;
duke@0 119 static RegMask mreg2regmask[];
duke@0 120 static RegMask STACK_ONLY_mask;
duke@0 121
duke@0 122 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
duke@0 123 void set_shared( Node *n ) { _shared.set(n->_idx); }
duke@0 124 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
duke@0 125 void set_visited( Node *n ) { _visited.set(n->_idx); }
duke@0 126 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
duke@0 127 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
duke@0 128
duke@0 129 // Mode bit to tell DFA and expand rules whether we are running after
duke@0 130 // (or during) register selection. Usually, the matcher runs before,
duke@0 131 // but it will also get called to generate post-allocation spill code.
duke@0 132 // In this situation, it is a deadly error to attempt to allocate more
duke@0 133 // temporary registers.
duke@0 134 bool _allocation_started;
duke@0 135
duke@0 136 // Machine register names
duke@0 137 static const char *regName[];
duke@0 138 // Machine register encodings
duke@0 139 static const unsigned char _regEncode[];
duke@0 140 // Machine Node names
duke@0 141 const char **_ruleName;
duke@0 142 // Rules that are cheaper to rematerialize than to spill
duke@0 143 static const uint _begin_rematerialize;
duke@0 144 static const uint _end_rematerialize;
duke@0 145
duke@0 146 // An array of chars, from 0 to _last_Mach_Reg.
duke@0 147 // No Save = 'N' (for register windows)
duke@0 148 // Save on Entry = 'E'
duke@0 149 // Save on Call = 'C'
duke@0 150 // Always Save = 'A' (same as SOE + SOC)
duke@0 151 const char *_register_save_policy;
duke@0 152 const char *_c_reg_save_policy;
duke@0 153 // Convert a machine register to a machine register type, so-as to
duke@0 154 // properly match spill code.
duke@0 155 const int *_register_save_type;
duke@0 156 // Maps from machine register to boolean; true if machine register can
duke@0 157 // be holding a call argument in some signature.
duke@0 158 static bool can_be_java_arg( int reg );
duke@0 159 // Maps from machine register to boolean; true if machine register holds
duke@0 160 // a spillable argument.
duke@0 161 static bool is_spillable_arg( int reg );
duke@0 162
duke@0 163 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
duke@0 164 // List is valid in the post-matching space.
duke@0 165 Node_List _null_check_tests;
duke@0 166 void collect_null_checks( Node *proj );
duke@0 167 void validate_null_checks( );
duke@0 168
duke@0 169 Matcher( Node_List &proj_list );
duke@0 170
duke@0 171 // Select instructions for entire method
duke@0 172 void match( );
duke@0 173 // Helper for match
duke@0 174 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
duke@0 175
duke@0 176 // Transform, then walk. Does implicit DCE while walking.
duke@0 177 // Name changed from "transform" to avoid it being virtual.
duke@0 178 Node *xform( Node *old_space_node, int Nodes );
duke@0 179
duke@0 180 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
duke@0 181 MachNode *match_tree( const Node *n );
duke@0 182 MachNode *match_sfpt( SafePointNode *sfpt );
duke@0 183 // Helper for match_sfpt
duke@0 184 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
duke@0 185
duke@0 186 // Initialize first stack mask and related masks.
duke@0 187 void init_first_stack_mask();
duke@0 188
duke@0 189 // If we should save-on-entry this register
duke@0 190 bool is_save_on_entry( int reg );
duke@0 191
duke@0 192 // Fixup the save-on-entry registers
duke@0 193 void Fixup_Save_On_Entry( );
duke@0 194
duke@0 195 // --- Frame handling ---
duke@0 196
duke@0 197 // Register number of the stack slot corresponding to the incoming SP.
duke@0 198 // Per the Big Picture in the AD file, it is:
duke@0 199 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
duke@0 200 OptoReg::Name _old_SP;
duke@0 201
duke@0 202 // Register number of the stack slot corresponding to the highest incoming
duke@0 203 // argument on the stack. Per the Big Picture in the AD file, it is:
duke@0 204 // _old_SP + out_preserve_stack_slots + incoming argument size.
duke@0 205 OptoReg::Name _in_arg_limit;
duke@0 206
duke@0 207 // Register number of the stack slot corresponding to the new SP.
duke@0 208 // Per the Big Picture in the AD file, it is:
duke@0 209 // _in_arg_limit + pad0
duke@0 210 OptoReg::Name _new_SP;
duke@0 211
duke@0 212 // Register number of the stack slot corresponding to the highest outgoing
duke@0 213 // argument on the stack. Per the Big Picture in the AD file, it is:
duke@0 214 // _new_SP + max outgoing arguments of all calls
duke@0 215 OptoReg::Name _out_arg_limit;
duke@0 216
duke@0 217 OptoRegPair *_parm_regs; // Array of machine registers per argument
duke@0 218 RegMask *_calling_convention_mask; // Array of RegMasks per argument
duke@0 219
duke@0 220 // Does matcher support this ideal node?
duke@0 221 static const bool has_match_rule(int opcode);
duke@0 222 static const bool _hasMatchRule[_last_opcode];
duke@0 223
duke@0 224 // Used to determine if we have fast l2f conversion
duke@0 225 // USII has it, USIII doesn't
duke@0 226 static const bool convL2FSupported(void);
duke@0 227
duke@0 228 // Vector width in bytes
duke@0 229 static const uint vector_width_in_bytes(void);
duke@0 230
duke@0 231 // Vector ideal reg
duke@0 232 static const uint vector_ideal_reg(void);
duke@0 233
duke@0 234 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
duke@0 235 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
duke@0 236 // Depends on the details of 64-bit constant generation on the CPU.
duke@0 237 static const bool isSimpleConstant64(jlong con);
duke@0 238
duke@0 239 // These calls are all generated by the ADLC
duke@0 240
duke@0 241 // TRUE - grows up, FALSE - grows down (Intel)
duke@0 242 virtual bool stack_direction() const;
duke@0 243
duke@0 244 // Java-Java calling convention
duke@0 245 // (what you use when Java calls Java)
duke@0 246
duke@0 247 // Alignment of stack in bytes, standard Intel word alignment is 4.
duke@0 248 // Sparc probably wants at least double-word (8).
duke@0 249 static uint stack_alignment_in_bytes();
duke@0 250 // Alignment of stack, measured in stack slots.
duke@0 251 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
duke@0 252 static uint stack_alignment_in_slots() {
duke@0 253 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
duke@0 254 }
duke@0 255
duke@0 256 // Array mapping arguments to registers. Argument 0 is usually the 'this'
duke@0 257 // pointer. Registers can include stack-slots and regular registers.
duke@0 258 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
duke@0 259
duke@0 260 // Convert a sig into a calling convention register layout
duke@0 261 // and find interesting things about it.
duke@0 262 static OptoReg::Name find_receiver( bool is_outgoing );
duke@0 263 // Return address register. On Intel it is a stack-slot. On PowerPC
duke@0 264 // it is the Link register. On Sparc it is r31?
duke@0 265 virtual OptoReg::Name return_addr() const;
duke@0 266 RegMask _return_addr_mask;
duke@0 267 // Return value register. On Intel it is EAX. On Sparc i0/o0.
duke@0 268 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
duke@0 269 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
duke@0 270 RegMask _return_value_mask;
duke@0 271 // Inline Cache Register
duke@0 272 static OptoReg::Name inline_cache_reg();
duke@0 273 static const RegMask &inline_cache_reg_mask();
duke@0 274 static int inline_cache_reg_encode();
duke@0 275
duke@0 276 // Register for DIVI projection of divmodI
duke@0 277 static RegMask divI_proj_mask();
duke@0 278 // Register for MODI projection of divmodI
duke@0 279 static RegMask modI_proj_mask();
duke@0 280
duke@0 281 // Register for DIVL projection of divmodL
duke@0 282 static RegMask divL_proj_mask();
duke@0 283 // Register for MODL projection of divmodL
duke@0 284 static RegMask modL_proj_mask();
duke@0 285
duke@0 286 // Java-Interpreter calling convention
duke@0 287 // (what you use when calling between compiled-Java and Interpreted-Java
duke@0 288
duke@0 289 // Number of callee-save + always-save registers
duke@0 290 // Ignores frame pointer and "special" registers
duke@0 291 static int number_of_saved_registers();
duke@0 292
duke@0 293 // The Method-klass-holder may be passed in the inline_cache_reg
duke@0 294 // and then expanded into the inline_cache_reg and a method_oop register
duke@0 295
duke@0 296 static OptoReg::Name interpreter_method_oop_reg();
duke@0 297 static const RegMask &interpreter_method_oop_reg_mask();
duke@0 298 static int interpreter_method_oop_reg_encode();
duke@0 299
duke@0 300 static OptoReg::Name compiler_method_oop_reg();
duke@0 301 static const RegMask &compiler_method_oop_reg_mask();
duke@0 302 static int compiler_method_oop_reg_encode();
duke@0 303
duke@0 304 // Interpreter's Frame Pointer Register
duke@0 305 static OptoReg::Name interpreter_frame_pointer_reg();
duke@0 306 static const RegMask &interpreter_frame_pointer_reg_mask();
duke@0 307
duke@0 308 // Java-Native calling convention
duke@0 309 // (what you use when intercalling between Java and C++ code)
duke@0 310
duke@0 311 // Array mapping arguments to registers. Argument 0 is usually the 'this'
duke@0 312 // pointer. Registers can include stack-slots and regular registers.
duke@0 313 static void c_calling_convention( BasicType*, VMRegPair *, uint );
duke@0 314 // Frame pointer. The frame pointer is kept at the base of the stack
duke@0 315 // and so is probably the stack pointer for most machines. On Intel
duke@0 316 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
duke@0 317 OptoReg::Name c_frame_pointer() const;
duke@0 318 static RegMask c_frame_ptr_mask;
duke@0 319
duke@0 320 // !!!!! Special stuff for building ScopeDescs
duke@0 321 virtual int regnum_to_fpu_offset(int regnum);
duke@0 322
duke@0 323 // Is this branch offset small enough to be addressed by a short branch?
duke@0 324 bool is_short_branch_offset(int offset);
duke@0 325
duke@0 326 // Optional scaling for the parameter to the ClearArray/CopyArray node.
duke@0 327 static const bool init_array_count_is_in_bytes;
duke@0 328
duke@0 329 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
duke@0 330 // Anything this size or smaller may get converted to discrete scalar stores.
duke@0 331 static const int init_array_short_size;
duke@0 332
duke@0 333 // Should the Matcher clone shifts on addressing modes, expecting them to
duke@0 334 // be subsumed into complex addressing expressions or compute them into
duke@0 335 // registers? True for Intel but false for most RISCs
duke@0 336 static const bool clone_shift_expressions;
duke@0 337
duke@0 338 // Is it better to copy float constants, or load them directly from memory?
duke@0 339 // Intel can load a float constant from a direct address, requiring no
duke@0 340 // extra registers. Most RISCs will have to materialize an address into a
duke@0 341 // register first, so they may as well materialize the constant immediately.
duke@0 342 static const bool rematerialize_float_constants;
duke@0 343
duke@0 344 // If CPU can load and store mis-aligned doubles directly then no fixup is
duke@0 345 // needed. Else we split the double into 2 integer pieces and move it
duke@0 346 // piece-by-piece. Only happens when passing doubles into C code or when
duke@0 347 // calling i2c adapters as the Java calling convention forces doubles to be
duke@0 348 // aligned.
duke@0 349 static const bool misaligned_doubles_ok;
duke@0 350
duke@0 351 // Perform a platform dependent implicit null fixup. This is needed
duke@0 352 // on windows95 to take care of some unusual register constraints.
duke@0 353 void pd_implicit_null_fixup(MachNode *load, uint idx);
duke@0 354
duke@0 355 // Advertise here if the CPU requires explicit rounding operations
duke@0 356 // to implement the UseStrictFP mode.
duke@0 357 static const bool strict_fp_requires_explicit_rounding;
duke@0 358
duke@0 359 // Do floats take an entire double register or just half?
duke@0 360 static const bool float_in_double;
duke@0 361 // Do ints take an entire long register or just half?
duke@0 362 static const bool int_in_long;
duke@0 363
duke@0 364 // This routine is run whenever a graph fails to match.
duke@0 365 // If it returns, the compiler should bailout to interpreter without error.
duke@0 366 // In non-product mode, SoftMatchFailure is false to detect non-canonical
duke@0 367 // graphs. Print a message and exit.
duke@0 368 static void soft_match_failure() {
duke@0 369 if( SoftMatchFailure ) return;
duke@0 370 else { fatal("SoftMatchFailure is not allowed except in product"); }
duke@0 371 }
duke@0 372
duke@0 373 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
duke@0 374 // acting as an Acquire and thus we don't need an Acquire here. We
duke@0 375 // retain the Node to act as a compiler ordering barrier.
duke@0 376 static bool prior_fast_lock( const Node *acq );
duke@0 377
duke@0 378 // Used by the DFA in dfa_sparc.cpp. Check for a following
duke@0 379 // FastUnLock acting as a Release and thus we don't need a Release
duke@0 380 // here. We retain the Node to act as a compiler ordering barrier.
duke@0 381 static bool post_fast_unlock( const Node *rel );
duke@0 382
duke@0 383 // Check for a following volatile memory barrier without an
duke@0 384 // intervening load and thus we don't need a barrier here. We
duke@0 385 // retain the Node to act as a compiler ordering barrier.
duke@0 386 static bool post_store_load_barrier(const Node* mb);
duke@0 387
duke@0 388
duke@0 389 #ifdef ASSERT
duke@0 390 void dump_old2new_map(); // machine-independent to machine-dependent
duke@0 391 #endif
duke@0 392 };