annotate src/cpu/sparc/vm/assembler_sparc.inline.hpp @ 2013:c17b998c5926

7011627: C1: call_RT must support targets that don't fit in wdisp30 Summary: Make both compilers emit near and far calls when necessary. Reviewed-by: never, kvn, phh
author iveresov
date Wed, 12 Jan 2011 18:33:25 -0800
parents 2f644f85485d
children
rev   line source
duke@0 1 /*
iveresov@2013 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1472 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 * or visit www.oracle.com if you need additional information or have any
trims@1472 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1885 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
stefank@1885 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
stefank@1885 27
stefank@1885 28 #include "asm/assembler.inline.hpp"
stefank@1885 29 #include "asm/codeBuffer.hpp"
stefank@1885 30 #include "code/codeCache.hpp"
stefank@1885 31 #include "runtime/handles.inline.hpp"
stefank@1885 32
duke@0 33 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
duke@0 34 jint& stub_inst = *(jint*) branch;
duke@0 35 stub_inst = patched_branch(target - branch, stub_inst, 0);
duke@0 36 }
duke@0 37
duke@0 38 #ifndef PRODUCT
duke@0 39 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
duke@0 40 jint stub_inst = *(jint*) branch;
duke@0 41 print_instruction(stub_inst);
duke@0 42 ::tty->print("%s", " (unresolved)");
duke@0 43 }
duke@0 44 #endif // PRODUCT
duke@0 45
duke@0 46 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
duke@0 47
duke@0 48
twisti@727 49 inline int AddressLiteral::low10() const {
twisti@727 50 return Assembler::low10(value());
twisti@727 51 }
twisti@727 52
twisti@727 53
duke@0 54 // inlines for SPARC assembler -- dmu 5/97
duke@0 55
duke@0 56 inline void Assembler::check_delay() {
duke@0 57 # ifdef CHECK_DELAY
duke@0 58 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
duke@0 59 delay_state = no_delay;
duke@0 60 # endif
duke@0 61 }
duke@0 62
duke@0 63 inline void Assembler::emit_long(int x) {
duke@0 64 check_delay();
duke@0 65 AbstractAssembler::emit_long(x);
duke@0 66 }
duke@0 67
duke@0 68 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
duke@0 69 relocate(rtype);
duke@0 70 emit_long(x);
duke@0 71 }
duke@0 72
duke@0 73 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
duke@0 74 relocate(rspec);
duke@0 75 emit_long(x);
duke@0 76 }
duke@0 77
duke@0 78
twisti@727 79 inline void Assembler::add(Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
twisti@727 80 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
twisti@727 81 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
duke@0 82
duke@0 83 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
duke@0 84 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
duke@0 85
duke@0 86 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
duke@0 87 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
duke@0 88
duke@0 89 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
duke@0 90 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
duke@0 91
duke@0 92 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
duke@0 93 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
duke@0 94
duke@0 95 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
duke@0 96 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
duke@0 97
duke@0 98 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
duke@0 99 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
duke@0 100
duke@0 101 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
duke@0 102 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
duke@0 103
duke@0 104 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
duke@0 105 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 106
duke@0 107 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
duke@0 108 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
duke@0 109
twisti@1006 110 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
twisti@1006 111 if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
twisti@1006 112 else ldf(w, s1, s2.as_constant(), d);
twisti@1006 113 }
twisti@1006 114
twisti@727 115 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
twisti@727 116 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }
duke@0 117
twisti@727 118 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
duke@0 119
duke@0 120 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 121 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 122 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 123 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 124
duke@0 125 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@0 126 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 127 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@0 128 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 129 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 130 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 131
duke@0 132 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
duke@0 133 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 134
duke@0 135 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
duke@0 136 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 137 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
duke@0 138 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 139 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
duke@0 140 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 141 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
duke@0 142 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 143 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
duke@0 144 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 145
duke@0 146 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
duke@0 147 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 148 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
duke@0 149 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 150
duke@0 151 #ifdef _LP64
duke@0 152 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
twisti@727 153 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
twisti@727 154 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
duke@0 155 #else
twisti@727 156 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
twisti@727 157 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
duke@0 158 #endif
duke@0 159
twisti@727 160 #ifdef ASSERT
twisti@727 161 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@727 162 # ifdef _LP64
twisti@727 163 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }
twisti@727 164 # else
twisti@727 165 inline void Assembler::ld( Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }
twisti@727 166 # endif
twisti@727 167 #endif
twisti@727 168
twisti@727 169 inline void Assembler::ld( const Address& a, Register d, int offset) {
twisti@727 170 if (a.has_index()) { assert(offset == 0, ""); ld( a.base(), a.index(), d); }
twisti@727 171 else { ld( a.base(), a.disp() + offset, d); }
jrose@622 172 }
twisti@727 173 inline void Assembler::ldsb(const Address& a, Register d, int offset) {
twisti@727 174 if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(), d); }
twisti@727 175 else { ldsb(a.base(), a.disp() + offset, d); }
jrose@622 176 }
twisti@727 177 inline void Assembler::ldsh(const Address& a, Register d, int offset) {
twisti@727 178 if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(), d); }
twisti@727 179 else { ldsh(a.base(), a.disp() + offset, d); }
jrose@622 180 }
twisti@727 181 inline void Assembler::ldsw(const Address& a, Register d, int offset) {
twisti@727 182 if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(), d); }
twisti@727 183 else { ldsw(a.base(), a.disp() + offset, d); }
jrose@622 184 }
twisti@727 185 inline void Assembler::ldub(const Address& a, Register d, int offset) {
twisti@727 186 if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(), d); }
twisti@727 187 else { ldub(a.base(), a.disp() + offset, d); }
jrose@622 188 }
twisti@727 189 inline void Assembler::lduh(const Address& a, Register d, int offset) {
twisti@727 190 if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(), d); }
twisti@727 191 else { lduh(a.base(), a.disp() + offset, d); }
jrose@622 192 }
twisti@727 193 inline void Assembler::lduw(const Address& a, Register d, int offset) {
twisti@727 194 if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(), d); }
twisti@727 195 else { lduw(a.base(), a.disp() + offset, d); }
jrose@622 196 }
twisti@727 197 inline void Assembler::ldd( const Address& a, Register d, int offset) {
twisti@727 198 if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(), d); }
twisti@727 199 else { ldd( a.base(), a.disp() + offset, d); }
jrose@622 200 }
twisti@727 201 inline void Assembler::ldx( const Address& a, Register d, int offset) {
twisti@727 202 if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(), d); }
twisti@727 203 else { ldx( a.base(), a.disp() + offset, d); }
jrose@622 204 }
jrose@622 205
twisti@727 206 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }
twisti@727 207 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }
twisti@727 208 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }
twisti@727 209 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }
twisti@727 210 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }
twisti@727 211 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }
twisti@727 212 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }
twisti@727 213 inline void Assembler::ld( Register s1, RegisterOrConstant s2, Register d) { ld( Address(s1, s2), d); }
twisti@727 214 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }
twisti@727 215
jrose@622 216 // form effective addresses this way:
jrose@1836 217 inline void Assembler::add(const Address& a, Register d, int offset) {
jrose@1836 218 if (a.has_index()) add(a.base(), a.index(), d);
jrose@1836 219 else { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
jrose@1836 220 if (offset != 0) add(d, offset, d);
jrose@1836 221 }
twisti@1423 222 inline void Assembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
twisti@1423 223 if (s2.is_register()) add(s1, s2.as_register(), d);
jrose@622 224 else { add(s1, s2.as_constant() + offset, d); offset = 0; }
jrose@622 225 if (offset != 0) add(d, offset, d);
jrose@622 226 }
duke@0 227
twisti@1423 228 inline void Assembler::andn(Register s1, RegisterOrConstant s2, Register d) {
twisti@1423 229 if (s2.is_register()) andn(s1, s2.as_register(), d);
twisti@1423 230 else andn(s1, s2.as_constant(), d);
twisti@1423 231 }
twisti@1423 232
duke@0 233 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
duke@0 234 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 235
duke@0 236
duke@0 237 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
duke@0 238 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 239
duke@0 240 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
duke@0 241
duke@0 242
duke@0 243 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
duke@0 244 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
duke@0 245
duke@0 246 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
duke@0 247
duke@0 248 // pp 222
duke@0 249
twisti@1006 250 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {
twisti@1006 251 if (s2.is_register()) stf(w, d, s1, s2.as_register());
twisti@1006 252 else stf(w, d, s1, s2.as_constant());
twisti@1006 253 }
twisti@1006 254
duke@0 255 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
duke@0 256 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 257
duke@0 258 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
duke@0 259
duke@0 260 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 261 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 262 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 263 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 264
duke@0 265 // p 226
duke@0 266
duke@0 267 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
duke@0 268 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 269 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
duke@0 270 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 271 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
duke@0 272 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 273
duke@0 274
duke@0 275 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
duke@0 276 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 277 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
duke@0 278 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 279
twisti@727 280 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
twisti@727 281 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
duke@0 282
twisti@727 283 #ifdef ASSERT
twisti@727 284 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@727 285 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }
twisti@727 286 #endif
twisti@727 287
twisti@727 288 inline void Assembler::stb(Register d, const Address& a, int offset) {
twisti@727 289 if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index() ); }
twisti@727 290 else { stb(d, a.base(), a.disp() + offset); }
jrose@622 291 }
twisti@727 292 inline void Assembler::sth(Register d, const Address& a, int offset) {
twisti@727 293 if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index() ); }
twisti@727 294 else { sth(d, a.base(), a.disp() + offset); }
jrose@622 295 }
twisti@727 296 inline void Assembler::stw(Register d, const Address& a, int offset) {
twisti@727 297 if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index() ); }
twisti@727 298 else { stw(d, a.base(), a.disp() + offset); }
jrose@622 299 }
twisti@727 300 inline void Assembler::st( Register d, const Address& a, int offset) {
twisti@727 301 if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index() ); }
twisti@727 302 else { st( d, a.base(), a.disp() + offset); }
jrose@622 303 }
twisti@727 304 inline void Assembler::std(Register d, const Address& a, int offset) {
twisti@727 305 if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index() ); }
twisti@727 306 else { std(d, a.base(), a.disp() + offset); }
twisti@727 307 }
twisti@727 308 inline void Assembler::stx(Register d, const Address& a, int offset) {
twisti@727 309 if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index() ); }
twisti@727 310 else { stx(d, a.base(), a.disp() + offset); }
jrose@622 311 }
jrose@622 312
twisti@727 313 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }
twisti@727 314 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }
twisti@1006 315 inline void Assembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }
twisti@727 316 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }
twisti@727 317 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }
twisti@727 318 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }
duke@0 319
duke@0 320 // v8 p 99
duke@0 321
duke@0 322 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
duke@0 323 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 324 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
duke@0 325 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 326 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
duke@0 327 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 328 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
duke@0 329 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 330
twisti@1921 331 inline void Assembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) {
twisti@1921 332 if (s2.is_register()) sub(s1, s2.as_register(), d);
twisti@1921 333 else { sub(s1, s2.as_constant() + offset, d); offset = 0; }
twisti@1921 334 if (offset != 0) sub(d, offset, d);
twisti@1921 335 }
duke@0 336
duke@0 337 // pp 231
duke@0 338
duke@0 339 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
duke@0 340 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
duke@0 341
duke@0 342 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
duke@0 343
duke@0 344
duke@0 345 // Use the right loads/stores for the platform
duke@0 346 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
duke@0 347 #ifdef _LP64
twisti@727 348 Assembler::ldx(s1, s2, d);
duke@0 349 #else
twisti@727 350 Assembler::ld( s1, s2, d);
duke@0 351 #endif
duke@0 352 }
duke@0 353
duke@0 354 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
duke@0 355 #ifdef _LP64
twisti@727 356 Assembler::ldx(s1, simm13a, d);
duke@0 357 #else
twisti@727 358 Assembler::ld( s1, simm13a, d);
duke@0 359 #endif
duke@0 360 }
duke@0 361
twisti@727 362 #ifdef ASSERT
twisti@727 363 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@727 364 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {
twisti@727 365 ld_ptr(s1, in_bytes(simm13a), d);
twisti@727 366 }
twisti@727 367 #endif
twisti@727 368
jrose@665 369 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
jrose@622 370 #ifdef _LP64
twisti@727 371 Assembler::ldx(s1, s2, d);
jrose@622 372 #else
twisti@727 373 Assembler::ld( s1, s2, d);
jrose@622 374 #endif
jrose@622 375 }
jrose@622 376
twisti@727 377 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {
duke@0 378 #ifdef _LP64
twisti@727 379 Assembler::ldx(a, d, offset);
duke@0 380 #else
twisti@727 381 Assembler::ld( a, d, offset);
duke@0 382 #endif
duke@0 383 }
duke@0 384
duke@0 385 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
duke@0 386 #ifdef _LP64
twisti@727 387 Assembler::stx(d, s1, s2);
duke@0 388 #else
duke@0 389 Assembler::st( d, s1, s2);
duke@0 390 #endif
duke@0 391 }
duke@0 392
duke@0 393 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
duke@0 394 #ifdef _LP64
twisti@727 395 Assembler::stx(d, s1, simm13a);
duke@0 396 #else
duke@0 397 Assembler::st( d, s1, simm13a);
duke@0 398 #endif
duke@0 399 }
duke@0 400
twisti@727 401 #ifdef ASSERT
twisti@727 402 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
twisti@727 403 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {
twisti@727 404 st_ptr(d, s1, in_bytes(simm13a));
twisti@727 405 }
twisti@727 406 #endif
twisti@727 407
jrose@665 408 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
jrose@622 409 #ifdef _LP64
twisti@727 410 Assembler::stx(d, s1, s2);
jrose@622 411 #else
jrose@622 412 Assembler::st( d, s1, s2);
jrose@622 413 #endif
jrose@622 414 }
jrose@622 415
twisti@727 416 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {
duke@0 417 #ifdef _LP64
twisti@727 418 Assembler::stx(d, a, offset);
duke@0 419 #else
twisti@727 420 Assembler::st( d, a, offset);
duke@0 421 #endif
duke@0 422 }
duke@0 423
duke@0 424 // Use the right loads/stores for the platform
duke@0 425 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
duke@0 426 #ifdef _LP64
duke@0 427 Assembler::ldx(s1, s2, d);
duke@0 428 #else
duke@0 429 Assembler::ldd(s1, s2, d);
duke@0 430 #endif
duke@0 431 }
duke@0 432
duke@0 433 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
duke@0 434 #ifdef _LP64
duke@0 435 Assembler::ldx(s1, simm13a, d);
duke@0 436 #else
duke@0 437 Assembler::ldd(s1, simm13a, d);
duke@0 438 #endif
duke@0 439 }
duke@0 440
jrose@665 441 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
jrose@622 442 #ifdef _LP64
jrose@622 443 Assembler::ldx(s1, s2, d);
jrose@622 444 #else
jrose@622 445 Assembler::ldd(s1, s2, d);
jrose@622 446 #endif
jrose@622 447 }
jrose@622 448
twisti@727 449 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {
duke@0 450 #ifdef _LP64
twisti@727 451 Assembler::ldx(a, d, offset);
duke@0 452 #else
twisti@727 453 Assembler::ldd(a, d, offset);
duke@0 454 #endif
duke@0 455 }
duke@0 456
duke@0 457 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
duke@0 458 #ifdef _LP64
duke@0 459 Assembler::stx(d, s1, s2);
duke@0 460 #else
duke@0 461 Assembler::std(d, s1, s2);
duke@0 462 #endif
duke@0 463 }
duke@0 464
duke@0 465 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
duke@0 466 #ifdef _LP64
duke@0 467 Assembler::stx(d, s1, simm13a);
duke@0 468 #else
duke@0 469 Assembler::std(d, s1, simm13a);
duke@0 470 #endif
duke@0 471 }
duke@0 472
jrose@665 473 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
jrose@622 474 #ifdef _LP64
jrose@622 475 Assembler::stx(d, s1, s2);
jrose@622 476 #else
jrose@622 477 Assembler::std(d, s1, s2);
jrose@622 478 #endif
jrose@622 479 }
jrose@622 480
duke@0 481 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
duke@0 482 #ifdef _LP64
duke@0 483 Assembler::stx(d, a, offset);
duke@0 484 #else
duke@0 485 Assembler::std(d, a, offset);
duke@0 486 #endif
duke@0 487 }
duke@0 488
duke@0 489 // Functions for isolating 64 bit shifts for LP64
duke@0 490
duke@0 491 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
duke@0 492 #ifdef _LP64
duke@0 493 Assembler::sllx(s1, s2, d);
duke@0 494 #else
twisti@727 495 Assembler::sll( s1, s2, d);
duke@0 496 #endif
duke@0 497 }
duke@0 498
duke@0 499 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
duke@0 500 #ifdef _LP64
duke@0 501 Assembler::sllx(s1, imm6a, d);
duke@0 502 #else
twisti@727 503 Assembler::sll( s1, imm6a, d);
duke@0 504 #endif
duke@0 505 }
duke@0 506
duke@0 507 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
duke@0 508 #ifdef _LP64
duke@0 509 Assembler::srlx(s1, s2, d);
duke@0 510 #else
twisti@727 511 Assembler::srl( s1, s2, d);
duke@0 512 #endif
duke@0 513 }
duke@0 514
duke@0 515 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
duke@0 516 #ifdef _LP64
duke@0 517 Assembler::srlx(s1, imm6a, d);
duke@0 518 #else
twisti@727 519 Assembler::srl( s1, imm6a, d);
duke@0 520 #endif
duke@0 521 }
duke@0 522
jrose@665 523 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
jrose@623 524 if (s2.is_register()) sll_ptr(s1, s2.as_register(), d);
jrose@623 525 else sll_ptr(s1, s2.as_constant(), d);
jrose@623 526 }
jrose@623 527
duke@0 528 // Use the right branch for the platform
duke@0 529
duke@0 530 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@0 531 if (VM_Version::v9_instructions_work())
duke@0 532 Assembler::bp(c, a, icc, p, d, rt);
duke@0 533 else
duke@0 534 Assembler::br(c, a, d, rt);
duke@0 535 }
duke@0 536
duke@0 537 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
duke@0 538 br(c, a, p, target(L));
duke@0 539 }
duke@0 540
duke@0 541
duke@0 542 // Branch that tests either xcc or icc depending on the
duke@0 543 // architecture compiled (LP64 or not)
duke@0 544 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@0 545 #ifdef _LP64
duke@0 546 Assembler::bp(c, a, xcc, p, d, rt);
duke@0 547 #else
duke@0 548 MacroAssembler::br(c, a, p, d, rt);
duke@0 549 #endif
duke@0 550 }
duke@0 551
duke@0 552 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
duke@0 553 brx(c, a, p, target(L));
duke@0 554 }
duke@0 555
duke@0 556 inline void MacroAssembler::ba( bool a, Label& L ) {
duke@0 557 br(always, a, pt, L);
duke@0 558 }
duke@0 559
duke@0 560 // Warning: V9 only functions
duke@0 561 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
duke@0 562 Assembler::bp(c, a, cc, p, d, rt);
duke@0 563 }
duke@0 564
duke@0 565 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
duke@0 566 Assembler::bp(c, a, cc, p, L);
duke@0 567 }
duke@0 568
duke@0 569 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
duke@0 570 if (VM_Version::v9_instructions_work())
duke@0 571 fbp(c, a, fcc0, p, d, rt);
duke@0 572 else
duke@0 573 Assembler::fb(c, a, d, rt);
duke@0 574 }
duke@0 575
duke@0 576 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
duke@0 577 fb(c, a, p, target(L));
duke@0 578 }
duke@0 579
duke@0 580 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
duke@0 581 Assembler::fbp(c, a, cc, p, d, rt);
duke@0 582 }
duke@0 583
duke@0 584 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
duke@0 585 Assembler::fbp(c, a, cc, p, L);
duke@0 586 }
duke@0 587
duke@0 588 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
duke@0 589 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
duke@0 590
iveresov@2013 591 inline bool MacroAssembler::is_far_target(address d) {
iveresov@2013 592 return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());
iveresov@2013 593 }
iveresov@2013 594
duke@0 595 // Call with a check to see if we need to deal with the added
duke@0 596 // expense of relocation and if we overflow the displacement
iveresov@2013 597 // of the quick call instruction.
duke@0 598 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
duke@0 599 #ifdef _LP64
duke@0 600 intptr_t disp;
duke@0 601 // NULL is ok because it will be relocated later.
duke@0 602 // Must change NULL to a reachable address in order to
duke@0 603 // pass asserts here and in wdisp.
duke@0 604 if ( d == NULL )
duke@0 605 d = pc();
duke@0 606
duke@0 607 // Is this address within range of the call instruction?
duke@0 608 // If not, use the expensive instruction sequence
iveresov@2013 609 if (is_far_target(d)) {
duke@0 610 relocate(rt);
twisti@727 611 AddressLiteral dest(d);
twisti@727 612 jumpl_to(dest, O7, O7);
iveresov@2013 613 } else {
iveresov@2013 614 Assembler::call(d, rt);
duke@0 615 }
duke@0 616 #else
duke@0 617 Assembler::call( d, rt );
duke@0 618 #endif
duke@0 619 }
duke@0 620
duke@0 621 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
duke@0 622 MacroAssembler::call( target(L), rt);
duke@0 623 }
duke@0 624
duke@0 625
duke@0 626
duke@0 627 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
duke@0 628 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
duke@0 629
duke@0 630 // prefetch instruction
duke@0 631 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
duke@0 632 if (VM_Version::v9_instructions_work())
duke@0 633 Assembler::bp( never, true, xcc, pt, d, rt );
duke@0 634 }
duke@0 635 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
duke@0 636
duke@0 637
duke@0 638 // clobbers o7 on V8!!
duke@0 639 // returns delta from gotten pc to addr after
duke@0 640 inline int MacroAssembler::get_pc( Register d ) {
duke@0 641 int x = offset();
duke@0 642 if (VM_Version::v9_instructions_work())
duke@0 643 rdpc(d);
duke@0 644 else {
duke@0 645 Label lbl;
duke@0 646 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
duke@0 647 if (d == O7) delayed()->nop();
duke@0 648 else delayed()->mov(O7, d);
duke@0 649 bind(lbl);
duke@0 650 }
duke@0 651 return offset() - x;
duke@0 652 }
duke@0 653
duke@0 654
duke@0 655 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
duke@0 656
duke@0 657
duke@0 658 // Loads the current PC of the following instruction as an immediate value in
duke@0 659 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
duke@0 660 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
duke@0 661 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
duke@0 662 #ifdef _LP64
duke@0 663 Unimplemented();
duke@0 664 #else
duke@0 665 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
duke@0 666 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
duke@0 667 #endif
duke@0 668 return thepc;
duke@0 669 }
duke@0 670
twisti@727 671
coleenp@1604 672 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
duke@0 673 assert_not_delayed();
twisti@727 674 sethi(addrlit, d);
twisti@727 675 ld(d, addrlit.low10() + offset, d);
duke@0 676 }
duke@0 677
duke@0 678
coleenp@1604 679 inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) {
duke@0 680 assert_not_delayed();
twisti@727 681 sethi(addrlit, d);
twisti@727 682 ld_ptr(d, addrlit.low10() + offset, d);
duke@0 683 }
duke@0 684
duke@0 685
coleenp@1604 686 inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
duke@0 687 assert_not_delayed();
twisti@727 688 sethi(addrlit, temp);
twisti@727 689 st(s, temp, addrlit.low10() + offset);
duke@0 690 }
duke@0 691
duke@0 692
coleenp@1604 693 inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
duke@0 694 assert_not_delayed();
twisti@727 695 sethi(addrlit, temp);
twisti@727 696 st_ptr(s, temp, addrlit.low10() + offset);
duke@0 697 }
duke@0 698
duke@0 699
duke@0 700 // This code sequence is relocatable to any address, even on LP64.
coleenp@1604 701 inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) {
duke@0 702 assert_not_delayed();
duke@0 703 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
duke@0 704 // variable length instruction streams.
twisti@727 705 patchable_sethi(addrlit, temp);
twisti@727 706 jmpl(temp, addrlit.low10() + offset, d);
duke@0 707 }
duke@0 708
duke@0 709
coleenp@1604 710 inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) {
twisti@727 711 jumpl_to(addrlit, temp, G0, offset);
duke@0 712 }
duke@0 713
duke@0 714
twisti@727 715 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,
twisti@727 716 int ld_offset, int jmp_offset) {
jrose@710 717 assert_not_delayed();
twisti@727 718 //sethi(al); // sethi is caller responsibility for this one
jrose@710 719 ld_ptr(a, temp, ld_offset);
jrose@710 720 jmp(temp, jmp_offset);
jrose@710 721 }
jrose@710 722
jrose@710 723
twisti@727 724 inline void MacroAssembler::set_oop(jobject obj, Register d) {
twisti@727 725 set_oop(allocate_oop_address(obj), d);
duke@0 726 }
duke@0 727
duke@0 728
twisti@727 729 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
twisti@727 730 set_oop(constant_oop_address(obj), d);
duke@0 731 }
duke@0 732
duke@0 733
jcoomes@1467 734 inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) {
twisti@727 735 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
twisti@727 736 set(obj_addr, d);
duke@0 737 }
duke@0 738
duke@0 739
duke@0 740 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
duke@0 741 if (a.is_register())
duke@0 742 mov(a.as_register(), d);
duke@0 743 else
duke@0 744 ld (a.as_address(), d);
duke@0 745 }
duke@0 746
duke@0 747 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
duke@0 748 if (a.is_register())
duke@0 749 mov(s, a.as_register());
duke@0 750 else
duke@0 751 st_ptr (s, a.as_address()); // ABI says everything is right justified.
duke@0 752 }
duke@0 753
duke@0 754 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
duke@0 755 if (a.is_register())
duke@0 756 mov(s, a.as_register());
duke@0 757 else
duke@0 758 st_ptr (s, a.as_address());
duke@0 759 }
duke@0 760
duke@0 761
duke@0 762 #ifdef _LP64
duke@0 763 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
duke@0 764 if (a.is_float_register())
duke@0 765 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
duke@0 766 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
duke@0 767 else
duke@0 768 // Floats are stored in the high half of the stack entry
duke@0 769 // The low half is undefined per the ABI.
duke@0 770 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
duke@0 771 }
duke@0 772
duke@0 773 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
duke@0 774 if (a.is_float_register())
duke@0 775 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
duke@0 776 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
duke@0 777 else
duke@0 778 stf(FloatRegisterImpl::D, s, a.as_address());
duke@0 779 }
duke@0 780
duke@0 781 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
duke@0 782 if (a.is_register())
duke@0 783 mov(s, a.as_register());
duke@0 784 else
duke@0 785 stx(s, a.as_address());
duke@0 786 }
duke@0 787 #endif
duke@0 788
duke@0 789 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
duke@0 790 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
duke@0 791 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
duke@0 792 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
duke@0 793
duke@0 794 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
duke@0 795 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
duke@0 796 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
duke@0 797 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
duke@0 798
duke@0 799 // returns if membar generates anything, obviously this code should mirror
duke@0 800 // membar below.
duke@0 801 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
duke@0 802 if( !os::is_MP() ) return false; // Not needed on single CPU
duke@0 803 if( VM_Version::v9_instructions_work() ) {
duke@0 804 const Membar_mask_bits effective_mask =
duke@0 805 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
duke@0 806 return (effective_mask != 0);
duke@0 807 } else {
duke@0 808 return true;
duke@0 809 }
duke@0 810 }
duke@0 811
duke@0 812 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
duke@0 813 // Uniprocessors do not need memory barriers
duke@0 814 if (!os::is_MP()) return;
duke@0 815 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
duke@0 816 // 8.4.4.3, a.31 and a.50.
duke@0 817 if( VM_Version::v9_instructions_work() ) {
duke@0 818 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
duke@0 819 // of the mmask subfield of const7a that does anything that isn't done
duke@0 820 // implicitly is StoreLoad.
duke@0 821 const Membar_mask_bits effective_mask =
duke@0 822 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
duke@0 823 if ( effective_mask != 0 ) {
duke@0 824 Assembler::membar( effective_mask );
duke@0 825 }
duke@0 826 } else {
duke@0 827 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
duke@0 828 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
duke@0 829 // which guarantees that all stores behave as if an stbar were issued just after
duke@0 830 // each one of them. On these machines, stbar ought to be a nop. There doesn't
duke@0 831 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
duke@0 832 // it can't be specified by stbar, nor have I come up with a way to simulate it.
duke@0 833 //
duke@0 834 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
duke@0 835 // space. Put one here to be on the safe side.
duke@0 836 Assembler::ldstub(SP, 0, G0);
duke@0 837 }
duke@0 838 }
stefank@1885 839
stefank@1885 840 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP