annotate src/cpu/x86/vm/nativeInst_x86.cpp @ 196:d1605aabd0a1

6719955: Update copyright year Summary: Update copyright year for files that have been modified in 2008 Reviewed-by: ohair, tbell
author xdono
date Wed, 02 Jul 2008 12:55:16 -0700
parents 018d5b58dd4f
children dc7f315e41f7
rev   line source
duke@0 1 /*
xdono@196 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 # include "incls/_precompiled.incl"
duke@0 26 # include "incls/_nativeInst_x86.cpp.incl"
duke@0 27
duke@0 28 void NativeInstruction::wrote(int offset) {
duke@0 29 ICache::invalidate_word(addr_at(offset));
duke@0 30 }
duke@0 31
duke@0 32
duke@0 33 void NativeCall::verify() {
duke@0 34 // Make sure code pattern is actually a call imm32 instruction.
duke@0 35 int inst = ubyte_at(0);
duke@0 36 if (inst != instruction_code) {
duke@0 37 tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),
duke@0 38 inst);
duke@0 39 fatal("not a call disp32");
duke@0 40 }
duke@0 41 }
duke@0 42
duke@0 43 address NativeCall::destination() const {
duke@0 44 // Getting the destination of a call isn't safe because that call can
duke@0 45 // be getting patched while you're calling this. There's only special
duke@0 46 // places where this can be called but not automatically verifiable by
duke@0 47 // checking which locks are held. The solution is true atomic patching
duke@0 48 // on x86, nyi.
duke@0 49 return return_address() + displacement();
duke@0 50 }
duke@0 51
duke@0 52 void NativeCall::print() {
duke@0 53 tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
duke@0 54 instruction_address(), destination());
duke@0 55 }
duke@0 56
duke@0 57 // Inserts a native call instruction at a given pc
duke@0 58 void NativeCall::insert(address code_pos, address entry) {
duke@0 59 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@0 60 #ifdef AMD64
duke@0 61 guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
duke@0 62 #endif // AMD64
duke@0 63 *code_pos = instruction_code;
duke@0 64 *((int32_t *)(code_pos+1)) = (int32_t) disp;
duke@0 65 ICache::invalidate_range(code_pos, instruction_size);
duke@0 66 }
duke@0 67
duke@0 68 // MT-safe patching of a call instruction.
duke@0 69 // First patches first word of instruction to two jmp's that jmps to them
duke@0 70 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
duke@0 71 // the jmp's with the first 4 byte of the new instruction.
duke@0 72 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
duke@0 73 assert(Patching_lock->is_locked() ||
duke@0 74 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@0 75 assert (instr_addr != NULL, "illegal address for code patching");
duke@0 76
duke@0 77 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
duke@0 78 if (os::is_MP()) {
duke@0 79 guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
duke@0 80 }
duke@0 81
duke@0 82 // First patch dummy jmp in place
duke@0 83 unsigned char patch[4];
duke@0 84 assert(sizeof(patch)==sizeof(jint), "sanity check");
duke@0 85 patch[0] = 0xEB; // jmp rel8
duke@0 86 patch[1] = 0xFE; // jmp to self
duke@0 87 patch[2] = 0xEB;
duke@0 88 patch[3] = 0xFE;
duke@0 89
duke@0 90 // First patch dummy jmp in place
duke@0 91 *(jint*)instr_addr = *(jint *)patch;
duke@0 92
duke@0 93 // Invalidate. Opteron requires a flush after every write.
duke@0 94 n_call->wrote(0);
duke@0 95
duke@0 96 // Patch 4th byte
duke@0 97 instr_addr[4] = code_buffer[4];
duke@0 98
duke@0 99 n_call->wrote(4);
duke@0 100
duke@0 101 // Patch bytes 0-3
duke@0 102 *(jint*)instr_addr = *(jint *)code_buffer;
duke@0 103
duke@0 104 n_call->wrote(0);
duke@0 105
duke@0 106 #ifdef ASSERT
duke@0 107 // verify patching
duke@0 108 for ( int i = 0; i < instruction_size; i++) {
duke@0 109 address ptr = (address)((intptr_t)code_buffer + i);
duke@0 110 int a_byte = (*ptr) & 0xFF;
duke@0 111 assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
duke@0 112 }
duke@0 113 #endif
duke@0 114
duke@0 115 }
duke@0 116
duke@0 117
duke@0 118 // Similar to replace_mt_safe, but just changes the destination. The
duke@0 119 // important thing is that free-running threads are able to execute this
duke@0 120 // call instruction at all times. If the displacement field is aligned
duke@0 121 // we can simply rely on atomicity of 32-bit writes to make sure other threads
duke@0 122 // will see no intermediate states. Otherwise, the first two bytes of the
duke@0 123 // call are guaranteed to be aligned, and can be atomically patched to a
duke@0 124 // self-loop to guard the instruction while we change the other bytes.
duke@0 125
duke@0 126 // We cannot rely on locks here, since the free-running threads must run at
duke@0 127 // full speed.
duke@0 128 //
duke@0 129 // Used in the runtime linkage of calls; see class CompiledIC.
duke@0 130 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
duke@0 131 void NativeCall::set_destination_mt_safe(address dest) {
duke@0 132 debug_only(verify());
duke@0 133 // Make sure patching code is locked. No two threads can patch at the same
duke@0 134 // time but one may be executing this code.
duke@0 135 assert(Patching_lock->is_locked() ||
duke@0 136 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@0 137 // Both C1 and C2 should now be generating code which aligns the patched address
duke@0 138 // to be within a single cache line except that C1 does not do the alignment on
duke@0 139 // uniprocessor systems.
duke@0 140 bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
duke@0 141 ((uintptr_t)displacement_address() + 3) / cache_line_size;
duke@0 142
duke@0 143 guarantee(!os::is_MP() || is_aligned, "destination must be aligned");
duke@0 144
duke@0 145 if (is_aligned) {
duke@0 146 // Simple case: The destination lies within a single cache line.
duke@0 147 set_destination(dest);
duke@0 148 } else if ((uintptr_t)instruction_address() / cache_line_size ==
duke@0 149 ((uintptr_t)instruction_address()+1) / cache_line_size) {
duke@0 150 // Tricky case: The instruction prefix lies within a single cache line.
duke@0 151 intptr_t disp = dest - return_address();
duke@0 152 #ifdef AMD64
duke@0 153 guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
duke@0 154 #endif // AMD64
duke@0 155
duke@0 156 int call_opcode = instruction_address()[0];
duke@0 157
duke@0 158 // First patch dummy jump in place:
duke@0 159 {
duke@0 160 u_char patch_jump[2];
duke@0 161 patch_jump[0] = 0xEB; // jmp rel8
duke@0 162 patch_jump[1] = 0xFE; // jmp to self
duke@0 163
duke@0 164 assert(sizeof(patch_jump)==sizeof(short), "sanity check");
duke@0 165 *(short*)instruction_address() = *(short*)patch_jump;
duke@0 166 }
duke@0 167 // Invalidate. Opteron requires a flush after every write.
duke@0 168 wrote(0);
duke@0 169
duke@0 170 // (Note: We assume any reader which has already started to read
duke@0 171 // the unpatched call will completely read the whole unpatched call
duke@0 172 // without seeing the next writes we are about to make.)
duke@0 173
duke@0 174 // Next, patch the last three bytes:
duke@0 175 u_char patch_disp[5];
duke@0 176 patch_disp[0] = call_opcode;
duke@0 177 *(int32_t*)&patch_disp[1] = (int32_t)disp;
duke@0 178 assert(sizeof(patch_disp)==instruction_size, "sanity check");
duke@0 179 for (int i = sizeof(short); i < instruction_size; i++)
duke@0 180 instruction_address()[i] = patch_disp[i];
duke@0 181
duke@0 182 // Invalidate. Opteron requires a flush after every write.
duke@0 183 wrote(sizeof(short));
duke@0 184
duke@0 185 // (Note: We assume that any reader which reads the opcode we are
duke@0 186 // about to repatch will also read the writes we just made.)
duke@0 187
duke@0 188 // Finally, overwrite the jump:
duke@0 189 *(short*)instruction_address() = *(short*)patch_disp;
duke@0 190 // Invalidate. Opteron requires a flush after every write.
duke@0 191 wrote(0);
duke@0 192
duke@0 193 debug_only(verify());
duke@0 194 guarantee(destination() == dest, "patch succeeded");
duke@0 195 } else {
duke@0 196 // Impossible: One or the other must be atomically writable.
duke@0 197 ShouldNotReachHere();
duke@0 198 }
duke@0 199 }
duke@0 200
duke@0 201
duke@0 202 void NativeMovConstReg::verify() {
duke@0 203 #ifdef AMD64
duke@0 204 // make sure code pattern is actually a mov reg64, imm64 instruction
duke@0 205 if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
duke@0 206 (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
duke@0 207 print();
duke@0 208 fatal("not a REX.W[B] mov reg64, imm64");
duke@0 209 }
duke@0 210 #else
duke@0 211 // make sure code pattern is actually a mov reg, imm32 instruction
duke@0 212 u_char test_byte = *(u_char*)instruction_address();
duke@0 213 u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
duke@0 214 if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
duke@0 215 #endif // AMD64
duke@0 216 }
duke@0 217
duke@0 218
duke@0 219 void NativeMovConstReg::print() {
duke@0 220 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
duke@0 221 instruction_address(), data());
duke@0 222 }
duke@0 223
duke@0 224 //-------------------------------------------------------------------
duke@0 225
duke@0 226 #ifndef AMD64
duke@0 227
duke@0 228 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
duke@0 229 int inst_size = instruction_size;
duke@0 230
duke@0 231 // See if there's an instruction size prefix override.
duke@0 232 if ( *(address(this)) == instruction_operandsize_prefix &&
duke@0 233 *(address(this)+1) != instruction_code_xmm_code ) { // Not SSE instr
duke@0 234 inst_size += 1;
duke@0 235 }
duke@0 236 if ( *(address(this)) == instruction_extended_prefix ) inst_size += 1;
duke@0 237
duke@0 238 for (int i = 0; i < instruction_size; i++) {
duke@0 239 *(new_instruction_address + i) = *(address(this) + i);
duke@0 240 }
duke@0 241 }
duke@0 242
duke@0 243 void NativeMovRegMem::verify() {
duke@0 244 // make sure code pattern is actually a mov [reg+offset], reg instruction
duke@0 245 u_char test_byte = *(u_char*)instruction_address();
duke@0 246 if ( ! ( (test_byte == instruction_code_reg2memb)
duke@0 247 || (test_byte == instruction_code_mem2regb)
duke@0 248 || (test_byte == instruction_code_mem2regl)
duke@0 249 || (test_byte == instruction_code_reg2meml)
duke@0 250 || (test_byte == instruction_code_mem2reg_movzxb )
duke@0 251 || (test_byte == instruction_code_mem2reg_movzxw )
duke@0 252 || (test_byte == instruction_code_mem2reg_movsxb )
duke@0 253 || (test_byte == instruction_code_mem2reg_movsxw )
duke@0 254 || (test_byte == instruction_code_float_s)
duke@0 255 || (test_byte == instruction_code_float_d)
duke@0 256 || (test_byte == instruction_code_long_volatile) ) )
duke@0 257 {
duke@0 258 u_char byte1 = ((u_char*)instruction_address())[1];
duke@0 259 u_char byte2 = ((u_char*)instruction_address())[2];
duke@0 260 if ((test_byte != instruction_code_xmm_ss_prefix &&
duke@0 261 test_byte != instruction_code_xmm_sd_prefix &&
duke@0 262 test_byte != instruction_operandsize_prefix) ||
duke@0 263 byte1 != instruction_code_xmm_code ||
duke@0 264 (byte2 != instruction_code_xmm_load &&
duke@0 265 byte2 != instruction_code_xmm_lpd &&
duke@0 266 byte2 != instruction_code_xmm_store)) {
duke@0 267 fatal ("not a mov [reg+offs], reg instruction");
duke@0 268 }
duke@0 269 }
duke@0 270 }
duke@0 271
duke@0 272
duke@0 273 void NativeMovRegMem::print() {
duke@0 274 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
duke@0 275 }
duke@0 276
duke@0 277 //-------------------------------------------------------------------
duke@0 278
duke@0 279 void NativeLoadAddress::verify() {
duke@0 280 // make sure code pattern is actually a mov [reg+offset], reg instruction
duke@0 281 u_char test_byte = *(u_char*)instruction_address();
duke@0 282 if ( ! (test_byte == instruction_code) ) {
duke@0 283 fatal ("not a lea reg, [reg+offs] instruction");
duke@0 284 }
duke@0 285 }
duke@0 286
duke@0 287
duke@0 288 void NativeLoadAddress::print() {
duke@0 289 tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
duke@0 290 }
duke@0 291
duke@0 292 #endif // !AMD64
duke@0 293
duke@0 294 //--------------------------------------------------------------------------------
duke@0 295
duke@0 296 void NativeJump::verify() {
duke@0 297 if (*(u_char*)instruction_address() != instruction_code) {
duke@0 298 fatal("not a jump instruction");
duke@0 299 }
duke@0 300 }
duke@0 301
duke@0 302
duke@0 303 void NativeJump::insert(address code_pos, address entry) {
duke@0 304 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@0 305 #ifdef AMD64
duke@0 306 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@0 307 #endif // AMD64
duke@0 308
duke@0 309 *code_pos = instruction_code;
duke@0 310 *((int32_t*)(code_pos + 1)) = (int32_t)disp;
duke@0 311
duke@0 312 ICache::invalidate_range(code_pos, instruction_size);
duke@0 313 }
duke@0 314
duke@0 315 void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
duke@0 316 // Patching to not_entrant can happen while activations of the method are
duke@0 317 // in use. The patching in that instance must happen only when certain
duke@0 318 // alignment restrictions are true. These guarantees check those
duke@0 319 // conditions.
duke@0 320 #ifdef AMD64
duke@0 321 const int linesize = 64;
duke@0 322 #else
duke@0 323 const int linesize = 32;
duke@0 324 #endif // AMD64
duke@0 325
duke@0 326 // Must be wordSize aligned
duke@0 327 guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
duke@0 328 "illegal address for code patching 2");
duke@0 329 // First 5 bytes must be within the same cache line - 4827828
duke@0 330 guarantee((uintptr_t) verified_entry / linesize ==
duke@0 331 ((uintptr_t) verified_entry + 4) / linesize,
duke@0 332 "illegal address for code patching 3");
duke@0 333 }
duke@0 334
duke@0 335
duke@0 336 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
duke@0 337 // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
duke@0 338 // First patches the first word atomically to be a jump to itself.
duke@0 339 // Then patches the last byte and then atomically patches the first word (4-bytes),
duke@0 340 // thus inserting the desired jump
duke@0 341 // This code is mt-safe with the following conditions: entry point is 4 byte aligned,
duke@0 342 // entry point is in same cache line as unverified entry point, and the instruction being
duke@0 343 // patched is >= 5 byte (size of patch).
duke@0 344 //
duke@0 345 // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
duke@0 346 // In C1 the restriction is enforced by CodeEmitter::method_entry
duke@0 347 //
duke@0 348 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
duke@0 349 // complete jump instruction (to be inserted) is in code_buffer;
duke@0 350 unsigned char code_buffer[5];
duke@0 351 code_buffer[0] = instruction_code;
duke@0 352 intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
duke@0 353 #ifdef AMD64
duke@0 354 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@0 355 #endif // AMD64
duke@0 356 *(int32_t*)(code_buffer + 1) = (int32_t)disp;
duke@0 357
duke@0 358 check_verified_entry_alignment(entry, verified_entry);
duke@0 359
duke@0 360 // Can't call nativeJump_at() because it's asserts jump exists
duke@0 361 NativeJump* n_jump = (NativeJump*) verified_entry;
duke@0 362
duke@0 363 //First patch dummy jmp in place
duke@0 364
duke@0 365 unsigned char patch[4];
duke@0 366 assert(sizeof(patch)==sizeof(int32_t), "sanity check");
duke@0 367 patch[0] = 0xEB; // jmp rel8
duke@0 368 patch[1] = 0xFE; // jmp to self
duke@0 369 patch[2] = 0xEB;
duke@0 370 patch[3] = 0xFE;
duke@0 371
duke@0 372 // First patch dummy jmp in place
duke@0 373 *(int32_t*)verified_entry = *(int32_t *)patch;
duke@0 374
duke@0 375 n_jump->wrote(0);
duke@0 376
duke@0 377 // Patch 5th byte (from jump instruction)
duke@0 378 verified_entry[4] = code_buffer[4];
duke@0 379
duke@0 380 n_jump->wrote(4);
duke@0 381
duke@0 382 // Patch bytes 0-3 (from jump instruction)
duke@0 383 *(int32_t*)verified_entry = *(int32_t *)code_buffer;
duke@0 384 // Invalidate. Opteron requires a flush after every write.
duke@0 385 n_jump->wrote(0);
duke@0 386
duke@0 387 }
duke@0 388
duke@0 389 void NativePopReg::insert(address code_pos, Register reg) {
duke@0 390 assert(reg->encoding() < 8, "no space for REX");
duke@0 391 assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
duke@0 392 *code_pos = (u_char)(instruction_code | reg->encoding());
duke@0 393 ICache::invalidate_range(code_pos, instruction_size);
duke@0 394 }
duke@0 395
duke@0 396
duke@0 397 void NativeIllegalInstruction::insert(address code_pos) {
duke@0 398 assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
duke@0 399 *(short *)code_pos = instruction_code;
duke@0 400 ICache::invalidate_range(code_pos, instruction_size);
duke@0 401 }
duke@0 402
duke@0 403 void NativeGeneralJump::verify() {
duke@0 404 assert(((NativeInstruction *)this)->is_jump() ||
duke@0 405 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
duke@0 406 }
duke@0 407
duke@0 408
duke@0 409 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
duke@0 410 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
duke@0 411 #ifdef AMD64
duke@0 412 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
duke@0 413 #endif // AMD64
duke@0 414
duke@0 415 *code_pos = unconditional_long_jump;
duke@0 416 *((int32_t *)(code_pos+1)) = (int32_t) disp;
duke@0 417 ICache::invalidate_range(code_pos, instruction_size);
duke@0 418 }
duke@0 419
duke@0 420
duke@0 421 // MT-safe patching of a long jump instruction.
duke@0 422 // First patches first word of instruction to two jmp's that jmps to them
duke@0 423 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
duke@0 424 // the jmp's with the first 4 byte of the new instruction.
duke@0 425 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
duke@0 426 assert (instr_addr != NULL, "illegal address for code patching (4)");
duke@0 427 NativeGeneralJump* n_jump = nativeGeneralJump_at (instr_addr); // checking that it is a jump
duke@0 428
duke@0 429 // Temporary code
duke@0 430 unsigned char patch[4];
duke@0 431 assert(sizeof(patch)==sizeof(int32_t), "sanity check");
duke@0 432 patch[0] = 0xEB; // jmp rel8
duke@0 433 patch[1] = 0xFE; // jmp to self
duke@0 434 patch[2] = 0xEB;
duke@0 435 patch[3] = 0xFE;
duke@0 436
duke@0 437 // First patch dummy jmp in place
duke@0 438 *(int32_t*)instr_addr = *(int32_t *)patch;
duke@0 439 n_jump->wrote(0);
duke@0 440
duke@0 441 // Patch 4th byte
duke@0 442 instr_addr[4] = code_buffer[4];
duke@0 443
duke@0 444 n_jump->wrote(4);
duke@0 445
duke@0 446 // Patch bytes 0-3
duke@0 447 *(jint*)instr_addr = *(jint *)code_buffer;
duke@0 448
duke@0 449 n_jump->wrote(0);
duke@0 450
duke@0 451 #ifdef ASSERT
duke@0 452 // verify patching
duke@0 453 for ( int i = 0; i < instruction_size; i++) {
duke@0 454 address ptr = (address)((intptr_t)code_buffer + i);
duke@0 455 int a_byte = (*ptr) & 0xFF;
duke@0 456 assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
duke@0 457 }
duke@0 458 #endif
duke@0 459
duke@0 460 }
duke@0 461
duke@0 462
duke@0 463
duke@0 464 address NativeGeneralJump::jump_destination() const {
duke@0 465 int op_code = ubyte_at(0);
duke@0 466 bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
duke@0 467 int offset = (op_code == 0x0F) ? 2 : 1;
duke@0 468 int length = offset + ((is_rel32off) ? 4 : 1);
duke@0 469
duke@0 470 if (is_rel32off)
duke@0 471 return addr_at(0) + length + int_at(offset);
duke@0 472 else
duke@0 473 return addr_at(0) + length + sbyte_at(offset);
duke@0 474 }
kamg@116 475
kamg@116 476 bool NativeInstruction::is_dtrace_trap() {
kamg@116 477 return (*(int32_t*)this & 0xff) == 0xcc;
kamg@116 478 }