annotate src/cpu/sparc/vm/nativeInst_sparc.cpp @ 196:d1605aabd0a1

6719955: Update copyright year Summary: Update copyright year for files that have been modified in 2008 Reviewed-by: ohair, tbell
author xdono
date Wed, 02 Jul 2008 12:55:16 -0700
parents 018d5b58dd4f
children 6b2273dd6fa9
rev   line source
duke@0 1 /*
xdono@196 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
duke@0 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
duke@0 20 * CA 95054 USA or visit www.sun.com if you need additional information or
duke@0 21 * have any questions.
duke@0 22 *
duke@0 23 */
duke@0 24
duke@0 25 # include "incls/_precompiled.incl"
duke@0 26 # include "incls/_nativeInst_sparc.cpp.incl"
duke@0 27
duke@0 28
kamg@116 29 bool NativeInstruction::is_dtrace_trap() {
kamg@116 30 return !is_nop();
kamg@116 31 }
kamg@116 32
duke@0 33 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) {
duke@0 34 ResourceMark rm;
duke@0 35 CodeBuffer buf(instaddr, 10 * BytesPerInstWord );
duke@0 36 MacroAssembler* _masm = new MacroAssembler(&buf);
duke@0 37 Register destreg;
duke@0 38
duke@0 39 destreg = inv_rd(*(unsigned int *)instaddr);
duke@0 40 // Generate a the new sequence
duke@0 41 Address dest( destreg, (address)x );
duke@0 42 _masm->sethi( dest, true );
duke@0 43 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord);
duke@0 44 }
duke@0 45
duke@0 46 void NativeInstruction::verify() {
duke@0 47 // make sure code pattern is actually an instruction address
duke@0 48 address addr = addr_at(0);
duke@0 49 if (addr == 0 || ((intptr_t)addr & 3) != 0) {
duke@0 50 fatal("not an instruction address");
duke@0 51 }
duke@0 52 }
duke@0 53
duke@0 54 void NativeInstruction::print() {
duke@0 55 tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0));
duke@0 56 }
duke@0 57
duke@0 58 void NativeInstruction::set_long_at(int offset, int i) {
duke@0 59 address addr = addr_at(offset);
duke@0 60 *(int*)addr = i;
duke@0 61 ICache::invalidate_word(addr);
duke@0 62 }
duke@0 63
duke@0 64 void NativeInstruction::set_jlong_at(int offset, jlong i) {
duke@0 65 address addr = addr_at(offset);
duke@0 66 *(jlong*)addr = i;
duke@0 67 // Don't need to invalidate 2 words here, because
duke@0 68 // the flush instruction operates on doublewords.
duke@0 69 ICache::invalidate_word(addr);
duke@0 70 }
duke@0 71
duke@0 72 void NativeInstruction::set_addr_at(int offset, address x) {
duke@0 73 address addr = addr_at(offset);
duke@0 74 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment");
duke@0 75 *(uintptr_t*)addr = (uintptr_t)x;
duke@0 76 // Don't need to invalidate 2 words here in the 64-bit case,
duke@0 77 // because the flush instruction operates on doublewords.
duke@0 78 ICache::invalidate_word(addr);
duke@0 79 // The Intel code has this assertion for NativeCall::set_destination,
duke@0 80 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset,
duke@0 81 // NativeJump::set_jump_destination, and NativePushImm32::set_data
duke@0 82 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction")
duke@0 83 }
duke@0 84
duke@0 85 bool NativeInstruction::is_zero_test(Register &reg) {
duke@0 86 int x = long_at(0);
duke@0 87 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3);
duke@0 88 if (is_op3(x, temp, Assembler::arith_op) &&
duke@0 89 inv_immed(x) && inv_rd(x) == G0) {
duke@0 90 if (inv_rs1(x) == G0) {
duke@0 91 reg = inv_rs2(x);
duke@0 92 return true;
duke@0 93 } else if (inv_rs2(x) == G0) {
duke@0 94 reg = inv_rs1(x);
duke@0 95 return true;
duke@0 96 }
duke@0 97 }
duke@0 98 return false;
duke@0 99 }
duke@0 100
duke@0 101 bool NativeInstruction::is_load_store_with_small_offset(Register reg) {
duke@0 102 int x = long_at(0);
duke@0 103 if (is_op(x, Assembler::ldst_op) &&
duke@0 104 inv_rs1(x) == reg && inv_immed(x)) {
duke@0 105 return true;
duke@0 106 }
duke@0 107 return false;
duke@0 108 }
duke@0 109
duke@0 110 void NativeCall::verify() {
duke@0 111 NativeInstruction::verify();
duke@0 112 // make sure code pattern is actually a call instruction
duke@0 113 if (!is_op(long_at(0), Assembler::call_op)) {
duke@0 114 fatal("not a call");
duke@0 115 }
duke@0 116 }
duke@0 117
duke@0 118 void NativeCall::print() {
duke@0 119 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
duke@0 120 }
duke@0 121
duke@0 122
duke@0 123 // MT-safe patching of a call instruction (and following word).
duke@0 124 // First patches the second word, and then atomicly replaces
duke@0 125 // the first word with the first new instruction word.
duke@0 126 // Other processors might briefly see the old first word
duke@0 127 // followed by the new second word. This is OK if the old
duke@0 128 // second word is harmless, and the new second word may be
duke@0 129 // harmlessly executed in the delay slot of the call.
duke@0 130 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
duke@0 131 assert(Patching_lock->is_locked() ||
duke@0 132 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@0 133 assert (instr_addr != NULL, "illegal address for code patching");
duke@0 134 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
duke@0 135 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
duke@0 136 int i0 = ((int*)code_buffer)[0];
duke@0 137 int i1 = ((int*)code_buffer)[1];
duke@0 138 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
duke@0 139 assert(inv_op(*contention_addr) == Assembler::arith_op ||
duke@0 140 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
duke@0 141 "must not interfere with original call");
duke@0 142 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
duke@0 143 n_call->set_long_at(1*BytesPerInstWord, i1);
duke@0 144 n_call->set_long_at(0*BytesPerInstWord, i0);
duke@0 145 // NOTE: It is possible that another thread T will execute
duke@0 146 // only the second patched word.
duke@0 147 // In other words, since the original instruction is this
duke@0 148 // call patching_stub; nop (NativeCall)
duke@0 149 // and the new sequence from the buffer is this:
duke@0 150 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
duke@0 151 // what T will execute is this:
duke@0 152 // call patching_stub; add %r, %lo(K), %r
duke@0 153 // thereby putting garbage into %r before calling the patching stub.
duke@0 154 // This is OK, because the patching stub ignores the value of %r.
duke@0 155
duke@0 156 // Make sure the first-patched instruction, which may co-exist
duke@0 157 // briefly with the call, will do something harmless.
duke@0 158 assert(inv_op(*contention_addr) == Assembler::arith_op ||
duke@0 159 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
duke@0 160 "must not interfere with original call");
duke@0 161 }
duke@0 162
duke@0 163 // Similar to replace_mt_safe, but just changes the destination. The
duke@0 164 // important thing is that free-running threads are able to execute this
duke@0 165 // call instruction at all times. Thus, the displacement field must be
duke@0 166 // instruction-word-aligned. This is always true on SPARC.
duke@0 167 //
duke@0 168 // Used in the runtime linkage of calls; see class CompiledIC.
duke@0 169 void NativeCall::set_destination_mt_safe(address dest) {
duke@0 170 assert(Patching_lock->is_locked() ||
duke@0 171 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@0 172 // set_destination uses set_long_at which does the ICache::invalidate
duke@0 173 set_destination(dest);
duke@0 174 }
duke@0 175
duke@0 176 // Code for unit testing implementation of NativeCall class
duke@0 177 void NativeCall::test() {
duke@0 178 #ifdef ASSERT
duke@0 179 ResourceMark rm;
duke@0 180 CodeBuffer cb("test", 100, 100);
duke@0 181 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 182 NativeCall *nc;
duke@0 183 uint idx;
duke@0 184 int offsets[] = {
duke@0 185 0x0,
duke@0 186 0xfffffff0,
duke@0 187 0x7ffffff0,
duke@0 188 0x80000000,
duke@0 189 0x20,
duke@0 190 0x4000,
duke@0 191 };
duke@0 192
duke@0 193 VM_Version::allow_all();
duke@0 194
duke@0 195 a->call( a->pc(), relocInfo::none );
duke@0 196 a->delayed()->nop();
duke@0 197 nc = nativeCall_at( cb.code_begin() );
duke@0 198 nc->print();
duke@0 199
duke@0 200 nc = nativeCall_overwriting_at( nc->next_instruction_address() );
duke@0 201 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
duke@0 202 nc->set_destination( cb.code_begin() + offsets[idx] );
duke@0 203 assert(nc->destination() == (cb.code_begin() + offsets[idx]), "check unit test");
duke@0 204 nc->print();
duke@0 205 }
duke@0 206
duke@0 207 nc = nativeCall_before( cb.code_begin() + 8 );
duke@0 208 nc->print();
duke@0 209
duke@0 210 VM_Version::revert();
duke@0 211 #endif
duke@0 212 }
duke@0 213 // End code for unit testing implementation of NativeCall class
duke@0 214
duke@0 215 //-------------------------------------------------------------------
duke@0 216
duke@0 217 #ifdef _LP64
duke@0 218
duke@0 219 void NativeFarCall::set_destination(address dest) {
duke@0 220 // Address materialized in the instruction stream, so nothing to do.
duke@0 221 return;
duke@0 222 #if 0 // What we'd do if we really did want to change the destination
duke@0 223 if (destination() == dest) {
duke@0 224 return;
duke@0 225 }
duke@0 226 ResourceMark rm;
duke@0 227 CodeBuffer buf(addr_at(0), instruction_size + 1);
duke@0 228 MacroAssembler* _masm = new MacroAssembler(&buf);
duke@0 229 // Generate the new sequence
duke@0 230 Address(O7, dest);
duke@0 231 _masm->jumpl_to(dest, O7);
duke@0 232 ICache::invalidate_range(addr_at(0), instruction_size );
duke@0 233 #endif
duke@0 234 }
duke@0 235
duke@0 236 void NativeFarCall::verify() {
duke@0 237 // make sure code pattern is actually a jumpl_to instruction
duke@0 238 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to");
duke@0 239 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
duke@0 240 nativeJump_at(addr_at(0))->verify();
duke@0 241 }
duke@0 242
duke@0 243 bool NativeFarCall::is_call_at(address instr) {
duke@0 244 return nativeInstruction_at(instr)->is_sethi();
duke@0 245 }
duke@0 246
duke@0 247 void NativeFarCall::print() {
duke@0 248 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
duke@0 249 }
duke@0 250
duke@0 251 bool NativeFarCall::destination_is_compiled_verified_entry_point() {
duke@0 252 nmethod* callee = CodeCache::find_nmethod(destination());
duke@0 253 if (callee == NULL) {
duke@0 254 return false;
duke@0 255 } else {
duke@0 256 return destination() == callee->verified_entry_point();
duke@0 257 }
duke@0 258 }
duke@0 259
duke@0 260 // MT-safe patching of a far call.
duke@0 261 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) {
duke@0 262 Unimplemented();
duke@0 263 }
duke@0 264
duke@0 265 // Code for unit testing implementation of NativeFarCall class
duke@0 266 void NativeFarCall::test() {
duke@0 267 Unimplemented();
duke@0 268 }
duke@0 269 // End code for unit testing implementation of NativeFarCall class
duke@0 270
duke@0 271 #endif // _LP64
duke@0 272
duke@0 273 //-------------------------------------------------------------------
duke@0 274
duke@0 275
duke@0 276 void NativeMovConstReg::verify() {
duke@0 277 NativeInstruction::verify();
duke@0 278 // make sure code pattern is actually a "set_oop" synthetic instruction
duke@0 279 // see MacroAssembler::set_oop()
duke@0 280 int i0 = long_at(sethi_offset);
duke@0 281 int i1 = long_at(add_offset);
duke@0 282
duke@0 283 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg"
duke@0 284 Register rd = inv_rd(i0);
duke@0 285 #ifndef _LP64
duke@0 286 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
duke@0 287 is_op3(i1, Assembler::add_op3, Assembler::arith_op) &&
duke@0 288 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
duke@0 289 rd == inv_rs1(i1) && rd == inv_rd(i1))) {
duke@0 290 fatal("not a set_oop");
duke@0 291 }
duke@0 292 #else
duke@0 293 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
duke@0 294 fatal("not a set_oop");
duke@0 295 }
duke@0 296 #endif
duke@0 297 }
duke@0 298
duke@0 299
duke@0 300 void NativeMovConstReg::print() {
duke@0 301 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
duke@0 302 }
duke@0 303
duke@0 304
duke@0 305 #ifdef _LP64
duke@0 306 intptr_t NativeMovConstReg::data() const {
duke@0 307 return data64(addr_at(sethi_offset), long_at(add_offset));
duke@0 308 }
duke@0 309 #else
duke@0 310 intptr_t NativeMovConstReg::data() const {
duke@0 311 return data32(long_at(sethi_offset), long_at(add_offset));
duke@0 312 }
duke@0 313 #endif
duke@0 314
duke@0 315
duke@0 316 void NativeMovConstReg::set_data(intptr_t x) {
duke@0 317 #ifdef _LP64
duke@0 318 set_data64_sethi(addr_at(sethi_offset), x);
duke@0 319 #else
duke@0 320 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x));
duke@0 321 #endif
duke@0 322 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x));
duke@0 323
duke@0 324 // also store the value into an oop_Relocation cell, if any
duke@0 325 CodeBlob* nm = CodeCache::find_blob(instruction_address());
duke@0 326 if (nm != NULL) {
duke@0 327 RelocIterator iter(nm, instruction_address(), next_instruction_address());
duke@0 328 oop* oop_addr = NULL;
duke@0 329 while (iter.next()) {
duke@0 330 if (iter.type() == relocInfo::oop_type) {
duke@0 331 oop_Relocation *r = iter.oop_reloc();
duke@0 332 if (oop_addr == NULL) {
duke@0 333 oop_addr = r->oop_addr();
duke@0 334 *oop_addr = (oop)x;
duke@0 335 } else {
duke@0 336 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
duke@0 337 }
duke@0 338 }
duke@0 339 }
duke@0 340 }
duke@0 341 }
duke@0 342
duke@0 343
duke@0 344 // Code for unit testing implementation of NativeMovConstReg class
duke@0 345 void NativeMovConstReg::test() {
duke@0 346 #ifdef ASSERT
duke@0 347 ResourceMark rm;
duke@0 348 CodeBuffer cb("test", 100, 100);
duke@0 349 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 350 NativeMovConstReg* nm;
duke@0 351 uint idx;
duke@0 352 int offsets[] = {
duke@0 353 0x0,
duke@0 354 0x7fffffff,
duke@0 355 0x80000000,
duke@0 356 0xffffffff,
duke@0 357 0x20,
duke@0 358 4096,
duke@0 359 4097,
duke@0 360 };
duke@0 361
duke@0 362 VM_Version::allow_all();
duke@0 363
duke@0 364 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
duke@0 365 a->add(I3, low10(0xaaaabbbb), I3);
duke@0 366 a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
duke@0 367 a->add(O2, low10(0xccccdddd), O2);
duke@0 368
duke@0 369 nm = nativeMovConstReg_at( cb.code_begin() );
duke@0 370 nm->print();
duke@0 371
duke@0 372 nm = nativeMovConstReg_at( nm->next_instruction_address() );
duke@0 373 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
duke@0 374 nm->set_data( offsets[idx] );
duke@0 375 assert(nm->data() == offsets[idx], "check unit test");
duke@0 376 }
duke@0 377 nm->print();
duke@0 378
duke@0 379 VM_Version::revert();
duke@0 380 #endif
duke@0 381 }
duke@0 382 // End code for unit testing implementation of NativeMovConstReg class
duke@0 383
duke@0 384 //-------------------------------------------------------------------
duke@0 385
duke@0 386 void NativeMovConstRegPatching::verify() {
duke@0 387 NativeInstruction::verify();
duke@0 388 // Make sure code pattern is sethi/nop/add.
duke@0 389 int i0 = long_at(sethi_offset);
duke@0 390 int i1 = long_at(nop_offset);
duke@0 391 int i2 = long_at(add_offset);
duke@0 392 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
duke@0 393
duke@0 394 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg"
duke@0 395 // The casual reader should note that on Sparc a nop is a special case if sethi
duke@0 396 // in which the destination register is %g0.
duke@0 397 Register rd0 = inv_rd(i0);
duke@0 398 Register rd1 = inv_rd(i1);
duke@0 399 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 &&
duke@0 400 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi
duke@0 401 is_op3(i2, Assembler::add_op3, Assembler::arith_op) &&
duke@0 402 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) &&
duke@0 403 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) {
duke@0 404 fatal("not a set_oop");
duke@0 405 }
duke@0 406 }
duke@0 407
duke@0 408
duke@0 409 void NativeMovConstRegPatching::print() {
duke@0 410 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
duke@0 411 }
duke@0 412
duke@0 413
duke@0 414 int NativeMovConstRegPatching::data() const {
duke@0 415 #ifdef _LP64
duke@0 416 return data64(addr_at(sethi_offset), long_at(add_offset));
duke@0 417 #else
duke@0 418 return data32(long_at(sethi_offset), long_at(add_offset));
duke@0 419 #endif
duke@0 420 }
duke@0 421
duke@0 422
duke@0 423 void NativeMovConstRegPatching::set_data(int x) {
duke@0 424 #ifdef _LP64
duke@0 425 set_data64_sethi(addr_at(sethi_offset), x);
duke@0 426 #else
duke@0 427 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x));
duke@0 428 #endif
duke@0 429 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x));
duke@0 430
duke@0 431 // also store the value into an oop_Relocation cell, if any
duke@0 432 CodeBlob* nm = CodeCache::find_blob(instruction_address());
duke@0 433 if (nm != NULL) {
duke@0 434 RelocIterator iter(nm, instruction_address(), next_instruction_address());
duke@0 435 oop* oop_addr = NULL;
duke@0 436 while (iter.next()) {
duke@0 437 if (iter.type() == relocInfo::oop_type) {
duke@0 438 oop_Relocation *r = iter.oop_reloc();
duke@0 439 if (oop_addr == NULL) {
duke@0 440 oop_addr = r->oop_addr();
duke@0 441 *oop_addr = (oop)x;
duke@0 442 } else {
duke@0 443 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
duke@0 444 }
duke@0 445 }
duke@0 446 }
duke@0 447 }
duke@0 448 }
duke@0 449
duke@0 450
duke@0 451 // Code for unit testing implementation of NativeMovConstRegPatching class
duke@0 452 void NativeMovConstRegPatching::test() {
duke@0 453 #ifdef ASSERT
duke@0 454 ResourceMark rm;
duke@0 455 CodeBuffer cb("test", 100, 100);
duke@0 456 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 457 NativeMovConstRegPatching* nm;
duke@0 458 uint idx;
duke@0 459 int offsets[] = {
duke@0 460 0x0,
duke@0 461 0x7fffffff,
duke@0 462 0x80000000,
duke@0 463 0xffffffff,
duke@0 464 0x20,
duke@0 465 4096,
duke@0 466 4097,
duke@0 467 };
duke@0 468
duke@0 469 VM_Version::allow_all();
duke@0 470
duke@0 471 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
duke@0 472 a->nop();
duke@0 473 a->add(I3, low10(0xaaaabbbb), I3);
duke@0 474 a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
duke@0 475 a->nop();
duke@0 476 a->add(O2, low10(0xccccdddd), O2);
duke@0 477
duke@0 478 nm = nativeMovConstRegPatching_at( cb.code_begin() );
duke@0 479 nm->print();
duke@0 480
duke@0 481 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() );
duke@0 482 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
duke@0 483 nm->set_data( offsets[idx] );
duke@0 484 assert(nm->data() == offsets[idx], "check unit test");
duke@0 485 }
duke@0 486 nm->print();
duke@0 487
duke@0 488 VM_Version::revert();
duke@0 489 #endif // ASSERT
duke@0 490 }
duke@0 491 // End code for unit testing implementation of NativeMovConstRegPatching class
duke@0 492
duke@0 493
duke@0 494 //-------------------------------------------------------------------
duke@0 495
duke@0 496
duke@0 497 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
duke@0 498 Untested("copy_instruction_to");
duke@0 499 int instruction_size = next_instruction_address() - instruction_address();
duke@0 500 for (int i = 0; i < instruction_size; i += BytesPerInstWord) {
duke@0 501 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i);
duke@0 502 }
duke@0 503 }
duke@0 504
duke@0 505
duke@0 506 void NativeMovRegMem::verify() {
duke@0 507 NativeInstruction::verify();
duke@0 508 // make sure code pattern is actually a "ld" or "st" of some sort.
duke@0 509 int i0 = long_at(0);
duke@0 510 int op3 = inv_op3(i0);
duke@0 511
duke@0 512 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok");
duke@0 513
duke@0 514 if (!(is_op(i0, Assembler::ldst_op) &&
duke@0 515 inv_immed(i0) &&
duke@0 516 0 != (op3 < op3_ldst_int_limit
duke@0 517 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
duke@0 518 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))))
duke@0 519 {
duke@0 520 int i1 = long_at(ldst_offset);
duke@0 521 Register rd = inv_rd(i0);
duke@0 522
duke@0 523 op3 = inv_op3(i1);
duke@0 524 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
duke@0 525 0 != (op3 < op3_ldst_int_limit
duke@0 526 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
duke@0 527 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
duke@0 528 fatal("not a ld* or st* op");
duke@0 529 }
duke@0 530 }
duke@0 531 }
duke@0 532
duke@0 533
duke@0 534 void NativeMovRegMem::print() {
duke@0 535 if (is_immediate()) {
duke@0 536 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
duke@0 537 } else {
duke@0 538 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
duke@0 539 }
duke@0 540 }
duke@0 541
duke@0 542
duke@0 543 // Code for unit testing implementation of NativeMovRegMem class
duke@0 544 void NativeMovRegMem::test() {
duke@0 545 #ifdef ASSERT
duke@0 546 ResourceMark rm;
duke@0 547 CodeBuffer cb("test", 1000, 1000);
duke@0 548 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 549 NativeMovRegMem* nm;
duke@0 550 uint idx = 0;
duke@0 551 uint idx1;
duke@0 552 int offsets[] = {
duke@0 553 0x0,
duke@0 554 0xffffffff,
duke@0 555 0x7fffffff,
duke@0 556 0x80000000,
duke@0 557 4096,
duke@0 558 4097,
duke@0 559 0x20,
duke@0 560 0x4000,
duke@0 561 };
duke@0 562
duke@0 563 VM_Version::allow_all();
duke@0 564
duke@0 565 a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
duke@0 566 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 567 a->ldsw( G5, I3, G4 ); idx++;
duke@0 568 a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
duke@0 569 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 570 a->ldsb( G5, I3, G4 ); idx++;
duke@0 571 a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
duke@0 572 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 573 a->ldsh( G5, I3, G4 ); idx++;
duke@0 574 a->lduw( G5, low10(0xffffffff), G4 ); idx++;
duke@0 575 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 576 a->lduw( G5, I3, G4 ); idx++;
duke@0 577 a->ldub( G5, low10(0xffffffff), G4 ); idx++;
duke@0 578 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 579 a->ldub( G5, I3, G4 ); idx++;
duke@0 580 a->lduh( G5, low10(0xffffffff), G4 ); idx++;
duke@0 581 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 582 a->lduh( G5, I3, G4 ); idx++;
duke@0 583 a->ldx( G5, low10(0xffffffff), G4 ); idx++;
duke@0 584 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 585 a->ldx( G5, I3, G4 ); idx++;
duke@0 586 a->ldd( G5, low10(0xffffffff), G4 ); idx++;
duke@0 587 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 588 a->ldd( G5, I3, G4 ); idx++;
duke@0 589 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
duke@0 590 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 591 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
duke@0 592
duke@0 593 a->stw( G5, G4, low10(0xffffffff) ); idx++;
duke@0 594 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 595 a->stw( G5, G4, I3 ); idx++;
duke@0 596 a->stb( G5, G4, low10(0xffffffff) ); idx++;
duke@0 597 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 598 a->stb( G5, G4, I3 ); idx++;
duke@0 599 a->sth( G5, G4, low10(0xffffffff) ); idx++;
duke@0 600 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 601 a->sth( G5, G4, I3 ); idx++;
duke@0 602 a->stx( G5, G4, low10(0xffffffff) ); idx++;
duke@0 603 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 604 a->stx( G5, G4, I3 ); idx++;
duke@0 605 a->std( G5, G4, low10(0xffffffff) ); idx++;
duke@0 606 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 607 a->std( G5, G4, I3 ); idx++;
duke@0 608 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
duke@0 609 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 610 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
duke@0 611
duke@0 612 nm = nativeMovRegMem_at( cb.code_begin() );
duke@0 613 nm->print();
duke@0 614 nm->set_offset( low10(0) );
duke@0 615 nm->print();
duke@0 616 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
duke@0 617 nm->print();
duke@0 618
duke@0 619 while (--idx) {
duke@0 620 nm = nativeMovRegMem_at( nm->next_instruction_address() );
duke@0 621 nm->print();
duke@0 622 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
duke@0 623 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
duke@0 624 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
duke@0 625 "check unit test");
duke@0 626 nm->print();
duke@0 627 }
duke@0 628 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
duke@0 629 nm->print();
duke@0 630 }
duke@0 631
duke@0 632 VM_Version::revert();
duke@0 633 #endif // ASSERT
duke@0 634 }
duke@0 635
duke@0 636 // End code for unit testing implementation of NativeMovRegMem class
duke@0 637
duke@0 638 //--------------------------------------------------------------------------------
duke@0 639
duke@0 640
duke@0 641 void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) {
duke@0 642 Untested("copy_instruction_to");
duke@0 643 int instruction_size = next_instruction_address() - instruction_address();
duke@0 644 for (int i = 0; i < instruction_size; i += wordSize) {
duke@0 645 *(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
duke@0 646 }
duke@0 647 }
duke@0 648
duke@0 649
duke@0 650 void NativeMovRegMemPatching::verify() {
duke@0 651 NativeInstruction::verify();
duke@0 652 // make sure code pattern is actually a "ld" or "st" of some sort.
duke@0 653 int i0 = long_at(0);
duke@0 654 int op3 = inv_op3(i0);
duke@0 655
duke@0 656 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
duke@0 657
duke@0 658 if (!(is_op(i0, Assembler::ldst_op) &&
duke@0 659 inv_immed(i0) &&
duke@0 660 0 != (op3 < op3_ldst_int_limit
duke@0 661 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
duke@0 662 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) {
duke@0 663 int i1 = long_at(ldst_offset);
duke@0 664 Register rd = inv_rd(i0);
duke@0 665
duke@0 666 op3 = inv_op3(i1);
duke@0 667 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
duke@0 668 0 != (op3 < op3_ldst_int_limit
duke@0 669 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
duke@0 670 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
duke@0 671 fatal("not a ld* or st* op");
duke@0 672 }
duke@0 673 }
duke@0 674 }
duke@0 675
duke@0 676
duke@0 677 void NativeMovRegMemPatching::print() {
duke@0 678 if (is_immediate()) {
duke@0 679 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
duke@0 680 } else {
duke@0 681 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
duke@0 682 }
duke@0 683 }
duke@0 684
duke@0 685
duke@0 686 // Code for unit testing implementation of NativeMovRegMemPatching class
duke@0 687 void NativeMovRegMemPatching::test() {
duke@0 688 #ifdef ASSERT
duke@0 689 ResourceMark rm;
duke@0 690 CodeBuffer cb("test", 1000, 1000);
duke@0 691 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 692 NativeMovRegMemPatching* nm;
duke@0 693 uint idx = 0;
duke@0 694 uint idx1;
duke@0 695 int offsets[] = {
duke@0 696 0x0,
duke@0 697 0xffffffff,
duke@0 698 0x7fffffff,
duke@0 699 0x80000000,
duke@0 700 4096,
duke@0 701 4097,
duke@0 702 0x20,
duke@0 703 0x4000,
duke@0 704 };
duke@0 705
duke@0 706 VM_Version::allow_all();
duke@0 707
duke@0 708 a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
duke@0 709 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 710 a->ldsw( G5, I3, G4 ); idx++;
duke@0 711 a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
duke@0 712 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 713 a->ldsb( G5, I3, G4 ); idx++;
duke@0 714 a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
duke@0 715 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 716 a->ldsh( G5, I3, G4 ); idx++;
duke@0 717 a->lduw( G5, low10(0xffffffff), G4 ); idx++;
duke@0 718 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 719 a->lduw( G5, I3, G4 ); idx++;
duke@0 720 a->ldub( G5, low10(0xffffffff), G4 ); idx++;
duke@0 721 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 722 a->ldub( G5, I3, G4 ); idx++;
duke@0 723 a->lduh( G5, low10(0xffffffff), G4 ); idx++;
duke@0 724 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 725 a->lduh( G5, I3, G4 ); idx++;
duke@0 726 a->ldx( G5, low10(0xffffffff), G4 ); idx++;
duke@0 727 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 728 a->ldx( G5, I3, G4 ); idx++;
duke@0 729 a->ldd( G5, low10(0xffffffff), G4 ); idx++;
duke@0 730 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 731 a->ldd( G5, I3, G4 ); idx++;
duke@0 732 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
duke@0 733 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 734 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
duke@0 735
duke@0 736 a->stw( G5, G4, low10(0xffffffff) ); idx++;
duke@0 737 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 738 a->stw( G5, G4, I3 ); idx++;
duke@0 739 a->stb( G5, G4, low10(0xffffffff) ); idx++;
duke@0 740 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 741 a->stb( G5, G4, I3 ); idx++;
duke@0 742 a->sth( G5, G4, low10(0xffffffff) ); idx++;
duke@0 743 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 744 a->sth( G5, G4, I3 ); idx++;
duke@0 745 a->stx( G5, G4, low10(0xffffffff) ); idx++;
duke@0 746 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 747 a->stx( G5, G4, I3 ); idx++;
duke@0 748 a->std( G5, G4, low10(0xffffffff) ); idx++;
duke@0 749 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 750 a->std( G5, G4, I3 ); idx++;
duke@0 751 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
duke@0 752 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
duke@0 753 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
duke@0 754
duke@0 755 nm = nativeMovRegMemPatching_at( cb.code_begin() );
duke@0 756 nm->print();
duke@0 757 nm->set_offset( low10(0) );
duke@0 758 nm->print();
duke@0 759 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
duke@0 760 nm->print();
duke@0 761
duke@0 762 while (--idx) {
duke@0 763 nm = nativeMovRegMemPatching_at( nm->next_instruction_address() );
duke@0 764 nm->print();
duke@0 765 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
duke@0 766 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
duke@0 767 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
duke@0 768 "check unit test");
duke@0 769 nm->print();
duke@0 770 }
duke@0 771 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
duke@0 772 nm->print();
duke@0 773 }
duke@0 774
duke@0 775 VM_Version::revert();
duke@0 776 #endif // ASSERT
duke@0 777 }
duke@0 778 // End code for unit testing implementation of NativeMovRegMemPatching class
duke@0 779
duke@0 780
duke@0 781 //--------------------------------------------------------------------------------
duke@0 782
duke@0 783
duke@0 784 void NativeJump::verify() {
duke@0 785 NativeInstruction::verify();
duke@0 786 int i0 = long_at(sethi_offset);
duke@0 787 int i1 = long_at(jmpl_offset);
duke@0 788 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
duke@0 789 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg"
duke@0 790 Register rd = inv_rd(i0);
duke@0 791 #ifndef _LP64
duke@0 792 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
duke@0 793 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) ||
duke@0 794 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) &&
duke@0 795 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
duke@0 796 rd == inv_rs1(i1))) {
duke@0 797 fatal("not a jump_to instruction");
duke@0 798 }
duke@0 799 #else
duke@0 800 // In LP64, the jump instruction location varies for non relocatable
duke@0 801 // jumps, for example is could be sethi, xor, jmp instead of the
duke@0 802 // 7 instructions for sethi. So let's check sethi only.
duke@0 803 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
duke@0 804 fatal("not a jump_to instruction");
duke@0 805 }
duke@0 806 #endif
duke@0 807 }
duke@0 808
duke@0 809
duke@0 810 void NativeJump::print() {
duke@0 811 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination());
duke@0 812 }
duke@0 813
duke@0 814
duke@0 815 // Code for unit testing implementation of NativeJump class
duke@0 816 void NativeJump::test() {
duke@0 817 #ifdef ASSERT
duke@0 818 ResourceMark rm;
duke@0 819 CodeBuffer cb("test", 100, 100);
duke@0 820 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 821 NativeJump* nj;
duke@0 822 uint idx;
duke@0 823 int offsets[] = {
duke@0 824 0x0,
duke@0 825 0xffffffff,
duke@0 826 0x7fffffff,
duke@0 827 0x80000000,
duke@0 828 4096,
duke@0 829 4097,
duke@0 830 0x20,
duke@0 831 0x4000,
duke@0 832 };
duke@0 833
duke@0 834 VM_Version::allow_all();
duke@0 835
duke@0 836 a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
duke@0 837 a->jmpl(I3, low10(0x7fffbbbb), G0, RelocationHolder::none);
duke@0 838 a->delayed()->nop();
duke@0 839 a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
duke@0 840 a->jmpl(I3, low10(0x7fffbbbb), L3, RelocationHolder::none);
duke@0 841 a->delayed()->nop();
duke@0 842
duke@0 843 nj = nativeJump_at( cb.code_begin() );
duke@0 844 nj->print();
duke@0 845
duke@0 846 nj = nativeJump_at( nj->next_instruction_address() );
duke@0 847 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
duke@0 848 nj->set_jump_destination( nj->instruction_address() + offsets[idx] );
duke@0 849 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test");
duke@0 850 nj->print();
duke@0 851 }
duke@0 852
duke@0 853 VM_Version::revert();
duke@0 854 #endif // ASSERT
duke@0 855 }
duke@0 856 // End code for unit testing implementation of NativeJump class
duke@0 857
duke@0 858
duke@0 859 void NativeJump::insert(address code_pos, address entry) {
duke@0 860 Unimplemented();
duke@0 861 }
duke@0 862
duke@0 863 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
duke@0 864 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
duke@0 865 // Atomic write can be only with 1 word.
duke@0 866 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
duke@0 867 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere
duke@0 868 // in the header of the nmethod, within a short branch's span of the patch point.
duke@0 869 // Set up the jump sequence using NativeJump::insert, and then use an annulled
duke@0 870 // unconditional branch at the target site (an atomic 1-word update).
duke@0 871 // Limitations: You can only patch nmethods, with any given nmethod patched at
duke@0 872 // most once, and the patch must be in the nmethod's header.
duke@0 873 // It's messy, but you can ask the CodeCache for the nmethod containing the
duke@0 874 // target address.
duke@0 875
duke@0 876 // %%%%% For now, do something MT-stupid:
duke@0 877 ResourceMark rm;
duke@0 878 int code_size = 1 * BytesPerInstWord;
duke@0 879 CodeBuffer cb(verified_entry, code_size + 1);
duke@0 880 MacroAssembler* a = new MacroAssembler(&cb);
duke@0 881 if (VM_Version::v9_instructions_work()) {
duke@0 882 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler
duke@0 883 } else {
duke@0 884 a->lduw(G0, 0, O7); // "ld" must agree with code in the signal handler
duke@0 885 }
duke@0 886 ICache::invalidate_range(verified_entry, code_size);
duke@0 887 }
duke@0 888
duke@0 889
duke@0 890 void NativeIllegalInstruction::insert(address code_pos) {
duke@0 891 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
duke@0 892 nii->set_long_at(0, illegal_instruction());
duke@0 893 }
duke@0 894
duke@0 895 static int illegal_instruction_bits = 0;
duke@0 896
duke@0 897 int NativeInstruction::illegal_instruction() {
duke@0 898 if (illegal_instruction_bits == 0) {
duke@0 899 ResourceMark rm;
duke@0 900 char buf[40];
duke@0 901 CodeBuffer cbuf((address)&buf[0], 20);
duke@0 902 MacroAssembler* a = new MacroAssembler(&cbuf);
duke@0 903 address ia = a->pc();
duke@0 904 a->trap(ST_RESERVED_FOR_USER_0 + 1);
duke@0 905 int bits = *(int*)ia;
duke@0 906 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
duke@0 907 illegal_instruction_bits = bits;
duke@0 908 assert(illegal_instruction_bits != 0, "oops");
duke@0 909 }
duke@0 910 return illegal_instruction_bits;
duke@0 911 }
duke@0 912
duke@0 913 static int ic_miss_trap_bits = 0;
duke@0 914
duke@0 915 bool NativeInstruction::is_ic_miss_trap() {
duke@0 916 if (ic_miss_trap_bits == 0) {
duke@0 917 ResourceMark rm;
duke@0 918 char buf[40];
duke@0 919 CodeBuffer cbuf((address)&buf[0], 20);
duke@0 920 MacroAssembler* a = new MacroAssembler(&cbuf);
duke@0 921 address ia = a->pc();
duke@0 922 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2);
duke@0 923 int bits = *(int*)ia;
duke@0 924 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
duke@0 925 ic_miss_trap_bits = bits;
duke@0 926 assert(ic_miss_trap_bits != 0, "oops");
duke@0 927 }
duke@0 928 return long_at(0) == ic_miss_trap_bits;
duke@0 929 }
duke@0 930
duke@0 931
duke@0 932 bool NativeInstruction::is_illegal() {
duke@0 933 if (illegal_instruction_bits == 0) {
duke@0 934 return false;
duke@0 935 }
duke@0 936 return long_at(0) == illegal_instruction_bits;
duke@0 937 }
duke@0 938
duke@0 939
duke@0 940 void NativeGeneralJump::verify() {
duke@0 941 assert(((NativeInstruction *)this)->is_jump() ||
duke@0 942 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
duke@0 943 }
duke@0 944
duke@0 945
duke@0 946 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
duke@0 947 Assembler::Condition condition = Assembler::always;
duke@0 948 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) |
duke@0 949 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22);
duke@0 950 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos);
duke@0 951 ni->set_long_at(0, x);
duke@0 952 }
duke@0 953
duke@0 954
duke@0 955 // MT-safe patching of a jmp instruction (and following word).
duke@0 956 // First patches the second word, and then atomicly replaces
duke@0 957 // the first word with the first new instruction word.
duke@0 958 // Other processors might briefly see the old first word
duke@0 959 // followed by the new second word. This is OK if the old
duke@0 960 // second word is harmless, and the new second word may be
duke@0 961 // harmlessly executed in the delay slot of the call.
duke@0 962 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
duke@0 963 assert(Patching_lock->is_locked() ||
duke@0 964 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
duke@0 965 assert (instr_addr != NULL, "illegal address for code patching");
duke@0 966 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call
duke@0 967 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
duke@0 968 int i0 = ((int*)code_buffer)[0];
duke@0 969 int i1 = ((int*)code_buffer)[1];
duke@0 970 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
duke@0 971 assert(inv_op(*contention_addr) == Assembler::arith_op ||
duke@0 972 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
duke@0 973 "must not interfere with original call");
duke@0 974 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
duke@0 975 h_jump->set_long_at(1*BytesPerInstWord, i1);
duke@0 976 h_jump->set_long_at(0*BytesPerInstWord, i0);
duke@0 977 // NOTE: It is possible that another thread T will execute
duke@0 978 // only the second patched word.
duke@0 979 // In other words, since the original instruction is this
duke@0 980 // jmp patching_stub; nop (NativeGeneralJump)
duke@0 981 // and the new sequence from the buffer is this:
duke@0 982 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
duke@0 983 // what T will execute is this:
duke@0 984 // jmp patching_stub; add %r, %lo(K), %r
duke@0 985 // thereby putting garbage into %r before calling the patching stub.
duke@0 986 // This is OK, because the patching stub ignores the value of %r.
duke@0 987
duke@0 988 // Make sure the first-patched instruction, which may co-exist
duke@0 989 // briefly with the call, will do something harmless.
duke@0 990 assert(inv_op(*contention_addr) == Assembler::arith_op ||
duke@0 991 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
duke@0 992 "must not interfere with original call");
duke@0 993 }