OpenJDK / panama / dev

changeset 58382:e2ad48fba3a8 vectorIntrinsics

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Remove redundant MaxV and MinV matcher entries
author rlupusoru
date Wed, 22 Aug 2018 10:46:44 -0700
parents 8a0b182b10ac
children e7182f8fc03f
files src/hotspot/cpu/x86/x86.ad
diffstat 1 files changed, 28 insertions(+), 116 deletions(-) [+]
line wrap: on
line diff
--- a/src/hotspot/cpu/x86/x86.ad	Tue Aug 21 16:54:45 2018 -0700
+++ b/src/hotspot/cpu/x86/x86.ad	Wed Aug 22 10:46:44 2018 -0700
@@ -14521,41 +14521,19 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct min16B_reg_evex(vecX dst, vecX src1, vecX src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsb  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 0;
+instruct min32B_reg(vecY dst, vecY src1, vecY src2) %{
+  predicate(UseAVX > 1 && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
+  match(Set dst (MinV src1 src2));
+  format %{ "vpminsb    $dst,$src1,$src2\t! " %}
+  ins_encode %{
+    int vector_len = 1;
     __ vpminsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
   %}
   ins_pipe( pipe_slow );
 %}
 
-instruct min32B_reg_avx(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 1 && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsb    $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpminsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
-instruct min32B_reg_evex(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsb  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpminsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
 instruct min64B_reg_evex(vecZ dst, vecZ src1, vecZ src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 64 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
+  predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 64 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
   match(Set dst (MinV src1 src2));
   format %{ "vpminsb  $dst,$src1,$src2\t! " %}
   ins_encode %{
@@ -14614,41 +14592,19 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct min8S_reg_evex(vecX dst, vecX src1, vecX src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsw  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 0;
+instruct min16S_reg(vecY dst, vecY src1, vecY src2) %{
+  predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
+  match(Set dst (MinV src1 src2));
+  format %{ "vpminsw    $dst,$src1,$src2\t! " %}
+  ins_encode %{
+    int vector_len = 1;
     __ vpminsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
   %}
   ins_pipe( pipe_slow );
 %}
 
-instruct min16S_reg_avx(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsw    $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpminsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
-instruct min16S_reg_evex(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MinV src1 src2));
-  format %{ "vpminsw  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpminsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
 instruct min32S_reg_evex(vecZ dst, vecZ src1, vecZ src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
+  predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
   match(Set dst (MinV src1 src2));
   format %{ "vpminsw  $dst,$src1,$src2\t! " %}
   ins_encode %{
@@ -15096,41 +15052,19 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct max16B_reg_evex(vecX dst, vecX src1, vecX src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsb  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 0;
+instruct max32B_reg(vecY dst, vecY src1, vecY src2) %{
+  predicate(UseAVX > 1 && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
+  match(Set dst (MaxV src1 src2));
+  format %{ "vpmaxsb    $dst,$src1,$src2\t! " %}
+  ins_encode %{
+    int vector_len = 1;
     __ vpmaxsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
   %}
   ins_pipe( pipe_slow );
 %}
 
-instruct max32B_reg_avx(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 1 && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsb    $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpmaxsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
-instruct max32B_reg_evex(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsb  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpmaxsb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
 instruct max64B_reg_evex(vecZ dst, vecZ src1, vecZ src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 64 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
+  predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 64 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
   match(Set dst (MaxV src1 src2));
   format %{ "vpmaxsb  $dst,$src1,$src2\t! " %}
   ins_encode %{
@@ -15189,41 +15123,19 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct max8S_reg_evex(vecX dst, vecX src1, vecX src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsw  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 0;
+instruct max16S_reg(vecY dst, vecY src1, vecY src2) %{
+  predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
+  match(Set dst (MaxV src1 src2));
+  format %{ "vpmaxsw    $dst,$src1,$src2\t! " %}
+  ins_encode %{
+    int vector_len = 1;
     __ vpmaxsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
   %}
   ins_pipe( pipe_slow );
 %}
 
-instruct max16S_reg_avx(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsw    $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpmaxsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
-instruct max16S_reg_evex(vecY dst, vecY src1, vecY src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
-  match(Set dst (MaxV src1 src2));
-  format %{ "vpmaxsw  $dst,$src1,$src2\t! " %}
-  ins_encode %{
-    int vector_len = 1;
-    __ vpmaxsw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len);
-  %}
-  ins_pipe( pipe_slow );
-%}
-
 instruct max32S_reg_evex(vecZ dst, vecZ src1, vecZ src2) %{
-  predicate(UseAVX > 2 && VM_Version::supports_avx512vl() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
+  predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
   match(Set dst (MaxV src1 src2));
   format %{ "vpmaxsw  $dst,$src1,$src2\t! " %}
   ins_encode %{
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