changeset 52372:0ecb4e520110

8209093: JEP 340: One AArch64 Port, Not Two Reviewed-by: dholmes, erikj, mikael, shade, avoitylov, bulasevich
author bobv
date Tue, 30 Oct 2018 10:39:19 -0400
parents 3c981e581f93
children 0c25fa66b5c5
files doc/building.html doc/building.md make/autoconf/flags-cflags.m4 make/autoconf/flags-ldflags.m4 make/autoconf/flags.m4 make/autoconf/hotspot.m4 make/conf/jib-profiles.js make/hotspot/lib/CompileJvm.gmk src/hotspot/cpu/arm/abstractInterpreter_arm.cpp src/hotspot/cpu/arm/arm.ad src/hotspot/cpu/arm/arm_64.ad src/hotspot/cpu/arm/assembler_arm.hpp src/hotspot/cpu/arm/assembler_arm_64.cpp src/hotspot/cpu/arm/assembler_arm_64.hpp src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp src/hotspot/cpu/arm/c1_Defs_arm.hpp src/hotspot/cpu/arm/c1_FrameMap_arm.cpp src/hotspot/cpu/arm/c1_FrameMap_arm.hpp src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp src/hotspot/cpu/arm/c1_LIRAssembler_arm.hpp src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp src/hotspot/cpu/arm/c1_LIRGenerator_arm.hpp src/hotspot/cpu/arm/c1_LIR_arm.cpp src/hotspot/cpu/arm/c1_LinearScan_arm.hpp src/hotspot/cpu/arm/c1_MacroAssembler_arm.cpp src/hotspot/cpu/arm/c1_Runtime1_arm.cpp src/hotspot/cpu/arm/c2_globals_arm.hpp src/hotspot/cpu/arm/frame_arm.cpp src/hotspot/cpu/arm/frame_arm.hpp src/hotspot/cpu/arm/frame_arm.inline.hpp src/hotspot/cpu/arm/gc/g1/g1BarrierSetAssembler_arm.cpp src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp src/hotspot/cpu/arm/gc/shared/cardTableBarrierSetAssembler_arm.cpp src/hotspot/cpu/arm/globalDefinitions_arm.hpp src/hotspot/cpu/arm/globals_arm.hpp src/hotspot/cpu/arm/icBuffer_arm.cpp src/hotspot/cpu/arm/icache_arm.cpp src/hotspot/cpu/arm/interp_masm_arm.cpp src/hotspot/cpu/arm/interp_masm_arm.hpp src/hotspot/cpu/arm/interpreterRT_arm.cpp src/hotspot/cpu/arm/interpreterRT_arm.hpp src/hotspot/cpu/arm/jniFastGetField_arm.cpp src/hotspot/cpu/arm/jniTypes_arm.hpp src/hotspot/cpu/arm/macroAssembler_arm.cpp src/hotspot/cpu/arm/macroAssembler_arm.hpp src/hotspot/cpu/arm/macroAssembler_arm.inline.hpp src/hotspot/cpu/arm/methodHandles_arm.cpp src/hotspot/cpu/arm/nativeInst_arm.hpp src/hotspot/cpu/arm/nativeInst_arm_64.cpp src/hotspot/cpu/arm/nativeInst_arm_64.hpp src/hotspot/cpu/arm/register_arm.cpp src/hotspot/cpu/arm/register_arm.hpp src/hotspot/cpu/arm/register_definitions_arm.cpp src/hotspot/cpu/arm/relocInfo_arm.cpp src/hotspot/cpu/arm/runtime_arm.cpp src/hotspot/cpu/arm/sharedRuntime_arm.cpp src/hotspot/cpu/arm/stubGenerator_arm.cpp src/hotspot/cpu/arm/stubRoutines_arm.cpp src/hotspot/cpu/arm/stubRoutines_arm.hpp src/hotspot/cpu/arm/templateInterpreterGenerator_arm.cpp src/hotspot/cpu/arm/templateTable_arm.cpp src/hotspot/cpu/arm/vm_version_arm.hpp src/hotspot/cpu/arm/vm_version_arm_64.cpp src/hotspot/cpu/arm/vm_version_ext_arm.cpp src/hotspot/cpu/arm/vtableStubs_arm.cpp src/hotspot/os_cpu/linux_arm/atomic_linux_arm.hpp src/hotspot/os_cpu/linux_arm/copy_linux_arm.inline.hpp src/hotspot/os_cpu/linux_arm/globals_linux_arm.hpp src/hotspot/os_cpu/linux_arm/linux_arm_32.s src/hotspot/os_cpu/linux_arm/linux_arm_64.s src/hotspot/os_cpu/linux_arm/orderAccess_linux_arm.hpp src/hotspot/os_cpu/linux_arm/os_linux_arm.cpp src/hotspot/os_cpu/linux_arm/os_linux_arm.hpp src/hotspot/os_cpu/linux_arm/prefetch_linux_arm.inline.hpp src/hotspot/os_cpu/linux_arm/thread_linux_arm.cpp src/hotspot/share/utilities/macros.hpp src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java
diffstat 78 files changed, 316 insertions(+), 15496 deletions(-) [+]
line wrap: on
line diff
--- a/doc/building.html	Mon Oct 29 11:31:25 2018 -0700
+++ b/doc/building.html	Tue Oct 30 10:39:19 2018 -0400
@@ -707,7 +707,6 @@
 <p>Additional architectures might be supported by Debian/Ubuntu Ports.</p>
 <h3 id="building-for-armaarch64">Building for ARM/aarch64</h3>
 <p>A common cross-compilation target is the ARM CPU. When building for ARM, it is useful to set the ABI profile. A number of pre-defined ABI profiles are available using <code>--with-abi-profile</code>: arm-vfp-sflt, arm-vfp-hflt, arm-sflt, armv5-vfp-sflt, armv6-vfp-hflt. Note that soft-float ABIs are no longer properly supported by the JDK.</p>
-<p>The JDK contains two different ports for the aarch64 platform, one is the original aarch64 port from the <a href="http://openjdk.java.net/projects/aarch64-port">AArch64 Port Project</a> and one is a 64-bit version of the Oracle contributed ARM port. When targeting aarch64, by the default the original aarch64 port is used. To select the Oracle ARM 64 port, use <code>--with-cpu-port=arm64</code>. Also set the corresponding value (<code>aarch64</code> or <code>arm64</code>) to --with-abi-profile, to ensure a consistent build.</p>
 <h3 id="verifying-the-build">Verifying the Build</h3>
 <p>The build will end up in a directory named like <code>build/linux-arm-normal-server-release</code>.</p>
 <p>Inside this build output directory, the <code>images/jdk</code> will contain the newly built JDK, for your <em>target</em> system.</p>
--- a/doc/building.md	Mon Oct 29 11:31:25 2018 -0700
+++ b/doc/building.md	Tue Oct 30 10:39:19 2018 -0400
@@ -1080,14 +1080,6 @@
 armv5-vfp-sflt, armv6-vfp-hflt. Note that soft-float ABIs are no longer
 properly supported by the JDK.
 
-The JDK contains two different ports for the aarch64 platform, one is the
-original aarch64 port from the [AArch64 Port Project](
-http://openjdk.java.net/projects/aarch64-port) and one is a 64-bit version of
-the Oracle contributed ARM port. When targeting aarch64, by the default the
-original aarch64 port is used. To select the Oracle ARM 64 port, use
-`--with-cpu-port=arm64`. Also set the corresponding value (`aarch64` or
-`arm64`) to --with-abi-profile, to ensure a consistent build.
-
 ### Verifying the Build
 
 The build will end up in a directory named like
--- a/make/autoconf/flags-cflags.m4	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/autoconf/flags-cflags.m4	Tue Oct 30 10:39:19 2018 -0400
@@ -747,10 +747,6 @@
       # -Wno-psabi to get rid of annoying "note: the mangling of 'va_list' has changed in GCC 4.4"
       $1_CFLAGS_CPU="-fsigned-char -Wno-psabi $ARM_ARCH_TYPE_FLAGS $ARM_FLOAT_TYPE_FLAGS -DJDK_ARCH_ABI_PROP_NAME='\"\$(JDK_ARCH_ABI_PROP_NAME)\"'"
       $1_CFLAGS_CPU_JVM="-DARM"
-    elif test "x$FLAGS_CPU" = xaarch64; then
-      if test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-        $1_CFLAGS_CPU_JVM="-fsigned-char -DARM"
-      fi
     elif test "x$FLAGS_CPU_ARCH" = xppc; then
       $1_CFLAGS_CPU_JVM="-minsert-sched-nops=regroup_exact -mno-multiple -mno-string"
       if test "x$FLAGS_CPU" = xppc64; then
--- a/make/autoconf/flags-ldflags.m4	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/autoconf/flags-ldflags.m4	Tue Oct 30 10:39:19 2018 -0400
@@ -173,10 +173,6 @@
     elif test "x$OPENJDK_$1_CPU" = xarm; then
       $1_CPU_LDFLAGS_JVM_ONLY="${$1_CPU_LDFLAGS_JVM_ONLY} -fsigned-char"
       $1_CPU_LDFLAGS="$ARM_ARCH_TYPE_FLAGS $ARM_FLOAT_TYPE_FLAGS"
-    elif test "x$FLAGS_CPU" = xaarch64; then
-      if test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-        $1_CPU_LDFLAGS_JVM_ONLY="${$1_CPU_LDFLAGS_JVM_ONLY} -fsigned-char"
-      fi
     fi
 
   elif test "x$TOOLCHAIN_TYPE" = xsolstudio; then
--- a/make/autoconf/flags.m4	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/autoconf/flags.m4	Tue Oct 30 10:39:19 2018 -0400
@@ -34,7 +34,7 @@
 AC_DEFUN([FLAGS_SETUP_ABI_PROFILE],
 [
   AC_ARG_WITH(abi-profile, [AS_HELP_STRING([--with-abi-profile],
-      [specify ABI profile for ARM builds (arm-vfp-sflt,arm-vfp-hflt,arm-sflt, armv5-vfp-sflt,armv6-vfp-hflt,arm64,aarch64) @<:@toolchain dependent@:>@ ])])
+      [specify ABI profile for ARM builds (arm-vfp-sflt,arm-vfp-hflt,arm-sflt, armv5-vfp-sflt,armv6-vfp-hflt,aarch64) @<:@toolchain dependent@:>@ ])])
 
   if test "x$with_abi_profile" != x; then
     if test "x$OPENJDK_TARGET_CPU" != xarm && \
@@ -61,10 +61,6 @@
     elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xarmv6-vfp-hflt; then
       ARM_FLOAT_TYPE=vfp-hflt
       ARM_ARCH_TYPE_FLAGS='-march=armv6 -marm'
-    elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xarm64; then
-      # No special flags, just need to trigger setting JDK_ARCH_ABI_PROP_NAME
-      ARM_FLOAT_TYPE=
-      ARM_ARCH_TYPE_FLAGS=
     elif test "x$OPENJDK_TARGET_ABI_PROFILE" = xaarch64; then
       # No special flags, just need to trigger setting JDK_ARCH_ABI_PROP_NAME
       ARM_FLOAT_TYPE=
--- a/make/autoconf/hotspot.m4	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/autoconf/hotspot.m4	Tue Oct 30 10:39:19 2018 -0400
@@ -72,8 +72,6 @@
   AC_ARG_WITH([jvm-variants], [AS_HELP_STRING([--with-jvm-variants],
       [JVM variants (separated by commas) to build (server,client,minimal,core,zero,custom) @<:@server@:>@])])
 
-  SETUP_HOTSPOT_TARGET_CPU_PORT
-
   if test "x$with_jvm_variants" = x; then
     with_jvm_variants="server"
   fi
@@ -299,9 +297,6 @@
   if test "x$OPENJDK_TARGET_CPU" = xarm; then
     HOTSPOT_TARGET_CPU=arm_32
     HOTSPOT_TARGET_CPU_DEFINE="ARM32"
-  elif test "x$OPENJDK_TARGET_CPU" = xaarch64 && test "x$HOTSPOT_TARGET_CPU_PORT" = xarm64; then
-    HOTSPOT_TARGET_CPU=arm_64
-    HOTSPOT_TARGET_CPU_ARCH=arm
   fi
 
   # Verify that dependencies are met for explicitly set features.
@@ -542,6 +537,9 @@
 
   # Used for verification of Makefiles by check-jvm-feature
   AC_SUBST(VALID_JVM_FEATURES)
+
+  # --with-cpu-port is no longer supported
+  BASIC_DEPRECATED_ARG_WITH(with-cpu-port)
 ])
 
 ###############################################################################
@@ -579,31 +577,6 @@
 ])
 
 ################################################################################
-#
-# Specify which sources will be used to build the 64-bit ARM port
-#
-# --with-cpu-port=arm64   will use hotspot/src/cpu/arm
-# --with-cpu-port=aarch64 will use hotspot/src/cpu/aarch64
-#
-AC_DEFUN([SETUP_HOTSPOT_TARGET_CPU_PORT],
-[
-  AC_ARG_WITH(cpu-port, [AS_HELP_STRING([--with-cpu-port],
-      [specify sources to use for Hotspot 64-bit ARM port (arm64,aarch64) @<:@aarch64@:>@ ])])
-
-  if test "x$with_cpu_port" != x; then
-    if test "x$OPENJDK_TARGET_CPU" != xaarch64; then
-      AC_MSG_ERROR([--with-cpu-port only available on aarch64])
-    fi
-    if test "x$with_cpu_port" != xarm64 && \
-        test "x$with_cpu_port" != xaarch64; then
-      AC_MSG_ERROR([--with-cpu-port must specify arm64 or aarch64])
-    fi
-    HOTSPOT_TARGET_CPU_PORT="$with_cpu_port"
-  fi
-])
-
-
-################################################################################
 # Check if gtest should be built
 #
 AC_DEFUN_ONCE([HOTSPOT_ENABLE_DISABLE_GTEST],
--- a/make/conf/jib-profiles.js	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/conf/jib-profiles.js	Tue Oct 30 10:39:19 2018 -0400
@@ -233,8 +233,7 @@
     common.main_profile_names = [
         "linux-x64", "linux-x86", "macosx-x64", "solaris-x64",
         "solaris-sparcv9", "windows-x64", "windows-x86",
-        "linux-aarch64", "linux-arm32", "linux-arm64", "linux-arm-vfp-hflt",
-        "linux-arm-vfp-hflt-dyn"
+        "linux-aarch64", "linux-arm32"
     ];
 
     // These are the base setttings for all the main build profiles.
@@ -440,20 +439,7 @@
             dependencies: ["devkit", "build_devkit", "cups"],
             configure_args: [
                 "--openjdk-target=aarch64-linux-gnu", "--with-freetype=bundled",
-                "--disable-warnings-as-errors", "--with-cpu-port=aarch64",
-            ],
-        },
-
-        "linux-arm64": {
-            target_os: "linux",
-            target_cpu: "aarch64",
-            build_cpu: "x64",
-            dependencies: ["devkit", "build_devkit", "cups", "headless_stubs"],
-            configure_args: [
-                "--with-cpu-port=arm64",
-                "--with-jvm-variants=server",
-                "--openjdk-target=aarch64-linux-gnu",
-                "--enable-headless-only"
+                "--disable-warnings-as-errors"
             ],
         },
 
@@ -467,30 +453,7 @@
                 "--with-abi-profile=arm-vfp-hflt", "--disable-warnings-as-errors"
             ],
         },
-
-        "linux-arm-vfp-hflt": {
-            target_os: "linux",
-            target_cpu: "arm",
-            build_cpu: "x64",
-            dependencies: ["devkit", "build_devkit", "cups"],
-            configure_args: [
-                "--with-jvm-variants=minimal1,client",
-                "--with-x=" + input.get("devkit", "install_path") + "/arm-linux-gnueabihf/libc/usr/X11R6-PI",
-                "--with-fontconfig=" + input.get("devkit", "install_path") + "/arm-linux-gnueabihf/libc/usr/X11R6-PI",
-                "--openjdk-target=arm-linux-gnueabihf",
-                "--with-abi-profile=arm-vfp-hflt",
-                "--with-freetype=bundled"
-            ],
-        },
-
-        // Special version of the SE profile adjusted to be testable on arm64 hardware.
-        "linux-arm-vfp-hflt-dyn": {
-            configure_args: "--with-stdc++lib=dynamic"
-        }
     };
-    // Let linux-arm-vfp-hflt-dyn inherit everything from linux-arm-vfp-hflt
-    profiles["linux-arm-vfp-hflt-dyn"] = concatObjects(
-        profiles["linux-arm-vfp-hflt-dyn"], profiles["linux-arm-vfp-hflt"]);
 
     // Add the base settings to all the main profiles
     common.main_profile_names.forEach(function (name) {
@@ -617,15 +580,6 @@
         },
        "linux-arm32": {
             platform: "linux-arm32",
-        },
-       "linux-arm64": {
-            platform: "linux-arm64-vfp-hflt",
-        },
-        "linux-arm-vfp-hflt": {
-            platform: "linux-arm32-vfp-hflt",
-        },
-        "linux-arm-vfp-hflt-dyn": {
-            platform: "linux-arm32-vfp-hflt-dyn",
         }
     }
     // Generate common artifacts for all main profiles
@@ -850,16 +804,8 @@
         solaris_x64: "SS12u4-Solaris11u1+1.0",
         solaris_sparcv9: "SS12u6-Solaris11u3+1.0",
         windows_x64: "VS2017-15.5.5+1.0",
-        linux_aarch64: (input.profile != null && input.profile.indexOf("arm64") >= 0
-                    ? "gcc-linaro-aarch64-linux-gnu-4.8-2013.11_linux+1.0"
-                    : "gcc7.3.0-Fedora27+1.0"),
-        linux_arm: (input.profile != null && input.profile.indexOf("hflt") >= 0
-                    ? "gcc-linaro-arm-linux-gnueabihf-raspbian-2012.09-20120921_linux+1.0"
-                    : (input.profile != null && input.profile.indexOf("arm32") >= 0
-                       ? "gcc7.3.0-Fedora27+1.0"
-                       : "arm-linaro-4.7+1.0"
-                       )
-                    )
+        linux_aarch64: "gcc7.3.0-Fedora27+1.0",
+        linux_arm: "gcc7.3.0-Fedora27+1.0"
     };
 
     var devkit_platform = (input.target_cpu == "x86"
--- a/make/hotspot/lib/CompileJvm.gmk	Mon Oct 29 11:31:25 2018 -0700
+++ b/make/hotspot/lib/CompileJvm.gmk	Tue Oct 30 10:39:19 2018 -0400
@@ -60,12 +60,6 @@
   OPENJDK_TARGET_CPU_VM_VERSION := amd64
 else ifeq ($(OPENJDK_TARGET_CPU), sparcv9)
   OPENJDK_TARGET_CPU_VM_VERSION := sparc
-else ifeq ($(HOTSPOT_TARGET_CPU_ARCH), arm)
-  ifeq ($(OPENJDK_TARGET_CPU), aarch64)
-    # This sets the Oracle Aarch64 port to use arm64
-    # while the original Aarch64 port uses aarch64
-    OPENJDK_TARGET_CPU_VM_VERSION := arm64
-  endif
 else
   OPENJDK_TARGET_CPU_VM_VERSION := $(OPENJDK_TARGET_CPU)
 endif
--- a/src/hotspot/cpu/arm/abstractInterpreter_arm.cpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/abstractInterpreter_arm.cpp	Tue Oct 30 10:39:19 2018 -0400
@@ -38,19 +38,6 @@
 int AbstractInterpreter::BasicType_as_index(BasicType type) {
   int i = 0;
   switch (type) {
-#ifdef AARCH64
-    case T_BOOLEAN: i = 0; break;
-    case T_CHAR   : i = 1; break;
-    case T_BYTE   : i = 2; break;
-    case T_SHORT  : i = 3; break;
-    case T_INT    : // fall through
-    case T_LONG   : // fall through
-    case T_VOID   : // fall through
-    case T_FLOAT  : // fall through
-    case T_DOUBLE : i = 4; break;
-    case T_OBJECT : // fall through
-    case T_ARRAY  : i = 5; break;
-#else
     case T_VOID   : i = 0; break;
     case T_BOOLEAN: i = 1; break;
     case T_CHAR   : i = 2; break;
@@ -62,7 +49,6 @@
     case T_LONG   : i = 7; break;
     case T_FLOAT  : i = 8; break;
     case T_DOUBLE : i = 9; break;
-#endif // AARCH64
     default       : ShouldNotReachHere();
   }
   assert(0 <= i && i < AbstractInterpreter::number_of_result_handlers, "index out of bounds");
@@ -71,7 +57,7 @@
 
 // How much stack a method activation needs in words.
 int AbstractInterpreter::size_top_interpreter_activation(Method* method) {
-  const int stub_code = AARCH64_ONLY(24) NOT_AARCH64(12);  // see generate_call_stub
+  const int stub_code = 12;  // see generate_call_stub
   // Save space for one monitor to get into the interpreted method in case
   // the method is synchronized
   int monitor_size    = method->is_synchronized() ?
@@ -108,9 +94,6 @@
          (moncount*frame::interpreter_frame_monitor_size()) +
          tempcount*Interpreter::stackElementWords + extra_args;
 
-#ifdef AARCH64
-  size = align_up(size, StackAlignmentInBytes/BytesPerWord);
-#endif // AARCH64
 
   return size;
 }
@@ -146,65 +129,7 @@
   // interpreter_frame_sender_sp is the original sp of the caller (the unextended_sp)
   // and sender_sp is (fp + sender_sp_offset*wordSize)
 
-#ifdef AARCH64
-  intptr_t* locals;
-  if (caller->is_interpreted_frame()) {
-    // attach locals to the expression stack of caller interpreter frame
-    locals = caller->interpreter_frame_tos_address() + caller_actual_parameters*Interpreter::stackElementWords - 1;
-  } else {
-    assert (is_bottom_frame, "should be");
-    locals = interpreter_frame->fp() + frame::sender_sp_offset + method->max_locals() - 1;
-  }
-
-  if (TraceDeoptimization) {
-    tty->print_cr("layout_activation:");
-
-    if (caller->is_entry_frame()) {
-      tty->print("entry ");
-    }
-    if (caller->is_compiled_frame()) {
-      tty->print("compiled ");
-    }
-    if (caller->is_interpreted_frame()) {
-      tty->print("interpreted ");
-    }
-    tty->print_cr("caller: sp=%p, unextended_sp=%p, fp=%p, pc=%p", caller->sp(), caller->unextended_sp(), caller->fp(), caller->pc());
-    tty->print_cr("interpreter_frame: sp=%p, unextended_sp=%p, fp=%p, pc=%p", interpreter_frame->sp(), interpreter_frame->unextended_sp(), interpreter_frame->fp(), interpreter_frame->pc());
-    tty->print_cr("method: max_locals = %d, size_of_parameters = %d", method->max_locals(), method->size_of_parameters());
-    tty->print_cr("caller_actual_parameters = %d", caller_actual_parameters);
-    tty->print_cr("locals = %p", locals);
-  }
-
-#ifdef ASSERT
-  if (caller_actual_parameters != method->size_of_parameters()) {
-    assert(caller->is_interpreted_frame(), "adjusted caller_actual_parameters, but caller is not interpreter frame");
-    Bytecode_invoke inv(caller->interpreter_frame_method(), caller->interpreter_frame_bci());
-
-    if (is_bottom_frame) {
-      assert(caller_actual_parameters == 0, "invalid adjusted caller_actual_parameters value for bottom frame");
-      assert(inv.is_invokedynamic() || inv.is_invokehandle(), "adjusted caller_actual_parameters for bottom frame, but not invokedynamic/invokehandle");
-    } else {
-      assert(caller_actual_parameters == method->size_of_parameters()+1, "invalid adjusted caller_actual_parameters value");
-      assert(!inv.is_invokedynamic() && MethodHandles::has_member_arg(inv.klass(), inv.name()), "adjusted caller_actual_parameters, but no member arg");
-    }
-  }
-  if (caller->is_interpreted_frame()) {
-    intptr_t* locals_base = (locals - method->max_locals()*Interpreter::stackElementWords + 1);
-    locals_base = align_down(locals_base, StackAlignmentInBytes);
-    assert(interpreter_frame->sender_sp() <= locals_base, "interpreter-to-interpreter frame chaining");
-
-  } else if (caller->is_compiled_frame()) {
-    assert(locals + 1 <= caller->unextended_sp(), "compiled-to-interpreter frame chaining");
-
-  } else {
-    assert(caller->is_entry_frame(), "should be");
-    assert(locals + 1 <= caller->fp(), "entry-to-interpreter frame chaining");
-  }
-#endif // ASSERT
-
-#else
   intptr_t* locals = interpreter_frame->sender_sp() + max_locals - 1;
-#endif // AARCH64
 
   interpreter_frame->interpreter_frame_set_locals(locals);
   BasicObjectLock* montop = interpreter_frame->interpreter_frame_monitor_begin();
@@ -215,44 +140,16 @@
   intptr_t* stack_top = (intptr_t*) monbot  -
     tempcount*Interpreter::stackElementWords -
     popframe_extra_args;
-#ifdef AARCH64
-  interpreter_frame->interpreter_frame_set_stack_top(stack_top);
-
-  // We have to add extra reserved slots to max_stack. There are 3 users of the extra slots,
-  // none of which are at the same time, so we just need to make sure there is enough room
-  // for the biggest user:
-  //   -reserved slot for exception handler
-  //   -reserved slots for JSR292. Method::extra_stack_entries() is the size.
-  //   -3 reserved slots so get_method_counters() can save some registers before call_VM().
-  int max_stack = method->constMethod()->max_stack() + MAX2(3, Method::extra_stack_entries());
-  intptr_t* extended_sp = (intptr_t*) monbot  -
-    (max_stack * Interpreter::stackElementWords) -
-    popframe_extra_args;
-  extended_sp = align_down(extended_sp, StackAlignmentInBytes);
-  interpreter_frame->interpreter_frame_set_extended_sp(extended_sp);
-#else
   interpreter_frame->interpreter_frame_set_last_sp(stack_top);
-#endif // AARCH64
 
   // All frames but the initial (oldest) interpreter frame we fill in have a
   // value for sender_sp that allows walking the stack but isn't
   // truly correct. Correct the value here.
 
-#ifdef AARCH64
-  if (caller->is_interpreted_frame()) {
-    intptr_t* sender_sp = align_down(caller->interpreter_frame_tos_address(), StackAlignmentInBytes);
-    interpreter_frame->set_interpreter_frame_sender_sp(sender_sp);
-
-  } else {
-    // in case of non-interpreter caller sender_sp of the oldest frame is already
-    // set to valid value
-  }
-#else
   if (extra_locals != 0 &&
       interpreter_frame->sender_sp() == interpreter_frame->interpreter_frame_sender_sp() ) {
     interpreter_frame->set_interpreter_frame_sender_sp(caller->sp() + extra_locals);
   }
-#endif // AARCH64
 
   *interpreter_frame->interpreter_frame_cache_addr() =
     method->constants()->cache();
--- a/src/hotspot/cpu/arm/arm.ad	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/arm.ad	Tue Oct 30 10:39:19 2018 -0400
@@ -67,15 +67,10 @@
   return MacroAssembler::_cache_fully_reachable();
 }
 
-#ifdef AARCH64
-#define ldr_32 ldr_w
-#define str_32 str_w
-#else
 #define ldr_32 ldr
 #define str_32 str
 #define tst_32 tst
 #define teq_32 teq
-#endif
 #if 1
 extern bool PrintOptoAssembly;
 #endif
@@ -111,12 +106,7 @@
   static int emit_deopt_handler(CodeBuffer& cbuf);
 
   static uint size_exception_handler() {
-#ifdef AARCH64
-    // ldr_literal; br; (pad); <literal>
-    return 3 * Assembler::InstructionSize + wordSize;
-#else
     return ( 3 * 4 );
-#endif
   }
 
 
@@ -205,9 +195,6 @@
 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
 
 int Compile::ConstantTable::calculate_table_base_offset() const {
-#ifdef AARCH64
-  return 0;
-#else
   int offset = -(size() / 2);
   // flds, fldd: 8-bit  offset multiplied by 4: +/- 1024
   // ldr, ldrb : 12-bit offset:                 +/- 4096
@@ -215,7 +202,6 @@
     offset = Assembler::min_simm10();
   }
   return offset;
-#endif
 }
 
 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
@@ -240,11 +226,7 @@
 }
 
 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
-#ifdef AARCH64
-  return 5 * Assembler::InstructionSize;
-#else
   return 8;
-#endif
 }
 
 #ifndef PRODUCT
@@ -262,12 +244,6 @@
   for (int i = 0; i < OptoPrologueNops; i++) {
     st->print_cr("NOP"); st->print("\t");
   }
-#ifdef AARCH64
-  if (OptoPrologueNops <= 0) {
-    st->print_cr("NOP\t! required for safe patching");
-    st->print("\t");
-  }
-#endif
 
   size_t framesize = C->frame_size_in_bytes();
   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
@@ -298,11 +274,6 @@
   for (int i = 0; i < OptoPrologueNops; i++) {
     __ nop();
   }
-#ifdef AARCH64
-  if (OptoPrologueNops <= 0) {
-    __ nop(); // required for safe patching by patch_verified_entry()
-  }
-#endif
 
   size_t framesize = C->frame_size_in_bytes();
   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
@@ -361,18 +332,8 @@
 
   if (do_polling() && ra_->C->is_method_compilation()) {
     st->print("\n\t");
-#ifdef AARCH64
-    if (MacroAssembler::page_reachable_from_cache(os::get_polling_page())) {
-      st->print("ADRP     Rtemp, #PollAddr\t! Load Polling address\n\t");
-      st->print("LDR      ZR,[Rtemp + #PollAddr & 0xfff]\t!Poll for Safepointing");
-    } else {
-      st->print("mov_slow Rtemp, #PollAddr\t! Load Polling address\n\t");
-      st->print("LDR      ZR,[Rtemp]\t!Poll for Safepointing");
-    }
-#else
     st->print("MOV    Rtemp, #PollAddr\t! Load Polling address\n\t");
     st->print("LDR    Rtemp,[Rtemp]\t!Poll for Safepointing");
-#endif
   }
 }
 #endif
@@ -390,36 +351,15 @@
 
   // If this does safepoint polling, then do it here
   if (do_polling() && ra_->C->is_method_compilation()) {
-#ifdef AARCH64
-    if (false && MacroAssembler::page_reachable_from_cache(os::get_polling_page())) {
-/* FIXME: TODO
-      __ relocate(relocInfo::xxx);
-      __ adrp(Rtemp, (intptr_t)os::get_polling_page());
-      __ relocate(relocInfo::poll_return_type);
-      int offset = os::get_polling_page() & 0xfff;
-      __ ldr(ZR, Address(Rtemp + offset));
-*/
-    } else {
-      __ mov_address(Rtemp, (address)os::get_polling_page(), symbolic_Relocation::polling_page_reference);
-      __ relocate(relocInfo::poll_return_type);
-      __ ldr(ZR, Address(Rtemp));
-    }
-#else
     // mov_slow here is usually one or two instruction
     __ mov_address(Rtemp, (address)os::get_polling_page(), symbolic_Relocation::polling_page_reference);
     __ relocate(relocInfo::poll_return_type);
     __ ldr(Rtemp, Address(Rtemp));
-#endif
   }
 }
 
 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
-#ifdef AARCH64
-  // allow for added alignment nop from mov_address bind_literal
-  return MachNode::size(ra_) + 1 * Assembler::InstructionSize;
-#else
   return MachNode::size(ra_);
-#endif
 }
 
 int MachEpilogNode::reloc() const {
@@ -451,16 +391,12 @@
 }
 
 static inline bool is_iRegLd_memhd(OptoReg::Name src_first, OptoReg::Name src_second, int offset) {
-#ifdef AARCH64
-  return is_memoryHD(offset);
-#else
   int rlo = Matcher::_regEncode[src_first];
   int rhi = Matcher::_regEncode[src_second];
   if (!((rlo&1)==0 && (rlo+1 == rhi))) {
     tty->print_cr("CAUGHT BAD LDRD/STRD");
   }
   return (rlo&1)==0 && (rlo+1 == rhi) && is_memoryHD(offset);
-#endif
 }
 
 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
@@ -549,11 +485,6 @@
                 Matcher::regName[src_first]);
 #endif
     }
-#ifdef AARCH64
-    if (src_first+1 == src_second && dst_first+1 == dst_second) {
-      return size + 4;
-    }
-#endif
     size += 4;
   }
 
@@ -722,20 +653,12 @@
       assert((src_first&1)==0 && src_first+1 == src_second, "pairs of registers must be aligned/contiguous");
       assert(src_second_rc == rc_int && dst_second_rc == rc_float, "unsupported");
       if (cbuf) {
-#ifdef AARCH64
-        __ fmov_dx(reg_to_FloatRegister_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[src_first]));
-#else
         __ fmdrr(reg_to_FloatRegister_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[src_first]), reg_to_register_object(Matcher::_regEncode[src_second]));
-#endif
 #ifndef PRODUCT
       } else if (!do_size) {
         if (size != 0) st->print("\n\t");
-#ifdef AARCH64
-        st->print("FMOV_DX   R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first));
-#else
         st->print("FMDRR   R_%s, R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first), OptoReg::regname(src_second));
 #endif
-#endif
       }
       return size + 4;
     } else {
@@ -759,20 +682,12 @@
       assert((dst_first&1)==0 && dst_first+1 == dst_second, "pairs of registers must be aligned/contiguous");
       assert(src_second_rc == rc_float && dst_second_rc == rc_int, "unsupported");
       if (cbuf) {
-#ifdef AARCH64
-        __ fmov_xd(reg_to_register_object(Matcher::_regEncode[dst_first]), reg_to_FloatRegister_object(Matcher::_regEncode[src_first]));
-#else
         __ fmrrd(reg_to_register_object(Matcher::_regEncode[dst_first]), reg_to_register_object(Matcher::_regEncode[dst_second]), reg_to_FloatRegister_object(Matcher::_regEncode[src_first]));
-#endif
 #ifndef PRODUCT
       } else if (!do_size) {
         if (size != 0) st->print("\n\t");
-#ifdef AARCH64
-        st->print("FMOV_XD R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(src_first));
-#else
         st->print("FMRRD   R_%s, R_%s, R_%s\t! spill",OptoReg::regname(dst_first), OptoReg::regname(dst_second), OptoReg::regname(src_first));
 #endif
-#endif
       }
       return size + 4;
     } else {
@@ -795,7 +710,6 @@
     return size;               // Self copy; no move
   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
 
-#ifndef AARCH64
   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
   // 32-bits of a 64-bit register, but are needed in low bits of another
   // register (else it's a hi-bits-to-hi-bits copy which should have
@@ -852,7 +766,6 @@
     }
     return size + 4;
   }
-#endif
 
   Unimplemented();
   return 0; // Mute compiler
@@ -910,11 +823,7 @@
     __ add(dst, SP, offset);
   } else {
     __ mov_slow(dst, offset);
-#ifdef AARCH64
-    __ add(dst, SP, dst, ex_lsl);
-#else
     __ add(dst, SP, dst);
-#endif
   }
 }
 
@@ -926,11 +835,7 @@
 
 //=============================================================================
 #ifndef PRODUCT
-#ifdef AARCH64
-#define R_RTEMP "R_R16"
-#else
 #define R_RTEMP "R_R12"
-#endif
 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
   st->print_cr("\nUEP:");
   if (UseCompressedClassPointers) {
@@ -952,14 +857,7 @@
 
   __ load_klass(Rtemp, receiver);
   __ cmp(Rtemp, iCache);
-#ifdef AARCH64
-  Label match;
-  __ b(match, eq);
-  __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, Rtemp);
-  __ bind(match);
-#else
   __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
-#endif
 }
 
 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
@@ -1005,24 +903,12 @@
   int offset = __ offset();
   address deopt_pc = __ pc();
 
-#ifdef AARCH64
-  // See LR saved by caller in sharedRuntime_arm.cpp
-  // see also hse1 ws
-  // see also LIR_Assembler::emit_deopt_handler
-
-  __ raw_push(LR, LR); // preserve LR in both slots
-  __ mov_relative_address(LR, deopt_pc);
-  __ str(LR, Address(SP, 1 * wordSize)); // save deopt PC
-  // OK to kill LR, because deopt blob will restore it from SP[0]
-  __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, LR_tmp);
-#else
   __ sub(SP, SP, wordSize); // make room for saved PC
   __ push(LR); // save LR that may be live when we get here
   __ mov_relative_address(LR, deopt_pc);
   __ str(LR, Address(SP, wordSize)); // save deopt PC
   __ pop(LR); // restore LR
   __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
-#endif
 
   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 
@@ -1073,21 +959,13 @@
   case Op_AddVF:
   case Op_SubVF:
   case Op_MulVF:
-#ifdef AARCH64
-    return VM_Version::has_simd();
-#else
     return VM_Version::has_vfp() || VM_Version::has_simd();
-#endif
   case Op_AddVD:
   case Op_SubVD:
   case Op_MulVD:
   case Op_DivVF:
   case Op_DivVD:
-#ifdef AARCH64
-    return VM_Version::has_simd();
-#else
     return VM_Version::has_vfp();
-#endif
   }
 
   return true;  // Per default match rules are supported.
@@ -1158,11 +1036,7 @@
 }
 
 const bool Matcher::convL2FSupported(void) {
-#ifdef AARCH64
-  return true;
-#else
   return false;
-#endif
 }
 
 // Is this branch offset short enough that a short branch can be used?
@@ -1181,29 +1055,17 @@
 
 const bool Matcher::isSimpleConstant64(jlong value) {
   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
-#ifdef AARCH64
-  return (value == 0);
-#else
   return false;
-#endif
 }
 
 // No scaling for the parameter the ClearArray node.
 const bool Matcher::init_array_count_is_in_bytes = true;
 
-#ifdef AARCH64
-const int Matcher::long_cmove_cost() { return 1; }
-#else
 // Needs 2 CMOV's for longs.
 const int Matcher::long_cmove_cost() { return 2; }
-#endif
-
-#ifdef AARCH64
-const int Matcher::float_cmove_cost() { return 1; }
-#else
+
 // CMOVF/CMOVD are expensive on ARM.
 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
-#endif
 
 // Does the CPU require late expand (see block.cpp for description of late expand)?
 const bool Matcher::require_postalloc_expand = false;
@@ -1211,11 +1073,7 @@
 // Do we need to mask the count passed to shift instructions or does
 // the cpu only look at the lower 5/6 bits anyway?
 // FIXME: does this handle vector shifts as well?
-#ifdef AARCH64
-const bool Matcher::need_masked_shift_count = false;
-#else
 const bool Matcher::need_masked_shift_count = true;
-#endif
 
 const bool Matcher::convi2l_type_required = true;
 
@@ -1261,14 +1119,7 @@
 // needed.  Else we split the double into 2 integer pieces and move it
 // piece-by-piece.  Only happens when passing doubles into C code as the
 // Java calling convention forces doubles to be aligned.
-#ifdef AARCH64
-// On stack replacement support:
-// We don't need Load[DL]_unaligned support, because interpreter stack
-// has correct alignment
-const bool Matcher::misaligned_doubles_ok = true;
-#else
 const bool Matcher::misaligned_doubles_ok = false;
-#endif
 
 // No-op on ARM.
 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
@@ -1300,10 +1151,6 @@
 // Registers not mentioned will be killed by the VM call in the trampoline, and
 // arguments in those registers not be available to the callee.
 bool Matcher::can_be_java_arg( int reg ) {
-#ifdef AARCH64
-  if (reg >= R_R0_num && reg < R_R8_num) return true;
-  if (reg >= R_V0_num && reg <= R_V7b_num && ((reg & 3) < 2)) return true;
-#else
   if (reg == R_R0_num ||
       reg == R_R1_num ||
       reg == R_R2_num ||
@@ -1311,7 +1158,6 @@
 
   if (reg >= R_S0_num &&
       reg <= R_S13_num) return true;
-#endif
   return false;
 }
 
@@ -1454,44 +1300,14 @@
     Register R8_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
     assert(R8_ic_reg == Ricklass, "should be");
     __ set_inst_mark();
-#ifdef AARCH64
-// TODO: see C1 LIR_Assembler::ic_call()
-    InlinedAddress oop_literal((address)Universe::non_oop_word());
-    int offset = __ offset();
-    int fixed_size = mov_oop_size * 4;
-    if (VM_Version::prefer_moves_over_load_literal()) {
-      uintptr_t val = (uintptr_t)Universe::non_oop_word();
-      __ movz(R8_ic_reg, (val >>  0) & 0xffff,  0);
-      __ movk(R8_ic_reg, (val >> 16) & 0xffff, 16);
-      __ movk(R8_ic_reg, (val >> 32) & 0xffff, 32);
-      __ movk(R8_ic_reg, (val >> 48) & 0xffff, 48);
-    } else {
-      __ ldr_literal(R8_ic_reg, oop_literal);
-    }
-    assert(__ offset() - offset == fixed_size, "bad mov_oop size");
-#else
     __ movw(R8_ic_reg, ((unsigned int)Universe::non_oop_word()) & 0xffff);
     __ movt(R8_ic_reg, ((unsigned int)Universe::non_oop_word()) >> 16);
-#endif
     address  virtual_call_oop_addr = __ inst_mark();
     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
     // who we intended to call.
     int method_index = resolved_method_index(cbuf);
     __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
     emit_call_reloc(cbuf, as_MachCall(), $meth, RelocationHolder::none);
-#ifdef AARCH64
-    if (!VM_Version::prefer_moves_over_load_literal()) {
-      Label skip_literal;
-      __ b(skip_literal);
-      int off2 = __ offset();
-      __ bind_literal(oop_literal);
-      if (__ offset() - off2 == wordSize) {
-        // no padding, so insert nop for worst-case sizing
-        __ nop();
-      }
-      __ bind(skip_literal);
-    }
-#endif
   %}
 
   enc_class LdReplImmI(immI src, regD dst, iRegI tmp, int cnt, int wth) %{
@@ -1558,16 +1374,8 @@
     // See if the lengths are different, and calculate min in str1_reg.
     // Stash diff in tmp2 in case we need it for a tie-breaker.
     __ subs_32(tmp2_reg, cnt1_reg, cnt2_reg);
-#ifdef AARCH64
-    Label Lskip;
-    __ _lsl_w(cnt1_reg, cnt1_reg, exact_log2(sizeof(jchar))); // scale the limit
-    __ b(Lskip, mi);
-    __ _lsl_w(cnt1_reg, cnt2_reg, exact_log2(sizeof(jchar))); // scale the limit
-    __ bind(Lskip);
-#else
     __ mov(cnt1_reg, AsmOperand(cnt1_reg, lsl, exact_log2(sizeof(jchar)))); // scale the limit
     __ mov(cnt1_reg, AsmOperand(cnt2_reg, lsl, exact_log2(sizeof(jchar))), pl); // scale the limit
-#endif
 
     // reallocate cnt1_reg, cnt2_reg, result_reg
     // Note:  limit_reg holds the string length pre-scaled by 2
@@ -1717,16 +1525,6 @@
     int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
 
     // return true if the same array
-#ifdef AARCH64
-    __ cmp(ary1_reg, ary2_reg);
-    __ b(Lequal, eq);
-
-    __ mov(result_reg, 0);
-
-    __ cbz(ary1_reg, Ldone); // not equal
-
-    __ cbz(ary2_reg, Ldone); // not equal
-#else
     __ teq(ary1_reg, ary2_reg);
     __ mov(result_reg, 1, eq);
     __ b(Ldone, eq); // equal
@@ -1738,19 +1536,12 @@
     __ tst(ary2_reg, ary2_reg);
     __ mov(result_reg, 0, eq);
     __ b(Ldone, eq);    // not equal
-#endif
 
     //load the lengths of arrays
     __ ldr_s32(tmp1_reg, Address(ary1_reg, length_offset)); // int
     __ ldr_s32(tmp2_reg, Address(ary2_reg, length_offset)); // int
 
     // return false if the two arrays are not equal length
-#ifdef AARCH64
-    __ cmp_w(tmp1_reg, tmp2_reg);
-    __ b(Ldone, ne);    // not equal
-
-    __ cbz_w(tmp1_reg, Lequal); // zero-length arrays are equal
-#else
     __ teq_32(tmp1_reg, tmp2_reg);
     __ mov(result_reg, 0, ne);
     __ b(Ldone, ne);    // not equal
@@ -1758,7 +1549,6 @@
     __ tst(tmp1_reg, tmp1_reg);
     __ mov(result_reg, 1, eq);
     __ b(Ldone, eq);    // zero-length arrays are equal
-#endif
 
     // load array addresses
     __ add(ary1_reg, ary1_reg, base_offset);
@@ -1852,11 +1642,7 @@
   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 
   // Compiled code's Frame Pointer
-#ifdef AARCH64
-  frame_pointer(R_SP);
-#else
   frame_pointer(R_R13);
-#endif
 
   // Stack alignment requirement
   stack_alignment(StackAlignmentInBytes);
@@ -1953,7 +1739,6 @@
   interface(CONST_INTER);
 %}
 
-#ifndef AARCH64
 // Integer Immediate: offset for half and double word loads and stores
 operand immIHD() %{
   predicate(is_memoryHD(n->get_int()));
@@ -1972,7 +1757,6 @@
   format %{ %}
   interface(CONST_INTER);
 %}
-#endif
 
 // Valid scale values for addressing modes and shifts
 operand immU5() %{
@@ -2183,45 +1967,6 @@
   interface(CONST_INTER);
 %}
 
-#ifdef AARCH64
-// Long Immediate: for logical instruction
-operand limmL() %{
-  predicate(is_limmL(n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand limmLn() %{
-  predicate(is_limmL(~n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Long Immediate: for arithmetic instruction
-operand aimmL() %{
-  predicate(is_aimm(n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand aimmLneg() %{
-  predicate(is_aimm(-n->get_long()));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-#endif // AARCH64
 
 // Long Immediate: the value FF
 operand immL_FF() %{
@@ -2404,11 +2149,7 @@
   match(R1RegI);
   match(R2RegI);
   match(R3RegI);
-#ifdef AARCH64
-  match(ZRRegI);
-#else
   match(R12RegI);
-#endif
 
   format %{ %}
   interface(REG_INTER);
@@ -2446,49 +2187,6 @@
   interface(REG_INTER);
 %}
 
-#ifdef AARCH64
-// Like sp_ptr_reg, but exclude regs (Aarch64 SP) that can't be
-// stored directly.  Includes ZR, so can't be used as a destination.
-operand store_ptr_RegP() %{
-  constraint(ALLOC_IN_RC(store_ptr_reg));
-  match(RegP);
-  match(iRegP);
-  match(ZRRegP);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegI() %{
-  constraint(ALLOC_IN_RC(store_reg));
-  match(RegI);
-  match(iRegI);
-  match(ZRRegI);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegL() %{
-  constraint(ALLOC_IN_RC(store_ptr_reg));
-  match(RegL);
-  match(iRegL);
-  match(ZRRegL);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand store_RegN() %{
-  constraint(ALLOC_IN_RC(store_reg));
-  match(RegN);
-  match(iRegN);
-  match(ZRRegN);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-#endif
 
 operand R0RegP() %{
   constraint(ALLOC_IN_RC(R0_regP));
@@ -2578,7 +2276,6 @@
   interface(REG_INTER);
 %}
 
-#ifndef AARCH64
 operand R12RegI() %{
   constraint(ALLOC_IN_RC(R12_regI));
   match(iRegI);
@@ -2586,18 +2283,13 @@
   format %{ %}
   interface(REG_INTER);
 %}
-#endif
 
 // Long Register
 operand iRegL() %{
   constraint(ALLOC_IN_RC(long_reg));
   match(RegL);
-#ifdef AARCH64
-  match(iRegLd);
-#else
   match(R0R1RegL);
   match(R2R3RegL);
-#endif
 //match(iRegLex);
 
   format %{ %}
@@ -2612,7 +2304,6 @@
   interface(REG_INTER);
 %}
 
-#ifndef AARCH64
 // first long arg, or return value
 operand R0R1RegL() %{
   constraint(ALLOC_IN_RC(R0R1_regL));
@@ -2629,7 +2320,6 @@
   format %{ %}
   interface(REG_INTER);
 %}
-#endif
 
 // Condition Code Flag Register
 operand flagsReg() %{
@@ -2671,7 +2361,6 @@
 %}
 
 // Condition Code Register, long comparisons.
-#ifndef AARCH64
 operand flagsRegL_LTGE() %{
   constraint(ALLOC_IN_RC(int_flags));
   match(RegFlags);
@@ -2719,7 +2408,6 @@
   format %{ "apsr_UL_LEGT" %}
   interface(REG_INTER);
 %}
-#endif
 
 // Condition Code Register, floating comparisons, unordered same as "less".
 operand flagsRegF() %{
@@ -2800,19 +2488,15 @@
   format %{ "[$reg]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp(0x0);
   %}
 %}
 
-#ifdef AARCH64
-// Indirect with scaled*1 uimm12 offset
-operand indOffsetU12ScaleB(sp_ptr_RegP reg, immUL12 offset) %{
+
+// Indirect with Offset in ]-4096, 4096[
+operand indOffset12(sp_ptr_RegP reg, immI12 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2820,18 +2504,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*2 uimm12 offset
-operand indOffsetU12ScaleS(sp_ptr_RegP reg, immUL12x2 offset) %{
+// Indirect with offset for float load/store
+operand indOffsetFP(sp_ptr_RegP reg, immIFP offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2839,18 +2519,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*4 uimm12 offset
-operand indOffsetU12ScaleI(sp_ptr_RegP reg, immUL12x4 offset) %{
+// Indirect with Offset for half and double words
+operand indOffsetHD(sp_ptr_RegP reg, immIHD offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2858,18 +2534,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*8 uimm12 offset
-operand indOffsetU12ScaleL(sp_ptr_RegP reg, immUL12x8 offset) %{
+// Indirect with Offset and Offset+4 in ]-1024, 1024[
+operand indOffsetFPx2(sp_ptr_RegP reg, immX10x2 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2877,18 +2549,14 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-// Indirect with scaled*16 uimm12 offset
-operand indOffsetU12ScaleQ(sp_ptr_RegP reg, immUL12x16 offset) %{
+// Indirect with Offset and Offset+4 in ]-4096, 4096[
+operand indOffset12x2(sp_ptr_RegP reg, immI12x2 offset) %{
   constraint(ALLOC_IN_RC(sp_ptr_reg));
   match(AddP reg offset);
 
@@ -2896,114 +2564,12 @@
   format %{ "[$reg + $offset]" %}
   interface(MEMORY_INTER) %{
     base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
     index(0xf); // PC => no index
-#endif
     scale(0x0);
     disp($offset);
   %}
 %}
 
-#else // ! AARCH64
-
-// Indirect with Offset in ]-4096, 4096[
-operand indOffset12(sp_ptr_RegP reg, immI12 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with offset for float load/store
-operand indOffsetFP(sp_ptr_RegP reg, immIFP offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset for half and double words
-operand indOffsetHD(sp_ptr_RegP reg, immIHD offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset and Offset+4 in ]-1024, 1024[
-operand indOffsetFPx2(sp_ptr_RegP reg, immX10x2 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-
-// Indirect with Offset and Offset+4 in ]-4096, 4096[
-operand indOffset12x2(sp_ptr_RegP reg, immI12x2 offset) %{
-  constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(AddP reg offset);
-
-  op_cost(100);
-  format %{ "[$reg + $offset]" %}
-  interface(MEMORY_INTER) %{
-    base($reg);
-#ifdef AARCH64
-    index(0xff); // 0xff => no index
-#else
-    index(0xf); // PC => no index
-#endif
-    scale(0x0);
-    disp($offset);
-  %}
-%}
-#endif // !AARCH64
-
 // Indirect with Register Index
 operand indIndex(iRegP addr, iRegX index) %{
   constraint(ALLOC_IN_RC(ptr_reg));
@@ -3019,9 +2585,8 @@
   %}
 %}
 
-#ifdef AARCH64
 // Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleS(iRegP addr, iRegX index, immI_1 scale) %{
+operand indIndexScale(iRegP addr, iRegX index, immU5 scale) %{
   constraint(ALLOC_IN_RC(ptr_reg));
   match(AddP addr (LShiftX index scale));
 
@@ -3035,127 +2600,6 @@
   %}
 %}
 
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleS(iRegP addr, iRegI index, immI_1 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleI(iRegP addr, iRegX index, immI_2 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleI(iRegP addr, iRegI index, immI_2 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleL(iRegP addr, iRegX index, immI_3 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleL(iRegP addr, iRegI index, immI_3 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScaleQ(iRegP addr, iRegX index, immI_4 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-
-// Indirect Memory Times Scale Plus 32-bit Index Register
-operand indIndexIScaleQ(iRegP addr, iRegI index, immI_4 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX (ConvI2L index) scale));
-
-  op_cost(100);
-  format %{"[$addr + $index.w << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x7fffffff); // sxtw
-  %}
-%}
-#else
-// Indirect Memory Times Scale Plus Index Register
-operand indIndexScale(iRegP addr, iRegX index, immU5 scale) %{
-  constraint(ALLOC_IN_RC(ptr_reg));
-  match(AddP addr (LShiftX index scale));
-
-  op_cost(100);
-  format %{"[$addr + $index << $scale]" %}
-  interface(MEMORY_INTER) %{
-    base($addr);
-    index($index);
-    scale($scale);
-    disp(0x0);
-  %}
-%}
-#endif
-
 // Operands for expressing Control Flow
 // NOTE:  Label is a predefined operand which should not be redefined in
 //        the AD file.  It is generically handled within the ADLC.
@@ -3312,29 +2756,6 @@
 // instructions for every form of operand when the instruction accepts
 // multiple operand types with the same basic encoding and format.  The classic
 // case of this is memory operands.
-#ifdef AARCH64
-opclass memoryB(indirect, indIndex, indOffsetU12ScaleB);
-opclass memoryS(indirect, indIndex, indIndexScaleS, indIndexIScaleS, indOffsetU12ScaleS);
-opclass memoryI(indirect, indIndex, indIndexScaleI, indIndexIScaleI, indOffsetU12ScaleI);
-opclass memoryL(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-opclass memoryP(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-opclass memoryQ(indirect, indIndex, indIndexScaleQ, indIndexIScaleQ, indOffsetU12ScaleQ);
-opclass memoryF(indirect, indIndex, indIndexScaleI, indIndexIScaleI, indOffsetU12ScaleI);
-opclass memoryD(indirect, indIndex, indIndexScaleL, indIndexIScaleL, indOffsetU12ScaleL);
-
-opclass memoryScaledS(indIndexScaleS, indIndexIScaleS);
-opclass memoryScaledI(indIndexScaleI, indIndexIScaleI);
-opclass memoryScaledL(indIndexScaleL, indIndexIScaleL);
-opclass memoryScaledP(indIndexScaleL, indIndexIScaleL);
-opclass memoryScaledQ(indIndexScaleQ, indIndexIScaleQ);
-opclass memoryScaledF(indIndexScaleI, indIndexIScaleI);
-opclass memoryScaledD(indIndexScaleL, indIndexIScaleL);
-// when ldrex/strex is used:
-opclass memoryex ( indirect );
-opclass indIndexMemory( indIndex );
-opclass memoryvld ( indirect /* , write back mode not implemented */ );
-
-#else
 
 opclass memoryI ( indirect, indOffset12, indIndex, indIndexScale );
 opclass memoryP ( indirect, indOffset12, indIndex, indIndexScale );
@@ -3354,7 +2775,6 @@
 opclass indIndexMemory( indIndex );
 opclass memorylong ( indirect, indOffset12x2 );
 opclass memoryvld ( indirect /* , write back mode not implemented */ );
-#endif
 
 //----------PIPELINE-----------------------------------------------------------
 pipeline %{
@@ -4163,7 +3583,6 @@
   size(4);
   format %{ "LDRSB   $dst,$mem\t! byte -> int" %}
   ins_encode %{
-    // High 32 bits are harmlessly set on Aarch64
     __ ldrsb($dst$$Register, $mem$$Address);
   %}
   ins_pipe(iload_mask_mem);
@@ -4174,13 +3593,6 @@
   match(Set dst (ConvI2L (LoadB mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRSB $dst,$mem\t! byte -> long"  %}
-  ins_encode %{
-    __ ldrsb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRSB $dst.lo,$mem\t! byte -> long\n\t"
             "ASR   $dst.hi,$dst.lo,31" %}
@@ -4188,7 +3600,6 @@
     __ ldrsb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
@@ -4210,13 +3621,6 @@
   match(Set dst (ConvI2L (LoadUB mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRB  $dst,$mem\t! ubyte -> long"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRB  $dst.lo,$mem\t! ubyte -> long\n\t"
             "MOV   $dst.hi,0" %}
@@ -4224,7 +3628,6 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4232,16 +3635,6 @@
 instruct loadUB2L_limmI(iRegL dst, memoryB mem, limmIlow8 mask) %{
   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
 
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST);
-  size(8);
-  format %{ "LDRB  $dst,$mem\t! ubyte -> long\n\t"
-            "AND  $dst,$dst,$mask" %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, limmI_low($mask$$constant, 8));
-  %}
-#else
   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
   size(12);
   format %{ "LDRB  $dst.lo,$mem\t! ubyte -> long\n\t"
@@ -4252,29 +3645,10 @@
     __ mov($dst$$Register->successor(), 0);
     __ andr($dst$$Register, $dst$$Register, limmI_low($mask$$constant, 8));
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Short (16bit signed)
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadSoff(iRegI dst, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadS (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDRSH   $dst,$mem+$off\t! short temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldrsh($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mask_mem);
-%}
-#endif
 
 instruct loadS(iRegI dst, memoryS mem) %{
   match(Set dst (LoadS mem));
@@ -4297,7 +3671,6 @@
 
   format %{ "LDRSB   $dst,$mem\t! short -> byte" %}
   ins_encode %{
-    // High 32 bits are harmlessly set on Aarch64
     __ ldrsb($dst$$Register, $mem$$Address);
   %}
   ins_pipe(iload_mask_mem);
@@ -4308,13 +3681,6 @@
   match(Set dst (ConvI2L (LoadS mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRSH $dst,$mem\t! short -> long"  %}
-  ins_encode %{
-    __ ldrsh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRSH $dst.lo,$mem\t! short -> long\n\t"
             "ASR   $dst.hi,$dst.lo,31" %}
@@ -4322,30 +3688,11 @@
     __ ldrsh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
 // Load Unsigned Short/Char (16bit UNsigned)
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadUSoff(iRegI dst, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadUS (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDRH   $dst,$mem+$off\t! ushort/char temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldrh($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadUS(iRegI dst, memoryS mem) %{
   match(Set dst (LoadUS mem));
@@ -4377,13 +3724,6 @@
   match(Set dst (ConvI2L (LoadUS mem)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRH  $dst,$mem\t! short -> long"  %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRH  $dst.lo,$mem\t! short -> long\n\t"
             "MOV   $dst.hi, 0" %}
@@ -4391,7 +3731,6 @@
     __ ldrh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4400,13 +3739,6 @@
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRB  $dst,$mem"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRB  $dst.lo,$mem\t! \n\t"
             "MOV   $dst.hi, 0" %}
@@ -4414,24 +3746,12 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Unsigned Short/Char (16bit UNsigned) with a immediate mask into a Long Register
 instruct loadUS2L_limmI(iRegL dst, memoryS mem, limmI mask) %{
   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST + 1*DEFAULT_COST);
-
-  size(8);
-  format %{ "LDRH   $dst,$mem\t! ushort/char & mask -> long\n\t"
-            "AND    $dst,$dst,$mask" %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, (uintx)$mask$$constant);
-  %}
-#else
   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
 
   size(12);
@@ -4443,30 +3763,11 @@
     __ mov($dst$$Register->successor(), 0);
     __ andr($dst$$Register, $dst$$Register, $mask$$constant);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Integer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadIoff(iRegI dst, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadI (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr_s32 $dst,$mem+$off\t! int temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_s32($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadI(iRegI dst, memoryI mem) %{
   match(Set dst (LoadI mem));
@@ -4537,15 +3838,6 @@
 // Load Integer into a Long Register
 instruct loadI2L(iRegL dst, memoryI mem) %{
   match(Set dst (ConvI2L (LoadI mem)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST);
-
-  size(4);
-  format %{ "LDRSW $dst.lo,$mem\t! int -> long"  %}
-  ins_encode %{
-    __ ldr_s32($dst$$Register, $mem$$Address);
-  %}
-#else
   ins_cost(MEMORY_REF_COST);
 
   size(8);
@@ -4555,22 +3847,12 @@
     __ ldr($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), AsmOperand($dst$$Register, asr, 31));
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
 // Load Integer with mask 0xFF into a Long Register
 instruct loadI2L_immI_255(iRegL dst, memoryB mem, immI_255 mask) %{
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-#ifdef AARCH64
-  ins_cost(MEMORY_REF_COST);
-
-  size(4);
-  format %{ "LDRB   $dst.lo,$mem\t! int & 0xFF -> long"  %}
-  ins_encode %{
-    __ ldrb($dst$$Register, $mem$$Address);
-  %}
-#else
   ins_cost(MEMORY_REF_COST);
 
   size(8);
@@ -4580,7 +3862,6 @@
     __ ldrb($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
@@ -4589,13 +3870,6 @@
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LDRH   $dst,$mem\t! int & 0xFFFF -> long" %}
-  ins_encode %{
-    __ ldrh($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDRH   $dst,$mem\t! int & 0xFFFF -> long\n\t"
             "MOV    $dst.hi, 0" %}
@@ -4603,27 +3877,9 @@
     __ ldrh($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mask_mem);
 %}
 
-#ifdef AARCH64
-// Load Integer with an immediate mask into a Long Register
-instruct loadI2L_limmI(iRegL dst, memoryI mem, limmI mask) %{
-  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-  ins_cost(MEMORY_REF_COST + 1*DEFAULT_COST);
-
-  size(8);
-  format %{ "LDRSW $dst,$mem\t! int -> long\n\t"
-            "AND   $dst,$dst,$mask" %}
-
-  ins_encode %{
-    __ ldr_s32($dst$$Register, $mem$$Address);
-    __ andr($dst$$Register, $dst$$Register, (uintx)$mask$$constant);
-  %}
-  ins_pipe(iload_mem);
-%}
-#else
 // Load Integer with a 31-bit immediate mask into a Long Register
 instruct loadI2L_limmU31(iRegL dst, memoryI mem, limmU31 mask) %{
   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
@@ -4641,27 +3897,7 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
-
-#ifdef AARCH64
-// Load Integer with mask into a Long Register
-// FIXME: use signedRegI mask, remove tmp?
-instruct loadI2L_immI(iRegL dst, memoryI mem, immI mask, iRegI tmp) %{
-  match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
-  effect(TEMP dst, TEMP tmp);
-
-  ins_cost(MEMORY_REF_COST + 3*DEFAULT_COST);
-  format %{ "LDRSW    $mem,$dst\t! int & 31-bit mask -> long\n\t"
-            "MOV_SLOW $tmp,$mask\n\t"
-            "AND      $dst,$tmp,$dst" %}
-  ins_encode %{
-    __ ldrsw($dst$$Register, $mem$$Address);
-    __ mov_slow($tmp$$Register, $mask$$constant);
-    __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
-  %}
-  ins_pipe(iload_mem);
-%}
-#else
+
 // Load Integer with a 31-bit mask into a Long Register
 // FIXME: use iRegI mask, remove tmp?
 instruct loadI2L_immU31(iRegL dst, memoryI mem, immU31 mask, iRegI tmp) %{
@@ -4682,20 +3918,12 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
 
 // Load Unsigned Integer into a Long Register
 instruct loadUI2L(iRegL dst, memoryI mem, immL_32bits mask) %{
   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
   ins_cost(MEMORY_REF_COST);
 
-#ifdef AARCH64
-//size(4);
-  format %{ "LDR_w $dst,$mem\t! uint -> long" %}
-  ins_encode %{
-    __ ldr_w($dst$$Register, $mem$$Address);
-  %}
-#else
   size(8);
   format %{ "LDR   $dst.lo,$mem\t! uint -> long\n\t"
             "MOV   $dst.hi,0" %}
@@ -4703,37 +3931,14 @@
     __ ldr($dst$$Register, $mem$$Address);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(iload_mem);
 %}
 
 // Load Long
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadLoff(iRegLd dst, memoryScaledL mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadL (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDR    $dst,$mem+$off\t! long temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadL(iRegLd dst, memoryL mem ) %{
-#ifdef AARCH64
-  // already atomic for Aarch64
-#else
   predicate(!((LoadLNode*)n)->require_atomic_access());
-#endif
   match(Set dst (LoadL mem));
   effect(TEMP dst);
   ins_cost(MEMORY_REF_COST);
@@ -4746,7 +3951,6 @@
   ins_pipe(iload_mem);
 %}
 
-#ifndef AARCH64
 instruct loadL_2instr(iRegL dst, memorylong mem ) %{
   predicate(!((LoadLNode*)n)->require_atomic_access());
   match(Set dst (LoadL mem));
@@ -4822,7 +4026,6 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif // !AARCH64
 
 // Load Range
 instruct loadRange(iRegI dst, memoryI mem) %{
@@ -4839,24 +4042,6 @@
 
 // Load Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadPoff(iRegP dst, memoryScaledP mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadP (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "LDR    $dst,$mem+$off\t! ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr($dst$$Register, nmem);
-  %}
-  ins_pipe(iload_mem);
-%}
-#endif
 
 instruct loadP(iRegP dst, memoryP mem) %{
   match(Set dst (LoadP mem));
@@ -4950,24 +4135,6 @@
 %}
 #endif
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadDoff(regD dst, memoryScaledD mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadD (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr    $dst,$mem+$off\t! double temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_d($dst$$FloatRegister, nmem);
-  %}
-  ins_pipe(floadD_mem);
-%}
-#endif
 
 instruct loadD(regD dst, memoryD mem) %{
   match(Set dst (LoadD mem));
@@ -4983,7 +4150,6 @@
   ins_pipe(floadD_mem);
 %}
 
-#ifndef AARCH64
 // Load Double - UNaligned
 instruct loadD_unaligned(regD_low dst, memoryF2 mem ) %{
   match(Set dst (LoadD_unaligned mem));
@@ -4999,26 +4165,7 @@
   %}
   ins_pipe(iload_mem);
 %}
-#endif
-
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct loadFoff(regF dst, memoryScaledF mem, aimmX off, iRegP tmp) %{
-  match(Set dst (LoadF (AddP mem off)));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "ldr    $dst,$mem+$off\t! float temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ ldr_s($dst$$FloatRegister, nmem);
-  %}
-  ins_pipe(floadF_mem);
-%}
-#endif
+
 
 instruct loadF(regF dst, memoryF mem) %{
   match(Set dst (LoadF mem));
@@ -5032,17 +4179,6 @@
   ins_pipe(floadF_mem);
 %}
 
-#ifdef AARCH64
-instruct load_limmI(iRegI dst, limmI src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST + 1); // + 1 because MOV is preferred
-  format %{ "ORR_w  $dst, ZR, $src\t! int"  %}
-  ins_encode %{
-    __ orr_w($dst$$Register, ZR, (uintx)$src$$constant);
-  %}
-  ins_pipe(ialu_imm);
-%}
-#endif
 
 // // Load Constant
 instruct loadConI( iRegI dst, immI src ) %{
@@ -5065,7 +4201,6 @@
   ins_pipe(ialu_imm);
 %}
 
-#ifndef AARCH64
 instruct loadConIMovn( iRegI dst, immIRotn src ) %{
   match(Set dst src);
   size(4);
@@ -5075,22 +4210,13 @@
   %}
   ins_pipe(ialu_imm_n);
 %}
-#endif
 
 instruct loadConI16( iRegI dst, immI16 src ) %{
   match(Set dst src);
   size(4);
-#ifdef AARCH64
-  format %{ "MOVZ_w  $dst, $src" %}
-#else
   format %{ "MOVW    $dst, $src" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov_w($dst$$Register, $src$$constant);
-#else
+  ins_encode %{
     __ movw($dst$$Register, $src$$constant);
-#endif
   %}
   ins_pipe(ialu_imm_n);
 %}
@@ -5124,80 +4250,6 @@
   ins_pipe(loadConP_poll);
 %}
 
-#ifdef AARCH64
-instruct loadConP0(iRegP dst, immP0 src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst,ZR\t!ptr" %}
-  ins_encode %{
-    __ mov($dst$$Register, ZR);
-  %}
-  ins_pipe(ialu_none);
-%}
-
-instruct loadConN(iRegN dst, immN src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 3/2);
-  format %{ "SET    $dst,$src\t! compressed ptr" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    // FIXME: use $constanttablebase?
-    __ set_narrow_oop(dst, (jobject)$src$$constant);
-  %}
-  ins_pipe(ialu_hi_lo_reg);
-%}
-
-instruct loadConN0(iRegN dst, immN0 src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst,ZR\t! compressed ptr" %}
-  ins_encode %{
-    __ mov($dst$$Register, ZR);
-  %}
-  ins_pipe(ialu_none);
-%}
-
-instruct loadConNKlass(iRegN dst, immNKlass src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 3/2);
-  format %{ "SET    $dst,$src\t! compressed klass ptr" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    // FIXME: use $constanttablebase?
-    __ set_narrow_klass(dst, (Klass*)$src$$constant);
-  %}
-  ins_pipe(ialu_hi_lo_reg);
-%}
-
-instruct load_limmL(iRegL dst, limmL src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "ORR    $dst, ZR, $src\t! long"  %}
-  ins_encode %{
-    __ orr($dst$$Register, ZR, (uintx)$src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-instruct load_immLMov(iRegL dst, immLMov src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST);
-  format %{ "MOV    $dst, $src\t! long"  %}
-  ins_encode %{
-    __ mov($dst$$Register, $src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-instruct loadConL(iRegL dst, immL src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 4); // worst case
-  format %{ "mov_slow   $dst, $src\t! long"  %}
-  ins_encode %{
-    // FIXME: use $constanttablebase?
-    __ mov_slow($dst$$Register, $src$$constant);
-  %}
-  ins_pipe(loadConL);
-%}
-#else
 instruct loadConL(iRegL dst, immL src) %{
   match(Set dst src);
   ins_cost(DEFAULT_COST * 4);
@@ -5223,7 +4275,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct loadConF_imm8(regF dst, imm8F src) %{
   match(Set dst src);
@@ -5238,25 +4289,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifdef AARCH64
-instruct loadIConF(iRegI dst, immF src) %{
-  match(Set dst src);
-  ins_cost(DEFAULT_COST * 2);
-
-  format %{ "MOV_SLOW  $dst, $src\t! loadIConF"  %}
-
-  ins_encode %{
-    // FIXME revisit once 6961697 is in
-    union {
-      jfloat f;
-      int i;
-    } v;
-    v.f = $src$$constant;
-    __ mov_slow($dst$$Register, v.i);
-  %}
-  ins_pipe(ialu_imm);
-%}
-#endif
 
 instruct loadConF(regF dst, immF src, iRegI tmp) %{
   match(Set dst src);
@@ -5323,11 +4355,7 @@
 
   format %{ "PLDW $mem\t! Prefetch allocation" %}
   ins_encode %{
-#ifdef AARCH64
-    __ prfm(pstl1keep, $mem$$Address);
-#else
     __ pldw($mem$$Address);
-#endif
   %}
   ins_pipe(iload_mem);
 %}
@@ -5360,24 +4388,6 @@
 
 // Store Char/Short
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeCoff(store_RegI src, memoryScaledS mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreC (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STRH    $src,$mem+$off\t! short temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ strh($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeC(memoryS mem, store_RegI src) %{
   match(Set mem (StoreC mem src));
@@ -5393,24 +4403,6 @@
 
 // Store Integer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeIoff(store_RegI src, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreI (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_32 $src,$mem+$off\t! int temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_32($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeI(memoryI mem, store_RegI src) %{
   match(Set mem (StoreI mem src));
@@ -5426,31 +4418,9 @@
 
 // Store Long
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeLoff(store_RegLd src, memoryScaledL mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreL (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_64 $src,$mem+$off\t! long temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_64($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeL(memoryL mem, store_RegLd src) %{
-#ifdef AARCH64
-  // already atomic for Aarch64
-#else
   predicate(!((StoreLNode*)n)->require_atomic_access());
-#endif
   match(Set mem (StoreL mem src));
   ins_cost(MEMORY_REF_COST);
 
@@ -5463,7 +4433,6 @@
   ins_pipe(istore_mem_reg);
 %}
 
-#ifndef AARCH64
 instruct storeL_2instr(memorylong mem, iRegL src) %{
   predicate(!((StoreLNode*)n)->require_atomic_access());
   match(Set mem (StoreL mem src));
@@ -5496,9 +4465,7 @@
   %}
   ins_pipe(istore_mem_reg);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct storeL_volatile_fp(memoryD mem, iRegL src) %{
   predicate(((StoreLNode*)n)->require_atomic_access());
   match(Set mem (StoreL mem src));
@@ -5512,7 +4479,6 @@
   %}
   ins_pipe(istore_mem_reg);
 %}
-#endif
 
 #ifdef XXX
 // Move SP Pointer
@@ -5534,60 +4500,12 @@
 %}
 #endif
 
-#ifdef AARCH64
-// FIXME
-// Store SP Pointer
-instruct storeSP(memoryP mem, SPRegP src, iRegP tmp) %{
-  match(Set mem (StoreP mem src));
-  predicate(_kids[1]->_leaf->is_Proj() && _kids[1]->_leaf->as_Proj()->_con == TypeFunc::FramePtr);
-  // Multiple StoreP rules, different only in register mask.
-  // Matcher makes the last always valid.  The others will
-  // only be valid if they cost less than the last valid
-  // rule.  So cost(rule1) < cost(rule2) < cost(last)
-  // Unlike immediates, register constraints are not checked
-  // at match time.
-  ins_cost(MEMORY_REF_COST+DEFAULT_COST+4);
-  effect(TEMP tmp);
-  size(8);
-
-  format %{ "MOV    $tmp,$src\t! SP ptr\n\t"
-            "STR    $tmp,$mem\t! SP ptr" %}
-  ins_encode %{
-    assert($src$$Register == SP, "SP expected");
-    __ mov($tmp$$Register, $src$$Register);
-    __ str($tmp$$Register, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_spORreg); // FIXME
-%}
-#endif // AARCH64
 
 // Store Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storePoff(store_ptr_RegP src, memoryScaledP mem, aimmX off, iRegP tmp) %{
-  predicate(!_kids[1]->_leaf->is_Proj() || _kids[1]->_leaf->as_Proj()->_con != TypeFunc::FramePtr);
-  match(Set mem (StoreP (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STR    $src,$mem+$off\t! ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeP(memoryP mem, store_ptr_RegP src) %{
   match(Set mem (StoreP mem src));
-#ifdef AARCH64
-  predicate(!_kids[1]->_leaf->is_Proj() || _kids[1]->_leaf->as_Proj()->_con != TypeFunc::FramePtr);
-#endif
   ins_cost(MEMORY_REF_COST);
   size(4);
 
@@ -5598,42 +4516,10 @@
   ins_pipe(istore_mem_spORreg);
 %}
 
-#ifdef AARCH64
-// Store NULL Pointer
-instruct storeP0(memoryP mem, immP0 src) %{
-  match(Set mem (StoreP mem src));
-  ins_cost(MEMORY_REF_COST);
-  size(4);
-
-  format %{ "STR    ZR,$mem\t! ptr" %}
-  ins_encode %{
-    __ str(ZR, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_spORreg);
-%}
-#endif // AARCH64
 
 #ifdef _LP64
 // Store Compressed Pointer
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeNoff(store_RegN src, memoryScaledI mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreN (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_32 $src,$mem+$off\t! compressed ptr temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_32($src$$Register, nmem);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 instruct storeN(memoryI mem, store_RegN src) %{
   match(Set mem (StoreN mem src));
@@ -5647,20 +4533,6 @@
   ins_pipe(istore_mem_reg);
 %}
 
-#ifdef AARCH64
-// Store NULL Pointer
-instruct storeN0(memoryI mem, immN0 src) %{
-  match(Set mem (StoreN mem src));
-  ins_cost(MEMORY_REF_COST);
-  size(4);
-
-  format %{ "str_32 ZR,$mem\t! compressed ptr" %}
-  ins_encode %{
-    __ str_32(ZR, $mem$$Address);
-  %}
-  ins_pipe(istore_mem_reg);
-%}
-#endif
 
 // Store Compressed Klass Pointer
 instruct storeNKlass(memoryI mem, store_RegN src) %{
@@ -5678,24 +4550,6 @@
 
 // Store Double
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeDoff(regD src, memoryScaledD mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreD (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "STR    $src,$mem+$off\t! double temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_d($src$$FloatRegister, nmem);
-  %}
-  ins_pipe(fstoreD_mem_reg);
-%}
-#endif
 
 instruct storeD(memoryD mem, regD src) %{
   match(Set mem (StoreD mem src));
@@ -5711,50 +4565,9 @@
   ins_pipe(fstoreD_mem_reg);
 %}
 
-#ifdef AARCH64
-instruct movI2F(regF dst, iRegI src) %{
-  match(Set dst src);
-  size(4);
-
-  format %{ "FMOV_sw $dst,$src\t! movI2F" %}
-  ins_encode %{
-    __ fmov_sw($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-
-instruct movF2I(iRegI dst, regF src) %{
-  match(Set dst src);
-  size(4);
-
-  format %{ "FMOV_ws $dst,$src\t! movF2I" %}
-  ins_encode %{
-    __ fmov_ws($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#endif
 
 // Store Float
 
-#ifdef AARCH64
-// XXX This variant shouldn't be necessary if 6217251 is implemented
-instruct storeFoff(regF src, memoryScaledF mem, aimmX off, iRegP tmp) %{
-  match(Set mem (StoreF (AddP mem off) src));
-  ins_cost(MEMORY_REF_COST + DEFAULT_COST); // assume shift/sign-extend is free
-  effect(TEMP tmp);
-  size(4 * 2);
-
-  format %{ "str_s  $src,$mem+$off\t! float temp=$tmp" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    __ add($tmp$$Register, base, $off$$constant);
-    Address nmem = Address::make_raw($tmp$$reg, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
-    __ str_s($src$$FloatRegister, nmem);
-  %}
-  ins_pipe(fstoreF_mem_reg);
-%}
-#endif
 
 instruct storeF( memoryF mem, regF src) %{
   match(Set mem (StoreF mem src));
@@ -5768,75 +4581,10 @@
   ins_pipe(fstoreF_mem_reg);
 %}
 
-#ifdef AARCH64
-// Convert oop pointer into compressed form
-instruct encodeHeapOop(iRegN dst, iRegP src, flagsReg ccr) %{
-  predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
-  match(Set dst (EncodeP src));
-  effect(KILL ccr);
-  format %{ "encode_heap_oop $dst, $src" %}
-  ins_encode %{
-    __ encode_heap_oop($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
-  predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
-  match(Set dst (EncodeP src));
-  format %{ "encode_heap_oop_not_null $dst, $src" %}
-  ins_encode %{
-    __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeHeapOop(iRegP dst, iRegN src, flagsReg ccr) %{
-  predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
-            n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
-  match(Set dst (DecodeN src));
-  effect(KILL ccr);
-  format %{ "decode_heap_oop $dst, $src" %}
-  ins_encode %{
-    __ decode_heap_oop($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
-  predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
-            n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
-  match(Set dst (DecodeN src));
-  format %{ "decode_heap_oop_not_null $dst, $src" %}
-  ins_encode %{
-    __ decode_heap_oop_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
-  match(Set dst (EncodePKlass src));
-  format %{ "encode_klass_not_null $dst, $src" %}
-  ins_encode %{
-    __ encode_klass_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
-  match(Set dst (DecodeNKlass src));
-  format %{ "decode_klass_not_null $dst, $src" %}
-  ins_encode %{
-    __ decode_klass_not_null($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif // AARCH64
 
 //----------MemBar Instructions-----------------------------------------------
 // Memory barrier flavors
 
-// TODO: take advantage of Aarch64 load-acquire, store-release, etc
 // pattern-match out unnecessary membars
 instruct membar_storestore() %{
   match(MemBarStoreStore);
@@ -5932,53 +4680,6 @@
 // %}
 
 
-#ifdef AARCH64
-// 0 constant in register
-instruct zrImmI0(ZRRegI dst, immI0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (int 0)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-// 0 constant in register
-instruct zrImmL0(ZRRegL dst, immL0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (long 0)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-#ifdef XXX
-// 0 constant in register
-instruct zrImmN0(ZRRegN dst, immN0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (compressed pointer NULL)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-
-// 0 constant in register
-instruct zrImmP0(ZRRegP dst, immP0 imm) %{
-  match(Set dst imm);
-  size(0);
-  ins_cost(0);
-
-  format %{ "! ZR (NULL)" %}
-  ins_encode( /*empty encoding*/ );
-  ins_pipe(ialu_none);
-%}
-#endif
-#endif // AARCH64
 
 // Cast Index to Pointer for unsafe natives
 instruct castX2P(iRegX src, iRegP dst) %{
@@ -6006,7 +4707,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 //----------Conditional Move---------------------------------------------------
 // Conditional move
 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
@@ -6019,187 +4719,8 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
-
-#ifdef AARCH64
-instruct cmovI_reg3(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovL_reg3(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovP_reg3(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovN_reg3(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIP_reg3(cmpOpP cmp, flagsRegP icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLP_reg3(cmpOpP cmp, flagsRegP icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPP_reg3(cmpOpP cmp, flagsRegP icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNP_reg3(cmpOpP cmp, flagsRegP icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIU_reg3(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLU_reg3(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPU_reg3(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNU_reg3(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovIZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (CMoveI (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! int" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovLZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! long" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovPZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegP dst, iRegP src1, iRegP src2) %{
-  match(Set dst (CMoveP (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-
-instruct cmovNZ_reg3(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegN dst, iRegN src1, iRegN src2) %{
-  match(Set dst (CMoveN (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "CSEL $dst,$src1,$src2,$cmp\t! compressed ptr" %}
-  ins_encode %{
-    __ csel($dst$$Register, $src1$$Register, $src2$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif // AARCH64
-
-#ifndef AARCH64
+
+
 instruct cmovIP_immMov(cmpOpP cmp, flagsRegP pcc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
   ins_cost(140);
@@ -6221,7 +4742,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovI_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6234,20 +4754,7 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct cmovL_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
-  match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
-  ins_cost(150);
-  size(4);
-  format %{ "MOV$cmp  $dst,$src\t! long" %}
-  ins_encode %{
-    __ mov($dst$$Register, $src$$Register, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(ialu_reg);
-%}
-#endif
-
-#ifndef AARCH64
+
 instruct cmovI_immMov(cmpOp cmp, flagsReg icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   ins_cost(140);
@@ -6269,7 +4776,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovII_reg_EQNELTGE(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6286,7 +4792,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 instruct cmovII_immMov_EQNELTGE(cmpOp0 cmp, flagsReg_EQNELTGE icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
@@ -6316,7 +4821,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
@@ -6329,7 +4833,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifndef AARCH64
 instruct cmovIIu_immMov(cmpOpU cmp, flagsRegU icc, iRegI dst, immIMov src) %{
   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
   ins_cost(140);
@@ -6351,7 +4854,6 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif
 
 // Conditional move
 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
@@ -6369,17 +4871,9 @@
   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
   ins_cost(140);
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR" %}
-#else
   format %{ "MOV$cmp  $dst,$src" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6430,17 +4924,9 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6454,17 +4940,9 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
@@ -6474,112 +4952,13 @@
   ins_cost(140);
 
   size(4);
-#ifdef AARCH64
-  format %{ "MOV$cmp  $dst,ZR\t! ptr" %}
-#else
   format %{ "MOV$cmp  $dst,$src\t! ptr" %}
-#endif
-  ins_encode %{
-#ifdef AARCH64
-    __ mov($dst$$Register,             ZR, (AsmCondition)($cmp$$cmpcode));
-#else
+  ins_encode %{
     __ mov($dst$$Register, $src$$constant, (AsmCondition)($cmp$$cmpcode));
-#endif
   %}
   ins_pipe(ialu_imm);
 %}
 
-#ifdef AARCH64
-// Conditional move
-instruct cmovF_reg(cmpOp cmp, flagsReg icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovD_reg(cmpOp cmp, flagsReg icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFP_reg(cmpOpP cmp, flagsRegP icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDP_reg(cmpOpP cmp, flagsRegP icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFU_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDU_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovFZ_reg(cmpOp0 cmp, flagsReg_EQNELTGE icc, regF dst, regF src1, regF src2) %{
-  match(Set dst (CMoveF (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_s $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_s($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-instruct cmovDZ_reg(cmpOp0 cmp, flagsReg_EQNELTGE icc, regD dst, regD src1, regD src2) %{
-  match(Set dst (CMoveD (Binary cmp icc) (Binary src2 src1)));
-  ins_cost(150);
-  size(4);
-  format %{ "FCSEL_d $dst,$src1,$src2,$cmp" %}
-  ins_encode %{
-    __ fcsel_d($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, (AsmCondition)($cmp$$cmpcode));
-  %}
-  ins_pipe(int_conditional_float_move);
-%}
-
-#else // !AARCH64
 
 // Conditional move
 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
@@ -6840,7 +5219,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif // !AARCH64
 
 
 //----------OS and Locking Instructions----------------------------------------
@@ -6897,7 +5275,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (LShiftI src1 src2) src3));
 
@@ -6908,22 +5285,7 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-#ifdef TODO
-instruct addshlL_reg_imm_reg(iRegL dst, iRegL src1, immU6 src2, iRegL src3) %{
-  match(Set dst (AddL (LShiftL src1 src2) src3));
-
-  size(4);
-  format %{ "ADD    $dst,$src3,$src1<<$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src3$$Register, AsmOperand($src1$$Register, lsl, $src2$$constant));
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#endif
-#endif
+
 
 instruct addshlI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (LShiftI src1 src2) src3));
@@ -6936,7 +5298,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (RShiftI src1 src2) src3));
 
@@ -6947,7 +5308,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct addsarI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (RShiftI src1 src2) src3));
@@ -6960,7 +5320,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct addshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AddI (URShiftI src1 src2) src3));
 
@@ -6971,7 +5330,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct addshrI_reg_imm_reg(iRegI dst, iRegI src1, immU5 src2, iRegI src3) %{
   match(Set dst (AddI (URShiftI src1 src2) src3));
@@ -7008,69 +5366,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-// unshifted I2L operand
-operand unshiftedI2L(iRegI src2) %{
-//constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(ConvI2L src2);
-
-  op_cost(1);
-  format %{ "$src2.w" %}
-  interface(MEMORY_INTER) %{
-    base($src2);
-    index(0xff);
-    scale(0x0);
-    disp(0x0);
-  %}
-%}
-
-// shifted I2L operand
-operand shiftedI2L(iRegI src2, immI_0_4 src3) %{
-//constraint(ALLOC_IN_RC(sp_ptr_reg));
-  match(LShiftX (ConvI2L src2) src3);
-
-  op_cost(1);
-  format %{ "$src2.w << $src3" %}
-  interface(MEMORY_INTER) %{
-    base($src2);
-    index(0xff);
-    scale($src3);
-    disp(0x0);
-  %}
-%}
-
-opclass shiftedRegI(shiftedI2L, unshiftedI2L);
-
-instruct shlL_reg_regI(iRegL dst, iRegI src1, immU6 src2) %{
-  match(Set dst (LShiftL (ConvI2L src1) src2));
-
-  size(4);
-  format %{ "LSL    $dst,$src1.w,$src2\t! ptr" %}
-  ins_encode %{
-    int c = $src2$$constant;
-    int r = 64 - c;
-    int s = 31;
-    if (s >= r) {
-      s = r - 1;
-    }
-    __ sbfm($dst$$Register, $src1$$Register, r, s);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-
-instruct addP_reg_regI(iRegP dst, iRegP src1, shiftedRegI src2) %{
-  match(Set dst (AddP src1 src2));
-
-  ins_cost(DEFAULT_COST * 3/2);
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2, sxtw\t! ptr" %}
-  ins_encode %{
-    Register base = reg_to_register_object($src2$$base);
-    __ add($dst$$Register, $src1$$Register, base, ex_sxtw, $src2$$scale);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#endif
 
 // shifted iRegX operand
 operand shiftedX(iRegX src2, shimmX src3) %{
@@ -7113,30 +5408,6 @@
 %}
 
 // Long Addition
-#ifdef AARCH64
-instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (AddL src1 src2));
-  size(4);
-  format %{ "ADD     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-
-instruct addL_reg_regI(iRegL dst, iRegL src1, shiftedRegI src2) %{
-  match(Set dst (AddL src1 src2));
-
-  ins_cost(DEFAULT_COST * 3/2);
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2, sxtw\t! long" %}
-  ins_encode %{
-    Register base = reg_to_register_object($src2$$base);
-    __ add($dst$$Register, $src1$$Register, base, ex_sxtw, $src2$$scale);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#else
 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2, flagsReg ccr) %{
   match(Set dst (AddL src1 src2));
   effect(KILL ccr);
@@ -7149,36 +5420,9 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-// Immediate Addition
-instruct addL_reg_aimm(iRegL dst, iRegL src1, aimmL src2) %{
-  match(Set dst (AddL src1 src2));
-
-  size(4);
-  format %{ "ADD    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-
-instruct addL_reg_immLneg(iRegL dst, iRegL src1, aimmLneg src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "ADD    $dst,$src1,-($src2)\t! long" %}
-  ins_encode %{
-    __ add($dst$$Register, $src1$$Register, -$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+
 // TODO
-#endif
-
-#ifndef AARCH64
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct addL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con, flagsReg ccr) %{
@@ -7193,26 +5437,19 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 //----------Conditional_store--------------------------------------------------
 // Conditional-store of the updated heap-top.
 // Used during allocation of the shared heap.
 // Sets flags (EQ) on success.
 
-// TODO: optimize out barriers with AArch64 load-acquire/store-release
 // LoadP-locked.
 instruct loadPLocked(iRegP dst, memoryex mem) %{
   match(Set dst (LoadPLocked mem));
   size(4);
   format %{ "LDREX  $dst,$mem" %}
   ins_encode %{
-#ifdef AARCH64
-    Register base = reg_to_register_object($mem$$base);
-    __ ldxr($dst$$Register, base);
-#else
     __ ldrex($dst$$Register,$mem$$Address);
-#endif
   %}
   ins_pipe(iload_mem);
 %}
@@ -7225,12 +5462,7 @@
   format %{ "STREX  $tmp,$newval,$heap_top_ptr\n\t"
             "CMP    $tmp, 0" %}
   ins_encode %{
-#ifdef AARCH64
-    Register base = reg_to_register_object($heap_top_ptr$$base);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-#else
     __ strex($tmp$$Register, $newval$$Register, $heap_top_ptr$$Address);
-#endif
     __ cmp($tmp$$Register, 0);
   %}
   ins_pipe( long_memory_op );
@@ -7238,20 +5470,6 @@
 
 // Conditional-store of an intx value.
 instruct storeXConditional( memoryex mem, iRegX oldval, iRegX newval, iRegX tmp, flagsReg icc ) %{
-#ifdef AARCH64
-  match(Set icc (StoreLConditional mem (Binary oldval newval)));
-  effect( TEMP tmp );
-  size(28);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem], DOESN'T set $newval=[$mem] in any case\n\t"
-            "SUBS     $tmp, $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "CMP      $tmp, 0\n\t"
-            "done:\n\t"
-            "membar   LoadStore|LoadLoad" %}
-#else
   match(Set icc (StoreIConditional mem (Binary oldval newval)));
   effect( TEMP tmp );
   size(28);
@@ -7263,29 +5481,15 @@
             "B.eq     loop \n\t"
             "TEQ      $tmp, 0\n\t"
             "membar   LoadStore|LoadLoad" %}
-#endif
   ins_encode %{
     Label loop;
     __ bind(loop);
-#ifdef AARCH64
-// FIXME: use load-acquire/store-release, remove membar?
-    Label done;
-    Register base = reg_to_register_object($mem$$base);
-    __ ldxr($tmp$$Register, base);
-    __ subs($tmp$$Register, $tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ cmp($tmp$$Register, 0);
-    __ bind(done);
-#else
     __ ldrex($tmp$$Register, $mem$$Address);
     __ eors($tmp$$Register, $tmp$$Register, $oldval$$Register);
     __ strex($tmp$$Register, $newval$$Register, $mem$$Address, eq);
     __ cmp($tmp$$Register, 1, eq);
     __ b(loop, eq);
     __ teq($tmp$$Register, 0);
-#endif
     // used by biased locking only. Requires a membar.
     __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadStore | MacroAssembler::LoadLoad), noreg);
   %}
@@ -7294,118 +5498,6 @@
 
 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
 
-#ifdef AARCH64
-// TODO: if combined with membar, elide membar and use
-// load-acquire/store-release if appropriate
-instruct compareAndSwapL_bool(memoryex mem, iRegL oldval, iRegL newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapL mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP      $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr($tmp$$Register, base);
-    __ cmp($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-instruct compareAndSwapI_bool(memoryex mem, iRegI oldval, iRegI newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapI mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP_w    $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr_w($tmp$$Register, base);
-    __ cmp_w($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr_w($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-// tmp must use iRegI instead of iRegN until 8051805 is fixed.
-instruct compareAndSwapN_bool(memoryex mem, iRegN oldval, iRegN newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapN mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP_w    $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr_w($tmp$$Register, base);
-    __ cmp_w($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr_w($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-instruct compareAndSwapP_bool(memoryex mem, iRegP oldval, iRegP newval, iRegI res, iRegI tmp, flagsReg ccr) %{
-  match(Set res (CompareAndSwapP mem (Binary oldval newval)));
-  effect( KILL ccr, TEMP tmp);
-  size(24);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp, $mem\t! If $oldval==[$mem] Then store $newval into [$mem]\n\t"
-            "CMP      $tmp, $oldval\n\t"
-            "B.ne     done\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop\n\t"
-            "done:\n\t"
-            "CSET_w   $res, eq" %}
-  ins_encode %{
-    Register base = reg_to_register_object($mem$$base);
-    Label loop, done;
-    __ bind(loop);
-    __ ldxr($tmp$$Register, base);
-    __ cmp($tmp$$Register, $oldval$$Register);
-    __ b(done, ne);
-    __ stxr($tmp$$Register, $newval$$Register,  base);
-    __ cbnz_w($tmp$$Register, loop);
-    __ bind(done);
-    __ cset_w($res$$Register, eq);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else // !AARCH64
 instruct compareAndSwapL_bool(memoryex mem, iRegL oldval, iRegLd newval, iRegI res, iRegLd tmp, flagsReg ccr ) %{
   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
   effect( KILL ccr, TEMP tmp);
@@ -7488,32 +5580,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct xaddI_aimmI_no_res(memoryex mem, aimmI add, Universe dummy, iRegI tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp1, $mem\n\t"
-            "ADD_w    $tmp1, $tmp1, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($tmp1$$Register, base);
-    __ add_w($tmp1$$Register, $tmp1$$Register, $add$$constant);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_aimmI_no_res(memoryex mem, aimmI add, Universe dummy, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddI mem add));
@@ -7537,32 +5604,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_reg_no_res(memoryex mem, iRegI add, Universe dummy, iRegI tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $tmp1, $mem\n\t"
-            "ADD_w    $tmp1, $tmp1, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($tmp1$$Register, base);
-    __ add_w($tmp1$$Register, $tmp1$$Register, $add$$Register);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_reg_no_res(memoryex mem, iRegI add, Universe dummy, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddI mem add));
@@ -7586,31 +5628,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_aimmI(memoryex mem, aimmI add, iRegI res, iRegI tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "ADD_w    $tmp1, $res, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ add_w($tmp1$$Register, $res$$Register, $add$$constant);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_aimmI(memoryex mem, aimmI add, iRegI res, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddI mem add));
   effect(KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7633,31 +5651,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddI_reg(memoryex mem, iRegI add, iRegI res, iRegI tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddI mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "ADD_w    $tmp1, $res, $add\n\t"
-            "STXR_w   $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ add_w($tmp1$$Register, $res$$Register, $add$$Register);
-    __ stxr_w($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddI_reg(memoryex mem, iRegI add, iRegI res, iRegI tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddI mem add));
   effect(KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7680,32 +5674,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_reg_no_res(memoryex mem, iRegL add, Universe dummy, iRegL tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp1, $mem\n\t"
-            "ADD      $tmp1, $tmp1, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($tmp1$$Register, base);
-    __ add($tmp1$$Register, $tmp1$$Register, $add$$Register);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddL_reg_no_res(memoryex mem, iRegL add, Universe dummy, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
   predicate(n->as_LoadStore()->result_not_used());
   match(Set dummy (GetAndAddL mem add));
@@ -7731,32 +5700,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_imm_no_res(memoryex mem, aimmL add, Universe dummy, iRegL tmp1, iRegI tmp2) %{
-  predicate(n->as_LoadStore()->result_not_used());
-  match(Set dummy (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $tmp1, $mem\n\t"
-            "ADD      $tmp1, $tmp1, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($tmp1$$Register, base);
-    __ add($tmp1$$Register, $tmp1$$Register, $add$$constant);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xaddL_immRot_no_res(memoryex mem, immLlowRot add, Universe dummy, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
@@ -7784,31 +5728,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_reg(memoryex mem, iRegL add, iRegL res, iRegL tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "ADD      $tmp1, $res, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ add($tmp1$$Register, $res$$Register, $add$$Register);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xaddL_reg(memoryex mem, iRegL add, iRegLd res, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
   match(Set res (GetAndAddL mem add));
   effect( KILL ccr, TEMP tmp1, TEMP tmp2, TEMP res);
@@ -7833,31 +5753,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xaddL_imm(memoryex mem, aimmL add, iRegL res, iRegL tmp1, iRegI tmp2) %{
-  match(Set res (GetAndAddL mem add));
-  effect(TEMP tmp1, TEMP tmp2, TEMP res);
-  size(16);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "ADD      $tmp1, $res, $add\n\t"
-            "STXR     $tmp2, $tmp1, $mem\n\t"
-            "CBNZ_w   $tmp2, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ add($tmp1$$Register, $res$$Register, $add$$constant);
-    __ stxr($tmp2$$Register, $tmp1$$Register, base);
-    __ cbnz_w($tmp2$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xaddL_immRot(memoryex mem, immLlowRot add, iRegLd res, iRegLd tmp1, iRegI tmp2, flagsReg ccr) %{
@@ -7884,52 +5780,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xchgI(memoryex mem, iRegI newval, iRegI res, iRegI tmp) %{
-  match(Set res (GetAndSetI mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ stxr_w($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-
-#ifdef XXX
-// Disabled until 8051805 is fixed.
-instruct xchgN(memoryex mem, iRegN newval, iRegN res, iRegN tmp) %{
-  match(Set res (GetAndSetN mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR_w   $res, $mem\n\t"
-            "STXR_w   $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr_w($res$$Register, base);
-    __ stxr_w($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#endif
-#else
+
 instruct xchgI(memoryex mem, iRegI newval, iRegI res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetI mem newval));
   effect(KILL ccr, TEMP tmp, TEMP res);
@@ -7950,29 +5801,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif
-
-#ifdef AARCH64
-instruct xchgL(memoryex mem, iRegL newval, iRegL res, iRegI tmp) %{
-  match(Set res (GetAndSetL mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDXR     $res, $mem\n\t"
-            "STXR     $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldxr($res$$Register, base);
-    __ stxr($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xchgL(memoryex mem, iRegLd newval, iRegLd res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetL mem newval));
   effect( KILL ccr, TEMP tmp, TEMP res);
@@ -7993,29 +5822,7 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct xchgP(memoryex mem, iRegP newval, iRegP res, iRegI tmp) %{
-  match(Set res (GetAndSetP mem newval));
-  effect(TEMP tmp, TEMP res);
-  size(12);
-  format %{ "loop:\n\t"
-            "LDREX    $res, $mem\n\t"
-            "STREX    $tmp, $newval, $mem\n\t"
-            "CBNZ_w   $tmp, loop" %}
-
-  ins_encode %{
-    Label loop;
-    Register base = reg_to_register_object($mem$$base);
-    __ bind(loop);
-    __ ldrex($res$$Register, base);
-    __ strex($tmp$$Register, $newval$$Register, base);
-    __ cbnz_w($tmp$$Register, loop);
-  %}
-  ins_pipe( long_memory_op );
-%}
-#else
+
 instruct xchgP(memoryex mem, iRegP newval, iRegP res, iRegI tmp, flagsReg ccr) %{
   match(Set res (GetAndSetP mem newval));
   effect(KILL ccr, TEMP tmp, TEMP res);
@@ -8036,7 +5843,6 @@
   %}
   ins_pipe( long_memory_op );
 %}
-#endif // !AARCH64
 
 //---------------------
 // Subtraction Instructions
@@ -8052,7 +5858,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (LShiftI src2 src3)));
 
@@ -8063,7 +5868,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (LShiftI src2 src3)));
@@ -8076,7 +5880,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (RShiftI src2 src3)));
 
@@ -8087,7 +5890,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (RShiftI src2 src3)));
@@ -8100,7 +5902,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct subshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI src1 (URShiftI src2 src3)));
 
@@ -8111,7 +5912,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct subshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (SubI src1 (URShiftI src2 src3)));
@@ -8124,7 +5924,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct rsbshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (SubI (LShiftI src1 src2) src3));
 
@@ -8190,7 +5989,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 // Immediate Subtraction
 instruct subI_reg_aimmI(iRegI dst, iRegI src1, aimmI src2) %{
@@ -8215,7 +6013,6 @@
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct subI_immRot_reg(iRegI dst, immIRot src1, iRegI src2) %{
   match(Set dst (SubI src1 src2));
 
@@ -8226,21 +6023,8 @@
   %}
   ins_pipe(ialu_zero_reg);
 %}
-#endif
 
 // Register Subtraction
-#ifdef AARCH64
-instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-%}
-#else
 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2, flagsReg icc ) %{
   match(Set dst (SubL src1 src2));
   effect (KILL icc);
@@ -8254,36 +6038,9 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-// Immediate Subtraction
-instruct subL_reg_aimm(iRegL dst, iRegL src1, aimmL src2) %{
-  match(Set dst (SubL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-
-instruct subL_reg_immLneg(iRegL dst, iRegL src1, aimmLneg src2) %{
-  match(Set dst (AddL src1 src2));
-
-  size(4);
-  format %{ "SUB    $dst,$src1,-($src2)\t! long" %}
-  ins_encode %{
-    __ sub($dst$$Register, $src1$$Register, -$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+
 // TODO
-#endif
-
-#ifndef AARCH64
+
 // Immediate Subtraction
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
@@ -8315,7 +6072,6 @@
   %}
   ins_pipe(ialu_zero_reg);
 %}
-#endif // !AARCH64
 
 // Multiplication Instructions
 // Integer Multiplication
@@ -8331,17 +6087,6 @@
   ins_pipe(imul_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (MulL src1 src2));
-  size(4);
-  format %{ "MUL  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ mul($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(imul_reg_reg);
-%}
-#else
 instruct mulL_lo1_hi2(iRegL dst, iRegL src1, iRegL src2) %{
   effect(DEF dst, USE src1, USE src2);
   size(4);
@@ -8383,22 +6128,9 @@
     mulL_lo1_lo2(dst, src1, src2);
   %}
 %}
-#endif // !AARCH64
 
 // Integer Division
 // Register Division
-#ifdef AARCH64
-instruct divI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
-  match(Set dst (DivI src1 src2));
-
-  size(4);
-  format %{ "SDIV    $dst,$src1,$src2\t! 32-bit" %}
-  ins_encode %{
-    __ sdiv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct divI_reg_reg(R1RegI dst, R0RegI src1, R2RegI src2, LRRegP lr, flagsReg ccr) %{
   match(Set dst (DivI src1 src2));
   effect( KILL ccr, KILL src1, KILL src2, KILL lr);
@@ -8410,21 +6142,8 @@
   %}
   ins_pipe(sdiv_reg_reg);
 %}
-#endif
 
 // Register Long Division
-#ifdef AARCH64
-instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
-  match(Set dst (DivL src1 src2));
-
-  size(4);
-  format %{ "SDIV    $dst,$src1,$src2" %}
-  ins_encode %{
-    __ sdiv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct divL_reg_reg(R0R1RegL dst, R2R3RegL src1, R0R1RegL src2) %{
   match(Set dst (DivL src1 src2));
   effect(CALL);
@@ -8436,38 +6155,9 @@
   %}
   ins_pipe(divL_reg_reg);
 %}
-#endif
 
 // Integer Remainder
 // Register Remainder
-#ifdef AARCH64
-#ifdef TODO
-instruct msubI_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
-  match(Set dst (SubI src1 (MulI src2 src3)));
-
-  size(4);
-  format %{ "MSUB    $dst,$src2,$src3,$src1\t! 32-bit\n\t" %}
-  ins_encode %{
-    __ msub_w($dst$$Register, $src2$$Register, $src3$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#endif
-
-instruct modI_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp) %{
-  match(Set dst (ModI src1 src2));
-  effect(TEMP temp);
-
-  size(8);
-  format %{ "SDIV    $temp,$src1,$src2\t! 32-bit\n\t"
-            "MSUB    $dst,$src2,$temp,$src1\t! 32-bit\n\t" %}
-  ins_encode %{
-    __ sdiv_w($temp$$Register, $src1$$Register, $src2$$Register);
-    __ msub_w($dst$$Register, $src2$$Register, $temp$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct modI_reg_reg(R0RegI dst, R0RegI src1, R2RegI src2, R1RegI temp, LRRegP lr, flagsReg ccr ) %{
   match(Set dst (ModI src1 src2));
   effect( KILL ccr, KILL temp, KILL src2, KILL lr);
@@ -8478,24 +6168,8 @@
   %}
   ins_pipe(sdiv_reg_reg);
 %}
-#endif
 
 // Register Long Remainder
-#ifdef AARCH64
-instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2, iRegL temp) %{
-  match(Set dst (ModL src1 src2));
-  effect(TEMP temp);
-
-  size(8);
-  format %{ "SDIV    $temp,$src1,$src2\n\t"
-            "MSUB    $dst,$src2,$temp,$src1" %}
-  ins_encode %{
-    __ sdiv($temp$$Register, $src1$$Register, $src2$$Register);
-    __ msub($dst$$Register, $src2$$Register, $temp$$Register, $src1$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-%}
-#else
 instruct modL_reg_reg(R0R1RegL dst, R2R3RegL src1, R0R1RegL src2) %{
   match(Set dst (ModL src1 src2));
   effect(CALL);
@@ -8507,7 +6181,6 @@
   %}
   ins_pipe(divL_reg_reg);
 %}
-#endif
 
 // Integer Shift Instructions
 
@@ -8516,17 +6189,10 @@
   match(Set dst (LShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSLV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ lslv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "LSL  $dst,$src1,$src2 \n\t" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsl, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8535,21 +6201,13 @@
   match(Set dst (LShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSL_w  $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ _lsl($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "LSL    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ logical_shift_left($dst$$Register, $src1$$Register, $src2$$constant);
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct shlL_reg_reg_merge_hi(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
   size(4);
@@ -8587,40 +6245,18 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (LShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LSLV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ lslv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     shlL_reg_reg_overlap(dst, src1, src2, ccr);
     shlL_reg_reg_merge_hi(dst, src1, src2);
     shlL_reg_reg_merge_lo(dst, src1, src2);
   %}
-#endif
-%}
-
-#ifdef AARCH64
-instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (LShiftL src1 src2));
-
-  size(4);
-  format %{ "LSL    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ logical_shift_left($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
+%}
+
 // Register Shift Left Immediate
 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (LShiftL src1 src2));
@@ -8655,23 +6291,15 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // !AARCH64
 
 // Register Arithmetic Shift Right
 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
   match(Set dst (RShiftI src1 src2));
   size(4);
-#ifdef AARCH64
-  format %{ "ASRV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ asrv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "ASR    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, asr, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8680,21 +6308,13 @@
   match(Set dst (RShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "ASR_w  $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _asr_w($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "ASR    $dst,$src1,$src2" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, asr, $src2$$constant));
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 // Register Shift Right Arithmetic Long
 instruct sarL_reg_reg_merge_lo(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
@@ -8733,41 +6353,19 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (RShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "ASRV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ asrv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     sarL_reg_reg_overlap(dst, src1, src2, ccr);
     sarL_reg_reg_merge_lo(dst, src1, src2);
     sarL_reg_reg_merge_hi(dst, src1, src2);
   %}
-#endif
 %}
 
 // Register Shift Left Immediate
-#ifdef AARCH64
-instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (RShiftL src1 src2));
-
-  size(4);
-  format %{ "ASR    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ _asr($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (RShiftL src1 src2));
 
@@ -8801,23 +6399,15 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Register Shift Right
 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
   match(Set dst (URShiftI src1 src2));
   size(4);
-#ifdef AARCH64
-  format %{ "LSRV   $dst,$src1,$src2\t! int" %}
-  ins_encode %{
-    __ lsrv_w($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   format %{ "LSR    $dst,$src1,$src2\t! int" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsr, $src2$$Register));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -8826,21 +6416,13 @@
   match(Set dst (URShiftI src1 src2));
 
   size(4);
-#ifdef AARCH64
-  format %{ "LSR_w  $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _lsr_w($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-#else
   format %{ "LSR    $dst,$src1,$src2" %}
   ins_encode %{
     __ mov($dst$$Register, AsmOperand($src1$$Register, lsr, $src2$$constant));
   %}
-#endif
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 // Register Shift Right
 instruct shrL_reg_reg_merge_lo(iRegL dst, iRegL src1, iRegI src2) %{
   effect(USE_DEF dst, USE src1, USE src2);
@@ -8879,41 +6461,19 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif // !AARCH64
 
 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
   match(Set dst (URShiftL src1 src2));
 
-#ifdef AARCH64
-  size(4);
-  format %{ "LSRV  $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ lsrv($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-  ins_pipe(ialu_reg_reg);
-#else
   expand %{
     flagsReg ccr;
     shrL_reg_reg_overlap(dst, src1, src2, ccr);
     shrL_reg_reg_merge_lo(dst, src1, src2);
     shrL_reg_reg_merge_hi(dst, src1, src2);
   %}
-#endif
 %}
 
 // Register Shift Right Immediate
-#ifdef AARCH64
-instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
-  match(Set dst (URShiftL src1 src2));
-
-  size(4);
-  format %{ "LSR    $dst,$src1,$src2" %}
-  ins_encode %{
-    __ _lsr($dst$$Register, $src1$$Register, $src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6Big src2) %{
   match(Set dst (URShiftL src1 src2));
 
@@ -8948,7 +6508,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // !AARCH64
 
 
 instruct shrP_reg_imm5(iRegX dst, iRegP src1, immU5 src2) %{
@@ -9146,7 +6705,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (LShiftI src2 src3)));
 
@@ -9157,7 +6715,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (LShiftI src2 src3)));
@@ -9170,7 +6727,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (RShiftI src2 src3)));
 
@@ -9181,7 +6737,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (RShiftI src2 src3)));
@@ -9194,7 +6749,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct andshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (AndI src1 (URShiftI src2 src3)));
 
@@ -9205,7 +6759,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct andshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (AndI src1 (URShiftI src2 src3)));
@@ -9230,7 +6783,6 @@
   ins_pipe(ialu_reg_imm);
 %}
 
-#ifndef AARCH64
 instruct andI_reg_limmn(iRegI dst, iRegI src1, limmIn src2) %{
   match(Set dst (AndI src1 src2));
 
@@ -9241,43 +6793,21 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Register And Long
 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
   match(Set dst (AndL src1 src2));
 
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "AND    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ andr($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "AND    $dst,$src1,$src2\t! long" %}
   ins_encode %{
     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
     __ andr($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-// Immediate And
-instruct andL_reg_limm(iRegL dst, iRegL src1, limmL src2) %{
-  match(Set dst (AndL src1 src2));
-
-  size(4);
-  format %{ "AND    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ andr($dst$$Register, $src1$$Register, (uintx)$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct andL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9291,7 +6821,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 // Or Instructions
 // Register Or
@@ -9306,7 +6835,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (LShiftI src2 src3)));
 
@@ -9317,7 +6845,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (LShiftI src2 src3)));
@@ -9330,7 +6857,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (RShiftI src2 src3)));
 
@@ -9341,7 +6867,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (RShiftI src2 src3)));
@@ -9354,7 +6879,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct orshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (OrI src1 (URShiftI src2 src3)));
 
@@ -9365,7 +6889,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct orshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (OrI src1 (URShiftI src2 src3)));
@@ -9396,13 +6919,6 @@
   match(Set dst (OrL src1 src2));
 
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "OR     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ orr($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "OR     $dst.lo,$src1.lo,$src2.lo\t! long\n\t"
             "OR     $dst.hi,$src1.hi,$src2.hi" %}
@@ -9410,22 +6926,9 @@
     __ orr($dst$$Register, $src1$$Register, $src2$$Register);
     __ orr($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct orL_reg_limm(iRegL dst, iRegL src1, limmL src2) %{
-  match(Set dst (OrL src1 src2));
-
-  size(4);
-  format %{ "ORR    $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ orr($dst$$Register, $src1$$Register, (uintx)$src2$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct orL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9440,7 +6943,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 #ifdef TODO
 // Use SPRegP to match Rthread (TLS register) without spilling.
@@ -9470,7 +6972,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (LShiftI src2 src3)));
 
@@ -9481,7 +6982,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorshlI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (LShiftI src2 src3)));
@@ -9494,7 +6994,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorsarI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (RShiftI src2 src3)));
 
@@ -9505,7 +7004,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorsarI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (RShiftI src2 src3)));
@@ -9518,7 +7016,6 @@
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifndef AARCH64
 instruct xorshrI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
   match(Set dst (XorI src1 (URShiftI src2 src3)));
 
@@ -9529,7 +7026,6 @@
   %}
   ins_pipe(ialu_reg_reg);
 %}
-#endif
 
 instruct xorshrI_reg_reg_imm(iRegI dst, iRegI src1, iRegI src2, immU5 src3) %{
   match(Set dst (XorI src1 (URShiftI src2 src3)));
@@ -9558,13 +7054,6 @@
 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
   match(Set dst (XorL src1 src2));
   ins_cost(DEFAULT_COST);
-#ifdef AARCH64
-  size(4);
-  format %{ "XOR     $dst,$src1,$src2\t! long" %}
-  ins_encode %{
-    __ eor($dst$$Register, $src1$$Register, $src2$$Register);
-  %}
-#else
   size(8);
   format %{ "XOR     $dst.hi,$src1.hi,$src2.hi\t! long\n\t"
             "XOR     $dst.lo,$src1.lo,$src2.lo\t! long" %}
@@ -9572,22 +7061,9 @@
     __ eor($dst$$Register, $src1$$Register, $src2$$Register);
     __ eor($dst$$Register->successor(), $src1$$Register->successor(), $src2$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
-#ifdef AARCH64
-instruct xorL_reg_limmL(iRegL dst, iRegL src1, limmL con) %{
-  match(Set dst (XorL src1 con));
-  ins_cost(DEFAULT_COST);
-  size(4);
-  format %{ "EOR     $dst,$src1,$con\t! long" %}
-  ins_encode %{
-    __ eor($dst$$Register, $src1$$Register, (uintx)$con$$constant);
-  %}
-  ins_pipe(ialu_reg_imm);
-%}
-#else
 // TODO: try immLRot2 instead, (0, $con$$constant) becomes
 // (hi($con$$constant), lo($con$$constant)) becomes
 instruct xorL_reg_immRot(iRegL dst, iRegL src1, immLlowRot con) %{
@@ -9602,22 +7078,11 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif // AARCH64
 
 //----------Convert to Boolean-------------------------------------------------
 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
   match(Set dst (Conv2B src));
   effect(KILL ccr);
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "cmp_32 $src,ZR\n\t"
-            "cset_w $dst, ne" %}
-  ins_encode %{
-    __ cmp_32($src$$Register, ZR);
-    __ cset_w($dst$$Register, ne);
-  %}
-#else
   size(12);
   ins_cost(DEFAULT_COST*2);
   format %{ "TST    $src,$src \n\t"
@@ -9628,23 +7093,12 @@
     __ mov($dst$$Register, 0);
     __ mov($dst$$Register, 1, ne);
   %}
-#endif
   ins_pipe(ialu_reg_ialu);
 %}
 
 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
   match(Set dst (Conv2B src));
   effect(KILL ccr);
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP    $src,ZR\n\t"
-            "cset   $dst, ne" %}
-  ins_encode %{
-    __ cmp($src$$Register, ZR);
-    __ cset($dst$$Register, ne);
-  %}
-#else
   size(12);
   ins_cost(DEFAULT_COST*2);
   format %{ "TST    $src,$src \n\t"
@@ -9655,23 +7109,12 @@
     __ mov($dst$$Register, 0);
     __ mov($dst$$Register, 1, ne);
   %}
-#endif
   ins_pipe(ialu_reg_ialu);
 %}
 
 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
   match(Set dst (CmpLTMask p q));
   effect( KILL ccr );
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP_w   $p,$q\n\t"
-            "CSETM_w $dst, lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$Register);
-    __ csetm_w($dst$$Register, lt);
-  %}
-#else
   ins_cost(DEFAULT_COST*3);
   format %{ "CMP    $p,$q\n\t"
             "MOV    $dst, #0\n\t"
@@ -9681,23 +7124,12 @@
     __ mov($dst$$Register, 0);
     __ mvn($dst$$Register, 0, lt);
   %}
-#endif
   ins_pipe(ialu_reg_reg_ialu);
 %}
 
 instruct cmpLTMask_reg_imm( iRegI dst, iRegI p, aimmI q, flagsReg ccr ) %{
   match(Set dst (CmpLTMask p q));
   effect( KILL ccr );
-#ifdef AARCH64
-  size(8);
-  ins_cost(DEFAULT_COST*2);
-  format %{ "CMP_w   $p,$q\n\t"
-            "CSETM_w $dst, lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$constant);
-    __ csetm_w($dst$$Register, lt);
-  %}
-#else
   ins_cost(DEFAULT_COST*3);
   format %{ "CMP    $p,$q\n\t"
             "MOV    $dst, #0\n\t"
@@ -9707,27 +7139,9 @@
     __ mov($dst$$Register, 0);
     __ mvn($dst$$Register, 0, lt);
   %}
-#endif
   ins_pipe(ialu_reg_reg_ialu);
 %}
 
-#ifdef AARCH64
-instruct cadd_cmpLTMask3( iRegI dst, iRegI p, iRegI q, iRegI y, iRegI x, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) x));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "CMP_w  $p,$q\n\t"
-            "ADD_w  $dst,$y,$x\n\t"
-            "CSEL_w $dst,$dst,$x,lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$Register);
-    __ add_w($dst$$Register, $y$$Register, $x$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $x$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask );
-%}
-#else
 instruct cadd_cmpLTMask3( iRegI p, iRegI q, iRegI y, iRegI z, flagsReg ccr ) %{
   match(Set z (AddI (AndI (CmpLTMask p q) y) z));
   effect( KILL ccr );
@@ -9740,25 +7154,7 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif
-
-#ifdef AARCH64
-instruct cadd_cmpLTMask4( iRegI dst, iRegI p, aimmI q, iRegI y, iRegI x, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) x));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "CMP_w  $p,$q\n\t"
-            "ADD_w  $dst,$y,$x\n\t"
-            "CSEL_w $dst,$dst,$x,lt" %}
-  ins_encode %{
-    __ cmp_w($p$$Register, $q$$constant);
-    __ add_w($dst$$Register, $y$$Register, $x$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $x$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask );
-%}
-#else
+
 // FIXME: remove unused "dst"
 instruct cadd_cmpLTMask4( iRegI dst, iRegI p, aimmI q, iRegI y, iRegI z, flagsReg ccr ) %{
   match(Set z (AddI (AndI (CmpLTMask p q) y) z));
@@ -9772,25 +7168,7 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif // !AARCH64
-
-#ifdef AARCH64
-instruct cadd_cmpLTMask( iRegI dst, iRegI p, iRegI q, iRegI y, flagsReg ccr ) %{
-  match(Set dst (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
-  effect( TEMP dst, KILL ccr );
-  size(12);
-  ins_cost(DEFAULT_COST*3);
-  format %{ "SUBS_w $p,$p,$q\n\t"
-            "ADD_w  $dst,$y,$p\n\t"
-            "CSEL_w $dst,$dst,$p,lt" %}
-  ins_encode %{
-    __ subs_w($p$$Register, $p$$Register, $q$$Register);
-    __ add_w($dst$$Register, $y$$Register, $p$$Register);
-    __ csel_w($dst$$Register, $dst$$Register, $p$$Register, lt);
-  %}
-  ins_pipe( cadd_cmpltmask ); // FIXME
-%}
-#else
+
 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, flagsReg ccr ) %{
   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
   effect( KILL ccr );
@@ -9803,7 +7181,6 @@
   %}
   ins_pipe( cadd_cmpltmask );
 %}
-#endif
 
 //----------Arithmetic Conversion Instructions---------------------------------
 // The conversions operations are all Alpha sorted.  Please keep it that way!
@@ -9821,27 +7198,6 @@
 // Convert a double to an int in a float register.
 // If the double is a NAN, stuff a zero in instead.
 
-#ifdef AARCH64
-instruct convD2I_reg_reg(iRegI dst, regD src) %{
-  match(Set dst (ConvD2I src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  format %{ "FCVTZS_wd $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_wd($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtD2I);
-%}
-
-instruct convD2L_reg_reg(iRegL dst, regD src) %{
-  match(Set dst (ConvD2L src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  format %{ "FCVTZS_xd $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_xd($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtD2L);
-%}
-#else
 instruct convD2I_reg_reg(iRegI dst, regD src, regF tmp) %{
   match(Set dst (ConvD2I src));
   effect( TEMP tmp );
@@ -9854,12 +7210,10 @@
   %}
   ins_pipe(fcvtD2I);
 %}
-#endif
 
 // Convert a double to a long in a double register.
 // If the double is a NAN, stuff a zero in instead.
 
-#ifndef AARCH64
 // Double to Long conversion
 instruct convD2L_reg(R0R1RegL dst, regD src) %{
   match(Set dst (ConvD2L src));
@@ -9879,7 +7233,6 @@
   %}
   ins_pipe(fcvtD2L);
 %}
-#endif
 
 instruct convF2D_reg(regD dst, regF src) %{
   match(Set dst (ConvF2D src));
@@ -9891,29 +7244,6 @@
   ins_pipe(fcvtF2D);
 %}
 
-#ifdef AARCH64
-instruct convF2I_reg_reg(iRegI dst, regF src) %{
-  match(Set dst (ConvF2I src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "FCVTZS_ws $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_ws($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtF2I);
-%}
-
-instruct convF2L_reg_reg(iRegL dst, regF src) %{
-  match(Set dst (ConvF2L src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "FCVTZS_xs $dst, $src" %}
-  ins_encode %{
-    __ fcvtzs_xs($dst$$Register, $src$$FloatRegister);
-  %}
-  ins_pipe(fcvtF2L);
-%}
-#else
 instruct convF2I_reg_reg(iRegI dst, regF src, regF tmp) %{
   match(Set dst (ConvF2I src));
   effect( TEMP tmp );
@@ -9947,20 +7277,7 @@
   %}
   ins_pipe(fcvtF2L);
 %}
-#endif
-
-#ifdef AARCH64
-instruct convI2D_reg_reg(iRegI src, regD dst) %{
-  match(Set dst (ConvI2D src));
-  ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_dw $dst,$src" %}
-  ins_encode %{
-      __ scvtf_dw($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtI2D);
-%}
-#else
+
 instruct convI2D_reg_reg(iRegI src, regD_low dst) %{
   match(Set dst (ConvI2D src));
   ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
@@ -9973,18 +7290,10 @@
   %}
   ins_pipe(fcvtI2D);
 %}
-#endif
 
 instruct convI2F_reg_reg( regF dst, iRegI src ) %{
   match(Set dst (ConvI2F src));
   ins_cost(DEFAULT_COST + MEMORY_REF_COST); // FIXME
-#ifdef AARCH64
-  size(4);
-  format %{ "SCVTF_sw $dst,$src" %}
-  ins_encode %{
-      __ scvtf_sw($dst$$FloatRegister, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "FMSR     $dst,$src \n\t"
             "FSITOS   $dst, $dst"%}
@@ -9992,19 +7301,11 @@
       __ fmsr($dst$$FloatRegister, $src$$Register);
       __ fsitos($dst$$FloatRegister, $dst$$FloatRegister);
   %}
-#endif
   ins_pipe(fcvtI2F);
 %}
 
 instruct convI2L_reg(iRegL dst, iRegI src) %{
   match(Set dst (ConvI2L src));
-#ifdef AARCH64
-  size(4);
-  format %{ "SXTW   $dst,$src\t! int->long" %}
-  ins_encode %{
-    __ sxtw($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo, $src \n\t"
             "ASR    $dst.hi,$src,31\t! int->long" %}
@@ -10012,20 +7313,12 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), AsmOperand($src$$Register, asr, 31));
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
 // Zero-extend convert int to long
 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
   match(Set dst (AndL (ConvI2L src) mask) );
-#ifdef AARCH64
-  size(4);
-  format %{ "mov_w  $dst,$src\t! zero-extend int to long"  %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo,$src.lo\t! zero-extend int to long\n\t"
             "MOV    $dst.hi, 0"%}
@@ -10033,20 +7326,12 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
 // Zero-extend long
 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
   match(Set dst (AndL src mask) );
-#ifdef AARCH64
-  size(4);
-  format %{ "mov_w  $dst,$src\t! zero-extend long"  %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   size(8);
   format %{ "MOV    $dst.lo,$src.lo\t! zero-extend long\n\t"
             "MOV    $dst.hi, 0"%}
@@ -10054,7 +7339,6 @@
     __ mov($dst$$Register, $src$$Register);
     __ mov($dst$$Register->successor(), 0);
   %}
-#endif
   ins_pipe(ialu_reg_reg);
 %}
 
@@ -10089,17 +7373,10 @@
   ins_cost(MEMORY_REF_COST); // FIXME
 
   size(4);
-#ifdef AARCH64
-  format %{ "FMOV_xd  $dst,$src\t! MoveD2L" %}
-  ins_encode %{
-    __ fmov_xd($dst$$Register, $src$$FloatRegister);
-  %}
-#else
   format %{ "FMRRD    $dst,$src\t! MoveD2L" %}
   ins_encode %{
     __ fmrrd($dst$$Register, $dst$$Register->successor(), $src$$FloatRegister);
   %}
-#endif
   ins_pipe(iload_mem); // FIXME
 %}
 
@@ -10109,46 +7386,16 @@
   ins_cost(MEMORY_REF_COST); // FIXME
 
   size(4);
-#ifdef AARCH64
-  format %{ "FMOV_dx $dst,$src\t! MoveL2D" %}
-  ins_encode %{
-    __ fmov_dx($dst$$FloatRegister, $src$$Register);
-  %}
-#else
   format %{ "FMDRR   $dst,$src\t! MoveL2D" %}
   ins_encode %{
     __ fmdrr($dst$$FloatRegister, $src$$Register, $src$$Register->successor());
   %}
-#endif
   ins_pipe(ialu_reg_reg); // FIXME
 %}
 
 //-----------
 // Long to Double conversion
 
-#ifdef AARCH64
-instruct convL2D(regD dst, iRegL src) %{
-  match(Set dst (ConvL2D src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_dx $dst, $src" %}
-  ins_encode %{
-    __ scvtf_dx($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtL2D);
-%}
-
-instruct convL2F(regF dst, iRegL src) %{
-  match(Set dst (ConvL2F src));
-  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); // FIXME
-  size(4);
-  format %{ "SCVTF_sx $dst, $src" %}
-  ins_encode %{
-    __ scvtf_sx($dst$$FloatRegister, $src$$Register);
-  %}
-  ins_pipe(fcvtL2F);
-%}
-#else
 // Magic constant, 0x43300000
 instruct loadConI_x43300000(iRegI dst) %{
   effect(DEF dst);
@@ -10194,7 +7441,6 @@
   ins_pipe(faddD_reg_reg);
 %}
 
-#ifndef AARCH64
 // Convert integer in high half of a double register (in the lower half of
 // the double register file) to double
 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
@@ -10206,7 +7452,6 @@
   %}
   ins_pipe(fcvtLHi2D);
 %}
-#endif
 
 // Add float double precision
 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
@@ -10297,26 +7542,17 @@
     addD_regD_regD(dst, tmp3, tmp4);
   %}
 %}
-#endif // !AARCH64
 
 instruct convL2I_reg(iRegI dst, iRegL src) %{
   match(Set dst (ConvL2I src));
   size(4);
-#ifdef AARCH64
-  format %{ "MOV_w  $dst,$src\t! long->int" %}
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-  %}
-#else
   format %{ "MOV    $dst,$src.lo\t! long->int" %}
   ins_encode %{
     __ mov($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe(ialu_move_reg_I_to_L);
 %}
 
-#ifndef AARCH64
 // Register Shift Right Immediate
 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
   match(Set dst (ConvL2I (RShiftL src cnt)));
@@ -10331,7 +7567,6 @@
   %}
   ins_pipe(ialu_reg_imm);
 %}
-#endif
 
 
 //----------Control Flow Instructions------------------------------------------
@@ -10410,7 +7645,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testshlI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (LShiftI op2 op3)) zero));
   size(4);
@@ -10421,7 +7655,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testshlI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (LShiftI op2 op3)) zero));
@@ -10434,7 +7667,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testsarI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (RShiftI op2 op3)) zero));
   size(4);
@@ -10445,7 +7677,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testsarI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (RShiftI op2 op3)) zero));
@@ -10458,7 +7689,6 @@
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
 
-#ifndef AARCH64
 instruct testshrI_reg_reg_reg( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, iRegI op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (URShiftI op2 op3)) zero));
   size(4);
@@ -10469,7 +7699,6 @@
   %}
   ins_pipe(ialu_cconly_reg_reg_zero);
 %}
-#endif
 
 instruct testshrI_reg_reg_imm( flagsReg_EQNELTGE icc, iRegI op1, iRegI op2, immU5 op3, immI0 zero ) %{
   match(Set icc (CmpI (AndI op1 (URShiftI op2 op3)) zero));
@@ -10493,31 +7722,6 @@
   ins_pipe(ialu_cconly_reg_imm_zero);
 %}
 
-#ifdef AARCH64
-instruct compL_reg_reg(flagsReg xcc, iRegL op1, iRegL op2)
-%{
-  match(Set xcc (CmpL op1 op2));
-  effect( DEF xcc, USE op1, USE op2 );
-
-  size(4);
-  format %{ "CMP     $op1,$op2\t! long" %}
-  ins_encode %{
-    __ cmp($op1$$Register, $op2$$Register);
-  %}
-  ins_pipe(ialu_cconly_reg_reg);
-%}
-
-instruct compUL_iReg(flagsRegU xcc, iRegL op1, iRegL op2) %{
-  match(Set xcc (CmpUL op1 op2));
-
-  size(4);
-  format %{ "CMP     $op1,$op2\t! unsigned long" %}
-  ins_encode %{
-    __ cmp($op1$$Register, $op2$$Register);
-  %}
-  ins_pipe(ialu_cconly_reg_reg);
-%}
-#else
 instruct compL_reg_reg_LTGE(flagsRegL_LTGE xcc, iRegL op1, iRegL op2, iRegL tmp) %{
   match(Set xcc (CmpL op1 op2));
   effect( DEF xcc, USE op1, USE op2, TEMP tmp );
@@ -10545,35 +7749,7 @@
   %}
   ins_pipe(ialu_cconly_reg_reg);
 %}
-#endif
-
-#ifdef AARCH64
-instruct compL_reg_con(flagsReg xcc, iRegL op1, aimmL con) %{
-  match(Set xcc (CmpL op1 con));
-  effect( DEF xcc, USE op1, USE con );
-
-  size(8);
-  format %{ "CMP     $op1,$con\t\t! long"  %}
-  ins_encode %{
-    __ cmp($op1$$Register, $con$$constant);
-  %}
-
-  ins_pipe(ialu_cconly_reg_imm);
-%}
-
-instruct compUL_reg_con(flagsRegU xcc, iRegL op1, aimmL con) %{
-  match(Set xcc (CmpUL op1 con));
-  effect(DEF xcc, USE op1, USE con);
-
-  size(8);
-  format %{ "CMP     $op1,$con\t\t! unsigned long"  %}
-  ins_encode %{
-    __ cmp($op1$$Register, $con$$constant);
-  %}
-
-  ins_pipe(ialu_cconly_reg_imm);
-%}
-#else
+
 instruct compL_reg_reg_EQNE(flagsRegL_EQNE xcc, iRegL op1, iRegL op2) %{
   match(Set xcc (CmpL op1 op2));
   effect( DEF xcc, USE op1, USE op2 );
@@ -10731,7 +7907,6 @@
 
   ins_pipe(ialu_cconly_reg_reg);
 %}
-#endif
 
 /* instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ */
 /*   match(Set xcc (CmpL (AndL op1 op2) zero)); */
@@ -10839,13 +8014,6 @@
   match(Set icc (CmpF src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP_s  $src1,$src2" %}
-  ins_encode %{
-    __ fcmp_s($src1$$FloatRegister, $src2$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPs  $src1,$src2\n\t"
             "FMSTAT" %}
@@ -10853,7 +8021,6 @@
     __ fcmps($src1$$FloatRegister, $src2$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddF_fcc_reg_reg_zero);
 %}
 
@@ -10861,13 +8028,6 @@
   match(Set icc (CmpF src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP0_s $src1" %}
-  ins_encode %{
-    __ fcmp0_s($src1$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPs  $src1,$src2\n\t"
             "FMSTAT" %}
@@ -10875,7 +8035,6 @@
     __ fcmpzs($src1$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddF_fcc_reg_reg_zero);
 %}
 
@@ -10883,13 +8042,6 @@
   match(Set icc (CmpD src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(4);
-  format %{ "FCMP_d $src1,$src2" %}
-  ins_encode %{
-    __ fcmp_d($src1$$FloatRegister, $src2$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPd  $src1,$src2 \n\t"
             "FMSTAT" %}
@@ -10897,7 +8049,6 @@
     __ fcmpd($src1$$FloatRegister, $src2$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddD_fcc_reg_reg_zero);
 %}
 
@@ -10905,13 +8056,6 @@
   match(Set icc (CmpD src1 src2));
   effect(KILL fcc);
 
-#ifdef AARCH64
-  size(8);
-  format %{ "FCMP0_d $src1" %}
-  ins_encode %{
-    __ fcmp0_d($src1$$FloatRegister);
-  %}
-#else
   size(8);
   format %{ "FCMPZd  $src1,$src2 \n\t"
             "FMSTAT" %}
@@ -10919,87 +8063,9 @@
     __ fcmpzd($src1$$FloatRegister);
     __ fmstat();
   %}
-#endif
   ins_pipe(faddD_fcc_reg_reg_zero);
 %}
 
-#ifdef AARCH64
-// Compare floating, generate -1,0,1
-instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg icc) %{
-  match(Set dst (CmpF3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP_s $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp_s($src1$$FloatRegister, $src2$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg icc) %{
-  match(Set dst (CmpD3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP_d $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp_d($src1$$FloatRegister, $src2$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpF0_reg(iRegI dst, regF src1, immF0 src2, flagsReg icc) %{
-  match(Set dst (CmpF3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP0_s $src1\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp0_s($src1$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-
-// Compare floating, generate -1,0,1
-instruct cmpD0_reg(iRegI dst, regD src1, immD0 src2, flagsReg icc) %{
-  match(Set dst (CmpD3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL icc);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "FCMP0_d $src1\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ fcmp0_d($src1$$FloatRegister);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( floating_cmp ); // FIXME
-%}
-#else
 // Compare floating, generate -1,0,1
 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF fcc) %{
   match(Set dst (CmpF3 src1 src2));
@@ -11076,7 +8142,6 @@
   %}
   ins_pipe( floating_cmp );
 %}
-#endif // !AARCH64
 
 //----------Branches---------------------------------------------------------
 // Jump
@@ -11158,61 +8223,6 @@
 %}
 #endif
 
-#ifdef AARCH64
-instruct cbzI(cmpOp cmp, iRegI op1, immI0 op2, label labl) %{
-  match(If cmp (CmpI op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! int $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz_w($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz_w($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-
-instruct cbzP(cmpOpP cmp, iRegP op1, immP0 op2, label labl) %{
-  match(If cmp (CmpP op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! ptr $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-
-instruct cbzL(cmpOpL cmp, iRegL op1, immL0 op2, label labl) %{
-  match(If cmp (CmpL op1 op2));
-  effect(USE labl);
-  predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq ||
-            _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
-  size(4);
-  ins_cost(BRANCH_COST);
-  format %{ "CB{N}Z $op1, $labl\t! long $cmp" %}
-  ins_encode %{
-    if ($cmp$$cmpcode == eq) {
-      __ cbz($op1$$Register, *($labl$$label));
-    } else {
-      __ cbnz($op1$$Register, *($labl$$label));
-    }
-  %}
-  ins_pipe(br_cc); // FIXME
-%}
-#endif
 
 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
   match(If cmp icc);
@@ -11240,7 +8250,6 @@
   ins_pipe(br_cc);
 %}
 
-#ifndef AARCH64
 instruct branchConL_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, label labl) %{
   match(If cmp xcc);
   effect(USE labl);
@@ -11324,7 +8333,6 @@
   %}
   ins_pipe(br_cc);
 %}
-#endif
 
 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
   match(CountedLoopEnd cmp icc);
@@ -11372,26 +8380,6 @@
 
 // Manifest a CmpL3 result in an integer register.  Very painful.
 // This is the test to avoid.
-#ifdef AARCH64
-instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr) %{
-  match(Set dst (CmpL3 src1 src2));
-  // effect(KILL fcc); // nobody cares if flagsRegF is killed
-  effect(KILL ccr);
-  ins_cost(DEFAULT_COST*3); // FIXME
-  size(12);
-  format %{ "CMP    $src1,$src2\n\t"
-            "CSET   $dst, gt\n\t"
-            "CSINV  $dst, $dst, ZR, ge" %}
-  ins_encode %{
-    Register dst = $dst$$Register;
-    __ cmp($src1$$Register, $src2$$Register);
-    __ cset(dst, gt);            // 1 if '>', else 0
-    __ csinv(dst, dst, ZR, ge);  // previous value if '>=', else -1
-  %}
-  ins_pipe( ialu_cconly_reg_reg ); // FIXME
-%}
-// TODO cmpL3_reg_imm
-#else
 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
   match(Set dst (CmpL3 src1 src2) );
   effect( KILL ccr );
@@ -11419,9 +8407,7 @@
   %}
   ins_pipe(cmpL_reg);
 %}
-#endif
-
-#ifndef AARCH64
+
 // Conditional move
 instruct cmovLL_reg_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegL dst, iRegL src) %{
   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
@@ -11509,9 +8495,7 @@
   %}
   ins_pipe(ialu_imm);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct cmovIL_reg_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegI dst, iRegI src) %{
   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
@@ -11550,9 +8534,7 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif // !AARCH64
-
-#ifndef AARCH64
+
 instruct cmovIL_imm_LTGE(cmpOpL cmp, flagsRegL_LTGE xcc, iRegI dst, immI16 src) %{
   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
   predicate(_kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
@@ -11738,25 +8720,9 @@
   %}
   ins_pipe(int_conditional_float_move);
 %}
-#endif // !AARCH64
 
 // ============================================================================
 // Safepoint Instruction
-#ifdef AARCH64
-instruct safePoint_poll(iRegP poll, flagsReg icc, RtempRegP tmp) %{
-  match(SafePoint poll);
-  // The handler stub kills Rtemp
-  effect(USE poll, KILL tmp, KILL icc);
-
-  size(4);
-  format %{ "LDR   ZR,[$poll]\t! Safepoint: poll for GC" %}
-  ins_encode %{
-    __ relocate(relocInfo::poll_type);
-    __ ldr(ZR, Address($poll$$Register));
-  %}
-  ins_pipe(loadPollP);
-%}
-#else
 // rather than KILL R12, it would be better to use any reg as
 // TEMP. Can't do that at this point because it crashes the compiler
 instruct safePoint_poll(iRegP poll, R12RegI tmp, flagsReg icc) %{
@@ -11771,7 +8737,6 @@
   %}
   ins_pipe(loadPollP);
 %}
-#endif
 
 
 // ============================================================================
@@ -11820,13 +8785,8 @@
   effect(USE meth);
   ins_cost(CALL_COST);
   format %{ "CALL,runtime" %}
-#ifdef AARCH64
-  ins_encode( save_last_PC, Java_To_Runtime( meth ),
-              call_epilog );
-#else
   ins_encode( Java_To_Runtime( meth ),
               call_epilog );
-#endif
   ins_pipe(simple_call);
 %}
 
@@ -11952,11 +8912,7 @@
   // Use the following format syntax
   format %{ "ShouldNotReachHere" %}
   ins_encode %{
-#ifdef AARCH64
-    __ dpcs1(0xdead);
-#else
     __ udf(0xdead);
-#endif
   %}
   ins_pipe(tail_call);
 %}
@@ -11986,49 +8942,21 @@
 // ============================================================================
 // inlined locking and unlocking
 
-#ifdef AARCH64
-instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch, iRegP scratch3 )
-#else
 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch )
-#endif
 %{
   match(Set pcc (FastLock object box));
 
-#ifdef AARCH64
-  effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
-#else
   effect(TEMP scratch, TEMP scratch2);
-#endif
   ins_cost(100);
 
-#ifdef AARCH64
-  format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $scratch3" %}
-  ins_encode %{
-    __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register);
-  %}
-#else
   format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2" %}
   ins_encode %{
     __ fast_lock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register);
   %}
-#endif
   ins_pipe(long_memory_op);
 %}
 
 
-#ifdef AARCH64
-instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch, iRegP scratch3 ) %{
-  match(Set pcc (FastUnlock object box));
-  effect(TEMP scratch, TEMP scratch2, TEMP scratch3);
-  ins_cost(100);
-
-  format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $scratch3" %}
-  ins_encode %{
-    __ fast_unlock($object$$Register, $box$$Register, $scratch$$Register, $scratch2$$Register, $scratch3$$Register);
-  %}
-  ins_pipe(long_memory_op);
-%}
-#else
 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, iRegP scratch ) %{
   match(Set pcc (FastUnlock object box));
   effect(TEMP scratch, TEMP scratch2);
@@ -12040,48 +8968,7 @@
   %}
   ins_pipe(long_memory_op);
 %}
-#endif
-
-#ifdef AARCH64
-// TODO: add version that takes immI cnt?
-instruct clear_array(iRegX cnt, iRegP base, iRegP ptr, iRegX temp, Universe dummy, flagsReg cpsr) %{
-  match(Set dummy (ClearArray cnt base));
-  effect(TEMP temp, TEMP ptr, KILL cpsr);
-  ins_cost(300);
-  format %{
-      "        MOV    $temp,$cnt\n"
-      "        ADD    $ptr,$base,$cnt\n"
-      "        SUBS   $temp,$temp,16\t! Count down dword pair in bytes\n"
-      "        B.lt   done16\n"
-      "loop:   STP    ZR,ZR,[$ptr,-16]!\n"
-      "        SUBS   $temp,$temp,16\t! Count down dword pair in bytes\n"
-      "        B.ge   loop\t! Clearing loop\n"
-      "done16: ADDS   $temp,$temp,8\t! Room for 1 more long?\n"
-      "        B.lt   done\n"
-      "        STR    ZR,[$base+$temp]\n"
-      "done:"
-  %}
-  ins_encode %{
-    // TODO: preload?
-    __ mov($temp$$Register, $cnt$$Register);
-    __ add($ptr$$Register, $base$$Register, $cnt$$Register);
-    Label loop, done, done16;
-    __ subs($temp$$Register, $temp$$Register, 16);
-    __ b(done16, lt);
-    __ bind(loop);
-    __ stp(ZR, ZR, Address($ptr$$Register, -16, pre_indexed));
-    __ subs($temp$$Register, $temp$$Register, 16);
-    __ b(loop, ge);
-    __ bind(done16);
-    __ adds($temp$$Register, $temp$$Register, 8);
-    __ b(done, lt);
-    // $temp should be 0 here
-    __ str(ZR, Address($base$$Register, $temp$$Register));
-    __ bind(done);
-  %}
-  ins_pipe(long_memory_op);
-%}
-#else
+
 // Count and Base registers are fixed because the allocator cannot
 // kill unknown registers.  The encodings are generic.
 instruct clear_array(iRegX cnt, iRegP base, iRegI temp, iRegX zero, Universe dummy, flagsReg cpsr) %{
@@ -12104,7 +8991,6 @@
   %}
   ins_pipe(long_memory_op);
 %}
-#endif
 
 #ifdef XXX
 // FIXME: Why R0/R1/R2/R3?
@@ -12159,17 +9045,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct countLeadingZerosL(iRegI dst, iRegL src) %{
-  match(Set dst (CountLeadingZerosL src));
-  size(4);
-  format %{ "CLZ $dst,$src" %}
-  ins_encode %{
-    __ clz($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#else
 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegI tmp, flagsReg ccr) %{
   match(Set dst (CountLeadingZerosL src));
   effect(TEMP tmp, TEMP dst, KILL ccr);
@@ -12186,7 +9061,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 instruct countTrailingZerosI(iRegI dst, iRegI src, iRegI tmp) %{
   match(Set dst (CountTrailingZerosI src));
@@ -12201,20 +9075,6 @@
   ins_pipe(ialu_reg);
 %}
 
-#ifdef AARCH64
-instruct countTrailingZerosL(iRegI dst, iRegL src, iRegL tmp) %{
-  match(Set dst (CountTrailingZerosL src));
-  effect(TEMP tmp);
-  size(8);
-  format %{ "RBIT $tmp, $src\n\t"
-            "CLZ  $dst,$tmp" %}
-  ins_encode %{
-    __ rbit($tmp$$Register, $src$$Register);
-    __ clz($dst$$Register, $tmp$$Register);
-  %}
-  ins_pipe(ialu_reg);
-%}
-#else
 instruct countTrailingZerosL(iRegI dst, iRegL src, iRegI tmp, flagsReg ccr) %{
   match(Set dst (CountTrailingZerosL src));
   effect(TEMP tmp, TEMP dst, KILL ccr);
@@ -12235,37 +9095,10 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 
 //---------- Population Count Instructions -------------------------------------
 
-#ifdef AARCH64
-instruct popCountI(iRegI dst, iRegI src, regD_low tmp) %{
-  predicate(UsePopCountInstruction);
-  match(Set dst (PopCountI src));
-  effect(TEMP tmp);
-  size(20);
-
-  format %{ "MOV_W      $dst,$src\n\t"
-            "FMOV_dx    $tmp,$dst\n\t"
-            "VCNT       $tmp.8B,$tmp.8B\n\t"
-            "ADDV       $tmp.B,$tmp.8B\n\t"
-            "FMRS       $dst,$tmp" %}
-
-  ins_encode %{
-    __ mov_w($dst$$Register, $src$$Register);
-    __ fmov_dx($tmp$$FloatRegister, $dst$$Register);
-    int quad = 0;
-    int cnt_size = 0; // VELEM_SIZE_8
-    __ vcnt($tmp$$FloatRegister, $tmp$$FloatRegister, quad, cnt_size);
-    int add_size = 0; // VELEM_SIZE_8
-    __ addv($tmp$$FloatRegister, $tmp$$FloatRegister, quad, add_size);
-    __ fmrs($dst$$Register, $tmp$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else
 instruct popCountI(iRegI dst, iRegI src, regD_low tmp) %{
   predicate(UsePopCountInstruction);
   match(Set dst (PopCountI src));
@@ -12287,32 +9120,7 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif
-
-#ifdef AARCH64
-instruct popCountL(iRegI dst, iRegL src, regD tmp) %{
-  predicate(UsePopCountInstruction);
-  match(Set dst (PopCountL src));
-  effect(TEMP tmp);
-  size(16);
-
-  format %{ "FMOV_dx    $tmp,$src\n\t"
-            "VCNT       $tmp.8B,$tmp.8B\n\t"
-            "ADDV       $tmp.B,$tmp.8B\n\t"
-            "FMOV_ws    $dst,$tmp" %}
-
-  ins_encode %{
-    __ fmov_dx($tmp$$FloatRegister, $src$$Register);
-    int quad = 0;
-    int cnt_size = 0;
-    __ vcnt($tmp$$FloatRegister, $tmp$$FloatRegister, quad, cnt_size);
-    int add_size = 0;
-    __ addv($tmp$$FloatRegister, $tmp$$FloatRegister, quad, add_size);
-    __ fmov_ws($dst$$Register, $tmp$$FloatRegister);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else
+
 // Note: Long.bitCount(long) returns an int.
 instruct popCountL(iRegI dst, iRegL src, regD_low tmp) %{
   predicate(UsePopCountInstruction);
@@ -12338,7 +9146,6 @@
   %}
   ins_pipe(ialu_reg);
 %}
-#endif
 
 
 // ============================================================================
@@ -12350,26 +9157,13 @@
   size(4);
   format %{ "REV32 $dst,$src" %}
   ins_encode %{
-#ifdef AARCH64
-    __ rev_w($dst$$Register, $src$$Register);
-    // high 32 bits zeroed, not sign extended
-#else
     __ rev($dst$$Register, $src$$Register);
-#endif
   %}
   ins_pipe( iload_mem ); // FIXME
 %}
 
 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
   match(Set dst (ReverseBytesL src));
-#ifdef AARCH64
-//size(4);
-  format %{ "REV $dst,$src"  %}
-  ins_encode %{
-    __ rev($dst$$Register, $src$$Register);
-  %}
-  ins_pipe(ialu_reg_reg); // FIXME
-#else
   effect(TEMP dst);
   size(8);
   format %{ "REV $dst.lo,$src.lo\n\t"
@@ -12379,45 +9173,25 @@
     __ rev($dst$$Register->successor(), $src$$Register);
   %}
   ins_pipe( iload_mem ); // FIXME
-#endif
 %}
 
 instruct bytes_reverse_unsigned_short(iRegI dst, iRegI src) %{
   match(Set dst (ReverseBytesUS src));
-#ifdef AARCH64
-  size(4);
-  format %{ "REV16_W $dst,$src" %}
-  ins_encode %{
-    __ rev16_w($dst$$Register, $src$$Register);
-    // high 32 bits zeroed
-  %}
-#else
   size(4);
   format %{ "REV16 $dst,$src" %}
   ins_encode %{
     __ rev16($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe( iload_mem ); // FIXME
 %}
 
 instruct bytes_reverse_short(iRegI dst, iRegI src) %{
   match(Set dst (ReverseBytesS src));
-#ifdef AARCH64
-  size(8);
-  format %{ "REV16_W $dst,$src\n\t"
-            "SIGN_EXT16 $dst" %}
-  ins_encode %{
-    __ rev16_w($dst$$Register, $src$$Register);
-    __ sign_extend($dst$$Register, $dst$$Register, 16);
-  %}
-#else
   size(4);
   format %{ "REVSH $dst,$src" %}
   ins_encode %{
     __ revsh($dst$$Register, $src$$Register);
   %}
-#endif
   ins_pipe( iload_mem ); // FIXME
 %}
 
@@ -12476,7 +9250,6 @@
   ins_pipe(fstoreD_mem_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed byte values in Double register
 instruct Repl8B_reg(vecD dst, iRegI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 8);
@@ -12498,7 +9271,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed byte values in Double register
 instruct Repl8B_reg_simd(vecD dst, iRegI src) %{
@@ -12530,7 +9302,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl8B_immI(vecD dst, immI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 8);
@@ -12544,7 +9315,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (4), (1)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 // TODO: support negative constants with MVNI?
@@ -12577,7 +9347,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed short/char values into Double register
 instruct Repl4S_reg(vecD dst, iRegI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12597,7 +9366,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed byte values in Double register
 instruct Repl4S_reg_simd(vecD dst, iRegI src) %{
@@ -12630,7 +9398,6 @@
 %}
 
 
-#ifndef AARCH64
 // Replicate scalar constant to packed short/char values in Double register
 instruct Repl4S_immI(vecD dst, immI src, iRegP tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12644,7 +9411,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (2), (2)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl4S_immU8(vecD dst, immU8 src) %{
@@ -12676,7 +9442,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed int values in Double register
 instruct Repl2I_reg(vecD dst, iRegI src) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12707,7 +9472,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed int values in Double register
 instruct Repl2I_reg_simd(vecD dst, iRegI src) %{
@@ -12740,7 +9504,6 @@
 %}
 
 
-#ifndef AARCH64
 // Replicate scalar zero constant to packed int values in Double register
 instruct Repl2I_immI(vecD dst, immI src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12754,7 +9517,6 @@
   ins_encode( LdReplImmI(src, dst, tmp, (1), (4)) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar constant to packed byte values in Double register
 instruct Repl2I_immU8(vecD dst, immU8 src) %{
@@ -12786,23 +9548,6 @@
   ins_pipe(loadConFD); // FIXME
 %}
 
-#ifdef AARCH64
-// Replicate scalar to packed byte values in Double register pair
-instruct Repl2L_reg(vecX dst, iRegL src) %{
-  predicate(n->as_Vector()->length() == 2);
-  match(Set dst (ReplicateL src));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "VDUP.2D $dst.Q,$src\t" %}
-  ins_encode %{
-    bool quad = true;
-    __ vdupI($dst$$FloatRegister, $src$$Register,
-             MacroAssembler::VELEM_SIZE_64, quad);
-  %}
-  ins_pipe(ialu_reg); // FIXME
-%}
-#else /* !AARCH64 */
 // Replicate scalar to packed byte values in Double register pair
 instruct Repl2L_reg(vecX dst, iRegL src) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12847,7 +9592,6 @@
     Repl2F_regI(dst,tmp);
   %}
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed float values in Double register
 instruct Repl2F_reg_simd(vecD dst, regF src) %{
@@ -12864,7 +9608,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar to packed float values in Double register pair
 instruct Repl4F_reg(vecX dst, regF src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 4);
@@ -12884,7 +9627,6 @@
   %}
   ins_pipe(ialu_reg); // FIXME
 %}
-#endif /* !AARCH64 */
 
 // Replicate scalar to packed float values in Double register pair
 instruct Repl4F_reg_simd(vecX dst, regF src) %{
@@ -12901,7 +9643,6 @@
   ins_pipe(ialu_reg); // FIXME
 %}
 
-#ifndef AARCH64
 // Replicate scalar zero constant to packed float values in Double register
 instruct Repl2F_immI(vecD dst, immF src, iRegI tmp) %{
   predicate(n->as_Vector()->length() == 2);
@@ -12915,22 +9656,9 @@
   ins_encode( LdReplImmF(src, dst, tmp) );
   ins_pipe(loadConFD); // FIXME
 %}
-#endif /* !AAARCH64 */
 
 // Replicate scalar to packed double float values in Double register pair
 instruct Repl2D_reg(vecX dst, regD src) %{
-#ifdef AARCH64
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (ReplicateD src));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "VDUP     $dst.2D,$src\t" %}
-  ins_encode %{
-    bool quad = true;
-    __ vdupD($dst$$FloatRegister, $src$$FloatRegister, quad);
-  %}
-#else
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (ReplicateD src));
   size(4*2);
@@ -12945,7 +9673,6 @@
     FloatRegister dstb = dsta->successor()->successor();
     __ fcpyd(dstb, src);
   %}
-#endif
   ins_pipe(ialu_reg); // FIXME
 %}
 
@@ -13062,7 +9789,6 @@
   ins_pipe( faddD_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vadd2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (AddVF src1 src2));
@@ -13080,7 +9806,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 instruct vadd4F_reg_simd(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && VM_Version::simd_math_is_compliant());
@@ -13095,20 +9820,6 @@
   ins_pipe( faddD_reg_reg ); // FIXME
 %}
 
-#ifdef AARCH64
-instruct vadd2D_reg_simd(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::simd_math_is_compliant());
-  match(Set dst (AddVD src1 src2));
-  size(4);
-  format %{ "VADD.F64 $dst.Q,$src1.Q,$src2.Q\t! add packed2D" %}
-  ins_encode %{
-    bool quad = true;
-    __ vaddF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-  ins_pipe( faddD_reg_reg ); // FIXME
-%}
-#else
 instruct vadd4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (AddVF src1 src2));
@@ -13164,7 +9875,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 
 // Bytes vector sub
@@ -13276,7 +9986,6 @@
   ins_pipe( faddF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vsub2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (SubVF src1 src2));
@@ -13299,7 +10008,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 
 instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
@@ -13315,20 +10023,6 @@
   ins_pipe( faddF_reg_reg ); // FIXME
 %}
 
-#ifdef AARCH64
-instruct vsub2D_reg_simd(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::simd_math_is_compliant());
-  match(Set dst (SubVD src1 src2));
-  size(4);
-  format %{ "VSUB.F64 $dst.Q,$src1.Q,$src2.Q\t! add packed2D" %}
-  ins_encode %{
-    bool quad = true;
-    __ vsubF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-  ins_pipe( faddD_reg_reg ); // FIXME
-%}
-#else
 instruct vsub4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (SubVF src1 src2));
@@ -13384,7 +10078,6 @@
 
   ins_pipe(faddF_reg_reg); // FIXME
 %}
-#endif
 
 // Shorts/Chars vector mul
 instruct vmul4S_reg(vecD dst, vecD src1, vecD src2) %{
@@ -13449,7 +10142,6 @@
   ins_pipe( fmulF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vmul2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
   match(Set dst (MulVF src1 src2));
@@ -13467,7 +10159,6 @@
 
   ins_pipe(fmulF_reg_reg); // FIXME
 %}
-#endif
 
 instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && VM_Version::simd_math_is_compliant());
@@ -13481,7 +10172,6 @@
   ins_pipe( fmulF_reg_reg ); // FIXME
 %}
 
-#ifndef AARCH64
 instruct vmul4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
   match(Set dst (MulVF src1 src2));
@@ -13514,25 +10204,7 @@
 
   ins_pipe(fmulF_reg_reg); // FIXME
 %}
-#endif
-
-#ifdef AARCH64
-instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (MulVD src1 src2));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FMUL.2D $dst,$src1,$src2\t! double[2]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vmulF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-%}
-#else
+
 instruct vmul2D_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (MulVD src1 src2));
@@ -13554,26 +10226,12 @@
 
   ins_pipe(fmulD_reg_reg); // FIXME
 %}
-#endif
 
 
 // Floats vector div
 instruct vdiv2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (DivVF src1 src2));
-#ifdef AARCH64
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.2S $dst,$src1,$src2\t! float[2]" %}
-  ins_encode %{
-    int quad = 0;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F32, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-#else
   size(4*2);
   ins_cost(DEFAULT_COST*2); // FIXME
 
@@ -13587,25 +10245,11 @@
   %}
 
   ins_pipe(fdivF_reg_reg); // FIXME
-#endif
 %}
 
 instruct vdiv4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (DivVF src1 src2));
-#ifdef AARCH64
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.4S $dst,$src1,$src2\t! float[4]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F32, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-#else
   size(4*4);
   ins_cost(DEFAULT_COST*4); // FIXME
 
@@ -13634,26 +10278,8 @@
   %}
 
   ins_pipe(fdivF_reg_reg); // FIXME
-#endif
-%}
-
-#ifdef AARCH64
-instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{
-  predicate(n->as_Vector()->length() == 2 && VM_Version::has_simd());
-  match(Set dst (DivVD src1 src2));
-  size(4*1);
-  ins_cost(DEFAULT_COST*1); // FIXME
-
-  format %{ "FDIV.2D $dst,$src1,$src2\t! double[2]" %}
-  ins_encode %{
-    int quad = 1;
-    __ vdivF($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
-             MacroAssembler::VFA_SIZE_F64, quad);
-  %}
-
-  ins_pipe(fdivF_reg_reg); // FIXME
-%}
-#else
+%}
+
 instruct vdiv2D_reg_vfp(vecX dst, vecX src1, vecX src2) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (DivVD src1 src2));
@@ -13675,7 +10301,6 @@
 
   ins_pipe(fdivD_reg_reg); // FIXME
 %}
-#endif
 
 // --------------------------------- NEG --------------------------------------
 
--- a/src/hotspot/cpu/arm/arm_64.ad	Mon Oct 29 11:31:25 2018 -0700
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,998 +0,0 @@
-//
-// Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved.
-// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-//
-// This code is free software; you can redistribute it and/or modify it
-// under the terms of the GNU General Public License version 2 only, as
-// published by the Free Software Foundation.
-//
-// This code is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-// version 2 for more details (a copy is included in the LICENSE file that
-// accompanied this code).
-//
-// You should have received a copy of the GNU General Public License version
-// 2 along with this work; if not, write to the Free Software Foundation,
-// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-//
-// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-// or visit www.oracle.com if you need additional information or have any
-// questions.
-//
-
-// ARM Architecture Description File
-
-//----------REGISTER DEFINITION BLOCK------------------------------------------
-// This information is used by the matcher and the register allocator to
-// describe individual registers and classes of registers within the target
-// archtecture.
-register %{
-//----------Architecture Description Register Definitions----------------------
-// General Registers
-// "reg_def"  name ( register save type, C convention save type,
-//                   ideal register type, encoding, vm name );
-// Register Save Types:
-//
-// NS  = No-Save:       The register allocator assumes that these registers
-//                      can be used without saving upon entry to the method, &
-//                      that they do not need to be saved at call sites.
-//
-// SOC = Save-On-Call:  The register allocator assumes that these registers
-//                      can be used without saving upon entry to the method,
-//                      but that they must be saved at call sites.
-//
-// SOE = Save-On-Entry: The register allocator assumes that these registers
-//                      must be saved before using them upon entry to the
-//                      method, but they do not need to be saved at call
-//                      sites.
-//
-// AS  = Always-Save:   The register allocator assumes that these registers
-//                      must be saved before using them upon entry to the
-//                      method, & that they must be saved at call sites.
-//
-// Ideal Register Type is used to determine how to save & restore a
-// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
-// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
-// FIXME: above comment seems wrong.  Spill done through MachSpillCopyNode
-//
-// The encoding number is the actual bit-pattern placed into the opcodes.
-
-
-// ----------------------------
-// Integer/Long Registers
-// ----------------------------
-
-// TODO: would be nice to keep track of high-word state:
-// zeroRegI --> RegL
-// signedRegI --> RegL
-// junkRegI --> RegL
-// how to tell C2 to treak RegI as RegL, or RegL as RegI?
-reg_def R_R0  (SOC, SOC, Op_RegI,   0, R0->as_VMReg());
-reg_def R_R0x (SOC, SOC, Op_RegI, 255, R0->as_VMReg()->next());
-reg_def R_R1  (SOC, SOC, Op_RegI,   1, R1->as_VMReg());
-reg_def R_R1x (SOC, SOC, Op_RegI, 255, R1->as_VMReg()->next());
-reg_def R_R2  (SOC, SOC, Op_RegI,   2, R2->as_VMReg());
-reg_def R_R2x (SOC, SOC, Op_RegI, 255, R2->as_VMReg()->next());
-reg_def R_R3  (SOC, SOC, Op_RegI,   3, R3->as_VMReg());
-reg_def R_R3x (SOC, SOC, Op_RegI, 255, R3->as_VMReg()->next());
-reg_def R_R4  (SOC, SOC, Op_RegI,   4, R4->as_VMReg());
-reg_def R_R4x (SOC, SOC, Op_RegI, 255, R4->as_VMReg()->next());
-reg_def R_R5  (SOC, SOC, Op_RegI,   5, R5->as_VMReg());
-reg_def R_R5x (SOC, SOC, Op_RegI, 255, R5->as_VMReg()->next());
-reg_def R_R6  (SOC, SOC, Op_RegI,   6, R6->as_VMReg());
-reg_def R_R6x (SOC, SOC, Op_RegI, 255, R6->as_VMReg()->next());
-reg_def R_R7  (SOC, SOC, Op_RegI,   7, R7->as_VMReg());
-reg_def R_R7x (SOC, SOC, Op_RegI, 255, R7->as_VMReg()->next());
-
-reg_def R_R8  (SOC, SOC, Op_RegI,   8, R8->as_VMReg());
-reg_def R_R8x (SOC, SOC, Op_RegI, 255, R8->as_VMReg()->next());
-reg_def R_R9  (SOC, SOC, Op_RegI,   9, R9->as_VMReg());
-reg_def R_R9x (SOC, SOC, Op_RegI, 255, R9->as_VMReg()->next());
-reg_def R_R10 (SOC, SOC, Op_RegI,  10, R10->as_VMReg());
-reg_def R_R10x(SOC, SOC, Op_RegI, 255, R10->as_VMReg()->next());
-reg_def R_R11 (SOC, SOC, Op_RegI,  11, R11->as_VMReg());
-reg_def R_R11x(SOC, SOC, Op_RegI, 255, R11->as_VMReg()->next());
-reg_def R_R12 (SOC, SOC, Op_RegI,  12, R12->as_VMReg());
-reg_def R_R12x(SOC, SOC, Op_RegI, 255, R12->as_VMReg()->next());
-reg_def R_R13 (SOC, SOC, Op_RegI,  13, R13->as_VMReg());
-reg_def R_R13x(SOC, SOC, Op_RegI, 255, R13->as_VMReg()->next());
-reg_def R_R14 (SOC, SOC, Op_RegI,  14, R14->as_VMReg());
-reg_def R_R14x(SOC, SOC, Op_RegI, 255, R14->as_VMReg()->next());
-reg_def R_R15 (SOC, SOC, Op_RegI,  15, R15->as_VMReg());
-reg_def R_R15x(SOC, SOC, Op_RegI, 255, R15->as_VMReg()->next());
-
-reg_def R_R16 (SOC, SOC, Op_RegI,  16, R16->as_VMReg()); // IP0
-reg_def R_R16x(SOC, SOC, Op_RegI, 255, R16->as_VMReg()->next());
-reg_def R_R17 (SOC, SOC, Op_RegI,  17, R17->as_VMReg()); // IP1
-reg_def R_R17x(SOC, SOC, Op_RegI, 255, R17->as_VMReg()->next());
-reg_def R_R18 (SOC, SOC, Op_RegI,  18, R18->as_VMReg()); // Platform Register
-reg_def R_R18x(SOC, SOC, Op_RegI, 255, R18->as_VMReg()->next());
-
-reg_def R_R19 (SOC, SOE, Op_RegI,  19, R19->as_VMReg());
-reg_def R_R19x(SOC, SOE, Op_RegI, 255, R19->as_VMReg()->next());
-reg_def R_R20 (SOC, SOE, Op_RegI,  20, R20->as_VMReg());
-reg_def R_R20x(SOC, SOE, Op_RegI, 255, R20->as_VMReg()->next());
-reg_def R_R21 (SOC, SOE, Op_RegI,  21, R21->as_VMReg());
-reg_def R_R21x(SOC, SOE, Op_RegI, 255, R21->as_VMReg()->next());
-reg_def R_R22 (SOC, SOE, Op_RegI,  22, R22->as_VMReg());
-reg_def R_R22x(SOC, SOE, Op_RegI, 255, R22->as_VMReg()->next());
-reg_def R_R23 (SOC, SOE, Op_RegI,  23, R23->as_VMReg());
-reg_def R_R23x(SOC, SOE, Op_RegI, 255, R23->as_VMReg()->next());
-reg_def R_R24 (SOC, SOE, Op_RegI,  24, R24->as_VMReg());
-reg_def R_R24x(SOC, SOE, Op_RegI, 255, R24->as_VMReg()->next());
-reg_def R_R25 (SOC, SOE, Op_RegI,  25, R25->as_VMReg());
-reg_def R_R25x(SOC, SOE, Op_RegI, 255, R25->as_VMReg()->next());
-reg_def R_R26 (SOC, SOE, Op_RegI,  26, R26->as_VMReg());
-reg_def R_R26x(SOC, SOE, Op_RegI, 255, R26->as_VMReg()->next());
-reg_def R_R27 (SOC, SOE, Op_RegI,  27, R27->as_VMReg());         // Rheap_base
-reg_def R_R27x(SOC, SOE, Op_RegI, 255, R27->as_VMReg()->next()); // Rheap_base
-reg_def R_R28 ( NS, SOE, Op_RegI,  28, R28->as_VMReg());         // TLS
-reg_def R_R28x( NS, SOE, Op_RegI, 255, R28->as_VMReg()->next()); // TLS
-
-reg_def R_R29 ( NS, SOE, Op_RegI,  29, R29->as_VMReg());         // FP
-reg_def R_R29x( NS, SOE, Op_RegI, 255, R29->as_VMReg()->next()); // FP
-reg_def R_R30 (SOC, SOC, Op_RegI,  30, R30->as_VMReg());         // LR
-reg_def R_R30x(SOC, SOC, Op_RegI, 255, R30->as_VMReg()->next()); // LR
-
-reg_def R_ZR ( NS,  NS, Op_RegI,  31, ZR->as_VMReg());  // ZR
-reg_def R_ZRx( NS,  NS, Op_RegI, 255, ZR->as_VMReg()->next()); // ZR
-
-// FIXME
-//reg_def R_SP ( NS,  NS, Op_RegP,  32, SP->as_VMReg());
-reg_def R_SP ( NS,  NS, Op_RegI,  32, SP->as_VMReg());
-//reg_def R_SPx( NS, NS, Op_RegP, 255, SP->as_VMReg()->next());
-reg_def R_SPx( NS,  NS, Op_RegI, 255, SP->as_VMReg()->next());
-
-// ----------------------------
-// Float/Double/Vector Registers
-// ----------------------------
-
-reg_def  R_V0(SOC, SOC, Op_RegF,  0,  V0->as_VMReg());
-reg_def  R_V1(SOC, SOC, Op_RegF,  1,  V1->as_VMReg());
-reg_def  R_V2(SOC, SOC, Op_RegF,  2,  V2->as_VMReg());
-reg_def  R_V3(SOC, SOC, Op_RegF,  3,  V3->as_VMReg());
-reg_def  R_V4(SOC, SOC, Op_RegF,  4,  V4->as_VMReg());
-reg_def  R_V5(SOC, SOC, Op_RegF,  5,  V5->as_VMReg());
-reg_def  R_V6(SOC, SOC, Op_RegF,  6,  V6->as_VMReg());
-reg_def  R_V7(SOC, SOC, Op_RegF,  7,  V7->as_VMReg());
-reg_def  R_V8(SOC, SOC, Op_RegF,  8,  V8->as_VMReg());
-reg_def  R_V9(SOC, SOC, Op_RegF,  9,  V9->as_VMReg());
-reg_def R_V10(SOC, SOC, Op_RegF, 10, V10->as_VMReg());
-reg_def R_V11(SOC, SOC, Op_RegF, 11, V11->as_VMReg());
-reg_def R_V12(SOC, SOC, Op_RegF, 12, V12->as_VMReg());
-reg_def R_V13(SOC, SOC, Op_RegF, 13, V13->as_VMReg());
-reg_def R_V14(SOC, SOC, Op_RegF, 14, V14->as_VMReg());
-reg_def R_V15(SOC, SOC, Op_RegF, 15, V15->as_VMReg());
-reg_def R_V16(SOC, SOC, Op_RegF, 16, V16->as_VMReg());
-reg_def R_V17(SOC, SOC, Op_RegF, 17, V17->as_VMReg());
-reg_def R_V18(SOC, SOC, Op_RegF, 18, V18->as_VMReg());
-reg_def R_V19(SOC, SOC, Op_RegF, 19, V19->as_VMReg());
-reg_def R_V20(SOC, SOC, Op_RegF, 20, V20->as_VMReg());
-reg_def R_V21(SOC, SOC, Op_RegF, 21, V21->as_VMReg());
-reg_def R_V22(SOC, SOC, Op_RegF, 22, V22->as_VMReg());
-reg_def R_V23(SOC, SOC, Op_RegF, 23, V23->as_VMReg());
-reg_def R_V24(SOC, SOC, Op_RegF, 24, V24->as_VMReg());
-reg_def R_V25(SOC, SOC, Op_RegF, 25, V25->as_VMReg());
-reg_def R_V26(SOC, SOC, Op_RegF, 26, V26->as_VMReg());
-reg_def R_V27(SOC, SOC, Op_RegF, 27, V27->as_VMReg());
-reg_def R_V28(SOC, SOC, Op_RegF, 28, V28->as_VMReg());
-reg_def R_V29(SOC, SOC, Op_RegF, 29, V29->as_VMReg());
-reg_def R_V30(SOC, SOC, Op_RegF, 30, V30->as_VMReg());
-reg_def R_V31(SOC, SOC, Op_RegF, 31, V31->as_VMReg());
-
-reg_def  R_V0b(SOC, SOC, Op_RegF, 255, V0->as_VMReg()->next(1));
-reg_def  R_V1b(SOC, SOC, Op_RegF, 255, V1->as_VMReg()->next(1));
-reg_def  R_V2b(SOC, SOC, Op_RegF, 255, V2->as_VMReg()->next(1));
-reg_def  R_V3b(SOC, SOC, Op_RegF,  3,  V3->as_VMReg()->next(1));
-reg_def  R_V4b(SOC, SOC, Op_RegF,  4,  V4->as_VMReg()->next(1));
-reg_def  R_V5b(SOC, SOC, Op_RegF,  5,  V5->as_VMReg()->next(1));
-reg_def  R_V6b(SOC, SOC, Op_RegF,  6,  V6->as_VMReg()->next(1));
-reg_def  R_V7b(SOC, SOC, Op_RegF,  7,  V7->as_VMReg()->next(1));
-reg_def  R_V8b(SOC, SOC, Op_RegF, 255, V8->as_VMReg()->next(1));
-reg_def  R_V9b(SOC, SOC, Op_RegF,  9,  V9->as_VMReg()->next(1));
-reg_def R_V10b(SOC, SOC, Op_RegF, 10, V10->as_VMReg()->next(1));
-reg_def R_V11b(SOC, SOC, Op_RegF, 11, V11->as_VMReg()->next(1));
-reg_def R_V12b(SOC, SOC, Op_RegF, 12, V12->as_VMReg()->next(1));
-reg_def R_V13b(SOC, SOC, Op_RegF, 13, V13->as_VMReg()->next(1));
-reg_def R_V14b(SOC, SOC, Op_RegF, 14, V14->as_VMReg()->next(1));
-reg_def R_V15b(SOC, SOC, Op_RegF, 15, V15->as_VMReg()->next(1));
-reg_def R_V16b(SOC, SOC, Op_RegF, 16, V16->as_VMReg()->next(1));
-reg_def R_V17b(SOC, SOC, Op_RegF, 17, V17->as_VMReg()->next(1));
-reg_def R_V18b(SOC, SOC, Op_RegF, 18, V18->as_VMReg()->next(1));
-reg_def R_V19b(SOC, SOC, Op_RegF, 19, V19->as_VMReg()->next(1));
-reg_def R_V20b(SOC, SOC, Op_RegF, 20, V20->as_VMReg()->next(1));
-reg_def R_V21b(SOC, SOC, Op_RegF, 21, V21->as_VMReg()->next(1));
-reg_def R_V22b(SOC, SOC, Op_RegF, 22, V22->as_VMReg()->next(1));
-reg_def R_V23b(SOC, SOC, Op_RegF, 23, V23->as_VMReg()->next(1));
-reg_def R_V24b(SOC, SOC, Op_RegF, 24, V24->as_VMReg()->next(1));
-reg_def R_V25b(SOC, SOC, Op_RegF, 25, V25->as_VMReg()->next(1));
-reg_def R_V26b(SOC, SOC, Op_RegF, 26, V26->as_VMReg()->next(1));
-reg_def R_V27b(SOC, SOC, Op_RegF, 27, V27->as_VMReg()->next(1));
-reg_def R_V28b(SOC, SOC, Op_RegF, 28, V28->as_VMReg()->next(1));
-reg_def R_V29b(SOC, SOC, Op_RegF, 29, V29->as_VMReg()->next(1));
-reg_def R_V30b(SOC, SOC, Op_RegD, 30, V30->as_VMReg()->next(1));
-reg_def R_V31b(SOC, SOC, Op_RegF, 31, V31->as_VMReg()->next(1));
-
-reg_def  R_V0c(SOC, SOC, Op_RegF,  0,  V0->as_VMReg()->next(2));
-reg_def  R_V1c(SOC, SOC, Op_RegF,  1,  V1->as_VMReg()->next(2));
-reg_def  R_V2c(SOC, SOC, Op_RegF,  2,  V2->as_VMReg()->next(2));
-reg_def  R_V3c(SOC, SOC, Op_RegF,  3,  V3->as_VMReg()->next(2));
-reg_def  R_V4c(SOC, SOC, Op_RegF,  4,  V4->as_VMReg()->next(2));
-reg_def  R_V5c(SOC, SOC, Op_RegF,  5,  V5->as_VMReg()->next(2));
-reg_def  R_V6c(SOC, SOC, Op_RegF,  6,  V6->as_VMReg()->next(2));
-reg_def  R_V7c(SOC, SOC, Op_RegF,  7,  V7->as_VMReg()->next(2));
-reg_def  R_V8c(SOC, SOC, Op_RegF,  8,  V8->as_VMReg()->next(2));
-reg_def  R_V9c(SOC, SOC, Op_RegF,  9,  V9->as_VMReg()->next(2));
-reg_def R_V10c(SOC, SOC, Op_RegF, 10, V10->as_VMReg()->next(2));
-reg_def R_V11c(SOC, SOC, Op_RegF, 11, V11->as_VMReg()->next(2));
-reg_def R_V12c(SOC, SOC, Op_RegF, 12, V12->as_VMReg()->next(2));
-reg_def R_V13c(SOC, SOC, Op_RegF, 13, V13->as_VMReg()->next(2));
-reg_def R_V14c(SOC, SOC, Op_RegF, 14, V14->as_VMReg()->next(2));
-reg_def R_V15c(SOC, SOC, Op_RegF, 15, V15->as_VMReg()->next(2));
-reg_def R_V16c(SOC, SOC, Op_RegF, 16, V16->as_VMReg()->next(2));
-reg_def R_V17c(SOC, SOC, Op_RegF, 17, V17->as_VMReg()->next(2));
-reg_def R_V18c(SOC, SOC, Op_RegF, 18, V18->as_VMReg()->next(2));
-reg_def R_V19c(SOC, SOC, Op_RegF, 19, V19->as_VMReg()->next(2));
-reg_def R_V20c(SOC, SOC, Op_RegF, 20, V20->as_VMReg()->next(2));
-reg_def R_V21c(SOC, SOC, Op_RegF, 21, V21->as_VMReg()->next(2));
-reg_def R_V22c(SOC, SOC, Op_RegF, 22, V22->as_VMReg()->next(2));
-reg_def R_V23c(SOC, SOC, Op_RegF, 23, V23->as_VMReg()->next(2));
-reg_def R_V24c(SOC, SOC, Op_RegF, 24, V24->as_VMReg()->next(2));
-reg_def R_V25c(SOC, SOC, Op_RegF, 25, V25->as_VMReg()->next(2));
-reg_def R_V26c(SOC, SOC, Op_RegF, 26, V26->as_VMReg()->next(2));
-reg_def R_V27c(SOC, SOC, Op_RegF, 27, V27->as_VMReg()->next(2));
-reg_def R_V28c(SOC, SOC, Op_RegF, 28, V28->as_VMReg()->next(2));
-reg_def R_V29c(SOC, SOC, Op_RegF, 29, V29->as_VMReg()->next(2));
-reg_def R_V30c(SOC, SOC, Op_RegF, 30, V30->as_VMReg()->next(2));
-reg_def R_V31c(SOC, SOC, Op_RegF, 31, V31->as_VMReg()->next(2));
-
-reg_def  R_V0d(SOC, SOC, Op_RegF,  0,  V0->as_VMReg()->next(3));
-reg_def  R_V1d(SOC, SOC, Op_RegF,  1,  V1->as_VMReg()->next(3));
-reg_def  R_V2d(SOC, SOC, Op_RegF,  2,  V2->as_VMReg()->next(3));
-reg_def  R_V3d(SOC, SOC, Op_RegF,  3,  V3->as_VMReg()->next(3));
-reg_def  R_V4d(SOC, SOC, Op_RegF,  4,  V4->as_VMReg()->next(3));
-reg_def  R_V5d(SOC, SOC, Op_RegF,  5,  V5->as_VMReg()->next(3));
-reg_def  R_V6d(SOC, SOC, Op_RegF,  6,  V6->as_VMReg()->next(3));
-reg_def  R_V7d(SOC, SOC, Op_RegF,  7,  V7->as_VMReg()->next(3));
-reg_def  R_V8d(SOC, SOC, Op_RegF,  8,  V8->as_VMReg()->next(3));
-reg_def  R_V9d(SOC, SOC, Op_RegF,  9,  V9->as_VMReg()->next(3));
-reg_def R_V10d(SOC, SOC, Op_RegF, 10, V10->as_VMReg()->next(3));
-reg_def R_V11d(SOC, SOC, Op_RegF, 11, V11->as_VMReg()->next(3));
-reg_def R_V12d(SOC, SOC, Op_RegF, 12, V12->as_VMReg()->next(3));
-reg_def R_V13d(SOC, SOC, Op_RegF, 13, V13->as_VMReg()->next(3));
-reg_def R_V14d(SOC, SOC, Op_RegF, 14, V14->as_VMReg()->next(3));
-reg_def R_V15d(SOC, SOC, Op_RegF, 15, V15->as_VMReg()->next(3));
-reg_def R_V16d(SOC, SOC, Op_RegF, 16, V16->as_VMReg()->next(3));
-reg_def R_V17d(SOC, SOC, Op_RegF, 17, V17->as_VMReg()->next(3));
-reg_def R_V18d(SOC, SOC, Op_RegF, 18, V18->as_VMReg()->next(3));
-reg_def R_V19d(SOC, SOC, Op_RegF, 19, V19->as_VMReg()->next(3));
-reg_def R_V20d(SOC, SOC, Op_RegF, 20, V20->as_VMReg()->next(3));
-reg_def R_V21d(SOC, SOC, Op_RegF, 21, V21->as_VMReg()->next(3));
-reg_def R_V22d(SOC, SOC, Op_RegF, 22, V22->as_VMReg()->next(3));
-reg_def R_V23d(SOC, SOC, Op_RegF, 23, V23->as_VMReg()->next(3));
-reg_def R_V24d(SOC, SOC, Op_RegF, 24, V24->as_VMReg()->next(3));
-reg_def R_V25d(SOC, SOC, Op_RegF, 25, V25->as_VMReg()->next(3));
-reg_def R_V26d(SOC, SOC, Op_RegF, 26, V26->as_VMReg()->next(3));
-reg_def R_V27d(SOC, SOC, Op_RegF, 27, V27->as_VMReg()->next(3));
-reg_def R_V28d(SOC, SOC, Op_RegF, 28, V28->as_VMReg()->next(3));
-reg_def R_V29d(SOC, SOC, Op_RegF, 29, V29->as_VMReg()->next(3));
-reg_def R_V30d(SOC, SOC, Op_RegF, 30, V30->as_VMReg()->next(3));
-reg_def R_V31d(SOC, SOC, Op_RegF, 31, V31->as_VMReg()->next(3));
-
-// ----------------------------
-// Special Registers
-// Condition Codes Flag Registers
-reg_def APSR (SOC, SOC,  Op_RegFlags, 255, VMRegImpl::Bad());
-reg_def FPSCR(SOC, SOC,  Op_RegFlags, 255, VMRegImpl::Bad());
-
-// ----------------------------
-// Specify the enum values for the registers.  These enums are only used by the
-// OptoReg "class". We can convert these enum values at will to VMReg when needed
-// for visibility to the rest of the vm. The order of this enum influences the
-// register allocator so having the freedom to set this order and not be stuck
-// with the order that is natural for the rest of the vm is worth it.
-
-// Quad vector must be aligned here, so list them first.
-alloc_class fprs(
-    R_V8,  R_V8b,  R_V8c,  R_V8d,  R_V9,  R_V9b,  R_V9c,  R_V9d,
-    R_V10, R_V10b, R_V10c, R_V10d, R_V11, R_V11b, R_V11c, R_V11d,
-    R_V12, R_V12b, R_V12c, R_V12d, R_V13, R_V13b, R_V13c, R_V13d,
-    R_V14, R_V14b, R_V14c, R_V14d, R_V15, R_V15b, R_V15c, R_V15d,
-    R_V16, R_V16b, R_V16c, R_V16d, R_V17, R_V17b, R_V17c, R_V17d,
-    R_V18, R_V18b, R_V18c, R_V18d, R_V19, R_V19b, R_V19c, R_V19d,
-    R_V20, R_V20b, R_V20c, R_V20d, R_V21, R_V21b, R_V21c, R_V21d,
-    R_V22, R_V22b, R_V22c, R_V22d, R_V23, R_V23b, R_V23c, R_V23d,
-    R_V24, R_V24b, R_V24c, R_V24d, R_V25, R_V25b, R_V25c, R_V25d,
-    R_V26, R_V26b, R_V26c, R_V26d, R_V27, R_V27b, R_V27c, R_V27d,
-    R_V28, R_V28b, R_V28c, R_V28d, R_V29, R_V29b, R_V29c, R_V29d,
-    R_V30, R_V30b, R_V30c, R_V30d, R_V31, R_V31b, R_V31c, R_V31d,
-    R_V0,  R_V0b,  R_V0c,  R_V0d,  R_V1,  R_V1b,  R_V1c,  R_V1d,
-    R_V2,  R_V2b,  R_V2c,  R_V2d,  R_V3,  R_V3b,  R_V3c,  R_V3d,
-    R_V4,  R_V4b,  R_V4c,  R_V4d,  R_V5,  R_V5b,  R_V5c,  R_V5d,
-    R_V6,  R_V6b,  R_V6c,  R_V6d,  R_V7,  R_V7b,  R_V7c,  R_V7d
-);
-
-// Need double-register alignment here.
-// We are already quad-register aligned because of vectors above.
-alloc_class gprs(
-    R_R0,  R_R0x,  R_R1,  R_R1x,  R_R2,  R_R2x,  R_R3,  R_R3x,
-    R_R4,  R_R4x,  R_R5,  R_R5x,  R_R6,  R_R6x,  R_R7,  R_R7x,
-    R_R8,  R_R8x,  R_R9,  R_R9x,  R_R10, R_R10x, R_R11, R_R11x,
-    R_R12, R_R12x, R_R13, R_R13x, R_R14, R_R14x, R_R15, R_R15x,
-    R_R16, R_R16x, R_R17, R_R17x, R_R18, R_R18x, R_R19, R_R19x,
-    R_R20, R_R20x, R_R21, R_R21x, R_R22, R_R22x, R_R23, R_R23x,
-    R_R24, R_R24x, R_R25, R_R25x, R_R26, R_R26x, R_R27, R_R27x,
-    R_R28, R_R28x, R_R29, R_R29x, R_R30, R_R30x
-);
-// Continuing with double-reigister alignment...
-alloc_class chunk2(APSR, FPSCR);
-alloc_class chunk3(R_SP, R_SPx);
-alloc_class chunk4(R_ZR, R_ZRx);
-
-//----------Architecture Description Register Classes--------------------------
-// Several register classes are automatically defined based upon information in
-// this architecture description.
-// 1) reg_class inline_cache_reg           ( as defined in frame section )
-// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
-// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
-//
-
-// ----------------------------
-// Integer Register Classes
-// ----------------------------
-reg_class int_reg_all(R_R0,  R_R1,  R_R2,  R_R3,  R_R4,  R_R5,  R_R6,  R_R7,
-                      R_R8,  R_R9,  R_R10, R_R11, R_R12, R_R13, R_R14, R_R15,
-                      R_R16, R_R17, R_R18, R_R19, R_R20, R_R21, R_R22, R_R23,
-                      R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30
-);
-
-// Exclusions from i_reg:
-// SP (R31)
-// Rthread/R28: reserved by HotSpot to the TLS register (invariant within Java)
-reg_class int_reg %{
-    return _INT_REG_mask;
-%}
-reg_class ptr_reg %{
-    return _PTR_REG_mask;
-%}
-reg_class vectorx_reg %{
-    return _VECTORX_REG_mask;
-%}
-
-reg_class R0_regI(R_R0);
-reg_class R1_regI(R_R1);
-reg_class R2_regI(R_R2);
-reg_class R3_regI(R_R3);
-//reg_class R12_regI(R_R12);
-
-// ----------------------------
-// Pointer Register Classes
-// ----------------------------
-
-// Special class for storeP instructions, which can store SP or RPC to TLS.
-// It is also used for memory addressing, allowing direct TLS addressing.
-
-reg_class sp_ptr_reg %{
-    return _SP_PTR_REG_mask;
-%}
-
-reg_class store_reg %{
-    return _STR_REG_mask;
-%}
-
-reg_class store_ptr_reg %{
-    return _STR_PTR_REG_mask;
-%}
-
-reg_class spillP_reg %{
-    return _SPILLP_REG_mask;
-%}
-
-// Other special pointer regs
-reg_class R0_regP(R_R0, R_R0x);
-reg_class R1_regP(R_R1, R_R1x);
-reg_class R2_regP(R_R2, R_R2x);
-reg_class Rexception_regP(R_R19, R_R19x);
-reg_class Ricklass_regP(R_R8, R_R8x);
-reg_class Rmethod_regP(R_R27, R_R27x);
-
-reg_class Rthread_regP(R_R28, R_R28x);
-reg_class IP_regP(R_R16, R_R16x);
-#define RtempRegP IPRegP
-reg_class LR_regP(R_R30, R_R30x);
-
-reg_class SP_regP(R_SP,  R_SPx);
-reg_class FP_regP(R_R29, R_R29x);
-
-reg_class ZR_regP(R_ZR, R_ZRx);
-reg_class ZR_regI(R_ZR);
-
-// ----------------------------
-// Long Register Classes
-// ----------------------------
-reg_class long_reg %{ return _PTR_REG_mask; %}
-// for ldrexd, strexd: first reg of pair must be even
-reg_class long_reg_align %{ return LONG_REG_mask(); %}
-
-reg_class R0_regL(R_R0,R_R0x); // arg 1 or return value
-
-// ----------------------------
-// Special Class for Condition Code Flags Register
-reg_class int_flags(APSR);
-reg_class float_flags(FPSCR);
-
-
-// ----------------------------
-// Float Point Register Classes
-// ----------------------------
-reg_class sflt_reg_0(
-  R_V0,  R_V1,  R_V2,  R_V3,  R_V4,  R_V5,  R_V6,  R_V7,
-  R_V8,  R_V9,  R_V10, R_V11, R_V12, R_V13, R_V14, R_V15,
-  R_V16, R_V17, R_V18, R_V19, R_V20, R_V21, R_V22, R_V23,
-  R_V24, R_V25, R_V26, R_V27, R_V28, R_V29, R_V30, R_V31);
-
-reg_class sflt_reg %{
-    return _SFLT_REG_mask;
-%}
-
-reg_class dflt_low_reg %{
-    return _DFLT_REG_mask;
-%}
-
-reg_class actual_dflt_reg %{
-    return _DFLT_REG_mask;
-%}
-
-reg_class vectorx_reg_0(
-  R_V0,  R_V1,  R_V2,  R_V3,  R_V4,  R_V5, R_V6, R_V7,
-  R_V8,  R_V9,  R_V10, R_V11, R_V12, R_V13, R_V14, R_V15,
-  R_V16, R_V17, R_V18, R_V19, R_V20, R_V21, R_V22, R_V23,
-  R_V24, R_V25, R_V26, R_V27, R_V28, R_V29, R_V30, /*R_V31,*/
-  R_V0b,  R_V1b,  R_V2b,  R_V3b,  R_V4b,  R_V5b,  R_V6b,  R_V7b,
-  R_V8b,  R_V9b,  R_V10b, R_V11b, R_V12b, R_V13b, R_V14b, R_V15b,
-  R_V16b, R_V17b, R_V18b, R_V19b, R_V20b, R_V21b, R_V22b, R_V23b,
-  R_V24b, R_V25b, R_V26b, R_V27b, R_V28b, R_V29b, R_V30b, /*R_V31b,*/
-  R_V0c,  R_V1c,  R_V2c,  R_V3c,  R_V4c,  R_V5c,  R_V6c,  R_V7c,
-  R_V8c,  R_V9c,  R_V10c, R_V11c, R_V12c, R_V13c, R_V14c, R_V15c,
-  R_V16c, R_V17c, R_V18c, R_V19c, R_V20c, R_V21c, R_V22c, R_V23c,
-  R_V24c, R_V25c, R_V26c, R_V27c, R_V28c, R_V29c, R_V30c, /*R_V31c,*/
-  R_V0d,  R_V1d,  R_V2d,  R_V3d,  R_V4d,  R_V5d,  R_V6d,  R_V7d,
-  R_V8d,  R_V9d,  R_V10d, R_V11d, R_V12d, R_V13d, R_V14d, R_V15d,
-  R_V16d, R_V17d, R_V18d, R_V19d, R_V20d, R_V21d, R_V22d, R_V23d,
-  R_V24d, R_V25d, R_V26d, R_V27d, R_V28d, R_V29d, R_V30d, /*R_V31d*/);
-
-reg_class Rmemcopy_reg %{
-    return _RMEMCOPY_REG_mask;
-%}
-
-%}
-
-source_hpp %{
-
-const MachRegisterNumbers R_mem_copy_lo_num = R_V31_num;
-const MachRegisterNumbers R_mem_copy_hi_num = R_V31b_num;
-const FloatRegister Rmemcopy = V31;
-
-const MachRegisterNumbers R_hf_ret_lo_num = R_V0_num;
-const MachRegisterNumbers R_hf_ret_hi_num = R_V0b_num;
-const FloatRegister Rhfret = V0;
-
-extern OptoReg::Name R_Ricklass_num;
-extern OptoReg::Name R_Rmethod_num;
-extern OptoReg::Name R_tls_num;
-extern OptoReg::Name R_Rheap_base_num;
-
-extern RegMask _INT_REG_mask;
-extern RegMask _PTR_REG_mask;
-extern RegMask _SFLT_REG_mask;
-extern RegMask _DFLT_REG_mask;
-extern RegMask _VECTORX_REG_mask;
-extern RegMask _RMEMCOPY_REG_mask;
-extern RegMask _SP_PTR_REG_mask;
-extern RegMask _SPILLP_REG_mask;
-extern RegMask _STR_REG_mask;
-extern RegMask _STR_PTR_REG_mask;
-
-#define LDR_DOUBLE "LDR_D"
-#define LDR_FLOAT  "LDR_S"
-#define STR_DOUBLE "STR_D"
-#define STR_FLOAT  "STR_S"
-#define STR_64     "STR"
-#define LDR_64     "LDR"
-#define STR_32     "STR_W"
-#define LDR_32     "LDR_W"
-#define MOV_DOUBLE "FMOV_D"
-#define MOV_FLOAT  "FMOV_S"
-#define FMSR       "FMOV_SW"
-#define FMRS       "FMOV_WS"
-#define LDREX      "ldxr  "
-#define STREX      "stxr  "
-
-#define str_64     str
-#define ldr_64     ldr
-#define ldr_32     ldr_w
-#define ldrex      ldxr
-#define strex      stxr
-
-#define fmsr       fmov_sw
-#define fmrs       fmov_ws
-#define fconsts    fmov_s
-#define fconstd    fmov_d
-
-static inline bool is_uimm12(jlong imm, int shift) {
-  return Assembler::is_unsigned_imm_in_range(imm, 12, shift);
-}
-
-static inline bool is_memoryD(int offset) {
-  int scale = 3; // LogBytesPerDouble
-  return is_uimm12(offset, scale);
-}
-
-static inline bool is_memoryfp(int offset) {
-  int scale = LogBytesPerInt; // include 32-bit word accesses
-  return is_uimm12(offset, scale);
-}
-
-static inline bool is_memoryI(int offset) {
-  int scale = LogBytesPerInt;
-  return is_uimm12(offset, scale);
-}
-
-static inline bool is_memoryP(int offset) {
-  int scale = LogBytesPerWord;
-  return is_uimm12(offset, scale);
-}
-
-static inline bool is_memoryHD(int offset) {
-  int scale = LogBytesPerInt; // include 32-bit word accesses
-  return is_uimm12(offset, scale);
-}
-
-uintx limmL_low(uintx imm, int n);
-
-static inline bool Xis_aimm(int imm) {
-  return Assembler::ArithmeticImmediate(imm).is_encoded();
-}
-
-static inline bool is_aimm(intptr_t imm) {
-  return Assembler::ArithmeticImmediate(imm).is_encoded();
-}
-
-static inline bool is_limmL(uintptr_t imm) {
-  return Assembler::LogicalImmediate(imm).is_encoded();
-}
-
-static inline bool is_limmL_low(intptr_t imm, int n) {
-  return is_limmL(limmL_low(imm, n));
-}
-
-static inline bool is_limmI(jint imm) {
-  return Assembler::LogicalImmediate(imm, true).is_encoded();
-}
-
-static inline uintx limmI_low(jint imm, int n) {
-  return limmL_low(imm, n);
-}
-
-static inline bool is_limmI_low(jint imm, int n) {
-  return is_limmL_low(imm, n);
-}
-
-%}
-
-source %{
-
-// Given a register encoding, produce a Integer Register object
-static Register reg_to_register_object(int register_encoding) {
-  assert(R0->encoding() == R_R0_enc && R30->encoding() == R_R30_enc, "right coding");
-  assert(Rthread->encoding() == R_R28_enc, "right coding");
-  assert(SP->encoding() == R_SP_enc, "right coding");
-  return as_Register(register_encoding);
-}
-
-// Given a register encoding, produce a single-precision Float Register object
-static FloatRegister reg_to_FloatRegister_object(int register_encoding) {
-  assert(V0->encoding() == R_V0_enc && V31->encoding() == R_V31_enc, "right coding");
-  return as_FloatRegister(register_encoding);
-}
-
-RegMask _INT_REG_mask;
-RegMask _PTR_REG_mask;
-RegMask _SFLT_REG_mask;
-RegMask _DFLT_REG_mask;
-RegMask _VECTORX_REG_mask;
-RegMask _RMEMCOPY_REG_mask;
-RegMask _SP_PTR_REG_mask;
-RegMask _SPILLP_REG_mask;
-RegMask _STR_REG_mask;
-RegMask _STR_PTR_REG_mask;
-
-OptoReg::Name R_Ricklass_num = -1;
-OptoReg::Name R_Rmethod_num  = -1;
-OptoReg::Name R_tls_num      = -1;
-OptoReg::Name R_Rtemp_num    = -1;
-OptoReg::Name R_Rheap_base_num = -1;
-
-static int mov_oop_size = -1;
-
-#ifdef ASSERT
-static bool same_mask(const RegMask &a, const RegMask &b) {
-    RegMask a_sub_b = a; a_sub_b.SUBTRACT(b);
-    RegMask b_sub_a = b; b_sub_a.SUBTRACT(a);
-    return a_sub_b.Size() == 0 && b_sub_a.Size() == 0;
-}
-#endif
-
-void Compile::pd_compiler2_init() {
-
-    R_Ricklass_num = OptoReg::as_OptoReg(Ricklass->as_VMReg());
-    R_Rmethod_num  = OptoReg::as_OptoReg(Rmethod->as_VMReg());
-    R_tls_num      = OptoReg::as_OptoReg(Rthread->as_VMReg());
-    R_Rtemp_num    = OptoReg::as_OptoReg(Rtemp->as_VMReg());
-    R_Rheap_base_num = OptoReg::as_OptoReg(Rheap_base->as_VMReg());
-
-    _INT_REG_mask = _INT_REG_ALL_mask;
-    _INT_REG_mask.Remove(R_tls_num);
-    _INT_REG_mask.Remove(R_SP_num);
-    if (UseCompressedOops) {
-      _INT_REG_mask.Remove(R_Rheap_base_num);
-    }
-    // Remove Rtemp because safepoint poll can trash it
-    // (see SharedRuntime::generate_handler_blob)
-    _INT_REG_mask.Remove(R_Rtemp_num);
-
-    _PTR_REG_mask = _INT_REG_mask;
-    _PTR_REG_mask.smear_to_sets(2);
-
-    // STR_REG    = INT_REG+ZR
-    // SPILLP_REG = INT_REG+SP
-    // SP_PTR_REG = INT_REG+SP+TLS
-    _STR_REG_mask = _INT_REG_mask;
-    _SP_PTR_REG_mask = _STR_REG_mask;
-    _STR_REG_mask.Insert(R_ZR_num);
-    _SP_PTR_REG_mask.Insert(R_SP_num);
-    _SPILLP_REG_mask = _SP_PTR_REG_mask;
-    _SP_PTR_REG_mask.Insert(R_tls_num);
-    _STR_PTR_REG_mask = _STR_REG_mask;
-    _STR_PTR_REG_mask.smear_to_sets(2);
-    _SP_PTR_REG_mask.smear_to_sets(2);
-    _SPILLP_REG_mask.smear_to_sets(2);
-
-    _RMEMCOPY_REG_mask = RegMask(R_mem_copy_lo_num);
-assert(OptoReg::as_OptoReg(Rmemcopy->as_VMReg()) == R_mem_copy_lo_num, "!");
-
-    _SFLT_REG_mask = _SFLT_REG_0_mask;
-    _SFLT_REG_mask.SUBTRACT(_RMEMCOPY_REG_mask);
-    _DFLT_REG_mask = _SFLT_REG_mask;
-    _DFLT_REG_mask.smear_to_sets(2);
-    _VECTORX_REG_mask = _SFLT_REG_mask;
-    _VECTORX_REG_mask.smear_to_sets(4);
-    assert(same_mask(_VECTORX_REG_mask, _VECTORX_REG_0_mask), "!");
-
-#ifdef ASSERT
-    RegMask r((RegMask *)&SFLT_REG_mask());
-    r.smear_to_sets(2);
-    assert(same_mask(r, _DFLT_REG_mask), "!");
-#endif
-
-    if (VM_Version::prefer_moves_over_load_literal()) {
-      mov_oop_size = 4;
-    } else {
-      mov_oop_size = 1;
-    }
-
-    assert(Matcher::interpreter_method_oop_reg_encode() == Rmethod->encoding(), "should be");
-}
-
-uintx limmL_low(uintx imm, int n) {
-  // 1: try as is
-  if (is_limmL(imm)) {
-    return imm;
-  }
-  // 2: try low bits + all 0's
-  uintx imm0 = imm & right_n_bits(n);
-  if (is_limmL(imm0)) {
-    return imm0;
-  }
-  // 3: try low bits + all 1's
-  uintx imm1 = imm0 | left_n_bits(BitsPerWord - n);
-  if (is_limmL(imm1)) {
-    return imm1;
-  }
-#if 0
-  // 4: try low bits replicated
-  int field = 1 << log2_intptr(n + n - 1);
-  assert(field >= n, "!");
-  assert(field / n == 1, "!");
-  intptr_t immr = immx;
-  while (field < BitsPerWord) {
-    intrptr_t bits = immr & right_n_bits(field);
-    immr = bits | (bits << field);
-    field = field << 1;
-  }
-  // replicate at power-of-2 boundary
-  if (is_limmL(immr)) {
-    return immr;
-  }
-#endif
-  return imm;
-}
-
-// Convert the raw encoding form into the form expected by the
-// constructor for Address.
-Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
-  RelocationHolder rspec;
-  if (disp_reloc != relocInfo::none) {
-    rspec = Relocation::spec_simple(disp_reloc);
-  }
-
-  Register rbase = (base == 0xff) ? SP : as_Register(base);
-  if (index != 0xff) {
-    Register rindex = as_Register(index);
-    if (disp == 0x7fffffff) { // special value to indicate sign-extend
-      Address madr(rbase, rindex, ex_sxtw, scale);
-      madr._rspec = rspec;
-      return madr;
-    } else {
-      assert(disp == 0, "unsupported");
-      Address madr(rbase, rindex, ex_lsl, scale);
-      madr._rspec = rspec;
-      return madr;
-    }
-  } else {
-    assert(scale == 0, "not supported");
-    Address madr(rbase, disp);
-    madr._rspec = rspec;
-    return madr;
-  }
-}
-
-// Location of compiled Java return values.  Same as C
-OptoRegPair c2::return_value(int ideal_reg) {
-  assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
-  static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, R_R0_num,     R_R0_num,  R_hf_ret_lo_num,  R_hf_ret_lo_num, R_R0_num };
-  static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, R_R0x_num, OptoReg::Bad,     R_hf_ret_hi_num, R_R0x_num };
-  return OptoRegPair( hi[ideal_reg], lo[ideal_reg]);
-}
-
-// !!!!! Special hack to get all type of calls to specify the byte offset
-//       from the start of the call to the point where the return address
-//       will point.
-
-int MachCallStaticJavaNode::ret_addr_offset() {
-  bool far = (_method == NULL) ? maybe_far_call(this) : !cache_reachable();
-  bool patchable = _method != NULL;
-  int call_size = MacroAssembler::call_size(entry_point(), far, patchable);
-  return (call_size + (_method_handle_invoke ? 1 : 0)) * NativeInstruction::instruction_size;
-}
-
-int MachCallDynamicJavaNode::ret_addr_offset() {
-  bool far = !cache_reachable();
-  int call_size = MacroAssembler::call_size(entry_point(), far, true);
-  return (mov_oop_size + call_size) * NativeInstruction::instruction_size; 
-}
-
-int MachCallRuntimeNode::ret_addr_offset() {
-  int call_size = 0;
-  // TODO: check if Leaf nodes also need this
-  if (!is_MachCallLeaf()) {
-    // adr $temp, ret_addr
-    // str $temp, [SP + last_java_pc]
-    call_size += 2;
-  }
-  // bl or mov_slow; blr
-  bool far = maybe_far_call(this);
-  call_size += MacroAssembler::call_size(entry_point(), far, false);
-  return call_size * NativeInstruction::instruction_size;
-}
-
-%}
-
-// The intptr_t operand types, defined by textual substitution.
-// (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
-#define immX      immL
-#define iRegX     iRegL
-#define aimmX     aimmL
-#define limmX     limmL
-#define immX9     immL9
-#define LShiftX   LShiftL
-#define shimmX    immU6
-
-#define store_RegLd store_RegL
-
-//----------ATTRIBUTES---------------------------------------------------------
-//----------Operand Attributes-------------------------------------------------
-op_attrib op_cost(1);          // Required cost attribute
-
-//----------OPERANDS-----------------------------------------------------------
-// Operand definitions must precede instruction definitions for correct parsing
-// in the ADLC because operands constitute user defined types which are used in
-// instruction definitions.
-
-//----------Simple Operands----------------------------------------------------
-// Immediate Operands
-
-// Integer Immediate: 9-bit (including sign bit), so same as immI8?
-// FIXME: simm9 allows -256, but immI8 doesn't...
-operand simm9() %{
-  predicate(Assembler::is_imm_in_range(n->get_int(), 9, 0));
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-
-operand uimm12() %{
-  predicate(Assembler::is_unsigned_imm_in_range(n->get_int(), 12, 0));
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand aimmP() %{
-  predicate(n->get_ptr() == 0 || (is_aimm(n->get_ptr()) && ((ConPNode*)n)->type()->reloc() == relocInfo::none));
-  match(ConP);
-
-  op_cost(0);
-  // formats are generated automatically for constants and base registers
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Long Immediate: 12-bit - for addressing mode
-operand immL12() %{
-  predicate((-4096 < n->get_long()) && (n->get_long() < 4096));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Long Immediate: 9-bit - for addressing mode
-operand immL9() %{
-  predicate((-256 <= n->get_long()) && (n->get_long() < 256));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immIMov() %{
-  predicate(n->get_int() >> 16 == 0);
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immLMov() %{
-  predicate(n->get_long() >> 16 == 0);
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immUL12() %{
-  predicate(is_uimm12(n->get_long(), 0));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immUL12x2() %{
-  predicate(is_uimm12(n->get_long(), 1));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immUL12x4() %{
-  predicate(is_uimm12(n->get_long(), 2));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immUL12x8() %{
-  predicate(is_uimm12(n->get_long(), 3));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-operand immUL12x16() %{
-  predicate(is_uimm12(n->get_long(), 4));
-  match(ConL);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Used for long shift
-operand immU6() %{
-  predicate(0 <= n->get_int() && (n->get_int() <= 63));
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Used for register extended shift
-operand immI_0_4() %{
-  predicate(0 <= n->get_int() && (n->get_int() <= 4));
-  match(ConI);
-  op_cost(0);
-
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
-// Compressed Pointer Register
-operand iRegN() %{
-  constraint(ALLOC_IN_RC(int_reg));
-  match(RegN);
-  match(ZRRegN);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand SPRegP() %{
-  constraint(ALLOC_IN_RC(SP_regP));
-  match(RegP);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand ZRRegP() %{
-  constraint(ALLOC_IN_RC(ZR_regP));
-  match(RegP);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand ZRRegL() %{
-  constraint(ALLOC_IN_RC(ZR_regP));
-  match(RegL);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand ZRRegI() %{
-  constraint(ALLOC_IN_RC(ZR_regI));
-  match(RegI);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
-
-operand ZRRegN() %{
-  constraint(ALLOC_IN_RC(ZR_regI));
-  match(RegN);
-
-  format %{ %}
-  interface(REG_INTER);
-%}
--- a/src/hotspot/cpu/arm/assembler_arm.hpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/assembler_arm.hpp	Tue Oct 30 10:39:19 2018 -0400
@@ -40,29 +40,14 @@
   lsl, lsr, asr, ror
 };
 
-#ifdef AARCH64
-enum AsmExtendOp {
-  ex_uxtb, ex_uxth, ex_uxtw, ex_uxtx,
-  ex_sxtb, ex_sxth, ex_sxtw, ex_sxtx,
-
-  ex_lsl = ex_uxtx
-};
-#endif
 
 enum AsmOffset {
-#ifdef AARCH64
-  basic_offset = 0b00,
-  pre_indexed  = 0b11,
-  post_indexed = 0b01
-#else
   basic_offset = 1 << 24,
   pre_indexed  = 1 << 24 | 1 << 21,
   post_indexed = 0
-#endif
 };
 
 
-#ifndef AARCH64
 enum AsmWriteback {
   no_writeback,
   writeback
@@ -72,7 +57,6 @@
   sub_offset = 0,
   add_offset = 1
 };
-#endif
 
 
 // ARM Addressing Modes 2 and 3 - Load and store
@@ -84,21 +68,13 @@
   AsmOffset _mode;
   RelocationHolder   _rspec;
   int       _shift_imm;
-#ifdef AARCH64
-  AsmExtendOp _extend;
-#else
   AsmShift  _shift;
   AsmOffsetOp _offset_op;
 
   static inline int abs(int x) { return x < 0 ? -x : x; }
   static inline int up (int x) { return x < 0 ?  0 : 1; }
-#endif
 
-#ifdef AARCH64
-  static const AsmExtendOp LSL = ex_lsl;
-#else
   static const AsmShift LSL = lsl;
-#endif
 
  public:
   Address() : _base(noreg) {}
@@ -109,12 +85,8 @@
     _disp = offset;
     _mode = mode;
     _shift_imm = 0;
-#ifdef AARCH64
-    _extend = ex_lsl;
-#else
     _shift = lsl;
     _offset_op = add_offset;
-#endif
   }
 
 #ifdef ASSERT
@@ -124,27 +96,11 @@
     _disp = in_bytes(offset);
     _mode = mode;
     _shift_imm = 0;
-#ifdef AARCH64
-    _extend = ex_lsl;
-#else
     _shift = lsl;
     _offset_op = add_offset;
-#endif
   }
 #endif
 
-#ifdef AARCH64
-  Address(Register rn, Register rm, AsmExtendOp extend = ex_lsl, int shift_imm = 0) {
-    assert ((extend == ex_uxtw) || (extend == ex_lsl) || (extend == ex_sxtw) || (extend == ex_sxtx), "invalid extend for address mode");
-    assert ((0 <= shift_imm) && (shift_imm <= 4), "shift amount is out of range");
-    _base = rn;
-    _index = rm;
-    _disp = 0;
-    _mode = basic_offset;
-    _extend = extend;
-    _shift_imm = shift_imm;
-  }
-#else
   Address(Register rn, Register rm, AsmShift shift = lsl,
           int shift_imm = 0, AsmOffset mode = basic_offset,
           AsmOffsetOp offset_op = add_offset) {
@@ -181,7 +137,6 @@
     _mode = basic_offset;
     _offset_op = add_offset;
   }
-#endif // AARCH64
 
   // [base + index * wordSize]
   static Address indexed_ptr(Register base, Register index) {
@@ -211,25 +166,6 @@
     return a;
   }
 
-#ifdef AARCH64
-  int encoding_simd() const {
-    assert(_index != SP, "encoding constraint");
-    assert(_disp == 0 || _mode == post_indexed,  "encoding constraint");
-    assert(_index == noreg || _mode == basic_offset, "encoding constraint");
-    assert(_mode == basic_offset || _mode == post_indexed, "encoding constraint");
-    assert(_extend == ex_lsl, "encoding constraint");
-    int index;
-    if (_index == noreg) {
-      if (_mode == post_indexed)
-        index = 0b100 << 5 | 31;
-      else
-        index = 0;
-    } else {
-      index = 0b100 << 5 | _index->encoding();
-    }
-    return index << 16 | _base->encoding_with_sp() << 5;
-  }
-#else /* !AARCH64 */
   int encoding2() const {
     assert(_mode == basic_offset || _base != PC, "unpredictable instruction");
     if (_index == noreg) {
@@ -287,7 +223,6 @@
 
     return _base->encoding() << 16 | index;
   }
-#endif // !AARCH64
 
   Register base() const {
     return _base;
@@ -309,11 +244,6 @@
     return _shift_imm;
   }
 
-#ifdef AARCH64
-  AsmExtendOp extend() const {
-    return _extend;
-  }
-#else
   AsmShift shift() const {
     return _shift;
   }
@@ -321,7 +251,6 @@
   AsmOffsetOp offset_op() const {
     return _offset_op;
   }
-#endif
 
   bool uses(Register reg) const { return _base == reg || _index == reg; }
 
@@ -394,11 +323,7 @@
 };
 #endif
 
-#ifdef AARCH64
-#include "assembler_arm_64.hpp"
-#else
 #include "assembler_arm_32.hpp"
-#endif
 
 
 #endif // CPU_ARM_VM_ASSEMBLER_ARM_HPP
--- a/src/hotspot/cpu/arm/assembler_arm_64.cpp	Mon Oct 29 11:31:25 2018 -0700
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,186 +0,0 @@
-/*
- * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "asm/assembler.hpp"
-#include "asm/assembler.inline.hpp"
-#include "ci/ciEnv.hpp"
-#include "gc/shared/cardTableBarrierSet.hpp"
-#include "gc/shared/collectedHeap.inline.hpp"
-#include "interpreter/interpreter.hpp"
-#include "interpreter/interpreterRuntime.hpp"
-#include "interpreter/templateInterpreterGenerator.hpp"
-#include "memory/resourceArea.hpp"
-#include "prims/jvm_misc.hpp"
-#include "prims/methodHandles.hpp"
-#include "runtime/biasedLocking.hpp"
-#include "runtime/interfaceSupport.inline.hpp"
-#include "runtime/objectMonitor.hpp"
-#include "runtime/os.hpp"
-#include "runtime/sharedRuntime.hpp"
-#include "runtime/stubRoutines.hpp"
-#include "utilities/hashtable.hpp"
-#include "utilities/macros.hpp"
-
-// Returns whether given imm has equal bit fields <0:size-1> and <size:2*size-1>.
-inline bool Assembler::LogicalImmediate::has_equal_subpatterns(uintx imm, int size) {
-  uintx mask = right_n_bits(size);
-  uintx subpattern1 = mask_bits(imm, mask);
-  uintx subpattern2 = mask_bits(imm >> size, mask);
-  return subpattern1 == subpattern2;
-}
-
-// Returns least size that is a power of two from 2 to 64 with the proviso that given
-// imm is composed of repeating patterns of this size.
-inline int Assembler::LogicalImmediate::least_pattern_size(uintx imm) {
-  int size = BitsPerWord;
-  while (size > 2 && has_equal_subpatterns(imm, size >> 1)) {
-    size >>= 1;
-  }
-  return size;
-}
-
-// Returns count of set bits in given imm. Based on variable-precision SWAR algorithm.
-inline int Assembler::LogicalImmediate::population_count(uintx x) {
-  x -= ((x >> 1) & 0x5555555555555555L);
-  x = (((x >> 2) & 0x3333333333333333L) + (x & 0x3333333333333333L));
-  x = (((x >> 4) + x) & 0x0f0f0f0f0f0f0f0fL);
-  x += (x >> 8);
-  x += (x >> 16);
-  x += (x >> 32);
-  return(x & 0x7f);
-}
-
-// Let given x be <A:B> where B = 0 and least bit of A = 1. Returns <A:C>, where C is B-size set bits.
-inline uintx Assembler::LogicalImmediate::set_least_zeroes(uintx x) {
-  return x | (x - 1);
-}
-
-
-#ifdef ASSERT
-
-// Restores immediate by encoded bit masks.
-uintx Assembler::LogicalImmediate::decode() {
-  assert (_encoded, "should be");
-
-  int len_code = (_immN << 6) | ((~_imms) & 0x3f);
-  assert (len_code != 0, "should be");
-
-  int len = 6;
-  while (!is_set_nth_bit(len_code, len)) len--;
-  int esize = 1 << len;
-  assert (len > 0, "should be");
-  assert ((_is32bit ? 32 : 64) >= esize, "should be");
-
-  int levels = right_n_bits(len);
-  int S = _imms & levels;
-  int R = _immr & levels;
-
-  assert (S != levels, "should be");
-
-  uintx welem = right_n_bits(S + 1);
-  uintx wmask = (R == 0) ? welem : ((welem >> R) | (welem << (esize - R)));
-
-  for (int size = esize; size < 64; size <<= 1) {
-    wmask |= (wmask << size);
-  }
-
-  return wmask;
-}
-
-#endif
-
-
-// Constructs LogicalImmediate by given imm. Figures out if given imm can be used in AArch64 logical
-// instructions (AND, ANDS, EOR, ORR) and saves its encoding.
-void Assembler::LogicalImmediate::construct(uintx imm, bool is32) {
-  _is32bit = is32;
-
-  if (is32) {
-    assert(((imm >> 32) == 0) || (((intx)imm >> 31) == -1), "32-bit immediate is out of range");
-
-    // Replicate low 32 bits.
-    imm &= 0xffffffff;
-    imm |= imm << 32;
-  }
-
-  // All-zeroes and all-ones can not be encoded.
-  if (imm != 0 && (~imm != 0)) {
-
-    // Let LPS (least pattern size) be the least size (power of two from 2 to 64) of repeating
-    // patterns in the immediate. If immediate value can be encoded, it is encoded by pattern
-    // of exactly LPS size (due to structure of valid patterns). In order to verify
-    // that immediate value can be encoded, LPS is calculated and <LPS-1:0> bits of immediate
-    // are verified to be valid pattern.
-    int lps = least_pattern_size(imm);
-    uintx lps_mask = right_n_bits(lps);
-
-    // A valid pattern has one of the following forms:
-    //  | 0 x A | 1 x B | 0 x C |, where B > 0 and C > 0, or
-    //  | 1 x A | 0 x B | 1 x C |, where B > 0 and C > 0.
-    // For simplicity, the second form of the pattern is inverted into the first form.
-    bool inverted = imm & 0x1;
-    uintx pattern = (inverted ? ~imm : imm) & lps_mask;
-
-    //  | 0 x A | 1 x (B + C)   |
-    uintx without_least_zeroes = set_least_zeroes(pattern);
-
-    // Pattern is valid iff without least zeroes it is a power of two - 1.
-    if ((without_least_zeroes & (without_least_zeroes + 1)) == 0) {
-
-      // Count B as population count of pattern.
-      int bits_count = population_count(pattern);
-
-      // Count B+C as population count of pattern without least zeroes
-      int left_range = population_count(without_least_zeroes);
-
-      // S-prefix is a part of imms field which encodes LPS.
-      //  LPS  |  S prefix
-      //   64  |     not defined
-      //   32  |     0b0
-      //   16  |     0b10
-      //    8  |     0b110
-      //    4  |     0b1110
-      //    2  |     0b11110
-      int s_prefix = (lps == 64) ? 0 : ~set_least_zeroes(lps) & 0x3f;
-
-      // immN bit is set iff LPS == 64.
-      _immN = (lps == 64) ? 1 : 0;
-      assert (!is32 || (_immN == 0), "32-bit immediate should be encoded with zero N-bit");
-
-      // immr is the rotation size.
-      _immr = lps + (inverted ? 0 : bits_count) - left_range;
-
-      // imms is the field that encodes bits count and S-prefix.
-      _imms = ((inverted ? (lps - bits_count) : bits_count) - 1) | s_prefix;
-
-      _encoded = true;
-      assert (decode() == imm, "illegal encoding");
-
-      return;
-    }
-  }
-
-  _encoded = false;
-}
--- a/src/hotspot/cpu/arm/assembler_arm_64.hpp	Mon Oct 29 11:31:25 2018 -0700
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1718 +0,0 @@
-/*
- * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#ifndef CPU_ARM_VM_ASSEMBLER_ARM_64_HPP
-#define CPU_ARM_VM_ASSEMBLER_ARM_64_HPP
-
-enum AsmShift12 {
-  lsl0, lsl12
-};
-
-enum AsmPrefetchOp {
-    pldl1keep = 0b00000,
-    pldl1strm,
-    pldl2keep,
-    pldl2strm,
-    pldl3keep,
-    pldl3strm,
-
-    plil1keep = 0b01000,
-    plil1strm,
-    plil2keep,
-    plil2strm,
-    plil3keep,
-    plil3strm,
-
-    pstl1keep = 0b10000,
-    pstl1strm,
-    pstl2keep,
-    pstl2strm,
-    pstl3keep,
-    pstl3strm,
-};
-
-// Shifted register operand for data processing instructions.
-class AsmOperand {
- private:
-  Register _reg;
-  AsmShift _shift;
-  int _shift_imm;
-
- public:
-  AsmOperand(Register reg) {
-    assert(reg != SP, "SP is not allowed in shifted register operand");
-    _reg = reg;
-    _shift = lsl;
-    _shift_imm = 0;
-  }
-
-  AsmOperand(Register reg, AsmShift shift, int shift_imm) {
-    assert(reg != SP, "SP is not allowed in shifted register operand");
-    assert(shift_imm >= 0, "shift amount should be non-negative");
-    _reg = reg;
-    _shift = shift;
-    _shift_imm = shift_imm;
-  }
-
-  Register reg() const {
-    return _reg;
-  }
-
-  AsmShift shift() const {
-    return _shift;
-  }
-
-  int shift_imm() const {
-    return _shift_imm;
-  }
-};
-
-
-class Assembler : public AbstractAssembler  {
-
- public:
-
-  static const int LogInstructionSize = 2;
-  static const int InstructionSize    = 1 << LogInstructionSize;
-
-  Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
-
-  static inline AsmCondition inverse(AsmCondition cond) {
-    assert ((cond != al) && (cond != nv), "AL and NV conditions cannot be inversed");
-    return (AsmCondition)((int)cond ^ 1);
-  }
-
-  // Returns value of nzcv flags conforming to the given condition.
-  static inline int flags_for_condition(AsmCondition cond) {
-    switch(cond) {            // NZCV
-      case mi: case lt: return 0b1000;
-      case eq: case le: return 0b0100;
-      case hs: case hi: return 0b0010;
-      case vs:          return 0b0001;
-      default:          return 0b0000;
-    }
-  }
-
-  // Immediate, encoded into logical instructions.
-  class LogicalImmediate {
-   private:
-    bool _encoded;
-    bool _is32bit;
-    int _immN;
-    int _immr;
-    int _imms;
-
-    static inline bool has_equal_subpatterns(uintx imm, int size);
-    static inline int least_pattern_size(uintx imm);
-    static inline int population_count(uintx x);
-    static inline uintx set_least_zeroes(uintx x);
-
-#ifdef ASSERT
-    uintx decode();
-#endif
-
-    void construct(uintx imm, bool is32);
-
-   public:
-    LogicalImmediate(uintx imm, bool is32 = false) { construct(imm, is32); }
-
-    // Returns true if given immediate can be used in AArch64 logical instruction.
-    bool is_encoded() const { return _encoded; }
-
-    bool is32bit() const { return _is32bit; }
-    int immN() const { assert(_encoded, "should be"); return _immN; }
-    int immr() const { assert(_encoded, "should be"); return _immr; }
-    int imms() const { assert(_encoded, "should be"); return _imms; }
-  };
-
-  // Immediate, encoded into arithmetic add/sub instructions.
-  class ArithmeticImmediate {
-   private:
-    bool _encoded;
-    int _imm;
-    AsmShift12 _shift;
-
-   public:
-    ArithmeticImmediate(intx x) {
-      if (is_unsigned_imm_in_range(x, 12, 0)) {
-        _encoded = true;
-        _imm = x;
-        _shift = lsl0;
-      } else if (is_unsigned_imm_in_range(x, 12, 12)) {
-        _encoded = true;
-        _imm = x >> 12;
-        _shift = lsl12;
-      } else {
-        _encoded = false;
-      }
-    }
-
-    ArithmeticImmediate(intx x, AsmShift12 sh) {
-      if (is_unsigned_imm_in_range(x, 12, 0)) {
-        _encoded = true;
-        _imm = x;
-        _shift = sh;
-      } else {
-        _encoded = false;
-      }
-    }
-
-    // Returns true if this immediate can be used in AArch64 arithmetic (add/sub/cmp/cmn) instructions.
-    bool is_encoded() const  { return _encoded; }
-
-    int imm() const          { assert(_encoded, "should be"); return _imm; }
-    AsmShift12 shift() const { assert(_encoded, "should be"); return _shift; }
-  };
-
-  static inline bool is_imm_in_range(intx value, int bits, int align_bits) {
-    intx sign_bits = (value >> (bits + align_bits - 1));
-    return ((value & right_n_bits(align_bits)) == 0) && ((sign_bits == 0) || (sign_bits == -1));
-  }
-
-  static inline int encode_imm(intx value, int bits, int align_bits, int low_bit_in_encoding) {
-    assert (is_imm_in_range(value, bits, align_bits), "immediate value is out of range");
-    return ((value >> align_bits) & right_n_bits(bits)) << low_bit_in_encoding;
-  }
-
-  static inline bool is_unsigned_imm_in_range(intx value, int bits, int align_bits) {
-    return (value >= 0) && ((value & right_n_bits(align_bits)) == 0) && ((value >> (align_bits + bits)) == 0);
-  }
-
-  static inline int encode_unsigned_imm(intx value, int bits, int align_bits, int low_bit_in_encoding) {
-    assert (is_unsigned_imm_in_range(value, bits, align_bits), "immediate value is out of range");
-    return (value >> align_bits) << low_bit_in_encoding;
-  }
-
-  static inline bool is_offset_in_range(intx offset, int bits) {
-    assert (bits == 14 || bits == 19 || bits == 26, "wrong bits number");
-    return is_imm_in_range(offset, bits, 2);
-  }
-
-  static inline int encode_offset(intx offset, int bits, int low_bit_in_encoding) {
-    return encode_imm(offset, bits, 2, low_bit_in_encoding);
-  }
-
-  // Returns true if given value can be used as immediate in arithmetic (add/sub/cmp/cmn) instructions.
-  static inline bool is_arith_imm_in_range(intx value) {
-    return ArithmeticImmediate(value).is_encoded();
-  }
-
-
-  // Load/store instructions
-
-#define F(mnemonic, opc) \
-  void mnemonic(Register rd, address literal_addr) {                                                       \
-    intx offset = literal_addr - pc();                                                                     \
-    assert (opc != 0b01 || offset == 0 || ((uintx)literal_addr & 7) == 0, "ldr target should be aligned"); \
-    assert (is_offset_in_range(offset, 19), "offset is out of range");                                     \
-    emit_int32(opc << 30 | 0b011 << 27 | encode_offset(offset, 19, 5) | rd->encoding_with_zr());           \
-  }
-
-  F(ldr_w, 0b00)
-  F(ldr,   0b01)
-  F(ldrsw, 0b10)
-#undef F
-
-#define F(mnemonic, opc) \
-  void mnemonic(FloatRegister rt, address literal_addr) {                                                  \
-    intx offset = literal_addr - pc();                                                                     \
-    assert (offset == 0 || ((uintx)literal_addr & right_n_bits(2 + opc)) == 0, "ldr target should be aligned"); \
-    assert (is_offset_in_range(offset, 19), "offset is out of range");                                     \
-    emit_int32(opc << 30 | 0b011100 << 24 | encode_offset(offset, 19, 5) | rt->encoding());                \
-  }
-
-  F(ldr_s, 0b00)
-  F(ldr_d, 0b01)
-  F(ldr_q, 0b10)
-#undef F
-
-#define F(mnemonic, size, o2, L, o1, o0) \
-  void mnemonic(Register rt, Register rn) {                                                                \
-    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | 0b11111 << 16 |               \
-        o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());                  \
-  }
-
-  F(ldxrb,   0b00, 0, 1, 0, 0)
-  F(ldaxrb,  0b00, 0, 1, 0, 1)
-  F(ldarb,   0b00, 1, 1, 0, 1)
-  F(ldxrh,   0b01, 0, 1, 0, 0)
-  F(ldaxrh,  0b01, 0, 1, 0, 1)
-  F(ldarh,   0b01, 1, 1, 0, 1)
-  F(ldxr_w,  0b10, 0, 1, 0, 0)
-  F(ldaxr_w, 0b10, 0, 1, 0, 1)
-  F(ldar_w,  0b10, 1, 1, 0, 1)
-  F(ldxr,    0b11, 0, 1, 0, 0)
-  F(ldaxr,   0b11, 0, 1, 0, 1)
-  F(ldar,    0b11, 1, 1, 0, 1)
-
-  F(stlrb,   0b00, 1, 0, 0, 1)
-  F(stlrh,   0b01, 1, 0, 0, 1)
-  F(stlr_w,  0b10, 1, 0, 0, 1)
-  F(stlr,    0b11, 1, 0, 0, 1)
-#undef F
-
-#define F(mnemonic, size, o2, L, o1, o0) \
-  void mnemonic(Register rs, Register rt, Register rn) {                                                     \
-    assert (rs != rt, "should be different");                                                                \
-    assert (rs != rn, "should be different");                                                                \
-    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | rs->encoding_with_zr() << 16 |  \
-        o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());                    \
-  }
-
-  F(stxrb,   0b00, 0, 0, 0, 0)
-  F(stlxrb,  0b00, 0, 0, 0, 1)
-  F(stxrh,   0b01, 0, 0, 0, 0)
-  F(stlxrh,  0b01, 0, 0, 0, 1)
-  F(stxr_w,  0b10, 0, 0, 0, 0)
-  F(stlxr_w, 0b10, 0, 0, 0, 1)
-  F(stxr,    0b11, 0, 0, 0, 0)
-  F(stlxr,   0b11, 0, 0, 0, 1)
-#undef F
-
-#define F(mnemonic, size, o2, L, o1, o0) \
-  void mnemonic(Register rt, Register rt2, Register rn) {                                                  \
-    assert (rt != rt2, "should be different");                                                             \
-    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | 0b11111 << 16 |               \
-        o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());  \
-  }
-
-  F(ldxp_w,  0b10, 0, 1, 1, 0)
-  F(ldaxp_w, 0b10, 0, 1, 1, 1)
-  F(ldxp,    0b11, 0, 1, 1, 0)
-  F(ldaxp,   0b11, 0, 1, 1, 1)
-#undef F
-
-#define F(mnemonic, size, o2, L, o1, o0) \
-  void mnemonic(Register rs, Register rt, Register rt2, Register rn) {                                       \
-    assert (rs != rt, "should be different");                                                                \
-    assert (rs != rt2, "should be different");                                                               \
-    assert (rs != rn, "should be different");                                                                \
-    emit_int32(size << 30 | 0b001000 << 24 | o2 << 23 | L << 22 | o1 << 21 | rs->encoding_with_zr() << 16 |  \
-        o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());    \
-  }
-
-  F(stxp_w,  0b10, 0, 0, 1, 0)
-  F(stlxp_w, 0b10, 0, 0, 1, 1)
-  F(stxp,    0b11, 0, 0, 1, 0)
-  F(stlxp,   0b11, 0, 0, 1, 1)
-#undef F
-
-#define F(mnemonic, opc, V, L) \
-  void mnemonic(Register rt, Register rt2, Register rn, int offset = 0) {                                  \
-    assert (!L || rt != rt2, "should be different");                                                       \
-    int align_bits = 2 + (opc >> 1);                                                                       \
-    assert (is_imm_in_range(offset, 7, align_bits), "offset is out of range");                             \
-    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | L << 22 | encode_imm(offset, 7, align_bits, 15) |       \
-        rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr());             \
-  }
-
-  F(stnp_w,  0b00, 0, 0)
-  F(ldnp_w,  0b00, 0, 1)
-  F(stnp,    0b10, 0, 0)
-  F(ldnp,    0b10, 0, 1)
-#undef F
-
-#define F(mnemonic, opc, V, L) \
-  void mnemonic(FloatRegister rt, FloatRegister rt2, Register rn, int offset = 0) {                        \
-    assert (!L || (rt != rt2), "should be different");                                                     \
-    int align_bits = 2 + opc;                                                                              \
-    assert (is_imm_in_range(offset, 7, align_bits), "offset is out of range");                             \
-    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | L << 22 | encode_imm(offset, 7, align_bits, 15) |       \
-        rt2->encoding() << 10 | rn->encoding_with_sp() << 5 | rt->encoding());                             \
-  }
-
-  F(stnp_s,  0b00, 1, 0)
-  F(stnp_d,  0b01, 1, 0)
-  F(stnp_q,  0b10, 1, 0)
-  F(ldnp_s,  0b00, 1, 1)
-  F(ldnp_d,  0b01, 1, 1)
-  F(ldnp_q,  0b10, 1, 1)
-#undef F
-
-#define F(mnemonic, size, V, opc) \
-  void mnemonic(Register rt, Address addr) { \
-    assert((addr.mode() == basic_offset) || (rt != addr.base()), "should be different");                    \
-    if (addr.index() == noreg) {                                                                            \
-      if ((addr.mode() == basic_offset) && is_unsigned_imm_in_range(addr.disp(), 12, size)) {               \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \
-           encode_unsigned_imm(addr.disp(), 12, size, 10) |                                                 \
-           addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                                  \
-      } else {                                                                                              \
-        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \
-           addr.mode() << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());              \
-      }                                                                                                     \
-    } else {                                                                                                \
-      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \
-      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == size), "invalid shift amount");               \
-      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \
-         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \
-         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                       \
-    }                                                                                                       \
-  }
-
-  F(strb,    0b00, 0, 0b00)
-  F(ldrb,    0b00, 0, 0b01)
-  F(ldrsb,   0b00, 0, 0b10)
-  F(ldrsb_w, 0b00, 0, 0b11)
-
-  F(strh,    0b01, 0, 0b00)
-  F(ldrh,    0b01, 0, 0b01)
-  F(ldrsh,   0b01, 0, 0b10)
-  F(ldrsh_w, 0b01, 0, 0b11)
-
-  F(str_w,   0b10, 0, 0b00)
-  F(ldr_w,   0b10, 0, 0b01)
-  F(ldrsw,   0b10, 0, 0b10)
-
-  F(str,     0b11, 0, 0b00)
-  F(ldr,     0b11, 0, 0b01)
-#undef F
-
-#define F(mnemonic, size, V, opc) \
-  void mnemonic(AsmPrefetchOp prfop, Address addr) { \
-    assert (addr.mode() == basic_offset, #mnemonic " supports only basic_offset address mode");             \
-    if (addr.index() == noreg) {                                                                            \
-      if (is_unsigned_imm_in_range(addr.disp(), 12, size)) {                                                \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \
-           encode_unsigned_imm(addr.disp(), 12, size, 10) |                                                 \
-           addr.base()->encoding_with_sp() << 5 | prfop);                                                   \
-      } else {                                                                                              \
-        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \
-           addr.base()->encoding_with_sp() << 5 | prfop);                                                   \
-      }                                                                                                     \
-    } else {                                                                                                \
-      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \
-      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == size), "invalid shift amount");               \
-      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \
-         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \
-         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | prfop);                                        \
-    }                                                                                                       \
-  }
-
-  F(prfm, 0b11, 0, 0b10)
-#undef F
-
-#define F(mnemonic, size, V, opc) \
-  void mnemonic(FloatRegister rt, Address addr) { \
-    int align_bits = (((opc & 0b10) >> 1) << 2) | size;                                                     \
-    if (addr.index() == noreg) {                                                                            \
-      if ((addr.mode() == basic_offset) && is_unsigned_imm_in_range(addr.disp(), 12, align_bits)) {         \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | 0b01 << 24 | opc << 22 |                            \
-           encode_unsigned_imm(addr.disp(), 12, align_bits, 10) |                                           \
-           addr.base()->encoding_with_sp() << 5 | rt->encoding());                                          \
-      } else {                                                                                              \
-        assert(is_imm_in_range(addr.disp(), 9, 0), "offset is out of range");                               \
-        emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | encode_imm(addr.disp(), 9, 0, 12) |     \
-           addr.mode() << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding());                      \
-      }                                                                                                     \
-    } else {                                                                                                \
-      assert (addr.disp() == 0, "non-zero displacement for [reg + reg] address mode");                      \
-      assert ((addr.shift_imm() == 0) || (addr.shift_imm() == align_bits), "invalid shift amount");         \
-      emit_int32(size << 30 | 0b111 << 27 | V << 26 | opc << 22 | 1 << 21 |                                 \
-         addr.index()->encoding_with_zr() << 16 | addr.extend() << 13 | (addr.shift_imm() != 0) << 12 |     \
-         0b10 << 10 | addr.base()->encoding_with_sp() << 5 | rt->encoding());                               \
-    }                                                                                                       \
-  }
-
-  F(str_b, 0b00, 1, 0b00)
-  F(ldr_b, 0b00, 1, 0b01)
-  F(str_h, 0b01, 1, 0b00)
-  F(ldr_h, 0b01, 1, 0b01)
-  F(str_s, 0b10, 1, 0b00)
-  F(ldr_s, 0b10, 1, 0b01)
-  F(str_d, 0b11, 1, 0b00)
-  F(ldr_d, 0b11, 1, 0b01)
-  F(str_q, 0b00, 1, 0b10)
-  F(ldr_q, 0b00, 1, 0b11)
-#undef F
-
-#define F(mnemonic, opc, V, L) \
-  void mnemonic(Register rt, Register rt2, Address addr) {                                                         \
-    assert((addr.mode() == basic_offset) || ((rt != addr.base()) && (rt2 != addr.base())), "should be different"); \
-    assert(!L || (rt != rt2), "should be different");                                                              \
-    assert(addr.index() == noreg, "[reg + reg] address mode is not available for load/store pair");                \
-    int align_bits = 2 + (opc >> 1);                                                                               \
-    int mode_encoding = (addr.mode() == basic_offset) ? 0b10 : addr.mode();                                        \
-    assert(is_imm_in_range(addr.disp(), 7, align_bits), "offset is out of range");                                 \
-    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | mode_encoding << 23 | L << 22 |                                 \
-       encode_imm(addr.disp(), 7, align_bits, 15) | rt2->encoding_with_zr() << 10 |                                \
-       addr.base()->encoding_with_sp() << 5 | rt->encoding_with_zr());                                             \
-  }
-
-  F(stp_w, 0b00, 0, 0)
-  F(ldp_w, 0b00, 0, 1)
-  F(ldpsw, 0b01, 0, 1)
-  F(stp,   0b10, 0, 0)
-  F(ldp,   0b10, 0, 1)
-#undef F
-
-#define F(mnemonic, opc, V, L) \
-  void mnemonic(FloatRegister rt, FloatRegister rt2, Address addr) {                                                         \
-    assert(!L || (rt != rt2), "should be different");                                                              \
-    assert(addr.index() == noreg, "[reg + reg] address mode is not available for load/store pair");                \
-    int align_bits = 2 + opc;                                                                                      \
-    int mode_encoding = (addr.mode() == basic_offset) ? 0b10 : addr.mode();                                        \
-    assert(is_imm_in_range(addr.disp(), 7, align_bits), "offset is out of range");                                 \
-    emit_int32(opc << 30 | 0b101 << 27 | V << 26 | mode_encoding << 23 | L << 22 |                                 \
-       encode_imm(addr.disp(), 7, align_bits, 15) | rt2->encoding() << 10 |                                        \
-       addr.base()->encoding_with_sp() << 5 | rt->encoding());                                                     \
-  }
-
-  F(stp_s, 0b00, 1, 0)
-  F(ldp_s, 0b00, 1, 1)
-  F(stp_d, 0b01, 1, 0)
-  F(ldp_d, 0b01, 1, 1)
-  F(stp_q, 0b10, 1, 0)
-  F(ldp_q, 0b10, 1, 1)
-#undef F
-
-  // Data processing instructions
-
-#define F(mnemonic, sf, opc) \
-  void mnemonic(Register rd, Register rn, const LogicalImmediate& imm) {                      \
-    assert (imm.is_encoded(), "illegal immediate for logical instruction");                   \
-    assert (imm.is32bit() == (sf == 0), "immediate size does not match instruction size");    \
-    emit_int32(sf << 31 | opc << 29 | 0b100100 << 23 | imm.immN() << 22 | imm.immr() << 16 |  \
-        imm.imms() << 10 | rn->encoding_with_zr() << 5 |                                      \
-        ((opc == 0b11) ? rd->encoding_with_zr() : rd->encoding_with_sp()));                   \
-  }                                                                                           \
-  void mnemonic(Register rd, Register rn, uintx imm) {                                        \
-    LogicalImmediate limm(imm, (sf == 0));                                                    \
-    mnemonic(rd, rn, limm);                                                                   \
-  }                                                                                           \
-  void mnemonic(Register rd, Register rn, unsigned int imm) {                                 \
-    mnemonic(rd, rn, (uintx)imm);                                                             \
-  }
-
-  F(andr_w, 0, 0b00)
-  F(orr_w,  0, 0b01)
-  F(eor_w,  0, 0b10)
-  F(ands_w, 0, 0b11)
-
-  F(andr, 1, 0b00)
-  F(orr,  1, 0b01)
-  F(eor,  1, 0b10)
-  F(ands, 1, 0b11)
-#undef F
-
-  void tst(Register rn, unsigned int imm) {
-    ands(ZR, rn, imm);
-  }
-
-  void tst_w(Register rn, unsigned int imm) {
-    ands_w(ZR, rn, imm);
-  }
-
-#define F(mnemonic, sf, opc, N) \
-  void mnemonic(Register rd, Register rn, AsmOperand operand) { \
-    assert (operand.shift_imm() >> (5 + sf) == 0, "shift amount is too large");          \
-    emit_int32(sf << 31 | opc << 29 | 0b01010 << 24 | operand.shift() << 22 | N << 21 |  \
-        operand.reg()->encoding_with_zr() << 16 | operand.shift_imm() << 10 |            \
-        rn->encoding_with_zr() << 5 | rd->encoding_with_zr());                           \
-  }
-
-  F(andr_w, 0, 0b00, 0)
-  F(bic_w,  0, 0b00, 1)
-  F(orr_w,  0, 0b01, 0)
-  F(orn_w,  0, 0b01, 1)
-  F(eor_w,  0, 0b10, 0)
-  F(eon_w,  0, 0b10, 1)
-  F(ands_w, 0, 0b11, 0)
-  F(bics_w, 0, 0b11, 1)
-
-  F(andr, 1, 0b00, 0)
-  F(bic,  1, 0b00, 1)
-  F(orr,  1, 0b01, 0)
-  F(orn,  1, 0b01, 1)
-  F(eor,  1, 0b10, 0)
-  F(eon,  1, 0b10, 1)
-  F(ands, 1, 0b11, 0)
-  F(bics, 1, 0b11, 1)
-#undef F
-
-  void tst(Register rn, AsmOperand operand) {
-    ands(ZR, rn, operand);
-  }
-
-  void tst_w(Register rn, AsmOperand operand) {
-    ands_w(ZR, rn, operand);
-  }
-
-  void mvn(Register rd, AsmOperand operand) {
-    orn(rd, ZR, operand);
-  }
-
-  void mvn_w(Register rd, AsmOperand operand) {
-    orn_w(rd, ZR, operand);
-  }
-
-#define F(mnemonic, sf, op, S) \
-  void mnemonic(Register rd, Register rn, const ArithmeticImmediate& imm) {                       \
-    assert(imm.is_encoded(), "immediate is out of range");                                        \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b10001 << 24 | imm.shift() << 22 |                \
-        imm.imm() << 10 | rn->encoding_with_sp() << 5 |                                           \
-        (S == 1 ? rd->encoding_with_zr() : rd->encoding_with_sp()));                              \
-  }                                                                                               \
-  void mnemonic(Register rd, Register rn, int imm) {                                              \
-    mnemonic(rd, rn, ArithmeticImmediate(imm));                                                   \
-  }                                                                                               \
-  void mnemonic(Register rd, Register rn, int imm, AsmShift12 shift) {                            \
-    mnemonic(rd, rn, ArithmeticImmediate(imm, shift));                                            \
-  }                                                                                               \
-  void mnemonic(Register rd, Register rn, Register rm, AsmExtendOp extend, int shift_imm = 0) {   \
-    assert ((0 <= shift_imm) && (shift_imm <= 4), "shift amount is out of range");                \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b01011001 << 21 | rm->encoding_with_zr() << 16 |  \
-        extend << 13 | shift_imm << 10 | rn->encoding_with_sp() << 5 |                            \
-        (S == 1 ? rd->encoding_with_zr() : rd->encoding_with_sp()));                              \
-  }                                                                                               \
-  void mnemonic(Register rd, Register rn, AsmOperand operand) {                                   \
-    assert (operand.shift() != ror, "illegal shift type");                                        \
-    assert (operand.shift_imm() >> (5 + sf) == 0, "shift amount is too large");                   \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b01011 << 24 | operand.shift() << 22 |            \
-        operand.reg()->encoding_with_zr() << 16 | operand.shift_imm() << 10 |                     \
-        rn->encoding_with_zr() << 5 | rd->encoding_with_zr());                                    \
-  }
-
-  F(add_w,  0, 0, 0)
-  F(adds_w, 0, 0, 1)
-  F(sub_w,  0, 1, 0)
-  F(subs_w, 0, 1, 1)
-
-  F(add,    1, 0, 0)
-  F(adds,   1, 0, 1)
-  F(sub,    1, 1, 0)
-  F(subs,   1, 1, 1)
-#undef F
-
-  void mov(Register rd, Register rm) {
-    if ((rd == SP) || (rm == SP)) {
-      add(rd, rm, 0);
-    } else {
-      orr(rd, ZR, rm);
-    }
-  }
-
-  void mov_w(Register rd, Register rm) {
-    if ((rd == SP) || (rm == SP)) {
-      add_w(rd, rm, 0);
-    } else {
-      orr_w(rd, ZR, rm);
-    }
-  }
-
-  void cmp(Register rn, int imm) {
-    subs(ZR, rn, imm);
-  }
-
-  void cmp_w(Register rn, int imm) {
-    subs_w(ZR, rn, imm);
-  }
-
-  void cmp(Register rn, Register rm) {
-    assert (rm != SP, "SP should not be used as the 2nd operand of cmp");
-    if (rn == SP) {
-      subs(ZR, rn, rm, ex_uxtx);
-    } else {
-      subs(ZR, rn, rm);
-    }
-  }
-
-  void cmp_w(Register rn, Register rm) {
-    assert ((rn != SP) && (rm != SP), "SP should not be used in 32-bit cmp");
-    subs_w(ZR, rn, rm);
-  }
-
-  void cmp(Register rn, AsmOperand operand) {
-    assert (rn != SP, "SP is not allowed in cmp with shifted register (AsmOperand)");
-    subs(ZR, rn, operand);
-  }
-
-  void cmn(Register rn, int imm) {
-    adds(ZR, rn, imm);
-  }
-
-  void cmn_w(Register rn, int imm) {
-    adds_w(ZR, rn, imm);
-  }
-
-  void cmn(Register rn, Register rm) {
-    assert (rm != SP, "SP should not be used as the 2nd operand of cmp");
-    if (rn == SP) {
-      adds(ZR, rn, rm, ex_uxtx);
-    } else {
-      adds(ZR, rn, rm);
-    }
-  }
-
-  void cmn_w(Register rn, Register rm) {
-    assert ((rn != SP) && (rm != SP), "SP should not be used in 32-bit cmp");
-    adds_w(ZR, rn, rm);
-  }
-
-  void neg(Register rd, Register rm) {
-    sub(rd, ZR, rm);
-  }
-
-  void neg_w(Register rd, Register rm) {
-    sub_w(rd, ZR, rm);
-  }
-
-#define F(mnemonic, sf, op, S) \
-  void mnemonic(Register rd, Register rn, Register rm) { \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b11010000 << 21 | rm->encoding_with_zr() << 16 |   \
-        rn->encoding_with_zr() << 5 | rd->encoding_with_zr());                                     \
-  }
-
-  F(adc_w,  0, 0, 0)
-  F(adcs_w, 0, 0, 1)
-  F(sbc_w,  0, 1, 0)
-  F(sbcs_w, 0, 1, 1)
-
-  F(adc,    1, 0, 0)
-  F(adcs,   1, 0, 1)
-  F(sbc,    1, 1, 0)
-  F(sbcs,   1, 1, 1)
-#undef F
-
-#define F(mnemonic, sf, N) \
-  void mnemonic(Register rd, Register rn, Register rm, int lsb) { \
-    assert ((lsb >> (5 + sf)) == 0, "illegal least significant bit position");        \
-    emit_int32(sf << 31 | 0b100111 << 23 | N << 22 | rm->encoding_with_zr() << 16 |   \
-        lsb << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());            \
-  }
-
-  F(extr_w,  0, 0)
-  F(extr,    1, 1)
-#undef F
-
-#define F(mnemonic, sf, opc) \
-  void mnemonic(Register rd, int imm, int shift) { \
-    assert ((imm >> 16) == 0, "immediate is out of range");                       \
-    assert (((shift & 0xf) == 0) && ((shift >> (5 + sf)) == 0), "invalid shift"); \
-    emit_int32(sf << 31 | opc << 29 | 0b100101 << 23 | (shift >> 4) << 21 |       \
-        imm << 5 | rd->encoding_with_zr());                                       \
-  }
-
-  F(movn_w,  0, 0b00)
-  F(movz_w,  0, 0b10)
-  F(movk_w,  0, 0b11)
-  F(movn,    1, 0b00)
-  F(movz,    1, 0b10)
-  F(movk,    1, 0b11)
-#undef F
-
-  void mov(Register rd, int imm) {
-    assert ((imm >> 16) == 0, "immediate is out of range");
-    movz(rd, imm, 0);
-  }
-
-  void mov_w(Register rd, int imm) {
-    assert ((imm >> 16) == 0, "immediate is out of range");
-    movz_w(rd, imm, 0);
-  }
-
-#define F(mnemonic, sf, op, S) \
-  void mnemonic(Register rn, int imm, int nzcv, AsmCondition cond) { \
-    assert ((imm >> 5) == 0, "immediate is out of range");                      \
-    assert ((nzcv >> 4) == 0, "illegal nzcv");                                  \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b11010010 << 21 | imm << 16 |   \
-         cond << 12 | 1 << 11 | rn->encoding_with_zr() << 5 | nzcv);            \
-  }
-
-  F(ccmn_w, 0, 0, 1)
-  F(ccmp_w, 0, 1, 1)
-  F(ccmn,   1, 0, 1)
-  F(ccmp,   1, 1, 1)
-#undef F
-
-#define F(mnemonic, sf, op, S) \
-  void mnemonic(Register rn, Register rm, int nzcv, AsmCondition cond) { \
-    assert ((nzcv >> 4) == 0, "illegal nzcv");                                                    \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b11010010 << 21 | rm->encoding_with_zr() << 16 |  \
-        cond << 12 | rn->encoding_with_zr() << 5 | nzcv);                                         \
-  }
-
-  F(ccmn_w, 0, 0, 1)
-  F(ccmp_w, 0, 1, 1)
-  F(ccmn,   1, 0, 1)
-  F(ccmp,   1, 1, 1)
-#undef F
-
-#define F(mnemonic, sf, op, S, op2) \
-  void mnemonic(Register rd, Register rn, Register rm, AsmCondition cond) { \
-    emit_int32(sf << 31 | op << 30 | S << 29 | 0b11010100 << 21 | rm->encoding_with_zr() << 16 |  \
-        cond << 12 | op2 << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());           \
-  }
-
-  F(csel_w,  0, 0, 0, 0b00)
-  F(csinc_w, 0, 0, 0, 0b01)
-  F(csinv_w, 0, 1, 0, 0b00)
-  F(csneg_w, 0, 1, 0, 0b01)
-
-  F(csel,    1, 0, 0, 0b00)
-  F(csinc,   1, 0, 0, 0b01)
-  F(csinv,   1, 1, 0, 0b00)
-  F(csneg,   1, 1, 0, 0b01)
-#undef F
-
-  void cset(Register rd, AsmCondition cond) {
-    csinc(rd, ZR, ZR, inverse(cond));
-  }
-
-  void cset_w(Register rd, AsmCondition cond) {
-    csinc_w(rd, ZR, ZR, inverse(cond));
-  }
-
-  void csetm(Register rd, AsmCondition cond) {
-    csinv(rd, ZR, ZR, inverse(cond));
-  }
-
-  void csetm_w(Register rd, AsmCondition cond) {
-    csinv_w(rd, ZR, ZR, inverse(cond));
-  }
-
-  void cinc(Register rd, Register rn, AsmCondition cond) {
-    csinc(rd, rn, rn, inverse(cond));
-  }
-
-  void cinc_w(Register rd, Register rn, AsmCondition cond) {
-    csinc_w(rd, rn, rn, inverse(cond));
-  }
-
-  void cinv(Register rd, Register rn, AsmCondition cond) {
-    csinv(rd, rn, rn, inverse(cond));
-  }
-
-  void cinv_w(Register rd, Register rn, AsmCondition cond) {
-    csinv_w(rd, rn, rn, inverse(cond));
-  }
-
-#define F(mnemonic, sf, S, opcode) \
-  void mnemonic(Register rd, Register rn) { \
-    emit_int32(sf << 31 | 1 << 30 | S << 29 | 0b11010110 << 21 | opcode << 10 |  \
-        rn->encoding_with_zr() << 5 | rd->encoding_with_zr());                   \
-  }
-
-  F(rbit_w,  0, 0, 0b000000)
-  F(rev16_w, 0, 0, 0b000001)
-  F(rev_w,   0, 0, 0b000010)
-  F(clz_w,   0, 0, 0b000100)
-  F(cls_w,   0, 0, 0b000101)
-
-  F(rbit,    1, 0, 0b000000)
-  F(rev16,   1, 0, 0b000001)
-  F(rev32,   1, 0, 0b000010)
-  F(rev,     1, 0, 0b000011)
-  F(clz,     1, 0, 0b000100)
-  F(cls,     1, 0, 0b000101)
-#undef F
-
-#define F(mnemonic, sf, S, opcode) \
-  void mnemonic(Register rd, Register rn, Register rm) { \
-    emit_int32(sf << 31 | S << 29 | 0b11010110 << 21 | rm->encoding_with_zr() << 16 |  \
-        opcode << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());          \
-  }
-
-  F(udiv_w,  0, 0, 0b000010)
-  F(sdiv_w,  0, 0, 0b000011)
-  F(lslv_w,  0, 0, 0b001000)
-  F(lsrv_w,  0, 0, 0b001001)
-  F(asrv_w,  0, 0, 0b001010)
-  F(rorv_w,  0, 0, 0b001011)
-
-  F(udiv,    1, 0, 0b000010)
-  F(sdiv,    1, 0, 0b000011)
-  F(lslv,    1, 0, 0b001000)
-  F(lsrv,    1, 0, 0b001001)
-  F(asrv,    1, 0, 0b001010)
-  F(rorv,    1, 0, 0b001011)
-#undef F
-
-#define F(mnemonic, sf, op31, o0) \
-  void mnemonic(Register rd, Register rn, Register rm, Register ra) { \
-    emit_int32(sf << 31 | 0b11011 << 24 | op31 << 21 | rm->encoding_with_zr() << 16 |                     \
-        o0 << 15 | ra->encoding_with_zr() << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());  \
-  }
-
-  F(madd_w,  0, 0b000, 0)
-  F(msub_w,  0, 0b000, 1)
-  F(madd,    1, 0b000, 0)
-  F(msub,    1, 0b000, 1)
-
-  F(smaddl,  1, 0b001, 0)
-  F(smsubl,  1, 0b001, 1)
-  F(umaddl,  1, 0b101, 0)
-  F(umsubl,  1, 0b101, 1)
-#undef F
-
-  void mul(Register rd, Register rn, Register rm) {
-      madd(rd, rn, rm, ZR);
-  }
-
-  void mul_w(Register rd, Register rn, Register rm) {
-      madd_w(rd, rn, rm, ZR);
-  }
-
-#define F(mnemonic, sf, op31, o0) \
-  void mnemonic(Register rd, Register rn, Register rm) { \
-    emit_int32(sf << 31 | 0b11011 << 24 | op31 << 21 | rm->encoding_with_zr() << 16 |      \
-        o0 << 15 | 0b11111 << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());  \
-  }
-
-  F(smulh,   1, 0b010, 0)
-  F(umulh,   1, 0b110, 0)
-#undef F
-
-#define F(mnemonic, op) \
-  void mnemonic(Register rd, address addr) { \
-    intx offset;                                                        \
-    if (op == 0) {                                                      \
-      offset = addr - pc();                                             \
-    } else {                                                            \
-      offset = (((intx)addr) - (((intx)pc()) & ~0xfff)) >> 12;          \
-    }                                                                   \
-    assert (is_imm_in_range(offset, 21, 0), "offset is out of range");  \
-    emit_int32(op << 31 | (offset & 3) << 29 | 0b10000 << 24 |          \
-        encode_imm(offset >> 2, 19, 0, 5) | rd->encoding_with_zr());    \
-  }                                                                     \
-
-  F(adr,   0)
-  F(adrp,  1)
-#undef F
-
-  void adr(Register rd, Label& L) {
-    adr(rd, target(L));
-  }
-
-#define F(mnemonic, sf, opc, N)                                                \
-  void mnemonic(Register rd, Register rn, int immr, int imms) {                \
-    assert ((immr >> (5 + sf)) == 0, "immr is out of range");                  \
-    assert ((imms >> (5 + sf)) == 0, "imms is out of range");                  \
-    emit_int32(sf << 31 | opc << 29 | 0b100110 << 23 | N << 22 | immr << 16 |  \
-        imms << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr());    \
-  }
-
-  F(sbfm_w, 0, 0b00, 0)
-  F(bfm_w,  0, 0b01, 0)
-  F(ubfm_w, 0, 0b10, 0)
-
-  F(sbfm, 1, 0b00, 1)
-  F(bfm,  1, 0b01, 1)
-  F(ubfm, 1, 0b10, 1)
-#undef F
-
-#define F(alias, mnemonic, sf, immr, imms) \
-  void alias(Register rd, Register rn, int lsb, int width) {                        \
-    assert ((lsb >> (5 + sf)) == 0, "lsb is out of range");                         \
-    assert ((1 <= width) && (width <= (32 << sf) - lsb), "width is out of range");  \
-    mnemonic(rd, rn, immr, imms);                                                   \
-  }
-
-  F(bfi_w,   bfm_w,  0, (-lsb) & 0x1f, width - 1)
-  F(bfi,     bfm,    1, (-lsb) & 0x3f, width - 1)
-  F(bfxil_w, bfm_w,  0, lsb,           lsb + width - 1)
-  F(bfxil,   bfm,    1, lsb,           lsb + width - 1)
-  F(sbfiz_w, sbfm_w, 0, (-lsb) & 0x1f, width - 1)
-  F(sbfiz,   sbfm,   1, (-lsb) & 0x3f, width - 1)
-  F(sbfx_w,  sbfm_w, 0, lsb,           lsb + width - 1)
-  F(sbfx,    sbfm,   1, lsb,           lsb + width - 1)
-  F(ubfiz_w, ubfm_w, 0, (-lsb) & 0x1f, width - 1)
-  F(ubfiz,   ubfm,   1, (-lsb) & 0x3f, width - 1)
-  F(ubfx_w,  ubfm_w, 0, lsb,           lsb + width - 1)
-  F(ubfx,    ubfm,   1, lsb,           lsb + width - 1)
-#undef F
-
-#define F(alias, mnemonic, sf, immr, imms) \
-  void alias(Register rd, Register rn, int shift) {              \
-    assert ((shift >> (5 + sf)) == 0, "shift is out of range");  \
-    mnemonic(rd, rn, immr, imms);                                \
-  }
-
-  F(_asr_w, sbfm_w, 0, shift, 31)
-  F(_asr,   sbfm,   1, shift, 63)
-  F(_lsl_w, ubfm_w, 0, (-shift) & 0x1f, 31 - shift)
-  F(_lsl,   ubfm,   1, (-shift) & 0x3f, 63 - shift)
-  F(_lsr_w, ubfm_w, 0, shift, 31)
-  F(_lsr,   ubfm,   1, shift, 63)
-#undef F
-
-#define F(alias, mnemonic, immr, imms) \
-  void alias(Register rd, Register rn) {   \
-    mnemonic(rd, rn, immr, imms);          \
-  }
-
-  F(sxtb_w, sbfm_w, 0, 7)
-  F(sxtb,   sbfm,   0, 7)
-  F(sxth_w, sbfm_w, 0, 15)
-  F(sxth,   sbfm,   0, 15)
-  F(sxtw,   sbfm,   0, 31)
-  F(uxtb_w, ubfm_w, 0, 7)
-  F(uxtb,   ubfm,   0, 7)
-  F(uxth_w, ubfm_w, 0, 15)
-  F(uxth,   ubfm,   0, 15)
-#undef F
-
-  // Branch instructions
-
-#define F(mnemonic, op) \
-  void mnemonic(Register rn) {                                                             \
-    emit_int32(0b1101011 << 25 | op << 21 | 0b11111 << 16 | rn->encoding_with_zr() << 5);  \
-  }
-
-  F(br,  0b00)
-  F(blr, 0b01)
-  F(ret, 0b10)
-#undef F
-
-  void ret() {
-    ret(LR);
-  }
-
-#define F(mnemonic, op) \
-  void mnemonic(address target) {                                         \
-    intx offset = target - pc();                                          \
-    assert (is_offset_in_range(offset, 26), "offset is out of range");    \
-    emit_int32(op << 31 | 0b00101 << 26 | encode_offset(offset, 26, 0));  \
-  }
-
-  F(b,  0)
-  F(bl, 1)
-#undef F
-
-  void b(address target, AsmCondition cond) {
-    if (cond == al) {
-      b(target);
-    } else {
-      intx offset = target - pc();
-      assert (is_offset_in_range(offset, 19), "offset is out of range");
-      emit_int32(0b0101010 << 25 | encode_offset(offset, 19, 5) | cond);
-    }
-  }
-
-
-#define F(mnemonic, sf, op)                                             \
-  void mnemonic(Register rt, address target) {                          \
-    intx offset = target - pc();                                        \
-    assert (is_offset_in_range(offset, 19), "offset is out of range");  \
-    emit_int32(sf << 31 | 0b011010 << 25 | op << 24 | encode_offset(offset, 19, 5) | rt->encoding_with_zr()); \
-  }                                                                     \
-
-  F(cbz_w,  0, 0)
-  F(cbnz_w, 0, 1)
-  F(cbz,    1, 0)
-  F(cbnz,   1, 1)
-#undef F
-
-#define F(mnemonic, op)                                                 \
-  void mnemonic(Register rt, int bit, address target) {                 \
-    intx offset = target - pc();                                        \
-    assert (is_offset_in_range(offset, 14), "offset is out of range");  \
-    assert (0 <= bit && bit < 64, "bit number is out of range");        \
-    emit_int32((bit >> 5) << 31 | 0b011011 << 25 | op << 24 | (bit & 0x1f) << 19 | \
-        encode_offset(offset, 14, 5) | rt->encoding_with_zr());         \
-  }                                                                     \
-
-  F(tbz,  0)
-  F(tbnz, 1)
-#undef F
-
-  // System instructions
-
-  enum DMB_Opt {
-    DMB_ld  = 0b1101,
-    DMB_st  = 0b1110,
-    DMB_all = 0b1111
-  };
-
-#define F(mnemonic, L, op0, op1, CRn, op2, Rt) \
-  void mnemonic(DMB_Opt option) {                                       \
-    emit_int32(0b1101010100 << 22 | L << 21 | op0 << 19 | op1 << 16 |   \
-        CRn << 12 | option << 8 | op2 << 5 | Rt);                       \
-  }
-
-  F(dsb,  0, 0b00, 0b011, 0b0011, 0b100, 0b11111)
-  F(dmb,  0, 0b00, 0b011, 0b0011, 0b101, 0b11111)
-#undef F
-
-#define F(mnemonic, L, op0, op1, CRn, Rt) \
-  void mnemonic(int imm) {                                              \
-    assert ((imm >> 7) == 0, "immediate is out of range");              \
-    emit_int32(0b1101010100 << 22 | L << 21 | op0 << 19 | op1 << 16 |   \
-        CRn << 12 | imm << 5 | Rt);                                     \
-  }
-
-  F(hint, 0, 0b00, 0b011, 0b0010, 0b11111)
-#undef F
-
-  void nop() {
-    hint(0);
-  }
-
-  void yield() {
-    hint(1);
-  }
-
-#define F(mnemonic, opc, op2, LL) \
-  void mnemonic(int imm = 0) {                                           \
-    assert ((imm >> 16) == 0, "immediate is out of range");              \
-    emit_int32(0b11010100 << 24 | opc << 21 | imm << 5 | op2 << 2 | LL); \
-  }
-
-  F(brk, 0b001, 0b000, 0b00)
-  F(hlt, 0b010, 0b000, 0b00)
-  F(dpcs1, 0b101, 0b000, 0b01)
-#undef F
-
-  enum SystemRegister { // o0<1> op1<3> CRn<4> CRm<4> op2<3>
-    SysReg_NZCV = 0b101101000010000,
-    SysReg_FPCR = 0b101101000100000,
-  };
-
-  void mrs(Register rt, SystemRegister systemReg) {
-    assert ((systemReg >> 15) == 0, "systemReg is out of range");
-    emit_int32(0b110101010011 << 20 | systemReg << 5 | rt->encoding_with_zr());
-  }
-
-  void msr(SystemRegister systemReg, Register rt) {
-    assert ((systemReg >> 15) == 0, "systemReg is out of range");
-    emit_int32(0b110101010001 << 20 | systemReg << 5 | rt->encoding_with_zr());
-  }
-
-  // Floating-point instructions
-
-#define F(mnemonic, M, S, type, opcode2) \
-  void mnemonic(FloatRegister rn, FloatRegister rm) {                         \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |     \
-        rm->encoding() << 16 | 0b1000 << 10 | rn->encoding() << 5 | opcode2); \
-  }
-
-  F(fcmp_s,   0, 0, 0b00, 0b00000)
-  F(fcmpe_s,  0, 0, 0b00, 0b01000)
-  F(fcmp_d,   0, 0, 0b01, 0b00000)
-  F(fcmpe_d,  0, 0, 0b01, 0b10000)
-#undef F
-
-#define F(mnemonic, M, S, type, opcode2) \
-  void mnemonic(FloatRegister rn) {                                           \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |     \
-        0b1000 << 10 | rn->encoding() << 5 | opcode2);                        \
-  }
-
-  F(fcmp0_s,   0, 0, 0b00, 0b01000)
-  F(fcmpe0_s,  0, 0, 0b00, 0b11000)
-  F(fcmp0_d,   0, 0, 0b01, 0b01000)
-  F(fcmpe0_d,  0, 0, 0b01, 0b11000)
-#undef F
-
-#define F(mnemonic, M, S, type, op) \
-  void mnemonic(FloatRegister rn, FloatRegister rm, int nzcv, AsmCondition cond) { \
-    assert ((nzcv >> 4) == 0, "illegal nzcv");                                                  \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |                       \
-        rm->encoding() << 16 | cond << 12 | 0b01 << 10 | rn->encoding() << 5 | op << 4 | nzcv); \
-  }
-
-  F(fccmp_s,   0, 0, 0b00, 0)
-  F(fccmpe_s,  0, 0, 0b00, 1)
-  F(fccmp_d,   0, 0, 0b01, 0)
-  F(fccmpe_d,  0, 0, 0b01, 1)
-#undef F
-
-#define F(mnemonic, M, S, type) \
-  void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm, AsmCondition cond) { \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |                       \
-        rm->encoding() << 16 | cond << 12 | 0b11 << 10 | rn->encoding() << 5 | rd->encoding()); \
-  }
-
-  F(fcsel_s,   0, 0, 0b00)
-  F(fcsel_d,   0, 0, 0b01)
-#undef F
-
-#define F(mnemonic, M, S, type, opcode) \
-  void mnemonic(FloatRegister rd, FloatRegister rn) { \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |      \
-        opcode << 15 | 0b10000 << 10 | rn->encoding() << 5 | rd->encoding());  \
-  }
-
-  F(fmov_s,   0, 0, 0b00, 0b000000)
-  F(fabs_s,   0, 0, 0b00, 0b000001)
-  F(fneg_s,   0, 0, 0b00, 0b000010)
-  F(fsqrt_s,  0, 0, 0b00, 0b000011)
-  F(fcvt_ds,  0, 0, 0b00, 0b000101)
-  F(fcvt_hs,  0, 0, 0b00, 0b000111)
-  F(frintn_s, 0, 0, 0b00, 0b001000)
-  F(frintp_s, 0, 0, 0b00, 0b001001)
-  F(frintm_s, 0, 0, 0b00, 0b001010)
-  F(frintz_s, 0, 0, 0b00, 0b001011)
-  F(frinta_s, 0, 0, 0b00, 0b001100)
-  F(frintx_s, 0, 0, 0b00, 0b001110)
-  F(frinti_s, 0, 0, 0b00, 0b001111)
-
-  F(fmov_d,   0, 0, 0b01, 0b000000)
-  F(fabs_d,   0, 0, 0b01, 0b000001)
-  F(fneg_d,   0, 0, 0b01, 0b000010)
-  F(fsqrt_d,  0, 0, 0b01, 0b000011)
-  F(fcvt_sd,  0, 0, 0b01, 0b000100)
-  F(fcvt_hd,  0, 0, 0b01, 0b000111)
-  F(frintn_d, 0, 0, 0b01, 0b001000)
-  F(frintp_d, 0, 0, 0b01, 0b001001)
-  F(frintm_d, 0, 0, 0b01, 0b001010)
-  F(frintz_d, 0, 0, 0b01, 0b001011)
-  F(frinta_d, 0, 0, 0b01, 0b001100)
-  F(frintx_d, 0, 0, 0b01, 0b001110)
-  F(frinti_d, 0, 0, 0b01, 0b001111)
-
-  F(fcvt_sh,  0, 0, 0b11, 0b000100)
-  F(fcvt_dh,  0, 0, 0b11, 0b000101)
-#undef F
-
-#define F(mnemonic, M, S, type, opcode) \
-  void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm) { \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |                          \
-        rm->encoding() << 16 | opcode << 12 | 0b10 << 10 | rn->encoding() << 5 | rd->encoding());  \
-  }
-
-  F(fmul_s,   0, 0, 0b00, 0b0000)
-  F(fdiv_s,   0, 0, 0b00, 0b0001)
-  F(fadd_s,   0, 0, 0b00, 0b0010)
-  F(fsub_s,   0, 0, 0b00, 0b0011)
-  F(fmax_s,   0, 0, 0b00, 0b0100)
-  F(fmin_s,   0, 0, 0b00, 0b0101)
-  F(fmaxnm_s, 0, 0, 0b00, 0b0110)
-  F(fminnm_s, 0, 0, 0b00, 0b0111)
-  F(fnmul_s,  0, 0, 0b00, 0b1000)
-
-  F(fmul_d,   0, 0, 0b01, 0b0000)
-  F(fdiv_d,   0, 0, 0b01, 0b0001)
-  F(fadd_d,   0, 0, 0b01, 0b0010)
-  F(fsub_d,   0, 0, 0b01, 0b0011)
-  F(fmax_d,   0, 0, 0b01, 0b0100)
-  F(fmin_d,   0, 0, 0b01, 0b0101)
-  F(fmaxnm_d, 0, 0, 0b01, 0b0110)
-  F(fminnm_d, 0, 0, 0b01, 0b0111)
-  F(fnmul_d,  0, 0, 0b01, 0b1000)
-#undef F
-
-#define F(mnemonic, M, S, type, o1, o0) \
-  void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm, FloatRegister ra) { \
-    emit_int32(M << 31 | S << 29 | 0b11111 << 24 | type << 22 | o1 << 21 | rm->encoding() << 16 |  \
-         o0 << 15 | ra->encoding() << 10 | rn->encoding() << 5 | rd->encoding());                  \
-  }
-
-  F(fmadd_s,  0, 0, 0b00, 0, 0)
-  F(fmsub_s,  0, 0, 0b00, 0, 1)
-  F(fnmadd_s, 0, 0, 0b00, 1, 0)
-  F(fnmsub_s, 0, 0, 0b00, 1, 1)
-
-  F(fmadd_d,  0, 0, 0b01, 0, 0)
-  F(fmsub_d,  0, 0, 0b01, 0, 1)
-  F(fnmadd_d, 0, 0, 0b01, 1, 0)
-  F(fnmsub_d, 0, 0, 0b01, 1, 1)
-#undef F
-
-#define F(mnemonic, M, S, type) \
-  void mnemonic(FloatRegister rd, int imm8) { \
-    assert ((imm8 >> 8) == 0, "immediate is out of range");                \
-    emit_int32(M << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |  \
-         imm8 << 13 | 0b100 << 10 | rd->encoding());                       \
-  }
-
-  F(fmov_s, 0, 0, 0b00)
-  F(fmov_d, 0, 0, 0b01)
-#undef F
-
-#define F(mnemonic, sf, S, type, rmode, opcode) \
-  void mnemonic(Register rd, FloatRegister rn) {                                     \
-    emit_int32(sf << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |           \
-         rmode << 19 | opcode << 16 | rn->encoding() << 5 | rd->encoding_with_zr()); \
-  }
-
-  F(fcvtns_ws, 0, 0, 0b00, 0b00, 0b000)
-  F(fcvtnu_ws, 0, 0, 0b00, 0b00, 0b001)
-  F(fcvtas_ws, 0, 0, 0b00, 0b00, 0b100)
-  F(fcvtau_ws, 0, 0, 0b00, 0b00, 0b101)
-  F(fmov_ws,   0, 0, 0b00, 0b00, 0b110)
-  F(fcvtps_ws, 0, 0, 0b00, 0b01, 0b000)
-  F(fcvtpu_ws, 0, 0, 0b00, 0b01, 0b001)
-  F(fcvtms_ws, 0, 0, 0b00, 0b10, 0b000)
-  F(fcvtmu_ws, 0, 0, 0b00, 0b10, 0b001)
-  F(fcvtzs_ws, 0, 0, 0b00, 0b11, 0b000)
-  F(fcvtzu_ws, 0, 0, 0b00, 0b11, 0b001)
-
-  F(fcvtns_wd, 0, 0, 0b01, 0b00, 0b000)
-  F(fcvtnu_wd, 0, 0, 0b01, 0b00, 0b001)
-  F(fcvtas_wd, 0, 0, 0b01, 0b00, 0b100)
-  F(fcvtau_wd, 0, 0, 0b01, 0b00, 0b101)
-  F(fcvtps_wd, 0, 0, 0b01, 0b01, 0b000)
-  F(fcvtpu_wd, 0, 0, 0b01, 0b01, 0b001)
-  F(fcvtms_wd, 0, 0, 0b01, 0b10, 0b000)
-  F(fcvtmu_wd, 0, 0, 0b01, 0b10, 0b001)
-  F(fcvtzs_wd, 0, 0, 0b01, 0b11, 0b000)
-  F(fcvtzu_wd, 0, 0, 0b01, 0b11, 0b001)
-
-  F(fcvtns_xs, 1, 0, 0b00, 0b00, 0b000)
-  F(fcvtnu_xs, 1, 0, 0b00, 0b00, 0b001)
-  F(fcvtas_xs, 1, 0, 0b00, 0b00, 0b100)
-  F(fcvtau_xs, 1, 0, 0b00, 0b00, 0b101)
-  F(fcvtps_xs, 1, 0, 0b00, 0b01, 0b000)
-  F(fcvtpu_xs, 1, 0, 0b00, 0b01, 0b001)
-  F(fcvtms_xs, 1, 0, 0b00, 0b10, 0b000)
-  F(fcvtmu_xs, 1, 0, 0b00, 0b10, 0b001)
-  F(fcvtzs_xs, 1, 0, 0b00, 0b11, 0b000)
-  F(fcvtzu_xs, 1, 0, 0b00, 0b11, 0b001)
-
-  F(fcvtns_xd, 1, 0, 0b01, 0b00, 0b000)
-  F(fcvtnu_xd, 1, 0, 0b01, 0b00, 0b001)
-  F(fcvtas_xd, 1, 0, 0b01, 0b00, 0b100)
-  F(fcvtau_xd, 1, 0, 0b01, 0b00, 0b101)
-  F(fmov_xd,   1, 0, 0b01, 0b00, 0b110)
-  F(fcvtps_xd, 1, 0, 0b01, 0b01, 0b000)
-  F(fcvtpu_xd, 1, 0, 0b01, 0b01, 0b001)
-  F(fcvtms_xd, 1, 0, 0b01, 0b10, 0b000)
-  F(fcvtmu_xd, 1, 0, 0b01, 0b10, 0b001)
-  F(fcvtzs_xd, 1, 0, 0b01, 0b11, 0b000)
-  F(fcvtzu_xd, 1, 0, 0b01, 0b11, 0b001)
-
-  F(fmov_xq,   1, 0, 0b10, 0b01, 0b110)
-#undef F
-
-#define F(mnemonic, sf, S, type, rmode, opcode) \
-  void mnemonic(FloatRegister rd, Register rn) {                                     \
-    emit_int32(sf << 31 | S << 29 | 0b11110 << 24 | type << 22 | 1 << 21 |           \
-         rmode << 19 | opcode << 16 | rn->encoding_with_zr() << 5 | rd->encoding()); \
-  }
-
-  F(scvtf_sw,  0, 0, 0b00, 0b00, 0b010)
-  F(ucvtf_sw,  0, 0, 0b00, 0b00, 0b011)
-  F(fmov_sw,   0, 0, 0b00, 0b00, 0b111)
-  F(scvtf_dw,  0, 0, 0b01, 0b00, 0b010)
-  F(ucvtf_dw,  0, 0, 0b01, 0b00, 0b011)
-
-  F(scvtf_sx,  1, 0, 0b00, 0b00, 0b010)
-  F(ucvtf_sx,  1, 0, 0b00, 0b00, 0b011)
-  F(scvtf_dx,  1, 0, 0b01, 0b00, 0b010)
-  F(ucvtf_dx,  1, 0, 0b01, 0b00, 0b011)
-  F(fmov_dx,   1, 0, 0b01, 0b00, 0b111)
-
-  F(fmov_qx,   1, 0, 0b10, 0b01, 0b111)
-#undef F
-
-#define F(mnemonic, opcode) \
-  void mnemonic(FloatRegister Vd, FloatRegister Vn) {                                     \
-    emit_int32( opcode << 10 | Vn->encoding() << 5 | Vd->encoding());             \
-  }
-
-  F(aese, 0b0100111000101000010010);
-  F(aesd, 0b0100111000101000010110);
-  F(aesmc, 0b0100111000101000011010);
-  F(aesimc, 0b0100111000101000011110);
-#undef F
-
-#ifdef COMPILER2
-  typedef VFP::double_num double_num;
-  typedef VFP::float_num  float_num;
-#endif
-
-  void vcnt(FloatRegister Dd, FloatRegister Dn, int quad = 0, int size = 0) {
-    // emitted at VM startup to detect whether the instruction is available
-    assert(!VM_Version::is_initialized() || VM_Version::has_simd(), "simd instruction");
-    assert(size == 0, "illegal size value");
-    emit_int32(0x0e205800 | quad << 30 | size << 22 | Dn->encoding() << 5 | Dd->encoding());
-  }
-
-#ifdef COMPILER2
-  void addv(FloatRegister Dd, FloatRegister Dm, int quad, int size) {
-    // emitted at VM startup to detect whether the instruction is available
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert((quad & ~1) == 0, "illegal value");
-    assert(size >= 0 && size < 3, "illegal value");
-    assert(((size << 1) | quad) != 4, "illegal values (size 2, quad 0)");
-    emit_int32(0x0e31b800 | quad << 30 | size << 22 | Dm->encoding() << 5 | Dd->encoding());
-  }
-
-  enum VElem_Size {
-    VELEM_SIZE_8  = 0x00,
-    VELEM_SIZE_16 = 0x01,
-    VELEM_SIZE_32 = 0x02,
-    VELEM_SIZE_64 = 0x03
-  };
-
-  enum VLD_Type {
-    VLD1_TYPE_1_REG  = 0b0111,
-    VLD1_TYPE_2_REGS = 0b1010,
-    VLD1_TYPE_3_REGS = 0b0110,
-    VLD1_TYPE_4_REGS = 0b0010
-  };
-
-  enum VFloat_Arith_Size {
-    VFA_SIZE_F32 = 0b0,
-    VFA_SIZE_F64 = 0b1
-  };
-
-#define F(mnemonic, U, S, P) \
-  void mnemonic(FloatRegister fd, FloatRegister fn, FloatRegister fm,    \
-                int size, int quad) {                                    \
-    assert(VM_Version::has_simd(), "simd instruction");                  \
-    assert(!(size == VFA_SIZE_F64 && !quad), "reserved");                \
-    assert((size & 1) == size, "overflow");                              \
-    emit_int32(quad << 30 | U << 29 | 0b01110 << 24 |                    \
-               S << 23 | size << 22 | 1 << 21 | P << 11 | 1 << 10 |      \
-               fm->encoding() << 16 |                                    \
-               fn->encoding() <<  5 |                                    \
-               fd->encoding());                                          \
-  }
-
-  F(vaddF, 0, 0, 0b11010)  // Vd = Vn + Vm (float)
-  F(vsubF, 0, 1, 0b11010)  // Vd = Vn - Vm (float)
-  F(vmulF, 1, 0, 0b11011)  // Vd = Vn - Vm (float)
-  F(vdivF, 1, 0, 0b11111)  // Vd = Vn / Vm (float)
-#undef F
-
-#define F(mnemonic, U) \
-  void mnemonic(FloatRegister fd, FloatRegister fm, FloatRegister fn,    \
-                int size, int quad) {                                    \
-    assert(VM_Version::has_simd(), "simd instruction");                  \
-    assert(!(size == VELEM_SIZE_64 && !quad), "reserved");               \
-    assert((size & 0b11) == size, "overflow");                           \
-    int R = 0; /* rounding */                                            \
-    int S = 0; /* saturating */                                          \
-    emit_int32(quad << 30 | U << 29 | 0b01110 << 24 | size << 22 |       \
-               1 << 21 | R << 12 | S << 11 | 0b10001 << 10 |             \
-               fm->encoding() << 16 |                                    \
-               fn->encoding() <<  5 |                                    \
-               fd->encoding());                                          \
-  }
-
-  F(vshlSI, 0)  // Vd = ashift(Vn,Vm) (int)
-  F(vshlUI, 1)  // Vd = lshift(Vn,Vm) (int)
-#undef F
-
-#define F(mnemonic, U, P, M) \
-  void mnemonic(FloatRegister fd, FloatRegister fn, FloatRegister fm,    \
-                int size, int quad) {                                    \
-    assert(VM_Version::has_simd(), "simd instruction");                  \
-    assert(!(size == VELEM_SIZE_64 && !quad), "reserved");               \
-    assert(!(size == VELEM_SIZE_64 && M), "reserved");                   \
-    assert((size & 0b11) == size, "overflow");                           \
-    emit_int32(quad << 30 | U << 29 | 0b01110 << 24 | size << 22 |       \
-               1 << 21 | P << 11 | 1 << 10 |                             \
-               fm->encoding() << 16 |                                    \
-               fn->encoding() <<  5 |                                    \
-               fd->encoding());                                          \
-  }
-
-  F(vmulI, 0, 0b10011,  true)  // Vd = Vn * Vm (int)
-  F(vaddI, 0, 0b10000, false)  // Vd = Vn + Vm (int)
-  F(vsubI, 1, 0b10000, false)  // Vd = Vn - Vm (int)
-#undef F
-
-#define F(mnemonic, U, O) \
-  void mnemonic(FloatRegister fd, FloatRegister fn, FloatRegister fm,    \
-                int quad) {                                              \
-    assert(VM_Version::has_simd(), "simd instruction");                  \
-    emit_int32(quad << 30 | U << 29 | 0b01110 << 24 | O << 22 |          \
-               1 << 21 | 0b00011 << 11 | 1 << 10 |                       \
-               fm->encoding() << 16 |                                    \
-               fn->encoding() <<  5 |                                    \
-               fd->encoding());                                          \
-  }
-
-  F(vandI, 0, 0b00)  // Vd = Vn & Vm (int)
-  F(vorI,  0, 0b10)  // Vd = Vn | Vm (int)
-  F(vxorI, 1, 0b00)  // Vd = Vn ^ Vm (int)
-#undef F
-
-  void vnegI(FloatRegister fd, FloatRegister fn, int size, int quad) {
-    int U = 1;
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(quad || size != VELEM_SIZE_64, "reserved");
-    emit_int32(quad << 30 | U << 29 | 0b01110 << 24 |
-              size << 22 | 0b100000101110 << 10 |
-              fn->encoding() << 5 |
-              fd->encoding() << 0);
-  }
-
-  void vshli(FloatRegister fd, FloatRegister fn, int esize, int imm, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-
-    if (imm >= esize) {
-      // maximum shift gives all zeroes, direction doesn't matter,
-      // but only available for shift right
-      vshri(fd, fn, esize, esize, true /* unsigned */, quad);
-      return;
-    }
-    assert(imm >= 0 && imm < esize, "out of range");
-
-    int imm7 = esize + imm;
-    int immh = imm7 >> 3;
-    assert(immh != 0, "encoding constraint");
-    assert((uint)immh < 16, "sanity");
-    assert(((immh >> 2) | quad) != 0b10, "reserved");
-    emit_int32(quad << 30 | 0b011110 << 23 | imm7 << 16 |
-               0b010101 << 10 | fn->encoding() << 5 | fd->encoding() << 0);
-  }
-
-  void vshri(FloatRegister fd, FloatRegister fn, int esize, int imm,
-             bool U /* unsigned */, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(imm > 0, "out of range");
-    if (imm >= esize) {
-      // maximum shift (all zeroes)
-      imm = esize;
-    }
-    int imm7 = 2 * esize - imm ;
-    int immh = imm7 >> 3;
-    assert(immh != 0, "encoding constraint");
-    assert((uint)immh < 16, "sanity");
-    assert(((immh >> 2) | quad) != 0b10, "reserved");
-    emit_int32(quad << 30 | U << 29 | 0b011110 << 23 | imm7 << 16 |
-               0b000001 << 10 | fn->encoding() << 5 | fd->encoding() << 0);
-  }
-  void vshrUI(FloatRegister fd, FloatRegister fm, int size, int imm, int quad) {
-    vshri(fd, fm, size, imm, true /* unsigned */, quad);
-  }
-  void vshrSI(FloatRegister fd, FloatRegister fm, int size, int imm, int quad) {
-    vshri(fd, fm, size, imm, false /* signed */, quad);
-  }
-
-  void vld1(FloatRegister Vt, Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(addr.disp() == 0 || addr.disp() == 16, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 1;
-    int opcode = VLD1_TYPE_1_REG;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vst1(FloatRegister Vt, Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(addr.disp() == 0 || addr.disp() == 16, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 0;
-    int opcode = VLD1_TYPE_1_REG;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vld1(FloatRegister Vt, FloatRegister Vt2, Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(Vt->successor() == Vt2, "Registers must be ordered");
-    assert(addr.disp() == 0 || addr.disp() == 32, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 1;
-    int opcode = VLD1_TYPE_2_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vst1(FloatRegister Vt, FloatRegister Vt2, Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(Vt->successor() == Vt2, "Registers must be ordered");
-    assert(bits == 128, "unsupported");
-    assert(addr.disp() == 0 || addr.disp() == 32, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 0;
-    int opcode = VLD1_TYPE_2_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,
-            Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,
-          "Registers must be ordered");
-    assert(addr.disp() == 0 || addr.disp() == 48, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 1;
-    int opcode = VLD1_TYPE_3_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vst1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,
-            Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(Vt->successor() == Vt2 &&  Vt2->successor() == Vt3,
-           "Registers must be ordered");
-    assert(addr.disp() == 0 || addr.disp() == 48, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 0;
-    int opcode = VLD1_TYPE_3_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vld1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,
-            FloatRegister Vt4, Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&
-           Vt3->successor() == Vt4, "Registers must be ordered");
-    assert(addr.disp() == 0 || addr.disp() == 64, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 1;
-    int opcode = VLD1_TYPE_4_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void vst1(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,
-            FloatRegister Vt4,  Address addr, VElem_Size size, int bits) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(bits == 128, "unsupported");
-    assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&
-           Vt3->successor() == Vt4, "Registers must be ordered");
-    assert(addr.disp() == 0 || addr.disp() == 64, "must be");
-    int type = 0b11; // 2D
-    int quad = 1;
-    int L = 0;
-    int opcode = VLD1_TYPE_4_REGS;
-    emit_int32(quad << 30 | 0b11 << 26 | L << 22 | opcode << 12 | size << 10 |
-               Vt->encoding() << 0 | addr.encoding_simd());
-  }
-
-  void rev32(FloatRegister Vd, FloatRegister Vn, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(size == VELEM_SIZE_8 || size == VELEM_SIZE_16, "must be");
-    emit_int32(quad << 30 | 0b101110 << 24 | size << 22 |
-               0b100000000010 << 10 | Vn->encoding() << 5 | Vd->encoding());
-  }
-
-  void eor(FloatRegister Vd, FloatRegister Vn,  FloatRegister Vm, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(size == VELEM_SIZE_8, "must be");
-    emit_int32(quad << 30 | 0b101110001 << 21 | Vm->encoding() << 16 |
-               0b000111 << 10 | Vn->encoding() << 5 | Vd->encoding());
-  }
-
-  void orr(FloatRegister Vd, FloatRegister Vn,  FloatRegister Vm, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(size == VELEM_SIZE_8, "must be");
-    emit_int32(quad << 30 | 0b001110101 << 21 | Vm->encoding() << 16 |
-               0b000111 << 10 | Vn->encoding() << 5 | Vd->encoding());
-  }
-
-  void vmovI(FloatRegister Dd, int imm8, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(imm8 >= 0 && imm8 < 256, "out of range");
-    int op;
-    int cmode;
-    switch (size) {
-    case VELEM_SIZE_8:
-      op = 0;
-      cmode = 0b1110;
-      break;
-    case VELEM_SIZE_16:
-      op = 0;
-      cmode = 0b1000;
-      break;
-    case VELEM_SIZE_32:
-      op = 0;
-      cmode = 0b0000;
-      break;
-    default:
-      cmode = 0;
-      ShouldNotReachHere();
-    }
-    int abc = imm8 >> 5;
-    int defgh = imm8 & 0b11111;
-    emit_int32(quad << 30 | op << 29 | 0b1111 << 24 |
-               abc << 16 | cmode << 12 | 0b01 << 10 |
-               defgh << 5 | Dd->encoding() << 0);
-  }
-
-  void vdupI(FloatRegister Dd, Register Rn, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    assert(size <= 3, "unallocated encoding");
-    assert(size != 3 || quad == 1, "reserved");
-    int imm5 = 1 << size;
-#ifdef ASSERT
-    switch (size) {
-    case VELEM_SIZE_8:
-      assert(imm5 == 0b00001, "sanity");
-      break;
-    case VELEM_SIZE_16:
-      assert(imm5 == 0b00010, "sanity");
-      break;
-    case VELEM_SIZE_32:
-      assert(imm5 == 0b00100, "sanity");
-      break;
-    case VELEM_SIZE_64:
-      assert(imm5 == 0b01000, "sanity");
-      break;
-    default:
-      ShouldNotReachHere();
-    }
-#endif
-    emit_int32(quad << 30 | 0b111 << 25 | 0b11 << 10 |
-               imm5 << 16 | Rn->encoding() << 5 |
-               Dd->encoding() << 0);
-  }
-
-  void vdup(FloatRegister Vd, FloatRegister Vn, VElem_Size size, int quad) {
-    assert(VM_Version::has_simd(), "simd instruction");
-    int index = 0;
-    int bytes = 1 << size;
-    int range = 16 / bytes;
-    assert(index < range, "overflow");
-
-    assert(size != VELEM_SIZE_64 || quad, "reserved");
-    assert(8 << VELEM_SIZE_8  ==  8, "sanity");
-    assert(8 << VELEM_SIZE_16 == 16, "sanity");
-    assert(8 << VELEM_SIZE_32 == 32, "sanity");
-    assert(8 << VELEM_SIZE_64 == 64, "sanity");
-
-    int imm5 = (index << (size + 1)) | bytes;
-
-    emit_int32(quad << 30 | 0b001110000 << 21 | imm5 << 16 | 0b000001 << 10 |
-               Vn->encoding() << 5 | Vd->encoding() << 0);
-  }
-
-  void vdupF(FloatRegister Vd, FloatRegister Vn, int quad) {
-    vdup(Vd, Vn, VELEM_SIZE_32, quad);
-  }
-
-  void vdupD(FloatRegister Vd, FloatRegister Vn, int quad) {
-    vdup(Vd, Vn, VELEM_SIZE_64, quad);
-  }
-#endif
-};
-
-
-#endif // CPU_ARM_VM_ASSEMBLER_ARM_64_HPP
--- a/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp	Tue Oct 30 10:39:19 2018 -0400
@@ -67,9 +67,6 @@
   __ bind(_entry);
 
   if (_info->deoptimize_on_exception()) {
-#ifdef AARCH64
-    __ NOT_TESTED();
-#endif
     __ call(Runtime1::entry_for(Runtime1::predicate_failed_trap_id), relocInfo::runtime_call_type);
     ce->add_call_info_here(_info);
     ce->verify_oop_map(_info);
@@ -86,9 +83,6 @@
   }
 
   if (_throw_index_out_of_bounds_exception) {
-#ifdef AARCH64
-    __ NOT_TESTED();
-#endif
     __ call(Runtime1::entry_for(Runtime1::throw_index_exception_id), relocInfo::runtime_call_type);
   } else {
     __ str(_array->as_pointer_register(), Address(SP, BytesPerWord)); // ??? Correct offset? Correct instruction?
@@ -208,16 +202,12 @@
   const Register lock_reg = _lock_reg->as_pointer_register();
 
   ce->verify_reserved_argument_area_size(2);
-#ifdef AARCH64
-  __ stp(obj_reg, lock_reg, Address(SP));
-#else
   if (obj_reg < lock_reg) {
     __ stmia(SP, RegisterSet(obj_reg) | RegisterSet(lock_reg));
   } else {
     __ str(obj_reg, Address(SP));
     __ str(lock_reg, Address(SP, BytesPerWord));
   }
-#endif // AARCH64
 
   Runtime1::StubID enter_id = ce->compilation()->has_fpu_code() ?
                               Runtime1::monitorenter_id :
@@ -259,7 +249,7 @@
 }
 
 void PatchingStub::emit_code(LIR_Assembler* ce) {
-  const int patchable_instruction_offset = AARCH64_ONLY(NativeInstruction::instruction_size) NOT_AARCH64(0);
+  const int patchable_instruction_offset = 0;
 
   assert(NativeCall::instruction_size <= _bytes_to_copy && _bytes_to_copy <= 0xFF,
          "not enough room for call");
@@ -267,31 +257,17 @@
   Label call_patch;
   bool is_load = (_id == load_klass_id) || (_id == load_mirror_id) || (_id == load_appendix_id);
 
-#ifdef AARCH64
-  assert(nativeInstruction_at(_pc_start)->is_nop(), "required for MT safe patching");
 
-  // Same alignment of reg2mem code and PatchingStub code. Required to make copied bind_literal() code properly aligned.
-  __ align(wordSize);
-#endif // AARCH64
-
-  if (is_load NOT_AARCH64(&& !VM_Version::supports_movw())) {
+  if (is_load && !VM_Version::supports_movw()) {
     address start = __ pc();
 
     // The following sequence duplicates code provided in MacroAssembler::patchable_mov_oop()
     // without creating relocation info entry.
-#ifdef AARCH64
-    // Extra nop for MT safe patching
-    __ nop();
-#endif // AARCH64
 
     assert((__ pc() - start) == patchable_instruction_offset, "should be");
-#ifdef AARCH64
-    __ ldr(_obj, __ pc());
-#else
     __ ldr(_obj, Address(PC));
     // Extra nop to handle case of large offset of oop placeholder (see NativeMovConstReg::set_data).
     __ nop();
-#endif // AARCH64
 
 #ifdef ASSERT
     for (int i = 0; i < _bytes_to_copy; i++) {
--- a/src/hotspot/cpu/arm/c1_Defs_arm.hpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/c1_Defs_arm.hpp	Tue Oct 30 10:39:19 2018 -0400
@@ -47,9 +47,9 @@
 
 // registers
 enum {
-  pd_nof_cpu_regs_frame_map             = AARCH64_ONLY(33) NOT_AARCH64(16), // number of registers used during code emission
-  pd_nof_caller_save_cpu_regs_frame_map = AARCH64_ONLY(27) NOT_AARCH64(10), // number of registers killed by calls
-  pd_nof_cpu_regs_reg_alloc             = AARCH64_ONLY(27) NOT_AARCH64(10), // number of registers that are visible to register allocator (including Rheap_base which is visible only if compressed pointers are not enabled)
+  pd_nof_cpu_regs_frame_map             = 16, // number of registers used during code emission
+  pd_nof_caller_save_cpu_regs_frame_map = 10, // number of registers killed by calls
+  pd_nof_cpu_regs_reg_alloc             = 10, // number of registers that are visible to register allocator (including Rheap_base which is visible only if compressed pointers are not enabled)
   pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map,                   // number of registers visible to linear scan
   pd_nof_cpu_regs_processed_in_linearscan = pd_nof_cpu_regs_reg_alloc + 1,  // number of registers processed in linear scan; includes LR as it is used as temporary register in c1_LIRGenerator_arm
   pd_first_cpu_reg = 0,
@@ -57,7 +57,7 @@
 
   pd_nof_fpu_regs_frame_map             = VFP(32) SOFT(0),                               // number of float registers used during code emission
   pd_nof_caller_save_fpu_regs_frame_map = VFP(32) SOFT(0),                               // number of float registers killed by calls
-  pd_nof_fpu_regs_reg_alloc             = AARCH64_ONLY(32) NOT_AARCH64(VFP(30) SOFT(0)), // number of float registers that are visible to register allocator
+  pd_nof_fpu_regs_reg_alloc             = VFP(30) SOFT(0), // number of float registers that are visible to register allocator
   pd_nof_fpu_regs_linearscan            = pd_nof_fpu_regs_frame_map,                     // number of float registers visible to linear scan
   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
   pd_last_fpu_reg  = pd_first_fpu_reg + pd_nof_fpu_regs_frame_map - 1,
@@ -74,11 +74,7 @@
   pd_float_saved_as_double = false
 };
 
-#ifdef AARCH64
-#define PATCHED_ADDR 0xff8
-#else
 #define PATCHED_ADDR (204)
-#endif
 #define CARDTABLEBARRIERSET_POST_BARRIER_HELPER
 #define GENERATE_ADDRESS_IS_PREFERRED
 
--- a/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/c1_FrameMap_arm.cpp	Tue Oct 30 10:39:19 2018 -0400
@@ -49,9 +49,6 @@
 LIR_Opr FrameMap::R4_metadata_opr;
 LIR_Opr FrameMap::R5_metadata_opr;
 
-#ifdef AARCH64
-LIR_Opr FrameMap::ZR_opr;
-#endif // AARCH64
 
 LIR_Opr FrameMap::LR_opr;
 LIR_Opr FrameMap::LR_oop_opr;
@@ -82,12 +79,7 @@
   } else if (r_1->is_Register()) {
     Register reg = r_1->as_Register();
     if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
-#ifdef AARCH64
-      assert(r_1->next() == r_2, "should be the same");
-      opr = as_long_opr(reg);
-#else
       opr = as_long_opr(reg, r_2->as_Register());
-#endif
     } else if (type == T_OBJECT || type == T_ARRAY) {
       opr = as_oop_opr(reg);
     } else if (type == T_METADATA) {
@@ -115,20 +107,10 @@
   int rnum = 0;
 
   // Registers used for allocation
-#ifdef AARCH64
-  assert(Rthread == R28 && Rheap_base == R27 && Rtemp == R16, "change the code here");
-  for (i = 0; i < 16; i++) {
-    map_register(rnum++, as_Register(i));
-  }
-  for (i = 17; i < 28; i++) {
-    map_register(rnum++, as_Register(i));
-  }
-#else
   assert(Rthread == R10 && Rtemp == R12, "change the code here");
   for (i = 0; i < 10; i++) {
     map_register(rnum++, as_Register(i));
   }
-#endif // AARCH64
   assert(rnum == pd_nof_cpu_regs_reg_alloc, "should be");
 
   // Registers not used for allocation
@@ -139,11 +121,7 @@
   map_register(rnum++, Rthread);
   map_register(rnum++, FP); // ARM32: R7 or R11
   map_register(rnum++, SP);
-#ifdef AARCH64
-  map_register(rnum++, ZR);
-#else
   map_register(rnum++, PC);
-#endif
   assert(rnum == pd_nof_cpu_regs_frame_map, "should be");
 
   _init_done = true;
@@ -155,9 +133,6 @@
   R4_opr  = as_opr(R4);   R4_oop_opr = as_oop_opr(R4);    R4_metadata_opr = as_metadata_opr(R4);
   R5_opr  = as_opr(R5);   R5_oop_opr = as_oop_opr(R5);    R5_metadata_opr = as_metadata_opr(R5);
 
-#ifdef AARCH64
-  ZR_opr = as_opr(ZR);
-#endif // AARCH64
 
   LR_opr      = as_opr(LR);
   LR_oop_opr  = as_oop_opr(LR);
@@ -169,11 +144,6 @@
   // LIR operands for result
   Int_result_opr = R0_opr;
   Object_result_opr = R0_oop_opr;
-#ifdef AARCH64
-  Long_result_opr = as_long_opr(R0);
-  Float_result_opr = as_float_opr(S0);
-  Double_result_opr = as_double_opr(D0);
-#else
   Long_result_opr = as_long_opr(R0, R1);
 #ifdef __ABI_HARD__
   Float_result_opr = as_float_opr(S0);
@@ -182,7 +152,6 @@
   Float_result_opr = LIR_OprFact::single_softfp(0);
   Double_result_opr = LIR_OprFact::double_softfp(0, 1);
 #endif // __ABI_HARD__
-#endif // AARCH64
 
   Exception_oop_opr = as_oop_opr(Rexception_obj);
   Exception_pc_opr = as_opr(Rexception_pc);
@@ -222,7 +191,7 @@
     }
     java_index += type2size[opr->type()];
   }
-  return max_offset < AARCH64_ONLY(16384) NOT_AARCH64(4096); // TODO-AARCH64 check that LIRAssembler does not generate load/store of byte and half-word with SP as address base
+  return max_offset < 4096;
 }
 
 VMReg FrameMap::fpu_regname(int n) {
--- a/src/hotspot/cpu/arm/c1_FrameMap_arm.hpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/c1_FrameMap_arm.hpp	Tue Oct 30 10:39:19 2018 -0400
@@ -54,9 +54,6 @@
   static LIR_Opr R4_metadata_opr;
   static LIR_Opr R5_metadata_opr;
 
-#ifdef AARCH64
-  static LIR_Opr ZR_opr;
-#endif // AARCH64
 
   static LIR_Opr LR_opr;
   static LIR_Opr LR_oop_opr;
@@ -75,19 +72,6 @@
   static LIR_Opr Exception_oop_opr;
   static LIR_Opr Exception_pc_opr;
 
-#ifdef AARCH64
-  static LIR_Opr as_long_opr(Register r) {
-    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
-  }
-
-  static LIR_Opr as_pointer_opr(Register r) {
-    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
-  }
-
-  static LIR_Opr as_double_opr(FloatRegister r) {
-    return LIR_OprFact::double_fpu(r->encoding());
-  }
-#else
   static LIR_Opr as_long_opr(Register r, Register r2) {
     return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
   }
@@ -99,7 +83,6 @@
   static LIR_Opr as_double_opr(FloatRegister r) {
     return LIR_OprFact::double_fpu(r->encoding(), r->successor()->encoding());
   }
-#endif
 
   static LIR_Opr as_float_opr(FloatRegister r) {
     return LIR_OprFact::single_fpu(r->encoding());
--- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp	Mon Oct 29 11:31:25 2018 -0700
+++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp	Tue Oct 30 10:39:19 2018 -0400
@@ -127,9 +127,6 @@
 Address LIR_Assembler::as_Address(LIR_Address* addr) {
   Register base = addr->base()->as_pointer_register();
 
-#ifdef AARCH64
-  int align = exact_log2(type2aelembytes(addr->type(), true));
-#endif
 
   if (addr->index()->is_illegal() || addr->index()->is_constant()) {
     int offset = addr->disp();
@@ -137,16 +134,9 @@
       offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
     }
 
-#ifdef AARCH64
-    if (!Assembler::is_unsigned_imm_in_range(offset, 12, align) && !Assembler::is_imm_in_range(offset, 9, 0)) {
-      BAILOUT_("offset not in range", Address(base));
-    }
-    assert(UseUnalignedAccesses || (offset & right_n_bits(align)) == 0, "offset should be aligned");
-#else
     if ((offset <= -4096) || (offset >= 4096)) {
       BAILOUT_("offset not in range", Address(base));
     }
-#endif // AARCH64
 
     return Address(base, offset);
 
@@ -154,44 +144,21 @@
     assert(addr->disp() == 0, "can't have both");
     int scale = addr->scale();
 
-#ifdef AARCH64
-    assert((scale == 0) || (scale == align), "scale should be zero or equal to embedded shift");
-
-    bool is_index_extended = (addr->index()->type() == T_INT);
-    if (is_index_extended) {
-      assert(addr->index()->is_single_cpu(), "should be");
-      return Address(base, addr->index()->as_register(), ex_sxtw, scale);
-    } else {
-      assert(addr->index()->is_double_cpu(), "should be");
-      return Address(base, addr->index()->as_register_lo(), ex_lsl, scale);
-    }
-#else
     assert(addr->index()->is_single_cpu(), "should be");
     return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
                         Address(base, addr->index()->as_register(), lsr, -scale);
-#endif // AARCH64
   }
 }
 
 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
-#ifdef AARCH64
-  ShouldNotCallThis(); // Not used on AArch64
-  return Address();
-#else
   Address base = as_Address(addr);
   assert(base.index() == noreg, "must be");
   if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
   return Address(base.base(), base.disp() + BytesPerWord);
-#endif // AARCH64
 }
 
 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
-#ifdef AARCH64
-  ShouldNotCallThis(); // Not used on AArch64
-  return Address();
-#else
   return as_Address(addr);
-#endif // AARCH64
 }
 
 
@@ -327,13 +294,8 @@
   int offset = code_offset();
 
   __ mov_relative_address(LR, __ pc());
-#ifdef AARCH64
-  __ raw_push(LR, LR);
-  __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, Rtemp);
-#else
   __ push(LR); // stub expects LR to be saved
   __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
-#endif // AARCH64
 
   assert(code_offset() - offset <= deopt_handler_size(), "overflow");
   __ end_a_stub();
@@ -347,7 +309,6 @@
   __ remove_frame(initial_frame_size_in_bytes());
 
   // mov_slow here is usually one or two instruction
-  // TODO-AARCH64 3 instructions on AArch64, so try to load polling page by ldr_literal
   __ mov_address(Rtemp, os::get_polling_page(), symbolic_Relocation::polling_page_reference);
   __ relocate(relocInfo::poll_return_type);
   __ ldr(Rtemp, Address(Rtemp));
@@ -386,12 +347,8 @@
 
     case T_LONG:
       assert(patch_code == lir_patch_none, "no patching handled here");
-#ifdef AARCH64
-      __ mov_slow(dest->as_pointer_register(), (intptr_t)c->as_jlong());
-#else
       __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
       __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
-#endif // AARCH64
       break;
 
     case T_OBJECT:
@@ -414,12 +371,8 @@
       if (dest->is_single_fpu()) {
         __ mov_float(dest->as_float_reg(), c->as_jfloat());
       } else {
-#ifdef AARCH64
-        ShouldNotReachHere();
-#else
         // Simple getters can return float constant directly into r0
         __ mov_slow(dest->as_register(), c->as_jint_bits());
-#endif // AARCH64
       }
       break;
 
@@ -427,13 +380,9 @@
       if (dest->is_double_fpu()) {
         __ mov_double(dest->as_double_reg(), c->as_jdouble());
       } else {
-#ifdef AARCH64
-        ShouldNotReachHere();
-#else
         // Simple getters can return double constant directly into r1r0
         __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
         __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
-#endif // AARCH64
       }
       break;
 
@@ -466,17 +415,12 @@
 
     case T_LONG:  // fall through
     case T_DOUBLE:
-#ifdef AARCH64
-      __ mov_slow(Rtemp, c->as_jlong_bits());
-      __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix()));
-#else
       __ mov_slow(Rtemp, c->as_jint_lo_bits());
       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
       if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
         __ mov_slow(Rtemp, c->as_jint_hi_bits());
       }
       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
-#endif // AARCH64
       break;
 
     default:
@@ -486,49 +430,14 @@
 
 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
                               CodeEmitInfo* info, bool wide) {
-#ifdef AARCH64
-  assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL) ||
-         (src->as_constant_ptr()->type() == T_INT && src->as_constant_ptr()->as_jint() == 0) ||
-         (src->as_constant_ptr()->type() == T_LONG && src->as_constant_ptr()->as_jlong() == 0) ||
-         (src->as_constant_ptr()->type() == T_FLOAT && src->as_constant_ptr()->as_jint_bits() == 0) ||
-         (src->as_constant_ptr()->type() == T_DOUBLE && src->as_constant_ptr()->as_jlong_bits() == 0),
-        "cannot handle otherwise");
-  assert(dest->as_address_ptr()->type() == type, "should be");
-
-  Address addr = as_Address(dest->as_address_ptr());
-  int null_check_offset = code_offset();
-  switch (type) {
-    case T_OBJECT:  // fall through
-    case T_ARRAY:
-        if (UseCompressedOops && !wide) {
-          __ str_w(ZR, addr);
-        } else {
-          __ str(ZR, addr);
-        }
-        break;
-    case T_ADDRESS: // fall through
-    case T_DOUBLE:  // fall through
-    case T_LONG:    __ str(ZR, addr);   break;
-    case T_FLOAT:   // fall through
-    case T_INT:     __ str_w(ZR, addr); break;
-    case T_BOOLEAN: // fall through
-    case T_BYTE:    __ strb(ZR, addr);  break;
-    case T_CHAR:    // fall through
-    case T_SHORT:   __ strh(ZR, addr);  break;
-    default: ShouldNotReachHere();
-  }
-#else
   assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
   __ mov(Rtemp, 0);
 
   int null_check_offset = code_offset();
   __ str(Rtemp, as_Address(dest->as_address_ptr()));
-#endif // AARCH64
 
   if (info != NULL) {
-#ifndef AARCH64
     assert(false, "arm32 didn't support this before, investigate if bug");
-#endif
     add_debug_info_for_null_check(null_check_offset, info);
   }
 }
@@ -539,27 +448,17 @@
   if (src->is_single_cpu()) {
     if (dest->is_single_cpu()) {
       move_regs(src->as_register(), dest->as_register());
-#ifdef AARCH64
-    } else if (dest->is_double_cpu()) {
-      assert ((src->type() == T_OBJECT) || (src->type() == T_ARRAY) || (src->type() == T_ADDRESS), "invalid src type");
-      move_regs(src->as_register(), dest->as_register_lo());
-#else
     } else if (dest->is_single_fpu()) {
       __ fmsr(dest->as_float_reg(), src->as_register());
-#endif // AARCH64
     } else {
       ShouldNotReachHere();
     }
   } else if (src->is_double_cpu()) {
-#ifdef AARCH64
-    move_regs(src->as_register_lo(), dest->as_register_lo());
-#else
     if (dest->is_double_cpu()) {
       __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
     } else {
       __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
     }
-#endif // AARCH64
   } else if (src->is_single_fpu()) {
     if (dest->is_single_fpu()) {
       __ mov_float(dest->as_float_reg(), src->as_float_reg());
@@ -572,11 +471,7 @@
     if (dest->is_double_fpu()) {
       __ mov_double(dest->as_double_reg(), src->as_double_reg());
     } else if (dest->is_double_cpu()) {
-#ifdef AARCH64
-      __ fmov_xd(dest->as_register_lo(), src->as_double_reg());
-#else
       __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
-#endif // AARCH64
     } else {
       ShouldNotReachHere();
     }
@@ -593,12 +488,10 @@
     frame_map()->address_for_slot(dest->single_stack_ix()) :
     frame_map()->address_for_slot(dest->double_stack_ix());
 
-#ifndef AARCH64
   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
   if (src->is_single_fpu() || src->is_double_fpu()) {
     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
   }
-#endif // !AARCH64
 
   if (src->is_single_cpu()) {
     switch (type) {
@@ -613,9 +506,7 @@
     }
   } else if (src->is_double_cpu()) {
     __ str(src->as_register_lo(), addr);
-#ifndef AARCH64
     __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
-#endif // !AARCH64
   } else if (src->is_single_fpu()) {
     __ str_float(src->as_float_reg(), addr);
   } else if (src->is_double_fpu()) {
@@ -636,15 +527,7 @@
 
   PatchingStub* patch = NULL;
   if (needs_patching) {
-#ifdef AARCH64
-    // Same alignment of reg2mem code and PatchingStub code. Required to make copied bind_literal() code properly aligned.
-    __ align(wordSize);
-#endif
     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
-#ifdef AARCH64
-    // Extra nop for MT safe patching
-    __ nop();
-#endif // AARCH64
   }
 
   int null_check_offset = code_offset();
@@ -653,24 +536,13 @@
     case T_ARRAY:
     case T_OBJECT:
       if (UseCompressedOops && !wide) {
-#ifdef AARCH64
-        const Register temp_src = Rtemp;
-        assert_different_registers(temp_src, src->as_register());
-        __ encode_heap_oop(temp_src, src->as_register());
-        null_check_offset = code_offset();
-        __ str_32(temp_src, as_Address(to_addr));
-#else
         ShouldNotReachHere();
-#endif // AARCH64
       } else {
         __ str(src->as_register(), as_Address(to_addr));
       }
       break;
 
     case T_ADDRESS:
-#ifdef AARCH64
-    case T_LONG:
-#endif // AARCH64
       __ str(src->as_pointer_register(), as_Address(to_addr));
       break;
 
@@ -691,17 +563,6 @@
       __ str_32(src->as_register(), as_Address(to_addr));
       break;
 
-#ifdef AARCH64
-
-    case T_FLOAT:
-      __ str_s(src->as_float_reg(), as_Address(to_addr));
-      break;
-
-    case T_DOUBLE:
-      __ str_d(src->as_double_reg(), as_Address(to_addr));
-      break;
-
-#else // AARCH64
 
 #ifdef __SOFTFP__
     case T_DOUBLE:
@@ -765,7 +626,6 @@
       break;
 #endif // __SOFTFP__
 
-#endif // AARCH64
 
     default:
       ShouldNotReachHere();
@@ -793,12 +653,10 @@
     frame_map()->address_for_slot(src->single_stack_ix()) :
     frame_map()->address_for_slot(src->double_stack_ix());
 
-#ifndef AARCH64
   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
   if (dest->is_single_fpu() || dest->is_double_fpu()) {
     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
   }
-#endif // !AARCH64
 
   if (dest->is_single_cpu()) {
     switch (type) {
@@ -816,9 +674,7 @@
     }
   } else if (dest->is_double_cpu()) {
     __ ldr(dest->as_register_lo(), addr);
-#ifndef AARCH64
     __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
-#endif // !AARCH64
   } else if (dest->is_single_fpu()) {
     __ ldr_float(dest->as_float_reg(), addr);
   } else if (dest->is_double_fpu()) {
@@ -853,12 +709,8 @@
     assert(src->is_double_stack(), "must be");
     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
-#ifdef AARCH64
-    assert(lo_word_offset_in_bytes == 0, "adjust this code");
-#else
     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
-#endif // AARCH64
   }
 }
 
@@ -875,10 +727,6 @@
   PatchingStub* patch = NULL;
   if (patch_code != lir_patch_none) {
     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
-#ifdef AARCH64
-    // Extra nop for MT safe patching
-    __ nop();
-#endif // AARCH64
   }
   if (info != NULL) {
     add_debug_info_for_null_check_here(info);
@@ -902,14 +750,10 @@
       }
       break;
 
-#ifdef AARCH64
-    case T_LONG:
-#else
     case T_INT:
 #ifdef __SOFTFP__
     case T_FLOAT:
 #endif // __SOFTFP__
-#endif // AARCH64
       __ ldr(dest->as_pointer_register(), as_Address(addr));
       break;
 
@@ -929,21 +773,6 @@
       __ ldrsh(dest->as_register(), as_Address(addr));
       break;
 
-#ifdef AARCH64
-
-    case T_INT:
-      __ ldr_w(dest->as_register(), as_Address(addr));
-      break;
-
-    case T_FLOAT:
-      __ ldr_s(dest->as_float_reg(), as_Address(addr));
-      break;
-
-    case T_DOUBLE:
-      __ ldr_d(dest->as_double_reg(), as_Address(addr));
-      break;
-
-#else // AARCH64
 
 #ifdef __SOFTFP__
     case T_DOUBLE:
@@ -1007,7 +836,6 @@
       break;
 #endif // __SOFTFP__
 
-#endif // AARCH64
 
     default:
       ShouldNotReachHere();
@@ -1021,23 +849,6 @@
     patching_epilog(patch, patch_code, base_reg, info);
   }
 
-#ifdef AARCH64
-  switch (type) {
-    case T_ARRAY:
-    case T_OBJECT:
-      if (UseCompressedOops && !wide) {
-        __ decode_heap_oop(dest->as_register());
-      }
-      __ verify_oop(dest->as_register());
-      break;
-
-    case T_ADDRESS:
-      if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
-        __ decode_klass_not_null(dest->as_register());
-      }
-      break;
-  }
-#endif // AARCH64
 }
 
 
@@ -1064,48 +875,13 @@
       // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
       // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
       __ cmp_32(left, c);
-#ifdef AARCH64
-      __ cset(dest, eq);
-#else
       __ mov(dest, 0, ne);
       __ mov(dest, 1, eq);
-#endif // AARCH64
     }
   } else {
-#ifdef AARCH64
-    Register left  = op->in_opr1()->as_pointer_register();
-    Register right = op->in_opr2()->as_pointer_register();
-    Register dest  = op->result_opr()->as_pointer_register();
-
-    switch (op->code()) {
-      case lir_idiv:
-        if (is_32) {
-          __ sdiv_w(dest, left, right);
-        } else {
-          __ sdiv(dest, left, right);
-        }
-        break;
-      case lir_irem: {
-        Register tmp = op->in_opr3()->as_pointer_register();
-        assert_different_registers(left, tmp);
-        assert_different_registers(right, tmp);
-        if (is_32) {
-          __ sdiv_w(tmp, left, right);
-          __ msub_w(dest, right, tmp, left);
-        } else {
-          __ sdiv(tmp, left, right);
-          __ msub(dest, right, tmp, left);
-        }
-        break;
-      }
-      default:
-        ShouldNotReachHere();
-    }
-#else
     assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
     __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
     add_debug_info_for_div0_here(op->info());
-#endif // AARCH64
   }
 }
 
@@ -1122,9 +898,7 @@
   assert (op->code() != lir_cond_float_branch, "this should be impossible");
 #else
   if (op->code() == lir_cond_float_branch) {
-#ifndef AARCH64
     __ fmstat();
-#endif // !AARCH64
     __ b(*(op->ublock()->label()), vs);
   }
 #endif // __SOFTFP__
@@ -1151,12 +925,8 @@
 
   switch (op->bytecode()) {
     case Bytecodes::_i2l:
-#ifdef AARCH64
-      __ sign_extend(dest->as_register_lo(), src->as_register(), 32);
-#else
       move_regs(src->as_register(), dest->as_register_lo());
       __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
-#endif // AARCH64
       break;
     case Bytecodes::_l2i:
       move_regs(src->as_register_lo(), dest->as_register());
@@ -1177,51 +947,21 @@
       __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
       break;
     case Bytecodes::_i2f:
-#ifdef AARCH64
-      __ scvtf_sw(dest->as_float_reg(), src->as_register());
-#else
       __ fmsr(Stemp, src->as_register());
       __ fsitos(dest->as_float_reg(), Stemp);
-#endif // AARCH64
       break;
     case Bytecodes::_i2d:
-#ifdef AARCH64
-      __ scvtf_dw(dest->as_double_reg(), src->as_register());
-#else
       __ fmsr(Stemp, src->as_register());
       __ fsitod(dest->as_double_reg(), Stemp);
-#endif // AARCH64
       break;
     case Bytecodes::_f2i:
-#ifdef AARCH64
-      __ fcvtzs_ws(dest->as_register(), src->as_float_reg());
-#else
       __ ftosizs(Stemp, src->as_float_reg());
       __ fmrs(dest->as_register(), Stemp);
-#endif // AARCH64
       break;
     case Bytecodes::_d2i:
-#ifdef AARCH64
-      __ fcvtzs_wd(dest->as_register(), src->as_double_reg());
-#else
       __ ftosizd(Stemp, src->as_double_reg());
       __ fmrs(dest->as_register(), Stemp);
-#endif // AARCH64
       break;
-#ifdef AARCH64
-    case Bytecodes::_l2f:
-      __ scvtf_sx(dest->as_float_reg(), src->as_register_lo());
-      break;
-    case Bytecodes::_l2d:
-      __ scvtf_dx(dest->as_double_reg(), src->as_register_lo());
-      break;
-    case Bytecodes::_f2l:
-      __ fcvtzs_xs(dest->as_register_lo(), src->as_float_reg());
-      break;
-    case Bytecodes::_d2l:
-      __ fcvtzs_xd(dest->as_register_lo(), src->as_double_reg());
-      break;
-#endif // AARCH64
     default:
       ShouldNotReachHere();
   }
@@ -1327,11 +1067,7 @@
   assert_different_registers(obj, mdo, data_val);
   setup_md_access(method, bci, md, data, mdo_offset_bias);
   Label not_null;
-#ifdef AARCH64
-  __ cbnz(obj, not_null);
-#else
   __ b(not_null, ne);
-#endif // AARCH64
   __ mov_metadata(mdo, md->constant_encoding());
   if (mdo_offset_bias > 0) {
     __ mov_slow(data_val, mdo_offset_bias);
@@ -1373,13 +1109,9 @@
   __ b(*failure);
 }
 
-// Sets `res` to true, if `cond` holds. On AArch64 also sets `res` to false if `cond` does not hold.
+// Sets `res` to true, if `cond` holds.
 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
-#ifdef AARCH64
-  __ cset(res, cond);
-#else
   __ mov(res, 1, cond);
-#endif // AARCH64
 }
 
 
@@ -1406,9 +1138,7 @@
       Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
 
       if (op->should_profile()) {
-#ifndef AARCH64
         __ cmp(value, 0);
-#endif // !AARCH64
         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
       } else {
         __ cbz(value, done);
@@ -1470,57 +1200,6 @@
       Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
 
-#ifdef AARCH64
-      move_regs(obj, res);
-      if (op->should_profile()) {
-        typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
-      } else {
-        __ cbz(obj, done);
-      }
-      if (k->is_loaded()) {
-        __ mov_metadata(k_RInfo, k->constant_encoding());
-      } else {
-        if (res != obj) {
-          op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
-        }
-        klass2reg_with_patching(k_RInfo, op->info_for_patch());
-      }
-      __ load_klass(klass_RInfo, res);
-
-      if (op->fast_check()) {
-        __ cmp(klass_RInfo, k_RInfo);
-        __ b(*failure_target, ne);
-      } else if (k->is_loaded()) {
-        __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
-        if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
-          __ cmp(Rtemp, k_RInfo);
-          __ b(*failure_target, ne);
-        } else {
-          __ cmp(klass_RInfo, k_RInfo);
-          __ cond_cmp(Rtemp, k_RInfo, ne);
-          __ b(*success_target, eq);
-          assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
-          __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
-          __ cbz(R0, *failure_target);
-        }
-      } else {
-        __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
-        // check for immediate positive hit
-        __ ldr(Rtemp, Address(klass_RInfo