annotate src/share/vm/c1/c1_LIRAssembler.hpp @ 13526:f5dd157e3889

8186439: [MVT] ClassFileParser should ignore JVM_ACC_VALUE for class file version < 53.1 Reviewed-by: dsimms
author thartmann
date Mon, 21 Aug 2017 12:26:21 +0200
parents 8a5735c11a84
children
rev   line source
duke@0 1 /*
goetz@11658 2 * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
duke@0 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@0 4 *
duke@0 5 * This code is free software; you can redistribute it and/or modify it
duke@0 6 * under the terms of the GNU General Public License version 2 only, as
duke@0 7 * published by the Free Software Foundation.
duke@0 8 *
duke@0 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@0 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@0 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@0 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@0 13 * accompanied this code).
duke@0 14 *
duke@0 15 * You should have received a copy of the GNU General Public License version
duke@0 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@0 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@0 18 *
trims@1472 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1472 20 * or visit www.oracle.com if you need additional information or have any
trims@1472 21 * questions.
duke@0 22 *
duke@0 23 */
duke@0 24
stefank@1879 25 #ifndef SHARE_VM_C1_C1_LIRASSEMBLER_HPP
stefank@1879 26 #define SHARE_VM_C1_C1_LIRASSEMBLER_HPP
stefank@1879 27
stefank@1879 28 #include "c1/c1_CodeStubs.hpp"
stefank@1879 29 #include "ci/ciMethodData.hpp"
coleenp@3602 30 #include "oops/methodData.hpp"
goetz@11658 31 #include "utilities/macros.hpp"
stefank@1879 32
duke@0 33 class Compilation;
duke@0 34 class ScopeValue;
ysr@342 35 class BarrierSet;
duke@0 36
duke@0 37 class LIR_Assembler: public CompilationResourceObj {
duke@0 38 private:
duke@0 39 C1_MacroAssembler* _masm;
duke@0 40 CodeStubList* _slow_case_stubs;
ysr@342 41 BarrierSet* _bs;
duke@0 42
duke@0 43 Compilation* _compilation;
duke@0 44 FrameMap* _frame_map;
duke@0 45 BlockBegin* _current_block;
duke@0 46
duke@0 47 Instruction* _pending_non_safepoint;
duke@0 48 int _pending_non_safepoint_offset;
duke@0 49
never@1378 50 Label _unwind_handler_entry;
never@1378 51
duke@0 52 #ifdef ASSERT
duke@0 53 BlockList _branch_target_blocks;
duke@0 54 void check_no_unbound_labels();
duke@0 55 #endif
duke@0 56
duke@0 57 FrameMap* frame_map() const { return _frame_map; }
duke@0 58
duke@0 59 void set_current_block(BlockBegin* b) { _current_block = b; }
duke@0 60 BlockBegin* current_block() const { return _current_block; }
duke@0 61
duke@0 62 // non-safepoint debug info management
duke@0 63 void flush_debug_info(int before_pc_offset) {
duke@0 64 if (_pending_non_safepoint != NULL) {
duke@0 65 if (_pending_non_safepoint_offset < before_pc_offset)
duke@0 66 record_non_safepoint_debug_info();
duke@0 67 _pending_non_safepoint = NULL;
duke@0 68 }
duke@0 69 }
duke@0 70 void process_debug_info(LIR_Op* op);
duke@0 71 void record_non_safepoint_debug_info();
duke@0 72
duke@0 73 // unified bailout support
duke@0 74 void bailout(const char* msg) const { compilation()->bailout(msg); }
duke@0 75 bool bailed_out() const { return compilation()->bailed_out(); }
duke@0 76
duke@0 77 // code emission patterns and accessors
duke@0 78 void check_codespace();
duke@0 79 bool needs_icache(ciMethod* method) const;
duke@0 80
duke@0 81 // returns offset of icache check
duke@0 82 int check_icache();
duke@0 83
duke@0 84 void jobject2reg(jobject o, Register reg);
duke@0 85 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info);
duke@0 86
coleenp@3602 87 void metadata2reg(Metadata* o, Register reg);
coleenp@3602 88 void klass2reg_with_patching(Register reg, CodeEmitInfo* info);
coleenp@3602 89
duke@0 90 void emit_stubs(CodeStubList* stub_list);
duke@0 91
duke@0 92 // addresses
never@304 93 Address as_Address(LIR_Address* addr);
never@304 94 Address as_Address_lo(LIR_Address* addr);
never@304 95 Address as_Address_hi(LIR_Address* addr);
duke@0 96
duke@0 97 // debug information
twisti@1484 98 void add_call_info(int pc_offset, CodeEmitInfo* cinfo);
duke@0 99 void add_debug_info_for_branch(CodeEmitInfo* info);
duke@0 100 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo);
duke@0 101 void add_debug_info_for_div0_here(CodeEmitInfo* info);
mdoerr@9508 102 ImplicitNullCheckStub* add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo);
mdoerr@9508 103 ImplicitNullCheckStub* add_debug_info_for_null_check_here(CodeEmitInfo* info);
duke@0 104
duke@0 105 void set_24bit_FPU();
duke@0 106 void reset_FPU();
duke@0 107 void fpop();
duke@0 108 void fxch(int i);
duke@0 109 void fld(int i);
duke@0 110 void ffree(int i);
duke@0 111
duke@0 112 void breakpoint();
duke@0 113 void push(LIR_Opr opr);
duke@0 114 void pop(LIR_Opr opr);
duke@0 115
duke@0 116 // patching
duke@0 117 void append_patching_stub(PatchingStub* stub);
duke@0 118 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info);
duke@0 119
duke@0 120 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op);
duke@0 121
roland@5193 122 PatchingStub::PatchID patching_id(CodeEmitInfo* info);
roland@5193 123
duke@0 124 public:
duke@0 125 LIR_Assembler(Compilation* c);
duke@0 126 ~LIR_Assembler();
duke@0 127 C1_MacroAssembler* masm() const { return _masm; }
duke@0 128 Compilation* compilation() const { return _compilation; }
duke@0 129 ciMethod* method() const { return compilation()->method(); }
duke@0 130
duke@0 131 CodeOffsets* offsets() const { return _compilation->offsets(); }
duke@0 132 int code_offset() const;
duke@0 133 address pc() const;
duke@0 134
roland@6307 135 int initial_frame_size_in_bytes() const;
roland@6307 136 int bang_size_in_bytes() const;
duke@0 137
duke@0 138 // test for constants which can be encoded directly in instructions
duke@0 139 static bool is_small_constant(LIR_Opr opr);
duke@0 140
duke@0 141 static LIR_Opr receiverOpr();
duke@0 142 static LIR_Opr osrBufferPointer();
duke@0 143
duke@0 144 // stubs
duke@0 145 void emit_slow_case_stubs();
duke@0 146 void emit_static_call_stub();
neliasso@6492 147 void append_code_stub(CodeStub* op);
duke@0 148 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); }
duke@0 149
duke@0 150 // code patterns
twisti@1204 151 int emit_exception_handler();
never@1378 152 int emit_unwind_handler();
duke@0 153 void emit_exception_entries(ExceptionInfoList* info_list);
twisti@1204 154 int emit_deopt_handler();
duke@0 155
duke@0 156 void emit_code(BlockList* hir);
duke@0 157 void emit_block(BlockBegin* block);
duke@0 158 void emit_lir_list(LIR_List* list);
duke@0 159
duke@0 160 // any last minute peephole optimizations are performed here. In
duke@0 161 // particular sparc uses this for delay slot filling.
duke@0 162 void peephole(LIR_List* list);
duke@0 163
duke@0 164 void return_op(LIR_Opr result);
duke@0 165
duke@0 166 // returns offset of poll instruction
duke@0 167 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info);
duke@0 168
duke@0 169 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info);
duke@0 170 void const2stack(LIR_Opr src, LIR_Opr dest);
iveresov@1909 171 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide);
duke@0 172 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack);
duke@0 173 void reg2reg (LIR_Opr src, LIR_Opr dest);
iveresov@1909 174 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type,
iveresov@1909 175 LIR_PatchCode patch_code, CodeEmitInfo* info,
iveresov@1909 176 bool pop_fpu_stack, bool wide, bool unaligned);
duke@0 177 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type);
duke@0 178 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type);
duke@0 179 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type,
iveresov@1909 180 LIR_PatchCode patch_code,
iveresov@1909 181 CodeEmitInfo* info, bool wide, bool unaligned);
duke@0 182
duke@0 183 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp);
duke@0 184 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest);
duke@0 185
duke@0 186 void move_regs(Register from_reg, Register to_reg);
duke@0 187 void swap_reg(Register a, Register b);
duke@0 188
duke@0 189 void emit_op0(LIR_Op0* op);
duke@0 190 void emit_op1(LIR_Op1* op);
duke@0 191 void emit_op2(LIR_Op2* op);
duke@0 192 void emit_op3(LIR_Op3* op);
duke@0 193 void emit_opBranch(LIR_OpBranch* op);
duke@0 194 void emit_opLabel(LIR_OpLabel* op);
duke@0 195 void emit_arraycopy(LIR_OpArrayCopy* op);
drchase@4918 196 void emit_updatecrc32(LIR_OpUpdateCRC32* op);
duke@0 197 void emit_opConvert(LIR_OpConvert* op);
duke@0 198 void emit_alloc_obj(LIR_OpAllocObj* op);
duke@0 199 void emit_alloc_array(LIR_OpAllocArray* op);
duke@0 200 void emit_opTypeCheck(LIR_OpTypeCheck* op);
iveresov@1711 201 void emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null);
duke@0 202 void emit_compare_and_swap(LIR_OpCompareAndSwap* op);
duke@0 203 void emit_lock(LIR_OpLock* op);
duke@0 204 void emit_call(LIR_OpJavaCall* op);
duke@0 205 void emit_rtcall(LIR_OpRTCall* op);
duke@0 206 void emit_profile_call(LIR_OpProfileCall* op);
roland@5479 207 void emit_profile_type(LIR_OpProfileType* op);
duke@0 208 void emit_delay(LIR_OpDelay* op);
duke@0 209
duke@0 210 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
duke@0 211 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
duke@0 212 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
roland@4425 213 #ifdef ASSERT
roland@4425 214 void emit_assert(LIR_OpAssert* op);
roland@4425 215 #endif
duke@0 216
duke@0 217 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
duke@0 218
duke@0 219 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack);
duke@0 220 void move_op(LIR_Opr src, LIR_Opr result, BasicType type,
iveresov@1909 221 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide);
duke@0 222 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
duke@0 223 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
duke@0 224 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
iveresov@1977 225 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
duke@0 226
twisti@1295 227 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);
twisti@1295 228 void ic_call( LIR_OpJavaCall* op);
twisti@1295 229 void vtable_call( LIR_OpJavaCall* op);
twisti@1295 230
duke@0 231 void osr_entry();
duke@0 232
duke@0 233 void build_frame();
duke@0 234
never@1378 235 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info);
never@1378 236 void unwind_op(LIR_Opr exceptionOop);
duke@0 237 void monitor_address(int monitor_ix, LIR_Opr dst);
duke@0 238
duke@0 239 void align_backward_branch_target();
duke@0 240 void align_call(LIR_Code code);
duke@0 241
duke@0 242 void negate(LIR_Opr left, LIR_Opr dest);
duke@0 243 void leal(LIR_Opr left, LIR_Opr dest);
duke@0 244
duke@0 245 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info);
duke@0 246
duke@0 247 void membar();
duke@0 248 void membar_acquire();
duke@0 249 void membar_release();
jiangli@3157 250 void membar_loadload();
jiangli@3157 251 void membar_storestore();
jiangli@3157 252 void membar_loadstore();
jiangli@3157 253 void membar_storeload();
ikrylov@10963 254 void on_spin_wait();
duke@0 255 void get_thread(LIR_Opr result);
duke@0 256
duke@0 257 void verify_oop_map(CodeEmitInfo* info);
duke@0 258
roland@3671 259 void atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp);
roland@3671 260
goetz@11658 261 #include CPU_HEADER(c1_LIRAssembler)
stefank@1879 262
kvn@12408 263 static int call_stub_size() {
kvn@12408 264 if (UseAOT) {
kvn@12408 265 return _call_stub_size + _call_aot_stub_size;
kvn@12408 266 } else {
kvn@12408 267 return _call_stub_size;
kvn@12408 268 }
kvn@12408 269 }
kvn@12408 270
kvn@12408 271 static int exception_handler_size() {
kvn@12408 272 return _exception_handler_size;
kvn@12408 273 }
kvn@12408 274
kvn@12408 275 static int deopt_handler_size() {
kvn@12408 276 return _deopt_handler_size;
kvn@12408 277 }
duke@0 278 };
stefank@1879 279
stefank@1879 280 #endif // SHARE_VM_C1_C1_LIRASSEMBLER_HPP