changeset 12624:b53b0251e250

8173472: AArch64: C1 comparisons with null only use 32-bit instructions Reviewed-by: roland
author aph
date Fri, 27 Jan 2017 09:50:15 +0000
parents bfa8e4b0d4e2
children 9bfa2cceba90
files src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
diffstat 1 files changed, 8 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Sun Jan 22 16:33:54 2017 +0800
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Fri Jan 27 09:50:15 2017 +0000
@@ -1922,12 +1922,17 @@
     }
 
     if (opr2->is_constant()) {
+      bool is_32bit = false; // width of register operand
       jlong imm;
+
       switch(opr2->type()) {
+      case T_INT:
+        imm = opr2->as_constant_ptr()->as_jint();
+        is_32bit = true;
+        break;
       case T_LONG:
         imm = opr2->as_constant_ptr()->as_jlong();
         break;
-      case T_INT:
       case T_ADDRESS:
         imm = opr2->as_constant_ptr()->as_jint();
         break;
@@ -1942,14 +1947,14 @@
       }
 
       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
-        if (type2aelembytes(opr1->type()) <= 4)
+        if (is_32bit)
           __ cmpw(reg1, imm);
         else
           __ cmp(reg1, imm);
         return;
       } else {
         __ mov(rscratch1, imm);
-        if (type2aelembytes(opr1->type()) <= 4)
+        if (is_32bit)
           __ cmpw(reg1, rscratch1);
         else
           __ cmp(reg1, rscratch1);