changeset 13399:bc075a2f87ad mvt

Merge
author dsimms
date Thu, 10 Aug 2017 09:23:41 +0200
parents 297678e133e6 6ad02163b738
children f5dd157e3889
files make/templates/gpl-cp-header make/templates/gpl-header src/cpu/aarch64/vm/debug_aarch64.cpp src/cpu/arm/vm/debug_arm.cpp src/cpu/ppc/vm/debug_ppc.cpp src/cpu/ppc/vm/globals_ppc.hpp src/cpu/s390/vm/debug_s390.cpp src/cpu/sparc/vm/debug_sparc.cpp src/cpu/sparc/vm/globals_sparc.hpp src/cpu/x86/vm/abstractInterpreter_x86.cpp src/cpu/x86/vm/debug_x86.cpp src/cpu/x86/vm/frame_x86.cpp src/cpu/x86/vm/globals_x86.hpp src/cpu/x86/vm/interpreterRT_x86.hpp src/cpu/x86/vm/interpreterRT_x86_32.cpp src/cpu/x86/vm/interpreterRT_x86_64.cpp src/cpu/x86/vm/macroAssembler_x86.cpp src/cpu/x86/vm/sharedRuntime_x86_32.cpp src/cpu/x86/vm/sharedRuntime_x86_64.cpp src/cpu/x86/vm/stubGenerator_x86_64.cpp src/cpu/x86/vm/templateTable_x86.cpp src/cpu/zero/vm/debug_zero.cpp src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/AtomicUnsigned.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/AtomicWord.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/ComparableWord.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/LocationIdentity.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/Pointer.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/PointerBase.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/PointerUtils.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/Signed.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/Unsigned.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/UnsignedUtils.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/WordBase.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.api.word/src/org/graalvm/api/word/WordFactory.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.aarch64/src/org/graalvm/compiler/core/aarch64/AArch64AddressLowering.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.aarch64/src/org/graalvm/compiler/core/aarch64/AArch64SuitesProvider.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.amd64/src/org/graalvm/compiler/core/amd64/AMD64SuitesProvider.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.sparc/src/org/graalvm/compiler/core/sparc/SPARCSuitesProvider.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest1.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest2.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest3.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest4.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest5.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTest6.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTestInterception01.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/MethodMetricsTestInterception02.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core.test/src/org/graalvm/compiler/core/test/debug/VerifyMethodMetricsTest.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.core/src/org/graalvm/compiler/core/GraalDebugInitializationParticipant.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug.test/src/org/graalvm/compiler/debug/test/DebugHistogramTest.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug.test/src/org/graalvm/compiler/debug/test/DebugTimerTest.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/Debug.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugConfigCustomizer.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugConfigScope.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugCounter.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugEnvironment.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugHistogram.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugInitializationParticipant.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugMethodMetrics.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugRetryableTask.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugTimer.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DebugValueFactory.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/DelegatingDebugConfig.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/Fingerprint.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/GraalDebugConfig.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/TopLevelDebugConfig.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/AccumulatedDebugValue.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/CloseableCounterImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/CounterImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugHistogramAsciiPrinter.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugHistogramImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugHistogramRPrinter.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugScope.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugValue.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugValueMap.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/DebugValuesPrinter.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/KeyRegistry.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/MemUseTrackerImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/TimerImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/method/MethodMetricsImpl.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/method/MethodMetricsInlineeScopeInfo.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/method/MethodMetricsPrinter.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.debug/src/org/graalvm/compiler/debug/internal/method/MethodMetricsRootScopeInfo.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot.amd64/src/org/graalvm/compiler/hotspot/amd64/AMD64HotSpotSuitesProvider.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot.test/src/org/graalvm/compiler/hotspot/test/RetryableCompilationTest.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot/src/org/graalvm/compiler/hotspot/FingerprintUtil.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot/src/org/graalvm/compiler/hotspot/HotSpotRetryableCompilation.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.java/src/org/graalvm/compiler/java/DefaultSuitesProvider.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir/src/org/graalvm/compiler/lir/alloc/trace/lsra/TraceIntervalWalker.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.options/src/org/graalvm/compiler/options/UniquePathUtilities.java src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.printer/src/org/graalvm/compiler/printer/GraalDebugConfigCustomizer.java src/os/aix/vm/interfaceSupport_aix.hpp src/os/bsd/vm/interfaceSupport_bsd.hpp src/os/bsd/vm/stubRoutines_bsd.cpp src/os/linux/vm/interfaceSupport_linux.hpp src/os/linux/vm/stubRoutines_linux.cpp src/os/solaris/vm/interfaceSupport_solaris.hpp src/os/solaris/vm/stubRoutines_solaris.cpp src/os/windows/vm/interfaceSupport_windows.hpp src/os/windows/vm/stubRoutines_windows.cpp src/os_cpu/linux_sparc/vm/atomic_linux_sparc.hpp src/os_cpu/linux_sparc/vm/atomic_linux_sparc.inline.hpp src/share/vm/c1/c1_GraphBuilder.cpp src/share/vm/ci/bcEscapeAnalyzer.cpp src/share/vm/ci/ciEnv.cpp src/share/vm/ci/ciInstance.cpp src/share/vm/ci/ciMethod.cpp src/share/vm/ci/ciMethodBlocks.cpp src/share/vm/ci/ciReplay.cpp src/share/vm/ci/ciTypeFlow.cpp src/share/vm/classfile/classFileParser.cpp src/share/vm/classfile/classFileParser.hpp src/share/vm/classfile/classLoader.cpp src/share/vm/classfile/javaClasses.cpp src/share/vm/classfile/systemDictionary.cpp src/share/vm/classfile/systemDictionary.hpp src/share/vm/classfile/vmSymbols.cpp src/share/vm/classfile/vmSymbols.hpp src/share/vm/code/codeBlob.cpp src/share/vm/code/codeBlob.hpp src/share/vm/code/compiledMethod.cpp src/share/vm/code/nmethod.cpp src/share/vm/compiler/compileBroker.cpp src/share/vm/gc/parallel/psCompactionManager.cpp src/share/vm/gc/parallel/psParallelCompact.cpp src/share/vm/gc/parallel/psPromotionManager.cpp src/share/vm/interpreter/abstractInterpreter.cpp src/share/vm/interpreter/abstractInterpreter.hpp src/share/vm/interpreter/bytecode.hpp src/share/vm/interpreter/bytecodeInterpreter.cpp src/share/vm/interpreter/bytecodeTracer.cpp src/share/vm/interpreter/bytecodes.cpp src/share/vm/interpreter/interpreterRuntime.cpp src/share/vm/interpreter/interpreterRuntime.hpp src/share/vm/interpreter/linkResolver.cpp src/share/vm/interpreter/oopMapCache.cpp src/share/vm/interpreter/rewriter.cpp src/share/vm/interpreter/rewriter.hpp src/share/vm/jvmci/jvmciCodeInstaller.cpp src/share/vm/jvmci/jvmciCompilerToVM.cpp src/share/vm/jvmci/jvmciEnv.cpp src/share/vm/jvmci/vmStructs_jvmci.cpp src/share/vm/logging/logStream.inline.hpp src/share/vm/logging/logTag.hpp src/share/vm/memory/allocation.hpp src/share/vm/memory/allocation.inline.hpp src/share/vm/memory/freeBlockDictionary.cpp src/share/vm/memory/freeBlockDictionary.hpp src/share/vm/oops/arrayOop.hpp src/share/vm/oops/constantPool.cpp src/share/vm/oops/constantPool.hpp src/share/vm/oops/cpCache.cpp src/share/vm/oops/cpCache.hpp src/share/vm/oops/generateOopMap.cpp src/share/vm/oops/generateOopMap.hpp src/share/vm/oops/instanceKlass.cpp src/share/vm/oops/instanceKlass.hpp src/share/vm/oops/instanceOop.hpp src/share/vm/oops/klass.hpp src/share/vm/oops/klassVtable.cpp src/share/vm/oops/klassVtable.hpp src/share/vm/oops/method.cpp src/share/vm/oops/method.hpp src/share/vm/oops/methodData.cpp src/share/vm/oops/oop.hpp src/share/vm/oops/oop.inline.hpp src/share/vm/oops/valueArrayKlass.cpp src/share/vm/oops/valueKlass.cpp src/share/vm/opto/buildOopMap.cpp src/share/vm/opto/castnode.cpp src/share/vm/opto/castnode.hpp src/share/vm/opto/cfgnode.cpp src/share/vm/opto/chaitin.cpp src/share/vm/opto/classes.hpp src/share/vm/opto/compile.cpp src/share/vm/opto/compile.hpp src/share/vm/opto/doCall.cpp src/share/vm/opto/escape.cpp src/share/vm/opto/graphKit.cpp src/share/vm/opto/graphKit.hpp src/share/vm/opto/lcm.cpp src/share/vm/opto/library_call.cpp src/share/vm/opto/live.cpp src/share/vm/opto/loopopts.cpp src/share/vm/opto/machnode.cpp src/share/vm/opto/macro.cpp src/share/vm/opto/macroArrayCopy.cpp src/share/vm/opto/matcher.cpp src/share/vm/opto/memnode.cpp src/share/vm/opto/multnode.cpp src/share/vm/opto/output.cpp src/share/vm/opto/parse1.cpp src/share/vm/opto/parse2.cpp src/share/vm/opto/parseHelper.cpp src/share/vm/opto/phaseX.cpp src/share/vm/opto/runtime.cpp src/share/vm/opto/type.cpp src/share/vm/opto/type.hpp src/share/vm/prims/jni.cpp src/share/vm/prims/jvm.cpp src/share/vm/prims/jvm.h src/share/vm/prims/jvmtiRedefineClasses.cpp src/share/vm/prims/methodComparator.cpp src/share/vm/prims/methodHandles.cpp src/share/vm/prims/whitebox.cpp src/share/vm/runtime/arguments.cpp src/share/vm/runtime/deoptimization.cpp src/share/vm/runtime/deoptimization.hpp src/share/vm/runtime/frame.cpp src/share/vm/runtime/frame.hpp src/share/vm/runtime/globals.hpp src/share/vm/runtime/handles.hpp src/share/vm/runtime/javaCalls.cpp src/share/vm/runtime/mutexLocker.cpp src/share/vm/runtime/reflection.cpp src/share/vm/runtime/safepoint.cpp src/share/vm/runtime/sharedRuntime.cpp src/share/vm/runtime/sharedRuntime.hpp src/share/vm/runtime/stubRoutines.cpp src/share/vm/runtime/stubRoutines.hpp src/share/vm/runtime/thread.cpp src/share/vm/runtime/thread.hpp src/share/vm/runtime/vmStructs.cpp src/share/vm/runtime/vm_operations.cpp src/share/vm/runtime/vm_operations.hpp src/share/vm/services/diagnosticCommand.cpp src/share/vm/utilities/globalDefinitions.hpp test/TEST.groups test/compiler/cpuflags/predicate/AESSupportPredicate.java test/compiler/rtm/cli/TestRTMAbortRatioOptionOnSupportedConfig.java test/compiler/rtm/cli/TestRTMAbortRatioOptionOnUnsupportedConfig.java test/compiler/rtm/cli/TestRTMTotalCountIncrRateOptionOnUnsupportedConfig.java test/compiler/testlibrary/rtm/predicate/SupportedCPU.java test/compiler/testlibrary/rtm/predicate/SupportedOS.java test/compiler/testlibrary/rtm/predicate/SupportedVM.java test/runtime/modules/JVMAddModulePackage.java
diffstat 1674 files changed, 41035 insertions(+), 31748 deletions(-) [+]
line wrap: on
line diff
--- a/.hgtags	Wed Aug 09 16:00:52 2017 -0400
+++ b/.hgtags	Thu Aug 10 09:23:41 2017 +0200
@@ -579,3 +579,16 @@
 1ca7ed1b17b5776930d641d1379834f3140a74e4 jdk-9+167
 fbb9c802649585d19f6d7e81b4a519d44806225a jdk-9+168
 16d692be099c5c38eb48cc9aca78b0c900910d5b jdk-9+169
+38a240fd58a287acb1963920b92ed4d9c2fd39e3 jdk-9+170
+9d4746eca95aec3e5a344bf2520745dcc1d17eed jdk-10+7
+f5ded0cf954c770deeecb80f2ba1ba6a05cd979b jdk-10+8
+233647e3d3800e76d7612014b745b37a88098f63 jdk-10+9
+d53171650a2cc6c6f699c966c533b914ca9c0602 jdk-9+171
+c6cd3ec8d46b034e57c86399380ffcf7f25706e4 jdk-10+10
+1ae9e84f68b359420d2d153ecfe5ee2903e33a2e jdk-9+172
+7f14e550f1e8abea41c223e5fdad2261e99ba929 jdk-10+11
+e64b1cb48d6e7703928a9d1da106fc27f8cb65fd jdk-9+173
+944791f8160185bffa13fbb821fc09b6198f1f25 jdk-9+174
+070aa7a2eb14c4645f7eb31384cba0a2ba72a4b5 jdk-10+12
+8f04d457168b9f1f4a1b2c37f49e0513ca9d33a7 jdk-9+175
+a9da03357f190807591177fe9846d6e68ad64fc0 jdk-10+13
--- a/.jcheck/conf	Wed Aug 09 16:00:52 2017 -0400
+++ b/.jcheck/conf	Thu Aug 10 09:23:41 2017 +0200
@@ -1,1 +1,2 @@
 project=jdk10
+bugids=dup
--- a/.mx.jvmci/mx_jvmci.py	Wed Aug 09 16:00:52 2017 -0400
+++ b/.mx.jvmci/mx_jvmci.py	Thu Aug 10 09:23:41 2017 +0200
@@ -303,9 +303,9 @@
                         out.close('link')
 
                     out.open('link')
-                    out.element('name', data='generated')
+                    out.element('name', data='gensrc')
                     out.element('type', data='2')
-                    generated = join(_get_hotspot_build_dir(jvmVariant, debugLevel), 'generated')
+                    generated = join(_get_hotspot_build_dir(jvmVariant, debugLevel), 'gensrc')
                     out.element('locationURI', data=mx.get_eclipse_project_rel_locationURI(generated, eclProjectDir))
                     out.close('link')
 
@@ -620,18 +620,12 @@
 def _get_hotspot_build_dir(jvmVariant=None, debugLevel=None):
     """
     Gets the directory in which a particular HotSpot configuration is built
-    (e.g., <JDK_REPO_ROOT>/build/macosx-x86_64-normal-server-release/hotspot/bsd_amd64_compiler2)
+    (e.g., <JDK_REPO_ROOT>/build/macosx-x86_64-normal-server-release/hotspot/variant-<variant>)
     """
     if jvmVariant is None:
         jvmVariant = _vm.jvmVariant
 
-    os = mx.get_os()
-    if os == 'darwin':
-        os = 'bsd'
-    arch = mx.get_arch()
-    buildname = {'client': 'compiler1', 'server': 'compiler2'}.get(jvmVariant, jvmVariant)
-
-    name = '{}_{}_{}'.format(os, arch, buildname)
+    name = 'variant-{}'.format(jvmVariant)
     return join(_get_jdk_build_dir(debugLevel=debugLevel), 'hotspot', name)
 
 class JVMCI9JDKConfig(mx.JDKConfig):
--- a/make/CompileTools.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/CompileTools.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -47,7 +47,7 @@
   $(eval $(call SetupJavaCompilation, BUILD_VM_COMPILER_MATCH_PROCESSOR, \
       SETUP := GENERATE_OLDBYTECODE, \
       SRC := \
-          $(SRC_DIR)/org.graalvm.api.word/src \
+          $(SRC_DIR)/org.graalvm.word/src \
           $(SRC_DIR)/org.graalvm.compiler.core/src \
           $(SRC_DIR)/org.graalvm.compiler.core.common/src \
           $(SRC_DIR)/org.graalvm.compiler.core.match.processor/src \
@@ -115,7 +115,7 @@
   $(eval $(call SetupJavaCompilation, BUILD_VM_COMPILER_REPLACEMENTS_VERIFIER, \
       SETUP := GENERATE_OLDBYTECODE, \
       SRC := \
-          $(SRC_DIR)/org.graalvm.api.word/src \
+          $(SRC_DIR)/org.graalvm.word/src \
           $(SRC_DIR)/org.graalvm.compiler.replacements.verifier/src \
           $(SRC_DIR)/org.graalvm.compiler.api.replacements/src \
           $(SRC_DIR)/org.graalvm.compiler.code/src \
--- a/make/gensrc/GensrcAdlc.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/gensrc/GensrcAdlc.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013, 2016, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2013, 2017, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -73,7 +73,7 @@
       OUTPUT_DIR := $(JVM_VARIANT_OUTPUTDIR)/tools/adlc, \
       PROGRAM := adlc, \
       DEBUG_SYMBOLS := false, \
-      DISABLED_WARNINGS_clang := parentheses tautological-compare, \
+      DISABLED_WARNINGS_clang := tautological-compare, \
       DISABLED_WARNINGS_solstudio := notemsource, \
   ))
 
--- a/make/lib/CompileDtracePostJvm.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/lib/CompileDtracePostJvm.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013, 2016, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2013, 2017, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -52,7 +52,7 @@
         CXX := $(BUILD_CXX), \
         LDEXE := $(BUILD_CXX), \
         generateJvmOffsets.cpp_CXXFLAGS := $(JVM_CFLAGS) -mt -xnolib -norunpath, \
-        generateJvmOffsetsMain.c_CFLAGS := -library=%none -mt -m64 -norunpath -z nodefs, \
+        generateJvmOffsetsMain.c_CFLAGS := -mt -m64 -norunpath -z nodefs, \
         LDFLAGS := -m64, \
         LIBS := -lc, \
         OBJECT_DIR := $(JVM_VARIANT_OUTPUTDIR)/tools/dtrace-gen-offsets/objs, \
--- a/make/lib/CompileGtest.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/lib/CompileGtest.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -52,7 +52,8 @@
 	$(call create-mapfile)
 endif
 
-# Disabling switch warning for clang because of test source.
+# Disabling undef, switch, format-nonliteral and tautological-undefined-compare
+# warnings for clang because of test source.
 
 # Note: On AIX, the gtest test classes linked into the libjvm.so push the TOC
 # size beyond 64k, so we need to link with bigtoc. However, this means that
--- a/make/lib/CompileJvm.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/lib/CompileJvm.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013, 2016, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2013, 2017, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -69,6 +69,7 @@
     -DTARGET_ARCH_$(HOTSPOT_TARGET_CPU_ARCH) \
     -DINCLUDE_SUFFIX_OS=_$(HOTSPOT_TARGET_OS) \
     -DINCLUDE_SUFFIX_CPU=_$(HOTSPOT_TARGET_CPU_ARCH) \
+    -DINCLUDE_SUFFIX_COMPILER=_$(HOTSPOT_TOOLCHAIN_TYPE) \
     -DTARGET_COMPILER_$(HOTSPOT_TOOLCHAIN_TYPE) \
     -D$(HOTSPOT_TARGET_CPU_DEFINE) \
     -DHOTSPOT_LIB_ARCH='"$(OPENJDK_TARGET_CPU_LEGACY_LIB)"' \
@@ -217,9 +218,7 @@
     CFLAGS_DEBUG_SYMBOLS := $(JVM_CFLAGS_SYMBOLS), \
     CXXFLAGS_DEBUG_SYMBOLS := $(JVM_CFLAGS_SYMBOLS), \
     vm_version.cpp_CXXFLAGS := $(CFLAGS_VM_VERSION), \
-    DISABLED_WARNINGS_clang := delete-non-virtual-dtor dynamic-class-memaccess \
-        empty-body format logical-op-parentheses parentheses \
-        parentheses-equality switch tautological-compare, \
+    DISABLED_WARNINGS_clang := tautological-compare, \
     DISABLED_WARNINGS_xlc := 1540-0216 1540-0198 1540-1090 1540-1639 \
         1540-1088 1500-010, \
     ASFLAGS := $(JVM_ASFLAGS), \
--- a/make/symbols/symbols-unix	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/symbols/symbols-unix	Thu Aug 10 09:23:41 2017 +0200
@@ -188,7 +188,6 @@
 JVM_AddModuleExports
 JVM_AddModuleExportsToAll
 JVM_AddModuleExportsToAllUnnamed
-JVM_AddModulePackage
 JVM_AddReadsModule
 JVM_DefineModule
 JVM_SetBootLoaderUnnamedModule
--- a/make/templates/gpl-cp-header	Wed Aug 09 16:00:52 2017 -0400
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-Copyright (c) %YEARS%, Oracle and/or its affiliates. All rights reserved.
-DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-
-This code is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License version 2 only, as
-published by the Free Software Foundation.  Oracle designates this
-particular file as subject to the "Classpath" exception as provided
-by Oracle in the LICENSE file that accompanied this code.
-
-This code is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-version 2 for more details (a copy is included in the LICENSE file that
-accompanied this code).
-
-You should have received a copy of the GNU General Public License version
-2 along with this work; if not, write to the Free Software Foundation,
-Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-
-Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-or visit www.oracle.com if you need additional information or have any
-questions.
--- a/make/templates/gpl-header	Wed Aug 09 16:00:52 2017 -0400
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,20 +0,0 @@
-Copyright (c) %YEARS%, Oracle and/or its affiliates. All rights reserved.
-DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-
-This code is free software; you can redistribute it and/or modify it
-under the terms of the GNU General Public License version 2 only, as
-published by the Free Software Foundation.
-
-This code is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-version 2 for more details (a copy is included in the LICENSE file that
-accompanied this code).
-
-You should have received a copy of the GNU General Public License version
-2 along with this work; if not, write to the Free Software Foundation,
-Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-
-Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-or visit www.oracle.com if you need additional information or have any
-questions.
--- a/make/test/JtregNative.gmk	Wed Aug 09 16:00:52 2017 -0400
+++ b/make/test/JtregNative.gmk	Thu Aug 10 09:23:41 2017 +0200
@@ -45,6 +45,7 @@
 BUILD_HOTSPOT_JTREG_NATIVE_SRC += \
     $(HOTSPOT_TOPDIR)/test/gc/g1/TestJNIWeakG1 \
     $(HOTSPOT_TOPDIR)/test/gc/stress/gclocker \
+    $(HOTSPOT_TOPDIR)/test/gc/cslocker \
     $(HOTSPOT_TOPDIR)/test/native_sanity \
     $(HOTSPOT_TOPDIR)/test/runtime/jni/8025979 \
     $(HOTSPOT_TOPDIR)/test/runtime/jni/8033445 \
@@ -61,6 +62,7 @@
     $(HOTSPOT_TOPDIR)/test/compiler/floatingpoint/ \
     $(HOTSPOT_TOPDIR)/test/compiler/calls \
     $(HOTSPOT_TOPDIR)/test/serviceability/jvmti/GetNamedModule \
+    $(HOTSPOT_TOPDIR)/test/serviceability/jvmti/IsModifiableModule \
     $(HOTSPOT_TOPDIR)/test/serviceability/jvmti/AddModuleReads \
     $(HOTSPOT_TOPDIR)/test/serviceability/jvmti/AddModuleExportsAndOpens \
     $(HOTSPOT_TOPDIR)/test/serviceability/jvmti/AddModuleUsesAndProvides \
@@ -91,6 +93,7 @@
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_liboverflow := -lc
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libSimpleClassFileLoadHook := -lc
     BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libGetNamedModuleTest := -lc
+    BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libIsModifiableModuleTest := -lc
     BUILD_HOTSPOT_JTREG_LIBRARIES_LDFLAGS_libAddModuleReadsTest := -lc
     BUILD_HOTSPOT_JTREG_LIBRARIES_LDFLAGS_libAddModuleExportsAndOpensTest := -lc
     BUILD_HOTSPOT_JTREG_LIBRARIES_LDFLAGS_libAddModuleUsesAndProvidesTest := -lc
--- a/src/cpu/aarch64/vm/aarch64.ad	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/aarch64.ad	Thu Aug 10 09:23:41 2017 +0200
@@ -5218,7 +5218,7 @@
   // ppc port uses 0 but we definitely need to allow for fixed_slots
   // which folds in the space used for monitors
   return_addr(STACK - 2 +
-              round_to((Compile::current()->in_preserve_stack_slots() +
+              align_up((Compile::current()->in_preserve_stack_slots() +
                         Compile::current()->fixed_slots()),
                        stack_alignment_in_slots()));
 
@@ -5343,6 +5343,17 @@
   interface(CONST_INTER);
 %}
 
+// Shift values for add/sub extension shift
+operand immIExt()
+%{
+  predicate(0 <= n->get_int() && (n->get_int() <= 4));
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 operand immI_le_4()
 %{
   predicate(n->get_int() <= 4);
@@ -5423,6 +5434,16 @@
   interface(CONST_INTER);
 %}
 
+operand immI_63()
+%{
+  predicate(n->get_int() == 63);
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 operand immI_64()
 %{
   predicate(n->get_int() == 64);
@@ -5453,20 +5474,10 @@
   interface(CONST_INTER);
 %}
 
-operand immL_63()
-%{
-  predicate(n->get_int() == 63);
-  match(ConI);
-
-  op_cost(0);
-  format %{ %}
-  interface(CONST_INTER);
-%}
-
 operand immL_255()
 %{
-  predicate(n->get_int() == 255);
-  match(ConI);
+  predicate(n->get_long() == 255L);
+  match(ConL);
 
   op_cost(0);
   format %{ %}
@@ -10951,7 +10962,7 @@
 
 // Long Negation
 
-instruct negL_reg(iRegLNoSp dst, iRegIorL2I src, immL0 zero, rFlagsReg cr) %{
+instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero, rFlagsReg cr) %{
   match(Set dst (SubL zero src));
 
   ins_cost(INSN_COST);
@@ -11146,7 +11157,7 @@
   ins_pipe(ldiv_reg_reg);
 %}
 
-instruct signExtractL(iRegLNoSp dst, iRegL src1, immL_63 div1, immL_63 div2) %{
+instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
   match(Set dst (URShiftL (RShiftL src1 div1) div2));
   ins_cost(INSN_COST);
   format %{ "lsr $dst, $src1, $div1" %}
@@ -11156,7 +11167,7 @@
   ins_pipe(ialu_reg_shift);
 %}
 
-instruct div2RoundL(iRegLNoSp dst, iRegL src, immL_63 div1, immL_63 div2) %{
+instruct div2RoundL(iRegLNoSp dst, iRegL src, immI_63 div1, immI_63 div2) %{
   match(Set dst (AddL src (URShiftL (RShiftL src div1) div2)));
   ins_cost(INSN_COST);
   format %{ "add $dst, $src, $div1" %}
@@ -12789,7 +12800,7 @@
 %{
   match(Set dst (AddL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtw $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12802,7 +12813,7 @@
 %{
   match(Set dst (SubL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "sub  $dst, $src1, sxtw $src2" %}
+  format %{ "sub  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12816,7 +12827,7 @@
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxth $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxth" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12829,7 +12840,7 @@
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12842,7 +12853,7 @@
 %{
   match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, uxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, uxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12855,7 +12866,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxth $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxth" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12868,7 +12879,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtw $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12881,7 +12892,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12894,7 +12905,7 @@
 %{
   match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, uxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, uxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -13034,6 +13045,294 @@
   ins_pipe(ialu_reg_reg);
 %}
 
+
+instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtw #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtw #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+
+instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtw #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%};
+
+instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtw #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%};
+
+
+instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxtw #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtw #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
 // END This section of the file is automatically generated. Do not edit --------------
 
 // ============================================================================
@@ -15387,9 +15686,9 @@
   format %{ "ShouldNotReachHere" %}
 
   ins_encode %{
-    // TODO
-    // implement proper trap call here
-    __ brk(999);
+    // +1 so NativeInstruction::is_sigill_zombie_not_entrant() doesn't
+    // return true
+    __ dpcs1(0xdead + 1);
   %}
 
   ins_pipe(pipe_class_default);
@@ -16777,6 +17076,48 @@
   ins_pipe(vmla128);
 %}
 
+// dst + src1 * src2
+instruct vmla2F(vecD dst, vecD src1, vecD src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 2);
+  match(Set dst (FmaVF  dst (Binary src1 src2)));
+  format %{ "fmla  $dst,$src1,$src2\t# vector (2S)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmla(as_FloatRegister($dst$$reg), __ T2S,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp64);
+%}
+
+// dst + src1 * src2
+instruct vmla4F(vecX dst, vecX src1, vecX src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 4);
+  match(Set dst (FmaVF  dst (Binary src1 src2)));
+  format %{ "fmla  $dst,$src1,$src2\t# vector (4S)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmla(as_FloatRegister($dst$$reg), __ T4S,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp128);
+%}
+
+// dst + src1 * src2
+instruct vmla2D(vecX dst, vecX src1, vecX src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 2);
+  match(Set dst (FmaVD  dst (Binary src1 src2)));
+  format %{ "fmla  $dst,$src1,$src2\t# vector (2D)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmla(as_FloatRegister($dst$$reg), __ T2D,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp128);
+%}
+
 // --------------------------------- MLS --------------------------------------
 
 instruct vmls4S(vecD dst, vecD src1, vecD src2)
@@ -16836,6 +17177,51 @@
   ins_pipe(vmla128);
 %}
 
+// dst - src1 * src2
+instruct vmls2F(vecD dst, vecD src1, vecD src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 2);
+  match(Set dst (FmaVF  dst (Binary (NegVF src1) src2)));
+  match(Set dst (FmaVF  dst (Binary src1 (NegVF src2))));
+  format %{ "fmls  $dst,$src1,$src2\t# vector (2S)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmls(as_FloatRegister($dst$$reg), __ T2S,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp64);
+%}
+
+// dst - src1 * src2
+instruct vmls4F(vecX dst, vecX src1, vecX src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 4);
+  match(Set dst (FmaVF  dst (Binary (NegVF src1) src2)));
+  match(Set dst (FmaVF  dst (Binary src1 (NegVF src2))));
+  format %{ "fmls  $dst,$src1,$src2\t# vector (4S)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmls(as_FloatRegister($dst$$reg), __ T4S,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp128);
+%}
+
+// dst - src1 * src2
+instruct vmls2D(vecX dst, vecX src1, vecX src2) %{
+  predicate(UseFMA && n->as_Vector()->length() == 2);
+  match(Set dst (FmaVD  dst (Binary (NegVD src1) src2)));
+  match(Set dst (FmaVD  dst (Binary src1 (NegVD src2))));
+  format %{ "fmls  $dst,$src1,$src2\t# vector (2D)" %}
+  ins_cost(INSN_COST);
+  ins_encode %{
+    __ fmls(as_FloatRegister($dst$$reg), __ T2D,
+            as_FloatRegister($src1$$reg),
+            as_FloatRegister($src2$$reg));
+  %}
+  ins_pipe(vmuldiv_fp128);
+%}
+
 // --------------------------------- DIV --------------------------------------
 
 instruct vdiv2F(vecD dst, vecD src1, vecD src2)
--- a/src/cpu/aarch64/vm/aarch64_ad.m4	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4	Thu Aug 10 09:23:41 2017 +0200
@@ -268,21 +268,21 @@
   ins_pipe(ialu_reg_reg_vshift);
 %}')dnl
 define(ROL_INSN, `
-instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
 %{
   match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
 
   expand %{
-    $3L_rReg(dst, src, shift, cr);
+    $3$1_rReg(dst, src, shift, cr);
   %}
 %}')dnl
 define(ROR_INSN, `
-instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
 %{
   match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
 
   expand %{
-    $3L_rReg(dst, src, shift, cr);
+    $3$1_rReg(dst, src, shift, cr);
   %}
 %}')dnl
 ROL_EXPAND(L, rol, rorv)
@@ -305,7 +305,7 @@
 %{
   match(Set dst ($3$2 src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "$4  $dst, $src1, $5 $src2" %}
+  format %{ "$4  $dst, $src1, $src2, $5" %}
 
    ins_encode %{
      __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -321,7 +321,7 @@
 %{
   match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
   ins_cost(INSN_COST);
-  format %{ "$5  $dst, $src1, $6 $src2" %}
+  format %{ "$5  $dst, $src1, $src2, $6" %}
 
    ins_encode %{
      __ $5(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -363,5 +363,82 @@
 ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb)
 ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
 ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
+dnl
+dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type)
+define(`ADD_SUB_EXTENDED_SHIFT', `
+instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr)
+%{
+  match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$5  $dst, $src1, $src2, $6 #lshift2" %}
 
+   ins_encode %{
+     __ $5(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$6, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl                   $1 $2 $3   $4   $5   $6  $7
+ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64)
+ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64)
+ADD_SUB_EXTENDED_SHIFT(L,32,Add,RShift,add,sxtw,64)
+dnl
+ADD_SUB_EXTENDED_SHIFT(L,8,Sub,RShift,sub,sxtb,64)
+ADD_SUB_EXTENDED_SHIFT(L,16,Sub,RShift,sub,sxth,64)
+ADD_SUB_EXTENDED_SHIFT(L,32,Sub,RShift,sub,sxtw,64)
+dnl
+ADD_SUB_EXTENDED_SHIFT(I,8,Add,RShift,addw,sxtb,32)
+ADD_SUB_EXTENDED_SHIFT(I,16,Add,RShift,addw,sxth,32)
+dnl
+ADD_SUB_EXTENDED_SHIFT(I,8,Sub,RShift,subw,sxtb,32)
+ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32)
+dnl
+dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type)
+define(`ADD_SUB_CONV_SHIFT', `
+instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$3  $dst, $src1, $src2, $4 #lshift" %}
+
+   ins_encode %{
+     __ $3(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$4, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl
+ADD_SUB_CONV_SHIFT(L,Add,add,sxtw);
+ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw);
+dnl
+dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type)
+define(`ADD_SUB_ZERO_EXTEND_SHIFT', `
+instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$4  $dst, $src1, $src2, $5 #lshift" %}
+
+   ins_encode %{
+     __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$5, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl
+dnl                       $1 $2  $3  $4  $5
+ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Add,add,uxtw)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Sub,sub,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Sub,sub,uxth)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Sub,sub,uxtw)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Add,addw,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Add,addw,uxth)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
+dnl
 // END This section of the file is automatically generated. Do not edit --------------
--- a/src/cpu/aarch64/vm/abstractInterpreter_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/abstractInterpreter_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -28,6 +28,7 @@
 #include "oops/constMethod.hpp"
 #include "oops/method.hpp"
 #include "runtime/frame.inline.hpp"
+#include "utilities/align.hpp"
 #include "utilities/debug.hpp"
 #include "utilities/macros.hpp"
 
@@ -53,27 +54,6 @@
   return i;
 }
 
-// These should never be compiled since the interpreter will prefer
-// the compiled version to the intrinsic version.
-bool AbstractInterpreter::can_be_compiled(methodHandle m) {
-  switch (method_kind(m)) {
-    case Interpreter::java_lang_math_sin     : // fall thru
-    case Interpreter::java_lang_math_cos     : // fall thru
-    case Interpreter::java_lang_math_tan     : // fall thru
-    case Interpreter::java_lang_math_abs     : // fall thru
-    case Interpreter::java_lang_math_log     : // fall thru
-    case Interpreter::java_lang_math_log10   : // fall thru
-    case Interpreter::java_lang_math_sqrt    : // fall thru
-    case Interpreter::java_lang_math_pow     : // fall thru
-    case Interpreter::java_lang_math_exp     : // fall thru
-    case Interpreter::java_lang_math_fmaD    : // fall thru
-    case Interpreter::java_lang_math_fmaF    :
-      return false;
-    default:
-      return true;
-  }
-}
-
 // How much stack a method activation needs in words.
 int AbstractInterpreter::size_top_interpreter_activation(Method* method) {
   const int entry_size = frame::interpreter_frame_monitor_size();
@@ -109,13 +89,19 @@
   // for the callee's params we only need to account for the extra
   // locals.
   int size = overhead +
-         (callee_locals - callee_params)*Interpreter::stackElementWords +
+         (callee_locals - callee_params) +
          monitors * frame::interpreter_frame_monitor_size() +
-         temps* Interpreter::stackElementWords + extra_args;
+         // On the top frame, at all times SP <= ESP, and SP is
+         // 16-aligned.  We ensure this by adjusting SP on method
+         // entry and re-entry to allow room for the maximum size of
+         // the expression stack.  When we call another method we bump
+         // SP so that no stack space is wasted.  So, only on the top
+         // frame do we need to allow max_stack words.
+         (is_top_frame ? max_stack : temps + extra_args);
 
   // On AArch64 we always keep the stack pointer 16-aligned, so we
   // must round up here.
-  size = round_to(size, 2);
+  size = align_up(size, 2);
 
   return size;
 }
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -2201,6 +2201,8 @@
   INSN(fdiv, 1, 0, 0b111111);
   INSN(fmul, 1, 0, 0b110111);
   INSN(fsub, 0, 1, 0b110101);
+  INSN(fmla, 0, 0, 0b110011);
+  INSN(fmls, 0, 1, 0b110011);
 
 #undef INSN
 
--- a/src/cpu/aarch64/vm/bytes_aarch64.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/bytes_aarch64.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -30,12 +30,6 @@
 
 class Bytes: AllStatic {
  public:
-  // Returns true if the byte ordering used by Java is different from the native byte ordering
-  // of the underlying machine. For example, this is true for Intel x86, but false for Solaris
-  // on Sparc.
-  static inline bool is_Java_byte_ordering_different(){ return true; }
-
-
   // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering
   // (no special code is needed since x86 CPUs can access unaligned data)
   static inline u2   get_native_u2(address p)         { return *(u2*)p; }
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -2740,8 +2740,7 @@
         // set already but no need to check.
         __ cbz(rscratch1, next);
 
-        __ andr(rscratch1, tmp, TypeEntries::type_unknown);
-        __ cbnz(rscratch1, next); // already unknown. Nothing to do anymore.
+        __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
 
         if (TypeEntries::is_type_none(current_klass)) {
           __ cbz(rscratch2, none);
@@ -2761,8 +2760,7 @@
                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
 
         __ ldr(tmp, mdo_addr);
-        __ andr(rscratch1, tmp, TypeEntries::type_unknown);
-        __ cbnz(rscratch1, next); // already unknown. Nothing to do anymore.
+        __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
       }
 
       // different than before. Cannot keep accurate profile.
@@ -2812,8 +2810,7 @@
                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
 
         __ ldr(tmp, mdo_addr);
-        __ andr(rscratch1, tmp, TypeEntries::type_unknown);
-        __ cbnz(rscratch1, next); // already unknown. Nothing to do anymore.
+        __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
 
         __ orr(tmp, tmp, TypeEntries::type_unknown);
         __ str(tmp, mdo_addr);
--- a/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -598,12 +598,12 @@
   } else {
     assert (x->op() == Bytecodes::_imul, "expect imul");
     if (right.is_constant()) {
-      int c = right.get_jint_constant();
-      if (! is_power_of_2(c) && ! is_power_of_2(c + 1) && ! is_power_of_2(c - 1)) {
+      jint c = right.get_jint_constant();
+      if (c > 0 && c < max_jint && (is_power_of_2(c) || is_power_of_2(c - 1) || is_power_of_2(c + 1))) {
+        right_arg->dont_load_item();
+      } else {
         // Cannot use constant op.
-        right.load_item();
-      } else {
-        right.dont_load_item();
+        right_arg->load_item();
       }
     } else {
       right.load_item();
@@ -1347,6 +1347,16 @@
 
 void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
                                        CodeEmitInfo* info) {
+  // 8179954: We need to make sure that the code generated for
+  // volatile accesses forms a sequentially-consistent set of
+  // operations when combined with STLR and LDAR.  Without a leading
+  // membar it's possible for a simple Dekker test to fail if loads
+  // use LD;DMB but stores use STLR.  This can happen if C2 compiles
+  // the stores in one method and C1 compiles the loads in another.
+  if (! UseBarriersForVolatile) {
+    __ membar();
+  }
+
   __ volatile_load_mem_reg(address, result, info);
 }
 
--- a/src/cpu/aarch64/vm/debug_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "code/codeCache.hpp"
-#include "code/nmethod.hpp"
-#include "runtime/frame.hpp"
-#include "runtime/init.hpp"
-#include "runtime/os.hpp"
-#include "utilities/debug.hpp"
-
-void pd_ps(frame f) {}
--- a/src/cpu/aarch64/vm/frame_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/frame_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -784,6 +784,8 @@
 frame::frame(void* sp, void* fp, void* pc) {
   init((intptr_t*)sp, (intptr_t*)fp, (address)pc);
 }
+
+void frame::pd_ps() {}
 #endif
 
 void JavaFrameAnchor::make_walkable(JavaThread* thread) {
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1754,8 +1754,7 @@
     // Load the offset of the area within the MDO used for
     // parameters. If it's negative we're not profiling any parameters
     ldr(tmp1, Address(mdp, in_bytes(MethodData::parameters_type_data_di_offset()) - in_bytes(MethodData::data_offset())));
-    cmp(tmp1, 0u);
-    br(Assembler::LT, profile_continue);
+    tbnz(tmp1, 63, profile_continue);  // i.e. sign bit set
 
     // Compute a pointer to the area for parameters from the offset
     // and move the pointer to the slot for the last
--- a/src/cpu/aarch64/vm/interpreterRT_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/interpreterRT_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -369,7 +369,7 @@
   }
 
  public:
-  SlowSignatureHandler(methodHandle method, address from, intptr_t* to)
+  SlowSignatureHandler(const methodHandle& method, address from, intptr_t* to)
     : NativeSignatureIterator(method)
   {
     _from = from;
--- a/src/cpu/aarch64/vm/interpreterRT_aarch64.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/interpreterRT_aarch64.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -47,7 +47,7 @@
 
  public:
   // Creation
-  SignatureHandlerGenerator(methodHandle method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
+  SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
     _masm = new MacroAssembler(buffer);
     _num_int_args = (method->is_static() ? 1 : 0);
     _num_fp_args = 0;
--- a/src/cpu/aarch64/vm/jniFastGetField_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/jniFastGetField_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -76,8 +76,7 @@
           SafepointSynchronize::safepoint_counter_addr(), offset);
   Address safepoint_counter_addr(rcounter_addr, offset);
   __ ldrw(rcounter, safepoint_counter_addr);
-  __ andw(rscratch1, rcounter, 1);
-  __ cbnzw(rscratch1, slow);
+  __ tbnz(rcounter, 0, slow);
   __ eor(robj, c_rarg1, rcounter);
   __ eor(robj, robj, rcounter);               // obj, since
                                               // robj ^ rcounter ^ rcounter == robj
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -38,6 +38,7 @@
 #include "opto/compile.hpp"
 #include "opto/intrinsicnode.hpp"
 #include "opto/node.hpp"
+#include "prims/jvm.h"
 #include "runtime/biasedLocking.hpp"
 #include "runtime/icache.hpp"
 #include "runtime/interfaceSupport.hpp"
@@ -2011,6 +2012,12 @@
   hlt(0);
 }
 
+void MacroAssembler::unimplemented(const char* what) {
+  char* b = new char[1024];
+  jio_snprintf(b, 1024, "unimplemented: %s", what);
+  stop(b);
+}
+
 // If a constant does not fit in an immediate field, generate some
 // number of MOV instructions and then perform the operation.
 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
--- a/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -169,6 +169,7 @@
 
   template<class T>
   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
+  // imm is limited to 12 bits.
   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 
   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
@@ -941,7 +942,7 @@
 
   void untested()                                { stop("untested"); }
 
-  void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
+  void unimplemented(const char* what = "");
 
   void should_not_reach_here()                   { stop("should not reach here"); }
 
@@ -949,8 +950,8 @@
   void bang_stack_with_offset(int offset) {
     // stack grows down, caller passes positive offset
     assert(offset > 0, "must bang with negative offset");
-    mov(rscratch2, -offset);
-    str(zr, Address(sp, rscratch2));
+    sub(rscratch2, sp, offset);
+    str(zr, Address(rscratch2));
   }
 
   // Writes to stack successive pages until offset reached to check for
--- a/src/cpu/aarch64/vm/methodHandles_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/methodHandles_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -137,8 +137,9 @@
   __ verify_oop(method_temp);
   __ load_heap_oop(method_temp, Address(method_temp, NONZERO(java_lang_invoke_LambdaForm::vmentry_offset_in_bytes())));
   __ verify_oop(method_temp);
-  // the following assumes that a Method* is normally compressed in the vmtarget field:
-  __ ldr(method_temp, Address(method_temp, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes())));
+  __ load_heap_oop(method_temp, Address(method_temp, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes())));
+  __ verify_oop(method_temp);
+  __ ldr(method_temp, Address(method_temp, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes())));
 
   if (VerifyMethodHandles && !for_compiler_entry) {
     // make sure recv is already on stack
@@ -282,7 +283,8 @@
 
     Address member_clazz(    member_reg, NONZERO(java_lang_invoke_MemberName::clazz_offset_in_bytes()));
     Address member_vmindex(  member_reg, NONZERO(java_lang_invoke_MemberName::vmindex_offset_in_bytes()));
-    Address member_vmtarget( member_reg, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()));
+    Address member_vmtarget( member_reg, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes()));
+    Address vmtarget_method( rmethod, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes()));
 
     Register temp1_recv_klass = temp1;
     if (iid != vmIntrinsics::_linkToStatic) {
@@ -335,14 +337,16 @@
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeSpecial, member_reg, temp3);
       }
-      __ ldr(rmethod, member_vmtarget);
+      __ load_heap_oop(rmethod, member_vmtarget);
+      __ ldr(rmethod, vmtarget_method);
       break;
 
     case vmIntrinsics::_linkToStatic:
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeStatic, member_reg, temp3);
       }
-      __ ldr(rmethod, member_vmtarget);
+      __ load_heap_oop(rmethod, member_vmtarget);
+      __ ldr(rmethod, vmtarget_method);
       break;
 
     case vmIntrinsics::_linkToVirtual:
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -36,6 +36,7 @@
 #include "oops/compiledICHolder.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/vframeArray.hpp"
+#include "utilities/align.hpp"
 #include "vmreg_aarch64.inline.hpp"
 #ifdef COMPILER1
 #include "c1/c1_Runtime1.hpp"
@@ -123,7 +124,7 @@
   assert(!save_vectors, "vectors are generated only by C2 and JVMCI");
 #endif
 
-  int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
+  int frame_size_in_bytes = align_up(additional_frame_words*wordSize +
                                      reg_save_size*BytesPerInt, 16);
   // OopMap frame size is in compiler stack slots (jint's) not bytes or words
   int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
@@ -190,7 +191,7 @@
   __ ldr(r0, Address(sp, r0_offset_in_bytes()));
 
   // Pop all of the register save are off the stack
-  __ add(sp, sp, round_to(return_offset_in_bytes(), 16));
+  __ add(sp, sp, align_up(return_offset_in_bytes(), 16));
 }
 
 // Is vector's size (in bytes) bigger than a size saved by default?
@@ -317,7 +318,7 @@
     }
   }
 
-  return round_to(stk_args, 2);
+  return align_up(stk_args, 2);
 }
 
 // Patch the callers callsite with entry to compiled code if it exists.
@@ -375,7 +376,7 @@
   __ mov(r13, sp);
 
   // stack is aligned, keep it that way
-  extraspace = round_to(extraspace, 2*wordSize);
+  extraspace = align_up(extraspace, 2*wordSize);
 
   if (extraspace)
     __ sub(sp, sp, extraspace);
@@ -547,7 +548,7 @@
   }
 
   // Cut-out for having no stack args.
-  int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
+  int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
   if (comp_args_on_stack) {
     __ sub(rscratch1, sp, comp_words_on_stack * wordSize);
     __ andr(sp, rscratch1, -16);
@@ -1206,7 +1207,7 @@
 }
 
 static void verify_oop_args(MacroAssembler* masm,
-                            methodHandle method,
+                            const methodHandle& method,
                             const BasicType* sig_bt,
                             const VMRegPair* regs) {
   Register temp_reg = r19;  // not part of any compiled calling seq
@@ -1228,7 +1229,7 @@
 }
 
 static void gen_special_dispatch(MacroAssembler* masm,
-                                 methodHandle method,
+                                 const methodHandle& method,
                                  const BasicType* sig_bt,
                                  const VMRegPair* regs) {
   verify_oop_args(masm, method, sig_bt, regs);
@@ -1486,7 +1487,7 @@
     total_save_slots = double_slots * 2 + single_slots;
     // align the save area
     if (double_slots != 0) {
-      stack_slots = round_to(stack_slots, 2);
+      stack_slots = align_up(stack_slots, 2);
     }
   }
 
@@ -1543,7 +1544,7 @@
 
   // Now compute actual number of stack words we need rounding to make
   // stack properly aligned.
-  stack_slots = round_to(stack_slots, StackAlignmentInSlots);
+  stack_slots = align_up(stack_slots, StackAlignmentInSlots);
 
   int stack_size = stack_slots * VMRegImpl::stack_slot_size;
 
@@ -2293,7 +2294,7 @@
     return 0;                   // No adjustment for negative locals
   int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
   // diff is counted in stack words
-  return round_to(diff, 2);
+  return align_up(diff, 2);
 }
 
 
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -39,6 +39,7 @@
 #include "runtime/stubCodeGenerator.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "runtime/thread.inline.hpp"
+#include "utilities/align.hpp"
 #ifdef COMPILER2
 #include "opto/runtime.hpp"
 #endif
@@ -619,19 +620,21 @@
 
   // Generate code for an array write pre barrier
   //
-  //     addr    -  starting address
-  //     count   -  element count
-  //     tmp     - scratch register
+  //     addr       - starting address
+  //     count      - element count
+  //     tmp        - scratch register
+  //     saved_regs - registers to be saved before calling static_write_ref_array_pre
   //
-  //     Destroy no registers except rscratch1 and rscratch2
+  //     Callers must specify which registers to preserve in saved_regs.
+  //     Clobbers: r0-r18, v0-v7, v16-v31, except saved_regs.
   //
-  void  gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized) {
+  void gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized, RegSet saved_regs) {
     BarrierSet* bs = Universe::heap()->barrier_set();
     switch (bs->kind()) {
     case BarrierSet::G1SATBCTLogging:
       // With G1, don't generate the call if we statically know that the target in uninitialized
       if (!dest_uninitialized) {
-        __ push_call_clobbered_registers();
+        __ push(saved_regs, sp);
         if (count == c_rarg0) {
           if (addr == c_rarg1) {
             // exactly backwards!!
@@ -647,7 +650,7 @@
           __ mov(c_rarg1, count);
         }
         __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2);
-        __ pop_call_clobbered_registers();
+        __ pop(saved_regs, sp);
         break;
       case BarrierSet::CardTableForRS:
       case BarrierSet::CardTableExtension:
@@ -664,20 +667,23 @@
   // Generate code for an array write post barrier
   //
   //  Input:
-  //     start    - register containing starting address of destination array
-  //     end      - register containing ending address of destination array
-  //     scratch  - scratch register
+  //     start      - register containing starting address of destination array
+  //     end        - register containing ending address of destination array
+  //     scratch    - scratch register
+  //     saved_regs - registers to be saved before calling static_write_ref_array_post
   //
   //  The input registers are overwritten.
   //  The ending address is inclusive.
-  void gen_write_ref_array_post_barrier(Register start, Register end, Register scratch) {
+  //  Callers must specify which registers to preserve in saved_regs.
+  //  Clobbers: r0-r18, v0-v7, v16-v31, except saved_regs.
+  void gen_write_ref_array_post_barrier(Register start, Register end, Register scratch, RegSet saved_regs) {
     assert_different_registers(start, end, scratch);
     BarrierSet* bs = Universe::heap()->barrier_set();
     switch (bs->kind()) {
       case BarrierSet::G1SATBCTLogging:
 
         {
-          __ push_call_clobbered_registers();
+          __ push(saved_regs, sp);
           // must compute element count unless barrier set interface is changed (other platforms supply count)
           assert_different_registers(start, end, scratch);
           __ lea(scratch, Address(end, BytesPerHeapOop));
@@ -686,7 +692,7 @@
           __ mov(c_rarg0, start);
           __ mov(c_rarg1, scratch);
           __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post), 2);
-          __ pop_call_clobbered_registers();
+          __ pop(saved_regs, sp);
         }
         break;
       case BarrierSet::CardTableForRS:
@@ -758,7 +764,7 @@
       // alignment.
       Label small;
       int low_limit = MAX2(zva_length * 2, (int)BlockZeroingLowLimit);
-      __ cmp(cnt, low_limit >> 3);
+      __ subs(rscratch1, cnt, low_limit >> 3);
       __ br(Assembler::LT, small);
       __ zero_dcache_blocks(base, cnt);
       __ bind(small);
@@ -821,7 +827,7 @@
     Label again, drain;
     const char *stub_name;
     if (direction == copy_forwards)
-      stub_name = "foward_copy_longs";
+      stub_name = "forward_copy_longs";
     else
       stub_name = "backward_copy_longs";
     StubCodeMark mark(this, "StubRoutines", stub_name);
@@ -1438,6 +1444,7 @@
   address generate_disjoint_copy(size_t size, bool aligned, bool is_oop, address *entry,
                                   const char *name, bool dest_uninitialized = false) {
     Register s = c_rarg0, d = c_rarg1, count = c_rarg2;
+    RegSet saved_reg = RegSet::of(s, d, count);
     __ align(CodeEntryAlignment);
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ pc();
@@ -1450,9 +1457,9 @@
     }
 
     if (is_oop) {
+      gen_write_ref_array_pre_barrier(d, count, dest_uninitialized, saved_reg);
+      // save regs before copy_memory
       __ push(RegSet::of(d, count), sp);
-      // no registers are destroyed by this call
-      gen_write_ref_array_pre_barrier(d, count, dest_uninitialized);
     }
     copy_memory(aligned, s, d, count, rscratch1, size);
     if (is_oop) {
@@ -1461,7 +1468,7 @@
         verify_oop_array(size, d, count, r16);
       __ sub(count, count, 1); // make an inclusive end pointer
       __ lea(count, Address(d, count, Address::lsl(exact_log2(size))));
-      gen_write_ref_array_post_barrier(d, count, rscratch1);
+      gen_write_ref_array_post_barrier(d, count, rscratch1, RegSet());
     }
     __ leave();
     __ mov(r0, zr); // return 0
@@ -1494,7 +1501,7 @@
                                  address *entry, const char *name,
                                  bool dest_uninitialized = false) {
     Register s = c_rarg0, d = c_rarg1, count = c_rarg2;
-
+    RegSet saved_regs = RegSet::of(s, d, count);
     StubCodeMark mark(this, "StubRoutines", name);
     address start = __ pc();
     __ enter();
@@ -1511,9 +1518,9 @@
     __ br(Assembler::HS, nooverlap_target);
 
     if (is_oop) {
+      gen_write_ref_array_pre_barrier(d, count, dest_uninitialized, saved_regs);
+      // save regs before copy_memory
       __ push(RegSet::of(d, count), sp);
-      // no registers are destroyed by this call
-      gen_write_ref_array_pre_barrier(d, count, dest_uninitialized);
     }
     copy_memory(aligned, s, d, count, rscratch1, -size);
     if (is_oop) {
@@ -1522,7 +1529,7 @@
         verify_oop_array(size, d, count, r16);
       __ sub(count, count, 1); // make an inclusive end pointer
       __ lea(count, Address(d, count, Address::lsl(exact_log2(size))));
-      gen_write_ref_array_post_barrier(d, count, rscratch1);
+      gen_write_ref_array_post_barrier(d, count, rscratch1, RegSet());
     }
     __ leave();
     __ mov(r0, zr); // return 0
@@ -1804,6 +1811,9 @@
     const Register ckoff       = c_rarg3;   // super_check_offset
     const Register ckval       = c_rarg4;   // super_klass
 
+    RegSet wb_pre_saved_regs = RegSet::range(c_rarg0, c_rarg4);
+    RegSet wb_post_saved_regs = RegSet::of(count);
+
     // Registers used as temps (r18, r19, r20 are save-on-entry)
     const Register count_save  = r21;       // orig elementscount
     const Register start_to    = r20;       // destination array start address
@@ -1861,7 +1871,7 @@
     }
 #endif //ASSERT
 
-    gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
+    gen_write_ref_array_pre_barrier(to, count, dest_uninitialized, wb_pre_saved_regs);
 
     // save the original count
     __ mov(count_save, count);
@@ -1905,7 +1915,7 @@
 
     __ BIND(L_do_card_marks);
     __ add(to, to, -heapOopSize);         // make an inclusive end pointer
-    gen_write_ref_array_post_barrier(start_to, to, rscratch1);
+    gen_write_ref_array_post_barrier(start_to, to, rscratch1, wb_post_saved_regs);
 
     __ bind(L_done_pop);
     __ pop(RegSet::of(r18, r19, r20, r21), sp);
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -246,8 +246,7 @@
       assert(load_bc_into_bc_reg, "we use bc_reg as temp");
       __ get_cache_and_index_and_bytecode_at_bcp(temp_reg, bc_reg, temp_reg, byte_no, 1);
       __ movw(bc_reg, bc);
-      __ cmpw(temp_reg, (unsigned) 0);
-      __ br(Assembler::EQ, L_patch_done);  // don't patch
+      __ cbzw(temp_reg, L_patch_done);  // don't patch
     }
     break;
   default:
@@ -2389,17 +2388,31 @@
   const Register obj   = r4;
   const Register off   = r19;
   const Register flags = r0;
+  const Register raw_flags = r6;
   const Register bc    = r4; // uses same reg as obj, so don't mix them
 
   resolve_cache_and_index(byte_no, cache, index, sizeof(u2));
   jvmti_post_field_access(cache, index, is_static, false);
-  load_field_cp_cache_entry(obj, cache, index, off, flags, is_static);
+  load_field_cp_cache_entry(obj, cache, index, off, raw_flags, is_static);
 
   if (!is_static) {
     // obj is on the stack
     pop_and_check_object(obj);
   }
 
+  // 8179954: We need to make sure that the code generated for
+  // volatile accesses forms a sequentially-consistent set of
+  // operations when combined with STLR and LDAR.  Without a leading
+  // membar it's possible for a simple Dekker test to fail if loads
+  // use LDR;DMB but stores use STLR.  This can happen if C2 compiles
+  // the stores in one method and we interpret the loads in another.
+  if (! UseBarriersForVolatile) {
+    Label notVolatile;
+    __ tbz(raw_flags, ConstantPoolCacheEntry::is_volatile_shift, notVolatile);
+    __ membar(MacroAssembler::AnyAny);
+    __ bind(notVolatile);
+  }
+
   const Address field(obj, off);
 
   Label Done, notByte, notBool, notInt, notShort, notChar,
@@ -2407,7 +2420,8 @@
 
   // x86 uses a shift and mask or wings it with a shift plus assert
   // the mask is not needed. aarch64 just uses bitfield extract
-  __ ubfxw(flags, flags, ConstantPoolCacheEntry::tos_state_shift,  ConstantPoolCacheEntry::tos_state_bits);
+  __ ubfxw(flags, raw_flags, ConstantPoolCacheEntry::tos_state_shift,
+           ConstantPoolCacheEntry::tos_state_bits);
 
   assert(btos == 0, "change code, btos != 0");
   __ cbnz(flags, notByte);
@@ -2529,9 +2543,11 @@
 #endif
 
   __ bind(Done);
-  // It's really not worth bothering to check whether this field
-  // really is volatile in the slow case.
+
+  Label notVolatile;
+  __ tbz(raw_flags, ConstantPoolCacheEntry::is_volatile_shift, notVolatile);
   __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
+  __ bind(notVolatile);
 }
 
 
@@ -2979,6 +2995,19 @@
   __ null_check(r0);
   const Address field(r0, r1);
 
+  // 8179954: We need to make sure that the code generated for
+  // volatile accesses forms a sequentially-consistent set of
+  // operations when combined with STLR and LDAR.  Without a leading
+  // membar it's possible for a simple Dekker test to fail if loads
+  // use LDR;DMB but stores use STLR.  This can happen if C2 compiles
+  // the stores in one method and we interpret the loads in another.
+  if (! UseBarriersForVolatile) {
+    Label notVolatile;
+    __ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile);
+    __ membar(MacroAssembler::AnyAny);
+    __ bind(notVolatile);
+  }
+
   // access field
   switch (bytecode()) {
   case Bytecodes::_fast_agetfield:
@@ -3027,6 +3056,22 @@
   __ get_cache_and_index_at_bcp(r2, r3, 2);
   __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
                                   ConstantPoolCacheEntry::f2_offset())));
+
+  // 8179954: We need to make sure that the code generated for
+  // volatile accesses forms a sequentially-consistent set of
+  // operations when combined with STLR and LDAR.  Without a leading
+  // membar it's possible for a simple Dekker test to fail if loads
+  // use LDR;DMB but stores use STLR.  This can happen if C2 compiles
+  // the stores in one method and we interpret the loads in another.
+  if (! UseBarriersForVolatile) {
+    Label notVolatile;
+    __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
+                                     ConstantPoolCacheEntry::flags_offset())));
+    __ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile);
+    __ membar(MacroAssembler::AnyAny);
+    __ bind(notVolatile);
+  }
+
   // make sure exception is reported in correct bcp range (getfield is
   // next instruction)
   __ increment(rbcp);
--- a/src/cpu/aarch64/vm/vtableStubs_aarch64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/aarch64/vm/vtableStubs_aarch64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -51,6 +51,11 @@
 VtableStub* VtableStubs::create_vtable_stub(int vtable_index) {
   const int aarch64_code_length = VtableStub::pd_code_size_limit(true);
   VtableStub* s = new(aarch64_code_length) VtableStub(true, vtable_index);
+  // Can be NULL if there is no free space in the code cache.
+  if (s == NULL) {
+    return NULL;
+  }
+
   ResourceMark rm;
   CodeBuffer cb(s->entry_point(), aarch64_code_length);
   MacroAssembler* masm = new MacroAssembler(&cb);
--- a/src/cpu/arm/vm/abstractInterpreter_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/abstractInterpreter_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -32,6 +32,7 @@
 #include "runtime/handles.inline.hpp"
 #include "runtime/frame.inline.hpp"
 #include "runtime/synchronizer.hpp"
+#include "utilities/align.hpp"
 #include "utilities/macros.hpp"
 
 int AbstractInterpreter::BasicType_as_index(BasicType type) {
@@ -68,23 +69,6 @@
   return i;
 }
 
-// These should never be compiled since the interpreter will prefer
-// the compiled version to the intrinsic version.
-bool AbstractInterpreter::can_be_compiled(methodHandle m) {
-  switch (method_kind(m)) {
-    case Interpreter::java_lang_math_sin     : // fall thru
-    case Interpreter::java_lang_math_cos     : // fall thru
-    case Interpreter::java_lang_math_tan     : // fall thru
-    case Interpreter::java_lang_math_abs     : // fall thru
-    case Interpreter::java_lang_math_log     : // fall thru
-    case Interpreter::java_lang_math_log10   : // fall thru
-    case Interpreter::java_lang_math_sqrt    :
-      return false;
-    default:
-      return true;
-  }
-}
-
 // How much stack a method activation needs in words.
 int AbstractInterpreter::size_top_interpreter_activation(Method* method) {
   const int stub_code = AARCH64_ONLY(24) NOT_AARCH64(12);  // see generate_call_stub
@@ -125,7 +109,7 @@
          tempcount*Interpreter::stackElementWords + extra_args;
 
 #ifdef AARCH64
-  size = round_to(size, StackAlignmentInBytes/BytesPerWord);
+  size = align_up(size, StackAlignmentInBytes/BytesPerWord);
 #endif // AARCH64
 
   return size;
@@ -206,7 +190,7 @@
   }
   if (caller->is_interpreted_frame()) {
     intptr_t* locals_base = (locals - method->max_locals()*Interpreter::stackElementWords + 1);
-    locals_base = (intptr_t*)round_down((intptr_t)locals_base, StackAlignmentInBytes);
+    locals_base = align_down(locals_base, StackAlignmentInBytes);
     assert(interpreter_frame->sender_sp() <= locals_base, "interpreter-to-interpreter frame chaining");
 
   } else if (caller->is_compiled_frame()) {
@@ -244,7 +228,7 @@
   intptr_t* extended_sp = (intptr_t*) monbot  -
     (max_stack * Interpreter::stackElementWords) -
     popframe_extra_args;
-  extended_sp = (intptr_t*)round_down((intptr_t)extended_sp, StackAlignmentInBytes);
+  extended_sp = align_down(extended_sp, StackAlignmentInBytes);
   interpreter_frame->interpreter_frame_set_extended_sp(extended_sp);
 #else
   interpreter_frame->interpreter_frame_set_last_sp(stack_top);
@@ -256,7 +240,7 @@
 
 #ifdef AARCH64
   if (caller->is_interpreted_frame()) {
-    intptr_t* sender_sp = (intptr_t*)round_down((intptr_t)caller->interpreter_frame_tos_address(), StackAlignmentInBytes);
+    intptr_t* sender_sp = align_down(caller->interpreter_frame_tos_address(), StackAlignmentInBytes);
     interpreter_frame->set_interpreter_frame_sender_sp(sender_sp);
 
   } else {
--- a/src/cpu/arm/vm/arm.ad	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/arm.ad	Thu Aug 10 09:23:41 2017 +0200
@@ -1881,7 +1881,7 @@
   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
   // Otherwise, it is above the locks and verification slot and alignment word
   return_addr(STACK - 1*VMRegImpl::slots_per_word +
-              round_to((Compile::current()->in_preserve_stack_slots() +
+              align_up((Compile::current()->in_preserve_stack_slots() +
                         Compile::current()->fixed_slots()),
                        stack_alignment_in_slots()));
 
@@ -11752,9 +11752,13 @@
 
   size(4);
   // Use the following format syntax
-  format %{ "breakpoint   ; ShouldNotReachHere" %}
-  ins_encode %{
-    __ breakpoint();
+  format %{ "ShouldNotReachHere" %}
+  ins_encode %{
+#ifdef AARCH64
+    __ dpcs1(0xdead);
+#else
+    __ udf(0xdead);
+#endif
   %}
   ins_pipe(tail_call);
 %}
--- a/src/cpu/arm/vm/assembler_arm_32.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/assembler_arm_32.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -578,6 +578,11 @@
   F(bl, 0xb)
 #undef F
 
+  void udf(int imm_16) {
+    assert((imm_16 >> 16) == 0, "encoding constraint");
+    emit_int32(0xe7f000f0 | (imm_16 & 0xfff0) << 8 | (imm_16 & 0xf));
+  }
+
   // ARMv7 instructions
 
 #define F(mnemonic, wt) \
--- a/src/cpu/arm/vm/assembler_arm_64.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/assembler_arm_64.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1083,6 +1083,7 @@
 
   F(brk, 0b001, 0b000, 0b00)
   F(hlt, 0b010, 0b000, 0b00)
+  F(dpcs1, 0b101, 0b000, 0b01)
 #undef F
 
   enum SystemRegister { // o0<1> op1<3> CRn<4> CRm<4> op2<3>
--- a/src/cpu/arm/vm/bytes_arm.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/bytes_arm.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -35,12 +35,6 @@
 class Bytes: AllStatic {
 
  public:
-  // Returns true if the byte ordering used by Java is different from the native byte ordering
-  // of the underlying machine.
-  static inline bool is_Java_byte_ordering_different() {
-    return VM_LITTLE_ENDIAN != 0;
-  }
-
   static inline u2 get_Java_u2(address p) {
     return (u2(p[0]) << 8) | u2(p[1]);
   }
--- a/src/cpu/arm/vm/c1_LIRGenerator_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/c1_LIRGenerator_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -923,8 +923,8 @@
   } else {
     left_arg->load_item();
     if (x->op() == Bytecodes::_imul && right_arg->is_constant()) {
-      int c = right_arg->get_jint_constant();
-      if (c > 0 && (is_power_of_2(c) || is_power_of_2(c - 1) || is_power_of_2(c + 1))) {
+      jint c = right_arg->get_jint_constant();
+      if (c > 0 && c < max_jint && (is_power_of_2(c) || is_power_of_2(c - 1) || is_power_of_2(c + 1))) {
         right_arg->dont_load_item();
       } else {
         right_arg->load_item();
--- a/src/cpu/arm/vm/c1_Runtime1_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/c1_Runtime1_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -37,6 +37,7 @@
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/signature.hpp"
 #include "runtime/vframeArray.hpp"
+#include "utilities/align.hpp"
 #include "vmreg_arm.inline.hpp"
 #if INCLUDE_ALL_GCS
 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
@@ -250,7 +251,7 @@
 
   __ sub(SP, SP, (reg_save_size - 2) * wordSize);
 
-  for (int i = 0; i < round_down(number_of_saved_gprs, 2); i += 2) {
+  for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) {
     __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
   }
 
--- a/src/cpu/arm/vm/debug_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "code/codeCache.hpp"
-#include "code/nmethod.hpp"
-#include "runtime/frame.hpp"
-#include "runtime/init.hpp"
-#include "runtime/os.hpp"
-#include "utilities/debug.hpp"
-
-void pd_ps(frame f) {}
--- a/src/cpu/arm/vm/frame_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/frame_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -621,6 +621,8 @@
 frame::frame(void* sp, void* fp, void* pc) {
   init((intptr_t*)sp, (intptr_t*)fp, (address)pc);
 }
+
+void frame::pd_ps() {}
 #endif
 
 intptr_t *frame::initial_deoptimization_info() {
--- a/src/cpu/arm/vm/interpreterRT_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/interpreterRT_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -422,7 +422,7 @@
 #endif // !__ABI_HARD__
 
  public:
-  SlowSignatureHandler(methodHandle method, address from, intptr_t* to) :
+  SlowSignatureHandler(const methodHandle& method, address from, intptr_t* to) :
     NativeSignatureIterator(method) {
     _from = from;
 
--- a/src/cpu/arm/vm/interpreterRT_arm.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/interpreterRT_arm.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -56,7 +56,7 @@
 #endif
  public:
   // Creation
-  SignatureHandlerGenerator(methodHandle method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
+  SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
     _masm = new MacroAssembler(buffer);
     _abi_offset = 0;
     _ireg = is_static() ? 2 : 1;
--- a/src/cpu/arm/vm/methodHandles_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/methodHandles_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -32,6 +32,7 @@
 #include "interpreter/interpreterRuntime.hpp"
 #include "memory/allocation.inline.hpp"
 #include "memory/resourceArea.hpp"
+#include "prims/jvm.h"
 #include "prims/methodHandles.hpp"
 
 #define __ _masm->
@@ -157,8 +158,9 @@
   __ load_heap_oop(tmp, Address(tmp, NONZERO(java_lang_invoke_LambdaForm::vmentry_offset_in_bytes())));
   __ verify_oop(tmp);
 
-  // the following assumes that a Method* is normally compressed in the vmtarget field:
-  __ ldr(Rmethod, Address(tmp, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes())));
+  __ load_heap_oop(Rmethod, Address(tmp, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes())));
+  __ verify_oop(Rmethod);
+  __ ldr(Rmethod, Address(Rmethod, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes())));
 
   if (VerifyMethodHandles && !for_compiler_entry) {
     // make sure recv is already on stack
@@ -320,7 +322,8 @@
 
     Address member_clazz(   member_reg, NONZERO(java_lang_invoke_MemberName::clazz_offset_in_bytes()));
     Address member_vmindex( member_reg, NONZERO(java_lang_invoke_MemberName::vmindex_offset_in_bytes()));
-    Address member_vmtarget(member_reg, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()));
+    Address member_vmtarget(member_reg, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes()));
+    Address vmtarget_method(Rmethod, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes()));
 
     Register temp1_recv_klass = temp1;
     if (iid != vmIntrinsics::_linkToStatic) {
@@ -375,14 +378,17 @@
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeSpecial, member_reg, temp3);
       }
-      __ ldr(Rmethod, member_vmtarget);
+      __ load_heap_oop(Rmethod, member_vmtarget);
+      __ ldr(Rmethod, vmtarget_method);
       break;
 
     case vmIntrinsics::_linkToStatic:
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeStatic, member_reg, temp3);
       }
-      __ ldr(Rmethod, member_vmtarget);
+      __ load_heap_oop(Rmethod, member_vmtarget);
+      __ ldr(Rmethod, vmtarget_method);
+      break;
       break;
 
     case vmIntrinsics::_linkToVirtual:
--- a/src/cpu/arm/vm/relocInfo_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/relocInfo_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -139,7 +139,7 @@
 #ifdef AARCH64
 #ifdef COMPILER2
   NativeMovConstReg* ni = nativeMovConstReg_at(addr());
-  if (ni->is_movz()) {
+  if (ni->is_mov_slow()) {
     return;
   }
 #endif
--- a/src/cpu/arm/vm/sharedRuntime_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/sharedRuntime_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -34,6 +34,7 @@
 #include "oops/compiledICHolder.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/vframeArray.hpp"
+#include "utilities/align.hpp"
 #include "vmreg_arm.inline.hpp"
 #ifdef COMPILER1
 #include "c1/c1_Runtime1.hpp"
@@ -747,7 +748,7 @@
   assert_different_registers(tmp, R0, R1, R2, R3, R4, R5, R6, R7, Rsender_sp, Rparams);
 
   if (comp_args_on_stack) {
-    __ sub_slow(SP, SP, round_to(comp_args_on_stack * VMRegImpl::stack_slot_size, StackAlignmentInBytes));
+    __ sub_slow(SP, SP, align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, StackAlignmentInBytes));
   }
 
   for (int i = 0; i < total_args_passed; i++) {
@@ -870,7 +871,7 @@
 
 #ifdef AARCH64
 
-  int extraspace = round_to(total_args_passed * Interpreter::stackElementSize, StackAlignmentInBytes);
+  int extraspace = align_up(total_args_passed * Interpreter::stackElementSize, StackAlignmentInBytes);
   if (extraspace) {
     __ sub(SP, SP, extraspace);
   }
@@ -1023,7 +1024,7 @@
 
 
 static void verify_oop_args(MacroAssembler* masm,
-                            methodHandle method,
+                            const methodHandle& method,
                             const BasicType* sig_bt,
                             const VMRegPair* regs) {
   Register temp_reg = Rmethod;  // not part of any compiled calling seq
@@ -1044,7 +1045,7 @@
 }
 
 static void gen_special_dispatch(MacroAssembler* masm,
-                                 methodHandle method,
+                                 const methodHandle& method,
                                  const BasicType* sig_bt,
                                  const VMRegPair* regs) {
   verify_oop_args(masm, method, sig_bt, regs);
@@ -1181,7 +1182,7 @@
   stack_slots += 2 * VMRegImpl::slots_per_word;
 
   // Calculate the final stack size taking account of alignment
-  stack_slots = round_to(stack_slots, StackAlignmentInBytes / VMRegImpl::stack_slot_size);
+  stack_slots = align_up(stack_slots, StackAlignmentInBytes / VMRegImpl::stack_slot_size);
   int stack_size = stack_slots * VMRegImpl::stack_slot_size;
   int lock_slot_fp_offset = stack_size - 2 * wordSize -
     lock_slot_offset * VMRegImpl::stack_slot_size;
@@ -1851,7 +1852,7 @@
 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
   int extra_locals_size = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
 #ifdef AARCH64
-  extra_locals_size = round_to(extra_locals_size, StackAlignmentInBytes/BytesPerWord);
+  extra_locals_size = align_up(extra_locals_size, StackAlignmentInBytes/BytesPerWord);
 #endif // AARCH64
   return extra_locals_size;
 }
--- a/src/cpu/arm/vm/stubGenerator_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/stubGenerator_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -37,6 +37,7 @@
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubCodeGenerator.hpp"
 #include "runtime/stubRoutines.hpp"
+#include "utilities/align.hpp"
 #ifdef COMPILER2
 #include "opto/runtime.hpp"
 #endif
@@ -2876,7 +2877,7 @@
       BLOCK_COMMENT("PreBarrier");
 
 #ifdef AARCH64
-      callee_saved_regs = round_to(callee_saved_regs, 2);
+      callee_saved_regs = align_up(callee_saved_regs, 2);
       for (int i = 0; i < callee_saved_regs; i += 2) {
         __ raw_push(as_Register(i), as_Register(i+1));
       }
--- a/src/cpu/arm/vm/templateInterpreterGenerator_arm.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/templateInterpreterGenerator_arm.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -45,6 +45,7 @@
 #include "runtime/synchronizer.hpp"
 #include "runtime/timer.hpp"
 #include "runtime/vframeArray.hpp"
+#include "utilities/align.hpp"
 #include "utilities/debug.hpp"
 #include "utilities/macros.hpp"
 
@@ -675,7 +676,7 @@
   // Rstack_top & RextendedSP
   __ sub(Rstack_top, SP, 10*wordSize);
   if (native_call) {
-    __ sub(RextendedSP, Rstack_top, round_to(wordSize, StackAlignmentInBytes));    // reserve 1 slot for exception handling
+    __ sub(RextendedSP, Rstack_top, align_up(wordSize, StackAlignmentInBytes));    // reserve 1 slot for exception handling
   } else {
     __ sub(RextendedSP, Rstack_top, AsmOperand(RmaxStack, lsl, Interpreter::logStackElementSize));
     __ align_reg(RextendedSP, RextendedSP, StackAlignmentInBytes);
@@ -1095,7 +1096,7 @@
   // Allocate more stack space to accomodate all arguments passed on GP and FP registers:
   // 8 * wordSize for GPRs
   // 8 * wordSize for FPRs
-  int reg_arguments = round_to(8*wordSize + 8*wordSize, StackAlignmentInBytes);
+  int reg_arguments = align_up(8*wordSize + 8*wordSize, StackAlignmentInBytes);
 #else
 
   // C functions need aligned stack
@@ -1108,7 +1109,7 @@
   // Allocate more stack space to accomodate all GP as well as FP registers:
   // 4 * wordSize
   // 8 * BytesPerLong
-  int reg_arguments = round_to((4*wordSize) + (8*BytesPerLong), StackAlignmentInBytes);
+  int reg_arguments = align_up((4*wordSize) + (8*BytesPerLong), StackAlignmentInBytes);
 #else
   // Reserve at least 4 words on the stack for loading
   // of parameters passed on registers (R0-R3).
--- a/src/cpu/arm/vm/vm_version_arm_32.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/vm_version_arm_32.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -25,6 +25,7 @@
 #include "precompiled.hpp"
 #include "asm/macroAssembler.inline.hpp"
 #include "memory/resourceArea.hpp"
+#include "prims/jvm.h"
 #include "runtime/java.hpp"
 #include "runtime/os.inline.hpp"
 #include "runtime/stubCodeGenerator.hpp"
@@ -256,7 +257,9 @@
     }
   }
 
-  AllocatePrefetchDistance = 128;
+  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
+    FLAG_SET_DEFAULT(AllocatePrefetchDistance, 128);
+  }
 
 #ifdef COMPILER2
   FLAG_SET_DEFAULT(UseFPUForSpilling, true);
--- a/src/cpu/arm/vm/vm_version_arm_64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/arm/vm/vm_version_arm_64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -25,6 +25,7 @@
 #include "precompiled.hpp"
 #include "asm/macroAssembler.inline.hpp"
 #include "memory/resourceArea.hpp"
+#include "prims/jvm.h"
 #include "runtime/java.hpp"
 #include "runtime/os.inline.hpp"
 #include "runtime/stubCodeGenerator.hpp"
@@ -201,7 +202,9 @@
     }
   }
 
-  AllocatePrefetchDistance = 128;
+  if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
+    FLAG_SET_DEFAULT(AllocatePrefetchDistance, 128);
+  }
 
 #ifdef COMPILER2
   FLAG_SET_DEFAULT(UseFPUForSpilling, true);
--- a/src/cpu/ppc/vm/abstractInterpreter_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/abstractInterpreter_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2014, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2015 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -51,27 +51,6 @@
   return i;
 }
 
-// These should never be compiled since the interpreter will prefer
-// the compiled version to the intrinsic version.
-bool AbstractInterpreter::can_be_compiled(methodHandle m) {
-  switch (method_kind(m)) {
-    case Interpreter::java_lang_math_sin     : // fall thru
-    case Interpreter::java_lang_math_cos     : // fall thru
-    case Interpreter::java_lang_math_tan     : // fall thru
-    case Interpreter::java_lang_math_abs     : // fall thru
-    case Interpreter::java_lang_math_log     : // fall thru
-    case Interpreter::java_lang_math_log10   : // fall thru
-    case Interpreter::java_lang_math_sqrt    : // fall thru
-    case Interpreter::java_lang_math_pow     : // fall thru
-    case Interpreter::java_lang_math_exp     : // fall thru
-    case Interpreter::java_lang_math_fmaD    : // fall thru
-    case Interpreter::java_lang_math_fmaF    :
-      return false;
-    default:
-      return true;
-  }
-}
-
 // How much stack a method activation needs in stack slots.
 // We must calc this exactly like in generate_fixed_frame.
 // Note: This returns the conservative size assuming maximum alignment.
--- a/src/cpu/ppc/vm/assembler_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/assembler_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
+ * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -376,10 +376,12 @@
     STWX_OPCODE  = (31u << OPCODE_SHIFT | 151u << 1),
     STWU_OPCODE  = (37u << OPCODE_SHIFT),
     STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
+    STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1),
 
     STH_OPCODE   = (44u << OPCODE_SHIFT),
     STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
     STHU_OPCODE  = (45u << OPCODE_SHIFT),
+    STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
 
     STB_OPCODE   = (38u << OPCODE_SHIFT),
     STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
@@ -401,11 +403,13 @@
     LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
     LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
     LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
+    LDBRX_OPCODE  = (31u << OPCODE_SHIFT | 532u << 1),              // X-FORM
 
     STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
     STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
-    STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),                  // X-FORM
+    STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),              // X-FORM
     STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
+    STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1),              // X-FORM
 
     RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
     RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
@@ -507,6 +511,7 @@
     STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
     MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
     MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),
+    MTVSRWA_OPCODE = (31u << OPCODE_SHIFT |  211u << 1),
 
     // Vector Permute and Formatting
     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
@@ -1552,6 +1557,9 @@
   inline void ld(   Register d, int si16,    Register s1);
   inline void ldu(  Register d, int si16,    Register s1);
 
+  // 8 bytes reversed
+  inline void ldbrx( Register d, Register s1, Register s2);
+
   // For convenience. Load pointer into d from b+s1.
   inline void ld_ptr(Register d, int b, Register s1);
   DEBUG_ONLY(inline void ld_ptr(Register d, ByteSize b, Register s1);)
@@ -1560,10 +1568,12 @@
   inline void stwx( Register d, Register s1, Register s2);
   inline void stw(  Register d, int si16,    Register s1);
   inline void stwu( Register d, int si16,    Register s1);
+  inline void stwbrx( Register d, Register s1, Register s2);
 
   inline void sthx( Register d, Register s1, Register s2);
   inline void sth(  Register d, int si16,    Register s1);
   inline void sthu( Register d, int si16,    Register s1);
+  inline void sthbrx( Register d, Register s1, Register s2);
 
   inline void stbx( Register d, Register s1, Register s2);
   inline void stb(  Register d, int si16,    Register s1);
@@ -1573,6 +1583,7 @@
   inline void std(  Register d, int si16,    Register s1);
   inline void stdu( Register d, int si16,    Register s1);
   inline void stdux(Register s, Register a,  Register b);
+  inline void stdbrx( Register d, Register s1, Register s2);
 
   inline void st_ptr(Register d, int si16,    Register s1);
   DEBUG_ONLY(inline void st_ptr(Register d, ByteSize b, Register s1);)
@@ -2128,6 +2139,11 @@
   inline void mtvrd(    VectorRegister  d, Register a);
   inline void mfvrd(    Register        a, VectorRegister d);
 
+  // Vector-Scalar (VSX) instructions.
+  inline void mtfprd(   FloatRegister   d, Register a);
+  inline void mtfprwa(  FloatRegister   d, Register a);
+  inline void mffprd(   Register        a, FloatRegister d);
+
   // AES (introduced with Power 8)
   inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
@@ -2182,14 +2198,18 @@
   inline void lbz(  Register d, int si16);
   inline void ldx(  Register d, Register s2);
   inline void ld(   Register d, int si16);
+  inline void ldbrx(Register d, Register s2);
   inline void stwx( Register d, Register s2);
   inline void stw(  Register d, int si16);
+  inline void stwbrx( Register d, Register s2);
   inline void sthx( Register d, Register s2);
   inline void sth(  Register d, int si16);
+  inline void sthbrx( Register d, Register s2);
   inline void stbx( Register d, Register s2);
   inline void stb(  Register d, int si16);
   inline void stdx( Register d, Register s2);
   inline void std(  Register d, int si16);
+  inline void stdbrx( Register d, Register s2);
 
   // PPC 2, section 3.2.1 Instruction Cache Instructions
   inline void icbi(    Register s2);
--- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
+ * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -327,6 +327,7 @@
 inline void Assembler::ld(   Register d, int si16,    Register s1) { emit_int32(LD_OPCODE  | rt(d) | ds(si16)   | ra0mem(s1));}
 inline void Assembler::ldx(  Register d, Register s1, Register s2) { emit_int32(LDX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
 inline void Assembler::ldu(  Register d, int si16,    Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LDU_OPCODE | rt(d) | ds(si16) | rta0mem(s1));}
+inline void Assembler::ldbrx( Register d, Register s1, Register s2) { emit_int32(LDBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));}
 
 inline void Assembler::ld_ptr(Register d, int b, Register s1) { ld(d, b, s1); }
 DEBUG_ONLY(inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) { ld(d, in_bytes(b), s1); })
@@ -335,10 +336,12 @@
 inline void Assembler::stwx( Register d, Register s1, Register s2) { emit_int32(STWX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 inline void Assembler::stw(  Register d, int si16,    Register s1) { emit_int32(STW_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
 inline void Assembler::stwu( Register d, int si16,    Register s1) { emit_int32(STWU_OPCODE | rs(d) | d1(si16)   | rta0mem(s1));}
+inline void Assembler::stwbrx( Register d, Register s1, Register s2) { emit_int32(STWBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 
 inline void Assembler::sthx( Register d, Register s1, Register s2) { emit_int32(STHX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 inline void Assembler::sth(  Register d, int si16,    Register s1) { emit_int32(STH_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
 inline void Assembler::sthu( Register d, int si16,    Register s1) { emit_int32(STHU_OPCODE | rs(d) | d1(si16)   | rta0mem(s1));}
+inline void Assembler::sthbrx( Register d, Register s1, Register s2) { emit_int32(STHBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 
 inline void Assembler::stbx( Register d, Register s1, Register s2) { emit_int32(STBX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 inline void Assembler::stb(  Register d, int si16,    Register s1) { emit_int32(STB_OPCODE  | rs(d) | d1(si16)   | ra0mem(s1));}
@@ -348,6 +351,7 @@
 inline void Assembler::stdx( Register d, Register s1, Register s2) { emit_int32(STDX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 inline void Assembler::stdu( Register d, int si16,    Register s1) { emit_int32(STDU_OPCODE | rs(d) | ds(si16)   | rta0mem(s1));}
 inline void Assembler::stdux(Register s, Register a,  Register b)  { emit_int32(STDUX_OPCODE| rs(s) | rta0mem(a) | rb(b));}
+inline void Assembler::stdbrx( Register d, Register s1, Register s2) { emit_int32(STDBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));}
 
 inline void Assembler::st_ptr(Register d, int b, Register s1) { std(d, b, s1); }
 DEBUG_ONLY(inline void Assembler::st_ptr(Register d, ByteSize b, Register s1) { std(d, in_bytes(b), s1); })
@@ -761,6 +765,11 @@
 inline void Assembler::mtvrd(  VectorRegister  d, Register a)               { emit_int32( MTVSRD_OPCODE  | vrt(d)  | ra(a)  | 1u); } // 1u: d is treated as Vector (VMX/Altivec).
 inline void Assembler::mfvrd(  Register        a, VectorRegister d)         { emit_int32( MFVSRD_OPCODE  | vrt(d)  | ra(a)  | 1u); } // 1u: d is treated as Vector (VMX/Altivec).
 
+// Vector-Scalar (VSX) instructions.
+inline void Assembler::mtfprd(  FloatRegister   d, Register a)      { emit_int32( MTVSRD_OPCODE  | frt(d)  | ra(a)); }
+inline void Assembler::mtfprwa( FloatRegister   d, Register a)      { emit_int32( MTVSRWA_OPCODE | frt(d)  | ra(a)); }
+inline void Assembler::mffprd(  Register        a, FloatRegister d) { emit_int32( MFVSRD_OPCODE  | frt(d)  | ra(a)); }
+
 inline void Assembler::vpkpx(   VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKPX_OPCODE   | vrt(d) | vra(a) | vrb(b)); }
 inline void Assembler::vpkshss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSHSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
 inline void Assembler::vpkswss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSWSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
@@ -944,14 +953,18 @@
 inline void Assembler::lbz(  Register d, int si16   ) { emit_int32( LBZ_OPCODE  | rt(d) | d1(si16));}
 inline void Assembler::ld(   Register d, int si16   ) { emit_int32( LD_OPCODE   | rt(d) | ds(si16));}
 inline void Assembler::ldx(  Register d, Register s2) { emit_int32( LDX_OPCODE  | rt(d) | rb(s2));}
+inline void Assembler::ldbrx(Register d, Register s2) { emit_int32( LDBRX_OPCODE| rt(d) | rb(s2));}
 inline void Assembler::stwx( Register d, Register s2) { emit_int32( STWX_OPCODE | rs(d) | rb(s2));}
 inline void Assembler::stw(  Register d, int si16   ) { emit_int32( STW_OPCODE  | rs(d) | d1(si16));}
+inline void Assembler::stwbrx(Register d, Register s2){ emit_int32(STWBRX_OPCODE| rs(d) | rb(s2));}
 inline void Assembler::sthx( Register d, Register s2) { emit_int32( STHX_OPCODE | rs(d) | rb(s2));}
 inline void Assembler::sth(  Register d, int si16   ) { emit_int32( STH_OPCODE  | rs(d) | d1(si16));}
+inline void Assembler::sthbrx(Register d, Register s2){ emit_int32(STHBRX_OPCODE| rs(d) | rb(s2));}
 inline void Assembler::stbx( Register d, Register s2) { emit_int32( STBX_OPCODE | rs(d) | rb(s2));}
 inline void Assembler::stb(  Register d, int si16   ) { emit_int32( STB_OPCODE  | rs(d) | d1(si16));}
 inline void Assembler::std(  Register d, int si16   ) { emit_int32( STD_OPCODE  | rs(d) | ds(si16));}
 inline void Assembler::stdx( Register d, Register s2) { emit_int32( STDX_OPCODE | rs(d) | rb(s2));}
+inline void Assembler::stdbrx(Register d, Register s2){ emit_int32(STDBRX_OPCODE| rs(d) | rb(s2));}
 
 // ra0 version
 inline void Assembler::icbi(    Register s2)          { emit_int32( ICBI_OPCODE   | rb(s2)           ); }
--- a/src/cpu/ppc/vm/bytes_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/bytes_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -37,10 +37,6 @@
 
 #if defined(VM_LITTLE_ENDIAN)
 
-  // Returns true, if the byte ordering used by Java is different from the native byte ordering
-  // of the underlying machine. For example, true for Intel x86, False, for Solaris on Sparc.
-  static inline bool is_Java_byte_ordering_different() { return true; }
-
   // Forward declarations of the compiler-dependent implementation
   static inline u2 swap_u2(u2 x);
   static inline u4 swap_u4(u4 x);
@@ -155,10 +151,6 @@
 
 #else // !defined(VM_LITTLE_ENDIAN)
 
-  // Returns true, if the byte ordering used by Java is different from the nativ byte ordering
-  // of the underlying machine. For example, true for Intel x86, False, for Solaris on Sparc.
-  static inline bool is_Java_byte_ordering_different() { return false; }
-
   // Thus, a swap between native and Java ordering is always a no-op:
   static inline u2   swap_u2(u2 x)  { return x; }
   static inline u4   swap_u4(u4 x)  { return x; }
--- a/src/cpu/ppc/vm/c1_LIRAssembler_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/c1_LIRAssembler_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -514,25 +514,48 @@
     }
     case Bytecodes::_i2d:
     case Bytecodes::_l2d: {
-      __ fcfid(dst->as_double_reg(), src->as_double_reg()); // via mem
+      bool src_in_memory = !VM_Version::has_mtfprd();
+      FloatRegister rdst = dst->as_double_reg();
+      FloatRegister rsrc;
+      if (src_in_memory) {
+        rsrc = src->as_double_reg(); // via mem
+      } else {
+        // move src to dst register
+        if (code == Bytecodes::_i2d) {
+          __ mtfprwa(rdst, src->as_register());
+        } else {
+          __ mtfprd(rdst, src->as_register_lo());
+        }
+        rsrc = rdst;
+      }
+      __ fcfid(rdst, rsrc);
       break;
     }
-    case Bytecodes::_i2f: {
+    case Bytecodes::_i2f:
+    case Bytecodes::_l2f: {
+      bool src_in_memory = !VM_Version::has_mtfprd();
       FloatRegister rdst = dst->as_float_reg();
-      FloatRegister rsrc = src->as_double_reg(); // via mem
+      FloatRegister rsrc;
+      if (src_in_memory) {
+        rsrc = src->as_double_reg(); // via mem
+      } else {
+        // move src to dst register
+        if (code == Bytecodes::_i2f) {
+          __ mtfprwa(rdst, src->as_register());
+        } else {
+          __ mtfprd(rdst, src->as_register_lo());
+        }
+        rsrc = rdst;
+      }
       if (VM_Version::has_fcfids()) {
         __ fcfids(rdst, rsrc);
       } else {
+        assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
         __ fcfid(rdst, rsrc);
         __ frsp(rdst, rdst);
       }
       break;
     }
-    case Bytecodes::_l2f: { // >= Power7
-      assert(VM_Version::has_fcfids(), "fcfid+frsp needs fixup code to avoid rounding incompatibility");
-      __ fcfids(dst->as_float_reg(), src->as_double_reg()); // via mem
-      break;
-    }
     case Bytecodes::_f2d: {
       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
       break;
@@ -543,31 +566,49 @@
     }
     case Bytecodes::_d2i:
     case Bytecodes::_f2i: {
+      bool dst_in_memory = !VM_Version::has_mtfprd();
       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
-      Address       addr = frame_map()->address_for_slot(dst->double_stack_ix());
+      Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
       Label L;
       // Result must be 0 if value is NaN; test by comparing value to itself.
       __ fcmpu(CCR0, rsrc, rsrc);
-      __ li(R0, 0); // 0 in case of NAN
-      __ std(R0, addr.disp(), addr.base());
+      if (dst_in_memory) {
+        __ li(R0, 0); // 0 in case of NAN
+        __ std(R0, addr.disp(), addr.base());
+      } else {
+        __ li(dst->as_register(), 0);
+      }
       __ bso(CCR0, L);
       __ fctiwz(rsrc, rsrc); // USE_KILL
-      __ stfd(rsrc, addr.disp(), addr.base());
+      if (dst_in_memory) {
+        __ stfd(rsrc, addr.disp(), addr.base());
+      } else {
+        __ mffprd(dst->as_register(), rsrc);
+      }
       __ bind(L);
       break;
     }
     case Bytecodes::_d2l:
     case Bytecodes::_f2l: {
+      bool dst_in_memory = !VM_Version::has_mtfprd();
       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
-      Address       addr = frame_map()->address_for_slot(dst->double_stack_ix());
+      Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
       Label L;
       // Result must be 0 if value is NaN; test by comparing value to itself.
       __ fcmpu(CCR0, rsrc, rsrc);
-      __ li(R0, 0); // 0 in case of NAN
-      __ std(R0, addr.disp(), addr.base());
+      if (dst_in_memory) {
+        __ li(R0, 0); // 0 in case of NAN
+        __ std(R0, addr.disp(), addr.base());
+      } else {
+        __ li(dst->as_register_lo(), 0);
+      }
       __ bso(CCR0, L);
       __ fctidz(rsrc, rsrc); // USE_KILL
-      __ stfd(rsrc, addr.disp(), addr.base());
+      if (dst_in_memory) {
+        __ stfd(rsrc, addr.disp(), addr.base());
+      } else {
+        __ mffprd(dst->as_register_lo(), rsrc);
+      }
       __ bind(L);
       break;
     }
--- a/src/cpu/ppc/vm/c1_LIRGenerator_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/c1_LIRGenerator_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -871,81 +871,91 @@
 // _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
 // _i2b, _i2c, _i2s
 void LIRGenerator::do_Convert(Convert* x) {
+  if (!VM_Version::has_mtfprd()) {
+    switch (x->op()) {
+
+      // int -> float: force spill
+      case Bytecodes::_l2f: {
+        if (!VM_Version::has_fcfids()) { // fcfids is >= Power7 only
+          // fcfid+frsp needs fixup code to avoid rounding incompatibility.
+          address entry = CAST_FROM_FN_PTR(address, SharedRuntime::l2f);
+          LIR_Opr result = call_runtime(x->value(), entry, x->type(), NULL);
+          set_result(x, result);
+          return;
+        } // else fallthru
+      }
+      case Bytecodes::_l2d: {
+        LIRItem value(x->value(), this);
+        LIR_Opr reg = rlock_result(x);
+        value.load_item();
+        LIR_Opr tmp = force_to_spill(value.result(), T_DOUBLE);
+        __ convert(x->op(), tmp, reg);
+        return;
+      }
+      case Bytecodes::_i2f:
+      case Bytecodes::_i2d: {
+        LIRItem value(x->value(), this);
+        LIR_Opr reg = rlock_result(x);
+        value.load_item();
+        // Convert i2l first.
+        LIR_Opr tmp1 = new_register(T_LONG);
+        __ convert(Bytecodes::_i2l, value.result(), tmp1);
+        LIR_Opr tmp2 = force_to_spill(tmp1, T_DOUBLE);
+        __ convert(x->op(), tmp2, reg);
+        return;
+      }
+
+      // float -> int: result will be stored
+      case Bytecodes::_f2l:
+      case Bytecodes::_d2l: {
+        LIRItem value(x->value(), this);
+        LIR_Opr reg = rlock_result(x);
+        value.set_destroys_register(); // USE_KILL
+        value.load_item();
+        set_vreg_flag(reg, must_start_in_memory);
+        __ convert(x->op(), value.result(), reg);
+        return;
+      }
+      case Bytecodes::_f2i:
+      case Bytecodes::_d2i: {
+        LIRItem value(x->value(), this);
+        LIR_Opr reg = rlock_result(x);
+        value.set_destroys_register(); // USE_KILL
+        value.load_item();
+        // Convert l2i afterwards.
+        LIR_Opr tmp1 = new_register(T_LONG);
+        set_vreg_flag(tmp1, must_start_in_memory);
+        __ convert(x->op(), value.result(), tmp1);
+        __ convert(Bytecodes::_l2i, tmp1, reg);
+        return;
+      }
+
+      // Within same category: just register conversions.
+      case Bytecodes::_i2b:
+      case Bytecodes::_i2c:
+      case Bytecodes::_i2s:
+      case Bytecodes::_i2l:
+      case Bytecodes::_l2i:
+      case Bytecodes::_f2d:
+      case Bytecodes::_d2f:
+        break;
+
+      default: ShouldNotReachHere();
+    }
+  }
+
+  // Register conversion.
+  LIRItem value(x->value(), this);
+  LIR_Opr reg = rlock_result(x);
+  value.load_item();
   switch (x->op()) {
-
-    // int -> float: force spill
-    case Bytecodes::_l2f: {
-      if (!VM_Version::has_fcfids()) { // fcfids is >= Power7 only
-        // fcfid+frsp needs fixup code to avoid rounding incompatibility.
-        address entry = CAST_FROM_FN_PTR(address, SharedRuntime::l2f);
-        LIR_Opr result = call_runtime(x->value(), entry, x->type(), NULL);
-        set_result(x, result);
-        break;
-      } // else fallthru
-    }
-    case Bytecodes::_l2d: {
-      LIRItem value(x->value(), this);
-      LIR_Opr reg = rlock_result(x);
-      value.load_item();
-      LIR_Opr tmp = force_to_spill(value.result(), T_DOUBLE);
-      __ convert(x->op(), tmp, reg);
-      break;
-    }
-    case Bytecodes::_i2f:
-    case Bytecodes::_i2d: {
-      LIRItem value(x->value(), this);
-      LIR_Opr reg = rlock_result(x);
-      value.load_item();
-      // Convert i2l first.
-      LIR_Opr tmp1 = new_register(T_LONG);
-      __ convert(Bytecodes::_i2l, value.result(), tmp1);
-      LIR_Opr tmp2 = force_to_spill(tmp1, T_DOUBLE);
-      __ convert(x->op(), tmp2, reg);
-      break;
-    }
-
-    // float -> int: result will be stored
     case Bytecodes::_f2l:
-    case Bytecodes::_d2l: {
-      LIRItem value(x->value(), this);
-      LIR_Opr reg = rlock_result(x);
-      value.set_destroys_register(); // USE_KILL
-      value.load_item();
-      set_vreg_flag(reg, must_start_in_memory);
-      __ convert(x->op(), value.result(), reg);
-      break;
-    }
+    case Bytecodes::_d2l:
     case Bytecodes::_f2i:
-    case Bytecodes::_d2i: {
-      LIRItem value(x->value(), this);
-      LIR_Opr reg = rlock_result(x);
-      value.set_destroys_register(); // USE_KILL
-      value.load_item();
-      // Convert l2i afterwards.
-      LIR_Opr tmp1 = new_register(T_LONG);
-      set_vreg_flag(tmp1, must_start_in_memory);
-      __ convert(x->op(), value.result(), tmp1);
-      __ convert(Bytecodes::_l2i, tmp1, reg);
-      break;
-    }
-
-    // Within same category: just register conversions.
-    case Bytecodes::_i2b:
-    case Bytecodes::_i2c:
-    case Bytecodes::_i2s:
-    case Bytecodes::_i2l:
-    case Bytecodes::_l2i:
-    case Bytecodes::_f2d:
-    case Bytecodes::_d2f: {
-      LIRItem value(x->value(), this);
-      LIR_Opr reg = rlock_result(x);
-      value.load_item();
-      __ convert(x->op(), value.result(), reg);
-      break;
-    }
-
-    default: ShouldNotReachHere();
+    case Bytecodes::_d2i: value.set_destroys_register(); break; // USE_KILL
+    default: break;
   }
+  __ convert(x->op(), value.result(), reg);
 }
 
 
--- a/src/cpu/ppc/vm/c1_MacroAssembler_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/c1_MacroAssembler_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -36,6 +36,7 @@
 #include "runtime/os.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "runtime/sharedRuntime.hpp"
+#include "utilities/align.hpp"
 
 
 void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) {
@@ -340,7 +341,7 @@
   // Check for negative or excessive length.
   size_t max_length = max_array_allocation_length >> log2_elt_size;
   if (UseTLAB) {
-    size_t max_tlab = align_size_up(ThreadLocalAllocBuffer::max_size() >> log2_elt_size, 64*K);
+    size_t max_tlab = align_up(ThreadLocalAllocBuffer::max_size() >> log2_elt_size, 64*K);
     if (max_tlab < max_length) { max_length = max_tlab; }
   }
   load_const_optimized(t1, max_length);
--- a/src/cpu/ppc/vm/c1_Runtime1_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/c1_Runtime1_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -36,6 +36,7 @@
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/signature.hpp"
 #include "runtime/vframeArray.hpp"
+#include "utilities/align.hpp"
 #include "utilities/macros.hpp"
 #include "vmreg_ppc.inline.hpp"
 #if INCLUDE_ALL_GCS
@@ -251,7 +252,7 @@
     fpu_reg_save_offsets[i] = sp_offset;
     sp_offset += BytesPerWord;
   }
-  frame_size_in_bytes = align_size_up(sp_offset, frame::alignment_in_bytes);
+  frame_size_in_bytes = align_up(sp_offset, frame::alignment_in_bytes);
 }
 
 
@@ -275,7 +276,7 @@
 static OopMapSet* generate_exception_throw_with_stack_parms(StubAssembler* sasm, address target,
                                                             int stack_parms) {
   // Make a frame and preserve the caller's caller-save registers.
-  const int parm_size_in_bytes = align_size_up(stack_parms << LogBytesPerWord, frame::alignment_in_bytes);
+  const int parm_size_in_bytes = align_up(stack_parms << LogBytesPerWord, frame::alignment_in_bytes);
   const int padding = parm_size_in_bytes - (stack_parms << LogBytesPerWord);
   OopMap* oop_map = save_live_registers(sasm, true, noreg, parm_size_in_bytes);
 
@@ -287,6 +288,7 @@
     __ ld(R5_ARG3, frame_size_in_bytes + padding + 8, R1_SP);
     case 1:
     __ ld(R4_ARG2, frame_size_in_bytes + padding + 0, R1_SP);
+    case 0:
     call_offset = __ call_RT(noreg, noreg, target);
     break;
     default: Unimplemented(); break;
@@ -325,7 +327,7 @@
 static OopMapSet* stub_call_with_stack_parms(StubAssembler* sasm, Register result, address target,
                                              int stack_parms, bool do_return = true) {
   // Make a frame and preserve the caller's caller-save registers.
-  const int parm_size_in_bytes = align_size_up(stack_parms << LogBytesPerWord, frame::alignment_in_bytes);
+  const int parm_size_in_bytes = align_up(stack_parms << LogBytesPerWord, frame::alignment_in_bytes);
   const int padding = parm_size_in_bytes - (stack_parms << LogBytesPerWord);
   OopMap* oop_map = save_live_registers(sasm, true, noreg, parm_size_in_bytes);
 
@@ -337,6 +339,7 @@
     __ ld(R5_ARG3, frame_size_in_bytes + padding + 8, R1_SP);
     case 1:
     __ ld(R4_ARG2, frame_size_in_bytes + padding + 0, R1_SP);
+    case 0:
     call_offset = __ call_RT(result, noreg, target);
     break;
     default: Unimplemented(); break;
--- a/src/cpu/ppc/vm/debug_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2013 SAP SE. All rights reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
- * or visit www.oracle.com if you need additional information or have any
- * questions.
- *
- */
-
-#include "precompiled.hpp"
-#include "code/codeCache.hpp"
-#include "code/nmethod.hpp"
-#include "runtime/frame.hpp"
-#include "runtime/init.hpp"
-#include "runtime/os.hpp"
-#include "utilities/debug.hpp"
-
-void pd_ps(frame f) {}
--- a/src/cpu/ppc/vm/frame_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/frame_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -244,4 +244,6 @@
 frame::frame(void* sp, void* fp, void* pc) : _sp((intptr_t*)sp), _unextended_sp((intptr_t*)sp) {
   find_codeblob_and_set_pc_and_deopt_state((address)pc); // also sets _fp and adjusts _unextended_sp
 }
+
+void frame::pd_ps() {}
 #endif
--- a/src/cpu/ppc/vm/frame_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/frame_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -82,13 +82,7 @@
  public:
 
   // C frame layout
-
-  enum {
-    // stack alignment
-    alignment_in_bytes = 16,
-    // log_2(16*8 bits) = 7.
-    log_2_of_alignment_in_bits = 7
-  };
+  static const int alignment_in_bytes = 16;
 
   // ABI_MINFRAME:
   struct abi_minframe {
--- a/src/cpu/ppc/vm/frame_ppc.inline.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/frame_ppc.inline.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -28,6 +28,7 @@
 
 #include "code/codeCache.hpp"
 #include "code/vmreg.inline.hpp"
+#include "utilities/align.hpp"
 
 // Inline functions for ppc64 frames:
 
@@ -193,7 +194,7 @@
 
 inline int frame::interpreter_frame_monitor_size() {
   // Number of stack slots for a monitor.
-  return round_to(BasicObjectLock::size(),  // number of stack slots
+  return align_up(BasicObjectLock::size(),  // number of stack slots
                   WordsPerLong);            // number of stack slots for a Java long
 }
 
--- a/src/cpu/ppc/vm/globals_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/globals_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
+ * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -167,7 +167,7 @@
   product(bool, ZapMemory, false, "Write 0x0101... to empty memory."        \
           " Use this to ease debugging.")                                   \
                                                                             \
-  /* Use Restricted Transactional Memory for lock eliding */                \
+  /* Use Restricted Transactional Memory for lock elision */                \
   product(bool, UseRTMLocking, false,                                       \
           "Enable RTM lock eliding for inflated locks in compiled code")    \
                                                                             \
@@ -177,24 +177,31 @@
   product(bool, UseRTMDeopt, false,                                         \
           "Perform deopt and recompilation based on RTM abort ratio")       \
                                                                             \
-  product(uintx, RTMRetryCount, 5,                                          \
+  product(int, RTMRetryCount, 5,                                            \
           "Number of RTM retries on lock abort or busy")                    \
+          range(0, max_jint)                                                \
                                                                             \
-  experimental(intx, RTMSpinLoopCount, 100,                                 \
+  experimental(int, RTMSpinLoopCount, 100,                                  \
           "Spin count for lock to become free before RTM retry")            \
+          range(0, 32767) /* immediate operand limit on ppc */              \
                                                                             \
-  experimental(intx, RTMAbortThreshold, 1000,                               \
+  experimental(int, RTMAbortThreshold, 1000,                                \
           "Calculate abort ratio after this number of aborts")              \
+          range(0, max_jint)                                                \
                                                                             \
-  experimental(intx, RTMLockingThreshold, 10000,                            \
+  experimental(int, RTMLockingThreshold, 10000,                             \
           "Lock count at which to do RTM lock eliding without "             \
           "abort ratio calculation")                                        \
+          range(0, max_jint)                                                \
                                                                             \
-  experimental(intx, RTMAbortRatio, 50,                                     \
+  experimental(int, RTMAbortRatio, 50,                                      \
           "Lock abort ratio at which to stop use RTM lock eliding")         \
+          range(0, 100) /* natural range */                                 \
                                                                             \
-  experimental(intx, RTMTotalCountIncrRate, 64,                             \
+  experimental(int, RTMTotalCountIncrRate, 64,                              \
           "Increment total RTM attempted lock count once every n times")    \
+          range(1, 32767) /* immediate operand limit on ppc */              \
+          constraint(RTMTotalCountIncrRateConstraintFunc,AfterErgo)         \
                                                                             \
   experimental(intx, RTMLockingCalculationDelay, 0,                         \
           "Number of milliseconds to wait before start calculating aborts " \
--- a/src/cpu/ppc/vm/interp_masm_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/interp_masm_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -99,8 +99,8 @@
 
   void push_2ptrs(Register first, Register second);
 
-  void push_l_pop_d(Register l = R17_tos, FloatRegister d = F15_ftos);
-  void push_d_pop_l(FloatRegister d = F15_ftos, Register l = R17_tos);
+  void move_l_to_d(Register l = R17_tos, FloatRegister d = F15_ftos);
+  void move_d_to_l(FloatRegister d = F15_ftos, Register l = R17_tos);
 
   void pop (TosState state);           // transition vtos -> state
   void push(TosState state);           // transition state -> vtos
--- a/src/cpu/ppc/vm/interp_masm_ppc_64.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/interp_masm_ppc_64.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -284,14 +284,22 @@
   addi(R15_esp, R15_esp, - 2 * Interpreter::stackElementSize );
 }
 
-void InterpreterMacroAssembler::push_l_pop_d(Register l, FloatRegister d) {
-  std(l, 0, R15_esp);
-  lfd(d, 0, R15_esp);
+void InterpreterMacroAssembler::move_l_to_d(Register l, FloatRegister d) {
+  if (VM_Version::has_mtfprd()) {
+    mtfprd(d, l);
+  } else {
+    std(l, 0, R15_esp);
+    lfd(d, 0, R15_esp);
+  }
 }
 
-void InterpreterMacroAssembler::push_d_pop_l(FloatRegister d, Register l) {
-  stfd(d, 0, R15_esp);
-  ld(l, 0, R15_esp);
+void InterpreterMacroAssembler::move_d_to_l(FloatRegister d, Register l) {
+  if (VM_Version::has_mtfprd()) {
+    mffprd(l, d);
+  } else {
+    stfd(d, 0, R15_esp);
+    ld(l, 0, R15_esp);
+  }
 }
 
 void InterpreterMacroAssembler::push(TosState state) {
--- a/src/cpu/ppc/vm/interpreterRT_ppc.hpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/interpreterRT_ppc.hpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -45,7 +45,7 @@
 
  public:
   // Creation
-  SignatureHandlerGenerator(methodHandle method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
+  SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) {
     _masm = new MacroAssembler(buffer);
     _num_used_fp_arg_regs = 0;
   }
--- a/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/macroAssembler_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -2498,14 +2498,20 @@
   //   All transactions = total_count *  RTMTotalCountIncrRate
   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
   ld(R0, RTMLockingCounters::abort_count_offset(), rtm_counters_Reg);
-  cmpdi(CCR0, R0, RTMAbortThreshold);
-  blt(CCR0, L_check_always_rtm2);
+  if (is_simm(RTMAbortThreshold, 16)) {   // cmpdi can handle 16bit immediate only.
+    cmpdi(CCR0, R0, RTMAbortThreshold);
+    blt(CCR0, L_check_always_rtm2);  // reload of rtm_counters_Reg not necessary
+  } else {
+    load_const_optimized(rtm_counters_Reg, RTMAbortThreshold);
+    cmpd(CCR0, R0, rtm_counters_Reg);
+    blt(CCR0, L_check_always_rtm1);  // reload of rtm_counters_Reg required
+  }
   mulli(R0, R0, 100);
 
   const Register tmpReg = rtm_counters_Reg;
   ld(tmpReg, RTMLockingCounters::total_count_offset(), rtm_counters_Reg);
-  mulli(tmpReg, tmpReg, RTMTotalCountIncrRate);
-  mulli(tmpReg, tmpReg, RTMAbortRatio);
+  mulli(tmpReg, tmpReg, RTMTotalCountIncrRate); // allowable range: int16
+  mulli(tmpReg, tmpReg, RTMAbortRatio);         // allowable range: int16
   cmpd(CCR0, R0, tmpReg);
   blt(CCR0, L_check_always_rtm1); // jump to reload
   if (method_data != NULL) {
@@ -2521,7 +2527,13 @@
   load_const_optimized(rtm_counters_Reg, (address)rtm_counters, R0); // reload
   bind(L_check_always_rtm2);
   ld(tmpReg, RTMLockingCounters::total_count_offset(), rtm_counters_Reg);
-  cmpdi(CCR0, tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
+  int64_t thresholdValue = RTMLockingThreshold / RTMTotalCountIncrRate;
+  if (is_simm(thresholdValue, 16)) {   // cmpdi can handle 16bit immediate only.
+    cmpdi(CCR0, tmpReg, thresholdValue);
+  } else {
+    load_const_optimized(R0, thresholdValue);
+    cmpd(CCR0, tmpReg, R0);
+  }
   blt(CCR0, L_done);
   if (method_data != NULL) {
     // Set rtm_state to "always rtm" in MDO.
@@ -2620,7 +2632,7 @@
   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
     Label L_noincrement;
     if (RTMTotalCountIncrRate > 1) {
-      branch_on_random_using_tb(tmp, (int)RTMTotalCountIncrRate, L_noincrement);
+      branch_on_random_using_tb(tmp, RTMTotalCountIncrRate, L_noincrement);
     }
     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
     load_const_optimized(tmp, (address)stack_rtm_counters->total_count_addr(), R0);
@@ -2687,7 +2699,7 @@
   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
     Label L_noincrement;
     if (RTMTotalCountIncrRate > 1) {
-      branch_on_random_using_tb(R0, (int)RTMTotalCountIncrRate, L_noincrement);
+      branch_on_random_using_tb(R0, RTMTotalCountIncrRate, L_noincrement);
     }
     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
     load_const(R0, (address)rtm_counters->total_count_addr(), tmpReg);
--- a/src/cpu/ppc/vm/methodHandles_ppc.cpp	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/methodHandles_ppc.cpp	Thu Aug 10 09:23:41 2017 +0200
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
+ * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -29,6 +29,7 @@
 #include "interpreter/interpreter.hpp"
 #include "memory/allocation.inline.hpp"
 #include "memory/resourceArea.hpp"
+#include "prims/jvm.h"
 #include "prims/methodHandles.hpp"
 
 #define __ _masm->
@@ -174,8 +175,9 @@
   __ verify_oop(method_temp);
   __ load_heap_oop_not_null(method_temp, NONZERO(java_lang_invoke_LambdaForm::vmentry_offset_in_bytes()), method_temp, temp2);
   __ verify_oop(method_temp);
-  // The following assumes that a Method* is normally compressed in the vmtarget field:
-  __ ld(method_temp, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()), method_temp);
+  __ load_heap_oop_not_null(method_temp, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes()), method_temp);
+  __ verify_oop(method_temp);
+  __ ld(method_temp, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes()), method_temp);
 
   if (VerifyMethodHandles && !for_compiler_entry) {
     // Make sure recv is already on stack.
@@ -361,14 +363,16 @@
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeSpecial, member_reg, temp2);
       }
-      __ ld(R19_method, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()), member_reg);
+      __ load_heap_oop(R19_method, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes()), member_reg);
+      __ ld(R19_method, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes()), R19_method);
       break;
 
     case vmIntrinsics::_linkToStatic:
       if (VerifyMethodHandles) {
         verify_ref_kind(_masm, JVM_REF_invokeStatic, member_reg, temp2);
       }
-      __ ld(R19_method, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()), member_reg);
+      __ load_heap_oop(R19_method, NONZERO(java_lang_invoke_MemberName::method_offset_in_bytes()), member_reg);
+      __ ld(R19_method, NONZERO(java_lang_invoke_ResolvedMethodName::vmtarget_offset_in_bytes()), R19_method);
       break;
 
     case vmIntrinsics::_linkToVirtual:
--- a/src/cpu/ppc/vm/ppc.ad	Wed Aug 09 16:00:52 2017 -0400
+++ b/src/cpu/ppc/vm/ppc.ad	Thu Aug 10 09:23:41 2017 +0200
@@ -1,6 +1,6 @@
 //
 // Copyright (c) 2011, 2017, Oracle and/or its affiliates. All rights reserved.
-// Copyright (c) 2012, 2016 SAP SE. All rights reserved.
+// Copyright (c) 2012, 2017 SAP SE. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -3079,6 +3079,17 @@
     __ bind(done);
   %}
 
+  enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
+    // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
+
+    MacroAssembler _masm(&cbuf);
+    Label done;
+    __ bso($crx$$CondRegister, done);
+    __ mffprd($dst$$Register, $src$$FloatRegister);
+    // TODO PPC port __ endgroup_if_needed(_size == 12);
+    __ bind(done);
+  %}
+
   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
 
@@ -5842,6 +5853,16 @@
   ins_pipe(pipe_class_default);
 %}
 
+instruct rldicl(iRegLdst dst, iRegLsrc src, immI16 shift, immI16 mask_begin) %{
+  effect(DEF dst, USE src, USE shift, USE mask_begin);
+
+  size(4);
+  ins_encode %{
+    __ rldicl($dst$$Register, $src$$Register, $shift$$constant, $mask_begin$$constant);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // Needed to postalloc expand loadConN: ConN is loaded as ConI
 // leaving the upper 32 bits with sign-extension bits.
 // This clears these bits: dst = src & 0xFFFFFFFF.
@@ -9306,6 +9327,44 @@
   ins_pipe(pipe_class_default);
 %}
 
+// Bitfield Extract: URShiftI + AndI
+instruct andI_urShiftI_regI_immI_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immI src2, immIpow2minus1 src3) %{
+  match(Set dst (AndI (URShiftI src1 src2) src3));
+
+  format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// int bitfield extract" %}
+  size(4);
+  ins_encode %{
+    // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
+    int rshift = ($src2$$constant) & 0x1f;
+    int length = log2_long(((jlong) $src3$$constant) + 1);
+    if (rshift + length > 32) {
+      // if necessary, adjust mask to omit rotated bits.
+      length = 32 - rshift;
+    }
+    __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
+// Bitfield Extract: URShiftL + AndL
+instruct andL_urShiftL_regL_immI_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immI src2, immLpow2minus1 src3) %{
+  match(Set dst (AndL (URShiftL src1 src2) src3));
+
+  format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// long bitfield extract" %}
+  size(4);
+  ins_encode %{
+    // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
+    int rshift  = ($src2$$constant) & 0x3f;
+    int length = log2_long(((jlong) $src3$$constant) + 1);
+    if (rshift + length > 64) {
+      // if necessary, adjust mask to omit rotated bits.
+      length = 64 - rshift;
+    }
+    __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
   match(Set dst (ConvL2I (ConvI2L src)));
 
@@ -10078,9 +10137,36 @@
 //   float intBitsToFloat(int bits)
 //
 // Notes on the implementation on ppc64:
-// We only provide rules which move between a register and a stack-location,
-// because we always have to go through memory when moving between a float
-// register and an integer register.
+// For Power7 and earlier, the rules are limited to those which move between a
+// register and a stack-location, because we always have to go through memory
+// when moving between a float register and an integer register.
+// This restriction is removed in Power8 with the introduction of the mtfprd
+// and mffprd instructions.
+
+instruct moveL2D_reg(regD dst, iRegLsrc src) %{
+  match(Set dst (MoveL2D src));
+  predicate(VM_Version::has_mtfprd());
+
+  format %{ "MTFPRD  $dst, $src" %}
+  size(4);
+  ins_encode %{
+    __ mtfprd($dst$$FloatRegister, $src$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
+instruct moveI2D_reg(regD dst, iRegIsrc src) %{
+  // no match-rule, false predicate
+  effect(DEF dst, USE src);
+  predicate(false);
+
+  format %{ "MTFPRWA $dst, $src" %}
+  size(4);
+  ins_encode %{
+    __ mtfprwa($dst$$FloatRegister, $src$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
 
 //---------- Chain stack slots between similar types --------
 
@@ -10519,6 +10605,16 @@
   ins_pipe(pipe_class_default);
 %}
 
+instruct extsh(iRegIdst dst, iRegIsrc src) %{
+  effect(DEF dst, USE src);
+
+  size(4);
+  ins_encode %{
+    __ extsh($dst$$Register, $src$$Register);
+  %}
+  ins_pipe(pipe_class_default);
+%}
+
 // LShiftI 16 + RShiftI 16 converts short to int.
 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
   match(Set dst (RShiftI (LShiftI src amount) amount));
@@ -10583,6 +10679,20 @@
   ins_pipe(pipe_class_default);
 %}
 
+instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
+  // no match-rule, false predicate
+  effect(DEF dst, USE crx, USE src);
+  predicate(false);
+
+  ins_variable_size_depending_on_alignment(true);
+
+  format %{ "cmovI   $crx, $dst, $src" %}
+  // Worst case is branch + move + stop, no stop without scheduler.
+  size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
+  ins_encode( enc_cmove_bso_reg(dst, crx, src) );
+  ins_pipe(pipe_class_default);
+%}
+
 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
   // no match-rule, false predicate
   effect(DEF dst, USE crx, USE mem);
@@ -10637,9 +10747,64 @@
   %}
 %}
 
+instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
+  // no match-rule, false predicate
+  effect(DEF dst, USE crx, USE src);
+  predicate(false);
+
+  format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
+  postalloc_expand %{
+    //
+    // replaces
+    //
+    //   region  dst  crx  src
+    //    \       |    |   /
+    //     dst=cmovI_bso_reg_conLvalue0
+    //
+    // with
+    //
+    //   region  dst
+    //    \       /
+    //     dst=loadConI16(0)
+    //      |
+    //      ^  region  dst  crx  src
+    //      |   \       |    |    /
+    //      dst=cmovI_bso_reg
+    //
+
+    // Create new nodes.
+    MachNode *m1 = new loadConI16Node();
+    MachNode *m2 = new cmovI_bso_regNode();
+
+    // inputs for new nodes
+    m1->add_req(n_region);
+    m2->add_req(n_region, n_crx, n_src);
+
+    // precedences for new nodes
+    m2->add_prec(m1);
+
+    // operands for new nodes
+    m1->_opnds[0] = op_dst;
+    m1->_opnds[1] = new immI16Oper(0);
+
+    m2->_opnds[0] = op_dst;
+    m2->_opnds[1] = op_crx;
+    m2->_opnds[2] = op_src;
+
+    // registers for new nodes
+    ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
+    ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
+
+    // Insert new nodes.
+    nodes->push(m1);
+    nodes->push(m2);
+  %}
+%}
+
 // Double to Int conversion, NaN is mapped to 0.
 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
   match(Set dst (ConvD2I src));
+  predicate(!VM_Version::has_mtfprd());
   ins_cost(DEFAULT_COST);
 
   expand %{
@@ -10653,6 +10818,21 @@
   %}
 %}
 
+// Double to Int conversion, NaN is mapped to 0. Special version for Power8.
+instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
+  match(Set dst (ConvD2I src));
+  predicate(VM_Version::has_mtfprd());
+  ins_cost(DEFAULT_COST);
+
+  expand %{
+    regD tmpD;
+    flagsReg crx;
+    cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
+    convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
+    cmovI_bso_