changeset 13383:bef84e964115

8158361: AArch64: Address calculation missed optimizations Summary: This issue is fixed by adding "addExtI_shift" pattern rule. Other similar rules are also added. Reviewed-by: aph, adinn Contributed-by: zhongwei.yao@linaro.org
author njian
date Fri, 23 Jun 2017 11:41:24 +0800
parents 7ae3e5da7a49
children 23e687f0c874
files src/cpu/aarch64/vm/aarch64.ad src/cpu/aarch64/vm/aarch64_ad.m4
diffstat 2 files changed, 391 insertions(+), 15 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch64/vm/aarch64.ad	Tue Jul 25 09:32:50 2017 -0700
+++ b/src/cpu/aarch64/vm/aarch64.ad	Fri Jun 23 11:41:24 2017 +0800
@@ -5343,6 +5343,17 @@
   interface(CONST_INTER);
 %}
 
+// Shift values for add/sub extension shift
+operand immIExt()
+%{
+  predicate(0 <= n->get_int() && (n->get_int() <= 4));
+  match(ConI);
+
+  op_cost(0);
+  format %{ %}
+  interface(CONST_INTER);
+%}
+
 operand immI_le_4()
 %{
   predicate(n->get_int() <= 4);
@@ -12789,7 +12800,7 @@
 %{
   match(Set dst (AddL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtw $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12802,7 +12813,7 @@
 %{
   match(Set dst (SubL src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "sub  $dst, $src1, sxtw $src2" %}
+  format %{ "sub  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12816,7 +12827,7 @@
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxth $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxth" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12829,7 +12840,7 @@
 %{
   match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12842,7 +12853,7 @@
 %{
   match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, uxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, uxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12855,7 +12866,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxth $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxth" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12868,7 +12879,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtw $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtw" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12881,7 +12892,7 @@
 %{
   match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, sxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, sxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -12894,7 +12905,7 @@
 %{
   match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
   ins_cost(INSN_COST);
-  format %{ "add  $dst, $src1, uxtb $src2" %}
+  format %{ "add  $dst, $src1, $src2, uxtb" %}
 
    ins_encode %{
      __ add(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -13034,6 +13045,294 @@
   ins_pipe(ialu_reg_reg);
 %}
 
+
+instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtw #lshift2" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtw #lshift2" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, sxtb #lshift2" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, sxth #lshift2" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+
+instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, sxtw #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%};
+
+instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, sxtw #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%};
+
+
+instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "add  $dst, $src1, $src2, uxtw #lshift" %}
+
+   ins_encode %{
+     __ add(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "sub  $dst, $src1, $src2, uxtw #lshift" %}
+
+   ins_encode %{
+     __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "addw  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, uxtb #lshift" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
+
+instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "subw  $dst, $src1, $src2, uxth #lshift" %}
+
+   ins_encode %{
+     __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}
 // END This section of the file is automatically generated. Do not edit --------------
 
 // ============================================================================
--- a/src/cpu/aarch64/vm/aarch64_ad.m4	Tue Jul 25 09:32:50 2017 -0700
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4	Fri Jun 23 11:41:24 2017 +0800
@@ -268,21 +268,21 @@
   ins_pipe(ialu_reg_reg_vshift);
 %}')dnl
 define(ROL_INSN, `
-instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
 %{
   match(Set dst (Or$1 (LShift$1 src shift) (URShift$1 src (SubI c$2 shift))));
 
   expand %{
-    $3L_rReg(dst, src, shift, cr);
+    $3$1_rReg(dst, src, shift, cr);
   %}
 %}')dnl
 define(ROR_INSN, `
-instruct $3$1_rReg_Var_C$2(iRegLNoSp dst, iRegL src, iRegI shift, immI$2 c$2, rFlagsReg cr)
+instruct $3$1_rReg_Var_C$2(iReg$1NoSp dst, iReg$1 src, iRegI shift, immI$2 c$2, rFlagsReg cr)
 %{
   match(Set dst (Or$1 (URShift$1 src shift) (LShift$1 src (SubI c$2 shift))));
 
   expand %{
-    $3L_rReg(dst, src, shift, cr);
+    $3$1_rReg(dst, src, shift, cr);
   %}
 %}')dnl
 ROL_EXPAND(L, rol, rorv)
@@ -305,7 +305,7 @@
 %{
   match(Set dst ($3$2 src1 (ConvI2L src2)));
   ins_cost(INSN_COST);
-  format %{ "$4  $dst, $src1, $5 $src2" %}
+  format %{ "$4  $dst, $src1, $src2, $5" %}
 
    ins_encode %{
      __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -321,7 +321,7 @@
 %{
   match(Set dst ($3$1 src1 EXTEND($1, $4, src2, lshift, rshift)));
   ins_cost(INSN_COST);
-  format %{ "$5  $dst, $src1, $6 $src2" %}
+  format %{ "$5  $dst, $src1, $src2, $6" %}
 
    ins_encode %{
      __ $5(as_Register($dst$$reg), as_Register($src1$$reg),
@@ -363,5 +363,82 @@
 ADD_SUB_ZERO_EXTEND(L,255,Sub,sub,uxtb)
 ADD_SUB_ZERO_EXTEND(L,65535,Sub,sub,uxth)
 ADD_SUB_ZERO_EXTEND(L,4294967295,Sub,sub,uxtw)
+dnl
+dnl ADD_SUB_ZERO_EXTEND_SHIFT(mode, size, add node, insn, ext type)
+define(`ADD_SUB_EXTENDED_SHIFT', `
+instruct $3Ext$1_$6_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, immIExt lshift2, immI_`'eval($7-$2) lshift1, immI_`'eval($7-$2) rshift1, rFlagsReg cr)
+%{
+  match(Set dst ($3$1 src1 (LShift$1 EXTEND($1, $4, src2, lshift1, rshift1) lshift2)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$5  $dst, $src1, $src2, $6 #lshift2" %}
 
+   ins_encode %{
+     __ $5(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$6, ($lshift2$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl                   $1 $2 $3   $4   $5   $6  $7
+ADD_SUB_EXTENDED_SHIFT(L,8,Add,RShift,add,sxtb,64)
+ADD_SUB_EXTENDED_SHIFT(L,16,Add,RShift,add,sxth,64)
+ADD_SUB_EXTENDED_SHIFT(L,32,Add,RShift,add,sxtw,64)
+dnl
+ADD_SUB_EXTENDED_SHIFT(L,8,Sub,RShift,sub,sxtb,64)
+ADD_SUB_EXTENDED_SHIFT(L,16,Sub,RShift,sub,sxth,64)
+ADD_SUB_EXTENDED_SHIFT(L,32,Sub,RShift,sub,sxtw,64)
+dnl
+ADD_SUB_EXTENDED_SHIFT(I,8,Add,RShift,addw,sxtb,32)
+ADD_SUB_EXTENDED_SHIFT(I,16,Add,RShift,addw,sxth,32)
+dnl
+ADD_SUB_EXTENDED_SHIFT(I,8,Sub,RShift,subw,sxtb,32)
+ADD_SUB_EXTENDED_SHIFT(I,16,Sub,RShift,subw,sxth,32)
+dnl
+dnl ADD_SUB_CONV_SHIFT(mode, add node, insn, ext type)
+define(`ADD_SUB_CONV_SHIFT', `
+instruct $2ExtI_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst ($2$1 src1 (LShiftL (ConvI2L src2) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$3  $dst, $src1, $src2, $4 #lshift" %}
+
+   ins_encode %{
+     __ $3(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$4, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl
+ADD_SUB_CONV_SHIFT(L,Add,add,sxtw);
+ADD_SUB_CONV_SHIFT(L,Sub,sub,sxtw);
+dnl
+dnl ADD_SUB_ZERO_EXTEND(mode, size, add node, insn, ext type)
+define(`ADD_SUB_ZERO_EXTEND_SHIFT', `
+instruct $3Ext$1_$5_and_shift(iReg$1NoSp dst, iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2, imm$1_$2 mask, immIExt lshift, rFlagsReg cr)
+%{
+  match(Set dst ($3$1 src1 (LShift$1 (And$1 src2 mask) lshift)));
+  ins_cost(1.9 * INSN_COST);
+  format %{ "$4  $dst, $src1, $src2, $5 #lshift" %}
+
+   ins_encode %{
+     __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
+            as_Register($src2$$reg), ext::$5, ($lshift$$constant));
+   %}
+  ins_pipe(ialu_reg_reg_shift);
+%}')
+dnl
+dnl                       $1 $2  $3  $4  $5
+ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Add,add,uxtw)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Sub,sub,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Sub,sub,uxth)
+ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Sub,sub,uxtw)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Add,addw,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Add,addw,uxth)
+dnl
+ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
+ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
+dnl
 // END This section of the file is automatically generated. Do not edit --------------