diff src/cpu/sparc/vm/vm_version_sparc.hpp @ 7301:f79d8e8caecb

8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect Summary: Chcek both l2-dcache-line-size and l2-cache-line-size properties to determine the size of the line Reviewed-by: kvn
author iveresov
date Fri, 10 Apr 2015 15:27:05 -0700
parents d635fd1ac81c
children d2dd79a4fd69
line wrap: on
line diff
--- a/src/cpu/sparc/vm/vm_version_sparc.hpp	Fri Apr 10 15:24:50 2015 -0700
+++ b/src/cpu/sparc/vm/vm_version_sparc.hpp	Fri Apr 10 15:27:05 2015 -0700
@@ -96,8 +96,8 @@
   static int  _features;
   static const char* _features_str;
 
-  static unsigned int _L2_cache_line_size;
-  static unsigned int L2_cache_line_size() { return _L2_cache_line_size; }
+  static unsigned int _L2_data_cache_line_size;
+  static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; }
 
   static void print_features();
   static int  determine_features();
@@ -171,7 +171,7 @@
   static const char* cpu_features()     { return _features_str; }
 
   // default prefetch block size on sparc
-  static intx prefetch_data_size()      { return L2_cache_line_size();  }
+  static intx prefetch_data_size()      { return L2_data_cache_line_size();  }
 
   // Prefetch
   static intx prefetch_copy_interval_in_bytes() {