changeset 8223:40cc86629062

8175234: aarch32: Delete incorrect NativeTrampolineCall::instruction_size Reviewed-by: enevill Contributed-by: akozlov@azul.com
author enevill
date Sun, 19 Feb 2017 20:14:42 +0000
parents 619ce4fed27a
children f1ee83181bfc
files src/cpu/aarch32/vm/macroAssembler_aarch32.cpp src/cpu/aarch32/vm/nativeInst_aarch32.cpp src/cpu/aarch32/vm/nativeInst_aarch32.hpp
diffstat 3 files changed, 7 insertions(+), 7 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch32/vm/macroAssembler_aarch32.cpp	Fri Feb 10 19:01:30 2017 +0300
+++ b/src/cpu/aarch32/vm/macroAssembler_aarch32.cpp	Sun Feb 19 20:14:42 2017 +0000
@@ -625,12 +625,15 @@
     // Have make trampline such way: destination address should be raw 4 byte value,
     // so it's patching could be done atomically.
     relocate(entry.rspec());
+    address start = pc();
     add(lr, r15_pc, NativeCall::instruction_size - 2 * NativeInstruction::arm_insn_sz);
     ldr(r15_pc, Address(r15_pc, 4));
     emit_int32((uintptr_t) entry.target());
     // possibly pad the call to the NativeCall size to make patching happy
-    for (int i = NativeCall::instruction_size; i > 3 * NativeInstruction::arm_insn_sz; i -= NativeInstruction::arm_insn_sz)
+    while (pc() - start < NativeCall::instruction_size) {
       nop();
+    }
+    assert(pc() - start == NativeCall::instruction_size, "fix NativeTrampolineCall::instruction_size!");
   } else {
     bl(entry);
   }
--- a/src/cpu/aarch32/vm/nativeInst_aarch32.cpp	Fri Feb 10 19:01:30 2017 +0300
+++ b/src/cpu/aarch32/vm/nativeInst_aarch32.cpp	Sun Feb 19 20:14:42 2017 +0000
@@ -176,7 +176,7 @@
 }
 
 bool NativeTrampolineCall::is_at(address addr) {
-  return (as_uint(addr    ) & ~0xffu) == 0xe28fe000  // add     lr, pc, #disp
+  return (as_uint(addr    ) & ~0xffu) == 0xe28fe000 // add     lr, pc, #disp
        && as_uint(addr + 4)          == 0xe51ff004; // ldr     pc, [pc, -4]
 }
 
--- a/src/cpu/aarch32/vm/nativeInst_aarch32.hpp	Fri Feb 10 19:01:30 2017 +0300
+++ b/src/cpu/aarch32/vm/nativeInst_aarch32.hpp	Sun Feb 19 20:14:42 2017 +0000
@@ -231,11 +231,9 @@
   return NativeMovConstReg::from(address);
 }
 
-class NativeTrampolineCall: public NativeBranchType {
+class NativeTrampolineCall: public NativeInstruction {
  public:
-  enum {
-    instruction_size = 3 * arm_insn_sz
-  };
+  // NativeTrampolineCall size is always equal to NativeCall::instruction_size
   address destination() const;
   void set_destination(address dest);
   void set_destination_mt_safe(address dest, bool assert_lock = true);
@@ -272,7 +270,6 @@
 
   static int instruction_size;
 #ifdef ASSERT
-  StaticAssert<(int) NativeTrampolineCall::instruction_size <= (int) max_instruction_size> dummy1;
   StaticAssert<NativeMovConstReg::movw_movt_pair_sz
       + NativeRegCall::instruction_size <= (int) max_instruction_size> dummy2;
   StaticAssert<NativeMovConstReg::mov_n_three_orr_sz