changeset 7854:4f80e59624fe

8156945: aarch32: add verification of Use*Intrinsics cmdline parameters Reviewed-by: enevill Contributed-by: alexey@azul.com
author enevill
date Fri, 13 May 2016 14:43:43 +0100
parents 21a14f1d4cdc
children bfc264a44947
files src/cpu/aarch32/vm/vm_version_aarch32.cpp
diffstat 1 files changed, 27 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/src/cpu/aarch32/vm/vm_version_aarch32.cpp	Fri May 13 14:33:06 2016 +0100
+++ b/src/cpu/aarch32/vm/vm_version_aarch32.cpp	Fri May 13 14:43:43 2016 +0100
@@ -204,6 +204,33 @@
   fprintf(stderr, "Unable to use memory barriers as not on ARMv7, disabling.\n");
   UseMembar = false;
   }*/
+
+  if (UseCRC32Intrinsics) {
+    if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
+      warning("CRC32 Intrinsics are not implemented on this CPU");
+    FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
+  }
+
+  if (UseAES) {
+    warning("AES instructions are not implemented on this CPU");
+    FLAG_SET_DEFAULT(UseAES, false);
+  }
+  if (UseAESIntrinsics) {
+    warning("AES intrinsics are not implemented on this CPU");
+    FLAG_SET_DEFAULT(UseAESIntrinsics, false);
+  }
+
+  if (UseSHA) {
+    warning("SHA instructions are not available on this CPU");
+    FLAG_SET_DEFAULT(UseSHA, false);
+  }
+  if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
+    warning("SHA intrinsics are not available on this CPU");
+    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
+    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
+    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
+  }
+
 }
 
 void VM_Version::initialize() {